DAC8043FSZ [ADI]
12-Bit Serial Input Multiplying CMOS Digital-to-Analog Converter; 12位串行输入乘法CMOS数位类比转换器
| 型号： | DAC8043FSZ |
| 厂家： | 
ADI |
| 描述： | 12-Bit Serial Input Multiplying CMOS Digital-to-Analog Converter |
| 文件： | 总16页 (文件大小：316K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
12-Bit Serial Input Multiplying CMOS
Digital-to-Analog Converter
DAC8043
FEATURES
FUNCTIONAL BLOCK DIAGRAM
12-bit accuracy in an 8-lead PDIP and SOIC package
Fast serial data input
Double data buffers
Low ½ LSB maximum INL and 1 LSB maximum DNL
Maximum gain error: 2 LSB
Low 5 ppm/°C maximum tempco
ESD resistant
DAC8043
R
FB
R
I
FB
V
12-BIT DAC
12
REF
OUT
12-BIT
DAC REGISTER
LD
Low cost
Available in die form
12
V
DD
CLK
SRI
12-BIT
SHIFT REGISTER
GND
APPLICATIONS
Autocalibration systems
Process control and industrial automation
Programmable amplifiers and attenuators
Digitally controlled filters
Figure 1.
GENERAL DESCRIPTION
The DAC8043 is a high accuracy 12-bit CMOS multiplying
DAC in a space-saving 8-lead PDIP package. Featuring serial
data input, double buffering, and excellent analog performance,
the DAC8043 is ideal for applications where PC board space is
at a premium. In addition, improved linearity and gain error
performance permit reduced parts count through the elimination
of trimming components. Separate input clock and load DAC
control lines allow full user control of data loading and analog
output.
Data in the DAC register is converted to an output current by
the digital-to-analog converter (DAC).
The fast interface timing of the DAC8043 may reduce timing
design considerations while minimizing microprocessor wait
states. For applications requiring an asynchronous clear function
or more versatile microprocessor interface logic, refer to the
AD5443.
Operating from a single 5 V power supply, the DAC8043 is the
ideal low power, small size, high performance solution to many
application problems. It is available in a PDIP package that is
compatible with auto-insertion equipment. There is also a
16-lead SOIC package available.
The circuit consists of a 12-bit serial-in, parallel-out shift register,
a 12-bit DAC register, a 12-bit CMOS DAC, and control logic.
Serial data is clocked into the input register on the rising edge
of the CLK pulse. When the new data word has been clocked
LD
in, it is loaded into the DAC register with the
input pin.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2011 Analog Devices, Inc. All rights reserved.
DAC8043
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................7
Terminology.......................................................................................9
Digital Section................................................................................. 10
General Circuit Information..................................................... 10
Equivalent Circuit Analysis ...................................................... 11
Dynamic Performance............................................................... 11
Applications Information .............................................................. 12
Application Tips ......................................................................... 12
Interfacing to the MC6800........................................................ 14
DAC8043 Interface to the 8085................................................ 14
DAC8043 to the 68000 Interface.............................................. 14
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 16
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Wafer Test Limits .......................................................................... 4
Absolute Maximum Ratings............................................................ 5
Caution .......................................................................................... 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
REVISION HISTORY
1/11—Rev. D to Rev. E
Updated Format..................................................................Universal
Added SOIC_W Models....................................................Universal
Added Table 5.................................................................................... 6
Updated Outline Dimensions....................................................... 15
Changes to Ordering Guide .......................................................... 15
3/03—Data Sheet Changed from Rev. C to Rev. D.
Deleted 8-Lead CIRDIP and 16-Lead Wide-Body SOL......Universal
Figures renumbered ...........................................................Universal
Changes to Absolute Maximum Ratings....................................... 4
Changes to Ordering Guide ............................................................ 4
Deleted to Dice Characteristics ...................................................... 4
Updated Outline Dimensions....................................................... 11
Rev. E | Page 2 of 16
DAC8043
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VDD = 5 V; VREF = 10 V; IOUT = GND = 0 V; TA = full temperature range specified under the Absolute Maximum Ratings, unless otherwise
noted.
Table 1.
Parameter
Symbol Conditions
Min Typ
Max
Unit
STATIC ACCURACY
Resolution
N
INL
12
Bits
LSB
LSB
LSB
Nonlinearity1
DAC8043G
DAC8043F
±±
1
±1
2
Differential Nonlinearity2
Gain Error3
DNL
GFSE
TA = 25°C
LSB
TA = full temperature range, all grades
2
±5
LSB
ppm/°C
Gain Tempco (ΔGain/∆Temp)4
Power Supply Rejection Ratio
(ΔGain/ΔVDD)
Output Leakage Current5
TCGFS
PSRR
ΔVDD = ±5%
±0.0006 ±0.002 %/%
ILKG
IZSE
RIN
TA = 25°C
TA = full temperature range
TA = 25°C
±5
nA
nA
LSB
LSB
kΩ
±25
0.03
0.15
15
Zero Scale Error6, 7
TA = full temperature range
Input Resistance8
AC PERFORMANCE
7
11
Output Current
Settling Time4, 9
tS
Q
TA = 25°C, VREF = 0 V
IOUT load = 100 Ω, CEXT = 13 pF, DAC register loaded
alternately with all 0s and all 1s
VREF = 20 V p-p @ f = 10 kHz, digital input = 0000
0000 0000
0.25
2
1
20
μs
nVs
Digital-to-Analog Glitch Energy4, 10
4, 11
Feedthrough Error (VREF to IOUT
)
FT
0.7
1
mV p-p
TA = 25°C
Total Harmonic Distortion4
THD
en
VREF = 6 V rms @ 1 kHz, DAC register loaded with
all 1s
10 Hz to 100 kHz between RFB and IOUT
–85
dB
Output Noise Voltage Density4, 12
DIGITAL INPUTS
Digital Input
17
nV/√Hz
High
Low
VIN
VIL
IIL
2.4
V
V
μA
pF
0.8
±1
8
Input Leakage Current13
Input Capacitance4, 11
ANALOG OUTPUTS
Output Capacitance4
VIN = 0 V to +5 V
VIN = 0 V
CIN
COUT
Digital inputs = VIH
Digital inputs = VIL
110
80
pF
pF
TIMING CHARACTERISTICS4, 14
Data Setup Time
tDS
tDH
tCH
tCL
tLD
tASB
TA = full temperature range
TA = full temperature range
TA = full temperature range
TA = full temperature range
TA = full temperature range
TA = full temperature range
40
80
90
120
120
0
ns
ns
ns
ns
ns
ns
Data Hold Time
Clock Pulsewidth High
Clock Pulsewidth Low
Load Pulsewidth
LSB Clock Into Input Register to
Load DAC Register Time
Rev. E | Page 3 of 16
DAC8043
Parameter
Symbol Conditions
Min Typ
4.75
Max
Unit
POWER SUPPLY
Supply Voltage
Supply Current
VDD
5
5.25
500
100
V
μA
μA
IDD
Digital inputs = VIH or VIL
Digital inputs = 0 V or VDD
1
1ꢀ2 LSB = 0.012% of full scale.
2 All grades are monotonic to 12 bits over temperature.
3 Using internal feedback resistor.
4 Guaranteed by design and not tested.
5 Applies to IOUT; all digital inputs = 0 V.
6 VREF = 10 V; all digital inputs = 0 V.
7 Calculated from worst-case RREF: IZSE (in LSBs) = (RREF × ILKG × 4096)ꢀVREF
8 Absolute temperature coefficient is less than 300 ppmꢀ°C.
.
9 IOUT load = 100 Ω , CEXT = 13 pF, digital input = 0 V to VDD or VDD to 0 V. Extrapolated to ½ LSB; tS = propagation delay (tPD) + 9τ
where τ = measured time constant of the final RC decay.
10
V
= 0 V, all digital inputs = 0 V to VDD or VDD to 0 V.
REF
11 All digit inputs = 0 V.
12 Calculations from en = √4K TRB
where:
K = Boltzmann constant, Jꢀ°K,
R = resistance, Ω,
T = resistor temperature, °K,
B = bandwidth, Hz.
13 Digital inputs are CMOS gates; IIN is typically 1 nA at 25°C.
14 Tested at VIN = 0 V or VDD
.
WAFER TEST LIMITS
VDD = 5 V, VREF = 10 V; IOUT = GND = 0 V, TA = 25°C.
Table 2.
DAC8043GBC Limit
Parameter1
Symbol
Conditions
Min
Typ
Max
Unit
STATIC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Gain Error
N
12
Bits
LSB
LSB
LSB
%ꢀ%
nA
INL
DNL
GFSE
PSRR
ILKG
1
1
2
Using internal feedback resistor
ΔVDD = 5%
Digital inputs = VIL
Power Supply Rejection Ratio
0.002
5
Output Leakage Current (IOUT
REFERENCE INPUT
Input Resistance
)
7
15
RIN
kΩ
DIGITAL INPUTS
Digital Input High
Digital Input Low
Input Leakage Current
POWER SUPPLY
VIH
VIL
IIL
2.4
V
V
μA
0.8
1
VIN = 0 V to VDD
Supply Current
IDD
Digital inputs = VIN or VIL
Digital inputs = 0 V or VDD
500
100
μA
μA
1 Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult a factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
Rev. E | Page 4 of 16
DAC8043
ABSOLUTE MAXIMUM RATINGS
CAUTION
TA = 25°C, unless otherwise noted.
1. Do not apply voltages higher than VDD or less than GND
potential on any terminal except VREF and RFB.
2. The digital control inputs are Zener-protected; however,
permanent damage may occur on unprotected units from
high energy electrostatic fields. Keep units in conductive
foam at all times until ready to use.
3. Use proper antistatic handling procedures.
4. Absolute Maximum Ratings apply to both packaged devices
and dice. Stresses above those listed under the Absolute
Maximum Ratings may cause permanent damage to the
device.
Table 3.
Parameter
Rating
VDD to GND
VREF to GND
VRFB to GND
Digital Input Voltage Range
VIOUT to GND
Operating Temperature Range
FP Version
GP Version
Junction Temperature
Storage Temperature
Lead Temperature (Soldering, 60 sec)
−0.3 V to +8 V
±18 V
±18 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−40°C to +85°C
0°C to 70°C
150°C
−65°C to +150°C
300°C
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 4. Thermal Resistance
Package Type
θJA
96
92
θJC
37
27
Unit
°C/W
°C/W
8-Lead PDIP
16-Lead SOIC
ESD CAUTION
Rev. E | Page 5 of 16
DAC8043
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC
NC
1
2
3
4
5
6
7
8
16 NC
15 NC
V
14 V
DD
REF
DAC8043
R
13 CLK
12 SRI
11 LD
FB
TOP VIEW
I
(Not to Scale)
OUT
GND
1
8
V
V
DD
REF
GND
NC
10 NC
DAC8043
2
3
4
R
CLK
SRI
LD
7
6
5
FB
9
NC
TOP VIEW
I
OUT
(Not to Scale)
NC = NO CONNECT. DO NOT
CONNECT TO THIS PIN.
GND
Figure 2. 8-Lead PDIP
Figure 3. 16-Lead Wide-Body SOIC
Table 5. Pin Function Descriptions
Pin No.
8-Lead PDIP 16-Lead SOIC
Mnemonic Description
1
2
3
4
VREF
RFB
DAC Reference Voltage Input Pin.
DAC Feedback Resistor Pin. This pin establishes voltage output for the DAC by
connecting to an external amplifier output.
3
4
5
5
6, 7
11
IOUT
GND
LD
DAC Current Output.
Ground Pin.
Load Strobe, Level-Sensitive Digital Input. Transfers shift-register data to DAC register
while active low.
6
12
SRI
12-Bit Serial Register Input. Data loads directly into the shift register MSB first. Extra
leading bits are ignored.
7
8
13
14
CLK
VDD
Serial Clock Input. Positive-edge clocks data into shift register.
Positive Power Supply Input.
1, 2, 8, 9, 10, 15, 16 NC
Do Not Connect to These Pins.
Rev. E | Page 6 of 16
DAC8043
TYPICAL PERFORMANCE CHARACTERISTICS
0
1.0
0.8
0.6
DIGITAL INPUT =
1111 1111 1111
V
V
= 5V
–12
–24
–36
–48
–60
–72
–84
–96
–108
–120
DD
= 100mV
REF
T
= 25°C
A
DIGITAL INPUT =
0000 0000 0000
0.4
0.2
0
1k
10k
100k
FREQUENCY (Hz)
1M
10M
0
1
2
3
4
V
(V)
IN
Figure 4. Gain vs. Frequency (Output Amplifier: OP42)
Figure 6. Supply Current vs. Logic Input Voltage
0
–20
–40
–60
–80
0.5
0.4
0.3
0.2
0.1
V
V
= 5V
DD
= 6V rms
IN
OUTPUT AMPLIFIER: OP42
= 25°C
T
A
0
–0.1
–0.2
–0.3
–0.4
–0.5
–100
–120
10
100
1k
10k
100k
0
512
1024
1536
2048
2560
3072
3584
4095
FREQUENCY (Hz)
DIGITAL INPUT CODE (Decimal)
Figure 5. Total Harmonic Distortion vs. Frequency (Multiplying Mode)
Figure 7. Linearity Error vs. Digital Input Code
Rev. E | Page 7 of 16
DAC8043
0.50
0.25
0
0.50
0.25
0
–0.25
–0.25
–0.50
–0.50
2
4
6
8
10
2
4
6
8
10
V
(V)
V
(V)
REF
REF
Figure 10. DNL Error vs. Reference Voltage
Figure 8. Linearity Error vs. Reference Voltage
4.0
3.0
2.4
2.0
1.0
–0.8
1
3
5
7
9
11
13
15
V
(V)
DD
Figure 9. Logic Threshold Voltage vs. Supply Voltage
Rev. E | Page 8 of 16
DAC8043
TERMINOLOGY
Interface Logic Information
Integral Nonlinearity (INL)
The DAC8043 has been designed for ease of operation. The
timing diagram (see Figure 12) illustrates the input register
loading sequence. Note that the most significant bit (MSB)
is loaded first.
This is the single most important DAC specification. Analog
Devices, Inc., measures INL as the maximum deviation of
the analog output (from the ideal) from a straight line drawn
between the end points. It is expressed as a percent of full-scale
range or in terms of LSBs.
Once the input register is full, the data is transferred to the
LD
DAC register by taking
momentarily low.
Refer to the Analog Devices Glossary of EE Terms for
additional digital-to-analog converter definitions.
Rev. E | Page 9 of 16
DAC8043
DIGITAL SECTION
LD
, and CLK) are TTL
The digital circuitry forms an interface in which serial data
can be loaded under microprocessor control into a 12-bit shift
register and then transferred, in parallel, to the 12-bit DAC
register.
The digital inputs of the DAC8043 (SRI,
compatible. The input voltage levels affect the amount of current
drawn from the supply; peak supply current occurs as the digital
input (VIN) passes through the transition region (see Figure 6).
Maintaining the digital input voltage levels as close as possible
to the VDD and GND supplies minimizes supply current
consumption.
A simplified circuit of the DAC8043 is shown in Figure 13,
which has an inverted R-2R ladder network consisting of silicon-
chrome, highly stable (50 ppm/°C) thin-film resistors, and
twelve pairs of NMOS current-steering switches.
The digital inputs of the DAC8043 have been designed with
ESD resistance incorporated through careful layout and the
inclusion of input protection circuitry. Figure 11 shows the input
protection diodes and series resistor; this input structure is
duplicated on each digital input. High voltage static charges
applied to the inputs are shunted to the supply and ground rails
through forward biased diodes. These protection diodes were
designed to clamp the inputs to well below dangerous levels
during static discharge conditions.
These switches steer binarily weighted currents into either IOUT
or GND; this yields a constant current in each ladder leg, regardless
of digital input code. This constant current results in a constant
input resistance at VREF equal to R. The VREF input may be driven by
any reference voltage or current, ac or dc, that is within the limits
stated in the Absolute Maximum Ratings section.
The twelve output current-steering NMOS FET switches are in
series with each R-2R resistor; they can introduce bit errors if all
are of the same RON resistance value. They were designed so that
the switch on resistance is binarily scaled so that the voltage drop
across each switch remains constant. If, for example, Switch S1 of
Figure 13 was designed with an on resistance of 10 Ω, Switch S2 for
20 Ω, and so on, a constant 5 mV drop would be maintained across
each switch.
GENERAL CIRCUIT INFORMATION
The DAC8043 is a 12-bit multiplying digital-to-analog
converter (DAC) with a very low temperature coefficient.
It contains an R-2R resistor ladder network, data input,
control logic, and two data registers.
V
DD
TL/TTL/CMOS
INPUTS
Figure 11. Digital Input Protection
1
BIT 1 MSB
BIT 2
BIT 11
BIT 12 LSB
SRI
tDS
tDH
tCL
1
2
11
CLK INPUT
tCH
tASB
LOAD SERIAL DATA
INTO INPUT REGISTER
tLD
LD
LOAD INPUT REGISTER’S
DATA INTO DAC REGISTER
1
DATA LOADED MSB FIRST.
Figure 12. Write Cycle Timing Diagram
Rev. E | Page 10 of 16
DAC8043
To further ensure accuracy across the full temperature range,
permanently on MOS switches were included in series with
the feedback resistor and the terminating resistor of the R-2R
ladder. The simplified DAC circuit, Figure 13, shows the location
of the series switches. These series switches are equivalently
scaled to two times Switch S1 (MSB) and to Switch S12 (LSB),
respectively, to maintain constant relative voltage drops with
varying temperature. During any testing of the resistor ladder
or RFEEDBACK (such as incoming inspection), VDD must be present
to turn on these series switches.
affected by these variations. This variation is best illustrated by
using the circuit of Figure 15 and the following equation:
RFB
RO
VERROR = VOS 1 +
where:
RO is a function of the digital code and
= 10 kΩ for more than four bits of Logic 1.
= 30 kΩ for any single bit of Logic 1.
Therefore, the offset gain varies as follows:
At Code 0011 1111 1111,
10kΩ
10kΩ
10kΩ
V
REF
20kΩ
S1
20kΩ
S2
20kΩ
20kΩ
20kΩ
S3
S12
10 kΩ
10 kΩ
*
VERROR = V 1 +
= 2VOS
OS
1
GND
At Code 0100 0000 0000,
I
OUT
10kΩ
10 kΩ
30 kΩ
R
FEEDBACK
VERROR = V 1 +
= 4 /3VOS
OS
*
2
BIT 1 (MSB) BIT 2
BIT 3
BIT 12 (LSB)
The error difference is 2/3 VOS.
DIGITAL INPUTS
(SWITCHES SHOWN FOR DIGITAL INPUTS (HIGH))
Because one LSB has a weight (for VREF = 10 V) of 2.4 mV for
the DAC8043, it is clearly important that VOS be minimized,
either by using the amplifier’s nulling pins or an external nulling
network or by selecting an amplifier with inherently low VOS.
Amplifiers with sufficiently low VOS include OP77, OP07, OP27,
and OP42.
*THESE SWITCHES PERMANENTLY ON.
Figure 13. Simplified DAC Circuit
EQUIVALENT CIRCUIT ANALYSIS
Figure 14 shows an equivalent analog circuit for the DAC8043.
The (D × VREF)/R current source is code dependent and is the
current generated by the DAC. The current source, ILKG, consists
of surface and junction leakages and doubles approximately
every 10°C. COUT is the output capacitance; it is the result of
the N-channel MOS switches and varies from 80 pF to 110 pF,
depending on the digital input code. RO is the equivalent out-
put resistance that also varies with digital input code. R is the
nominal R-2R resistor ladder resistance.
R
R
R
V
ETC
REF
R
FB
2R
2R
2R
OP77
V
OS
R
Figure 15. Simplified Circuit
R
FB
I
The gain and phase stability of the output amplifier, board
layout, and power supply decoupling all affect the dynamic
performance. The use of a small compensation capacitor may
be required when high speed operational amplifiers are used. It
may be connected across the feedback resistor of the amplifier
to provide the necessary phase compensation to critically damp
the output. The output capacitance of the DAC8043 and the RFB
resistor form a pole that must be outside the amplifier’s unity
gain crossover frequency.
V
OUT
REF
D × V
R
REF
C
I
R
R
OUT
LKG
GND
Figure 14. Equivalent Analog Circuit
DYNAMIC PERFORMANCE
Output Impedance
The output resistance of the DAC8043, as in the case of the
output capacitance, varies with the digital input code. This
resistance, looking back into the IOUT terminal, may be between
10 kΩ (the feedback resistor alone when all digital inputs are low)
and 7.5 kΩ (the feedback resistor in parallel with approximately
30 kΩ of the R-2R ladder network resistance when any single bit
logic is high). Static accuracy and dynamic performance will be
The considerations when using high speed amplifiers are:
1. Phase compensation (see Figure 16 and Figure 17).
2. Power supply decoupling at the device socket and the use
of proper grounding techniques.
Rev. E | Page 11 of 16
DAC8043
APPLICATIONS INFORMATION
Gain error may be trimmed by adjusting R1, as shown in Figure 17.
The DAC register must first be loaded with all 1s. R1 may then
be adjusted until VOUT = −VREF (4095/4096). In the case of an
adjustable VREF, R1 and R2 may be omitted, with VREF adjusted
to yield the desired full-scale output.
APPLICATION TIPS
In most applications, linearity depends upon the potential
of the IOUT and GND pins being equal to each other. In most
applications, the DAC is connected to an external op amp
with its noninverting input tied to ground (see Figure 16 and
Figure 17). The amplifier selected should have a low input bias
current and low drift over temperature. The amplifier’s input offset
voltage should be nulled to less than 200 μV (less than 10% of
1 LSB).
In most applications, the DAC8043’s negligible zero-scale error
and very low gain error permit the elimination of the trimming
components (R1 and the external R2) without adversely affecting
on circuit performance.
Table 6. Unipolar Code Table1, 2
The noninverting input of the operational amplifier should have
a minimum resistance connection to ground; the usual bias
current compensation resistor should not be used. This resistor
can cause a variable offset voltage appearing as a varying output
error. All grounded pins should tie to a single common ground
point, avoiding ground loops. The VDD power supply should
have a low noise level with no transients greater than 17 V.
Digital Input
Nominal Analog Output
MSB LSB
(VOUT as Shown in Figure 16 and Figure 17)
1111 1111 1111
1000 0000 0001
1000 0000 0000
0111 1111 1111
0000 0000 0001
0000 0000 0000
4095
4096
−VREF
−VREF
−VREF
−VREF
−VREF
−VREF
2049
4096
Unipolar Operation (2-Quadrant)
VREF
2
2048
4096
The circuits shown in Figure 16 and Figure 17 may be used with
an ac or dc reference voltage. The output of the circuit ranges
between 0 V and approximately −VREF (4095/4096), depending
upon the digital input code. The relationship between the
digital input and the analog output is shown in Table 6. The
limiting parameters for the VREF range are the maximum input
voltage range of the op amp or 25 V, whichever is lowest.
5V
= −
2047
4096
1
4096
0
V
REF
= 0
10V
4096
V
V
DD
REF
SERIAL
DATA
INPUT
1 Nominal full scale for Figure 16 and Figure 17 circuits is given by
R
FB
+15V
7
4095
4096
REF
15pF
DAC8043
FS = −V
CLK
LD
2
3
I
OUT
6
V
OUT
OP77
4
2 Nominal LSB magnitude for Figure 16 and Figure 17 circuits is given by
GND
1
REF
LSB = V
or V
(
2−n
)
REF
–15V
4096
Figure 16. Unipolar Operation with High Accuracy Op Amp (2-Quadrant)
V
10V
REF
5V
R
1
100Ω
V
V
DD
R
50Ω
REF
2
SERIAL
DATA
INPUT
R
FB
+15V
15pF
DAC8043
CLK
LD
2
7
OP42
4
I
OUT
6
V
OUT
3
GND
–15V
Figure 17. Unipolar Operation with Fast Op Amp and Gain Error Trimming
(2-Quadrant)
Rev. E | Page 12 of 16
DAC8043
Bipolar Operation (4-Quadrant)
scale can be adjusted by loading the DAC register with 1111
1111 1111 and either adjusting the amplitude of VREF or the
value of R5 until the desired VOUT is achieved.
Figure 19 details a suggested circuit for bipolar, or offset binary,
operation. Table 7 shows the digital input to analog output
relationship. The circuit uses offset binary coding. Twos comple-
ment code can be converted to offset binary by software
inversion of the MSB or by the addition of an external inverter
to the MSB input.
Analog/Digital Division
The transfer function for the DAC8043 connected in the
multiplying mode, as shown in Figure 16, Figure 17, and
Figure 19, is
Table 7. Bipolar (Offset Binary) Code Table1, 2
A
A2 A3
A12
IN
VO V
1
...
Digital Input
Nominal Analog Output
21 22 23
212
MSB
LSB
(VOUT as Shown in Figure 19)
where AX assumes a value of 1 for an on bit and 0 for an off bit.
1111 1111 1111
2047
2048
The transfer function is modified when the DAC is connected
in the feedback of an operational amplifier, as shown in Figure 18
and becomes
VREF
VREF
1000 0000 0001
1
2048
VIN
1000 0000 0000
0111 1111 1111
0
VO
A
A2 A3
A12
1
...
1
2048
21 22 23
24
VREF
VREF
VREF
The previous transfer function is the division of an analog
voltage (VREF) by a digital word. The amplifier goes to the rails
with all bits off because division by zero is infinity. With all bits
on the gain is 1 ( 1 ꢀSB). The gain becomes 4096 with the ꢀSB,
Bit 12, on.
0000 0000 0001
0000 0000 0000
2047
2048
2048
2048
DIGITAL
INPUT
1 Nominal full scale for Figure 19 circuits is given by
2047
2048
REF
FS V
LD SRI CLK
2 Nominal LSB magnitude for Figure 19 circuits is given by
V
R
V
DD
IN
5V
FB
1
2048
REF
LSB V
DAC8043
I
V
REF
OUT
Resistors R3, R4, and R5 must be selected to match within 0.01%,
and they all must be of the same (preferably metal foil) type to
ensure temperature coefficient matching. Mismatching between
R3 and R4 causes offset and full-scale errors, while an R5 to R4
and R3 mismatch results in full-scale error.
GND
2
3
6
V
OP42
OUT
Calibration is performed by loading the DAC register with 1000
0000 0000 and adjusting R1 until VOUT = 0 V. R1 and R2 may be
omitted, adjusting the ratio of R3 to R4 to yield VOUT = 0 V. Full
Figure 18. Analog/Digital Divider
R
50Ω
2
R
4
20kΩ
5V
C
1
R
20kΩ
5
10.33pF
V
R
FB
DD
R
10kΩ
3
I
OUT
1/2
V
V
IN
REF DAC8043
OP200
1/2
R
100Ω
A
1
1
V
GND
OP200
CONTROL
BITS
OUT
A
2
SRI
CONTROL SERIAL
ANALOG
COMMON
INPUTS
DATA
INPUT
Figure 19. Bipolar Operation (4-Quadrant, Offset Binary)
Rev. E | Page 13 of 16
DAC8043
Serial data supplied to the DAC8043 must be present in
the right-justified format in Register H and Register L of the
microprocessor.
INTERFACING TO THE MC6800
As shown in Figure 20, the DAC8043 may be interfaced to the
MC6800 by successively executing memory write instructions
while manipulating the data between writes, so that each write
presents the next bit.
A
0
(8)
ADDRESS BUS (16)
A
15
In this example, the most significant bits are found in the 0000
and 0001 memory locations. The four MSBs are found in the
lower half of 0000 and the eight LSBs in 0001. The data is taken
from the DB7 line.
8085
A
A
2
0
E
E
E
1
3
2
8212
ALE
WR
74LS138
ADDRESS
DECODER
5V
The serial data loading is triggered by the CLK pulse, which
is asserted by a decoded memory write to the 2000 memory
AD
AD
0
7
(8)
DATA
W
location, R/ , and Φ2. A write to address location 4000
CLK
LD
SRI
SOD
transfers data from the input register to the DAC register.
DAC8043*
*ANALOG CIRCUITRY OMITTED FOR
SIMPLICITY.
A
0
16-BIT DATA BUS
A
15
Figure 21. DAC8043 to 8085 Interface
DAC8043 TO THE 68000 INTERFACE
R/W
A
A
2
0
E
1
MC6800
Φ2
The interface of the DAC8043 to the 68000 microprocessor is
shown in Figure 22. Serial data to the DAC is taken from one
of the microprocessor’s data bus lines.
74LS138
E
3
2
ADDRESS
DECODER
E
DB
DB
0
7
8-BIT DATA BUS
A
1
ADDRESS BUS
A
23
CLK
LD
DAC8043*
SRI
ADDRESS
DECODE
*ANALOG CIRCUITRY OMITTED
FOR SIMPLICITY.
CS
AS
68000
MICRO-
Figure 20. DAC8043 to MC6800 Interface
PROCESSOR
VMA
+
DAC8043 INTERFACE TO THE 8085
CLK
LD
The interface of the DAC8043 to the 8085 microprocessor
is shown in Figure 21. Note that the SOD line of the micro-
processor is used to present data serially to the DAC.
VPA
UDS
1/4 74HC125
DAC8043*
SRI
DB
15
Data is clocked into the DAC8043 by executing memory write
instructions. The clock input is generated by decoding Address
DATA BUS
*ANALOG CIRCUITRY OMITTED FOR SIMPLICITY.
DB
0
WR
8000 and
memory write instruction to Address A000.
. Data is loaded into the DAC register with a
Figure 22. DAC8043 to 68000 Microprocessor Interface
Rev. E | Page 14 of 16
DAC8043
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
1
5
4
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 23. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-8)
Dimensions shown in inches and (millimeters)
10.50 (0.4134)
10.10 (0.3976)
16
1
9
8
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
0.25 (0.0098)
1.27 (0.0500)
BSC
45°
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 24. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-16)
Dimensions shown in millimeters and (inches)
Rev. E | Page 15 of 16
DAC8043
ORDERING GUIDE
Model1, 2
Relative Accuracy
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
0°C to 70°C
Package Description
8-Lead PDIP
8-Lead PDIP
16-Lead SOIC_W
8-Lead PDIP
8-Lead PDIP
Package Option
DAC8043FP
DAC8043FPZ
DAC8043FSZ
DAC8043GP
DAC8043GPZ
±1 LSB
±1 LSB
±1 LSB
±± LSB
±± LSB
N-8
N-8
RW-16
N-8
N-8
0°C to 70°C
1 Z = RoHS Compliant Part.
2 All commercial and industrial temperature range parts are available with burn-in.
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00271-0-1/11(E)
Rev. E | Page 16 of 16
相关型号：
DAC8043U/2K5
D/A Converter, 1 Func, Serial Input Loading, 0.25us Settling Time, PDSO8, GREEN, SOIC-8
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