DAC8248FW [ADI]
Dual 12-Bit 8-Bit Byte Double-Buffered CMOS D/A Converter; 双12位8位字节双缓冲CMOS D / A转换器
| 型号： | DAC8248FW |
| 厂家： | 
ADI |
| 描述： | Dual 12-Bit 8-Bit Byte Double-Buffered CMOS D/A Converter |
| 文件： | 总16页 (文件大小：351K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual 12-Bit (8-Bit Byte)
Double-Buffered CMOS D/A Converter
a
DAC8248
P IN CO NNECTIO NS
FEATURES
Tw o Matched 12-Bit DACs on One Chip
12-Bit Resolution w ith an 8-Bit Data Bus
Direct Interface w ith 8-Bit Microprocessors
Double-Buffered Digital Inputs
RESET to Zero Pin
24-P in 0.3" Cer dip (W Suffix),
24-P in Epoxy D IP (P Suffix),
24-P in SO L (S Suffix)
12-Bit Endpoint Linearity (؎1/ 2 LSB) Over Tem perature
؉5 V to ؉15 V Single Supply Operation
Latch-Up Resistant
Im proved ESD Resistance
Packaged in a Narrow 0.3" 24-Pin DIP and 0.3" 24-Pin
SOL Package
Available in Die Form
APPLICATIONS
Multichannel Microprocessor-Controlled System s
Robotics/ Process Control/ Autom ation
Autom atic Test Equipm ent
Program m able Attenuator, Pow er Supplies, Window
Com parators
Instrum entation Equipm ent
T he DAC8248’s double-buffered digital inputs allow both
DAC’s analog output to be updated simultaneously. T his is par-
ticularly useful in multiple DAC systems where a common
LDAC signal updates all DACs at the same time. A single
RESET pin resets both outputs to zero.
Battery Operated Equipm ent
GENERAL D ESCRIP TIO N
T he DAC8248’s monolithic construction offers excellent DAC-
to-DAC matching and tracking over the full operating tempera-
ture range. T he DAC consists of two thin-film R-2R resistor
ladder networks, two 12-bit, two 8-bit, and two 4-bit data regis-
ters, and control logic circuitry. Separate reference input and
feedback resistors are provided for each DAC. T he DAC8248
(continued on page 4)
T he DAC8248 is a dual 12-bit, double-buffered, CMOS digital-
to-analog converter. It has an 8-bit wide input data port that inter-
faces directly with 8-bit microprocessors. It loads a 12-bit word in
two bytes using a single control; it can accept either a least signifi-
cant byte or most significant byte first. For designs with a 12-bit or
16-bit wide data path, choose the DAC8222 or DAC8221.
FUNCTIO NAL BLO CK D IAGRAM
REV. B
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
DAC8248–SPECIFICATIONS
(@ V = +5 V or +15 V; VREF A = VREF B = +10 V; VOUTA = VOUT B = 0 V; AGND = DGND = 0 V;
DD
ELECTRICAL CHARACTERlSTICS
T = Full Temp Range specified in Absolute Maximum Ratings; unless otherwise noted. Specifications apply for DAC A and DAC B.)
A
D AC8248
P aram eter
Sym bol
Conditions
Min
Typ
Max
Units
ST AT IC ACCURACY
Resolution
N
12
Bits
Relative Accuracy
INL
DAC8248A/E/G
DAC8248F/H
All Grades are Guaranteed Monotonic
DAC8248A/E
DAC8248G
DAC8248F/H
±1/2
±1
±1
±1
±2
LSB
LSB
LSB
LSB
LSB
LSB
Differential Nonlinearity
Full-Scale Gain Error1
DNL
GFSE
±4
Gain T emperature Coefficient
(∆Gain/∆T emperature)
T CGFS
ILKG
(Notes 2, 3)
All Digital Inputs = 0s
TA = +25°C
TA = Full T emperature Range
(Note 4)
±2
±5
ppm/°C
Output Leakage Current
±5
±10
±50
15
I
OUT A (Pin 2), IOUT B (Pin 24)
nA
kΩ
Input Resistance (VREF A
,
)
RREF
8
11
REF B
∆RREF
RREF
Input Resistance Match
±0.2
±1
%
DIGIT AL INPUT S
Digital Input High
VINH
VINL
VDD = +5 V
VDD = +15 V
VDD = +5 V
VDD = +15 V
2.4
13.5
V
V
V
V
Digital Input Low
0.8
1.5
Input Current (VIN = 0 V
TA = +25°C
TA = Full T emperature Range
DB0–DB11
WR, LDAC, DAC A/DAC B,
LSB/MSB, RESET
±0.001 ±1
±10
µA
µA
pF
or VDD and VINL or VINH
Input Capacitance
(Note 2)
)
IIN
CIN
10
15
pF
POWER SUPPLY
Supply Current
IDD
Digital Inputs = VINL or VINH
Digital Inputs = 0 V or VDD
∆VDD = ±5%
2
100
mA
µA
10
DC Power Supply Rejection Ratio
(∆Gain/∆VDD
PSRR
)
0.002
%/%
AC PERFORMANCE CHARACTERIST ICS2
Propagation Delay5, 6
tPD
tS
CO
TA = +25°C
TA = +25°C
Digital Inputs = All 0s
350
1
ns
µs
Output Current Setting T ime6, 7
Output Capacitance
C
OUT A, COUT B
Digital Inputs = All 1s
OUT A, COUT B
90
pF
pF
dB
dB
C
120
–70
–70
AC Feedthrough at
FTA
FTB
VREF A to IOUT A; VREF A = 20 V p-p
f = 100 kHz; TA = +25°C
VREF B to IOUT B; VREF B = 20 V p-p
f = 100 kHz; TA = +25°C
I
OUT A or IOUT B
–2–
REV. B
DAC8248
P aram eter
Sym bol
Conditions
D AC8248
Units
VD D = +5 V
VD D = +15 V
Switching Characteristics
(Notes 2, 8)
+25؇C –40؇C to +85؇C –55؇C to +125؇C All Tem ps
(Note 9)
(Note 10)
LSB/MSB Select to
Write Set-Up T ime
LSB/MSB Select to
Write Hold T ime
DAC Select to
Write Set-Up T ime
DAC Select to
Write Hold T ime
LDAC to
Write Set-Up T ime
LDAC to
Write Hold T ime
Data Valid to
Write Set-Up T ime
Data Valid to
tCBS
tCBH
tAS
130
0
170
0
180
0
80
0
ns min
ns min
ns min
ns min
ns min
ns min
ns min
180
0
210
0
220
0
80
0
tAH
tLS
tLH
tDS
120
0
150
0
160
0
80
0
160
210
220
70
Write Hold T ime
Write Pulse Width
LDAC Pulse Width
Reset Pulse Width
tDH
tWR
tLWD
tRWD
0
0
0
10
90
60
60
ns min
ns min
ns min
ns min
130
100
80
150
110
90
170
130
90
NOT ES
11Measured using internal RFB A and RFB B. Both DAC digital inputs = 1111 1111 1111.
12Guaranteed and not tested.
13Gain T C is measured from +25°C to T MIN or from +25°C to T MAX
14Absolute T emperature Coefficient is approximately +50 ppm/°C.
.
15From 50% of digital input to 90% of final analog output current. VREF A = VREF B = +10 V; OUT A, OUT B load = 100 Ω, CEXT = 13 pF.
16WR, LDAC = 0 V; DB0–DB7 = 0 V to VDD or VDD to 0 V.
17Settling time is measured from 50% of the digital input change to where the output settles within 1/2 LSB of full scale.
18See T iming Diagram.
19T hese limits apply for the commercial and industrial grade products.
10T hese limits also apply as typical values for VDD = +12 V with +5 V CMOS logic levels and T A = +25°C.
Specifications subject to change without notice.
Burn-In Circuit
REV. B
–3–
DAC8248
(continued from page 1)
1
P ackage Type
Units
JA
JC
operates on a single supply from +5 V to +15 V, and it dissi-
pates less than 0.5 mW at +5 V (using zero or VDD logic levels).
T he device is packaged in a space-saving 0.3", 24-pin DIP.
24-Pin Hermetic DIP (W)
24-Pin Plastic DIP (P)
24-Pin SOL (S)
69
62
72
10
32
24
°C/W
°C/W
°C/W
T he DAC8248 is manufactured with PMI’s highly stable thin-
film resistors on an advanced oxide-isolated, silicon-gate,
CMOS technology. PMI’s improved latch-up resistant design
eliminates the need for external protective Schottky diodes.
NOT E
1
JA specified for worst case mounting conditions, i.e., JA is specified for device in
socket for cerdip and P-DIP packages; JA is specified for device soldered to printed
circuit board for SOL package.
CAUTIO N
ABSO LUTE MAXIMUM RATINGS
(T A = +25°C, unless otherwise noted.)
1. Do not apply voltages higher than VDD or less than GND
potential on any terminal except VREF and RFB
.
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V
AGND to DGND . . . . . . . . . . . . . . . . . . –0.3 V, VDD +0.3 V
Digital Input Voltage to DGND . . . . . . . –0.3 V, VDD +0.3 V
2. T he digital control inputs are Zener-protected; however,
permanent damage may occur on unprotected units from
high energy electrostatic fields. Keep units in conductive
foam at all times until ready to use.
I
OUT A, IOUT B to AGND . . . . . . . . . . . . . . –0.3 V, VDD +0.3 V
V
V
REF A, VREF B to AGND . . . . . . . . . . . . . . . . . . . . . . . . ±25 V
RFB A, VRFB B to AGND . . . . . . . . . . . . . . . . . . . . . . . . ±25 V
3. Do not insert this device into powered sockets; remove
power before insertion or removal.
Operating T emperature Range
AW Version . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
EW, FW, FP Versions . . . . . . . . . . . . . . . . –40°C to +85°C
GP, HP, HS Versions . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Junction T emperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Storage T emperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead T emperature (Soldering, 60 sec) . . . . . . . . . . . . +300°C
4. Use proper antistatic handling procedures.
5. Devices can suffer permanent damage and/or reliability deg-
radation if stressed above the limits listed under Absolute
Maximum Ratings for extended periods. T his is a stress rat-
ing only and functional operation at or above this specifica-
tion is not implied.
O RD ERING GUID E 1
Relative
Accuracy
(+5 V or +15 V)
Gain Error
(+5 V or +15 V)
Tem perature
Range
P ackage
D escription
Model
DAC8248AW2 ±1/2 LSB
±1 LSB
±1 LSB
±2 LSB
±4 LSB
±4 LSB
±4 LSB
±4 LSB
–55°C to +125°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
24-Pin Cerdip
24-Pin Cerdip
DAC8248EW
DAC8248GP
DAC8248FW
DAC8248HP
DAC8248FP
±1/2 LSB
±1/2 LSB
±1 LSB
±1 LSB
±1 LSB
24-Pin Plastic DIP
24-Pin Cerdip
24-Pin Plastic DIP
24-Pin Plastic DIP
24-Pin SOL
–40°C to +85°C
0°C to +70°C
DAC8248HS3 ±1 LSB
NOT ES
1Burn-in is available on commercial and industrial temperature range parts in cerdip, plastic DIP, and T O-can packages.
2For devices processed in total compliance to MIL-ST D-883, add/883 after part number. Consult factory for 883 data sheet.
3For availability and burn-in information on SO and PLCC packages, contact your local sales office.
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the DAC8248 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–4–
DAC8248
D ICE CH ARACTERISTICS
11. AGND
12. IOUTA
13. RFB A
13. NC
14. DB1
15. DB0(LSB)
16. RESET
17. LSB/ MSB
14. VREF A
15. DGND
16. DB7(MSB)
18. DAC A/ DAC B
19. LDAC
20. WR
17. DB6
18. DB5
19. DB4
10. DB3
11. DB2
12. NC
21. VDD
22. VREF B
23. RFB B
24. IOUT B
SUBSTRATE (DIE BACKSIDE) IS INTERNALLY
CONNECTED TO VDD
.
Die Size 0.124 × 0.132 inch, 16,368 sq. m ils
(3.15 × 3.55 m m , 10.56 sq. m m )
WAFER TEST LIMITS @ V = +5 V or +15 V, VREF A = VREF B = +10 V, VOUT A = VOUT B = 0 V; AGND = DGND = 0 V; T = 25؇C.
DD
A
D AC8248G
Lim it
P aram eter
Sym bol
Conditions
Units
Relative Accuracy
INL
DNL
GFSE
Endpoint Linearity Error
±1
±1
±4
LSB max
LSB max
LSB max
Differential Nonlinearity
Full-Scale Gain Error1
Output Leakage
All Grades are Guaranteed Monotonic
Digital Inputs = 1111 1111 1111
Digital Inputs = 0000 0000 0000
Pads 2 and 24
(IOUT A, IOUT B
)
ILKG
±50
nA max
Input Resistance
(VREF A, VREF B
REF A, VREF B Input
Resistance Match
)
RREF
∆RREF
RREF
VINH
Pads 4 and 22
8/15
kΩ min/kΩ max
V
±1
2.4
13.5
0.8
1.5
±1
2
% max
V min
V min
V max
V max
µA max
mA max
mA max
Digital Input High
VDD = +5 V
VDD = +15 V
VDD = +5 V
VDD = +15 V
VIN = 0 V or VDD; VINL or VINH
All Digital Inputs VINL or VINH
All Digital Inputs 0 V or VDD
Digital Input Low
VINL
Digital Input Current
Supply Current
IIN
IDD
0.1
DC Supply Rejection
(∆Gain/∆VDD
)
PSR
∆VDD = ±5%
0.002
%/% max
NOT ES
1Measured using internal RFB A and RFB B
.
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
REV. B
–5–
DAC8248–Typical Performance Characteristics
Channel-to-Channel Matching (DAC
A & B are Superim posed)
Differential Nonlinearity vs. VREF
Differential Nonlinearity vs. VREF
Nonlinearity vs. VREF
Nonlinearity vs. VREF
Nonlinearity vs. VDD
Absolute Gain Error Change vs. VREF
Nonlinearity vs. Code (DAC A & B
are Superim posed)
Nonlinearity vs. Code at TA = –55°C,
+25°C, +125°C for DAC A & B
(All Superim posed)
REV. B
–6–
DAC8248
Full-Scale Gain Error vs. Tem perature
Logic Input Threshold Voltage
vs. Supply Voltage (VDD
Supply Current vs. Tem perature
)
Supply Current vs. Logic Input Voltage
Multiplying Mode Frequency Response vs. Digital Code
Output Leakage Current vs. Tem perature
Analog Crosstalk vs. Frequency
REV. B
–7–
DAC8248
Four Cycle Update
Five Cycle Update
Write Tim ing Cycle Diagram
P ARAMETER D EFINITIO NS
GENERAL CIRCUIT D ESCRIP TIO N
RESO LUTIO N (N)
CO NVERTER SECTIO N
T he resolution of a DAC is the number of states (2n) that the
full-scale range (FSR) is divided (or resolved) into; where n is
equal to the number of bits.
T he DAC8248 incorporates two multiplying 12-bit current out-
put CMOS digital-to-analog converters on one monolithic chip.
It contains two highly stable thin-film R-2R resistor ladder net-
works, two 12-bit DAC registers, two 8-bit input registers, and
two 4-bit input registers. It also contains the DAC control logic
circuitry and 24 single-pole, double-throw NMOS transistor
current switches.
RELATIVE ACCURACY (INL)
Relative accuracy, or integral nonlinearity, is the maximum de-
viation of the analog output (from the ideal) from a straight line
drawn between the end points. It is expressed in terms of least
significant bit (LSB), or as a percent of full scale.
Figure 1 shows a simplified circuit for the R-2R ladder and tran-
sistor switches for a single DAC. R is typically 11 kΩ. T he tran-
sistor switches are binarily scaled in size to maintain a constant
voltage drop across each switch. Figure 2 shows a single NMOS
transistor switch.
D IFFERENTIAL NO NLINEARITY (D NL)
Differential nonlinearity is the worst case deviation of any adja-
cent analog output from the ideal 1 LSB step size. T he devia-
tion of the actual “step size” from the ideal step size of 1 LSB is
called the differential nonlinearity error or DNL. DACs with
DNL greater than ±1 LSB may be nonmonotonic. ±1/2 LSB
INL guarantees monotonicity and ±1 LSB maximum DNL.
GAIN ERRO R (G FSE
)
Gain error is the difference between the actual and the ideal
analog output range, expressed as a percent of full-scale or in
terms of LSB value. It is the deviation in slope of the DAC
transfer characteristic from ideal.
Refer to PMI 1990/91 Data Book, Section 11, for additional
digital-to-analog converter definitions.
Figure 1. Sim plified Single DAC Circuit Configuration.
(Switches Are Shown For All Digital Inputs at Zero)
REV. B
–8–
DAC8248
D IGITAL SECTIO N
The DAC8248’s digital inputs are TTL compatible at VDD = +5 V
and CMOS compatible at VDD = +15 V. They were designed to
convert TTL and CMOS input logic levels into voltage levels that
will drive the internal circuitry. The DAC8248 can use +5 V
CMOS logic levels with VDD = +12 V; however, supply current
will increase to approximately 5 mA–6 mA.
Figure 3 shows the DAC’s digital input structure for one bit.
T his circuitry drives the DAC registers. Digital controls, φ and
φ, shown are generated from the DAC’s input control logic
circuitry.
Figure 2. N-Channel Current Steering Switch
T he binary-weighted currents are switched between IOUT and
AGND by the transistor switches. Selection between IOUT and
AGND is determined by the digital input code. It is important
to keep the voltage difference between IOUT and AGND termi-
nals as close to zero as practical to preserve data sheet limits. It
is easily accomplished by connecting the DAC’s AGND to the
noninverting input of an operational amplifier and IOUT to the
inverting input. T he amplifier’s feedback resistor can be elimi-
nated by connecting the op amp’s output directly to the DAC’s
RFB terminal (by using the DAC’s internal feedback resistor,
R
FB). T he amplifier also provides the current-to-voltage conver-
sion for the DAC’s output current.
Figure 3. Digital Input Structure For One Bit
T he output voltage is dependent on the DAC’s digital input
code and VREF, and is given by:
T he digital inputs are electrostatic-discharge (ESD) protected
with two internal distributed diodes as shown in Figure 3; they
are connected between VDD and DGND. Each input has a typi-
cal input current of less than 1 nA.
VOUT = VREF × D/4096
where D is the digital input code integer number that is between
0 and 4095.
T he digital inputs are CMOS inverters and draw supply current
when operating in their linear region. Using a +5 V supply, the
linear region is between +1.2 V to +2.8 V with current peaking
at +1.8 V. Using a +15 V supply, the linear region is from
+1.2 V to +12 V (current peaking at +3.9 V). It is recom-
mended that the digital inputs be operated as close to the power
supply voltage and DGND as is practically possible; this will
keep supply currents to a minimum. T he DAC8248 may be
operated with any supply voltage between the range of +5 V to
+15 V and still perform to data sheet limits.
T he DAC’s input resistance, RREF, is always equal to a constant
value, R. T his means that VREF can be driven by a reference
voltage or current, ac or dc (positive or negative). It is recom-
mended that a low temperature-coefficient external RFB resistor
be used if a current source is employed.
T he DAC’s output capacitance (COUT ) is code dependent and
varies from 90 pF (all digital inputs low) to 120 pF (all digital
inputs high).
T o ensure accuracy over the full operating temperature range,
permanently turned “ON” MOS transistor switches were in-
cluded in series with the feedback resistor (RFB) and the R-2R
ladder’s terminating resistor (see Figure 1). T he gates of these
NMOS transistors are internally connected to VDD and will be
turned “OFF” (open) if VDD is not applied. If an op amp is us-
ing the DAC’s RFB resistor to close its feedback loop, then VDD
must be applied before or at the same time as the op amp’s sup-
ply; this will prevent the op amp’s output from becoming “open
circuited” and swinging to either rail. In addition, some applica-
tions require the DAC’s ladder resistance to fall within a certain
range and are measured at incoming inspection; VDD must be
applied before these measurements can be made.
T he DAC8248’s 8-bit wide data port loads a 12-bit word in two
bytes: 8-bits then 4-bits (or 4-bits first then 8-bits, at users dis-
cretion) in a right justified data format. T his data is loaded into
the input registers with the LSB/MSB and WR control pins.
Data transfer from the input registers to the DAC registers can
be automatic. It can occur upon loading of the second data byte
into the input register, or can occur at a later time through a
strobed transfer using the LDAC control pin.
REV. B
–9–
DAC8248
Figure 4. Four Cycle Update Tim ing Diagram
Figure 5. Five Cycle Update Tim ing Diagram
REV. B
–10–
DAC8248
AUTO MATIC D ATA TRANSFER MO D E
Strobed data transfer separating data loading and transfer op-
erations serves two functions: the DAC output updating may be
more precisely controlled, and multiple DACs in a multiple
DAC system can be updated simultaneously.
Data may be transferred automatically from the input register to
the DAC register. T he first cycle loads the first data byte into
the input register; the second cycle loads the second data byte
and simultaneously transfers the full 12-bit data word to the
DAC register. It takes four cycles to load and transfer two com-
plete digital words for both DAC’s, see Figure 4 (Four Cycle
Update T iming Diagram) and the Mode Selection T able.
RESET
T he DAC8248 comes with a RESET pin that is useful in system
calibration cycles and/or during system power-up. All registers
are reset to zero when RESET is low, and latched at zero on the
rising edge of the RESET signal when WRITE is high.
STRO BED D ATA TRANSFER MO D E
Strobed data transfer allows the full 12-bit digital word to be
loaded into the input registers and transferred to the DAC regis-
ters at a later time. T his transfer mode requires five cycles: four
to load two new data words into both DACs, and the fifth to
transfer all data into the DAC registers. See Figure 5 (Five Cycle
Update T iming Diagram) and the Mode Selection T able.
INTERFACE CO NTRO L LO GIC
T he DAC8248’s control logic is shown in Figure 6. T his cir-
cuitry interfaces with the system bus and controls the DAC
functions.
Figure 6. Input Control Logic
MO D E SELECTIO N TABLE
D IGITAL INP UTS
REGISTER STATUS
D AC A
Input Register
D AC B
Input Register
D AC
D AC
DAC A/B WR
LSB/MSB RESET LDAC LSB
MSB
Register
LSB
MSB
Register
L
L
L
L
H
H
H
H
X
X
X
X
L
L
L
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
L
H
L
H
L
H
L
H
L
X
X
WR
WR
LAT
LAT
WR
LAT
WR
LAT
WR
LAT
WR
LAT
WR
LAT
LAT
LAT
LAT
WR
LAT
LAT
LAT
LAT
LAT
LAT
WR
WR
LAT
LAT
LAT
WR
LAT
WR
LAT
WR
LAT
WR
L
L
L
L
L
L
L
H
H
X
H
LAT
LAT
LAT
LAT
LAT
LAT
LAT
LAT
WR
LAT
LAT
LAT
LAT
LAT
LAT
L
WR
H
H
X
X
X
X
LAT
LAT
LAT
LAT
LAT
WR
LAT
WR
ALL REGIST ERS ARE RESET T O ZEROS
ZEROS ARE LAT CHED IN ALL REGIST ERS
g
L = Low, H = High, X = Don’t Care, WR = Registers Being Loaded, LAT = Registers Latched.
REV. B
–11–
DAC8248
Table I. Unipolar Binary Code Table (Refer to Figure 7)
Binary Num ber in
INTERFACE CO NTRO L LO GIC P IN FUNCTIO NS
LSB/MSB – (P IN 17) LEAST SIGNIFICANT BIT (Active
Low)/ MO ST SIGNIFICANT BIT (Active H igh). Selects
lower 8-bits (LSBs) or upper 4-bits (MSBs); either can be
loaded first. It is used with the WR signal to load data into the
input registers. Data is loaded in a right justified format.
D AC Register
Analog O utput, VO UT
(D AC A or D AC B)
MSB
LSB
4095
1111 1111 1111
1000 0000 0000
–VREF
DAC A/D AC B – (P IN 18) D AC SELECTIO N. Active low
for DAC A and Active High for DAC B.
4096
2048
4096
1
–VREF
= – VREF
WR – (P IN 20) WRITE – Active Low. Used with the LSB/
MSB signal to load data into the input registers, or Active High
to latch data into the input registers.
2
1
0000 0000 0001
0000 0000 0000
–VREF
0 V
4096
LDAC – (P IN 19) LO AD D AC. Used to transfer data sim-
ultaneously from DAC A and DAC B input registers to both
DAC output registers. T he DAC register becomes transparent
(activity on the digital inputs appear at the analog output) when
both WR and LDAC are low. Data is latched into the output
registers on the rising edge of LDAC.
NOT E
1 LSB = (2-12) (VREF)=
1
(VREF)
4096
Low temperature-coefficient (approximately 50 ppm/°C) resis-
tors or trimmers should be used. Maximum full-scale error
RESET – (P IN 16) – Active Low. Functions as a zero over-
ride; all registers are forced to zero when the RESET signal is
low. All registers are latched to zeros when the write signal is
high and RESET goes high.
without these resistors for the top grade device and VREF
=
±10 V is 0.024%, and 0.049% for the low grade. Capacitors C1
and C2 provide phase compensation to reduce overshoot and
ringing when high-speed op amps are used.
AP P LICATIO NS INFO RMATIO N
UNIP O LAR O P ERATIO N
Full-scale adjustment is achieved by loading the appropriate
DAC’s digital inputs with 1111 1111 1111 and adjusting R1 (or
R3 for DAC B) so that:
Figure 7 shows a simple unipolar (2-quadrant multiplication)
circuit using the DAC8248 and OP270 dual op amp (use two
OP42s for applications requiring higher speeds), and T able I
shows the corresponding code table. Resistors R1, R2, and R3,
R4 are used only if full-scale gain adjustments are required.
4095
VOUT = VREF
×
4096
Full-scale can also be adjusted by varying VREF voltage and
eliminating R1, R2, R3, and R4. Zero adjustment is performed by
Figure 7. Unipolar Configuration (2-Ouadrant Multiplication)
REV. B
–12–
DAC8248
Table II. Bipolar (O ffset Binary) Code Table
(Refer to Figure 8)
loading the appropriate DAC’s digital inputs with 0000 0000
0000 and adjusting the op amp’s offset voltage to 0 V. It is rec-
ommended that the op amp offset voltage be adjusted to less
than 10% of 1 LSB (244 µV), and over the operating tempera-
ture range of interest. T his will ensure the DAC’s monotonicity
and minimize gain and linearity errors.
Binary Num ber in
D AC Register
Analog O utput, VO UT
(D AC A or D AC B)
MSB
LSB
2047
BIP O LAR O P ERATIO N
1111 1111 1111
+VREF
2048
T he bipolar (offset binary) 4-quadrant configuration using the
DAC8248 is shown in Figure 8, and the corresponding code is
shown in T able II. T he circuit makes use of the OP470, a quad
op amp (use four OP42s for applications requiring higher
speeds).
1
1000 0000 0001
1000 0000 0000
+VREF
2048
0 V
1
The full-scale output voltage may be adjusted by varying VREF or
the value of R5 and R8, and thus eliminating resistors R1, R2,
R3, and R4. If resistors R1 through R4 are omitted, then R5, R6,
R7 (R8, R9, and R10 for DAC B) should be ratio-matched to
0.01% to keep gain error within data sheet specifications. The re-
sistors should have identical temperature-coefficients if operating
over the full temperature range.
0111 1111 1111
0000 0000 0000
–VREF
2048
2048
–VREF
2048
NOT E:
1
1 LSB=(2–11)(VREF) =
(VREF)
2048
Zero and full-scale are adjusted in one of two ways and are at
the users discretion. Zero-output is adjusted by loading the ap-
propriate DAC’s digital inputs with 1000 0000 0000 and vary-
ing R1 (R3 for DAC B) so that VOUT A (or VOUT B) equals 0 V.
If R1, R2 (R3, R4 for DAC B) are omitted, then zero output
can be adjusted by varying R6, R7 ratios (R9, R10 for DAC B).
Full-scale is adjusted by loading the appropriate DAC’s digital
inputs with 1111 1111 1111 and varying R5 (R8 for DAC B).
SINGLE SUP P LY O P ERATIO N
CURRENT STEERING MO D E
Because the DAC8248’s R-2R resistor ladder terminating resis-
tor is internally connected to AGND, it lends itself well for
single supply operation in the current steering mode configura-
tion. T his means that AGND can be raised above system
Figure 8. Bipolar Configuration (4-Quadrant Multiplication)
–13–
REV. B
DAC8248
ground as shown in Figure 9. T he output voltage will be be-
tween +5 V and +10 V depending on the digital input code.
T he output expression is given by:
AP P LICATIO NS TIP S
GENERAL GRO UND MANAGEMENT
Grounding techniques should be tailored to each individual sys-
tem. Ground loops should be avoided, and ground current paths
should be as short as possible and have a low impedance.
VOUT = VOS × (D/4096)(VOS
)
where VOS = Offset Reference Voltage (+5 V in Figure 9)
D = Decimal Equivalent of the Digital Input Word
T he DAC8248’s AGND and DGND pins should be tied to-
gether at the device socket to prevent digital transients from ap-
pearing at the analog output. T his common point then becomes
the single ground point connection. AGND and DGND is then
brought out separately and tied to their respective power supply
grounds. Ground loops can be created if both grounds are tied
together at more than one location, i.e., tied together at the de-
vice and at the digital and analog power supplies.
VO LTAGE SWITCH ING MO D E
Figure 10 shows the DAC8248 in another single supply configu-
ration. T he R-2R ladder is used in the voltage switching mode
and functions as a voltage divider. T he output voltage (at the
VREF pin) exhibits a constant impedance R (typically 11 kΩ) and
must be buffered by an op amp. T he RFB pins are not used and
are left open. T he reference input voltage must be maintained
within +1.25 V of AGND, and VDD between +12 V and +15 V;
this ensures that device accuracy is preserved.
PC board ground plane can be used for the single point ground
connection should the connections not be practical at the device
socket. If neither of these connections are practical or allowed,
then the device should be placed as close as possible to the sys-
tems single point ground connection. Back-to-back Schottky di-
odes should then be connected between AGND and DGND.
T he output voltage expression is given by:
VOUT = VREF (D/4096)
where D = Decimal Equivalent of the Digital Input Word
P O WER SUP P LY D ECO UP LING
Power supplies used with the DAC8248 should be well filtered
and regulated. Local supply decoupling consisting of a 1 µF to
10 µF tantalum capacitor in parallel with a 0.1 µF ceramic is
highly recommended. T he capacitors should be connected be-
tween the VDD and DGND pins and at the device socket.
Figure 9. Single Supply Operation (Current Switching Mode)
REV. B
–14–
DAC8248
Figure 10. Single Supply Operation (Voltage Switching Mode)
Figure 11. Digitally-Program m able Window Detector (Upper/Lower Lim it Detector)
MICRO P RO CESSO R INTERFACE CIRCUITS
T he DAC8248s versatile loading structure allows direct inter-
face to an 8-bit microprocessor. Its simplicity reduces the num-
ber of required glue logic components. Figures 12 and 13 show
the DAC8248 interface configurations with the MC6809 and
MC68008 microprocessors.
REV. B
–15–
Figure 13. DAC8248 to MC68008 Interface
Figure 12. DAC8248 to MC6809 Interface
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
24-Lead Cerdip
(Q-24)
0.005 (0.13) MIN
0.098 (2.49) MAX
24
13
0.310 (7.87)
0.220 (5.59)
1
12
0.320 (8.13)
0.290 (7.37)
PIN 1
0.060 (1.52)
0.015 (0.38)
1.280 (32.51) MAX
0.200 (5.08)
MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
0.070 (1.78)
0.030 (0.76)
0.100 (2.54)
BSC
15°
0°
24 Lead SO L
24-Lead P lastic D IP
(N-24)
(R-24)
0.6141 (15.60)
0.5985 (15.20)
1.275 (32.30)
1.125 (28.60)
24
1
13
12
0.280 (7.11)
0.240 (6.10)
24
13
12
0.325 (8.25)
0.300 (7.62)
0.195 (4.95)
0.115 (2.93)
PIN 1
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
1
0.150
(3.81)
MIN
0.200 (5.05)
0.125 (3.18)
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.015 (0.381)
0.008 (0.204)
0.0291 (0.74)
0.0098 (0.25)
x 45°
0.100 (2.54)
BSC
0.022 (0.558)
0.014 (0.356)
0.070 (1.77) SEATING
PLANE
0.045 (1.15)
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0118 (0.30)
0.0040 (0.10)
SEATING
PLANE
0.0125 (0.32)
0.0138 (0.35)
0.0091 (0.23)
–16–
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