DAC8408AT [ADI]
Quad 8-Bit Multiplying CMOS D/A Converter with Memory; 4个8位乘法CMOS D / A转换器，具有记忆
| 型号： | DAC8408AT |
| 厂家： | 
ADI |
| 描述： | Quad 8-Bit Multiplying CMOS D/A Converter with Memory |
| 文件： | 总16页 (文件大小：219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad 8-Bit Multiplying CMOS
D/A Converter with Memory
a
DAC8408
FEATURES
A common 8-bit T T L/CMOS compatible input port is used to
Four DACs in a 28 Pin, 0.6 Inch Wide DIP or 28-Pin J EDEC load data into any of the four DAC data-latches. Control lines
Plastic Chip Carrier
؎1/ 4 LSB Endpoint Linearity
Guaranteed Monotonic
DS1, DS2, and A/B determine which DAC will accept data.
Data loading is similar to that of a RAMs write cycle. Data can
be read back onto the same data bus with control line R/W. T he
DAC8408 is bus compatible with most 8-bit microprocessors,
including the 6800, 8080, 8085, and Z80. T he DAC8408 oper-
ates on a single +5 volt supply and dissipates less than 20 mW.
T he DAC8408 is manufactured using PMI’s highly stable,
thin-film resistors on an advanced oxide-isolated, silicon-gate,
CMOS process. PMI’s improved latch-up resistant design elimi-
nates the need for external protective Schottky diodes.
DACs Matched to Within 1%
Microprocessor Com patible
Read/ Write Capability (w ith Mem ory)
TTL/ CMOS Com patible
Four-Quadrant Multiplication
Single-Supply Operation (+5 V)
Low Pow er Consum ption
Latch-Up Resistant
O RD ERING INFO RMATIO N1
Available In Die Form
APPLICATIONS
Tem perature
Range
P ackage
D escription
Voltage Set Points in Autom atic Test Equipm ent
System s Requiring Data Access for Self-Diagnostics
Industrial Autom ation
Multichannel Microprocessor-Controlled System s
Digitally Controlled Op Am p Offset Adjustm ent
Process Control
Model
INL
D NL
DAC8408GP
DAC8408ET
±1/4 LSB ±1/2 LSB 0°C to +70°C
±1/4 LSB ±1/2 LSB –40°C to +85°C
28-Pin Plastic DIP
28-Pin Cerdip
DAC8408AT 2 ±1/4 LSB ±1/2 LSB –55°C to +125°C 28-Pin Cerdip
DAC8408FT
±1/2 LSB ±1 LSB
–40°C to +85°C
–55°C to +125°C 28-Pin Cerdip
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
28-Pin Cerdip
DAC8408BT 2 ±1/2 LSB ±1 LSB
DAC8408FPC 3 ±1/2 LSB ±1 LSB
28-Contact PLCC
28-Pin SOL
28-Pin Plastic DIP
Digital Attenuators
DAC8408FS
DAC8408FP
±1/2 LSB ±1 LSB
±1/2 LSB ±1 LSB
NOT ES
1Burn-in is available on commercial and industrial temperature range parts
in cerdip, plastic DIP, and T O-can packages. For outline information see Pack-
age Information section.
GENERAL D ESCRIP TIO N
T he DAC8408 is a monolithic quad 8-bit multiplying digital-to-
analog CMOS converter. Each DAC has its own reference input,
feedback resistor, and onboard data latches that feature
read/write capability. T he readback function serves as memory
for those systems requiring self-diagnostics.
2For devices processed in total compliance to MIL-ST D-883, add /883 after
part number. Consult factory for 883 data sheet.
3For availability and burn-in information on SO and PLCC packages, contact
your local sales office.
FUNCTIO NAL BLO CK D IAGRAM
DAC8408
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
DAC8408
ELECTRICAL CHARACTERISTICS (@ V = +5 V; V = ؎10 V; V A, B, C, D = 0 V; T = –55؇C to +125؇C apply for
DD
REF
OUT
A
DAC8408AT/BT, T = –40؇C to +85؇C apply for DAC8408ET/FT/FP/FPC/FS; T = 0؇C to +70؇C apply for DAC8408GP, unless otherwise noted.
A
A
Specifications apply for DAC A, B, C, & D.)
D AC8408
Typ
P aram eter
Sym bol
Conditions
Min
Max
Units
ST AT IC ACCURACY
Resolution
N
INL
8
Bits
Nonlinearity1, 2
DAC8408A/E/G
DAC8408B/F/H
DAC8408A/E/G
DAC8408B/F/H
(Using Internal RFB
±1/4
±1/2
±1/2
±1
±1
±40
LSB
LSB
LSB
LSB
LSB
ppm/°C
Differential
Nonlinearity
DNL
Gain Error
GFSE
T CGFS
)
Gain T empco3, 6
Power Supply Rejection
(∆VDD = ±10%)
±2
PSR
ILKG
0.001
%FSR/%
IOUT 1A
, , ,
B C D
Leakage Current13
TA =+25°C
TA = Full T emperature Range
±30
±100
nA
nA
REFERENCE INPUT
Input Voltage Range
Input Resistance Match4
Input Resistance
±20
±1
14
V
%
kΩ
RA, B, C, D
RIN
6
10
DIGIT AL INPUT S
Digital Input Low
Digital Input High
Input Current5
VIL
VIH
0.8
V
V
µA
2.4
TA = +25°C
±0.01 ±1.0
IIN
CIN
TA = Full T emperature Range
±10.0 µA
Input Capacitance6
8
pF
DAT A BUS OUT PUT S
Digital Output Low
Digital Output High
VOL
VOH
ILKG
16 mA Sink
400 µA Source
TA = +25°C
0.4
V
V
µA
4
Output Leakage Current
±0.005 ±1.0
TA = Full T emperature Range
±0.075 ±10.0 µA
DAC OUT PUT S6
Propagation Delay7
Settling T ime11,12
Output Capacitance
tPD
tS
COUT
150
190
180
250
30
ns
ns
pF
pF
dB
DAC Latches All “0s”
DAC Latches All “1s”
(20 Vp-p @ F = 100 kHz)
50
AC Feedthrough
FT
54
SWIT CHING CHARACT ERIST ICS6, 10
Write to Data Strobe T ime
tDS1 or
tDS2
tDSU
TA = +25°C
TA = Full T emperature Range
TA = +25°C
90
145
150
175
10
0
0
0
0
220
350
320
430
200
270
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Valid to Strobe Set-Up T ime
T
A = Full T emperature Range
Data Valid to Strobe Hold T ime
DAC Select to Strobe Set-Up T ime
DAC Select to Strobe Hold T ime
Write Select to Strobe Set-Up T ime
Write Select to Strobe Hold T ime
Read to Data Strobe Width
tDH
tAS
tAH
tWSU
tWH
tRDS
TA = +25°C
A = Full T emperature Range
TA = +25°C
A = Full T emperature Range
TA = +25°C
T
Data Strobe to Output Valid T ime
Output Data to Deselect T ime
tCO
T
tOT D
T
A = Full T emperature Range
Read Select to Strobe Set-Up T ime
Read Select to Strobe Hold T ime
tRSU
tRH
0
Specifications subject to change without notice.
–2–
REV. A
DAC8408
@ V = +5 V; V = ؎10 V; V A, B, C, D = 0 V; T = –55؇C to +125؇C apply for
ELECTRICAL CHARACTERISTICS
DD
REF
OUT
A
DAC8408AT/BT, T = –40؇C to +85؇C apply for DAC8408ET/FT/FP/FPC/FS; T = 0؇C to +70؇C apply for DAC8408GP, unless otherwise noted.
A
A
Specifications apply for DAC A, B, C, & D. Continued
D AC8408
Typ
P aram eter
Sym bol
Conditions
Min
Max
Units
POWER SUPPLY
Voltage Range
VDD
IDD
IDD
4.5
5.5
50
1.0
1.5
V
Supply Current8
Supply Current9
µA
mA
mA
TA = +25°C
TA = Full T emperature Range
7From Digital Input to 90% of final analog output current.
NOT ES
1T his is an end-point linearity specification.
8All Digital Inputs “0” or VDD
.
2Guaranteed to be monotonic over the full operating temperature range.
3ppm/°C of FSR (FSR = Full Scale Range = VREF-1 LSB.)
4Input Resistance T emperature Coefficient = +300ppm/°C.
5Logic Inputs are MOS gates. T ypical input current at +25°C Is less than 10 nA.
6Guaranteed by design.
9All Digital Inputs VIH or VIL
10See T iming Diagram.
.
11Digital Inputs = 0 V to VDD or VDD to 0 V.
12Extrapolated: tS (1/2 LSB) = tPD + 6.2τ where τ = the measured first time con-
stant of the final RC decay.
13All Digital Inputs = 0 V; VREF = +10 V.
Specifications subject to change without notice.
P IN CO NNECTIO NS
DAC8408
TOP VIEW
(Not to Scale)
ABSO LUTE MAXIMUM RATINGS
(TA = +25°C, unless otherwise noted.)
P ackage Type
JA
*
JC
Units
28-Pin Hermetic DIP (T )
28-Pin Plastic DIP (P)
28-Pin SOL (S)
55
53
68
66
10
27
23
29
°C/W
°C/W
°C/W
°C/W
VDD to IOUT 2A, IOUT 2B, IOUT 2C, IOUT
. . . . . . . . . . 0 V, +7 V
2D
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +7 V
IOUT 1A, IOUT
,
1B
28-Contact PLCC (PC)
I
OUT 1C, IOUT 1D to DGND . . . . . . . . . –0.3 V to VDD +0.3 V
R
FBA, RFBB, RFBC, RFBD to IOUT . . . . . . . . . . . . . . . . . ±25 V
*θJA is specified for worst case mounting conditions, i.e., θJA is specified for
device in socket for cerdip and P-DIP packages; θJA is specified for device
soldered to printed circuit board for SOL and PLCC packages.
I
OUT 2A, IOUT 2B
,
I
OUT 2C, IOUT 2D to DGND . . . . . . . . . –0.3 V to VDD + 0.3 V
DB0 through DB7 to DGND . . . . . . . . –0.3 V to VDD + 0.3 V
Control Logic
Input Voltage to DGND . . . . . . . . . . –0.3 V + VDD + 0.3 V
CAUTIO N
1. Do not apply voltages higher than VDD +0.3 V or less than
–0.3 V potential on any terminal except VREF and RFB
.
VREFA, VREFB, VREFC, VREFD to
I
OUT 2A, IOUT 2B, IOUT 2C, IOUT 2D . . . . . . . . . . . . . . . . ±25 V
2. T he digital control inputs are diode-protected; however,
permanent damage may occur on unconnected inputs from
high energy electrostatic fields. Keep in conductive foam at
all times until ready to use.
Operating T emperature Range
Commercial Grade (GP) . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial Grade (ET , FT , FP, FPC, FS) . –40°C to +85°C
Military Grade (AT , BT ) . . . . . . . . . . . . . . –55°C to +125°C
Junction T emperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Storage T emperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead T emperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
3. Use proper antistatic handling procedures.
4. Absolute Maximum Ratings apply to both packaged devices
and DICE. Stresses above those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the device.
REV. A
–3–
DAC8408
Burn-in Circuit
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the DAC8408 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
D ICE CH ARACTERISTICS
1. VDD
2. VREF
15. DB6
16. DB7 (MSB)
A
3. RFB
4. IOUT 1A
A
17. A/B
18. R/W
5. IOUT 2A/IOUT 2B
6. IOUT 1B
7. RFB
8. VREF
19. DS1
20. DS2
B
B
21. VREF
22. RFB
D
D
9. DB0 (LSB)
10. DB1
11. DB2
23. IOUT 1D
24. IOUT 2C/IOUT 2D
25. IOUT 1C
12. DB3
13. DB4
14. DB5
26. RFB
27. VREF
28. DGND
C
C
DIE SIZE 0.130 × 0.124 inch, 16,120 sq. m ils
(3.30 × 3.15 m m , 10.4 sq. m m )
REV. A
–4–
DAC8408
at V = +5 V; V = ؎10 V; V A, B, C, D = 0 V; T = +25؇C, unless otherwise noted. Specifications apply for
DD
REF
OUT
A
WAFER TESTLIMITS
DAC A, B, C, & D.
D AC8408G
Lim its
P aram eter
Sym bol
Conditions
Units
ST AT IC ACCURACY
Resolution
N
8
Bits min
Nonlinearity1
INL
DNL
GFSE
PSR
±1/2
±1
±1
LSB max
LSB max
LSB max
%FSR/% max
Differential Nonlinearity
Gain Error
Using Internal RFB
Using Internal RFB
Power Supply Rejection
0.001
(∆VDD = ±10%)2
IOUT 1A, B, C, D Leakage Current ILKG
All Digital Inputs = 0 V
±30
nA max
VREF = +10 V
REFERENCE INPUT
Reference Input
RIN
RIN
6/14
kΩ min/max
Resistance3
Input Resistance Match
±1
% max
DIGIT AL INPUT S
Digital Input Low
Digital Input High
Input Current4
VIL
VIH
IIN
0.8
2.4
±1.0
V max
V min
µA max
DAT A BUS OUT PUT S
Digital Output Low
Digital Output High
VOL
VOH
ILKG
1.6 mA Sink
400 µA Source
0.4
4
±1.0
V max
V min
µA max
Output Leakage Current
POWER SUPPLY
Supply Current5
Supply Current6
IDD
IDD
50
1.0
µA max
mA max
NOT ES
1T his is an endpoint linearity specification.
2FSR is Full Scale Range = VREF –1 LSB.
3Input Resistance T emperature Coefficient approximately equals +300 ppm/°C.
4Logic inputs are MOS gates.T ypical input current at +25°C is less than 10 nA.
5All Digital Inputs are either “0” or VDD
.
6All Digital Inputs are either VIH or VIL
.
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
REV. A
–5–
DAC8408
TYP ICAL P ERFO RMANCE CH ARACTERISTICS
Analog Crosstalk vs. Frequency
Supply Current vs. Logic Level
REV. A
–6–
DAC8408
Tim ing Diagram
P ARAMETER D EFINITIO NS
RESO LUTIO N
AC FEED TH RO UGH ERRO R
T his is the error caused by capacitance coupling from VREF to
the DAC output with all switches off.
Resolution is the number of states (2n) that the full-scale range
(FSR) of a DAC is divided (or resolved) into.
SETTLING TIME
NO NLINEARITY
Nonlinearity (Relative Accuracy) is a measure of the maximum
deviation from a straight line passing through the end-points of
the DAC transfer function. It is measured after adjusting for
ideal zero and full-scale and is expressed in LSB, %, or ppm of
full-scale range.
Settling T ime is the time required for the output function of the
DAC to settle to within 1/2 LSB for a given digital input signal.
P RO P AGATIO N D ELAY
T his is a measure of the internal delays of the DAC. It is defined
as the time from a digital input change to the analog output cur-
rent reaching 90% of its final value.
D IFFERENTIAL NO NLINEARITY
Differential Nonlinearity is the worst case deviation of any adja-
cent analog outputs from the ideal 1 LSB step size. A specified
differential nonlinearity of ±1 LSB maximum over the operating
temperature range ensures monotonicity.
CH ANNEL-TO -CH ANNEL ISO LATIO N
T his is the portion of input signal that appears at the output of a
DAC from another DAC’s reference input. It is expressed as a
ratio in dB.
GAIN ERRO R
D IGITAL CRO SSTALK
Gain Error (full-scale error) is a measure of the output error be-
tween the ideal and actual DAC output. T he ideal full-scale
output is VREF –1 LSB.
Digital Crosstalk is the glitch energy transferred to the output of
one DAC due to a change in digital input code from other
DACs. It is specified in nVs.
O UTP UT CAP ACITANCE
Output Capacitance is that capacitance between IOUT 1A, IOUT 1B
OUT 1C, or IOUT 1D and AGND.
,
I
REV. A
–7–
DAC8408
CIRCUIT INFO RMATIO N
T he DAC8408 combines four identical 8-bit CMOS DACs
onto a single monolithic chip. Each DAC has its own reference
input, feedback resistor, and on-board data latches. It also fea-
tures a read/write function that serves as an accessible memory
location for digital-input data words. T he DAC’s three-state
readback drivers place the data word back onto the data bus.
D /A CO NVERTER SECTIO N
Each DAC contains a highly stable, silicon-chromium, thin-film,
R-2R resistor ladder network and eight pairs of current steering
switches. T hese switches are in series with each ladder resistor
and are single-pole, double-throw NMOS transistors; the gates
of these transistors are controlled by CMOS inverters. Figure 1
shows a simplified circuit of the R-2R resistor ladder section,
and Figure 2 shows an approximate equivalent switch circuit.
T he current through each resistor leg is switched between IOUT 1
and IOUT 2. T his maintains a constant current in each leg, re-
gardless of the digital input logic states.
Figure 1. Sim plified D/A Circuit of DAC8408
Each transistor switch has a finite “ON” resistance that can in-
troduce errors to the DAC’s specified performance. T hese resis-
tances must be accounted for by making the voltage drop across
each transistor equal to each other. T his is done by binarily-
scaling the transistor’s “ON” resistance from the most signifi-
cant bit (MSB) to the least significant bit (LSB). With 10 volts
applied at the reference input, the current through the MSB
switch is 0.5 mA, the next bit is 0.25 mA, etc.; this maintains a
constant 10 mV drop across each switch and the converter’s ac-
curacy is maintained. It also results in a constant resistance ap-
pearing at the DAC’s reference input terminal; this allows the
DAC to be driven by a voltage or current source, ac or dc of
positive or negative polarity.
Figure 2. N-Channel Current Steering Switch
Shown in Figure 3 is an equivalent output circuit for DAC A.
T he circuit is shown with all digital inputs high. T he leakage
current source is the combination of surface and junction leak-
ages to the substrate. T he 1/256 current source represents the
constant 1-bit current drain through the ladder terminating re-
sistor. T he situation is reversed with all digital inputs low, as
shown in Figure 4. T he output capacitance is code dependent,
and therefore, is modulated between the low and high values.
Figure 3. Equivalent DAC Circuit (AII Digital Inputs HIGH)
REV. A
–8–
DAC8408
INTERFACE LO GIC SECTIO N
D AC O per ating Modes
• All DACs in HOLD MODE.
• DAC A, B, C, or D individually selected (WRIT E MODE).
• DAC A, B, C, or D individually selected (READ MODE).
• DACs A and C simultaneously selected (WRIT E MODE).
• DACs B and D simultaneously selected (WRIT E MODE).
D AC Selection: Control inputs, DS1, DS2, and A/B select
which DAC can accept data from the input port (see Mode Se-
lection T able).
Mode Selection: Control inputs DS and R/W control the oper-
ating mode of the selected DAC.
Figure 4. Equivalent DAC Circuit (AII Digital Inputs LOW)
Wr ite Mode: When the control inputs DS and R/W are both
low, the selected DAC is in the write mode. T he input data
latches of the selected DAC are transparent, and its analog out-
put responds to activity on the data inputs DB0–DB7.
D IGITAL SECTIO N
Figure 5 shows the digital input/output structure for one bit.
T he digital WR, WR, and RD controls shown in the figure are
internally generated from the external A/B, R/W, DS1, and DS2
signals. T he combination of these signals decide which DAC is
selected. T he digital inputs are CMOS inverters, designed such
that T T L input levels (2.4 V and 0.8 V) are converted into
CMOS logic levels. When the digital input is in the region of 1.2 V
to 1.8 V, the input stages operate in their linear region and draw
current from the +5 V supply (see T ypical Supply Current vs.
Logic Level curve on page 6). It is recommended that the digital
input voltages be as close to VDD and DGND as is practical in
order to minimize supply currents. T his allows maximum sav-
ings in power dissipation inherent with CMOS devices. T he
three-state readback digital output drivers (in the active mode)
provide T T L-compatible digital outputs with a fan-out of one
T T L load. T he three state digital readback leakage-current is
typically 5 nA.
H old Mode: T he selected DAC latch retains the data that was
present on the bus line just prior to DS or R/W going to a high
state. All analog outputs remain at the values corresponding to
the data in their respective latches.
Read Mode: When DS is low and R/W is high, the selected
DAC is in the read mode, and the data held in the appropriate
latch is put back onto the data bus.
MO D E SELECTIO N TABLE
Control Logic
D S1
D S2 A/B
R/W
Mode
D AC
L
L
H
H
H
H
L
L
H
L
H
L
L
L
L
L
WRIT E
WRIT E
WRIT E
WRIT E
A
B
C
D
L
L
H
H
H
H
L
L
H
L
H
L
H
H
H
H
READ
READ
READ
READ
A
B
C
D
L
L
L
L
H
L
L
L
WRIT E
WRIT E
A&C
B&D
H
L
L
H
L
L
X
H
L
X
H
H
HOLD
HOLD
HOLD
A/B/C/D
A/B/C/D
A/B/C/D
Figure 5. Digital Input/Output Structure
L = Low State, H = High State, X = Irrelevant
REV. A
–9–
DAC8408
BASIC AP P LICATIO NS
are used only if gain error adjustments are required and range
between 50 Ω and 1000 Ω. Resistors R21, R22, R23, and R24
will range betwen 50 Ω and 500 Ω. If these resistors are used, it
is essential that resistor pairs R9–R13, R10–R14, R11–R15,
R12–R16 are matched both in value and tempco. T hey should
be within 0.01%; wire wound or metal foil types are preferred
for best temperature coefficient matching. T he circuits of Figure
6 and 7 can either be used as a fixed reference D/A converter, or
as an attenuator with an ac input voltage.
Some basic circuit configurations are shown in Figures 6 and 7.
Figure 6 shows the DAC8408 connected in a unipolar configu-
ration (2-Quadrant Multiplication), and T able I shows the Code
T able. Resistors R1, R2, R3, and R4 are used to trim full scale
output. Full-scale output voltage = VREF –1 LSB = VREF (1–2–8)
or VREF × (255/256) with all digital inputs high. Low tempera-
ture coefficient (approximately 50 ppm/°C) resistors or trim-
mers should be selected if used. Full scale can also be adjusted
using VREF voltage. T his will eliminate resistors R1, R2, R3, and
R4. In many applications, R1 through R4 are not required, and
the maximum gain error will then be that of the DAC.
Table I. Unipolar Binary Code Table (Refer to Figure 6)
D AC D ata Input
Each DAC exhibits a variable output resistance that is code-
dependent. T his produces a code-dependent, differential non-
linearity term at the amplifier’s output which can have a maxi-
mum value of 0.67 × the amplifier’s offset voltage. T his differ-
ential nonlinearity term adds to the R-2R resistor ladder differ-
ential-nonlinearity; the output may no longer be monotonic. T o
maintain monotonicity and minimize gain and linearity errors, it
is recommended that the op amp offset voltage be adjusted to
less than 10% of 1 LSB (1 LSB = 2–8 × VREF or 1/256 × VREF),
or less than 3.9 mV over the operating temperature range. Zero-
scale output voltage (with all digital inputs low) may be adjusted
using the op amp offset adjustment. Capacitors C1, C2, C3,
and C4 provide phase compensation and help prevent overshoot
and ringing when using high speed op amps.
MSB
LSB
Analog O utput
255
1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
–VREF
256
129
–VREF
256
128
–VIN
–VREF
–VREF
–VREF
–VREF
=
256
127
2
256
1
256
0
= 0
256
Figure 7 shows the recommended circuit configuration for the
bipolar operation (4-quadrant multiplication), and Table II shows
the Code T able. T rimmer resistors R17, R18, R19, and R20
NOT E
1
1 LSB = (2–8) (VREF) =
(VREF)
256
Figure 6. Quad DAC Unipolar Operation (2-Quadrant Multiplication)
REV. A
–10–
DAC8408
Figure 7. Quad DAC Bipolar Operation (4-Quadrant Multiplication)
Table II. Bipolar (O ffset Binary) Code Table
(Refer to Figure 7)
AP P LICATIO N H INTS
General Ground Managem ent: AC or transient voltages be-
tween AGND and DGND can appear as noise at the DAC8408’s
analog output. Note that in Figures 5 and 6, IOUT 2A/IOUT 2B and
D AC D ata Input
MSB LSB
Analog O utput
(D AC A O R D AC B)
I
OUT 2C/IOUT 2D are connected to AGND. T herefore, it is rec-
127
ommended that AGND and DGND be tied together at the
DAC8408 socket. In systems where AGND and DGND are tied
together on the backplane, two diodes (1N914 or equivalent)
should be connected in inverse parallel between AGND and
DGND.
1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
+VREF
128
1
+VREF
128
0
Wr ite Enable Tim ing: During the period when both DS and
R/W are held low, the DAC latches are transparent and the ana-
log output responds directly to the digital data input. T o pre-
vent unwanted variations of the analog output, the R/W should
not go low until the data bus is fully settled (DAT A VALID).
1
–VREF
128
127
–VREF
128
128
–VREF
128
NOT E
1
1 LSB = (2–7) (VREF) =
(VREF)
128
REV. A
–11–
DAC8408
SINGLE SUP P LY, VO LTAGE O UTP UT O P ERATIO N
The DAC8408 can be connected with a single +5 V supply to
produce DAC output voltages from 0 V to +1.5 V. In Figure 8,
the DAC8408 R-2R ladder is inverted from its normal connec-
tion. A +1.500 V reference is connected to the current output pin
4 (IOUT 1A), and the normal VREF input pin becomes the DAC
output. Instead of a normal current output, the R-2R ladder out-
puts a voltage. The OP-490, consisting of four precision low
power op amps that can operate its inputs and outputs to zero
volts, buffers the DAC to produce a low impedance output volt-
age from 0 V to +1.5 V full-scale. Table III shows the code table.
Table III. Single Supply Binary Code Table (Refer to Figure 8)
D AC D ata Input
MSB
LSB
Analog O utput
255
1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
VREF
VREF
VREF
VREF
VREF
VREF
, +1.4941 V
256
129
256
, +0.7559 V
, +0.7500 V
, +0.7441 V
, +0.0059 V
, 0.0000 V
128
256
With the supply and reference voltages as shown, better than 1/2
LSB differential and integral nonlinearity can be expected. To
maintain this performance level, the +5 V supply must not drop
below 4.75 V. Similarly, the reference voltage must be no higher
than 1.5 V. This is because the CMOS switches require a mini-
mum level of bias in order to maintain the linearity performance.
127
256
1
256
0
256
Figure 8. Unipolar Supply, Voltage Output DAC Operation
REV. A
–12–
DAC8408
Figure 9. A Digitally Program m able Universal Active Filter
A D IGITALLY P RO GRAMMABLE ACTIVE FILTER
A powerful D/A converter application is a programmable active
filter design as shown in Figure 9. T he design is based on the
state-variable filter topology which offers stable and repeatable
filter characteristics. DAC B and DAC D can be programmed in
tandem with a single digital byte load which sets the center fre-
quency of the filter. DAC A sets the Q of the filter. DAC C sets
the gain of the filter transfer function. T he unique feature of this
design is that varying the gain of filter does not affect the Q of
the filter. Similarly, the reverse is also true. T his makes the pro-
grammability of the filter extremely reliable and predictable.
Note that low-pass, high-pass, and bandpass outputs are avail-
able. T his sophisticated function is achieved in only two IC
packages.
Figure 10. Program m able Active Filter Band-Pass
Frequency Response
T he network analyzer photo shown in Figure 10 superimposes
five actual bandpass responses ranging from the lowest fre-
quency of 75 Hz (1 LSB ON) to a full-scale frequency of 19.132
kHz (all bits ON), which is equivalent to a 256 to 1 dynamic
range. T he frequency is determined by fC = 1/2πRC where R is
the ladder resistance (RIN) of the DAC8408, and C is 1000 pF.
Note that from device to device, the resistance RIN varies. T hus
some tuning may be necessary.
All components used are available off-the-shelf. Using low drift
thin-film resistors, the DAC8408 exhibits very stable perfor-
mance over temperature. T he wide bandwidth of the OP-470
produces excellent high frequency and high Q response. In addi-
tion, the OP470’s low input offset voltage assures an unusually
low dc offset at the filter output.
REV. A
–13–
DAC8408
Figure 11. A Digitally Program m able, Low-Distortion Sinewave Oscillator
A LO W-D ISTO RTIO N, P RO GRAMMABLE
SINEWAVE O SCILLATO R
475Ω in series with the FET transistor, which acts as an auto-
matic gain control variable resistor. T he AGC action maintains
a very stable sinewave amplitude at any frequency. Again, only
two ICs accomplish a very useful function.
By varying the previous state-variable filter topology slightly,
one can obtain a very low distortion sinewave oscillator with
programmable frequency feature as shown in Figure 11. Again,
DAC B and DAC D in tandem control the oscillating frequency
based on the relationship fC = 1/2πRC. Positive feedback is
accomplished via the 82.5 kΩ and the 20 kΩ potentiometer.
T he Q of the oscillator is determined by the ratio of 10 kΩ and
At the highest frequency setting, the harmonic distortion level
measures 0.016%. As the frequencies drop, distortion also drops
to a low of 0.006%. At the lowest frequency setting, distortion
came back up to a worst case of 0.035%.
REV. A
–14–
–15–
–16–
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