DAC8412 [ADI]
Quad, 12-Bit DAC Voltage Output with Readback; 四通道，12位DAC电压输出，回读
| 型号： | DAC8412 |
| 厂家： | 
ADI |
| 描述： | Quad, 12-Bit DAC Voltage Output with Readback |
| 文件： | 总14页 (文件大小：438K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad, 12-Bit DAC
Voltage Output with Readback
a
DAC8412/DAC8413
FUNCTIONAL BLOCK DIAGRAM
FEATURES
+5 V to ؎15 V Operation
Unipolar or Bipolar Operation
True Voltage Output
Double-Buffered Inputs
Reset to Min (DAC8413) or Center Scale (DAC8412)
Fast Bus Access Time
V
V
V
REFH
LOGIC
DD
12
I/O
DATA
I/O
INPUT
REG A
OUTPUT
REG A
DAC A
DAC B
V
V
V
V
PORT
OUTA
OUTB
OUTC
OUTD
DGND
INPUT
REG B
OUTPUT
REG B
A0
A1
Readback
INPUT
REG C
OUTPUT
REG C
CONTROL
LOGIC
DAC C
DAC D
R/W
APPLICATIONS
Automatic Test Equipment
Digitally Controlled Calibration
Servo Controls
CS
INPUT
REG D
OUTPUT
REG D
RESET
LDAC
Process Control Equipment
V
V
SS
REFL
GENERAL DESCRIPTION
Digital controls allow the user to load or read back data from any
DAC, load any DAC and transfer data to all DACs at one time.
The DAC8412 and DAC8413 are quad, 12-bit voltage output
DACs with readback capability. Built using a complementary
BiCMOS process, these monolithic DACs offer the user very
high package density.
An active low RESET loads all DAC output registers to mid-
scale for the DAC8412 and zero scale for the DAC8413.
The DAC8412/DAC8413 are available in 28-lead plastic DIP,
PLCC and LCC packages. They can be operated from a wide
variety of supply and reference voltages with supplies ranging
from single +5 V to 15 V, and references from +2.5 V to 10 V.
Power dissipation is less than 330 mW with 15 V supplies and
only 60 mW with a +5 V supply.
Output voltage swing is set by the two reference inputs VREFH
and VREFL. By setting the VREFL input to 0 V and VREFH to a
positive voltage, the DAC will provide a unipolar positive output
range. A similar configuration with VREFH at 0 V and VREFL at
a negative voltage will provide a unipolar negative output range.
Bipolar outputs are configured by connecting both VREFH and
VREFL to nonzero voltages. This method of setting output voltage
range has advantages over other bipolar offsetting methods because
it is not dependent on internal and external resistors with different
temperature coefficients.
For MIL-STD-883 applications, contact your local ADI sales
office for the DAC8412/DAC8413/883 data sheet which specifies
operation over the –55°C to +125°C temperature range. All
883 parts are also available on Standard Military Drawings
5962-91 76401MXA through 76404M3A.
0.500
0.375
+125؇C
+25؇C
0.250
0.125
0
–55؇C
–0.125
V
V
V
V
= +15V
= –15V
DD
SS
–0.250
–0.375
–0.500
= +10V
= –10V
REFH
REFL
T
= –55؇C, +25؇C, +125؇C
A
0
512 1024
1536
2046
2548 2560
3072
4096
DIGITAL INPUT CODE – Decimal
Figure 1. INL vs. Code Over Temperature
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
DAC8412/DAC8413–SPECIFICATIONS
(@ VDD = +15.0 V, VSS = –15.0 V, VLOGIC = +5.0 V, VREFH = +10.0 V, VREFL = –10.0 V,
–40؇C ≤ TA ≤ +85؇C unless otherwise noted. See Note 1 for supply variations.)
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Integral Nonlinearity Error
INL
INL
E Grade
F Grade
0.25
0.5
1
LSB
LSB
Differential Nonlinearity Error
Min-Scale Error
Full-Scale Error
Min-Scale Tempco
Full-Scale Tempco
Linearity Matching
DNL
VZSE
VFSE
TCVZSE
TCVFSE
Monotonic Over Temperature
RL = 2 kΩ
–1
LSB
LSB
LSB
ppm/°C
ppm/°C
LSB
2
2
RL = 2 kΩ
RL = 2 kΩ
RL = 2 kΩ
Adjacent DAC Matching
15
20
1
REFERENCE
Positive Reference Input Voltage Range
Negative Reference Input Voltage Range
Reference High Input Current
Reference Low Input Current
Large Signal Bandwidth
Note 2
Note 2
VREFL + 2.5
VDD – 2.5
V
V
mA
mA
kHz
–10
–2.75
0
V
REFH – 2.5
IREFH
IREFL
BW
+1.5
+2
160
+2.75
+2.75
–3 dB, VREFH = 0 V to +10 V p-p
AMPLIFIER CHARACTERISTICS
Output Current
Settling Time
Slew Rate
Analog Crosstalk
IOUT
tS
SR
RL = 2 kΩ, CL = 100 pF
to 0.01%, 10 V Step, RL = 1 kΩ
10% to 90%
–5
+5
mA
µs
V/µs
dB
10
2.2
72
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Output High Voltage
Logic Output Low Voltage
Logic Input Current
VINH
VINL
VOH
VOL
IIN
TA = +25°C
2.4
2.4
V
V
V
V
µA
pF
nV-s
TA = +25°C
0.8
IOH = +0.4 mA
IOL = –1.6 mA
0.4
1
Input Capacitance
CIN
8
5
Digital Feedthrough3
VREFH = +2.5 V, VREFL = 0 V
Note 4
LOGIC TIMING CHARACTERISTICS3
Chip Select Write Pulsewidth
Write Setup
Write Hold
Address Setup
Address Hold
Load Setup
Load Hold
Write Data Setup
Write Data Hold
Load Data Pulsewidth
Reset Pulsewidth
Chip Select Read Pulsewidth
Read Data Hold
Read Data Setup
Data to Hi Z
Chip Select to Data
tWCS
tWS
tWH
tAS
tAH
tLS
80
0
0
0
0
70
30
20
0
170
140
130
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWCS = 80 ns
tWCS = 80 ns
tLH
tWDS
tWDH
tLDW
tRESET
tRCS
tRDH
tRDS
tDZ
tWCS = 80 ns
tWCS = 80 ns
tRCS = 130 ns
tRCS = 130 ns
CL = 10 pF
0
200
160
tCSD
CL = 100 pF
SUPPLY CHARACTERISTICS
Power Supply Sensitivity
Positive Supply Current
Negative Supply Current
Power Dissipation
PSS
IDD
ISS
14.25 V ≤ VDD ≤ 15.75 V
VREFH = +2.5 V
150
12
ppm/V
mA
mA
8.5
–6.5
–10
PDISS
330
mW
NOTES
1All supplies can be varied 5%, and operation is guaranteed. Device is tested with nominal supplies.
2Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.
3All parameters are guaranteed by design.
4All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
Specifications subject to change without notice.
REV. D
–2–
DAC8412/DAC8413
(@ VDD = VLOGIC = +5.0 V ؎ 5%, VSS = 0.0 V, VREFH = +2.5 V, VREFL = 0.0 V, and VSS = –5.0 V ؎ 5%,
VREFL = –2.5 V, –40؇C ≤ TA ≤ +85؇C unless otherwise noted. See Note 1 for supply variations.)
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Integral Nonlinearity Error
INL
INL
INL
INL
E Grade
1/2
1
2
2
4
LSB
LSB
LSB
LSB
F Grade
VSS = 0.0 V; E Grade2
V
SS = 0.0 V; F Grade2
Differential Nonlinearity Error
Min-Scale Error
Full-Scale Error
Min-Scale Error
Full-Scale Error
DNL
VZSE
VFSE
VZSE
VFSE
Monotonic Over Temperature
VSS = –5.0 V
VSS = –5.0 V
VSS = 0.0 V
VSS = 0.0 V
–1
LSB
LSB
LSB
LSB
4
4
8
8
LSB
Min-Scale Tempco
Full-Scale Tempco
Linearity Matching
TCVZSE
TCVFSE
100
100
1
ppm/°C
ppm/°C
LSB
Adjacent DAC Matching
Note 3
REFERENCE
Positive Reference Input Voltage Range
Negative Reference Input Voltage Range
VREFL + 2.5
0
–2.5
–1.0
VDD – 2.5
VREFH – 2.5
VREFH – 2.5
+1.0
V
V
V
mA
kHz
V
SS = 0.0 V
VSS = –5.0 V
Code 000H
–3 dB, VREFH = 0 V to 2.5 V p-p
Reference High Input Current
Large Signal Bandwidth
IREFH
BW
450
AMPLIFIER CHARACTERISTICS
Output Current
Settling Time
IOUT
tS
SR
RL = 2 kΩ, CL = 100 pF
to 0.01%, 2.5 V Step, RL = 1 kΩ
10% to 90%
–1.25
+1.25
mA
µs
V/µs
7
2.2
Slew Rate
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Output High Voltage
Logic Output Low Voltage
Logic Input Current
VINH
VINL
VOH
VOL
IIN
TA = +25°C
2.4
2.4
V
V
V
V
µA
pF
TA = +25°C
0.8
IOH = +0.4 mA
IOL = –1.6 mA
0.45
1
Input Capacitance
CIN
8
LOGIC TIMING CHARACTERISTICS4
Chip Select Write Pulsewidth
Write Setup
Write Hold
Address Setup
Address Hold
Load Setup
Load Hold
Write Data Setup
Write Data Hold
Load Data Pulsewidth
Reset Pulsewidth
Chip Select Read Pulsewidth
Read Data Hold
Read Data Setup
Data to Hi Z
Note 5
tWCS
tWS
tWH
tAS
tAH
tLS
150
0
0
0
0
70
50
20
0
180
150
170
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWCS = 150 ns
tWCS = 150 ns
tLH
tWDS
tWDH
tLDW
tRESET
tRCS
tRDH
tRDS
tDZ
tWCS = 150 ns
tWCS = 150 ns
tRCS = 170 ns
tRCS = 170 ns
CL = 10 pF
200
320
Chip Select to Data
tCSD
CL = 100 pF
SUPPLY CHARACTERISTICS
Power Supply Sensitivity
Positive Supply Current
Negative Supply Current
Power Dissipation
PSS
IDD
ISS
100
7
ppm/V
mA
mA
mW
mW
12
VSS = –5.0 V
VSS = 0 V
VSS = –5 V
–10
PDISS
60
110
NOTES
1All supplies can be varied 5%, and operation is guaranteed. Device is tested with VDD = +4.75 V.
2For single supply operation only (VREFL = 0.0 V, VSS = 0.0 V): Due to internal offset errors, INL and DNL are measured beginning at code 2 (002H).
3Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.
4All parameters are guaranteed by design.
5All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
Specifications subject to change without notice.
REV. D
–3–
DAC8412/DAC8413
tRCS
80ns
CS
CS
tRDH
tRDS
t
WH
t
R/W
WS
R/W
tAS
tAH
A0/A1
t
AS
ADDRESS
ONE
ADDRESS
TWO
ADDRESS
THREE
ADDRESS
FOUR
ADDRESS
tDZ
HI -Z
HI-Z
DATA
OUT
DATA VALID
t
t
LS
LH
tCSD
LDAC
Figure 2. Data Output (Read Timing)
t
LDW
t
t
WDS
WDH
DATA1
VALID
DATA3
VALID
DATA4
VALID
DATA2
VALID
tWCS
DATA IN
CS
tWH
tWS
Figure 5. Double Buffer Mode
R/W
V
DD
tAH
tAS
V
V
REFH
A0/A1
REFL
R1
+
+
R2
R2
V
C1
tLDW
tLH
D1
C2
tLS
+
C1
C1
D1
D1
LDAC
V
V
REFL
REFH
N/C
N/C
V
V
V
N/C
OUTB
OUTA
SS
tWDS
OUTC
OUTD
tWDH
R3
R3
R3
V
C2
N/C
C2
DATA IN
V
DD
V
tRESET
DGND
RESET
LDAC
DB0
LOGIC
CS
C2
RESET
A0
A1
Figure 3. Data WRITE (Input and Output Registers) Timing
R/W
DB11
DB1
DB2
80ns
R6
DB3
DB10
DB9
CS
DB4
R4
R5
R4
DB5
DB8
DB7
R1
t
t
WH
WS
DB6
*
R/W
ONCE PER PORT
DGND
+
t
AS
D1
C1
V
ADDRESS
ONE
ADDRESS
TWO
ADDRESS
THREE
ADDRESS
FOUR
SS
ADDRESS
V
= +15V, V = –15V, V
= +10V, V
= 0V
DD
SS
REFH
REFL
R1 = 10⍀, R2 = 100⍀, R3 = 5k⍀, R4 = 10k⍀, R5 = 100k⍀,
R6 = 47⍀ FOR LCC, R6 = 100⍀ FOR DIP
t
t
LH
LS
C1 = 4.7F (ONCE PER PORT), C2 = 0.01F (EACH DEVICE)
D1 = 1N4001 OR EQUIVALENT (ONCE PER PORT)
LDAC
Figure 6. Burn-In Diagram
t
t
WDS
WDH
DATA1
VALID
DATA3
VALID
DATA4
VALID
DATA2
VALID
DATA IN
Figure 4. Single Buffer Mode
REV. D
–4–
DAC8412/DAC8413
ABSOLUTE MAXIMUM RATINGS
Thermal Resistance
(
TA = +25°C unless otherwise noted)
Package Type
JA*
Units
JC
VSS to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +33.0 V
SS to VLOGIC . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +33.0 V
VLOGIC to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7.0 V
28-Lead Plastic DIP (P)
28-Lead Hermetic Leadless Chip Carrier (TC) 70 28 °C/W
28-Lead Plastic Leaded Chip Carrier (PC) 63 25 °C/W
48 22 °C/W
V
V
V
SS to VREFL . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +VSS–2.0 V
REFH to VDD . . . . . . . . . . . . . . . . . . . . . . . . . +2.0 V, +33.0 V
*θJA is specified for worst-case mounting conditions, i. e., θJA is specified for device
in socket.
VREFH to VREFL . . . . . . . . . . . . . . . . . . . . . . . . +2.0 V, VSS–VDD
Current into Any Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . 15 mA
Digital Input Voltage to DGND . . . . . –0.3 V, VLOGIC +0.3 V
Digital Output Voltage to DGND . . . . . . . . . . –0.3 V, +7.0 V
Operating Temperature Range
ET, FT, EP, FP, FPC . . . . . . . . . . . . . . . . –40°C to +85°C
AT, BT, BTC . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Dice Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Power Dissipation Package . . . . . . . . . . . . . . . . . . . 1000 mW
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300°C
ORDERING INFORMATION1, 2
INL
(LSB)
Military3 Temperature
–55؇C to +125؇C
Extended Industrial3 Temperature
–40؇C to +85؇C
Package
Description
Package
Option
1
1.5
0.5
1
DAC8412FPC
PLCC
LCC
Plastic DIP
Plastic DIP
PLCC
LCC
Plastic DIP
Plastic DIP
P-28A
E-28A
N-28
DAC8412BTC/883
DAC8413BTC/883
DAC8412EP
DAC8412FP
DAC8413FPC
N-28
1
P-28A
E-28A
N-28
1.5
0.5
1
DAC8413EP
DAC8413FP
N-28
NOTES
1Die Size 0.225 × 0.165 inches, 37,125 sq. mils (5.715 × 4.191 mm, 23.95 sq. mm). Substrate should be connected to VDD; Transistor Count = 2595.
2Burn-in is available on extended industrial temperature range parts in cerdip.
3A complete /883 data sheet is available. For availability and burn-in information, contact your local sales office.
CAUTION
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only; functional operation at or above this specification is not implied.
Exposure to the above maximum rating conditions for extended periods may affect
device reliability.
2. Digital inputsand outputs are protected, however, permanent damage may occur on unprotected units
from high-energy electrostatic fields. Keep units in conductive foam or packaging at all times until
ready to use. Use proper antistatic handling procedures.
WARNING!
ESD SENSITIVE DEVICE
3. Remove power before inserting or removing units from their sockets.
4. Analog outputs are protected from short circuit to ground or either supply.
REV. D
–5–
DAC8412/DAC8413
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATIONS
Plastic DIP
Pin Name
Description
1
2
3
4
5
6
VREFH
VOUTB
VOUTA
VSS
DGND
RESET
High-Side DAC Reference Input
DAC B Output
DAC A Output
Lower-Rail Power Supply
Digital Ground
Reset Input and Output Registers to all 0s,
Enabled at Active Low
Load Data to DAC, Enabled at Active Low
Data Bit 0, LSB
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
Data Bit 8
Data Bit 9
Data Bit 10
Data Bit 11, MSB
V
1
2
REFH
OUTB
OUTA
28
27
26
25
24
23
22
V
V
V
V
V
REFL
V
V
OUTC
OUTD
DD
3
V
4
SS
DAC8412
DAC8413
5
DGND
LOGIC
6
RESET
CS
TOP VIEW
(NOT TO SCALE)
A0
7
LDAC
7
8
9
LDAC
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
R/W
DB0 (LSB)
8
21 A1
DB1
DB2
DB3
DB4
R/W
9
20
19
18
17
16
15
DB11 (MSB)
DB10
10
11
12
10
11
12
13
14
15
16
17
18
19
20
DB9
DB8
DB5 13
DB6
DB7
14
PLCC
4
3
2
1
28 27 26
Active Low to Write Data to DAC. Active
High to Readback Previous Data at Data Bit
Pins with VLOGIC Connected to +5 V
Address Bit 1
Address Bit 0
Chip Select, Enabled at Active Low
Voltage Supply for Readback Function. Can
be Open Circuit If Not Used
DGND
25
5
6
7
8
9
V
V
DD
24
23
RESET
LOGIC
CS
LDAC
21
22
23
24
A1
A0
CS
DAC8412PC
DAC8413PC
DB0 (LSB)
22 A0
21
20
DB1
A1
DB2 10
DB3 11
R/W
TOP VIEW
(NOT TO SCALE)
VLOGIC
19 DB11 (MSB)
12 13 14 15 16 17 18
25
26
27
28
VDD
Upper-Rail Power Supply
DAC D Output
DAC C Output
VOUTD
VOUTC
VREFL
Low-Side DAC Reference Input
LCC
4
3
2
1
28 27 26
DGND
25
5
6
V
V
DD
24
23
22
21
20
RESET
LOGIC
7
CS
A0
LDAC
DAC8412TC
DAC8413TC
DB0 (LSB)
8
9
DB1
DB2
A1
TOP VIEW
(NOT TO SCALE)
10
R/W
DB3 11
19 DB11 (MSB)
12 13 14 15 16 17 18
REV. D
–6–
Typical Performance Characteristics–
DAC8412/DAC8413
V
V
V
= +5V
= 0V
DD
SS
+2
+1
0
= 0V
REFL
0.3
0.2
0.1
+1
0
T
= +25؇C
A
V
V
V
T
= +15V
= –15V
DD
–1
–2
V
V
V
= +15V
= –15V
DD
SS
SS
–1
= 0V
REFL
= –10.0V
REFL
= +25؇C
A
T
= +25؇C
A
6
8
10
– Volts
12
6
7
8
9
10
11
12
1
2
3
V
V
– Volts
V
– Volts
REFH
REFH
REFH
Figure 7. DNL vs. VREFH
Figure 8. DNL vs. VREFH
Figure 9. INL vs. VREFH
0.3
0.4
V
V
V
V
= +15V
= –15V
DD
SS
X+3
= +10V
= –10V
0.1
0.2
0
REFH
REFL
+1
X
–0.1
0
X+3
X–3
–0.3
–0.5
–0.7
–0.2
–0.4
–0.6
V
V
V
= +5V
X
V
V
V
V
= +15V
= –15V
DD
SS
DD
–1
= 0V
= 0V
SS
= +10V
= –10V
REFL
REFH
REFL
T
= +25؇C
A
X–3
1
2
3
0
0
200
400
600
800
1000
200
400
600
800
1000
T = HOURS OF OPERATION AT +125؇C
V
– Volts
T = HOURS OF OPERATION AT +125؇C
REFH
Figure 10. INL vs. VREFH
Figure 11. Full-Scale Error vs.
Time Accelerated by Burn-In
Figure 12. Zero-Scale Error vs.
Time Accelerated by Burn-In
0.3
0.2
V
V
V
V
= +15V
= –15V
V
V
V
V
= +15V
= –15V
DD
SS
DD
SS
= +10V
= –10V
= +10V
= –10V
REFH
REFL
REFH
REFL
0.1
–0.1
–0.3
–0.5
0
–0.2
–0.4
DAC A
DAC C
DAC A
DAC D
DAC D
DAC B
DAC C
DAC B
–0.6
–75
0
75
150
–75
0
75
150
TEMPERATURE – ؇C
TEMPERATURE – ؇C
Figure 13. Full-Scale Error vs.
Temperature
Figure 14. Zero-Scale Error vs.
Temperature
REV. D
–7–
DAC8412/DAC8413
0.37500
0.26125
0.18750
0.08375
0.500
0.375
0.250
0.125
0
–0.09375
–0.18750
0
–0.125
–0.250
–0.375
–0.500
V
V
V
V
T
= +15V
= –15V
DD
SS
V
V
T
= +10V
= 0V
= +25؇C
REFH
REFL
= +10V
= –10V
REFH
REFL
–0.23125
–0.37500
= –55؇C, +25؇C, +125؇C
A
A
0
512
1024 1536
2048 2560
3072
3584
4096
0
512
1024 1536
2048
2560
3072
3584 4096
DIGITAL INPUT CODE – Decimal
DIGITAL INPUT CODE – Decimal
Figure 15. Channel-to-Channel Matching
Figure 18. INL vs. Code
(VSUPPLY
=
15 V)
1.00
2.0
1.5
1.0
V
= +15V
= –15V
= +10V
= –10V
DD
SS
V
V
V
= +5.0V
= 0V
DD
SS
V
V
V
0.75
0.50
0.25
REFH
REFL
= +2.5V
REFH
T
= +25؇C
A
T
= +25؇C
A
0
–0.25
–0.50
–0.75
–1.00
0.5
0
–0.5
0
512
1024 1536
2048 2560
3072
3584
4096
0
511
1023
1535
2047 2559
3071 3583
4095
DIGITAL INPUT CODE – Decimal
DIGITAL INPUT CODE – Decimal
Figure 16. Channel-to-Channel Matching
(VSUPPLY = +5 V/GND)
Figure 19. IVREFH vs. Code
13
V
V
V
= +15V
= –15V
DD
SS
= –10V
REFL
10
7
4
–7
–3
1
5
9
13
V
– Volts
REFH
Figure 17. IDD vs. VREFH All DACs High
REV. D
–8–
DAC8412/DAC8413
10V
32.5mV
15.5mV
V
V
V
V
= +15V
= –15V
DD
SS
0
INPUT
–5V
+5V
INPUT
0
= +10V
= –10V
REFH
REFL
T
= +25؇C
A
1V/
DIV
V
V
V
V
= +15V
= –15V
5mV/DIV
2mV/DIV
DD
SS
1 LSB ERROR BAND
V
5
V
5
EA
= +10V
DIV
REFH
DIV
= –10V
REFL
TRIG'D
T = +25؇C
TRIG'D
TRIG'D
A
V
V
V
V
= +15V
= –15V
DD
SS
= +10V
= –10V
REFH
REFL
T
= +25؇C
A
0V
–580ns
–17.5mV
–4.5mV
1s/DIV
9.42s
–1.96s
2s/DIV
18.04s
–1.96s
2s/DIV
18.04s
Figure 22. Positive Slew Rate
Figure 20. Settling Time (Positive)
Figure 21. Settling Time (Negative)
10V
12
10
8
1.0
V
V
V
V
T
= +15V
= –15V
V
V
V
V
T
= +15V
= –15V
DD
SS
DD
SS
0.8
0.6
= +10V
= –10V
= +10V
= –10V
REFH
REFL
REFH
REFL
= +25؇C
= +25؇C
A
A
1V/
DIV
EA
V
V
V
V
= +15V
= –15V
DD
SS
6
0.4
= +10V
= –10V
REFH
REFL
TRIG'D
T
= +25؇C
A
4
0.2
2
0.0
0
0.01
–0.2
0.01
0V
–580ns
0.10
1.00
10.0
100
0.10
1.00
10.0
100
1s/DIV
9.42s
LOAD RESISTANCE – K⍀
LOAD RESISTANCE – K⍀
Figure 23. Negative Slew Rate
Figure 24. DAC 8412 INL vs. Load
Resistance
Figure 25. DAC 8412 Output Swing
vs. Load Resistance
10
100
+PSRR
I
DD
6
80
V
V
= +15V
= –15V
DD
SS
0
–PSRR
–10
2
–2
60
+PSRR:
V
V
= +15V؎1Vp
= –15V
V
V
V
V
= +15V
= –15V
DD
DD
SS
40
20
0
–30
–50
SS
–PSRR:
= 0 ؎100mV
= –10V
REFH
I
V
V
V
= +15V
= –15V؎1V
SS
DD
SS
REFL
–6
DATA BITS = +5V
200mV p-p
= 10V
REFH
ALL DATA 0
–10
–75
0
10
100
1k 10k 100k 1M 10M
0
75
150
10
100
1k
10k
100k
1M
TEMPERATURE – ؇C
FREQUENCY – Hz
FREQUENCY – Hz
Figure 26. Small Signal Response
Figure 27. Power Supply Current vs.
Temperature
Figure 28. PSRR vs. Frequency
REV. D
–9–
DAC8412/DAC8413
10.0
0
V
V
V
V
= +15V
= –15V
DD
SS
V
V
V
V
= +15V
= –15V
DD
SS
30
+I
= +10V
SC
REFH
= +10V
= –10V
REFH
REFL
= –10V
1.00
0.10
20
10
REFL
CH1 MEAN
66.19V
T
= +25؇C
A
T
= +25؇C
A
DATA = 000
H
V
V
V
V
= +15V
= –15V
DD
SS
1
0
= +10V
= –10V
REFH
REFL
–10
–20
–30
0
T
= +25؇C
A
–I
SC
0.01
20uV/DIV
M 200s
A CH1 12.9mV
0.001
1
10
100
1000
10000
–25 –20 –15 –10 –5
0
5
10 15 20 25
NOISE FREQUENCY – Hz
V
– Volts
OUT
Figure 29. DAC8412 Noise
Frequency vs. Noise Density
Figure 30. IOUT vs. VOUT
Figure 31. Broadband Noise
10s
25
+I
V
V
V
V
= +15V
= 0V
SC
DD
SS
20
15
10
5
1V
4s
= +10V
= 0V
REFH
REFL
GLITCH AT DAC OUTPUT
T
= +25؇C
A
DATA = 800
H
0
2
–5
–10
–15
1
–I
SC
DEGLITCHER OUTPUT
CH2
1V
–20
–25
1.86V
–6
–4
–2
0
2
4
6
V
– Volts
OUT
Figure 32. IOUT vs. VOUT
Figure 33. Glitch and Deglitched Results
OPERATION
Introduction
precision instrumentation control, a deglitcher circuit can be
implemented with a standard sample-and-hold circuit. (See
Figure 34.) When CS is enabled by synchronizing the hold
period to be longer than the glitch tradition, the output voltage
can be smoothed with minimum disturbance. A quad sample-
and-hold amplifier, SMP04, has been used to illustrate the
deglitching result. (See Figure 33.)
The DAC8412 and DAC8413 are quad, voltage output, 12-bit
parallel input DACs featuring a 12-bit data bus with readback
capability. The only differences between the DAC8412 and
DAC8413 are the reset functions. The DAC8412 resets to mid-
scale (code 800H) and the DAC8413 resets to minimum scale
(code 000H).
DACOUT
The ability to operate from a single +5 V supply is a unique fea-
ture of these DACs.
DACOUT'
S/H
Operation of the DAC8412 and DAC8413 can be viewed by
dividing the system into three separate functional groups: the
digital I/O and logic, the digital to analog converters and the output
amplifiers.
DACOUT
DACs
CS
Each DAC is a voltage switched, high impedance (R = 50 kΩ),
R-2R ladder configuration. Each 2R resistor is driven by a pair of
switches that connect the resistor to either VREFH or VREFL
.
H
S
H
S/H
S
Glitch
DACOUT'
Worst-case glitch occurs at the transition between half-scale
digital code 1000 0000 0000 to half-scale minus 1 LSB, 0111
1111 1111. It can be measured at about 2 V µs. (See Figure 33.)
For demanding applications such as waveform generation or
Figure 34. Deglitcher Circuit
REV. D
–10–
DAC8412/DAC8413
Reference Inputs
The R/W input, when enabled by CS, controls the writing to and
All four DACs share common reference high (VREFH) and refer-
ence low (VREFL) inputs. The voltages applied to these reference
inputs set the output high and low voltage limits of all four of
the DACs. Each reference input has voltage restrictions with
respect to the other reference and to the power supplies. The
VREFL can be set at any voltage between VSS and VREFH – 2.5 V,
and VREFH can be set to any value between +VDD – 2.5 V and
VREFL + 2.5 V. Note that because of these restrictions the
DAC8412 references cannot be inverted (i.e., VREFL cannot be
greater than VREFH).
reading from the input register.
Coding
Both the DAC8412 and DAC8413 use binary coding. The out-
put voltage can be calculated by:
(VREFH _VREFL) × N
VOUT = VREFL
+
4096
where N is the digital code in decimal.
RESET
It is important to note that the DAC8412’s VREFH input both
sinks and sources current. Also the input current of both VREFH
and VREFL are code dependent. Many references have limited
current sinking capability and must be buffered with an ampli-
fier to drive VREFH. The VREFL has no such special requirements.
The RESET function can be used either at power-up or at any
time during the DAC’s operation. The RESET function is inde-
pendent of CS. This pin is active LOW and sets the DAC output
registers to either center code for the DAC8412, or zero code
for the DAC8413. The reset to center code is most useful when
the DAC is configured for bipolar references and an output of
zero volts after reset is desired.
It is recommended that the reference inputs be bypassed with
0.2 µF capacitors when operating with 10 V references. This
limits the reference bandwidth.
Supplies
Supplies required are VSS, VDD and VLOGIC. The VSS supply can
be set between –15 V and 0 V. VDD is the positive supply; its op-
erating range is between +5 V and +15 V.
Digital I/O
See Table I for digital control logic truth table. Digital I/O consists
of a 12-bit bidirectional data bus, two registers select inputs, A0
and A1, a R/W input, a RESET input, a Chip Select (CS), and
a Load DAC (LDAC) input. Control of the DACs and bus
direction is determined by these inputs as shown in Table I.
Digital data bits are labeled with the MSB defined as data bit
“11” and the LSB as data bit “0.” All digital pins are TTL/
CMOS compatible.
VLOGIC is the digital output supply voltage for the readback
function. It is normally connected to +5 V. This pin is a logic
reference input only. It does not supply current to the device.
If you are not using the readback function, VLOGIC can be left open-
circuit. While VLOGIC does not supply current to the DAC8412,
it does supply currents to the digital outputs when readback
is used.
See Figure 35 for a simplified I/O logic diagram. The register
select inputs A0 and A1 select individual DAC registers “A”
(binary code 00) through “D” (binary code 11). Decoding of
the registers is enabled by the CS input. When CS is high no
decoding takes place, and neither the writing nor the reading of
the input registers is enabled. The loading of the second bank of
registers is controlled by the asynchronous LDAC input. By tak-
ing LDAC low while CS is enabled, all output registers can be
updated simultaneously. Note that the tLDW required pulsewidth
for updating all DACs is a minimum of 170 ns.
Amplifiers
Unlike many voltage output DACs, the DAC8412 features buff-
ered voltage outputs. Each output is capable of both sourcing
and sinking 5 mA at 10 volts, eliminating the need for external
amplifiers when driving 500 pF or smaller capacitive load in
most applications. These amplifiers are short-circuit protected.
Table I. DAC8412/DAC8413 Logic Table
A1
A0
R/W
CS
RS
LDAC
INPUT REG
OUTPUT REG
MODE
DAC
L
L
H
H
L
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
X
L
L
L
L
L
L
L
L
H
H
H
H
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
H
H
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
H
H
H
H
H
H
H
H
L
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
READ
READ
READ
READ
HOLD
HOLD
WRITE
WRITE
WRITE
WRITE
HOLD
HOLD
HOLD
HOLD
HOLD
HOLD
HOLD
HOLD
Transparent
Transparent
Transparent
Transparent
WRITE INPUT
WRITE INPUT
WRITE INPUT
WRITE INPUT
READ INPUT
READ INPUT
READ INPUT
READ INPUT
A
B
C
D
A
B
C
D
A
B
C
D
All
All
All
All
L
H
H
L
L
H
H
X
X
X
X
Update all output registers
HOLD HOLD
H
X
X
*All registers reset to mid/zero-scale
*All registers latched to mid/zero-scale
g
*DAC8412 resets to midscale, and DAC8413 resets to zero scale. L = Logic Low; H = Logic High; X - Don’t Care. Input and Output registers are transparent when
asserted.
REV. D
–11–
DAC8412/DAC8413
V
V
V
SS
REFH
DD
RDDACA
WRDACA
RDDACB
WRDB0
WRDB1
WRDB2
WRDB3
WRDB4
WRDB5
CS
DAC A
DAC B
DAC C
DAC D
V
V
V
OUTA
OUTB
OUTC
OUTD
A0
A1
OUTPUT
REGISTER
WRDACB
INPUT
REGISTER WRDB6
RDDACC
WRDB7
WRDB8
WRDACC
R/W
WRDB9
RDDACD
WRDACD
WRDB10
WRDB11
V
DB11..DB0
V
REFL
V
LOGIC
LDAC
RESET
READOUTBAR
READBACKDATAIN_DB11
READBACKDATAIN_DB10
READOUT
READBACK
DATAOUT_DB11
DGND
Figure 35. Simplified I/O Logic Diagram
+15V
39k⍀
Careful attention to grounding is important to accurate opera-
tion of the DAC8412. This is not because the DAC8412 is
more sensitive than other 12-bit DACs, but because with four
outputs and two references there is greater potential for ground
loops. Since the DAC8412 has no analog ground, the ground
must be specified with respect to the reference.
+15V
V
DD
6.2⍀
V
REFH
BALANCE
100k⍀
0.2F
Reference Configurations
DAC8412
OR
DAC8413
AD688 FOR ؎10V
AD588 FOR ؎ 5V
Output voltage ranges can be configured as either unipolar or
bipolar, and within these choices a wide variety of options exists.
The unipolar configuration can be either positive or negative
voltage output, and the bipolar configuration can be either sym-
metrical or nonsymmetrical.
0.1F
//10F
GAIN
100k⍀
6.2⍀
V
REFL
0.2F
V
SS
1F
+15V
+15V
–15V
؎5 OR ؎10V OPERATION
+
V
V
REFH
Figure 37. Symmetrical Bipolar Operation
DD
INPUT
OP400
OUTPUT
TRIM
Figure 37 (Symmetrical Bipolar Operation) shows the DAC8412
configured for 10 V operation. Note: See the AD688 data
sheet for a full explanation of reference operation. Adjustments may
not be required for many applications since the AD688 is a very
high accuracy reference. However if additional adjustments are
required, adjust the DAC8412 full scale first. Begin by loading
the digital full-scale code (FFFH), and then adjust the Gain
Adjust potentiometer to attain a DAC output voltage of 9.9976 V.
Then, adjust the Balance Adjust to set the center scale output
voltage to 0.000 V.
0.2F
DAC8412
OR
DAC8413
REF10
0.1F
//10F
10k⍀
V
REFL
V
SS
+10V OPERATION
–15V
Figure 36. Unipolar +10 V Operation
REV. D
–12–
DAC8412/DAC8413
The 0.2 µF bypass capacitors shown at the reference inputs
in Figure 37 should be used whenever 10 V references are
used. Applications with single references or references to 5 V
may not require the 0.2 µF bypassing. The 6.2 Ω resistor in series
with the output of the reference amplifier is to keep the amplifier
from oscillating with the capacitive load. We have found that this is
large enough to stabilize this circuit. Larger resistor values are
acceptable, provided that the drop across the resistor doesn’t
exceed a VBE. Assuming a minimum VBE of 0.6 V and a maxi-
mum current of 2.75 mA, then the resistor should be under
200 Ω for the loading of a single DAC8412.
Figure 38 shows the DAC8412 configured for –10 V to 0 V
operation. A REF08 with a –10 V output is connected directly
to VREFL for the reference voltage.
Single +5 V Supply Operation
For operation with a +5 V supply, the reference voltage should be
set between 1.0 V and +2.5 V for optimum linearity. Figure
39 shows a REF43 used to supply a +2.5 V reference voltage.
The headroom of the reference and DAC are both sufficient to
support a +5 V supply with 5% tolerance. VDD and VLOGIC
should be connected to the same supply. Separate bypassing
to each pin should also be used.
Using two separate references is not recommended. Having two
references could cause different drifts with time and tempera-
ture; whereas with a single reference, most drifts will track.
+5V
10F
0.01F
Unipolar positive full-scale operation can usually be set with a
reference with the correct output voltage. This is preferable to
using a reference and dividing down to the required value. For a
10 V full-scale output, the circuit can be configured as shown
in Figure 38. In this configuration the full-scale value is set first
by adjusting the 10 kΩ resistor for a full-scale output of 9.9976 V.
INPUT
V
DD
V
OUTPUT
REFH
REF43
0.2F
DAC8412
OR
DAC8413
TRIM
0.1F
//10F
10k⍀
GND
V
REFL
10k⍀
V
SS
ZERO TO +2.5V OPERATION
SINGLE +5V SUPPLY
V
V
DD
REFH
TRIM
OUTPUT
DAC8412
OR
DAC8413
REF08
0.1F
//10F
GND
Figure 39. +5 V Single Supply Operation
0.2F
V
REFL
0.01F
10F
V
SS
ZERO TO –10V OPERATION
–15V
Figure 38. Unipolar –10 V Operation
REV. D
–13–
DAC8412/DAC8413
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Position Leadless Chip Carrier
(TC Suffix)
0.300 (7.62)
BSC
0.075
(1.91)
REF
0.100 (2.54)
0.064 (1.63)
0.458 (11.63)
0.442 (11.23)
SQ
0.150
(3.51)
BSC
0.015 (0.38)
MIN
0.095 (2.41)
0.075 (1.90)
4
26
28
25
5
0.028 (0.71)
0.022 (0.56)
1
0.458
0.011 (0.28)
0.007 (0.18)
R TYP
TOP
VIEW
(11.63)
MAX
SQ
BOTTOM
VIEW
0.050
(1.27)
BSC
0.075
(1.91)
REF
19
11
18
12
45؇ TYP
0.200
(5.08)
BSC
0.088 (2.24)
0.054 (1.37)
0.055 (1.40)
0.045 (1.14)
28-Lead PLCC (P-28A)
(PC Suffix)
0.180 (4.57)
0.165 (4.19)
0.048 (1.21)
0.042 (1.07)
0.056 (1.42)
0.025 (0.63)
0.015 (0.38)
0.042 (1.07)
0.048 (1.21)
0.042 (1.07)
4
26
25
5
PIN 1
IDENTIFIER
0.021 (0.53)
0.013 (0.33)
0.430 (10.92)
0.390 (9.91)
0.050
(1.27)
BSC
TOP VIEW
(PINS DOWN)
0.032 (0.81)
0.026 (0.66)
11
19
12
18
0.020
(0.50)
R
0.040 (1.01)
0.025 (0.64)
0.456 (11.58)
SQ
0.450 (11.43)
0.495 (12.57)
0.110 (2.79)
0.085 (2.16)
SQ
0.485 (12.32)
28-Lead Epoxy DIP (N-28)
(P Suffix)
1.565 (39.70)
1.380 (35.10)
28
15
0.580 (14.73)
0.485 (12.32)
1
14
PIN 1
0.060 (1.52)
0.015 (0.38)
0.625 (15.87)
0.600 (15.24)
0.250
(6.35)
MAX
0.195 (4.95)
0.125 (3.18)
0.150
(3.81)
MIN
0.015 (0.381)
0.008 (0.204)
0.200 (5.05)
0.125 (3.18)
0.100
(2.54)
BSC
0.070
(1.77)
MAX
0.022 (0.558)
0.014 (0.356)
SEATING
PLANE
REV. D
–14–
相关型号：
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