DAC8426AR/883_技术文档

Quad 8-Bit Voltage Out CMOS DAC

Complete with Internal 10 V Reference

a

DAC8426

FEATURES

offering a 25 ppm/°C temperature coefficient and 5 mA of exter-

No Adjustm ents Required, Total Error ؎1 LSB Max

Over Tem perature

Four Voltage-Output DACs on a Single Chip

Internal 10 V Bandgap Reference

Operates from Single ؉15 V Supply

Fast 50 ns Data Load Tim e, All Tem peratures

Pin-for-Pin Replacem ent for PM-7226 and AD7226,

Elim inates External Reference

nal load driving capability.

T he DAC8426 contains four 8-bit voltage-output CMOS D/A

converters on a single chip. A 10 V output bandgap reference

sets the output full-scale voltage. T he circuit also includes four

input latches and interface control logic.

One of the four latches, selected by the address inputs, is loaded

from the 8-bit data bus input when the write strobe is active

low. All digital inputs are T T L/CMOS (5 V) compatible. T he

on-board amplifiers can drive up to 10 mA from either a single

or dual supply. T he on-board reference that is always connected

to the internal DACs has 5 mA available to drive external devices.

APPLICATIONS

Process Controls

Multichannel Microprocessor Controlled:

System Calibration

Op Am p Offset and Gain Adjust

Level and Threshold Setting

Its compact size, low power, and economical cost-per-channel,

make the DAC8426 attractive for applications requiring mul-

tiple D/A converters without sacrificing circuit-board space. Sys-

tem reliability is also increased due to reduced parts count.

PMI’s advanced oxide-based, silicon-gate, CMOS process al-

lows the DAC8426’s analog and digital circuitry to be manufac-

tured on the same chip. T his, coupled with PMI’s highly stable

thin-film R-2R resistor ladder, aids in matching and tempera-

ture tracking between DACs.

GENERAL D ESCRIP TIO N

T he DAC8426 is a complete quad voltage output D/A converter

with internal reference. T his product fits directly into any exist-

ing 7226 socket where the user currently has a 10 V external

reference. T he external reference is no longer necessary. T he

internal reference of the DAC8426 is laser-trimmed to ±0.4%

FUNCTIO NAL BLO CK D IAGRAM

REV. C

Inform ation furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assum ed by Analog Devices for its

use, nor for any infringem ents of patents or other rights of third parties

which m ay result from its use. No license is granted by im plication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.

Tel: 617/ 329-4700

Fax: 617/ 326-8703

(V = +15 V ؎ 10%, AGND = DGND = 0 V, V = 0 V, T = –55؇C to +125؇C

applies for DAC8426AR/BR, T = –40؇C to +85؇C applies for DAC8426ER/EP/FR/FP/FS, unless otherwise noted.)

DAC8426–SPECIFICATIONS

DD

SS

A

P aram eter

Sym bol

Conditions

Min Typ

Max

Units

ST AT IC PERFORMANCE

Resolution

N

T UE

8

Bits

T otal Unadjusted Error¹

Includes Reference

A, E

B, F

A, E

B, F

±1

±2

±1/2

±1

LSB

ppm/°C

mV

Relative Accuracy

INL

Differential Nonlinearity²

Full-Scale T emperature Coefficient

Zero Scale Error

T emperature Coefficient

DNL

T CG_FS

V_ZSE

Includes Reference

25

10

20

T CV_ZS

Dual Supply

No Load

V_SS= –5 V

µV/°C

REFERENCE OUT PUT

Output Voltage

V_REFOUT

A, E

B, F

9.96

9.92

20

10.04

10.08

V

T emperature Coefficient

Load Regulation

Line Regulation

T CV_REFOUT

LD_REG

LN_REG

e_nrms

I_REFOUT

ppm/°C

%/mA

%/V

µV p-p

mA

∆I_L= 5 mA

∆V_DD±10%

f = 0.1 Hz to 10 Hz

∆V_REFOUT < 40 mV

0.02

0.008

3

0.1

0.04

10

Output Noise³

Output Current

5

7

DIGIT AL INPUT S

Logic Input “0”

Logic Input “1”

Input Current

V_INL

V_INH

I_IN

0.8

V

µA

pF

2.4

V_IN= 0 V or V_DD

0.1

4

10

8

Input Capacitance³

C_IN

POWER SUPPLIES

Positive Supply Current⁴

Negative Supply Current⁴

Power Dissipation⁵

I_DD

I_SS

P_DISS

P_SS

6

4

90

14

10

210

mA

mW

%/%

Dual Supply

V_SS= –5 V

Power Supply Sensitivity

∆V_DD= ±5%

0.0002 0.01

V = +15 V ؎ 10%, AGND = DGND = 0 V, V = 0 V, T = –55؇C to +125؇C applies for

DAC8426AR/BR, T = –40؇C to +85؇C applies for DAC8426ER/EP/FR/FP/FS, unless otherwise noted.

ELECTRICAL CHARACTERISTICS

DD

SS

A

P aram eter

Sym bol

Conditions

Min

Typ⁶Max

Units

DAC OUT PUT

Output Current (Source)³

Output Current (Sink)³

Minimum Load Resistance

I_OUTSOURCE

I_OUTSINK

R_L(MIN)

Digital In = All Ones

Digital In = All Zeroes V_SS= –5 V

Digital In = All Ones

10

350

2

mA

µA

kΩ

450

DYNAMIC PERFORMANCE³

V_OUTSlew Rate

V_OUTSettling T ime

(Positive or Negative)

Digital Crosstalk

SR

t_S

4

3

V/µs

µs

T o ±1/2 LSB, R_L= 2 kΩ

Q

10

nVs

SWIT CHING CHARACT ERIST ICS³

Address T o Write Setup T ime

Address T o Write Hold T ime

Data Valid T o Write Setup T ime

Data Valid T o Write Hold T ime

Write Pulse Width

t_AS

0

70

10

50

ns

t_AH

t_DS

t_DH

t_WR

NOT ES

¹Includes Full-Scale Error, Relative Accuracy, and Zero Code Error. Note ±1 LSB = ±0.39% error.

²All devices guaranteed monotonic over the full operating temperature range.

³Guaranteed and not subject to production test.

⁴Digital inputs V_IN= V_INLor V_INH; V_OUTand V_REFOUT unloaded.

⁵P_DISScalculated by I_DD× V_DD

.

⁶T ypicals represent measured characteristics at T _A= +25°C.

Specifications subject to change without notice.

–2–

REV. C

DAC8426

ABSO LUTE MAXIMUM RATINGS

CAUTIO N

V_DDto AGND or DGND . . . . . . . . . . . . . . . . . –0.3 V, +17 V

V_SSto AGND or DGND . . . . . . . . . . . . . . . . . . . . . –7 V, V_DD

V_DDto V_SS. . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +24 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +5 V

Digital Input Voltage to DGND . . . . . . . . . . . . . –0.3 V, V_DD

V_REFOUT to AGND¹. . . . . . . . . . . . . . . . . . . . . –0.3 V, V_DD

V_OUTto AGND¹. . . . . . . . . . . . . . . . . . . . . . . . . . . . V_SS, V_DD

Operating T emperature

Military AR/BR . . . . . . . . . . . . . . . . . . . . –55°C to +125°C

Extended Industrial ER/EP/FR/FP/FS . . . . –40°C to +85°C

Maximum Junction T emperature . . . . . . . . . . . . . . . . +150°C

Storage T emperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead T emperature (Soldering, 60 sec) . . . . . . . . . . . . +300°C

1. Do not apply voltages higher than V_DDor less than V_SSpo-

tential on any terminal.

2. T he digital control inputs are zener-protected; however,

permanent damage may occur on unprotected units from

high-energy electrostatic fields. Keep units in conductive

foam at all times until ready to use.

3. Do not insert this device into powered sockets. Remove

power before insertion or removal.

4. Stresses above those listed under “Absolute Maximum Rat-

ings” may cause permanent damage to device.

P IN CO NNECTIO NS

TH ERMAL RESISTANCE

20-P in Cer dip

(R Suffix)

2

P ackage Type

␪

JA

␪

JC

Units

20-P in Epoxy D IP

(P Suffix)

20-Pin Cerdip (R)

20-Pin Plastic DIP (P)

20-Pin SOL(S)

70

61

80

7

24

22

°C/W

20-P in SO L

(S Suffix)

NOT ES

¹Outputs may be shorted to any terminal provided the package power dissipation

is not exceeded. T ypical output short-circuit current to AGND is 50 mA.

²θ_JAis specified for worst case mounting conditions, i.e., θ_JAis specified for de-

vice in socket for cerdip and P-DIP packages; θ_JAis specified for device sol-

dered to printed circuit board for SOL package.

O RD ERING GUID E ¹

Tem perature Range

Model

Total Unadjusted Error

P ackage D escription

DAC8426AR²

DAC8426ER

DAC8426EP

DAC8426BR²

DAC8426FR

DAC8426FP

DAC8426FS³

±1 LSB

±2 LSB

–55°C to +125°C

–40°C to +85°C

–55°C to +125°C

–40°C to +85°C

20-Pin Cerdip (Q-20)

20-Pin Plastic DIP (N-20)

20-Pin Cerdip (Q-20)

20-Pin Plastic DIP (N-20)

20-Lead SOL (R-20)

NOT ES

¹Burn-in is available on commercial and industrial temperature range parts in cerdip, plastic DIP, and T O-can packages.

²For devices processed in total compliance to MIL-ST D-883, add /883 after part number. Consult factory for 883 data sheet.

³For availability and burn-in information on SO and PLCC packages, contact your local sales office.

Burn-In Circuit

REV. C

–3–

DAC8426

D ICE CH ARACTERISTICS

1. V_{OUT B}

2. V_{OUT A}

3. V_SS

4. V_REFOUT

5. AGND

6. DGND

7. DB₇(MSB)

8. DB₆

11. DB₃

12. DB₂

13. DB₁

14. DB₀(LSB)

15. WR

16. A₁

17. A₀

18. V_DD

9. DB₅

10. DB₄

19. V_{OUT D}

20. V_{OUT C}

DIE SIZE 0.129 × 0.152 inch, 19,608 sq. m ils

(3.28 × 3.86 m m , 12.65 sq. m m )

at V = +15 V ؎ 5%; V = AGND = DGND = 0 V; unless otherwise specified. T = +25؇C. All specifications

WAFER TEST LIMITS

DD

SS

A

apply for DACs A, B, C, and D.

D AC8426GBC

Lim its

P aram eter

Sym bol

Conditions

Units

T otal Unadjusted Error

Relative Accuracy

Differential Nonlinearity

Full-Scale Error

T UE

INL

DNL

G_FSE

V_ZSE

±2

±1

±20

10

10.04

0.1

0.04

5

2.4

0.8

±1

LSB max

mV max

mA min

V max

%/mA max

%/V max

mA min

V min

Zero Code Error

DAC Output Current

Reference Output Voltage

Load Regulation

Line Regulation

Reference Output Current

Logic Inputs High

I

V

_OUTSOURCE

_REFOUT

Digital In = All Ones

No Load

∆I_L= 5 mA

∆V_DD= ±10 V

∆V_REFOUT < 40 mV

LD_REG

LN_REG

I_REFOUT

V_INH

V_INL

I_IN

I_DD

I_SS

Logic Inputs Low

V max

Logic Input Current

Positive Supply Current

Negative Supply Current

V_IN= 0 V or V_DD

V_IN= V_INLor V_INH

V_IN= V_INLor V_INH’V_SS= –5 V

µA max

mA max

14

10

NOT E

Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed

for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.

CAUTIO N

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the DAC8426 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. C

–4–

Typical Performance Characteristics–DAC8426

Channel-to-Channel Matching (DACs

A, B, C, D, Superim posed)

Relative Accuracy vs. Code

at T_A= –55°C, +25°C, +125°C

(All Superim posed)

Zero Code Error vs. Tem perature

Broadband Noise (DC to 200 kHz)

Long Term Drift Accelerated by

Burn-In

V_OUTNoise Density vs. Frequency

V

(0)

OUT

⌬V

PSRR(+) = –20 LOG

V_DD= +15 V ؎1 V_P, V_SS= 0 V

(0)

,

DD

V

OUT

⌬V

PSRR(–) = –20 LOG

,

SS

V_DD= +15 V, V_SS= –4 V ؎1 V_P

Power Supply Current vs.

Tem perature

PSRR vs. Frequency

REV. C

–5–

DAC8426–Typical Performance Characteristics

Output Im pedance (V_REFOUT)

vs. Frequency

V_REFOUT Load Regulation

vs. Tem perature

V_REFOUT Error from 10.000 V

vs. Tem perature

V_REFOUT Start Up

V_REFOUT Line Regulation vs. Tem perature

REV. C

–6–

DAC8426

P ARAMETER D EFINITIO NS

TO TAL UNAD JUSTED ERRO R (TUE)

Table I. D AC Control Logic Truth Table

T his specification includes the Full-Scale-Error, Relative Accu-

racy Zero-Code-Error and the internal reference voltage. T he

ideal Full-Scale output voltage is 10 V minus 1 LSB which

equals 9.961 volts. Each LSB equals 10 V × (1/256) = 0.039 volts.

Logic Control

A₁

D AC8426

O peration

WR

A₀

H

X

No Operation

Device Not Selected

DAC A T ransparent

DAC A Latched

DAC B T ransparent

DAC B Latched

DAC C T ransparent

DAC C Latched

DAC D T ransparent

DAC D Latched

D IGITAL CRO SSTALK

L

g

L

g

L

g

L

g

L

H

L

H

L

H

Digital crosstalk is the signal coupled to the output of a DAC

due to a changing digital input from adjacent DACs being up-

dated. It is specified in nano-Volt-seconds (nVs).

CIRCUIT D ESCRIP TIO N

T he DAC8426 is a complete quad 8-bit D/A converter. It con-

tains an internal bandgap reference, four voltage switched R-2R

ladder DACs, four DAC latches, four output buffer amplifiers,

and an address decoder. All four DACs share the internal ten

volt reference and analog ground(AGND). Figure 1 provides an

equivalent DAC plus buffer schematic.

L = Low State, H = High State, X = Don’t Care

Figure 1. Sim plified Circuit Configuration for One DAC.

(Switches Are Shown for All “1s” on the Digital Inputs.)

T he eleven digital inputs are compatible with both T T L and 5 V

(or higher) CMOS logic. T able I shows the DAC control logic

truth table for WR, A₁, and A₀operation. When WR is active

low the input latch of the selected DAC is transparent, and the

DAC’s output responds to the data present on the eight digital

data inputs (DBx). T he data (DBx) is latched into the ad-

dressed DAC’s latch on the positive edge of the WR control sig-

nal. T he important timing requirements are shown in the Write

Cycle T iming Diagram, Figure 2.

Figure 2. Write Cycle Tim ing Diagram

the design of the internal DAC switching to minimize transients

on the reference voltage terminal (V_REFOUT ). Other devices

connected to this reference terminal should have well behaved

input loading characteristics. D/A converters such as the PMI

PM7226A have been designed to minimize reference input tran-

sient currents and can be directly connected to the DAC8426

10 V reference. Devices exhibiting large current transients due

to internal switching should be buffered with an op amp to

maintain good overall system noise performance. A 10 µF refer-

ence output bypass capacitor is required.

INTERNAL 10 VO LT REFERENCE

T he internal 10 V bandgap reference of the DAC8426 is trimm-

ed to the output voltage and temperature drift specifications.

T his internal reference is connected to the reference inputs of

the four internal 8-bit D/A converters. T he output terminal of

the internal 10 V reference is available on pin 4. T he 10 V out-

put of the reference is produced with respect to the AGND pin.

T his reference output can be used to supply as much as 5 mA of

additional current to external devices. Care has been taken in

BUFFER AMP LIFIER SECTIO N

T he four internal unity-gain voltage buffers provide low output

impedance capable of sourcing 5 mA or sinking 350 µA. Typical

output slew rates of ±4 V/µs are achieved with 10 V full-scale out-

put changes and R_L= 2 kΩ. Figure 3 photographs show large sig-

nal and settling time response. Capacitive loads to 3300 pF

maximum, and resistive loads to 2 kΩ minimum can be applied.

REV. C

–7–

DAC8426

a) Large Signal

b) Settling Tim e Response (Negative Transition)

Test Conditions, All Photos:

_DD= +15 V

V

C_REFOUT = 10 ␮F

R_L= 2 k⍀

Digital Input Sequence 0, 255, 0

c) Settling Tim e Response (Positive Transition)

Figure 3. Dynam ic Response

four output buffer amplifiers are connected to V_SS. Operating

the DAC8426 from dual supplies (V_DD= +15 V and V_SS= –5 V)

improves negative going output settling time near zero volts.

T he outputs can withstand an indefinite short-circuit to AGND

to typically 50 mA. T he output may also be shorted to any volt-

age between V_DDand V_SS; however, care must be taken to not

exceed the device maximum power dissipation.

When operating single supply (V_DD= +15 V and V_SS= 0 V) the

output sink current decreases as the output approaches zero

voltage. Within 200 mV of AGND (single-supply operation) the

internal sinking capability appears resistive at a value of approxi-

mately 1200 Ω. T he buffer amplifier output current and voltage

characteristics are plotted in Figure 5.

T he amplifier’s emitter follower output stage consists of an in-

trinsic NPN bipolar transistor with a 400 µA NMOS pull-down

current-source load connected to V_SS. T his circuit configuration

shown in Figure 4 enables the output amplifier to develop out-

put voltages very close to AGND. Only the negative supply of the

REV. C

–8–

DAC8426

AP P LICATIO NS SETUP

UNIP O LAR O UTP UT O P ERATIO N

T he output voltage appearing at any output V_OUTis equal to the

internal 10 V reference multiplied by the decimal value of the

latched digital input divided by 2⁸(= 256). In equation form:

One additional characteristic guaranteed is a DNL of ±1 LSB

on all grades. T he DAC8426 is therefore guaranteed to be mon-

otonic. In the situation where a continuously positive 1 LSB

digital increment is applied, the output voltage will always in-

crease in value, never decrease. T his is very important is servo

applications and other closed-loop feedback systems. Finally, in

the typical characteristic curves, long term output voltage drift

(stability) is provided.

V_OUT(D) = D/256 × 10 V

where D = 0₁₀to 255₁₀

BIP O LAR O UTP UT O P ERATIO N

An external op amp plus two resistors can easily convert any

DAC output to bipolar output voltage swings. Figure 6 shows all

four DACs output operating in bipolar mode. This is the general

expression describing the bipolar output transfer equation:

V_OUT(D) = [(1 +R₂/R₁) × D/256 × 10 V] –R₂/R₁× 10 V,

where D = 0₁₀to 255₁₀

If R₁= R₂, then V_OUTbecomes:

V_OUT(D) = (D/128–1) × 10 V

T able III lists various output voltages with R₁= R₂versus digital

input code. T his coding is considered offset binary. Note that

the LSB step size is now 20 V/256 = 0.078 V, twice as large as

the unipolar output case previously discussed. In order to minimize

gain and offset errors, choose R₁and R₂to match and track

within 0.1% over the selected operating temperature range

of interest.

Figure 4. Am plifier Output Stage

Note that the maximum possible output is 1 LSB less than the

internal 10 V reference, that is, 255/256 × 10 V = 9.961 V.

T able II lists output voltages for a given digital input. T he total

unadjusted error (T UE) specification of the product grade used

determines the output tolerances of the values listed in T able II.

For example, a ±2 LSB grade DAC8426FP loaded with decimal

128₁₀(half-scale) would have a guaranteed output voltage oc-

curring in the range of 5 V ±2 LSB, which is 5 V ±(2 × 10 V/256)

= 5 V ±0.078 V. T herefore V_OUTis guaranteed to occur in the

following range:

Table II. Unipolar O utput Voltage as a Function of

D igital Input Code

D igital Input

Code

Analog O utput

Voltage (= D /256 × 10 V)

255

254

129

128

127

1

9.961 V

9.922 V

5.039 V

5.000 V

4.961 V

0.039 V

0.000 V

Full-Scale (FS)

FS-1 LSB

4.922 V ≤ V_OUT(128) ≤ 5.078 V

Half-Scale

1 LSB

Zero-Scale

0

O FFSETTING AGND

Since the DAC ladder and bandgap reference are terminated at

AGND, it is possible to offset AGND positive with respect to

DGND. T he 10 V output span remains if a positive offset is ap-

plied to AGND. T he offset voltage source connected to AGND

must be capable of sinking 14 mA. AGND cannot be taken

negative with respect to DGND; this would forward bias an in-

ternal diode. Allowance must be made at V_DDto maintain 3.5 V

of headroom above V_REFOUT . T his connection setup is useful

in single supply applications where virtual ground needs to be

slightly positive with respect to ground. In this application con-

nect V_SSto DGND to take advantage of the extra buffer output

current sinking capability when the DAC output is programmed

to all zeros code, see Figure 7.

Figure 5. DAC Output Current Sink

For the top grade DAC8426EP ±1 LSB total unadjusted error

(TUE), the guaranteed range is 4.961 V ≤ V_OUT(128₁₀) ≤ 5.039 V.

T hese tolerances provide the worst case analysis including tem-

perature changes.

REV. C

–9–

DAC8426

Table III. Bipolar O utput Voltage as a Function of D igital

Input Code

D igital Input

Code

Analog O utput

Voltage (= D /256 × 10 V)

255

254

129

128

127

1

9.922 V

9.844 V

0.078 V

0.000 V

–0.078 V

–9.922 V

–10.000 V

Full-Scale (FS)

FS-1 LSB

Zero-Scale

0

Neg Full-Scale

Figure 7. AGND Biasing Schem e Providing Offset Output

Range

3. Power Supply Sequencing—No special requirements exist

with the DAC8426. However, users should be aware that of-

ten the 5 V logic supply may be powered up momentarily

prior to the +15 V analog supply. In this situation, the

DAC8426 ESD input protection diodes will forward bias if

the applied input logic is at logic “1”. No damage will result

to the input since the DAC8426 is designed to withstand mo-

mentary currents of up to 130 mA. T his situation will likely

exist for any DAC or ADC operating from a separate analog

supply.

Figure 6. Bipolar Operation

CO NNECTIO N AND LAYO UT GUID ELINES

Layout and design techniques used in the interface between dig-

ital and analog circuitry require special attention to detail. The

following considerations should be evaluated prior to PCB layout.

1. Return signal paths through the ground system should be

carefully considered. High-speed digital logic current pulses

traveling on return ground traces generate glitches that can be

radiated to the analog circuits if the ground path layout pro-

duces loop antennas. Ground planes can minimize this situa-

tion. Separate digital and analog grounding areas to minimize

crosstalk. Ideally a single common-point ground should be on

the same PCB board as the DAC8426. T he analog ground re-

turns should take advantage of the appropriate placement of

power supply bypass capacitors.

4. ESD input protection—Attention has been given in the de-

sign of the DAC8426 to ESD sensitivity. Using the human

body model test technique (MIL-ST D 3015.4) the DAC8426

generally will withstand 1500 V ESD transients on all pins.

Handling and testing prior to PCB insertion generally exposes

ICs to the toughest environment they will experience. Once

the IC is soldered in the PCB, it is still important to consider

any traces that connect to PCB edge connectors. T hese traces

should be protected with appropriate devices especially if the

boards will experience field replacement or adjustment. Han-

dling the exposed edge connectors by field maintenance

people in a low humidity environment can produce 20 kV

ESD transients which will be detrimental to almost any inte-

grated IC connected to the edge connector.

2. For optimum performance, bypass V_DDand V_SS(if using

negative supply voltage) with 0.1 µF ceramic disk capacitors

to shunt high-frequency spikes. Also use in parallel 6.8 µF to

10 µF capacitors to provide a charge reservoir for lower fre-

quency load change requirements. T he reference output

(V_REFOUT ) should be bypassed with a 10 µF tantalum ca-

pacitor to optimize reference output stability during data in-

put changes. T his helps to minimize digital crosstalk.

REV. C

–10–

DAC8426

MICRO P RO CESSO R INTERFACING

T he DAC8426 easily interfaces to most 8- and 16-bit wide data-

bus systems. Serial and 4-bit busses can also be accommodated

with additional latches and control circuitry. Interfacing can be

accomplished with databus transfers running with 50 ns write

pulse widths.

Examples of various microprocessor interface circuits are pro-

vided in Figures 8 through 12. T hese figures have omitted cir-

cuitry not essential to the bus interface. T he design process

should include review of the DAC8426 timing diagram with the

µP system timing diagram.

Figure 10. DAC8426 to 6809 Interface (Sim plified circuit,