EVAL-AD5668SDCZ [ADI]
Octal, 12-/14-/16-Bit SPI Voltage Output denseDAC with 5 ppm/°C On-Chip Reference; 八， 12位/ 14位/ 16位SPI电压输出denseDAC 5 PPM / °时C片参考
| 型号： | EVAL-AD5668SDCZ |
| 厂家： | 
ADI |
| 描述： | Octal, 12-/14-/16-Bit SPI Voltage Output denseDAC with 5 ppm/°C On-Chip Reference |
| 文件： | 总32页 (文件大小：1246K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Octal, 12-/14-/16-Bit SPI Voltage Output
denseDAC with 5 ppm/°C On-Chip Reference
Data Sheet
AD5628/AD5648/AD5668
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
/V
V
REFIN REFOUT
DD
Low power, small footprint, pin-compatible octal DACs
AD5668: 16 bits
AD5628/AD5648/AD5668
1.25V/2.5V
REF
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
AD5648: 14 bits
AD5628: 12 bits
INPUT
DAC
STRING
DAC A
V
V
V
V
V
V
V
V
A
B
C
D
E
F
LDAC
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
REGISTER
REGISTER
DAC
REGISTER
STRING
DAC B
INPUT
REGISTER
14-lead/16-lead TSSOP, 16-lead LFCSP, and 16-lead WLCSP
On-chip 1.25 V/2.5 V, 5 ppm/°C reference
Power down to 400 nA @ 5 V, 200 nA @ 3 V
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to zero scale or midscale
3 power-down functions
Hardware LDAC and LDAC override function
CLR function to programmable code
Rail-to-rail operation
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
SCLK
SYNC
DIN
INTERFACE
LOGIC
DAC
REGISTER
STRING
DAC D
INPUT
REGISTER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC E
DAC
REGISTER
STRING
DAC F
INPUT
REGISTER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC G
G
H
DAC
REGISTER
STRING
DAC H
INPUT
REGISTER
POWER-DOWN
POWER-ON
RESET
LOGIC
GND
1
1
LDAC CLR
1
RU-16 PACKAGE ONLY
APPLICATIONS
Process control
Figure 1.
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
selectable output loads while in power-down mode for any or all
DAC channels. The outputs of all DACs can be updated simul-
The AD5628/AD5648/AD5668 devices are low power, octal,
12-/14-/16-bit, buffered voltage-output DACs. All devices
operate from a single 2.7 V to 5.5 V supply and are guaranteed
monotonic by design. The AD5668 and AD5628 are available in
both a 4 mm × 4 mm LFCSP and a 16-lead TSSOP, while the
AD5648 is available in both a 14-lead and 16-lead TSSOP.
taneously using the
function, with the added functionality
LDAC
of user-selectable DAC channels to simultaneously update. There
is also an asynchronous that updates all DACs to a user-
CLR
programmable code—zero scale, midscale, or full scale.
The AD5628/AD5648/AD5668 utilize a versatile 3-wire serial
interface that operates at clock rates of up to 50 MHz and is
compatible with standard SPI®, QSPI™, MICROWIRE™, and
DSP interface standards. The on-chip precision output amplifier
enables rail-to-rail output swing.
The AD5628/AD5648/AD5668 have an on-chip reference with
an internal gain of 2. The AD5628-1/AD5648-1/AD5668-1 have
a 1.25 V 5 ppm/°C reference, giving a full-scale output range
of 2.5 V; the AD5628-2/AD5648-2/AD5668-2 and AD5668-3 have
a 2.5 V 5 ppm/°C reference, giving a full-scale output range of
5 V. The on-board reference is off at power-up, allowing the use
of an external reference. The internal reference is enabled via a
software write.
PRODUCT HIGHLIGHTS
1. Octal, 12-/14-/16-bit DAC.
2. On-chip 1.25 V/2.5 V, 5 ppm/°C reference.
3. Available in 14-lead/16-lead TSSOP, 16-lead LFCSP, and
16-lead WLCSP.
4. Power-on reset to 0 V or midscale.
5. Power-down capability. When powered down, the DAC
typically consumes 200 nA at 3 V and 400 nA at 5 V.
The part incorporates a power-on reset circuit that ensures that the
DAC output powers up to 0 V (AD5628-1/AD5648-1/AD5668-1,
AD5628-2/AD5648-2/AD5668-2) or midscale (AD5668-3) and
remains powered up at this level until a valid write takes place.
The part contains a power-down feature that reduces the current
consumption of the device to 400 nA at 5 V and provides software-
Rev. G
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2005–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD5628/AD5648/AD5668
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
D/A Section................................................................................. 21
Resistor String............................................................................. 21
Internal Reference ...................................................................... 21
Output Amplifier........................................................................ 22
Serial Interface ............................................................................ 22
Input Shift Register .................................................................... 23
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 6
Timing Characteristics ................................................................ 7
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 19
Theory of Operation ...................................................................... 21
Interrupt .......................................................................... 23
SYNC
Internal Reference Register....................................................... 24
Power-On Reset.......................................................................... 24
Power-Down Modes .................................................................. 24
Clear Code Register ................................................................... 24
Function .......................................................................... 26
LDAC
Power Supply Bypassing and Grounding................................ 26
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 29
REVISION HISTORY
Changes to Table 2.............................................................................5
Changes to Table 3.............................................................................6
Changes to Table 4.............................................................................7
Deleted SnPb from Table 5...............................................................8
Added Figure 5; Renumbered Sequentially ...................................9
Changes to Table 6.............................................................................9
Replaced Typical Performance Characteristics Section ............ 10
Changes to Power-On Reset Section ........................................... 23
Updated Outline Dimensions....................................................... 26
Changes to Ordering Guide.......................................................... 28
1/13—Rev. F to Rev. G
Added WLCSP Reference TC of 15 ppm/°C, Table 2.................. 5
Changes to Ordering Guide .......................................................... 29
8/11—Rev. E to Rev. F
Added 16-Lead WLCSP.....................................................Universal
Added Figure 6 and Table 7; Renumbered Sequentially ........... 10
Changes to Figure 32 and Figure 33............................................. 15
Updated Outline Dimensions....................................................... 26
Changes to Ordering Guide .......................................................... 28
1/11—Rev. D to Rev. E
1/10—Rev. B to Rev. C
Changes to AD5628 Relative Accuracy, Zero-Code Error, Offset
Error, and Reference TC Parameters, Table 1............................... 3
Changes to AD5628 Relative Accuracy, Zero-Code Error, Offset
Error, and Reference TC Parameters, Table 2............................... 5
Changes to Output Voltage Settling Time, Table 3 ...................... 6
Added Figure 53; Renumbered Sequentially .............................. 17
Change to Output Amplifier Section........................................... 21
Changes to Ordering Guide .......................................................... 28
Changes to Figure 3........................................................................ 10
Changes to Ordering Guide.......................................................... 28
2/09—Rev. A to Rev. B
Changes to Reference Current Parameter, Table 1........................3
Changes to IDD (Normal Mode) Parameter, Table 1......................4
Changes to Reference Current Parameter, Table 2........................5
Changes to IDD (Normal Mode) Parameter, Table 2......................6
11/05—Rev. 0 to Rev. A
Change to Specifications ..................................................................3
9/10—Rev. C to Rev. D
Change to Title.................................................................................. 1
Added 16-Lead LFCSP Throughout ................................Universal
Changes to Table 1............................................................................ 3
10/05—Revision 0: Initial Version
Rev. G | Page 2 of 32
Data Sheet
AD5628/AD5648/AD5668
SPECIFICATIONS
VDD = 4.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted.
Table 1.
A Grade1
Typ Max
B Grade1
Typ Max
Parameter
STATIC PERFORMANCE2
Min
Min
Unit
Conditions/Comments
AD5628
Resolution
Relative Accuracy
Differential Nonlinearity
12
12
Bits
LSB
0.25 LSB
0.5
2
4
0.25
0.5
2
1
See Figure 9
Guaranteed monotonic by design
(see Figure 12)
AD5648
Resolution
Relative Accuracy
Differential Nonlinearity
14
16
14
16
Bits
LSB
LSB
8
0.5
4
0.5
See Figure 8
Guaranteed monotonic by design
(see Figure 11)
AD5668
Resolution
Relative Accuracy
Differential Nonlinearity
Bits
LSB
LSB
8
2
32
1
8
2
16
1
See Figure 7
Guaranteed monotonic by design
(see Figure 10)
Zero-Code Error
Zero-Code Error Drift
Full-Scale Error
6
19
6
19
mV
µV/°C
% FSR
All 0s loaded to DAC register (see Figure 26)
−0.2 −1
−0.2 −1
All 1s loaded to DAC register
(see Figure 27)
Gain Error
Gain Temperature Coefficient
Offset Error
DC Power Supply Rejection Ratio
DC Crosstalk
1
1
% FSR
ppm
mV
dB
µV
2.5
2.5
Of FSR/°C
VDD 10%
6
–80
10
19
6
–80
10
19
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
(External Reference)
5
10
25
5
10
25
µV/mA
µV
µV
Due to load current change
Due to powering down (per channel)
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
DC Crosstalk
(Internal Reference)
10
10
µV/mA
Due to load current change
OUTPUT CHARACTERISTICS3
Output Voltage Range
0
VDD
0
VDD
V
Capacitive Load Stability
2
2
nF
nF
Ω
mA
µs
RL = ∞
RL = 2 kΩ
10
0.5
30
4
10
0.5
30
4
DC Output Impedance
Short-Circuit Current
Power-Up Time
VDD = 5 V
Coming out of power-down mode, VDD = 5 V
REFERENCE INPUTS
Reference Current
Reference Input Range
Reference Input Impedance
REFERENCE OUTPUT
Output Voltage
40
55
VDD
40
55
VDD
µA
V
kΩ
VREF = VDD = 5.5 V (per DAC channel)
0
0
14.6
14.6
AD56x8-2, AD56x8-3
Reference TC3
2.495
2.505 2.495
10
2.505
10
10
V
At ambient
5
15
7.5
5
5
7.5
ppm/°C TSSOP
ppm/°C LFCSP
kΩ
Reference Output Impedance
Rev. G | Page 3 of 32
AD5628/AD5648/AD5668
Data Sheet
A Grade1
Typ Max
B Grade1
Typ Max
Parameter
LOGIC INPUTS3
Min
Min
Unit
Conditions/Comments
Input Current
3
0.8
3
0.8
µA
V
V
All digital inputs
VDD = 5 V
VDD = 5 V
Input Low Voltage, VINL
Input High Voltage, VINH
Pin Capacitance
POWER REQUIREMENTS
VDD
2
2
3
3
pF
4.5
5.5
4.5
5.5
V
All digital inputs at 0 or VDD,
DAC active, excludes load current
IDD (Normal Mode)4
VDD = 4.5 V to 5.5 V
VDD = 4.5 V to 5.5 V
IDD (All Power-Down Modes)5
VIH = VDD and VIL = GND
Internal reference off
Internal reference on
1.0
1.8
1.5
2.25
1.0
1.7
1.5
2.25
mA
mA
VDD = 4.5 V to 5.5 V
0.4
1
0.4
1
µA
VIH = VDD and VIL = GND
1 Temperature range is −40°C to +105°C, typical at 25°C.
2 Linearity calculated using a reduced code range of AD5628 (Code 32 to Code 4064), AD5648 (Code 128 to Code 16,256), and AD5668 (Code 512 to 65,024). Output
unloaded.
3 Guaranteed by design and characterization; not production tested.
4 Interface inactive. All DACs active. DAC outputs unloaded.
5 All eight DACs powered down.
Rev. G | Page 4 of 32
Data Sheet
AD5628/AD5648/AD5668
VDD = 2.7 V to 3.6 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
A Grade1
Typ Max
B Grade1
Typ Max
Parameter
STATIC PERFORMANCE2
Min
Min
Unit
Conditions/Comments
AD5628
Resolution
Relative Accuracy
Differential Nonlinearity
12
12
Bits
LSB
0.25 LSB
0.5
2
4
0.25
0.5
2
1
See Figure 9
Guaranteed monotonic by design
(see Figure 12)
AD5648
Resolution
Relative Accuracy
Differential Nonlinearity
14
16
14
16
Bits
LSB
LSB
8
0.5
4
0.5
See Figure 8
Guaranteed monotonic by design
(see Figure 11)
AD5668
Resolution
Relative Accuracy
Differential Nonlinearity
Bits
LSB
LSB
8
2
32
1
8
2
16
1
See Figure 7
Guaranteed monotonic by design
(see Figure 10)
All 0s loaded to DAC register (see Figure 26)
All 1s loaded to DAC register (see Figure 27)
Of FSR/°C
Zero-Code Error
Zero-Code Error Drift
Full-Scale Error
Gain Error
Gain Temperature Coefficient
Offset Error
6
19
6
19
mV
µV/°C
% FSR
% FSR
ppm
mV
−0.2 −1
−0.2 −1
1
1
2.5
6
2.5
6
19
19
DC Power Supply Rejection
–80
–80
dB
VDD 10%
Ratio3
DC Crosstalk 3
(External Reference)
10
10
µV
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
5
10
25
5
10
25
µV/mA
µV
µV
Due to load current change
Due to powering down (per channel)
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
DC Crosstalk 3
(Internal Reference)
10
10
µV/mA
Due to load current change
OUTPUT CHARACTERISTICS3
Output Voltage Range
0
VDD
0
VDD
V
Capacitive Load Stability
2
2
nF
nF
Ω
mA
µs
RL = ∞
RL = 2 kΩ
10
0.5
30
4
10
0.5
30
4
DC Output Impedance
Short-Circuit Current
Power-Up Time
VDD = 3 V
Coming out of power-down mode, VDD = 3 V
REFERENCE INPUTS
Reference Current
Reference Input Range
Reference Input Impedance
REFERENCE OUTPUT
Output Voltage
40
55
VDD
40
55
VDD
µA
kΩ
VREF = VDD = 5.5 V (per DAC channel)
0
0
14.6
14.6
AD5628/AD5648/AD5668-1
Reference TC3
1.247
1.253 1.247
15
1.253
15
15
V
At ambient
5
15
5
5
15
7.5
ppm/°C TSSOP
ppm/°C LFCSP
ppm/°C WLCSP
kΩ
Reference Output
Impedance
7.5
Rev. G | Page 5 of 32
AD5628/AD5648/AD5668
Data Sheet
A Grade1
Typ Max
B Grade1
Typ Max
Parameter
LOGIC INPUTS3
Min
Min
Unit
Conditions/Comments
Input Current
3
0.8
3
0.8
µA
V
V
All digital inputs
VDD = 3 V
VDD = 3 V
Input Low Voltage, VINL
Input High Voltage, VINH
Pin Capacitance
POWER REQUIREMENTS
VDD
2
2
3
3
pF
2.7
3.6
2.7
3.6
V
All digital inputs at 0 or VDD,
DAC active, excludes load current
VIH = VDD and VIL = GND
Internal reference off
IDD (Normal Mode)4
VDD = 2.7 V to 3.6 V
VDD = 2.7 V to 3.6 V
IDD (All Power-Down Modes)5
1.0
1.8
1.5
2.25
1.0
1.7
1.5
2.25
mA
mA
Internal reference on
VDD = 2.7 V to 3.6 V
0.2
1
0.2
1
µA
VIH = VDD and VIL = GND
1 Temperature range is −40°C to +105°C, typical at 25°C.
2 Linearity calculated using a reduced code range of AD5628 (Code 32 to Code 4064), AD5648 (Code 128 to Code 16256), and AD5668 (Code 512 to 65024). Output
unloaded.
3 Guaranteed by design and characterization; not production tested.
4 Interface inactive. All DACs active. DAC outputs unloaded.
5 All eight DACs powered down.
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1, 2
Min
Typ
2.5
1.2
4
Max
Unit
µs
V/µs
nV-s
Conditions/Comments3
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Impulse
7
¼ to ¾ scale settling to 2 LSB (16-bit resolution)
1 LSB (16-bit resolution) change around major carry
(see Figure 42)
19
nV-s
From code 0xEA00 to code 0xE9FF (16-bit resolution)
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
Output Noise Spectral Density
0.1
0.2
0.4
0.8
320
−80
120
100
12
nV-s
nV-s
nV-s
nV-s
kHz
dB
nV/√Hz
nV/√Hz
μV p-p
VREF = 2 V 0.2 V p-p
VREF = 2 V 0.1 V p-p, frequency = 10 kHz
DAC code = 0x8400(16-bit resolution), 1 kHz
DAC code = 0x8400(16-bit resolution), 10 kHz
0.1 Hz to 10 Hz, DAC code = 0x0000
Output Noise
1 Guaranteed by design and characterization; not production tested.
2 See the Terminology section.
3 Temperature range is −40°C to +105°C, typical at 25°C.
Rev. G | Page 6 of 32
Data Sheet
AD5628/AD5648/AD5668
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
DD = 2.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.
V
Table 4.
Limit at TMIN, TMAX
Parameter
VDD = 2.7 V to 5.5 V
Unit
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge set-up time
Data set-up time
1
t1
t2
t3
t4
20
8
8
13
4
4
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
t5
t6
t7
Data hold time
0
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
LDAC pulse width low
t8
15
13
0
t9
t10
t11
t12
t13
t14
t15
10
15
5
SCLK falling edge to LDAC rising edge
CLR pulse width low
0
SCLK falling edge to LDAC falling edge
CLR pulse activation time
300
1 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested.
t10
t1
t9
SCLK
t2
t8
t7
t3
t4
SYNC
DIN
t6
t5
DB31
DB0
t14
t11
1
LDAC
t12
2
LDAC
t13
CLR
t15
V
OUT
1
2
ASYNCHRONOUS LDAC UPDATE MODE.
SYNCHRONOUS LDAC UPDATE MODE.
Figure 2. Serial Write Operation
Rev. G | Page 7 of 32
AD5628/AD5648/AD5668
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to GND
−0.3 V to +7 V
Digital Input Voltage to GND
VOUT to GND
VREFIN/VREFOUT to GND
Operating Temperature Range
Industrial
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
ESD CAUTION
−40°C to +105°C
−65°C to +150°C
150°C
Storage Temperature Range
Junction Temperature (TJ MAX
)
TSSOP Package
Power Dissipation
θJA Thermal Impedance
(TJ MAX − TA)/θJA
150.4°C/W
Reflow Soldering Peak Temperature
Pb Free
260°C
Rev. G | Page 8 of 32
Data Sheet
AD5628/AD5648/AD5668
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD5628/AD5668
V
1
2
3
4
12 GND
DD
V
V
A
C
E
11
10
9
V
V
B
D
F
OUT
OUT
OUT
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
LDAC
SYNC
SCLK
DIN
OUT
1
2
3
4
5
6
7
SYNC
14
13
12
11
10
9
V
V
OUT
SCLK
DIN
OUT
V
GND
V
DD
DD
AD5628/
AD5648/
AD5668
TOP VIEW
(Not to Scale)
AD5628/
AD5648/
V
A
C
E
V
V
V
V
B
V
A
GND
OUT
OUT
OUT
OUT
OUT
OUT
V
D
F
V
C
E
V
V
V
V
B
OUT
OUT
OUT
OUT
OUT
OUT
TOP VIEW
(Not to Scale)
V
V
D
F
OUT
OUT
V
G
V
G
OUT
H
OUT
8
V
/V
H
V
/V
CLR
NOTES
REFIN REFOUT
REFIN REFOUT
1. EXPOSED PAD MUST BE TIED TO GND.
Figure 3. 14-Lead TSSOP (RU-14)
Figure 4. 16-Lead TSSOP (RU-16)
Figure 5. 16-Lead LFCSP(CP-16-17)
Table 6. Pin Function Descriptions
Pin No.
14-Lead 16-Lead
16-Lead
LFCSP
TSSOP
TSSOP
Mnemonic
Description
15
N/A
1
LDAC
Pulsing this pin low allows any or all DAC registers to be updated if the input registers
have new data. This allows all DAC outputs to simultaneously update. Alternatively, this
pin can be tied permanently low.
1
2
16
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data.
When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift
register. Data is transferred in on the falling edges of the next 32 clocks. If SYNC is taken
high before the 32nd falling edge, the rising edge of SYNC acts as an interrupt and the
write sequence is ignored by the device.
2
3
1
VDD
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply
should be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
3
11
4
10
7
4
13
5
12
8
2
11
3
10
6
VOUT
VOUT
VOUT
VOUT
VREFIN
VREFOUT
A
B
C
D
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
The AD5628/AD5648/AD5668 have a common pin for reference input and reference
output. When using the internal reference, this is the reference output pin. When using
an external reference, this is the reference input pin. The default for this pin is as a
reference input.
/
N/A
9
7
CLR
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all
LDAC pulses are ignored. When CLR is activated, the input register and the DAC register
are updated with the data contained in the CLR code register—zero, midscale, or full
scale. Default setting clears the output to 0 V.
5
9
6
8
12
13
6
11
7
10
14
15
4
9
5
8
12
13
VOUT
VOUT
VOUT
VOUT
GND
DIN
E
F
G
H
Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register
on the falling edge of the serial clock input.
14
16
14
SCLK
EPAD
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the
serial clock input. Data can be transferred at rates of up to 50 MHz.
It is recommended that the exposed paddle be soldered to the ground plane.
EPAD
Rev. G | Page 9 of 32
AD5628/AD5648/AD5668
Data Sheet
BALL A1
INDICATOR
1
2
3
4
GND SCL
DIN SYNC
A
V
V
B LDAC
V
V
A
OUT
OUT
DD
B
C
D
F V
D V
E V
C
G
OUT
OUT
OUT
OUT
V
H
CLR
V
V
OUT
REF
OUT
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
Figure 6. 16-Lead WLCSP
Table 7. 16-Lead WLCSP Pin Function Descriptions
Pin. No. Mnemonic Description
B2
A4
LDAC
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows
all DAC outputs to simultaneously update. Alternatively, this pin can be tied permanently low.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it
powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges
of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising edge of SYNC acts as an
interrupt and the write sequence is ignored by the device.
SYNC
B3
VDD
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a
10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
B4
B1
C4
C2
D3
VOUT
VOUT
VOUT
VOUT
A
B
C
D
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
VREFIN/VREFOUT The AD5628/AD5648/AD5668 have a common pin for reference input and reference output. When using the
internal reference, this is the reference output pin. When using an external reference, this is the reference input
pin. The default for this pin is as a reference input.
D2
CLR
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored.
When CLR is activated, the input register and the DAC register are updated with the data contained in the CLR
code register—zero, midscale, or full scale. Default setting clears the output to 0 V.
Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
C3
C1
D4
D1
A1
A3
VOUT
VOUT
VOUT
VOUT
GND
DIN
E
F
G
H
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
A4
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at rates of up to 50 MHz.
Rev. G | Page 10 of 32
Data Sheet
AD5628/AD5648/AD5668
TYPICAL PERFORMANCE CHARACTERISTICS
10
1.0
0.8
V
= 5V
V
= 5V
DD
EXT REF = 5V
= 25°C
DD
EXT REF = 5V
T = 25°C
A
8
6
T
A
0.6
4
0.4
2
0.2
0
0
–2
–4
–6
–8
–10
–0.2
–0.4
–0.6
–0.8
–1.0
0
10k
20k
30k
CODES
40k
50k
60k 65535
0
10k
20k
30k
CODES
40k
50k
60k 65535
Figure 7. INL AD5668—External Reference
Figure 10. DNL AD5668—External Reference
4
0.5
V
= 5V
DD
EXT REF = 5V
= 25°C
V
= 5V
DD
EXT REF = 5V
0.4
0.3
0.2
0.1
3
2
T
A
T
= 25°C
A
1
0
0
–0.1
–1
–2
–3
–4
–0.2
–0.3
–0.4
–0.5
0
5k
10k
15k 16384
0
5k
10k
15k 16384
CODES
CODES
Figure 11. DNL AD5648—External Reference
Figure 8. INL AD5648—External Reference
1.0
0.8
0.20
0.15
0.10
0.05
0
V
= 5V
V
= 5V
DD
EXT REF = 5V
= 25°C
DD
EXT REF = 5V
= 25°C
T
T
A
A
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.05
–0.10
–0.15
–0.20
0
500
1000 1500 2000 2500 3000 3500
CODES
4095
0
500
1000 1500 2000 2500 3000 3500
CODES
4095
Figure 9. INL AD5628—External Reference
Figure 12. DNL AD5628—External Reference
Rev. G | Page 11 of 32
AD5628/AD5648/AD5668
Data Sheet
10
1.0
0.5
V
= 5V
V
= 5V
DD
INT REF = 2.5V
= 25°C
DD
INT REF = 2.5V
T = 25°C
A
T
A
5
0
0
–5
–0.5
–1.0
–10
0
10k
20k
30k
CODES
40k
50k
60k 65535
0
10k
20k
30k
CODES
40k
50k
60k 65535
Figure 13. INL AD5668-2/AD5668-3
Figure 16. DNL AD5668-2/AD5668-3
0.5
4
V
= 5V
V
= 5V
DD
EXT REF = 5V
DD
EXT REF = 2.5V
0.4
0.3
0.2
0.1
3
2
T
= 25°C
T = 25°C
A
A
1
0
0
–0.1
–1
–2
–3
–4
–0.2
–0.3
–0.4
–0.5
0
5k
10k
15k 16383
0
5k
10k
15k 16383
CODES
CODES
Figure 14. INL AD5648-2
Figure 17. DNL AD5648-2
0.20
0.15
0.10
0.05
0
1.0
0.5
V
= 5V
V
= 5V
DD
INT REF = 2.5V
= 25°C
DD
INT REF = 2.5V
= 25°C
T
T
A
A
0
–0.05
–0.10
–0.15
–0.20
–0.5
–1.0
0
500
1000 1500 2000 2500 3000 3500
CODES
4095
0
500
1000 1500 2000 2500 3000 3500
CODES
4095
Figure 18. DNL AD5628-2
Figure 15. INL AD5628-2
Rev. G | Page 12 of 32
Data Sheet
AD5628/AD5648/AD5668
10
8
1.0
0.5
V
= 3V
V
= 3V
DD
INT REF = 1.25V
= 25°C
DD
INT REF = 1.25V
= 25°C
T
T
A
A
6
4
2
0
0
–2
–4
–6
–8
–10
–0.5
–1.0
0
10k
20k
30k
CODES
40k
50k
60k 65535
0
10k
20k
30k
CODES
40k
50k
60k 65535
Figure 19. INL AD5668-1
Figure 22. DNL AD5668-1
4
0.5
V
= 3V
DD
EXT REF = 1.25V
V
= 3V
DD
EXT REF = 1.25V
0.4
0.3
0.2
0.1
3
2
T
= 25°C
T
= 25°C
A
A
1
0
0
–0.1
–1
–2
–3
–4
–0.2
–0.3
–0.4
–0.5
0
5k
10k
15k 16383
0
5k
10k
15k 16383
CODES
CODES
Figure 20. INL AD5648-1
Figure 23. DNL AD5648-1
1.0
0.5
0.20
0.15
0.10
0.05
0
V
= 3V
V
= 3V
DD
INT REF = 1.25V
= 25°C
DD
INT REF = 1.25V
T = 25°C
A
T
A
0
–0.05
–0.10
–0.15
–0.20
–0.5
–1.0
0
500
1000 1500 2000 2500 3000 3500
CODES
4095
0
500
1000 1500 2000 2500 3000 3500
CODES
4095
Figure 21. INL AD5628-1
Figure 24. DNL AD5628-1
Rev. G | Page 13 of 32
AD5628/AD5648/AD5668
Data Sheet
0
1.95
1.90
1.85
1.80
1.75
1.70
1.65
1.60
1.55
V
= 5V
T
= 25°C
DD
A
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
OFFSET ERROR
FULL-SCALE ERROR
GAIN ERROR
ZERO-SCALE ERROR
–40 –25 –10
5
20
35
50
65
80
95 110 125
2.7
3.1
3.5
3.9
4.3
(V)
4.7
5.1
5.5
TEMPERATURE (°C)
V
DD
Figure 25. Gain Error and Full-Scale Error vs. Temperature
Figure 28. Zero-Scale Error and Offset Error vs. Supply Voltage
21
18
15
12
9
6
V
= 5V
DD
5
4
3
2
1
0
OFFSET ERROR
ZERO-SCALE ERROR
6
3
0
–40 –25 –10
5
20
35
50
65
80
95 110 125
0.85
0.90
0.95
1.00
1.05
I
WITH EXTERNAL REFERENCE (mA)
TEMPERATURE (°C)
DD
Figure 26. Zero-Scale Error and Offset Error vs. Temperature
Figure 29. IDD Histogram with External Reference
18
–0.16
–0.17
–0.18
–0.19
–0.20
–0.21
–0.22
–0.23
–0.24
–0.25
–0.26
T
= 25°C
A
FULL-SCALE ERROR
16
14
12
10
8
6
4
GAIN ERROR
2
0
2.7
3.1
3.5
3.9
4.3
(V)
4.7
5.1
5.5
1.65
1.70
1.75
1.80
1.85
1.190
I
WITH INTERNAL REFERENCE (mA)
V
DD
DD
Figure 30. IDD Histogram with Internal Reference
Figure 27. Gain Error and Full-Scale Error vs. Supply Voltage
Rev. G | Page 14 of 32
Data Sheet
AD5628/AD5648/AD5668
0.4
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
T = 25°C
A
T
= 25°C
A
0.3
0.2
V
= 5V
DD
0.1
V
= 3V, INT REF = 1.25V
DD
0
V
= 3V
DD
–0.1
–0.2
–0.3
–0.4
–0.5
V
= 5V, INT REF = 2.5V
DD
0
10k
20k
30k
40k
50k
60k
–10
–8
–6
–4
–2
0
2
4
6
8
10
DIGITAL CODES (Decimal)
SOURCE/SINK CURRENT (mA)
Figure 34. Supply Current vs. Code
Figure 31. Headroom at Rails vs. Source and Sink
6
5
2.0
V
= 5V
DD
INT REF = 2.5V
FULL SCALE
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
T
= 25°C
A
3/4 SCALE
4
V
V
= 5.5V
DD
3
MIDSCALE
1/4 SCALE
= 3.6V
DD
2
1
0
ZERO SCALE
–1
–0.03
–0.02
–0.01
0
0.01
0.02
0.03
–40 –25 –10
5
20
35
50
65
80
95 110 125
CURRENT (A)
TEMPERATURE (°C)
Figure 32. AD5668-2/AD5668-3 Source and Sink Capability
Figure 35. Supply Current vs. Temperature
1.48
1.46
1.44
1.42
1.40
1.38
1.36
1.34
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
T
= 25°C
A
V
= 3V
DD
INT REF = 1.25V
T
= 25°C
A
FULL SCALE
3/4 SCALE
MIDSCALE
1/4 SCALE
ZERO SCALE
–0.5
–1.0
–0.03
2.7
3.1
3.5
3.9
4.3
(V)
4.7
5.1
5.5
–0.02
–0.01
0
0.01
0.02
0.03
V
DD
CURRENT (A)
Figure 36. Supply Current vs. Supply Voltage
Figure 33. AD5668-1 Source and Sink Capability
Rev. G | Page 15 of 32
AD5628/AD5648/AD5668
Data Sheet
2.3
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
T
= 25°C
A
V
= 5V
DD
EXT REF = 5V
= 25°C
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
T
A
V
DD
V
= 5V
DD
V
A
OUT
V
= 3V
DD
–0.5
–0.0010
0
0.5
1.0
1.5
2.0
2.5
3.0
(V)
3.5
4.0
4.5
5.0
–0.0006
–0.0002
0.0002
0.0006
0.0010
V
LOGIC
TIME (s)
Figure 37. Supply Current vs. Logic Input Voltage
Figure 40. Power-On Reset to Midscale
6
5.5
V
V
= 5V
TH
DD
EXT REF = 5V
= 5V
24 CLK RISING EDGE
DD
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
EXT REF = 5V
= 25°C
T
= 25°C
A
T
A
5
4
3
2
1
0
V
A
OUT
–0.5
–10
–2
0
2
4
6
8
–5
0
5
10
TIME (µs)
TIME (µs)
Figure 38. Full-Scale Settling Time, 5 V
Figure 41. Exiting Power-Down to Midscale
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 5V
T
DD
V
= 5V
DD
EXT REF = 5V
= 25°C
EXT REF = 5V
T
= 25°C
A
T
A
V
DD
V
A
OUT
3
TH
24 CLK RISING EDGE
V
A
OUT
4
–0.5
–0.0010
–0.0006
–0.0002
0.0002
0.0006
0.0010
M400ns
17.0%
A
CH4
1.50V
B
CH3 10.0mV
CH4 5.0V
T
TIME (s)
W
Figure 39. Power-On Reset to 0 V
Figure 42. Digital-to-Analog Glitch Impulse (Negative)
Rev. G | Page 16 of 32
Data Sheet
AD5628/AD5648/AD5668
0.0010
0.20
0.15
0.10
0.05
0
V
= 5V
EXT REF = 2.5V
DD
EXT REF = 5V
= 25°C
T
A
0.0005
0
–0.0005
–0.0010
–0.0015
–0.05
–0.10
–0.15
–0.20
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
10
TIME (µs)
TIME (s)
Figure 43. Analog Crosstalk
Figure 46. 0.1 Hz to 10 Hz Output Noise Plot, External Reference
0.0020
0.0015
0.0010
0.0005
0
0.20
V
= 5V
INT REF = 1.25V
DD
EXT REF = 5V
= 25°C
0.15
0.10
0.05
0
T
A
–0.05
–0.10
–0.15
–0.20
–0.0005
–0.0010
–0.0015
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
9
10
TIME (µs)
TIME (s)
Figure 44. DAC-to-DAC Crosstalk
Figure 47. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference
0.06
0.04
0.02
0
800
700
600
500
400
EXT REF = 5V
V
= 2.5V
REF
–0.02
–0.04
–0.06
–0.08
300
200
100
0
V
= 1.25V
REF
0
1
2
3
4
5
6
7
8
9
10
100
1k
10k
100k
1M
TIME (s)
FREQUENCY (Hz)
Figure 45. 0.1 Hz to 10 Hz Output Noise Plot, External Reference
Figure 48. Noise Spectral Density, Internal Reference
Rev. G | Page 17 of 32
AD5628/AD5648/AD5668
Data Sheet
10
0
0
V
= 5.5V
DD
EXT REF = 5V
= 25°C
T
–20
–40
A
V
= 2V ± 0.1V p-p
REF
FREQUENCY = 10kHz
–10
–20
–30
–40
–50
–60
–70
–80
–60
–80
CH A
CH B
CH C
CH D
CH E
CH F
CH G
CH H
–3dB
–100
–120
–140
V
= 5.5V
DD
EXT REF = 5V
= 25°C
T
A
V
= 2V ± 0.2V p-p
REF
10
100
1k
1k0
100k
1M
10M
100M
0
2000
4000
6000
8000
10,000
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 52. Multiplying Bandwidth
Figure 49. Total Harmonic Distortion
1.2510
1.2508
1.2506
1.2504
1.2502
1.2500
1.2498
1.2496
1.2494
1.2492
1.2490
V
= 5.5V
DD
9
8
7
6
5
4
3
2
1
T
= 25°C
A
V
= EXTERNAL REFERENCE = 5V
DD
V
= EXTERNAL REFERENCE = 3V
DD
–40
25
105
0
0
1
2
3
4
5
6
7
8
9
10
TEMPERATURE (°C)
CAPACITIVE LOAD (nF)
Figure 53. 1.25 V Reference Temperature Coefficient vs. Temperature
Figure 50. Settling Time vs. Capacitive Load
2.503
2.502
2.501
2.500
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
EXT REF = 5V
V
A
OUT
2.499
2.498
2.497
2.496
2.495
CLR PULSE
–0.5
105
25
–40
–10
–5
0
5
10
TEMPERATURE (°C)
TIME (µs)
CLR
Figure 54. 2.5 V Reference Temperature Coefficient vs. Temperature
Figure 51. Hardware
Rev. G | Page 18 of 32
Data Sheet
AD5628/AD5648/AD5668
TERMINOLOGY
Relative Accuracy
Digital-to-Analog Glitch Impulse
For the DAC, relative accuracy, or integral nonlinearity (INL), is
a measure of the maximum deviation in LSBs from a straight line
passing through the endpoints of the DAC transfer function.
Figure 7 to Figure 9, Figure 13 to Figure 15, and Figure 19 to
Figure 21 show plots of typical INL vs. code.
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s and
is measured when the digital input code is changed by 1 LSB at
the major carry transition (0x7FFF to 0x8000). See Figure 42.
Differential Nonlinearity
DC Power Supply Rejection Ratio (PSRR)
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of 1 LSB
maximum ensures monotonicity. This DAC is guaranteed mono-
tonic by design. Figure 10 to Figure 12, Figure 16 to Figure 18,
and Figure 22 to Figure 24 show plots of typical DNL vs. code.
PSRR indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in decibels. VREF is held at 2 V, and VDD is varied 10%.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change on one DAC (or soft power-down
and power-up) while monitoring another DAC kept at midscale.
It is expressed in microvolts.
Offset Error
Offset error is a measure of the difference between the actual
V
OUT and the ideal VOUT, expressed in millivolts in the linear
region of the transfer function. Offset error is measured on the
AD5668 with Code 512 loaded into the DAC register. It can be
negative or positive and is expressed in millivolts.
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has to another
DAC kept at midscale. It is expressed in microvolts per milliamp.
Zero-Code Error
Zero-code error is a measure of the output error when zero
code (0x0000) is loaded into the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive in
the AD5628/AD5648/AD5668, because the output of the DAC
cannot go below 0 V. It is due to a combination of the offset
errors in the DAC and output amplifier. Zero-code error is
expressed in millivolts. Figure 28 shows a plot of typical zero-
code error vs. temperature.
Reference Feedthrough
Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
is not being updated (that is,
decibels.
is high). It is expressed in
LDAC
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of a DAC from the digital input pins of the
device, but is measured when the DAC is not being written to
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed as a percentage of the full-scale range.
(
held high). It is specified in nV-s and measured with a
SYNC
full-scale change on the digital input pins, that is, from all 0s to
all 1s or vice versa.
Zero-Code Error Drift
Digital Crosstalk
Zero-code error drift is a measure of the change in zero-code
error with a change in temperature. It is expressed in µV/°C.
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s or vice versa) in the input register of another DAC.
It is measured in standalone mode and is expressed in nV-s.
Gain Error Drift
Gain error drift is a measure of the change in gain error with
changes in temperature. It is expressed in (ppm of full-scale
range)/°C.
Analog Crosstalk
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code (0xFFFF) is loaded into the DAC register. Ideally, the
output should be VDD – 1 LSB. Full-scale error is expressed as a
percentage of the full-scale range. Figure 25 shows a plot of
typical full-scale error vs. temperature.
code change (all 0s to all 1s or vice versa) while keeping
LDAC
low and monitoring the output of
high, and then pulsing
LDAC
the DAC whose digital code has not changed. The area of the
glitch is expressed in nV-s.
Rev. G | Page 19 of 32
AD5628/AD5648/AD5668
Data Sheet
DAC-to-DAC Crosstalk
Total Harmonic Distortion (THD)
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
output change of another DAC. This includes both digital and
analog crosstalk. It is measured by loading one of the DACs
with a full-scale code change (all 0s to all 1s or vice versa) with
Total harmonic distortion is the difference between an ideal
sine wave and its attenuated version using the DAC. The sine
wave is used as the reference for the DAC, and the THD is a
measure of the harmonics present on the DAC output. It is
measured in decibels.
low and monitoring the output of another DAC. The
LDAC
energy of the glitch is expressed in nV-s.
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
Rev. G | Page 20 of 32
Data Sheet
AD5628/AD5648/AD5668
THEORY OF OPERATION
D/A SECTION
R
R
R
The AD5628/AD5648/AD5668 DACs are fabricated on a
CMOS process. The architecture consists of a string of DACs
followed by an output buffer amplifier. Each part includes an
internal 1.25 V/2.5 V, 5 ppm/°C reference with an internal gain
of 2. Figure 55 shows a block diagram of the DAC architecture.
TO OUTPUT
AMPLIFIER
V
DD
V
REFIN
OUTPUT
AMPLIFIER
(GAIN = ×2)
REF
DAC
REGISTER
V
OUT
R
R
RESISTOR
STRING
GND
Figure 55. DAC Architecture
Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by
Figure 56. Resistor String
INTERNAL REFERENCE
D
VOUT VREFIN
The AD5628/AD5648/AD5668 have an on-chip reference with
an internal gain of 2. The AD5628/AD5648/AD5668-1 have a
1.25 V, 5 ppm/°C reference, giving a full-scale output of 2.5 V;
the AD5628/AD5648/AD5668-2, -3 have a 2.5 V, 5 ppm/°C
reference, giving a full-scale output of 5 V. The on-board
reference is off at power-up, allowing the use of an external
reference. The internal reference is enabled via a write to the
control register (see Table 8).
2N
The ideal output voltage when using the internal reference is
given by
D
VOUT 2VREFOUT
2N
where:
D = decimal equivalent of the binary code that is loaded to the
DAC register.
0 to 4095 for AD5628 (12 bits).
0 to 16,383 for AD5648 (14 bits).
0 to 65,535 for AD5668 (16 bits).
N = the DAC resolution.
The internal reference associated with each part is available at
the VREFOUT pin. A buffer is required if the reference output is
used to drive external loads. When using the internal reference,
it is recommended that a 100 nF capacitor be placed between
the reference output and GND for reference stability.
Individual channel power-down is not supported while using
the internal reference.
RESISTOR STRING
The resistor string section is shown in Figure 56. It is simply a
string of resistors, each of value R. The code loaded into the
DAC register determines at which node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
Rev. G | Page 21 of 32
AD5628/AD5648/AD5668
Data Sheet
Table 8. Command Definitions
Command
OUTPUT AMPLIFIER
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to VDD. The
amplifier is capable of driving a load of 2 kΩ in parallel with
200 pF to GND. The source and sink capabilities of the output
amplifier can be seen in Figure 32 and Figure 33. The slew rate
is 1.5 V/μs with a ¼ to ¾ scale settling time of 7 μs.
C3 C2 C1 C0 Description
0
0
0
0
0
0
0
0
1
0
1
0
Write to Input Register n
Update DAC Register n
Write to Input Register n, update all
(software LDAC)
0
0
0
0
0
1
1
–
1
0
1
1
1
1
0
0
–
1
1
0
0
1
1
0
0
–
1
1
0
1
0
1
0
1
–
1
Write to and update DAC Channel n
Power down/power up DAC
Load clear code register
Load LDAC register
Reset (power-on reset)
Set up internal REF register
Reserved
SERIAL INTERFACE
The AD5628/AD5648/AD5668 have a 3-wire serial interface
SYNC
(
, SCLK, and DIN) that is compatible with SPI, QSPI, and
MICROWIRE interface standards as well as most DSPs. See
Figure 2 for a timing diagram of a typical write sequence.
Reserved
Reserved
SYNC
The write sequence begins by bringing the
line low. Data
from the DIN line is clocked into the 32-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 50 MHz, making the AD5628/AD5648/AD5668 compatible
with high speed DSPs. On the 32nd falling clock edge, the last
data bit is clocked in and the programmed function is executed,
that is, a change in DAC register contents and/or a change in
Table 9. Address Commands
Address (n)
A3
0
A2
0
A1
0
A0
0
Selected DAC Channel
DAC A
SYNC
the mode of operation. At this stage, the
line can be kept
0
0
0
1
DAC B
low or be brought high. In either case, it must be brought high
for a minimum of 15 ns before the next write sequence so that a
0
0
0
0
0
1
1
1
0
0
1
0
DAC C
DAC D
DAC E
SYNC
SYNC
falling edge of
can initiate the next write sequence.
should be idled low between write sequences for even lower
power operation of the part. As is mentioned previously,
0
0
1
1
0
1
1
0
DAC F
DAC G
SYNC
however,
write sequence.
must be brought high again just before the next
0
1
1
1
1
1
1
1
DAC H
All DACs
Rev. G | Page 22 of 32
Data Sheet
AD5628/AD5648/AD5668
INTERRUPT
SYNC
INPUT SHIFT REGISTER
SYNC
In a normal write sequence, the
32 falling edges of SCLK, and the DAC is updated on the 32nd
SYNC SYNC
is brought
line is kept low for
The input shift register is 32 bits wide. The first four bits are
don’t cares. The next four bits are the command bits, C3 to C0
(see Table 8), followed by the 4-bit DAC address, A3 to A0 (see
Table 9) and finally the 16-/14-/12-bit data-word. The data-
word comprises the 16-/14-/12-bit input code followed by four,
six, or eight don’t care bits for the AD5668, AD5648, and
AD5628, respectively (see Figure 57 through Figure 59). These
data bits are transferred to the DAC register on the 32nd falling
edge of SCLK.
falling edge and rising edge of
. However, if
high before the 32nd falling edge, this acts as an interrupt to the
write sequence. The shift register is reset, and the write sequence
is seen as invalid. Neither an update of the DAC register contents
nor a change in the operating mode occurs (see Figure 60).
DB31 (MSB)
DB0 (LSB)
X
X
X
X
X
X
X
X
C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
X
X
X
X
X
DATA BITS
COMMAND BITS
ADDRESS BITS
Figure 57. AD5668 Input Register Contents
DB31 (MSB)
DB0 (LSB)
X
X
C3 C2 C1 C0 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
X
DATA BITS
COMMAND BITS
ADDRESS BITS
Figure 58. AD5648 Input Register Contents
DB31 (MSB)
DB0 (LSB)
X
X
C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
X
X
X
DATA BITS
COMMAND BITS
ADDRESS BITS
Figure 59. AD5628 Input Register Contents
SCLK
SYNC
DIN
DB31
DB0
DB31
DB0
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 32ND FALLING EDGE
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 32ND FALLING EDGE
SYNC
Figure 60.
Interrupt Facility
Rev. G | Page 23 of 32
AD5628/AD5648/AD5668
Data Sheet
advantage that the output impedance of the part is known while
the part is in power-down mode. There are three different
options. The output is connected internally to GND through
either a 1 kΩ or a 100 kΩ resistor, or it is left open-circuited
(three-state). The output stage is illustrated in Figure 61.
INTERNAL REFERENCE REGISTER
The on-board reference is off at power-up by default. This allows
the use of an external reference if the application requires it. The
on-board reference can be turned on or off by a user-program-
mable internal REF register by setting Bit DB0 high or low (see
Table 10). Command 1000 is reserved for setting the internal
REF register (see Table 8). Table 12 shows how the state of the
bits in the input shift register corresponds to the mode of
operation of the device.
The bias generator of the selected DAC(s), output amplifier,
resistor string, and other associated linear circuitry are shut
down when the power-down mode is activated. The internal
reference is powered down only when all channels are powered
down. However, the contents of the DAC register are unaffected
when in power-down. The time to exit power-down is typically
4 µs for VDD = 5 V and for VDD = 3 V. See Figure 41 for a plot.
POWER-ON RESET
The AD5628/AD5648/AD5668 family contains a power-on
reset circuit that controls the output voltage during power-up.
The AD5628/AD5648/AD5668-1, -2 DAC output powers up to
0 V, and the AD5668-3 DAC output powers up to midscale. The
output remains powered up at this level until a valid write
sequence is made to the DAC. This is useful in applications
where it is important to know the state of the output of the DAC
while it is in the process of powering up. There is also a software
executable reset function that resets the DAC to the power-on
reset code. Command 0111 is reserved for this reset function
Any combination of DACs can be powered up by setting PD1
and PD0 to 0 (normal operation). The output powers up to the
value in the input register (
low) or to the value in the
LDAC
DAC register before powering down (
high).
LDAC
CLEAR CODE REGISTER
The AD5628/AD5648/AD5668 have a hardware
pin that
CLR
input is falling edge
is an asynchronous clear input. The
CLR
line low clears the contents of the
(see Table 8). Any events on
or during power-on
LDAC CLR
sensitive. Bringing the
CLR
input register and the DAC registers to the data contained in
the user-configurable register and sets the analog outputs
reset are ignored.
CLR
POWER-DOWN MODES
accordingly. This function can be used in system calibration to load
zero scale, midscale, or full scale to all channels together. These
clear code values are user-programmable by setting two bits,
The AD5628/AD5648/AD5668 contain four separate modes
of operation. Command 0100 is reserved for the power-down
function (see Table 8). These modes are software-programmable
by setting two bits, Bit DB9 and Bit DB8, in the control register.
Bit DB1 and Bit DB0, in the
control register (see Table 14).
CLR
The default setting clears the outputs to 0 V. Command 0101 is
reserved for loading the clear code register (see Table 8).
Table 12 shows how the state of the bits corresponds to the
mode of operation of the device. Any or all DACs (DAC H to
DAC A) can be powered down to the selected mode by setting
the corresponding eight bits (DB7 to DB0) to 1. See Table 13 for
the contents of the input shift register during power-down/power-
up operation. When using the internal reference, only all channel
power-down to the selected modes is supported.
The part exits clear code mode on the 32nd falling edge of the next
write to the part. If
is activated during a write sequence, the
CLR
write is aborted.
The
pulse activation time—the falling edge of
to
CLR
CLR
when the output starts to change—is typically 280 ns. However, if
outside the DAC linear region, it typically takes 520 ns after
When both bits are set to 0, the part works normally with its
normal power consumption of 1.3 mA at 5 V. However, for the
three power-down modes, the supply current falls to 0.4 µA at
5 V (0.2 µA at 3 V). Not only does the supply current fall, but
the output stage is also internally switched from the output of
the amplifier to a resistor network of known values. This has the
executing
for the output to start changing (see Figure 51).
CLR
See Table 15 for contents of the input shift register during the
loading clear code register operation.
Rev. G | Page 24 of 32
Data Sheet
AD5628/AD5648/AD5668
Table 10. Internal Reference Register
Internal REF Register (DB0)
Action
0
1
Reference off (default)
Reference on
Table 11. 32-Bit Input Shift Register Contents for Reference Set-Up Command
MSB
LSB
DB31 to DB28
X
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19 to DB1
X
DB0
1
0
0
0
X
X
X
X
1/0
Don’t cares
Command bits (C3 to C0)
Address bits (A3 to A0)—don’t cares
Don’t cares
Internal REF
register
Table 12. Power-Down Modes of Operation
DB9
DB8
Operating Mode
Normal operation
Power-down modes
1 kΩ to GND
100 kΩ to GND
Three-state
0
0
0
1
1
1
0
1
Table 13. 32-Bit Input Shift Register Contents for Power-Down/Power-Up Function
MSB
LSB
DB31
to
DB19
to
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
X
0
1
0
0
X
X
X
X
X
PD1
PD0
DAC
H
DAC
G
DAC
F
DAC
E
DAC
D
DAC
C
DAC
B
DAC
A
Don’t
cares
Command bits (C3 to C0)
Address bits (A3 to A0)—
don’t cares
Don’t
cares
Power-
down mode
Power-down/power-up channel selection—set bit to 1 to select
RESISTOR
STRING DAC
AMPLIFIER
V
OUT
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
Figure 61. Output Stage During Power-Down
Table 14. Clear Code Register
Clear Code Register
DB1
CR1
0
DB0
CR0
0
Clears to Code
0x0000
0
1
0x8000
1
0
0xFFFF
1
1
No operation
Table 15. 32-Bit Input Shift Register Contents for Clear Code Function
MSB
LSB
DB0
CR0
DB31 to DB28
X
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19 to DB2
X
DB1
0
1
0
1
X
X
X
X
CR1
Don’t cares
Command bits (C3 to C0)
Address bits (A3 to A0)—don’t cares
Don’t cares
Clear code register
Rev. G | Page 25 of 32
AD5628/AD5648/AD5668
Data Sheet
pin. See Table 17 for the contents of the input shift register
during the load register mode of operation.
FUNCTION
LDAC
LDAC
The outputs of all DACs can be updated simultaneously using
the hardware
pin.
POWER SUPPLY BYPASSING AND GROUNDING
LDAC
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the board.
The printed circuit board containing the AD5628/AD5648/
AD5668 should have separate analog and digital sections. If the
AD5628/AD5648/AD5668 are in a system where other devices
require an AGND-to-DGND connection, the connection should
be made at one point only. This ground point should be as close
as possible to the AD5628/AD5648/AD5668.
Synchronous
: After new data is read, the DAC registers
LDAC
are updated on the falling edge of the 32nd SCLK pulse.
can be permanently low or pulsed as in Figure 2.
LDAC
Asynchronous
time that the input registers are written to. When
low, the DAC registers are updated with the contents of the
input register.
: The outputs are not updated at the same
LDAC
goes
LDAC
The power supply to the AD5628/AD5648/AD5668 should be
bypassed with 10 µF and 0.1 µF capacitors. The capacitors
should physically be as close as possible to the device, with the
0.1 µF capacitor ideally right up against the device. The 10 µF
capacitors are the tantalum bead type. It is important that the
0.1 µF capacitor has low effective series resistance (ESR) and
low effective series inductance (ESI), such as is typical of
common ceramic types of capacitors. This 0.1 µF capacitor
provides a low impedance path to ground for high frequencies
caused by transient currents due to internal logic switching.
Alternatively, the outputs of all DACs can be updated simulta-
neously using the software
function by writing to Input
LDAC
Register n and updating all DAC registers. Command 0011 is
reserved for this software function.
LDAC
register gives the user extra flexibility and control
An
LDAC
over the hardware
pin. This register allows the user to
LDAC
select which combination of channels to simultaneously update
when the hardware pin is executed. Setting the bit
LDAC
register to 0 for a DAC channel means that this channel’s update
is controlled by the pin. If this bit is set to 1, this channel
LDAC
The power supply line should have as large a trace as possible to
provide a low impedance path and reduce glitch effects on the
supply line. Clocks and other fast switching digital signals should
be shielded from other parts of the board by digital ground. Avoid
crossover of digital and analog signals if possible. When traces
cross on opposite sides of the board, ensure that they run at right
angles to each other to reduce feedthrough effects through the
board. The best board layout technique is the microstrip technique,
where the component side of the board is dedicated to the ground
plane only and the signal traces are placed on the solder side.
However, this is not always possible with a 2-layer board.
LDAC
updates synchronously; that is, the DAC register is updated
after new data is read, regardless of the state of the pin. It
LDAC
pin as being tied low. (See Table 16
effectively sees the
LDAC
register mode of operation.) This flexibility is
for the
LDAC
useful in applications where the user wants to simultaneously
update select channels while the rest of the channels are
synchronously updating.
Writing to the DAC using command 0110 loads the 8-bit
LDAC
register (DB7 to DB0). The default for each channel is 0, that is,
the pin works normally. Setting the bits to 1 means the
LDAC
DAC channel is updated regardless of the state of the
LDAC
Table 16.
Register
LDAC
Load DAC Register
Bits (DB7 to DB0)
Pin
Operation
LDAC
LDAC
1/0
X—don’t care
LDAC
Determined by LDAC pin.
DAC channels update, overriding the LDAC pin. DAC channels see LDAC as 0.
0
1
Table 17. 32-Bit Input Shift Register Contents for
Register Function
LDAC
MSB
LSB
DB31
to
DB19
to
DB28
DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
X
0
1
1
0
X
X
X
X
X
DAC
H
DAC
G
DAC
F
DAC
E
DAC
D
DAC
C
DAC
B
DAC
A
Don’t
cares
Command bits (C3 to C0)
Address bits (A3 to A0)—
don’t cares
Don’t
cares
LDAC
LDAC
pin
Setting
bit to 1 overrides
Rev. G | Page 26 of 32
Data Sheet
AD5628/AD5648/AD5668
OUTLINE DIMENSIONS
5.10
5.00
4.90
14
8
7
4.50
4.40
4.30
6.40
BSC
1
PIN 1
0.65 BSC
1.05
1.00
0.80
1.20
MAX
0.20
0.09
0.75
0.60
0.45
8°
0°
0.15
0.05
COPLANARITY
0.10
SEATING
PLANE
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 62. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 63. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
Rev. G | Page 27 of 32
AD5628/AD5648/AD5668
Data Sheet
4.10
4.00 SQ
3.90
0.35
0.30
0.25
PIN 1
INDICATOR
PIN 1
INDICATOR
13
16
0.65
BSC
12
1
EXPOSED
PAD
2.70
2.60 SQ
2.50
4
9
8
5
0.45
0.40
0.35
0.20 MIN
TOP VIEW
BOTTOM VIEW
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
Figure 64. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-16-17)
Dimensions shown in millimeters
2.645
2.605 SQ
2.565
4
3
2
1
A
B
C
D
BALL A1
IDENTIFIER
1.50
REF
0.50
REF
TOP VIEW
(BALL SIDE DOWN)
BOTTOM VIEW
(BALL SIDE UP)
0.650
0.595
0.540
SIDE VIEW
COPLANARITY
0.05
0.340
0.320
0.300
SEATING
PLANE
0.270
0.240
0.210
Figure 65. 16-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-16-16)
Dimensions shown in millimeters
Rev. G | Page 28 of 32
Data Sheet
AD5628/AD5648/AD5668
ORDERING GUIDE
Package
Option
Power-On
Reset to Code
Internal
Reference
Model1
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package Description
14-Lead TSSOP
14-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
Accuracy
1 LSB INL
1 LSB INL
1 LSB INL
1 LSB INL
2 LSB INL
2 LSB INL
2 LSB INL
2 LSB INL
1 LSB INL
1 LSB INL
4 LSB INL
4 LSB INL
4 LSB INL
4 LSB INL
8 LSB INL
8 LSB INL
AD5628BRUZ-1
AD5628BRUZ-1REEL7
AD5628BRUZ-2
AD5628BRUZ-2REEL7
AD5628ARUZ-2
AD5628ARUZ-2REEL7
AD5628ACPZ-1-RL7
AD5628ACPZ-2-RL7
AD5628BCPZ-2-RL7
AD5628BCBZ-1-RL7
AD5648BRUZ-1
AD5648BRUZ-1REEL7
AD5648BRUZ-2
AD5648BRUZ-2REEL7
AD5648ARUZ-2
AD5648ARUZ-2REEL7
AD5668BRUZ-1
AD5668BRUZ-1REEL7
AD5668BRUZ-2
AD5668BRUZ-2REEL7
AD5668BRUZ-3
AD5668BRUZ-3REEL7
AD5668ARUZ-2
RU-14
RU-14
RU-16
RU-16
RU-16
RU-16
CP-16-17
CP-16-17
CP-16-17
CB-16-16
RU-14
RU-14
RU-16
RU-16
RU-16
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
1.25 V
1.25 V
2.5 V
2.5 V
2.5 V
2.5 V
1.25 V
2.5 V
2.5 V
1.25 V
1.25 V
1.25 V
2.5 V
2.5 V
2.5 V
2.5 V
16-Lead TSSOP
16-Lead TSSOP
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead WLCSP
14-Lead TSSOP
14-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
16-Lead TSSOP
RU-16
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
Zero
Zero
Zero
Zero
Midscale
Midscale
Zero
16 LSB INL 1.25 V
16 LSB INL 1.25 V
16 LSB INL 2.5 V
16 LSB INL 2.5 V
16 LSB INL 2.5 V
16 LSB INL 2.5 V
32 LSB INL 2.5 V
32 LSB INL 2.5 V
32 LSB INL 2.5 V
32 LSB INL 2.5 V
16 LSB INL 1.25 V
16 LSB INL 1.25 V
16 LSB INL 2.5 V
16 LSB INL 2.5 V
32 LSB INL 2.5 V
32 LSB INL 2.5 V
16 LSB INL 1.25 V
AD5668ARUZ-2REEL7
AD5668ARUZ-3
Zero
16-Lead TSSOP
16-Lead TSSOP
RU-16
RU-16
Midscale
Midscale
Zero
Zero
Zero
Zero
Zero
Midscale
Zero
AD5668ARUZ-3REEL7
AD5668BCPZ-1-RL7
AD5668BCPZ-1500RL7
AD5668BCPZ-2-RL7
AD5668BCPZ-2500RL7
AD5668ACPZ-2-RL7
AD5668ACPZ-3-RL7
AD5668BCBZ-1-RL7
EVAL-AD5668SDCZ
EVAL-AD5668SDRZ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead WLCSP
LFCSP Evaluation Board
TSSOP Evaluation Board
CP-16-17
CP-16-17
CP-16-17
CP-16-17
CP-16-17
CP-16-17
CB-16-16
1 Z = RoHS Compliant Part.
Rev. G | Page 29 of 32
AD5628/AD5648/AD5668
NOTES
Data Sheet
Rev. G | Page 30 of 32
Data Sheet
NOTES
AD5628/AD5648/AD5668
Rev. G | Page 31 of 32
AD5628/AD5648/AD5668
NOTES
Data Sheet
©2005–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05302-0-1/13(G)
Rev. G | Page 32 of 32
相关型号：
EVAL-AD5668SDRZ
Octal, 12-/14-/16-Bit SPI Voltage Output denseDAC with 5 ppm/°C On-Chip Reference
ADI
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