EVAL-AD7156EBZ [ADI]
Ultralow Power, 1.8 V, 3 mm × 3 mm, 2-Channel Capacitance Converter; 超低功耗， 1.8 V为3mm ×3毫米， 2通道电容式转换器
| 型号： | EVAL-AD7156EBZ |
| 厂家： | 
ADI |
| 描述： | Ultralow Power, 1.8 V, 3 mm × 3 mm, 2-Channel Capacitance Converter |
| 文件： | 总28页 (文件大小：388K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultralow Power, 1.8 V, 3 mm × 3 mm,
2-Channel Capacitance Converter
AD7156
FEATURES
GENERAL DESCRIPTION
Ultralow power
The AD7156 delivers a complete signal processing solution for
capacitive sensors, featuring an ultralow power converter with
fast response time.
Power supply voltage: 1.8 V to 3.6 V
Operation power supply current: 70 μA typical
Power-down current: 2 μA typical
Fast response time
Conversion time: 10 ms per channel
Wake-up time from serial interface: 300 μs
Adaptive environmental compensation
2 capacitance input channels
Sensor capacitance (CSENS): 0 pF up to 13 pF
Sensitivity up to 3 fF
The AD7156 uses an Analog Devices, Inc., capacitance-to-
digital converter (CDC) technology, which combines features
important for interfacing to real sensors, such as high input
sensitivity and high tolerance of both input parasitic ground
capacitance and leakage current.
The integrated adaptive threshold algorithm compensates for
any variations in the sensor capacitance due to environmental
factors like humidity and temperature or due to changes in the
dielectric material over time.
2 modes of operation
Standalone with fixed settings
Interfaced to a microcontroller for user-defined settings
2 detection output flags
2-wire serial interface (I2C-compatible)
Operating temperature: −40°C to +85°C
10-lead LFCSP package (3 mm × 3 mm × 0.8 mm)
By default, the AD7156 operates in standalone mode using the
fixed power-up settings and indicates detection on two digital
outputs. Alternatively, the AD7156 can be interfaced to a micro-
controller via the serial interface, the internal registers can be
programmed with user-defined settings, and the data and status
can be read from the part.
APPLICATIONS
The AD7156 operates with a 1.8 V to 3.6 V power supply. It is
specified over the temperature range of −40°C to +85°C.
Buttons and switches
Proximity sensing
Contactless switching
Position detection
Level detection
Portable products
FUNCTIONAL BLOCK DIAGRAM
VDD
CIN1
SCL
SDA
DIGITAL
FILTER
SERIAL
INTERFACE
C
C
SENS1
Σ-Δ CDC
AD7156
EXC1
CIN2
MUX
THRESHOLD
OUT1
OUT2
SENS2
EXCITATION
EXC2
THRESHOLD
GND
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
AD7156
TABLE OF CONTENTS
Features .............................................................................................. 1
Fixed Threshold Registers......................................................... 18
Sensitivity Registers ................................................................... 18
Timeout Registers....................................................................... 18
Setup Registers............................................................................ 19
Configuration Register .............................................................. 20
Power-Down Timer Register.................................................... 21
CAPDAC Registers .................................................................... 21
Serial Number Register.............................................................. 21
Chip ID Register......................................................................... 21
Serial Interface ................................................................................ 22
Read Operation........................................................................... 22
Write Operation.......................................................................... 22
AD7156 Reset ............................................................................. 23
General Call ................................................................................ 23
Hardware Design Considerations ................................................ 24
Overview ..................................................................................... 24
Parasitic Capacitance to Ground.............................................. 24
Parasitic Resistance to Ground................................................. 24
Parasitic Parallel Resistance ...................................................... 24
Parasitic Serial Resistance ......................................................... 25
Input Overvoltage Protection................................................... 25
Input EMC Protection ............................................................... 25
Power Supply Decoupling and Filtering.................................. 25
Application Examples ................................................................ 26
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 27
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 11
Capacitance-to-Digital Converter............................................ 11
CAPDAC ..................................................................................... 11
Comparator and Threshold Modes.......................................... 12
Adaptive Threshold.................................................................... 12
Sensitivity..................................................................................... 12
Data Average ............................................................................... 13
Hysteresis..................................................................................... 13
Timeout........................................................................................ 13
Auto-DAC Adjustment.............................................................. 14
Power-Down Timer ................................................................... 14
Register Descriptions ..................................................................... 15
Status Register............................................................................. 16
Data Registers ............................................................................. 17
Average Registers........................................................................ 18
REVISION HISTORY
10/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD7156
SPECIFICATIONS
VDD = 1.8 V to 3.6 V, GND = 0 V, temperature range = −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit1
Test Conditions/Comments
CAPACITIVE INPUT
Conversion Input Range, CIN to EXC2, 3
3.2
1.6
0.8
0.4
4
2
1
0.5
2.0
1.6
1.4
1.0
50
pF
pF
pF
pF
fF
fF
fF
fF
pF
4 pF input range
2 pF input range
1 pF input range
0.5 pF input range
4 pF input range
2 pF input range
1 pF input range
0.5 pF input range
Resolution4, 5
Maximum Allowed Capacitance, CIN to GND4, 6
See Figure 4, Figure 5, and
Figure 6
Minimum Allowed Resistance, CIN to GND4, 6
Maximum Allowed Serial Resistance4, 6
Gain Error
10
50
MΩ
kΩ
%
%FSR
%
See Figure 10 and Figure 11
See Figure 14
−20
−2
+20
+2
Gain Deviation over Temperature4
Gain Matching Between Ranges4
Offset Error4
0.5
See Figure 17
50
5
fF
fF
CIN and EXC pins disconnected
CIN and EXC pins disconnected
See Figure 16
Offset Deviation over Temperature4
Integral Nonlinearity (INL)4
Channel-to-Channel Isolation4
Power Supply Rejection4
CAPDAC
0.05
60
4
%
dB
fF/V
Full Range
10
25
12.5
200
pF
fF
Resolution (LSB)4
Differential Nonlinearity (DNL)4
Auto-DAC Increment/Decrement4, 7
EXCITATION
0.25
75
LSB
% of CIN range
Voltage4, 7
VDD/2
V
Frequency
16
1000
kHz
pF
See Figure 18
See Figure 7, Figure 8, and
Figure 9
Maximum Allowed Capacitance EXC to GND4, 6
Minimum Allowed Resistance EXC to GND4, 6
LOGIC OUTPUTS (OUT1, OUT2)
1
MΩ
See Figure 12 and Figure 13
Output Low Voltage (VOL
Output High Voltage (VOH
)
0.4
V
V
ISINK = −3 mA
ISOURCE = +3 mA
)
VDD – 0.6
70
SERIAL INTERFACE INPUTS (SCL, SDA)
Input High Voltage (VIH)
Input Low Voltage (VIL)
Input Leakage Current
Input Pin Capacitance
% of VDD
% of VDD
μA
25
5
0.1
6
pF
OPEN-DRAIN OUTPUT (SDA)
Output Low Voltage (VOL
)
0.4
5
V
I
SINK = −6.0 mA
Output High Leakage Current (IOH
)
0.1
μA
VOUT = VDD
Rev. 0 | Page 3 of 28
AD7156
Parameter
Min
Typ
Max
Unit1
Test Conditions/Comments
POWER REQUIREMENTS
VDD-to-GND Voltage
IDD Current4, 8
1.8
3.6
75
85
10
17
V
65
70
2
μA
μA
μA
μA
VDD ≤ 2.7 V, see Figure 20
VDD = 3.6 V, see Figure 20
VDD ≤ 2.7 V, see Figure 21
VDD = 3.6 V, see Figure 21
IDD Current Power-Down Mode4, 8
2
1 Capacitance units: 1 pF = 1 × 10−12 F; 1 fF = 10−15 F.
2 The CAPDAC can be used to shift (offset) the input range. The total capacitance of the sensor can therefore be up to the sum of the CAPDAC value and the conversion
input range. With the auto-DAC feature, the CAPDAC is adjusted automatically when the CDC input value is lower than 25% or higher than 75% of the CDC nominal
input range.
3 The maximum capacitance of the sensor connected between the EXCx and CINx pins is equal to the sum of the minimum guaranteed value of the CAPDAC and the
minimum guaranteed input range.
4 The maximum specification is not production tested but is supported by characterization data at initial product release.
5 The resolution of the converter is not limited by the output data format or output data LSB (least significant bit) size, but by the converter and system noise level. The
noise-free resolution is defined as level of peak-to-peak noise coming from the converter itself, with no connection to the CIN and EXC pins.
6 These specifications are understood separately. Any combination of the capacitance to ground and serial resistance may result in additional errors, for example gain
error, gain drift, offset error, offset drift, and power supply rejection.
7 Specification is not production tested but is guaranteed by design.
8 Digital inputs equal to VDD or GND.
Rev. 0 | Page 4 of 28
AD7156
TIMING SPECIFICATIONS
VDD = 1.8 V to 3.6 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = VDD, temperature range = −40°C to +85°C, unless otherwise noted.
Table 2.
Parameter
Min Typ Max
Unit
Test Conditions/Comments
CONVERTER
Conversion Time1
20
ms
ms
ms
ms
Both channels, 10 ms per channel.
Wake-Up Time from Power-Down Mode2, 3
Power-Up Time2, 4
0.3
2
2
Reset Time2, 5
SERIAL INTERFACE6, 7
See Figure 2.
SCL Frequency
0
0.6
1.3
400
kHz
μs
μs
μs
μs
μs
μs
μs
μs
ns
μs
SCL High Pulse Width, tHIGH
SCL Low Pulse Width, tLOW
SCL, SDA Rise Time, tR
0.3
0.3
SCL, SDA Fall Time, tF
Hold Time (Start Condition), tHD;STA
Setup Time (Start Condition), tSU;STA
Data Setup Time, tSU;DAT
Setup Time (Stop Condition), tSU;STO
Data Hold Time (Master), tHD;DAT
Bus-Free Time (Between Stop and Start Conditions), tBUF
0.6
0.6
0.1
0.6
10
After this period, the first clock is generated.
Relevant for repeated start condition.
1.3
1 Conversion time is 304 internal clock cycles for both channels (nominal clock 16 kHz); the internal clock frequency is equal to the specified excitation frequency.
2 Specification is not production tested but is supported by characterization data at initial product release.
3 Wake-up time is the maximum delay between the last SCL edge writing the configuration register and the start of conversion.
4 Power-up time is the maximum delay between the VDD crossing the minimum level (1.8 V) and either the start of conversion or when ready to receive a serial
interface command.
5 Reset time is the maximum delay between the last SCL edge writing the reset command and either the start of conversion or when ready to receive a serial
interface command.
6 Sample tested during initial release to ensure compliance.
7 All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Output load = 10 pF.
tR
tF
tLOW
tHD;STA
SCL
SDA
tHIGH
tSU;STA
tSU;STO
tHD;STA
tHD;DAT
tSU;DAT
tBUF
S
P
S
P
Figure 2. Serial Interface Timing Diagram
Rev. 0 | Page 5 of 28
AD7156
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
Positive Supply Voltage VDD to GND
−0.3 V to +3.9 V
Voltage on Any Input or Output to GND
ESD Rating
–0.3V toVDD + 0.3 V
ESD Association Human Body Model, S5.1
Field-Inducted Charged Device Model
4 kV
500 V
ESD CAUTION
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
LFCSP Package
−40°C to +85°C
–65°C to +150°C
150°C
49°C/W
3°C/W
θJA, Thermal Impedance to Air
θJC, Thermal Impedance to Case
Reflow Soldering (Pb-Free)
Peak Temperature
260(0/−5)°C
Time at Peak Temperature
10 sec to 40 sec
Rev. 0 | Page 6 of 28
AD7156
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND
VDD
1
2
3
4
5
10 SDA
9
8
7
6
SCL
AD7156
TOP VIEW
(Not to Scale)
CIN2
CIN1
EXC2
OUT2
OUT1
EXC1
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO
GND OR IT MUST BE ISOLATED (FLOATING).
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
GND
VDD
Ground Pin.
Power Supply Voltage. This pin should be decoupled to GND using a low impedance capacitor, such as a
0.1 ꢀF X7R multilayer ceramic capacitor.
CDC Capacitive Input Channel 2. The measured capacitance (sensor) is connected between the EXC2 pin and
the CIN2 pin. If not used, this pin can be left open circuit or be connected to GND. When a conversion is
performed on Channel 2, the CIN2 pin is internally connected to a high impedance input of the Σ-Δ
modulator. When a conversion is performed on the other channel or in idle mode or power-down mode,
the CIN2 pin is internally disconnected and left floating by the part.
CDC Capacitive Input Channel 1. The measured capacitance (sensor) is connected between the EXC1 pin and
the CIN1 pin. If not used, this pin can be left open circuit or be connected to GND. When a conversion is
performed on Channel 1, the CIN1 pin is internally connected to a high impedance input of the Σ-Δ
modulator. When a conversion is performed on the other channel or in idle mode or power-down mode,
the CIN1 pin is internally disconnected and left floating by the part.
CDC Excitation Output Channel 2. The measured capacitance is connected between the EXC2 pin and the
CIN2 pin. If not used, this pin should be left as an open circuit. When a conversion is performed on Channel 2,
the EXC2 pin is internally connected to the output of the excitation signal driver. When a conversion is per-
formed on the other channel or in idle mode or power-down mode, the EXC2 pin is internally connected
to GND.
CDC Excitation Output Channel 1. The measured capacitance is connected between the EXC1 pin and the
CIN1 pin. If not used, this pin should be left as an open circuit. When a conversion is performed on Channel 1,
the EXC1 pin is internally connected to the output of the excitation signal driver. When a conversion is per-
formed on the other channel or in idle mode or power-down mode, the EXC1 pin is internally connected
to GND.
3
4
5
6
CIN2
CIN1
EXC2
EXC1
7
8
9
OUT1
OUT2
SCL
Logic Output Channel 1. A high level on this output indicates proximity detected on CIN1.
Logic Output Channel 2. A high level on this output indicates proximity detected on CIN2.
Serial Interface Clock Input. This pin connects to the master clock line and requires a pull-up resistor if not
provided elsewhere in the system.
10
SDA
Serial Interface Bidirectional Data. This pin connects to the master data line and requires a pull-up resistor if
not provided elsewhere in the system.
Rev. 0 | Page 7 of 28
AD7156
TYPICAL PERFORMANCE CHARACTERISTICS
2.0
1.8
1.6
1.4
1.2
1
0
3.3V
1.8V
–1
–2
–3
–4
1.8V
1.0
0.8
0.6
3.3V
0.4
0.2
0
0
50
100
150
200
250
300
0
500
1000
1500
2000
CAPACITANCE CIN TO GROUND (pF)
CAPACITANCE EXC TO GROUND (pF)
Figure 4. Capacitance Input Offset Error vs. Capacitance CIN to GND,
VDD = 1.8 V and 3.3 V, EXC Pin Open Circuit
Figure 7. Capacitance Input Offset Error vs. Capacitance EXC to GND,
VDD = 1.8 V and 3.3 V, CIN Pin Open Circuit
5
0
1
3.3V
0
1.8V
–5
3.3V
–1
–10
1.8V
–2
–3
–4
–15
–20
–25
0
50
100
150
200
250
300
0
500
1000
1500
2000
CAPACITANCE CIN TO GROUND (pF)
CAPACITANCE EXC TO GROUND (pF)
Figure 5. Capacitance Input Gain Error vs. Capacitance CIN to GND,
VDD = 1.8 V and 3.3 V, CIN to EXC = 3 pF
Figure 8. Capacitance Input Gain Error vs. Capacitance EXC to GND,
VDD = 1.8 V and 3.3 V, CIN to EXC = 3 pF
5
0
1
0
–1
–2
–3
–4
3.3V
3.3V
–5
1.8V
–10
1.8V
–15
–20
–25
0
50
100
150
200
250
300
0
500
1000
1500
2000
CAPACITANCE CIN TO GROUND (pF)
CAPACITANCE EXC TO GROUND (pF)
Figure 9. Capacitance Input Gain Error vs. Capacitance EXC to GND,
VDD = 1.8 V and 3.3 V, CIN to EXC = 9 pF
Figure 6. Capacitance Input Gain Error vs. Capacitance CIN to GND,
VDD = 1.8 V and 3.3 V, CIN to EXC = 9 pF
Rev. 0 | Page 8 of 28
AD7156
2
0
0.2
0
3.3V
3.3V
1.8V
–2
–4
–6
–8
–10
–0.2
–0.4
–0.6
–0.8
–1.0
1.8V
1
10
100
1k
0.1
1
10
100
1k
RESISTANCE CIN TO GND (MΩ)
RESISTANCE EXC TO GROUND (MΩ)
Figure 10. Capacitance Input Gain Error vs. Resistance CIN to GND,
VDD = 1.8 V and 3.3 V, CIN to EXC = 3 pF
Figure 13. Capacitance Input Gain Error vs. Resistance EXC to GND,
VDD = 1.8 V and 3.3 V, CIN to EXC = 9 pF
2
1
0
0
3.3V
3.3V
–1
1.8V
–2
–2
1.8V
–4
–6
–3
–4
–5
–6
–7
–8
–10
1
10
100
1k
0
20
40
60
80
100
RESISTANCE CIN TO GND (MΩ)
SERIAL RESISTANCE (kΩ)
Figure 11. Capacitance Input Gain Error vs. Resistance CIN to GND,
VDD = 1.8 V and 3.3 V, CIN to EXC = 9 pF
Figure 14. Capacitance Input Gain Error vs. Serial Resistance,
VDD = 1.8 V and 3.3 V, CIN to EXC = 3 pF
0.2
10
1.8V
0
1.8V
0
3.3V
–0.2
–10
3.3V
–0.4
–0.6
–0.8
–1.0
–20
–30
–40
–50
0.1
1
10
100
1k
1
10
100
1k
RESISTANCE EXC TO GROUND (MΩ)
PARELLEL RESISTANCE (MΩ)
Figure 15. Capacitance Input Gain Error vs. Parallel Resistance,
VDD = 1.8 V and 3.3 V, CIN to EXC = 3 pF
Figure 12. Capacitance Input Gain Error vs. Resistance EXC to GND,
VDD = 1.8 V and 3.3 V, CIN to EXC = 3 pF
Rev. 0 | Page 9 of 28
AD7156
5
4
20
10
3
2
3.3V
1
1.8V
0
0
–1
–2
–3
–4
–10
–20
–5
–50
–25
0
25
50
75
100
0
5
10
15
20
25
30
TEMPERATURE (°C)
CAPDAC CODE
Figure 16. Capacitance Input Offset Error vs. Temperature,
VDD = 1.8 V and 3.3 V, CIN and EXC Pins Open Circuit
Figure 19. CAPDAC Differential Nonlinearity (DNL), VDD = 1.8 V
0.35
80
3.6V
0.25
0.15
70
2.7V
0.05
2V
60
–0.05
–0.15
–0.25
–0.35
1.8V
50
40
–50
0
50
100
–50
–25
0
25
50
75
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. Capacitance Input Gain Error vs. Temperature,
VDD = 2.7 V, CIN to EXC = 4 pF
Figure 20. Current vs. Temperature,
VDD = 1.8 V, 2 V, 2.7 V, and 3.6 V
16.50
4.0
16.25
16.00
15.75
15.50
15.25
15.00
14.75
14.50
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
2.7V
2V
3.6V
1.8V
3.6V
2.7V
2V
1.8V
75
–50
–25
0
25
50
75
100
–50
–25
0
25
50
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 18. EXC Frequency Error vs. Temperature,
VDD = 1.8 V, 2 V, 2.7 V, and 3.6 V
Figure 21. Power-Down Current vs. Temperature,
VDD = 1.8 V, 2 V, 2.7 V, and 3.6 V
Rev. 0 | Page 10 of 28
AD7156
THEORY OF OPERATION
3.3V
VDD
AD7156
CLOCK
GENERATOR
POWER-DOWN
TIMER
CIN1
SCL
SDA
PROGRAMMING
INTERFACE
DIGITAL
FILTER
SERIAL
INTERFACE
Σ-Δ CDC
C
X1
EXC1
MUX
OUT1
OUT2
THRESHOLD
CAPDAC
CIN2
DIGITAL
OUTPUTS
C
X2
EXC2
EXCITATION
THRESHOLD
GND
Figure 22. AD7156 Block Diagram
The AD7156 core is a high performance capacitance-to-digital
converter (CDC) that allows the part to be interfaced directly
to a capacitive sensor.
CAPACITANCE-TO-DIGITAL CONVERTER
(CDC)
CLOCK
GENERATOR
The comparators compare the CDC results with thresholds, either
fixed or dynamically adjusted by the on-chip adaptive threshold
algorithm engine. Thus, the outputs indicate a defined change in
the input sensor capacitance.
0x0000 TO 0xFFF0
DATA
CIN
Σ-Δ
DIGITAL
FILTER
MODULATOR
C
X
0pF TO 4pF
EXCITATION
EXC
The AD7156 also integrates an excitation source, CAPDAC
for the capacitive inputs, an input multiplexer, a complete clock
generator, a power-down timer, a power supply monitor, control
logic, and an I2C®-compatible serial interface for configuring the
part and accessing the internal CDC data and status, if required
in the system (see Figure 22).
Figure 23. CDC Simplified Block Diagram
CAPDAC
The AD7156 CDC core maximum full-scale input range is 0 pF
to 4 pF. However, the part can accept a higher input capacitance,
caused, for example, by a nonchanging offset capacitance of up to
10 pF. This offset capacitance can be compensated for by using
the programmable on-chip CAPDAC.
CAPACITANCE-TO-DIGITAL CONVERTER
Figure 23 shows the CDC simplified functional diagram. The
converter consists of a second-order Σ-Δ charge balancing
modulator and a third-order digital filter. The measured
capacitance CX is connected between an excitation source
and the Σ-Δ modulator input. The excitation signal is applied
on the CX capacitor during the conversion, and the modulator
continuously samples the charge going through the CX. The
digital filter processes the modulator output, which is a stream
of 0s and 1s containing the information in 0 and 1 density. The
data is processed by the adaptive threshold engine and output
comparators; the data can also be read through the serial interface.
CAPDAC
0x0000 TO 0xFFF0
10pF
DATA
CIN
0pF TO 4pF
C
X
10pF TO 14pF
EXC
Figure 24. Using a CAPDAC
The AD7156 is designed for floating capacitive sensors.
Therefore, both CX plates have to be isolated from ground
or any other fixed potential node in the system.
The CAPDAC can be understood as a negative capacitance
connected internally to a CIN pin. The CAPDAC has a 6-bit
resolution and a monotonic transfer function. Figure 24 shows
how to use the CAPDAC to shift the CDC 0 pF to 4 pF input
range to measure capacitance between 10 pF and 14 pF.
The AD7156 features slew rate limiting on the excitation voltage
output, which decreases the energy of higher harmonics on the
excitation signal and dramatically improves the system electro-
magnetic compatibility (EMC).
Rev. 0 | Page 11 of 28
AD7156
INPUT OUTSIDE THRESHOLD WINDOW
COMPARATOR AND THRESHOLD MODES
POSITIVE
The AD7156 comparators and their thresholds can be
programmed to operate in two modes: fixed and adaptive
threshold modes. In an adaptive mode, the threshold
is dynamically adjusted and the comparator output indicates
fast changes and ignores slow changes in the input (sensor)
capacitance. Alternatively, the threshold can be programmed
as a constant (fixed) value, and the output then indicates any
change in the input capacitance that crosses the defined fixed
threshold.
THRESHOLD
INPUT CAPACITANCE
NEGATIVE
THRESHOLD
OUTPUT ACTIVE
OUTPUT
TIME
Figure 28. Out-Window (Adaptive) Threshold Mode
ADAPTIVE THRESHOLD
The AD7156 logic output (active high) indicates either a positive or
a negative change in the input capacitance, in both adaptive and
fixed threshold modes (see Figure 25 and Figure 26).
In an adaptive mode, the thresholds are dynamically adjusted,
ensuring indication of fast changes (for example, an object
moving close to a capacitive proximity sensor) and eliminating
slow changes in the input (sensor) capacitance, usually caused
by environment changes such as humidity or temperature or
changes in the sensor dielectric material over time (see Figure 29).
POSITIVE CHANGE
POSITIVE
THRESHOLD
INPUT
CAPACITANCE
FAST CHANGE
SLOW CHANGE
OUTPUT ACTIVE
INPUT CAPACITANCE
THRESHOLD
OUTPUT
TIME
OUTPUT ACTIVE
Figure 25. Positive Threshold Mode
Indicates Positive Change in Input Capacitance
OUTPUT
TIME
Figure 29. Adaptive Threshold Indicates Fast Changes and Eliminates Slow
Changes in Input Capacitance
NEGATIVE CHANGE
INPUT
CAPACITANCE
SENSITIVITY
NEGATIVE
THRESHOLD
In adaptive threshold mode, the output comparator threshold
is set as a defined distance (sensitivity) above the data average,
below the data average, or both, depending on the selected
threshold mode of operation (see Figure 30). The sensitivity
value is programmable in the range of 0 LSB to 255 LSB of the
12-bit CDC converter (see the Register Descriptions section).
DATA
OUTPUT ACTIVE
OUTPUT
TIME
Figure 26. Negative Threshold Mode
Indicates Negative Change in Input Capacitance
POSITIVE
Additionally, for the adaptive mode only, the comparators can
work as window comparators, indicating input either inside or
outside a selected sensitivity band (see Figure 27 and Figure 28).
THRESHOLD
SENSITIVITY
DATA AVERAGE
SENSITIVITY
NEGATIVE
THRESHOLD
OUTPUT ACTIVE
POSITIVE
INPUT INSIDE THRESHOLD WINDOW
THRESHOLD
INPUT CAPACITANCE
NEGATIVE
THRESHOLD
TIME
Figure 30. Threshold Sensitivity
OUTPUT ACTIVE
OUTPUT
TIME
Figure 27. In-Window (Adaptive) Threshold Mode
Rev. 0 | Page 12 of 28
AD7156
DATA AVERAGE
TIMEOUT
The adaptive threshold algorithm is based on an average calculated
from the previous CDC output data, using the following equation:
In the case of a large, long change in the capacitive input, when
the data average adapting to a new condition takes too long, a
timeout can be set.
Data(N) − Average(N − 1)
Average(N) = Average(N − 1) +
+ 1
2ThrSettling
The timeout becomes active (counting) when the CDC data
goes outside the band of data average sensitivity. When the
timeout elapses (a defined number of CDC conversions is
counted), the data average (and thus the thresholds), is forced
to follow the new CDC data value immediately (see Figure 33).
where:
Average(N) is the new average value.
Average(N − 1) is the average value from the previous cycle.
Data(N) is the latest complete CDC conversion result.
ThrSettling is a parameter, programmable in the setup registers.
The timeout can be set independently for approaching (for change
in data toward the threshold) and for receding (for change in data
away from the threshold). See Figure 34, Figure 35, and the Register
Descriptions section for further information.
A more specific case of the input capacitance waveform is a step
change. The response of the average to an input capacitance step
change (more exactly, response to a step change in the CDC output
data) is an exponential settling curve, which can be characterized
by the following equation:
DATA AVERAGE
+ SENSITIVITY
LARGE CHANGE IN DATA
DATA AVERAGE
Average(N) = Average(0) + Change(1 − eN /TimeConst
)
DATA AVERAGE
– SENSITIVITY
where:
Average(N) is the value of average N complete CDC conversion
cycles after a step change on the input.
TIME
TIMEOUT
Average(0) is the value before the step change.
TimeConst = 2(ThrSettling + 1)
Figure 33. Threshold Timeout After a Large Change in CDC Data
ThrSettling is a parameter, programmable in the setup registers.
See Figure 31 and the Register Descriptions section for further
information.
TIMEOUT APPROACHING
INPUT
CAPACITANCE
THRESHOLD
INPUT CAPACITANCE
(CDC DATA) CHANGE
DATA AVERAGE
DATA AVERAGE RESPONSE
TIME
OUTPUT ACTIVE
OUTPUT
Figure 31. Data Average Response to Data Step Change
TIME
Figure 34. Approaching Timeout in Negative Threshold Mode
Shortens False Output Trigger
HYSTERESIS
In adaptive threshold mode, the comparator features hysteresis.
The hysteresis is fixed to ¼ of the threshold sensitivity and can
be programmed on or off. The comparator does not have hyster-
esis in the fixed threshold mode.
TIMEOUT RECEDING
LARGE CHANGE
DATA
POSITIVE
THRESHOLD
INPUT
CAPACITANCE
HYSTERSIS
THRESHOLD
OUTPUT ACTIVE
DATA AVERAGE
OUTPUT ACTIVE
OUTPUT
TIME
OUTPUT
TIME
Figure 35. Positive Timeout in Negative Threshold Mode
Shortens Period of Missing Output Trigger
Figure 32. Threshold Hysteresis
Rev. 0 | Page 13 of 28
AD7156
AUTO-DAC ADJUSTMENT
POWER-DOWN TIMER
In adaptive threshold mode, the part can dynamically adjust the
CAPDAC to keep the CDC in an optimal operating capacitive
range. When the auto-DAC function is enabled, the CAPDAC
value is automatically incremented when the data average
exceeds ¾ of the CDC full range (average > 0xA800), and
the CAPDAC value is decremented when the data average
goes below ¼ of the CDC full range (average < 0x5800).
The auto-DAC increment or decrement step depends on
the selected CDC capacitive input range (see the Setup Registers
section).
In power sensitive applications, the AD7156 can be set to
automatically enter power-down mode after a programmed
period of time in which the outputs have not been activated.
The AD7156 can then be returned to a normal operational
mode either via the serial interface or by the power supply
off/on sequence.
When the CAPDAC value reaches 0, the ¼ threshold for further
decrementing is ignored. Similarly, when the CAPDAC value
reaches its full range, the ¾ threshold is ignored. The CDC and
the rest of the algorithm are continuously working, and they are
functional down to a capacitance input of 0 pF or as high as the
capacitance input of (CAPDAC full range + CDC full range),
respectively.
Rev. 0 | Page 14 of 28
AD7156
REGISTER DESCRIPTIONS
Table 5. Register Summary1
Addr Pointer
Register
Dec
Hex
R/W Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Status
0
0x00
R
PwrDown
(0)
DacStep2
OUT2
DacStep1
OUT1
C1/C2
RDY2
(1)
RDY1
(1)
(0)
(1)
(0)
(0)
(1)
Ch 1 Data High
1
2
3
4
5
6
7
8
9
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
R
R
R
R
R
R
R
R
0x00
Ch 1 Data Low
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Ch 2 Data High
Ch 2 Data Low
Ch 1 Average High
Ch 1 Average Low
Ch 2 Average High
Ch 2 Average Low
Ch 1 Sensitivity/
R/W Ch 1 sensitivity (in adaptive threshold mode)/Ch 1 threshold high byte (in fixed threshold mode)
Ch 1 Threshold High
0x08
Ch 1 Timeout/
Ch 1 Threshold Low
10
11
12
13
0x0A
0x0B
0x0C
0x0D
R/W Ch 1 timeout (in adaptive threshold mode)/CH 1threshold low byte (in fixed threshold mode)
0x86
Ch 1 Setup
R/W
RngH1
(0)
RngL1
(0)
Hyst1
(0)
ThrSettling1 (4-bit value)
(0x0B)
(0)
Ch 2 Sensitivity/
Ch 2 Threshold High
R/W Ch 2 sensitivity (in adaptive threshold mode)/Ch 2 threshold high byte (in fixed threshold mode)
0x08
Ch 2 Timeout/
Ch 2 Threshold Low
R/W Ch 2 timeout (in adaptive threshold mode)/Ch 2 threshold low byte (in fixed threshold mode)
0x86
Ch 2 Setup
14
15
16
17
18
0x0E
0x0F
0x10
0x11
0x12
R/W
R/W
R/W
R/W
R/W
RngH2
(0)
RngL2
(0)
Hyst2
(0)
ThrSettling2 (4-bit value)
(0x0B)
(0)
ThrMD0
(0)
Configuration
Power-Down Timer
Ch 1 CAPDAC
Ch 2 CAPDAC
ThrFixed
(0)
ThrMD1
(0)
EnCh1
(1)
EnCh2
(1)
MD2
(0)
MD1
(0)
MD0
(1)
Power-down timeout (6-bit value)
(0)
DacEn1
(1)
(1)
DacAuto1
(1)
(0x00)
DacValue1 (6-bit value)
(0x00)
DacEn2
(1)
DacAuto2
(1)
DacValue2 (6-bit value)
(0x00)
Serial Number 3
Serial Number 2
Serial Number 1
19
20
21
0x13
0x14
0x15
R
R
R
Serial number—Byte 3 (MSB)
Serial number—Byte 2
Serial number—Byte 1
Serial Number 0
Chip ID
22
23
0x16
0x17
R
R
Serial number—Byte 0 (LSB)
Chip identification code
1 The default values are given in parentheses.
Rev. 0 | Page 15 of 28
AD7156
STATUS REGISTER
Address Pointer 0x00
8 Bits, Read Only
Default Value 0x53 Before Conversion, 0x54 After Conversion
The status register indicates the status of the part. The register can be read via the 2-wire serial interface to query the status of the outputs,
check the CDC finished conversion, and check whether the CAPDAC has been changed by the auto-DAC function.
Table 6. Status Register Bit Map1
Bit 7
Bit 6
Bit 5
OUT2
(0)
Bit 4
Bit 3
OUT1
(0)
Bit 2
C1/C2
(0)
Bit 1
RDY2
(1)
Bit 0
RDY1
(1)
PwrDown
(0)
DacStep2
(1)
DacStep1
(1)
1 The default values are given in parentheses.
Table 7. Status Register Bit Descriptions
Bit
Mnemonic
PwrDown
DacStep2
Description
7
PwrDown = 1 indicates that the part is in a power-down.
6
DacStep2 = 0 indicates that the Channel 2 CAPDAC value was changed after the last CDC conversion as part of
the auto-DAC function. The bit value is updated after each finished CDC conversion on this channel.
5
4
3
2
1
OUT2
OUT2 = 1 indicates that the Channel 2 data (CIN2 capacitance) crossed the threshold, according to the selected
comparator mode of operation. The bit value is updated after each finished CDC conversion on this channel.
DacStep1
OUT1
DacStep1 = 0 indicates that the Channel 1 CAPDAC value was changed during the last conversion as part of the
auto-DAC function. The bit value is updated after each finished CDC conversion on this channel.
OUT1 = 1 indicates that the Channel 1 data (CIN1 capacitance) crossed the threshold, according to the selected
comparator mode of operation. The bit value is updated after each finished CDC conversion on this channel.
C1/C2
RDY2
C1/C2 = 0 indicates that the last finished CDC conversion was on Channel 1.
C1/C2 = 1 indicates that the last finished CDC conversion was on Channel 2.
RDY2 = 0 indicates a finished CDC conversion on Channel 2. The bit is reset back to 1 when the Channel 2 data
register is read via the serial interface or after a part reset or power-up.
0
RDY1
RDY1 = 0 indicates a finished CDC conversion on Channel 1. The bit is reset back to 1 when the Channel 1 data
register is read via serial interface or after a part reset or power-up.
Rev. 0 | Page 16 of 28
AD7156
For an ideal part, linear, with no offset error and no gain error,
the input capacitance can be calculated from the output data
using the following equation:
DATA REGISTERS
Ch 1 Address Pointer 0x01, Address Pointer 0x02
Ch 2 Address Pointer 0x03, Address Pointer 0x04
16 Bits, Read Only
Data −12,288
C (pF) =
× Input _ Range (pF)
Default Value 0x0000
40,960
Data from the last complete capacitance-to-digital conversion
reflects the capacitance on the input. Only the 12 MSBs of the
data registers are used for the CDC result. The 4 LSBs are
always 0, as shown in Figure 36.
where Input_Range = 4 pF, 2 pF, 1 pF, or 0.5 pF.
The following is the same equation written with hexadecimal
numbers:
Data − 0x3000
The data register is updated after a finished conversion on the
capacitive channel, with one exception: when the serial interface
read operation from the data register is in progress, the data
register is not updated and the new capacitance conversion
result is lost.
C (pF) =
× Input _ Range (pF)
0xA000
With offset error and gain error included, the equation is:
Data −12,288
C (pF) =
× Input _ Range (pF)×
+ Offset _ Error (pF)
40,960
The stop condition on the serial interface is considered to be
the end of the read operation. Therefore, to prevent incorrect
data reading through the serial interface, the two bytes of a
data register should be read sequentially using the register
address pointer autoincrement feature of the serial interface.
Gain _ Error(%)
⎛
⎜
⎝
⎞
⎟
⎠
1 +
100%
Or the same equation with hexadecimal numbers:
Data − 0x3000
C (pF) =
× Input _ Range (pF) ×
+ Offset _ Error (pF)
The nominal AD7156 CDC transfer function (an ideal transfer
function excluding offset and/or gain error) maps the input
capacitance between zero scale and full scale to output data
codes between 0x3000 and 0xD000 only (see Table 8).
0xA000
Gain_ Error(%)
⎛
⎜
⎝
⎞
⎟
⎠
1 +
100%
MSB
DATA HIGH
DATA LOW
LSB
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
12-BIT CDC RESULT
0
Figure 36. CDC Data Register
Table 8. AD7156 Capacitance-to-Data Mapping1
Data
Input Capacitance
0x0000
0x3000
0x5800
0x8000
0xA800
0xD000
0xFFF0
Under range (below 0 pF)
Zero scale (0 pF)
Quarter scale (+0.5 pF)—auto-DAC step down
Midscale (+1 pF)
Three-quarter scale (+1.5 pF)—auto-DAC step up
Full scale (+2 pF)
Over range (above +2 pF)
1 An ideal part with no offset and gain error, values shown in picofarad for 2 pF capacitance input range.
Rev. 0 | Page 17 of 28
AD7156
For an ideal part with no gain error, the sensitivity can be
calculated using the following equation:
AVERAGE REGISTERS
Ch 1 Address Pointer 0x05, Address Pointer 0x06
Ch 2 Address Pointer 0x07, Address Pointer 0x08
16 Bits, Read Only
Sens _ Reg
Sensitivity (pF) =
× Input _ Range (pF)
2560
Default Value 0x0000
Or the same equation with hexadecimal numbers
These registers show the average calculated from the previous
CDC data. The 12-bit CDC result corresponds to the 12 MSBs
of the average register.
Sens _ Reg
0xA00
Sensitivity (pF) =
× Input _ Range (pF)
With gain error included, the sensitivity can be calculated using
the following equation:
The settling time of the average can be set by programming
the ThrSettling bits in the setup registers. The average register
is overwritten directly with the CDC output data, that is, the
history is erased if the timeout is enabled and elapses.
Sense _ Reg
Sensitivity (pF) =
× Input _ Range (pF)×
2560
Gain_ Error (%)
⎛
⎞
FIXED THRESHOLD REGISTERS
⎜
⎜
⎟
⎟
1+
100%
Ch 1 Address Pointer 0x09, Address Pointer 0x0A
Ch 2 Address Pointer 0x0C, Address Pointer 0x0D
16 Bits, Read/Write, Factory Preset 0x0886
⎝
⎠
Or the same equation with hexadecimal numbers
Sense _ Reg
0xA00
A constant threshold for the output comparator in the fixed
threshold mode can be set using these registers. The 12-bit
CDC result corresponds to the 12 MSBs of the threshold regis-
ter. The fixed threshold registers share the address pointer and
location on chip with the sensitivity and timeout registers. The
fixed threshold registers are not accessible in the adaptive thre-
shold mode.
Sensitivity (pF) =
× Input _ Range (pF)×
Gain _ Error (%)
⎛
⎞
⎜
⎜
⎟
⎟
1+
100%
⎝
⎠
TIMEOUT REGISTERS
Ch 1 Address Pointer 0x0A
Ch 2 Address Pointer 0x0D
8 Bits, Read/Write, Factory Preset 0x86
SENSITIVITY REGISTERS
Ch 1 Address Pointer 0x09
Ch 2 Address Pointer 0x0C
8 Bits, Read/Write, Factory Preset 0x08
Table 9. Timeout Register Bit Map
Bit
Mnemonic
TimeOutApr
TimeOutRec
Default
0x08
[7:4]
[3:0]
Sensitivity registers set the distance of the positive threshold above
the data average, and the distance of the negative threshold below
the data average, in the adaptive threshold mode.
DATA
0x06
These registers set timeouts for the adaptive threshold mode.
The approaching timeout starts when the CDC data crosses the
data average sensitivity band toward the threshold, according
to the selected positive, negative, or window threshold mode.
The approaching timeout elapses after the number of conversion
cycles equals 2TimeOutApr, where TimeOutApr is the value of the
four most significant bits of the timeout register.
POSITIVE
THRESHOLD
SENSITIVITY
DATA AVERAGE
SENSITIVITY
NEGATIVE
THRESHOLD
OUTPUT ACTIVE
The receding timeout starts when the CDC data crosses
the data average sensitivity band away from the threshold,
according to the selected positive or negative threshold mode.
The receding timeout is not used in the window threshold
mode. The receding timeout elapses after the number of
conversion cycles equals 2TimeOutRec, where TimeOutRec is the
value of the four least significant bits of the timeout register.
TIME
Figure 37. Threshold Sensitivity
The sensitivity is an 8-bit value and is mapped to the lower eight
bits of the 12-bit CDC data, that is, it corresponds to the 16-bit
data register as shown in Figure 38.
SENSITIVITY
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
When either the approaching or receding timeout elapses (that
is, after the defined number of CDC conversions is counted),
the data average (and thus the thresholds) is forced to follow
the new CDC data value immediately.
DATA HIGH
DATA LOW
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
12-BIT CDC RESULT
When the timeout register equals 0, timeouts are disabled.
Figure 38. Relation Between Sensitivity Register and CDC Data Register
Rev. 0 | Page 18 of 28
AD7156
SETUP REGISTERS
Ch 1 Address Pointer 0x0B
Ch 2 Address Pointer 0x0E
8 Bits, Read/Write, Factory Preset 0x0B
Table 10. Setup Registers Bit Map1
Bit 7
RngH
(0)
Bit 6
RngL
(0)
Bit 5
Bit 4
Hyst
(0)
Bit 3
Bit 2
Bit 1
Bit 0
ThrSettling (4-Bit Value)
(0x0B)
(0)
1 The default values are given in parentheses.
Table 11. Setup Registers Bit Descriptions
Bit
Mnemonic
Description
7
6
RngH
RngL
Range bits set the CDC input range and determine the step for the auto-DAC function.
RngH
RngL
Capacitive Input Range (pF)
Auto-DAC Step (CAPDAC LSB)
0
0
1
1
0
1
0
1
2
4
1
2
8
0.5
1
4
5
4
This bit should be 0 for the specified operation.
Hyst
Hyst = 1 disables hysteresis in adaptive threshold mode. This bit has no effect in fixed threshold mode;
hysteresis is always disabled in the fixed threshold mode.
[3:0]
ThrSettling
Determines dynamic behavior of the data average and thus the settling time of the adaptive thresholds. Data
average is calculated from the previous CDC output data, using equation:
Data(N) − Average(N −1)
Average(N) = Average(N −1) +
2ThrSettling + 1
where:
Average(N) is the new average value.
Average(N − 1) is the average value from the previous cycle.
Data(N) is the latest complete CDC conversion result.
ThrSettling is the programmable parameter.
The response of the average to an input capacitance step change (that is, response to the change in the CDC
output data) is an exponential settling curve characterized by the following equation:
Average(N) = Average(0) + Change(1− eN / TimeConst
)
where:
Average(N) is the value of average N complete CDC conversion cycles after a step change on the input.
Average(0) is the value before the step change.
TimeConst can be selected in the range between 2 and 65,536 conversion cycle multiples, in steps of power of
2, by programming the ThrSettling bits. TimeConst = 2(ThrSettling + 1)
INPUT CAPACITANCE
(CDC DATA) CHANGE
DATA AVERAGE RESPONSE
TIME
Figure 39. Data Average Response to Data Step Change
Rev. 0 | Page 19 of 28
AD7156
CONFIGURATION REGISTER
Address Pointer 0x0F
8 Bits, Read/Write, Factory Preset 0x19
Table 12. Configuration Register Bit Map1
Bit 7
ThrFixed
(0)
Bit 6
ThrMD1
(0)
Bit 5
ThrMD0
(0)
Bit 4
EnCh1
(1)
Bit 3
EnCh2
(1)
Bit 2
MD2
(0)
Bit 1
MD1
(0)
Bit 0
MD0
(1)
1 The default values are given in parentheses.
Table 13.Configuration Register Bit Descriptions
Bit
Mnemonic
Description
7
ThrFixed
ThrFixed = 1 sets the fixed threshold mode; the outputs reflect the comparison of data and a fixed (constant)
value of the threshold registers.
ThrFixed = 0 sets the adaptive threshold mode; the outputs reflect the comparison of data to the adaptive
thresholds. The adaptive threshold is set dynamically, based on the history of the previous data.
6
5
ThrMD1
ThrMD0
These bits set the output comparators mode
Output Active When
ThrMD1
ThrMD0
Threshold Mode
Negative
Adaptive Threshold Mode
Data < average – sensitivity
Data > average + sensitivity
Fixed Threshold Mode
Data < threshold
0
0
1
0
1
0
Positive
Data > threshold
In-window
Data > average – sensitivity
and
Data < average + sensitivity
1
1
Out-window
Data < average – sensitivity
or
Data > average + sensitivity
4
3
EnCh1
EnCh2
Enables conversion on Channel 1
Enables conversion on Channel 2
Converter mode of operation setup
2
1
0
MD2
MD1
MD0
MD2
MD1
MD0
Mode
Description
0
0
0
0
0
1
Idle
The part is fully powered up, but performing no conversion.
Continuous
Conversion
The part is repeatedly performing conversions on the
enabled channel(s); if two channels are enabled, the part is
sequentially switching between them.
0
1
0
Single conversion
The part performs a single conversion on the enabled
channel; if two channels are enabled, the part performs two
conversions, one on each channel. After finishing the
conversion(s), the part goes to the idle mode.
0
1
1
1
Power-down
Reserved
The part powers down the on-chip circuits, except the
digital interface.
X
X
Do not use these modes.
Rev. 0 | Page 20 of 28
AD7156
POWER-DOWN TIMER REGISTER
Address Pointer 0x10
8 Bits, Read/Write, Factory Preset 0x40
Table 14. Power-Down Timer Register Bit Map1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Power-down timeout (6-bit value)
(0x00)
(0)
(1)
1 The default values are given in parentheses.
Table 15.Power-Down Timer Register Bit Descriptions
Bit
Mnemonic
Description
7
This bit must be 0 for proper operation.
This bit must be 1 for proper operation.
6
[5:0]
Power-down
timeout
This bit defines the period duration of the power-down timeout.
If the comparator outputs have not been activated during the programmed period, the part enters power-down
mode automatically. The part can be then returned to a normal operational mode either via the serial interface
or by the power supply off/on sequence.
The period is programmable in steps of 4 hours. For example, setting the value to 0x06 sets the duration to 24
hours. The maximum value of 0x3F corresponds to approximately 10.5 days.
The value of 0x00 disables the power-down timeout, and the part does not enter power-down mode automatically.
CAPDAC REGISTERS
Ch 1 Address Pointer 0x11
Ch 2 Address Pointer 0x12
8 Bits, Read/Write, Factory Preset 0xC0
Table 16. CAPDAC Registers Bit Map1
Bit 7
DacEn
(1)
Bit 6
DacAuto
(1)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DacValue (6-bit value)
(0x00)
1 The default values are given in parentheses.
Table 17. CAPDAC Registers Bit Descriptions
Bit
Mnemonic
Description
DacEn = 1 enables capacitive the DAC.
DacAuto = 1 enables the auto-DAC function in the adaptive threshold mode.
7
DacEn
6
DacAuto
When the auto-DAC function is enabled, the part dynamically adjusts the CAPDAC to keep the CDC in an
optimal operating capacitive range. The CAPDAC value is automatically incremented when the data average
exceeds ¾ of the CDC full range, and the CAPDAC value is decremented when the data average goes below ¼
of the CDC full range. The auto-DAC increment or decrement step depends on the selected CDC capacitive
input range.
This bit has no effect in fixed threshold mode; the auto-DAC function is always disabled in the fixed threshold mode.
[5:0]
DacValue
CAPDAC value, Code 0x00 ≈ 0 pF, Code 0x3F ≈ CAPDAC full range.
SERIAL NUMBER REGISTER
CHIP ID REGISTER
Address Pointer 0x13, Address Pointer 0x14, Address
Pointer 0x15, Address Pointer 0x16
Address Pointer 0x17
8 Bits, Read Only, Factory Preset 0xXX
32 Bits, Read Only, Factory Preset 0xXXXX
This register holds the chip identification code, used in factory
manufacturing and testing.
This register holds a serial number, unique for each individual part.
Rev. 0 | Page 21 of 28
AD7156
SERIAL INTERFACE
The AD7156 supports an I2C-compatible, 2-wire serial inter-
face. The two wires on the serial bus (interface) are called SCL
(clock) and SDA (data). These two wires carry all addressing,
control, and data information one bit at a time over the bus to
all connected peripheral devices. The SDA wire carries the data,
while the SCL wire synchronizes the sender and receiver during
the data transfer. The devices on the bus are classified as either
master or slave devices. A device that initiates a data transfer
message is called a master, whereas a device that responds to
this message is called a slave.
In continuous conversion mode, the address pointers’ auto-
incrementer should be used for reading a conversion result.
This means that the two data bytes should be read using one
multibyte read transaction rather than two separate single byte
transactions. The single byte data read transaction may result in
the data bytes from two different results being mixed. The same
applies for four data bytes if both capacitive channels are enabled.
The user can also access any unique register (address) on a
one-to-one basis without having to update all the registers.
The address pointer register contents cannot be read.
To control the AD7156 device on the bus, the following
protocol must be utilized. First, the master initiates a data
transfer by establishing a start condition, defined by a high-
to-low transition on SDA while SCL remains high. This
indicates that the start byte follows. This 8-bit start byte is
made up of a 7-bit address plus an R/W bit indicator.
If an incorrect address pointer location is accessed or if the
user allows the autoincrementer to exceed the required register
address, the following applies:
•
In read mode, the AD7156 continues to output various
internal register contents until the master device issues
a no acknowledge, start, or stop condition. The address
pointers’ autoincrementer contents are reset to point to
the status register at the 0x00 address when a stop condition
is received at the end of a read operation. This allows the
status register to be read (polled) continually without
having to constantly write to the address pointer.
In write mode, the data for the invalid address is not
loaded into the AD7156 registers, but an acknowledge
is issued by the AD7156.
All peripherals connected to the bus respond to the start
condition and shift in the next eight bits (7-bit address + R/W
bit). The bits arrive MSB first. The peripheral that recognizes
the transmitted address responds by pulling the data line low
during the ninth clock pulse. This is known as the acknowledge
bit. All other devices withdraw from the bus at this point and
maintain an idle condition. An exception to this is the general
call address, which is described in the General Call section. In
the idle condition, the device monitors the SDA and SCL lines
waiting for the start condition and the correct address byte.
•
WRITE OPERATION
The R/W bit determines the direction of the data transfer.
A Logic 0 LSB in the start byte means that the master writes
information to the addressed peripheral. In this case, the
AD7156 becomes a slave receiver. A Logic 1 LSB in the
start byte means that the master reads information from
the addressed peripheral. In this case, the AD7156 becomes
a slave transmitter. In all instances, the AD7156 acts as a
standard slave device on the serial bus.
When a write is selected, the byte following the start byte is
always the register address pointer (subaddress) byte, which
points to one of the internal registers on the AD7156. The
address pointer byte is automatically loaded into the address
pointer register and acknowledged by the AD7156. After the
address pointer byte acknowledge, a stop condition, a repeated
start condition, or another data byte can follow from the master.
A stop condition is defined by a low-to-high transition on SDA
while SCL remains high. If a stop condition is encountered by
the AD7156, it returns to its idle condition and the address
pointer is reset to 0x00.
The start byte address for the AD7156 is 0x90 for a write and
0x91 for a read.
READ OPERATION
If a data byte is transmitted after the register address pointer
byte, the AD7156 loads this byte into the register that is cur-
rently addressed by the address pointer register and sends
an acknowledge, and the address pointer autoincrementer
automatically increments the address pointer register to the
next internal register address. Thus, subsequent transmitted
data bytes are loaded into sequentially incremented addresses.
When a read is selected in the start byte, the register that is
currently addressed by the address pointer is transmitted to the
SDA line by the AD7156. This is then clocked out by the master
device, and the AD7156 awaits an acknowledge from the master.
If an acknowledge is received from the master, the address
autoincrementer automatically increments the address pointer
register and outputs the next addressed register content to the
SDA line for transmission to the master. If no acknowledge is
received, the AD7156 returns to the idle state and the address
pointer is not incremented. The address pointers’ autoincrementer
allows block data to be written to or read from the starting address
and subsequent incremental addresses.
Rev. 0 | Page 22 of 28
AD7156
If a repeated start condition is encountered after the address
pointer byte, all peripherals connected to the bus respond exactly
as outlined previously for a start condition; that is, a repeated
start condition is treated the same as a start condition. When a
master device issues a stop condition, it relinquishes control of
the bus, allowing another master device to take control of the
bus. Therefore, a master wanting to retain control of the bus
issues successive start conditions known as repeated start
conditions.
GENERAL CALL
When a master issues a slave address consisting of seven 0s
with the eighth bit (R/W) set to 0, this is known as the general
call address. The general call address is for addressing every
device connected to the serial bus. The AD7156 acknowledges
this address and reads in the following data byte.
If the second byte is 0x06, the AD7156 is reset, completely
uploading all default values. The AD7156 does not respond
to the serial bus commands (do not acknowledge) during the
default values upload for approximately 2 ms.
AD7156 RESET
To reset the AD7156 without having to reset the entire serial
bus, an explicit reset command is provided. This uses a particular
address pointer word as a command word to reset the part and
upload all default settings. The AD7156 does not respond to the
serial bus commands (do not acknowledge) during the default
values upload for approximately 2 ms.
The AD7156 does not acknowledge any other general call
commands.
The reset command address word is 0xBF.
SDA
SCL
S
8
9
8
9
8
9
P
1 – 7
1 – 7
1 – 7
DATA
START ADDR
ACK SUBADDRESS ACK
ACK
STOP
R/W
Figure 40. Bus Data Transfer
WRITE
SEQUENCE
S
S
SLAVE ADDR A(S) SUB ADDR A(S)
LSB = 0
DATA
A(S)
A(S)
P
DATA
A(M)
LSB = 1
READ
SEQUENCE
A(M)
SLAVE ADDR A(S)
SUB ADDR A(S)
S
SLAVE ADDR A(S)
DATA
DATA
P
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
S = START BIT
P = STOP BIT
A(S) = NO ACKNOWLEDGE BY SLAVE
A(M) = NO ACKNOWLEDGE BY MASTER
Figure 41. Write and Read Sequences
Rev. 0 | Page 23 of 28
AD7156
HARDWARE DESIGN CONSIDERATIONS
OVERVIEW
PARASITIC RESISTANCE TO GROUND
The AD7156 is an interface to capacitive sensors.
On the input side, Sensor CX can be connected directly between
the AD7156 EXC and CIN pins. The way it is connected and the
electrical parameters of the sensor connection, such as parasitic
resistance or capacitance, can affect the system performance.
Therefore, any circuit with additional components in the capacitive
front end, such as overvoltage protection, has to be carefully
designed, considering the AD7156 specified limits and informa-
tion provided in this section.
R
GND1
DATA
CIN
CDC
C
X
R
GND2
EXC
On the output side, the AD7156 can work as a standalone device,
using the power-up default register settings and flagging the
result on the digital outputs. Alternatively, the AD7156 can be
interfaced to a microcontroller via the 2-wire serial interface,
offering flexibility by overwriting the AD7156 register values
from the host with a user-specific setup.
Figure 43. Parasitic Resistance to Ground
The AD7156 CDC result is affected by a leakage current from
CX to ground; therefore, CX should be isolated from the ground.
The equivalent resistance between CX and ground should be
maximized (see Figure 43). For more information, see Figure 10
to Figure 13.
PARASITIC CAPACITANCE TO GROUND
PARASITIC PARALLEL RESISTANCE
C
GND1
DATA
CIN
CDC
DATA
CIN
CDC
C
X
C
R
P
X
C
GND2
EXC
EXC
Figure 42. Parasitic Capacitance to Ground
Figure 44. Parasitic Parallel Resistance
The CDC architecture used in the AD7156 measures the
capacitance, CX, connected between the EXC pins and the
CIN pins. In theory, any capacitance, CGND, to ground should
not affect the CDC result (see Figure 42).
The AD7156 CDC measures the charge transfer between the
EXC and CIN pins. Any resistance connected in parallel to the
measured capacitance, CX (see Figure 44), such as the parasitic
resistance of the sensor, also transfers charge. Therefore, the
parallel resistor is seen as an additional capacitance in the
output data. The equivalent parallel capacitance (or error
caused by the parallel resistance) can be approximately
calculated as
The practical implementation of the circuitry in the chip implies
certain limits, and the result is gradually affected by capacitance
to ground (for information about the allowed capacitance to
GND for CIN and information about excitation see Table 1
and Figure 4 to Figure 9).
1
CP
=
RP × fEXC × 4
where:
RP is the parallel resistance.
EXC is the excitation frequency.
For additional information, see Figure 15.
f
Rev. 0 | Page 24 of 28
AD7156
PARASITIC SERIAL RESISTANCE
INPUT EMC PROTECTION
39kꢀ
82kꢀ
CIN
C
X
68pF
22pF
EXC
CDC
R
S1
DATA
CIN
CDC
10kꢀ
47pF
GND
C
X
Figure 47. AD7156 CIN EMC Protection
R
S2
EXC
Some applications may require an additional input filter for
improving EMC. Any input filter must be carefully designed,
considering the balance between the system capacitance
performance and system electromagnetic immunity.
Figure 45. Parasitic Serial Resistance
The AD7156 CDC result is affected by a resistance in series
with the measured capacitance.
Figure 47 shows one of the possible input circuit configurations
for significantly improving the system immunity against high
frequency noise while only slightly affecting the AD7156
performance in terms of additional gain and offset error.
The total serial resistance (RS1 + RS2 in Figure 45) should be in
the order of hundreds of Ω (see Figure 14).
INPUT OVERVOLTAGE PROTECTION
POWER SUPPLY DECOUPLING AND FILTERING
CDC
1kꢀ
V
DD
R
S1
0.1µF
10µF
CIN
1kꢀ 1kꢀ
C
X
SDA
SCL
R
S2
EXC
CDC
GND
GND
Figure 48. AD7156 VDD Decoupling and Filtering
Figure 46. AD7156 CIN Overvoltage Protection
The AD7156 has good dc and low frequency power supply
rejection but may be sensitive to higher frequency ripple and
noise, specifically around the excitation frequency and its
harmonics. Figure 48 shows a possible circuit configuration
for improving the system immunity against ripple and noise
coupled to the AD7156 via the power supply.
The AD7156 capacitive input has an internal ESD protection.
However, some applications may require an additional over-
voltage protection, depending on the application-specific
requirements. Any additional circuit in the capacitive front
end must be carefully designed, especially with respect to the
limits recommended for maximum capacitance to ground,
maximum serial resistance, maximum leakage, and so on.
If the serial interface is connected to the other circuits in the
system, it is better to connect the pull-up resistors on the other
side of the VDD filter than to connect to the AD7156. If the
AD7156 is used in standalone mode and the serial interface
is not used, it is better to connect the pull-up resistors directly
to the AD7156 VDD.
Rev. 0 | Page 25 of 28
AD7156
APPLICATION EXAMPLES
0.1µF
1kꢀ
1kꢀ
VDD
AD7156
CIN1
SDA
SCL
C
C
SENS1
3V
BATTERY
EXC1
OUT1
OUT2
CIN2
1kꢀ
1kꢀ
SENS2
EXC2
LED1
LED2
GND
Figure 49. AD7156 Standalone Operation Application Diagram
3.3V
0.1µF
1kꢀ
1kꢀ
VDD
HOST
MICROCONTROLLER
AD7156
CIN1
SDA
SCL
SDA
SCL
C
C
SENS1
EXC1
CIN2
OUT1
OUT2
IRQ1
IRQ2
SENS2
EXC2
GND
Figure 50. AD7156 Interfaced to a Host Microcontroller
V
1kꢀ
3.3V
1µF
SUPPLY
ADP1720-3.3
0.1µF
10µF
1µF
VDD
R1 R2
39kꢀ
82kꢀ
68pF
CIN1
22pF
1kꢀ 1kꢀ
AD7156
SDA
SCL
C
C
SENS1
10kꢀ
EXC1
47pF
OUT1
OUT1
OUT2
CIN2
22pF
39kꢀ
82kꢀ
68pF
Q1
OUT2
SENS2
10kꢀ
EXC2
47pF
Q2
GND
Figure 51. AD7156 Standalone Operation with EMC Protection
Rev. 0 | Page 26 of 28
AD7156
OUTLINE DIMENSIONS
0.30
0.23
0.18
3.00
BSC SQ
0.50 BSC
10
6
5
PIN 1 INDEX
1.74
1.64
1.49
*
EXPOSED
PAD
AREA
(BOTTOM VIEW)
0.50
0.40
0.30
1
PIN 1
INDICATOR
(R 0.20)
TOP VIEW
2.48
2.38
2.23
0.80 MAX
0.55 NOM
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SEATING
PLANE
0.20 REF
*
FOR PROPER CONNECTION OF THE EXPOSED PAD PLEASE REFER TO
THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION
OF THIS DATA SHEET.
Figure 52. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD7156BCPZ-REEL1
AD7156BCPZ-REEL71
EVAL-AD7156EBZ1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
CP-10-9
CP-10-9
Branding
C6L
C6L
10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
Evaluation Board
1 Z = RoHS Compliant Part.
Rev. 0 | Page 27 of 28
AD7156
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07726-0-10/08(0)
Rev. 0 | Page 28 of 28
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