EVAL-AD7668CB [ADI]
Evaluation Board AD766X/AD767X; 评估板AD766X / AD767X型号: | EVAL-AD7668CB |
厂家: | ADI |
描述: | Evaluation Board AD766X/AD767X |
文件: | 总15页 (文件大小:1839K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
Evaluation Board AD766X/AD767X
EVAL-AD766XCB/AD767XCB
FEATURES
The EVAL-AD766XCB/AD767XCB is ideal for use with
either the Analog Devices EVAL-CONTROL BOARD, or as a
stand-alone evaluation board. The design offers the flexibility
of applying external control signals and is capable of generating
16-bit conversion results on a parallel buffered outputs.
Versatile Analog Signal Conditioning Circuitry
On-Board Reference, Crystal Oscillator and Buffers
16-Bit Parallel Buffered Outputs
Ideal For DSP and Data Acquisition Card Interfaces
Analog and Digital Prototyping Area
EVAL-CONTROL BOARD Compatibility
PC Software for Control and Data Analysis
On-board components include an AD780, a +2.5V ultrahigh
precision bandgap reference, a signal conditioning circuit
with two op-amps and digital logic. The board interfaces with
a 96-way connector for the EVAL-CONTROL BOARD, a
20-pin IDC connector for serial output interface, and a 40-
pin IDC connector for parallel output data. SMB connectors
are provided for the low noise analog signal source, an exter-
nal master clock and an external start/convert input.
GENERAL DESCRIPTION
The EVAL-AD766XCB/AD767XCB is an evaluation board
for the AD766X/AD767X 16-bit A/D converter family. The
AD766X/AD767X family ( see ordering guide for product list )
is a high speed, successive approximation based architecture
with very high performance, low power family of 16-Bit ADCs
which operate from a single +5V supply with a 100kSPS to
1MSPS throughput rate range, and a flexible parallel or serial
interface. The AD766X/AD767X evaluation board is designed
to demonstrate the ADC's performance and to provide an easy
to understand interface for a variety of system applications. A
full description of the AD766X/AD767X is available in the
Analog Devices AD766X/AD767X data sheets and should be
consulted when utilizing this evaluation board.
ORDERING GUIDE
Evaluation board Model
Product
EVAL-AD7650CB
EVAL-AD7660CB
EVAL-AD7662CB
EVAL-AD7663CB
EVAL-AD7664CB
EVAL-AD7665CB
EVAL-AD7668CB
EVAL-AD7671CB
EVAL-AD7675CB
EVAL-AD7676CB
EVAL-AD7677CB
EVAL-CONTROL BRD2
AD7650AST
AD7660AST
AD7662YST
AD7663AST
AD7664AST
AD7665AST
AD7668YST
AD7671AST
AD7675AST
AD7676AST
AD7677AST
Controller Board
FUNCTIONAL BLOCK DIAGRAM
+/-5 V
+/-12 V
+5 V
CNVST
CNVST
BUSY
REF 2.5V
REF
AD780
V
L
AD766x
or
AD767x
40
96
PIN
PIN
AUX_IN
CONN
CONN
DIGITAL LOGIC
SIGNAL
DATA
CONDITIONING
IN
20
PIN
IN
CONN
MCLK
Clock
Configuration switches
MCLK
REV. PrK
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2001
PRELIMINARY TECHNICAL DATA
EVAL-AD766XCB/AD767XCB
OPERATING THE EVAL-AD766XCB/AD767XCB
The EVAL-AD766XCB/AD767XCB is a four-layer board
carefully laid out and tested to demonstrate the specific high
accuracy performance of the AD766X/AD767X. Figure 1
shows the schematics of the evaluation board. The layouts of
the board are given in :
Top side silk-screen - Figure 2
Top side layer - Figure 3
Ground layer - Figure 4
Shield layer - Figure 5
tor P1. When slave serial reading mode of the
AD766X/AD767X is used, the external serial clock SCLK
applied to the ADC is at half the MCLK frequency.
Power Supplies and Grounding
The evaluation board ground plane is separated into two
sections: a plane for the digital interface circuitry and an ana-
log plane for the analog input and external reference
circuitry. To attain high resolution performance, the board
was designed to ensure that all digital ground return paths do
not cross the analog ground return paths.
Bottom side layer - Figure 6
Bottom side silk-screen - Figure 7.
The EVAL-AD766XCB/AD767XCB has three power supply
blocks: a single 5V supply VA (SJ1) for the AD766X/AD767X
and the reference voltage circuitry, a digital 5V supply VL (SJ2)
for the digital interface circuitry and the digital section of the
ADC, and a selectable +/-12V (with a possibility of +/-15V
with control Brd2) or +/-5V supply for the analog signal con-
ditioning circuitry (SJ3). All supplies are decoupled to ground
with 10 F tantalum and 0.1 F ceramic capacitors.
The EVAL-AD766XCB/AD767XCB is a flexible design that
enables the user to choose among many different board con-
figurations. A description of each selectable jumper/switch is
listed in Table II and the available test points are listed in
Table III. Note that the button of a switch in position A ( U3
side ) defines a low level.
The EVAL-AD766XCB/AD767XCB is configured in factory
with 0 to 2.5 V ADC input range for the AD7660, AD7664,
and AD7675/7676/7677 and +/-5V for the AD7663/7665/
7671; front-end amplifiers U6 and U7 set with a gain of +1,
powered through the EVAL-CONTROL BOARD, and the
on-board CNVST generation used.
Analog Input Ranges
The analog front-end amplifier circuitry U6 and U7 allows
flexible configuration changes such as positive or negative
gain, input range scaling, filtering, addition of a DC compo-
nent, use of different op-amp and supplies.
Figure 1 shows the front end op-amp configuration used with
the AD7660/7663/7664/7665/7671/7675/7676/7677.
In some applications, it is desired to use a bipolar or wider
On-board or external CNVST could be used. When an exter-
nal CNVST signal is applied, this signal should have very low
jitter and sharp edges to get the best noise performance of the
part. Meanwhile, it is recommended to use the on-board
CNVST generation which is done by dividing MCLK signal
(20MHZ) by the numbers shown in Table I, which are en-
tered in the software. Activity on BUSY pin of the ADC
turns on the LED.
analog input range like, for instance, 10V, 5V,
2.5V, or
0 to +5V. For the AD76XX parts which do not have directly
those input ranges like the AD7660/7664/7675/7676/7677,
by simple modifications of the input driver circuitry of the
EVAL-AD766XCB/AD767XCB, bipolar and wider input
ranges can be used without any performance degradation.
Components values required and resulting full-scale ranges
are shown in table IV and table V.
In factory, the analog input of U6 is set at mid-scale
(R6=R7=590⍀) for the AD7660/7664/7675/7676/7677. For
AD7663/7665/7671, R7 is not connected to maintain the
input at 0V (mid-scale). This allows a transition noise test
without any other equipment. An FFT test can be done by
applying a very low distortion AC source.
Table I. CNVST GENERATION
Part
Division Factor
ThroughputRate
100KSPS
500KSPS
250KSPS
571KSPS
571KSPS
1MSPS
AD7660
AD7662/68
AD7663
AD7664/50
AD7665
AD7671
AD7675
AD7676
AD7677
200
40
80
35
35
20
EVAL-CONTROL BOARD INTERFACE
200
35
100KSPS
571KSPS
1MSPS
The EVAL-AD766XCB/AD767XCB interfaces to the EVAL-
CONTROL BRD2 through the 96-way connector.
20
RUNNING THE EVAL-AD766X/AD767XCB SOFTWARE
Software Description
Conversion data is available at the output bus BD on U3, on
the 40-pin connector P2, and on the 96-pin connector P3.
Additionally, BD data is updated on the falling/rising edge of
DBUSY and BBUSY on P3, low when BD data is valid are
delayed from the BD data by about 20 ns to ease the inter-
face. When either parallel or serial reading mode of the ADC
is used, the data is available on this parallel bus. When serial
reading mode of the ADC is used, the serial interface signals
of the ADC are buffered and available on the 20-pin connec-
The EVAL-AD766XCB/AD767XCB comes with software for
analyzing the AD766X/AD767X. Through the EVAL-CON-
TROL BRD2 one can perform a histogram to determine code
transition noise, and Fast Fourier Transforms (FFT's) to
determine the Signal-to-Noise Ratio (SNR), Signal-to-Noise-
plus-Distortion (SNRD) and Total-Harmonic-Distortion
(THD). The front-end PC software has four screens as
shown in Figure 8,9,10 and 11. Figure 8 is the Setup Screen
where input voltage range, sample rate, number of samples
are selected. Figure 9 is the Histogram Screen, which allows
the code distribution for DC input and computes the mean
and standard deviation.
REV. PrK
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PRELIMINARY TECHNICAL DATA
EVAL-AD766XCB/AD767XCB
Figure 10 is the FFT Screen, which performs an FFT on the
Software Installation
captured data, computes the Signal-to-Noise Ratio (SNR),
Signal-to-Noise-plus-Distortion (SINAD) and total-Har-
monic-Distortion (THD). Figure 11 is the time domain
representation of the output. When the on-board CNVST
generation is used, a synchronous FFT could be achieved by
synchronizing the external AC generator with the Fsync signal
(TP11) which is an exact division by 2 of MCLK.
- Double-Click on Setup.exe from the CD-ROM and follow the
installation instructions.
NOTE: The software runs under Windows 95/98 only.
TABLE II. JUMPER DESCRIPTION
Jumper
Default position
Function
Designation with the control
board ( Factory
settings)
JP1
JP2
A
A
Selection of the positive supply of the front-end amplifier U6. When JP1 is in posi-
tion A, the +12V supply from the control board is applied to JP3 otherwise VS+ on
SJ3 is used.
Selection of the negative supply of the front-end amplifier U6. When JP2 is in posi-
tion A, the -12V supply from the control board is applied to JP4 otherwise VS- on
SJ3 is used.
JP3
JP4
JP5
A
Selection of the positive supply of the front-end amplifier U6. When JP3 is in posi-
tion A, the +5V supply from the control board is used otherwise JP1 output is used.
A
Selection of the negative supply of the front-end amplifier U6. When JP4 is in posi-
tion A, the -5V supply from the control board is used otherwise JP2 output is used.
not A
Selection of the master clock MCLK signal. When JP5 is in position A, the signal on
J4 is used otherwise the on-board 20 MHz clock is used as a MCLK signal. MCLK
signal is used to generate the on-board CNVST signal and the external serial clock
SCLK.
JP6
JP7
A, U3 side
A, U3 side
Selection of RDC ( Read during convert ). When the button of the switch is close to
J4 connector ( not A position ) and when the serial reading mode is selected, the data
are read during conversion otherwise the data are read after conversion. JP6 has no
use in parallel reading mode.
Selection of PD ( Powerdown ). When the button of the switch is close to J4 connec-
tor ( not A position ), the ADC is in power-down mode.
JP8
JP9
A, U3 side
A, U3 side
Spare switch.
Selection of RESET. When the button of the switch is close to J4 connector ( not A
position ), the ADC is reset.
JP10
A, U3 side
Selection of SER/PAR ( serial/parallel reading mode ). When the button of the switch
is close to J4 connector ( not A position ), the data are read in serial mode otherwise
the data are read in parallel mode.
JP11
not A, SJ4 side
A, U3 side
Selection of OC/2C ( coding ). When the button of the switch is close to J4 connector
( not A position ), the ADC uses a straight binary coding otherwise the twos comple-
ment coding is used.
JP12
Selection of WARP. When the button of the switch is close to J4 connector ( not A
position ), the ADC uses the WARP mode which is the fastest one. With the AD7660,
JP12 is a spare switch.
REV PrK
–3–
PRELIMINARY TECHNICAL DATA
EVAL-AD766XCB/AD767XCB
TABLE II. JUMPER DESCRIPTION
Function
Jumper
Default position
Designation with the control
board ( Factory
settings)
JP13
A, U3 side
Selection of IMPULSE. When the button of the switch is close to J4 connector
( not A position ), the ADC uses the IMPULSE mode which is the mode with the
lowest power dissipation. With the AD7660, JP13 is a spare switch.
JP14
JP15
JP16
A, U3 side
A, U3 side
A, U3 side
TEST1. For factory use only and it is pull down.
TEST0. For factory use only and it is pull down.
Selection of EXT/INT ( use of external or internal serial clock ). When the button of
the switch is close to J4 connector ( not A position ) and when the serial reading
mode is selected, the data are read with an external serial clock SCLK generated from
the master clock MCLK otherwise the data are read with the ADC serial clock. When
external serial clock reading mode is selected, MCLK has to be fast enough to be able
the read the data properly as explained in the AD766X data sheet. JP16 has no use in
parallel reading mode.
JP17
A, U3 side
Selection of INVSYNC ( SYNC active level ). When the button of the switch is close
to J4 connector ( not A position ) and when the master serial reading mode is se
lected, the SYNC signal is active Low. JP17 has no use in parallel reading mode or
slave serial reading mode.
JP18
JP19
JP20
A, U3 side
not A
Selection of INVSCLK ( SCLK active edge ). When the button of the switch is close
to J4 connector ( not A position ) and when the serial reading mode is selected,
INVSCLK is high. JP18 has no use in parallel reading mode.
Selection of CNVST signal. When JP19 is in position A, the signal on J3 is used
otherwise the on-board CNVST generation is used. MCLK signal is used to generate
the on-board CNVST signal.
not A
Selection of REF signal. When JP20 is in position A, the REF is buffered. When
JP20 is not in position A, the REF is not buffered.
Table IV. Component values Vs. Input ranges ( AD7660 )
Table III. EVAL-AD766XCB/AD767XCB Test Points
Input range
R1
R3
R6
R7
Test Point
TP1
TP2
TP3
TP4
Available Signal
10V
5V
0 to -5V
8k⍀
8k⍀
8k⍀
1k⍀
2k⍀
8k⍀
8k⍀
6.67k⍀ 10k⍀
0⍀ none
10k⍀
DGND Digital ground
DGND Digital ground
SIG+
AGND Analog ground close to SIG+
REF ADC Reference input
BUSY ADC BUSY signal
ADC Analog input
TP5
TP6
TP7
TP8
RD
C S
ADC RD signal
ADC CS signal
Table V. Component values Vs. Input ranges ( AD7664 )
TP9
AGND Analog ground close to REF
CNVST ADC CNVST signal
Input range
R1
R3
R6
R7
TP10
TP11
TP12
TP13
TP14
TP15
TP16
10V
5V
0 to -5V
2k⍀
2k⍀
1k⍀
250⍀ 8k⍀
500⍀ 6.67k⍀ 10k⍀
1k⍀ 0⍀ none
10k⍀
FSYNC
MCLK divided by 2
OVDD ADC digital output supply
DVDD ADC digital core supply
VANA1 ADC analog supply
AGND Analog ground close to SIG-
SIG-
ADC Analog input
REV. PrK
–4–
PRELIMINARY TECHNICAL DATA
EVAL-AD766XCB/AD767XCB
TESTING METHODS
Histogram
USE OF EVAL-AD766XCB/AD767XCB AS STAND-
ALONE EVALUATION BOARD
To perform a histogram test, apply a DC signal to the input. It
is advised to filter the signal to make the DC Source noise com-
patible with that of the ADC. C26 provides this filtering.
You have the option of using the
EVAL-AD766XCB/AD767XCB as a stand-alone evaluation
board. This method does not require the control board, nor does
it require use of the accompanied software. The digital output
will now be available on P1 (20-pin connector, for use in serial
mode) or P2 (40-pin connector, for use in parallel mode). Cer-
tain modifications have to be made on the board to allow proper
operation of the evaluation board. Refer to Table II to obtain
the jumper positions for stand-alone operation. When in stand-
alone, CNVST could be externally applied or is generated
internally according to Table I.
AC Testing
To perform an AC test, apply a sinusoidal signal to the
evaluation board. Low distortion, better than 100dB, is required
to allow true evaluation of the part. One possibility is to filter the
input signal from the AC source. There is no suggested
bandpass filter but consideration should be taken in the choice.
Furthermore, when the full-scale input range is more than a few
Vpp, it is recommended that you use the on board amplifier to
amplify the signal, thus preventing the filter from distorting the
input signal.
Please refer to Figure 1 to obtain the data output pins on the
connectors.
Data is updated on the falling edge of BUSY. BCS and BWR
are inputs to the FPGA and are connected to P1 and P2.
When BCS, CONTROL are low and BWR is high, which is
the default value defined by the on-board pull-up/pull-down
resistors, the data bus BD available on the P2 connector is
enabled.
Please refer to Figures 8,9,10 and 11 to see the screens of the
software.
Software Description
The AD16bit.exe is the software which allows you to analyze
different performance characteristics of the AD766X,
AD767X, AD97X and AD67X 16-bit ADC family. The soft-
ware allows you to test the histogram as well as perform
different AC tests.
SUPPLYING THE BOARD FOR STAND-ALONE USE
SJ1 is the analog supply. Connect VA+ to +5V and AGND to
GND. SJ2 is the digital supply. SJ2 requires the same values as
SJ1, and SJ2 may be connected to SJ1. SJ3 is the supply for the
front end amplifier (U6). Connect +12V to VS+, GND to
AGND, and -12V to VS-.
Setup Requirements
- Evaluation Control Board 2 (ADSP2189)
- Evaluation Board
- Power Supply (AC 15V/1A source could be bought from
ADI)
- Parallel Port Cable (provided with the evaluation control
board)
- AC Source (low distortion)
- DC Source (low noise)
- Bandpass Filter (value based on your signal frequency, low
distortion)
REV PrK
–5–
PRELIMINARY TECHNICAL DATA
EVAL-AD766XCB/AD767XCB
EVAL-BOARD SETTING FOR INPUT
CONFIGURATIONS
The AD7663/AD7665 and AD7671 have the ability to oper-
ate both unipolar and bipolar range. The available options are
+/- 10V, +/- 5V, +/- 2.5V, 0 to 10V, 0 to 5V and 0 to 2.5V.
Table VI shows the required configurations for each input
range. (REF = 2.5V). Table VII lists the default settings of
the board for all parts.
Table VI. AD7663/7665/7671 Analog Input Configuration
Input Voltage
Range
IND(4R)
INC(4R)
INB(2R)
INA(R)
4 REF
VIN
VIN
VIN
VIN
VIN
INGND
VIN
INGND
INGND
VIN
REF
2 REF
REF
REF
VIN
REF
0 V to 4REF
VIN
VIN
INGND
INGND
0 V to 2REF
VIN
INGND
0 V to REF
VIN
VIN
VIN
VIN
Table VII. Default Settings
Component/Part
AD7660
R7
S9
S10
R48
0⍀
C40
R47
C39
590⍀
None
590⍀
None
None
590⍀
590⍀
590⍀
None 0⍀
None 0⍀
None 0⍀
None 0⍀
None 0⍀
None
None
2.7nF
None
None
AD7663
0⍀
AD7664
15⍀
0⍀
AD7665
AD7671
0⍀
AD7675
0⍀
0⍀
0⍀
None 15⍀
None 15⍀
None 15⍀
2.7nF 15⍀
2.7nF 15⍀
2.7nF 15⍀
2.7nF
2.7nF
2.7nF
AD7676
AD7677
–6–
REV PrK
PRELIMINARY TECHNICAL DATA
EVAL-AD766XCB/AD767XCB
D G N D
D G N D
A G N D
A V D D
D V D D
O V D D
T 0 / E 0 C
3 6
1 7
2 0
1
T 1 / P D R E F
3 0
S E R / P A R
8
O B / 2 C
5
W A R P
6
I M P U L S E
7
R E S E T
2
3 3
B Y T E S W A P
4
P D
1 9
1 8
3 4
8
4
7
4
7
4
8
1
8
1
+ V I N
G N D
4
2
Figure 1. Schematic
REV PrK
–7–
PRELIMINARY TECHNICAL DATA
EVAL-AD766XCB/AD767XCB
M C L K
T E S T 1 _ O U T
T E S T 0 _ I N
D 7
D 6
D 5
D 4
T 0
R 3 5
R 2 2
R D C
1 0 K
K 0 1
J P 6
I N V S C L K
I N V S Y N C
E X T / I N T
T E S T 0 _ I N
T 1
J P 1 8
J P 1 7
J P 1 6
J P 1 5
1 0 K
1 0 K
1 0 K
R 2 1
R 2 0
R 1 9
R 1 8
R 1 5
T E S T 1 _ O 1 U 0 T 0
S E R / P A R 1 0 K
J P 1 4
J P 1 0
J P 1 1
J P 1 2
O B / 2 C
1 0 K
R 1 4
R 1 6
R 1 7
R 1 3
R 1 2
W A R P
K 0 1
I M P U L S E 1 0 K
J P 1 3
J P 9
R E S E T
K 0 1
B Y T E
1 0 K
J P 8
J P 7
P D
K 0 1
R 1 1
Figure 1 Schematic
REV. PrK
–8–
PRELIMINARY TECHNICAL DATA
EVAL-AD766XCB/AD767XCB
Figure 2. Top side silk-screen ( Not to Scale ).
Figure 3. Top side ( Not to Scale ).
REV PrK
–9–
PRELIMINARY TECHNICAL DATA
EVAL-AD766XCB/AD767XCB
Figure 4. Ground Layer ( Not to Scale ).
Figure 5. Shield Layer ( Not to Scale ).
REV. PrK
–10–
PRELIMINARY TECHNICAL DATA
EVAL-AD766XCB/AD767XCB
Figure 6. Bottom side layer ( Not to Scale ).
Figure 7. Bottom side silk-screen ( Not to Scale ).
REV PrK
–11–
PRELIMINARY TECHNICAL DATA
EVAL-AD766XCB/AD767XCB
2) The part under evaluation is chosen from this menu. The
available choices are AD766X, AD97x and AD67x.
1) The Run button starts the software. All input configurations
are read by the software after running the software. You will
need to press this button first.
3) Input Configurations are chosen here. For the AD766X/
AD767X, the available choices are: PwDown, Reset, Interface,
Coding, Byte, and Reading.
4) The
choice of
test is made
here. You
may choose
to perform
either a
Histogram
test or an
AC test.
Figure 8. Setup Screen
This is the performance window.
5) You may choose to take one sample (Sample,F3), or per-
form continuous sampling (Continuous,F4). You may also
choose the Help, Save, Print or Quit options. The Help menu
will show you a description of the functionality of the chosen
command.
REV. PrK
–12–
PRELIMINARY TECHNICAL DATA
EVAL-AD766XCB/AD767XCB
The results are displayed on this chart. You may also use the
cursor (yellow) and drag it to your desired location, where the
X-axis value and the Y-axis value will be displayed.
Figure 9. Histogram Screen
This control allows you the choice of display. You have the
option of Time or Histogram. You also have the option of
changing the X-axis unit
Different measurements are displayed here. The DC value,
transition noise, and other values.
REV PrK
–13–
PRELIMINARY TECHNICAL DATA
EVAL-AD766XCB/AD767XCB
The results are displayed on this chart. You may also use the
cursor (yellow) and drag it to your desired location, where the
X-axis value and the Y-axis value will be displayed.
Figure 10. FFT Screen
This is the control that allows you
You may choose either a Kaiser window or a Blackmann-Har-
ris window or a Sync FFT from this menu. . When choosing a
Sync FFT, you will need to synchronize your analog source to
the sampling frequency. The input frequency should be the
value Sync Fr, which is to the right of Target frequency. The
process for this is as follows:
the choice of either time domain
or frequency domain. You may
also change the X-axis unit here.
AC test results are shown here. You also have the
choice of viewing the amplitude of a certain FFT
component by changing the FFT component
menu.
1. You Choose a Target frequency
2. The software calculates an integer n based on the target
frequency you entered and the sampling frequency, Fsamp.
3. The software rounds up the value n to the next prime
number.
4. The software then calculates the corresponding input fre-
quency (Fin) and displays that as Sync Fr.
The equation, (capture window size) is shown below:
(1/Fsamp) * (number of samples) = n * (1/Fin)
REV. PrK
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PRELIMINARY TECHNICAL DATA
EVAL-AD766XCB/AD767XCB
You can also view the output in the Time domain as shown below.
Figure 11. Time-Domain Screen
To view the Time domain, select Time in this menu.
REV PrK
–15–
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