EVAL-AD7887CB4_技术文档

2.7 V to 5.25 V, Micropower, 2-Channel,

125 kSPS, 12-Bit ADC in 8-Lead MSOP

AD7887

FUNCTIONAL BLOCK DIAGRAM

FEATURES

Specified for V_DDof 2.7 V to 5.25 V

Flexible power/throughput rate management

Shutdown mode: 1 μA max

One or two single-ended inputs

Serial interface: SPI®/QSPI™/MICROWIRE™/DSP compatible

8-lead narrow SOIC and MSOP packages

AD7887

AIN0

I/P

MUX

T/H

AIN1/

V

REF

2.5V

REF

COMP

AIN1/V

SOFTWARE

CONTROL

LATCH

REF

V

BUF

DD

APPLICATIONS

Battery-powered systems (personal digital assistants,

medical instruments, mobile communications)

Instrumentation and control systems

High speed modems

GND

CHARGE

REDISTRIBUTION

DAC

SAR + ADC

CONTROL LOGIC

SPORT

DIN

SCLK

CS

DOUT

Figure 1.

GENERAL DESCRIPTION

The AD7887 is a high speed, low power, 12-bit analog-to-digital

converter (ADC) that operates from a single 2.7 V to 5.25 V

power supply. The AD7887 is capable of 125 kSPS throughput

rate. The input track-and-hold acquires a signal in 500 ns and

features a single-ended sampling scheme. The output coding for

the AD7887 is straight binary, and the part is capable of

converting full power signals of up to 2.5 MHz.

a result, the input voltage range on both the AIN0 and AIN1

inputs is 0 to V_DD

.

CMOS construction ensures low power dissipation of typically

2 mW for normal operation and 3 μW in power-down mode.

The part is available in an 8-lead, 0.15-inch-wide narrow body

SOIC and an 8-lead MSOP package.

PRODUCT HIGHLIGHTS

The AD7887 can be configured for either dual- or single-channel

operation via the on-chip control register. There is a default

single-channel mode that allows the AD7887 to be operated as a

read-only ADC. In single-channel operation, there is one

analog input (AIN0) and the AIN1/V_REFpin assumes its V_REF

function. This V_REFpin allows the user access to the part’s

internal 2.5 V reference, or the V_REFpin can be overdriven by an

external reference to provide the reference voltage for the part.

This external reference voltage has a range of 2.5 V to V_DD. The

1. Smallest 12-bit dual-/single-channel ADC; 8-lead MSOP

package.

2. Lowest power 12-bit dual-/single-channel ADC.

3. Flexible power management options, including automatic

power-down after conversion.

4. Read-only ADC capability.

5. Analog input range from 0 V to V_REF

.

analog input range on AIN0 is 0 to V_REF

.

6. Versatile serial input/output port (SPI/QSPI/MICROWIRE/

DSP compatible).

In dual-channel operation, the AIN1/V_REFpin assumes its AIN1

function, providing a second analog input channel. In this case,

the reference voltage for the part is provided via the V_DDpin. As

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD7887

TABLE OF CONTENTS

Features .............................................................................................. 1

Theory of Operation ...................................................................... 11

Circuit Information.................................................................... 11

Converter Operation.................................................................. 11

ADC Transfer Function............................................................. 11

Typical Connection Diagram ................................................... 11

Analog Input ............................................................................... 12

Power-Down Options................................................................ 13

Power vs. Throughput Rate....................................................... 13

Modes of Operation................................................................... 13

Serial Interface............................................................................ 17

Microprocessor Interfacing....................................................... 18

Application Hints ....................................................................... 20

Outline Dimensions....................................................................... 21

Ordering Guide .......................................................................... 21

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications .................................................................. 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Typical Performance Characteristics ............................................. 8

Terminology ...................................................................................... 9

Control Register.............................................................................. 10

REVISION HISTORY

2/09—Rev. C to Rev. D

Changes to Ordering Guide .......................................................... 21

9/06—Rev. B to Rev. C

Updated Format..................................................................Universal

Change to Absolute Maximum Ratings......................................... 6

Additions to Pin Configurations .................................................... 7

Added Table 7.................................................................................. 18

Updated Outline Dimensions....................................................... 21

Changes to Ordering Guide .......................................................... 21

Rev. D | Page 2 of 24

AD7887

SPECIFICATIONS

V_DD= 2.7 V to 5.25 V, V_REF= 2.5 V, external/internal reference unless otherwise noted, f_SCLK= 2 MHz, T_A= T_MINto T_MAX, unless otherwise noted.

Table 1.

Parameter

A Version¹B Version¹

Unit

Test Conditions/Comments

DYNAMIC PERFORMANCE

Signal to Noise + Distortion Ratio (SNR)^{2, 3}

Total Harmonic Distortion (THD)²

Peak Harmonic or Spurious Noise²

Intermodulation Distortion (IMD)²

Second-Order Terms

71

−80

–80

71

−80

dB typ

f_IN= 10 kHz sine wave, f_SAMPLE= 125 kSPS

−80

2.5

−80

2.5

dB typ

MHz typ

fa = 9.983 kHz, fb = 10.05 kHz, f_SAMPLE= 125 kSPS

f_IN= 25 kHz

@ 3 dB

Third-Order Terms

Channel-to-Channel Isolation²

Full-Power Bandwidth

DC ACCURACY

Any channel

Resolution

12

±2

±3

±4

±±

0.5

±2

±1

±±

2

12

±1

±3

±4

±±

0.5

±2

±1

±±

2

Bits

Integral Nonlinearity²

Differential Nonlinearity²

Offset Error²

LSB max

LSB typ

LSB max

LSB typ

LSB max

Guaranteed no missing codes to 11 bits (A Grade)

V_DD= 5 V, dual-channel mode

V_DD= 3 V, dual-channel mode

Single-channel mode

Offset Error Match²

Gain Error²

Dual-channel mode

Single-channel mode, external reference

Single-channel mode, internal reference

Gain Error Match²

ANALOG INPUT

Input Voltage Ranges

Leakage Current

Input Capacitance

0 to V_REF

±5

20

0 to V_REF

±5

20

V

μA max

pF typ

REFERENCE INPUT/OUTPUT

REF_INInput Voltage Range

Input Impedance

2.5/V_DD

10

2.5/V_DD

10

V min/max

kΩ typ

Functional from 1.2 V

Very high impedance if internal reference disabled

REF_OUTOutput Voltage

REF_OUTTemperature Coefficient

LOGIC INPUTS

2.45/2.55

±50

2.45/2.55

±50

V min/max

ppm/°C typ

Input High Voltage, V_INH

2.4

2.1

0.8

±1

10

2.4

2.1

0.8

±1

10

V min

V max

μA max

pF max

V_DD= 4.75 V to 5.25 V

V_DD= 2.7 V to 3.± V

V_DD= 2.7 V to 5.25 V

Input Low Voltage, V_INL

Input Current, I_IN

Typically 10 nA, V_IN= 0 V or V_DD

4

Input Capacitance, C_IN

LOGIC OUTPUTS

Output High Voltage, V_OH

I_SOURCE= 200 μA

V_DD= 2.7 V to 5.25 V

I_SINK= 200 μA

V_DD− 0.5

0.4

±1

V_DD− 0.5

0.4

±1

V min

Output Low Voltage, V_OL

V max

μA max

pF max

Floating-State Leakage Current

Floating-State Output Capacitance⁵

Output Coding

10

Straight (Natural) Binary

Rev. D | Page 3 of 24

AD7887

Parameter

A Version¹B Version¹

Unit

Test Conditions/Comments

CONVERSION RATE

Throughput Time

1±

SCLK cycles Conversion time plus acquisition time is 125 kSPS,

with 2 MHz Clock

SCLK cycles

Track/Hold Acquisition Time²

1.5

Conversion Time

14.5

SCLK cycles

7.25 μs (2 MHz Clock)

POWER REQUIREMENTS

V_DD

+2.7/+5.25 +2.7/+5.25 V min/max

I_DD

Normal Mode⁵(Mode 2)

Static

700

850

700

450

120

12

210

1

2

3.5

2.1

5

3

1.05

±30

700

850

700

450

120

12

210

1

2

3.5

2.1

5

3

1.05

±30

μA max

μA typ

Operational (f_SAMPLE= 125 kSPS)

Internal reference enabled

Internal reference disabled

f_SAMPLE= 50 kSPS

f_SAMPLE= 10 kSPS

f_SAMPLE= 1 kSPS

V_DD= 2.7 V to 5.25 V

V_DD= 2.7 V to 3.± V

V_DD= 4.75 V to 5.25 V

V_DD= 5 V

V_DD= 3 V

V_DD= 5 V

V_DD= 3 V

V_DD= 5 V

Using Standby Mode (Mode 4)

Using Shutdown Mode (Modes 1, 3)

μA typ

Standby Mode^±

Shutdown Mode^±

μA max

mW max

μW max

mW max

μW max

Normal Mode Power Dissipation

Shutdown Power Dissipation

Standby Power Dissipation

V_DD= 3 V

¹Temperature range for A and B versions is −40°C to +125°C.

²See the Terminology section.

³SNR calculation includes distortion and noise components.

⁴Sample tested at +25°C to ensure compliance.

5

CS

All digital inputs at GND except at V_DD. No load on the digital outputs. Analog inputs at GND.

±

CS

SCLK at GND when SCLK off. All digital inputs at GND except for at V_DD. No load on the digital outputs. Analog inputs at GND.

Rev. D | Page 4 of 24

AD7887

TIMING SPECIFICATIONS¹

Table 2.

Limit at T_MIN, T_MAX

(A, B Versions)

Parameter

4.75 V to 5.25 V

2.7 V to 3.6 V

Unit

Description

2

f_SCLK

2

MHz max

t_CONVERT

t_ACQ

t₁

14.5 × t_SCLK

1.5 × t_SCLK

10

14.5 × t_SCLK

1.5 × t_SCLK

10

Throughput time = t_CONVERT+ t_ACQ= 1± t_SCLK

CS to SCLK setup time

ns min

ns max

ns min

ns max

μs typ

3

t₂

30

±0

Delay from CS until DOUT three-state disabled

Data access time after SCLK falling edge

Data setup time prior to SCLK rising edge

Data valid to SCLK hold time

SCLK high pulse width

SCLK low pulse width

3

t₃

75

20

0.4 × t_SCLK

80

5

100

20

0.4 × t_SCLK

80

5

t₄

t₅

t_±

t₇

4

t₈

CS rising edge to DOUT high impedance

Power-up time from shutdown

t₉

¹Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V_DD) and timed from a voltage level of 1.± V.

²Mark/space ratio for the SCLK input is 40/±0 to ±0/40.

³Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.

⁴t₈is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated

back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t₈, quoted in the timing characteristics is the true bus relinquish

time of the part and is independent of the bus loading.

200µA

I

OL

TO

OUTPUT

1.6V

C

L

50pF

200µA

I

OH

Figure 2. Load Circuit for Digital Output Timing Specifications

Rev. D | Page 5 of 24

AD7887

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Table 3.

Parameter

V_DDto AGND

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rating

−0.3 V to +7 V

Analog Input Voltage to AGND

Digital Input Voltage to AGND

Digital Output Voltage to AGND

REF_IN/REF_OUTto AGND

Input Current to Any Pin Except Supplies¹

Operating Temperature Range

Commercial Temperature Range

A, B Versions

−0.3 V to V_DD+ 0.3 V

±10 mA

ESD CAUTION

−40°C to +125°C

−±5°C to +150°C

+150°C

Storage Temperature Range

Junction Temperature

SOIC or MSOP Package Power Dissipation

θ_JAThermal Impedance

450 mW

157°C/W (SOIC)

205.9°C/W (MSOP)

5±°C/W (SOIC)

43.74°C/W (MSOP)

θ_JCThermal Impedance

Lead Temperature, Soldering

Vapor Phase (±0 sec)

Infrared (15 sec)

Pb-Free Temperature, Soldering Reflow

ESD

215°C

220°C

2±0(0)°C

4 kV

¹Transient currents of up to 100 mA do not cause SCR latch-up.

Rev. D | Page ± of 24

AD7887

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

CS

1

2

3

4

8

7

6

5

SCLK

DOUT

DIN

CS

1

2

3

4

8

7

6

5

SCLK

DOUT

DIN

AD7887

V

DD

TOP VIEW

GND

TOP VIEW

(Not to Scale)

AIN1/V

AIN0

AIN1/V

AIN0

REF

Figure 3. SOIC_N Pin Configuration

Figure 4. MSOP Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

CS

Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7887

and also frames the serial data transfer. When the AD7887 operates in its default mode, the CS pin also acts as

the shutdown pin such that with the CS pin high, the AD7887 is in its power-down mode.

2

3

V_DD

Power Supply Input. The V_DDrange for the AD7887 is from 2.7 V to 5.25 V. When the AD7887 is configured for

two-channel operation, this pin also provides the reference source for the part.

Ground Pin. This pin is the ground reference point for all circuitry on the AD7887. In systems with separate AGND

and DGND planes, these planes should be tied together as close as possible to this GND pin. Where this is not

possible, this GND pin should connect to the AGND plane.

GND

4

AIN1/V_REF

Analog Input 1/Voltage Reference Input. In single-channel mode, this pin becomes the reference input/output.

In this case, the user can either access the internal 2.5 V reference or overdrive the internal reference with the

voltage applied to this pin. The reference voltage range for an externally applied reference is 1.2 V to V_DD. In two-

channel mode, this pin provides the second analog input channel, AIN1. The input voltage range on AIN1 is

0 to V_DD.

5

±

AIN0

DIN

Analog Input 0. In single-channel mode, this is the analog input and the input voltage range is 0 to V_REF. In dual-

channel mode, it has an analog input range of 0 to V_DD.

Data In. Logic Input. Data to be written to the AD7887’s control register is provided on this input and clocked into

the register on the rising edge of SCLK (see the Control Register section). The AD7887 can be operated as a

single-channel, read-only ADC by tying the DIN line permanently to GND.

7

8

DOUT

SCLK

Data Out. Logic output. The conversion result from the AD7887 is provided on this output as a serial data stream.

The bits are clocked out on the falling edge of the SCLK input. The data stream consists of four leading zeros

followed by the 12 bits of conversion data, which is provided MSB first.

Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part and writing serial data to

the control register. This clock input is also used as the clock source for the AD7887’s conversion process.

Rev. D | Page 7 of 24

AD7887

TYPICAL PERFORMANCE CHARACTERISTICS

0

–75

–77

–79

–81

4096 POINT FFT

SAMPLING

V

= 5.5V/2.7V

DD

100mV p-p SINE WAVE ON V

DD

REF = 2.488V EXT REFERENCE

125kSPS

f_IN= 10kHz

SNR = 71dB

–10

–30

–50

IN

–83

–85

–87

–70

–90

–89

–91

–93

–110

64.15

2.65

12.85

23.15

33.65

43.85

54.35

INPUT FREQUENCY (kHz)

Figure 5. Dynamic Performance

Figure 7. PSRR vs. Frequency

73.0

V

= 5V

DD

5V EXT REFERENCE

72.5

72.0

71.5

71.0

0.15

10.89

21.14

31.59

42.14

INPUT FREQUENCY (kHz)

Figure 6. SNR vs. Input Frequency

Rev. D | Page 8 of 24

AD7887

TERMINOLOGY

Peak Harmonic or Spurious Noise

Integral Nonlinearity

Peak harmonic or spurious noise is defined as the ratio of the

rms value of the next largest component in the ADC output

spectrum (up to f_S/2 and excluding dc) to the rms value of the

fundamental. Normally, the value of this specification is

determined by the largest harmonic in the spectrum, but for

ADCs where the harmonics are buried in the noise floor, the

largest harmonic could be a noise peak.

This is the maximum deviation from a straight line passing

through the endpoints of the ADC transfer function. The end-

points of the transfer function are zero scale, a point ½ LSB

below the first code transition, and full scale, a point ½ LSB

above the last code transition.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB

change between any two adjacent codes in the ADC.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and fb,

any active device with nonlinearities creates distortion products

at sum and difference frequencies of mfa nfb where m, n = 0,

1, 2, 3, and so on. Intermodulation distortion terms are those for

which neither m nor n are equal to 0. For example, the second-

order terms include (fa + fb) and (fa − fb), and the third order

terms include (2fa + fb), (2fa − fb), (fa + 2fb) and (fa − 2fb).

Offset Error

This is the deviation of the first code transition (00 . . . 000) to

(00 . . . 001) from the ideal, that is, AGND + 0.5 LSB.

Offset Error Match

This is the difference in offset error between any two channels.

Gain Error

This is the deviation of the last code transition (111 . . . 110) to

(111 . . . 111) from the ideal (that is, V_REF− 1.5 LSB) after the

offset error has been adjusted out.

The AD7887 is tested using the CCIF standard in which two

input frequencies near the top end of the input bandwidth are

used. In this case, the second-order terms are usually distanced

in frequency from the original sine waves, and the third-order

terms are usually at a frequency close to the input frequencies.

As a result, the second- and third-order terms are specified

separately. The calculation of the intermodulation distortion is

as per the THD specification, where it is the ratio of the rms

sum of the individual distortion products to the rms amplitude

of the sum of the fundamentals expressed in decibels.

Gain Error Match

This is the difference in gain error between any two channels.

Track/Hold Acquisition Time

The track/hold amplifier returns to track mode at the end of

conversion. Track/hold acquisition time is the time required for

the output of the track/hold amplifier to reach its final value,

within 1/2 LSB, after the end of a conversion.

Channel-to-Channel Isolation

Signal to (Noise + Distortion) Ratio

Channel-to-channel isolation is a measure of the level of

crosstalk between channels. It is measured by applying a full-

scale 25 kHz sine wave signal to the nonselected input channel

and determining how much that signal is attenuated in the

selected channel. The figure given is the worst case across both

channels for the AD7887.

This is the measured ratio of signal to (noise + distortion) at the

output of the ADC. The signal is the rms amplitude of the fun-

damental. Noise is the sum of all nonfundamental signals up to half

the sampling frequency (f_S/2), excluding dc. The ratio is dependent

on the number of quantization levels in the digitization process: the

more levels, the smaller the quantization noise. The theoretical

signal to (noise + distortion) ratio for an ideal N-bit converter

with a sine wave input is given by

Power Supply Rejection (PSR)

Variations in power supply affect the full-scale transition, but

not the converter’s linearity. PSR is the maximum change in the

full-scale transition point due to a change in power supply voltage

from the nominal value. See Figure 7.

Signal to (Noise + Distortion) = (6.02 N + 1.76) dB

Thus for a 12-bit converter, this is 74 dB.

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms sum of

harmonics to the fundamental. For the AD7887, it is defined as

PSRR is defined as the ratio of the power in the ADC output at

frequency f to the power of a full-scale sine wave applied to the

ADC of frequency f_S:

2

PSRR (dB) = 10 log(Pf/Pfs)

V₂+ V₃+ V₄+ V₅+ V₆

THD(dB) = 20 log

where Pf is the power at frequency f in ADC output and Pfs is

the power at frequency f_Sin ADC full-scale input.

V₁

where V₁is the rms amplitude of the fundamental and V₂, V₃,

V₄, V₅, and V₆are the rms amplitudes of the second through the

sixth harmonics.

Rev. D | Page 9 of 24

AD7887

CONTROL REGISTER

The control register on the AD7887 is an 8-bit, write-only register. Data is loaded from the DIN pin of the AD7887 on the rising edge of

SCLK. The data is transferred on the DIN line at the same time as the conversion result is read from the part. This requires 16 serial

CS

clocks for every data transfer. Only the information provided on the first eight rising clock edges after

falling edge is loaded to the

control register. MSB denotes the first bit in the data stream. The bit functions are outlined in Table 5. The contents of the control register

on power up is all 0s.

MSB

DONTC

ZERO

REF

SIN/DUAL

CH

ZERO

PM1

PM0

Table 5. Control Register

Bit

Mnemonic

Comment

7

DONTC

Don’t Care. The value written to this bit of the control register is a don’t care, that is, it doesn’t matter if the bit

is 0 or 1.

±

5

ZERO

REF

A zero must be written to this bit to ensure correct operation of the AD7887.

Reference Bit. With a 0 in this bit, the on-chip reference is enabled. With a 1 in this bit, the on-chip reference is

disabled.

4

SIN/DUAL

Single/Dual Bit. This bit determines whether the AD7887 operates in single-channel or dual-channel mode. A

0 in this bit selects single-channel operation and the AIN1/V_REFpin assumes its V_REFfunction. A 1 in this bit selects

dual-channel mode, with the reference voltage for the ADC internally connected to V_DDand the AIN1/V_REFpin

assuming its AIN1 function as the second analog input channel. To obtain best performance from the AD7887,

the internal reference should be disabled when operating in the dual-channel mode, that is, REF = 1.

3

CH

Channel Bit. When the part is selected for dual-channel mode, this bit determines which channel is converted

for the next conversion. A 0 in this bit selects the AIN0 input, and a 1 in this bit selects the AIN1 input. In single-

channel mode, this bit should always be 0.

2

ZERO

A 0 must be written to this bit to ensure correct operation of the AD7887.

1, 0

PM1, PM0

Power Management Bits. These two bits decode the mode of operation of the AD7887 as described in Table ±.

Table 6. Power Management Options

PM1

PM0

Mode

0

Mode 1. In this mode, the AD7887 enters shutdown if the CS input is 1 and is in full power mode when CS is 0.

Thus the part comes out of shutdown on the falling edge of CS and enters shutdown on the rising edge of CS.

0

1

0

Mode 2. In this mode, the AD7887 is always fully powered up, regardless of the status of any of the logic inputs.

Mode 3. In this mode, the AD7887 automatically enters shutdown mode at the end of each conversion,

regardless of the state of CS.

1

Mode 4. In this standby mode, portions of the AD7887 are powered down but the on-chip reference voltage

remains powered up. This mode is similar to Mode 3, but allows the part to power up much faster. The REF bit

should be 0 to ensure that the on-chip reference is enabled.

Rev. D | Page 10 of 24

AD7887

THEORY OF OPERATION

CIRCUIT INFORMATION

CHARGE

REDISTRIBUTION

DAC

The AD7887 is a fast, low power, 12-bit, single-supply, single-

channel/dual-channel ADC. The part can be operated from a

3 V (2.7 V to 3.6 V) supply or from a 5 V (4.75 V to 5.25 V) supply.

When operated from either a 5 V or 3 V supply, the AD7887 is

capable of throughput rates of 125 kSPS when provided with a

2 MHz clock.

SAMPLING

CAPACITOR

A

V

IN

CONTROL

LOGIC

SW1

B

CONVERSION

PHASE

SW2

COMPARATOR

AGND

(REF IN/REF OUT)/2

The AD7887 provides the user with an on-chip, track/hold

analog-to-digital converter reference and a serial interface

housed in an 8-lead package. The serial clock input accesses data

from the part and provides the clock source for the successive

approximation ADC. The part can be configured for single-

channel or dual-channel operation. When configured as a

single-channel part, the analog input range is 0 to V_REF(where the

externally applied V_REFcan be between 1.2 V and V_DD). When

the AD7887 is configured for two input channels, the input

range is determined by internal connections to be 0 to V_DD.

Figure 9. ADC Conversion Phase

ADC TRANSFER FUNCTION

The output coding of the AD7887 is straight binary. The

designed code transitions occur at successive integer LSB values

(that is, 1 LSB, 2 LSB, and so on). The LSB size is V_REF/4096. The

ideal transfer characteristic for the AD7887 is shown in Figure 10.

111 ... 111

111 ... 110

If single-channel operation is required, the AD7887 can be

operated in a read-only mode by tying the DIN line permanently

to GND. For applications where the user wants to change the

mode of operation or wants to operate the AD7887 as a dual-

channel ADC, the DIN line can be used to clock data into the

part’s control register.

111 ... 000

1LSB = V

/4096

REF

011 ... 111

000 ... 010

000 ... 001

000 ... 000

CONVERTER OPERATION

The AD7887 is a successive approximation ADC built around a

charge-redistribution DAC. Figure 8 and Figure 9 show simplified

schematics of the ADC. Figure 8 shows the ADC during its

acquisition phase. SW2 is closed and SW1 is in Position A, the

comparator is held in a balanced condition, and the sampling

capacitor acquires the signal on AIN.

+V

REF

– 1.5LSB

0.5LSB

0V

ANALOG INPUT

Figure 10. Transfer Characteristic

TYPICAL CONNECTION DIAGRAM

Figure 11 shows a typical connection diagram for the AD7887.

The GND pin is connected to the analog ground plane of the

system. The part is in dual-channel mode so V_REFis internally

connected to a well-decoupled V_DDpin to provide an analog

input range of 0 V to V_DD. The conversion result is output in a

16-bit word with four leading zeros followed by the MSB of the

12-bit result. For applications where power consumption is of

concern, the automatic power-down at the end of conversion

should be used to improve power performance. See the Modes

of Operation section.

CHARGE

REDISTRIBUTION

DAC

SAMPLING

CAPACITOR

A

AIN

CONTROL

LOGIC

SW1

B

ACQUISITION

PHASE

SW2

COMPARATOR

AGND

(REF IN/REF OUT)/2

Figure 8. ADC Acquisition Phase

SUPPLY 2.7V

TO 5.25V

10µF

0.1µF

When the ADC starts a conversion (see Figure 9), SW2 opens

and SW1 moves to Position B, causing the comparator to become

unbalanced. The control logic and the charge-redistribution DAC

are used to add and subtract fixed amounts of charge from the

sampling capacitor to bring the comparator back into a balanced

condition. When the comparator is rebalanced, the conversion

is complete. The control logic generates the ADC output code.

Figure 10 shows the ADC transfer function.

SERIAL

INTERFACE

V

DD

AD7887

AIN1

SCLK

0V TO V

DD

µC/µP

INPUT

DOUT

DIN

AIN2

GND

CS

Figure 11. Typical Connection Diagram

Rev. D | Page 11 of 24

AD7887

–65

–70

–75

ANALOG INPUT

THD vs. FREQUENCY FOR DIFFERENT

SOURCE IMPEDANCES

Figure 12 shows an equivalent circuit of the analog input

structure of the AD7887. The two diodes, D1 and D2, provide

ESD protection for the analog inputs. Care must be taken to

ensure that the analog input signal never exceed the supply rails

by more than 200 mV. Exceeding this value causes the diodes

to become forward biased and to start conducting into the

substrate. The maximum current these diodes can conduct

without causing irreversible damage to the part is 20 mA.

However, it is worth noting that a small amount of current

(1 mA) being conducted into the substrate due to an

overvoltage on an unselected channel can cause inaccurate

conversions on a selected channel. Capacitor C1 in Figure 12 is

typically about 4 pF and can primarily be attributed to pin

capacitance. Resistor R1 is a lumped component made up of the

on resistance of a multiplexer and a switch. This resistor is

typically about 100 Ω. Capacitor C2 is the ADC sampling

capacitor and typically has a capacitance of 20 pF.

V

= 5V

DD

5V EXT REFERENCE

R

= 1kΩ, C = 100pF

IN

R

= 50Ω, C = 2.2nF

IN

–80

–85

–90

R

= 10Ω, C = 10nF

IN

0.15

10.89

21.14

31.59

42.14

49.86

INPUT FREQUENCY (kHz)

Figure 13. THD vs. Analog Input Frequency

On-Chip Reference

The AD7887 has an on-chip 2.5 V reference. This reference can

be enabled or disabled by clearing or setting the REF bit in the

control register, respectively. If the on-chip reference is to be used

externally in a system, it must be buffered before it is applied

elsewhere. If an external reference is applied to the device, the

internal reference is automatically overdriven. However, it is

advised to disable the internal reference by setting the REF bit

in the control register when an external reference is applied in

order to obtain optimum performance from the device. When

the internal reference is disabled, SW1, shown in Figure 14,

opens and the input impedance seen at the AIN1/V_REFpin is the

input impedance of the reference buffer, which is in the region

of gigaohms. When the internal reference is enabled, the input

impedance seen at the pin is typically 10 kΩ. When the AD7887

is operated in two-channel mode, the reference is taken from

V_DDinternally, not from the on-chip 2.5 V reference.

Note that the analog input capacitance seen when in track mode

is typically 38 pF, whereas in hold mode it is typically 4 pF.

V

DD

D1

C2

20pF

R1

V

IN

C1

4pF

D2

CONVERSION PHASE—SWITCH OPEN

TRACK PHASE—SWITCH CLOSED

Figure 12. Equivalent Analog Input Circuit

For ac applications, removing high frequency components from

the analog input signal is recommended by use of an RC

low-pass filter on the relevant analog input pin. In applications

where harmonic distortion and signal-to-noise ratio are critical,

the analog input should be driven from a low impedance

source. Large source impedances will significantly affect the ac

performance of the ADC. This may necessitate the use of an

input buffer amplifier. The choice of op amp is a function of the

particular application.

AIN1/V

REF

SW1

10kΩ

2.5V

Figure 14. On-Chip Reference Circuitry

When no amplifier is used to drive the analog input, the source

impedance should be limited to low values. The maximum

source impedance depends on the amount of total harmonic

distortion (THD) that can be tolerated. The THD increases as

the source impedance increases and performance degrades.

Figure 13 shows a graph of the total harmonic distortion vs. the

analog input signal frequency for different source impedances.

Rev. D | Page 12 of 24

AD7887

power vs. throughput rate for automatic shutdown with both

5 V and 3 V supplies.

POWER-DOWN OPTIONS

The AD7887 provides flexible power management to allow

the user to achieve the best power performance for a given

throughput rate.

10

The power management options are selected by programming

the power management bits (that is, PM1 and PM0) in the

control register. Table 6 summarizes the available options.

When the power management bits are programmed for either

V

= 5V

DD

SCLK = 2MHz

1

V

= 3V

of the auto power-down modes, the part enters power-down

DD

SCLK = 2MHz

th

CS

mode on the 16 rising SCLK edge after the falling edge of

.

0.1

CS

The first falling SCLK edge after the

falling edge causes the

part to power up again. When the AD7887 is in Mode 1, that is,

PM1 = PM0 = 0, the part enters shutdown on the rising edge of

0.01

CS

and power up from shutdown on the falling edge of . If

0

10

20

30

40

50

CS

is brought high during the conversion in this mode, the part

THROUGHPUT RATE (kSPS)

immediately enters shutdown.

Figure 15. Power vs. Throughput Rate

Power-Up Times

MODES OF OPERATION

The AD7887 has an approximate 1 μs power-up time when

powering up from standby or when using an external reference.

When V_DDis first connected the AD7887 powers up in Mode 1,

that is, PM1 = PM0 = 0. The part is put into shutdown on the

The AD7887 has several modes of operation that are designed

to provide flexible power management options. These options

can be chosen to optimize the power dissipation/throughput

rate ratio for differing application requirements. The modes of

operation are controlled by the PM1 and PM0 bits of the control

register, as previously outlined in Table 6. For read-only operation

of the AD7887, the default mode of all 0s in the control register

can be set up by tying the DIN line permanently low.

CS

rising edge of

in this mode. A subsequent power-up from

shutdown takes approximately 5 μs. The AD7887 wake-up time

is very short in the autostandby mode; therefore, it is possible to

wake up the part and carry out a valid conversion in the same

read/write operation.

Mode 1 (PM1 = 0, PM0 = 0)

POWER VS. THROUGHPUT RATE

This mode allows the user to control the powering down of the

By operating the AD7887 in autoshutdown mode, autostandby

mode, or Mode 1, the average power consumption of the

AD7887 decreases at lower throughput rates. Figure 15 shows

how as the throughput rate is reduced, the device remains in its

power-down state longer and the average power consumption

over time drops accordingly.

CS

part via the

powered up; whenever

CS

pin. Whenever

is low, the AD7887 is fully

is high, the AD7887 is in full

goes from high to low, all on-chip circuitry

CS

shutdown. When

starts to power up. It takes approximately 5 μs for the AD7887

internal circuitry to be fully powered up. As a result, a

conversion (or sample-and-hold acquisition) should not be

initiated during this 5 μs.

For example, if the AD7887 is operated in a continuous sampling

mode with a throughput rate of 10 kSPS and a SCLK of 2 MHz

(V_DD= 5 V), PM1 = 1 and PM0 = 0, that is, the device is in auto-

shutdown mode, and the on-chip reference is used, the power

consumption is calculated as follows: The power dissipation

during normal operation is 3.5 mW (V_DD= 5 V). If the power-up

time is 5 μs and the remaining conversion plus acquisition time

is 15.5 t_SCLK, that is, approximately 7.75 μs (see Figure 18), the

AD7887 can be said to dissipate 3.5 mW for 12.75 μs during

each conversion cycle. If the throughput rate is 10 kSPS, the

cycle time is 100 μs and the average power dissipated during

each cycle is (12.75/100) × (3.5 mW) = 446.25 μW. If V_DD= 3 V,

SCLK = 2 MHz, and the device is in autoshutdown mode using the

on-chip reference, the power dissipation during normal operation

is 2.1 mW. The AD7887 can now be said to dissipate 2.1 mW

for 12.75 μs during each conversion cycle. With a throughput

rate of 10 kSPS, the average power dissipated during each cycle

is (12.75/100) × (2.1 mW) = 267.75 μW. Figure 15 shows the

Figure 16 shows a general diagram of the operation of the

AD7887 in this mode. The input signal is sampled on the

second rising edge of SCLK following the

user should ensure that 5 μs elapses between the falling edge of

and the second rising edge of SCLK. In microcontroller

applications, this is readily achievable by driving the

from one of the port lines and ensuring that the serial data read

(from the microcontrollers serial port) is not initiated for 5 μs.

In DSP applications, where

serial frame synchronization line, it is usually not possible to

CS

to 5 μs without affecting the speed of the rest of the serial clock.

Therefore, the user must write to the control register to exit this

mode and (by writing PM1 = 0 and PM0 = 1) put the part into

Mode 2, that is, normal mode. A second conversion needs to be

initiated when the part is powered up to get a conversion result.

The write operation that takes place in conjunction with this

CS

falling edge. The

CS

input

CS

is generally derived from the

separate the

falling edge and second SCLK rising edge by up

Rev. D | Page 13 of 24

AD7887

second conversion can put the part back into Mode 1, and the

SCLK

between the first falling edge of

and the second rising

falling edge, as shown in Figure 18.

In microcontroller applications (or with a slow serial clock), this

CS

part goes into power-down mode when

returns high.

CS

edge of SCLK after the

Mode 2 (PM1 = 0, PM0 = 1)

is readily achievable by driving the

input from one of the

In this mode of operation, the AD7887 remains fully powered

CS

port lines and ensuring that the serial data read (from the

microcontroller’s serial port) is not initiated for 5 μs. However,

for higher speed serial clocks, it will not be possible to have a

5 μs delay between powering up and the first rising edge of the

SCLK. Therefore, the user must write to the control register to

exit this mode and (by writing PM1 = 0 and PM0 = 1) put the

part into Mode 2. A second conversion needs to be initiated

when the part is powered up to get a conversion result, as

shown in Figure 19. The write operation that takes place in

conjunction with this second conversion can put the part back

into Mode 3, and the part goes into power-down mode when

the conversion sequence ends.

up regardless of the status of the

line. It is intended for fastest

throughput rate performance because the user does not have to

worry about the 5 μs power-up time previously mentioned.

Figure 17 shows the general diagram of the operation of the

AD7887 in this mode.

The data presented to the AD7887 on the DIN line during the

first eight clock cycles of the data transfer are loaded to the

control register. To continue to operate in this mode, the user

must ensure that PM1 is loaded with 0 and PM0 is loaded with

1 on every data transfer.

CS

The falling edge of

initiates the sequence, and the input

signal is sampled on the second rising edge of the SCLK input.

Sixteen serial clock cycles are required to complete the conversion

and access the conversion result. Once a data transfer is complete

Mode 4 (PM1 = 1, PM0 = 1)

In this mode, the AD7887 automatically enters a standby (or

sleep) mode at the end of every conversion. In this standby

mode, all on-chip circuitry, apart from the on-chip reference, is

powered down. This mode is similar to Mode 3, but, in this

case, the power-up time is much shorter because the on-chip

reference remains powered up at all times.

CS

(that is, once returns high), another conversion can be initiated

CS

immediately by bringing

low again.

Mode 3 (PM1 = 1, PM0 = 0)

In this mode, the AD7887 automatically enters its full shutdown

mode at the end of every conversion. It is similar to Mode 1

Figure 20 shows the general diagram of the operation of the

AD7887 in this mode. On the first falling SCLK edge after

CS

except that the status of

does not have any effect on the

goes low, the AD7887 comes out of standby. The AD7887 wake-

up time is very short in this mode, so it is possible to wake up

the part and carry out a valid conversion in the same read/write

operation. The input signal is sampled on the second rising

power-down status of the AD7887.

Figure 18 shows the general diagram of the operation of the

CS

AD7887 in this mode. On the first falling SCLK edge after

goes low, all on-chip circuitry starts to power up. It takes

approximately 5 μs for the AD7887 internal circuitry to be fully

powered up. As a result, a conversion (or sample-and-hold

acquisition) should not be initiated during this 5 μs. The input

signal is sampled on the second rising edge of SCLK following

CS

edge of SCLK following the

falling edge. At the end of

conversion (last rising edge of SCLK), the part automatically

enters its standby mode.

CS

the

falling edge. The user should ensure that 5 μs elapses

Rev. D | Page 14 of 24

AD7887

THE PART POWERS UP ON CS

FALLING EDGE AS PM1 AND PM0 = 0

THE PART POWERS DOWN ON CS

RISING EDGE AS PM1 AND PM0 = 0

CS

16

1

SCLK

FOUR LEADING ZEROS + CONVERSION RESULT

DOUT

DIN

DATA IN

CONTROL REGISTER DATA IS LOADED ON THE FIRST EIGHT CLOCKS.

PM1 AND PM0 = 0 TO KEEP THE PART IN THIS MODE

Figure 16. Mode 1 Operation

THE PART REMAINS POWERED UP

AT ALL TIMES AS

PM1 = 0 AND PM0 = 1

CS

16

1

SCLK

DOUT

DIN

FOUR LEADING ZEROS + CONVERSION RESULT

DATA IN

CONTROL REGISTER DATA IS LOADED ON THE FIRST EIGHT CLOCKS.

PM1 = 0 AND PM0 = 1 TO KEEP THE PART IN THIS MODE

Figure 17. Mode 2 Operation

Rev. D | Page 15 of 24

AD7887

THE PART ENTERS

THE PART POWERS UP FROM

SHUTDOWN ON SCLK FALLING EDGE AS

PM1 = 1 AND PM0 = 0

SHUTDOWN AT THE END OF

CONVERSION AS PM1 = 1 AND PM0 = 0

CS

16

1

2

1

SCLK

t₁₀= 5µs

FOUR LEADING ZEROS + CONVERSION RESULT

DATA IN

DOUT

DIN

DATA IN

CONTROL REGISTER DATA IS LOADED ON THE

FIRST EIGHT CLOCKS. PM1 = 1 AND PM0 = 0

PM1 = 1 AND PM0 = 0 TO KEEP THE

PART IN THIS MODE

Figure 18. Mode 3 Operation (Microcontroller for Slow SCLKs)

THE PART ENTERS

SHUTDOWN AT THE END

OF CONVERSION AS

PM1 = 1 AND PM0 = 0

THE PART ENTERS

SHUTDOWN AT THE END OF

CONVERSION AS PM1 = 1

AND PM0 = 0

THE PART BEGINS TO POWER

UP FROM SHUTDOWN

THE PART REMAINS POWERED UP

AS PM1 = 0 AND PM0 = 1

CS

8

16

8

16

1

8

16

SCLK

FOUR LEADING ZEROS

+ CONVERSION RESULT

FOUR LEADING ZEROS

+ CONVERSION RESULT

FOUR LEADING ZEROS

+ CONVERSION RESULT

DOUT

DIN

DATA IN

CONTROL REGISTER DATA IS LOADED ON

THE FIRST EIGHT CLOCKS. PM1 = 1 AND PM0 = 0

PM1 = 0 AND PM0 = 1 TO PLACE

THE PART IN NORMAL MODE

PM1 = 1 AND PM0 = 0 TO PLACE

THE PART BACK IN MODE 3

Figure 19. Mode 3 Operation (Microcontroller for High Speed SCLKs)

THE PART POWERS UP

FROM STANDBY ON SCLK

FALLING EDGE AS PM1 = 1

AND PM0 = 1

THE PART ENTERS

STANDBY AT THE END OF

CONVERSION AS

PM1 = 1 AND PM0 = 1

CS

16

1

SCLK

FOUR LEADING ZEROS + CONVERSION RESULT

DATA IN

DOUT

DIN

DATA IN

CONTROL REGISTER DATA IS LOADED ON

THE FIRST EIGHT CLOCKS. PM1 = 1 AND PM0 = 1

PM1 = 1 AND PM0 = 1 TO KEEP

THE PART IN THIS MODE

Figure 20. Mode 4 Operation

Rev. D | Page 1± of 24

AD7887

the channel address for the next conversion while the present

conversion is in progress.

SERIAL INTERFACE

Figure 21 shows the detailed timing diagrams for serial

interfacing to the AD7887. The serial clock provides the

conversion clock and also controls the transfer of information

to and from the AD7887 during conversion.

Writing of information to the control register takes place on the

first eight rising edges of SCLK in a data transfer. The control

register is always written to when a data transfer takes place.

However, the AD7887 can be operated in a read-only mode by

tying DIN low, thereby loading all 0s to the control register

every time. When operating the AD7887 in write/read mode,

the user must be careful to always set up the correct

CS

initiates the data transfer and conversion process. For some

CS

modes, the falling edge of

wakes up the part. In all cases, it

gates the serial clock to the AD7887 and puts the on-chip

track/hold into track mode. The input signal is sampled on the

second rising edge of the SCLK input after the falling edge of

information on the DIN line when reading data from the part.

Sixteen serial clock cycles are required to perform the con-

version process and to access data from the AD7887. In

CS

. Thus, the first one and one-half clock cycles after the falling

CS

edge of

are when the acquisition of the input signal takes

CS

applications where the first serial clock edge following

going

place. This time is denoted as the acquisition time (t_ACQ). In

CS

low is a falling edge, this edge clocks out the first leading zero.

Thus, the first rising clock edge on the SCLK clock has the first

leading zero provided. In applications where the first serial

modes where the falling edge of

wakes up the part, the

acquisition time must allow for the wake-up time of 5 μs. The

on-chip track/hold goes from track mode to hold mode on the

second rising edge of SCLK, and a conversion is also initiated

on this edge. The conversion process takes an additional

fourteen and one-half SCLK cycles to complete. The rising edge

CS

clock edge following

going low is a rising edge, the first

leading zero may not be set up in time for the processor to read

it correctly. However, subsequent bits are clocked out on the

falling edge of SCLK so that they are provided to the processor

on the following rising edge. Thus, the second leading zero is

clocked out on the falling edge subsequent to the first rising

edge. The final bit in the data transfer is valid on the 16^thrising

edge, having been clocked out on the previous falling edge.

CS

of

puts the bus back into three-state. If

is left low, a new

conversion can be initiated.

In dual-channel operation, the input channel that is sampled is

the one that was selected in the previous write to the control

register. Thus, in dual-channel operation, the user must write

t_ACQ

t_CONVERT

CS

t₆

t₁

16

1

2

3

4

5

6

15

SCLK

DOUT

t₈

t₂

t₇

t₃

DB11

THREE-

STATE

THREE-

STATE

FOUR LEADING ZEROS

DB10

DB9

DB0

t₄

t₅

ZERO

REF

SIN/DUAL

CH

ZERO

PM1

PM0

DONTC

DIN

Figure 21. Serial Interface Timing Diagram

Rev. D | Page 17 of 24

AD7887

this example however, the timer interrupt is used to control the

sampling rate of the ADC and, under certain conditions,

equidistant sampling cannot be achieved.

MICROPROCESSOR INTERFACING

The serial interface on the AD7887 allows the part to be directly

connected to a range of many different microprocessors. This

section explains how to interface the AD7887 with some of the

more common microcontroller and DSP serial interface

protocols.

The timer registers are loaded with a value that will provide an

interrupt at the required sample interval. When an interrupt is

received, a value is transmitted with TFS/DT (ADC control

word). The TFS is used to control the RFS and hence the

reading of data. The frequency of the serial clock is set in the

SCLKDIV register. When the instruction to transmit with TFS

is given (that is, AX0 = TX0), the state of the SCLK is checked.

The DSP waits until the SCLK has gone high, low, and high

again before a transmission starts. If the timer and SCLK values

are chosen such that the instruction to transmit occurs on or

near the rising edge of SCLK, the data may be transmitted or it

may wait until the next clock edge.

AD7887 to TMS320C5x

The serial interface on the TMS320C5x uses a continuous serial

clock and frame synchronization signals to synchronize the data

transfer operations with peripheral devices like the AD7887.

CS

The

input allows easy interfacing with an inverter between

the serial clock of the TMS320C5x and the AD7887 being the

only glue logic required. The serial port of the TMS320C5x is

set up to operate in burst mode with internal CLKX (Tx serial

clock) and FSX (Tx frame sync). The serial port control register

(SPC) must have the following setup: FO = 0, FSM = 1,

MCM = 1, and TXM = 1. The connection diagram is shown in

Figure 22.

For example, the ADSP-2111 has a master clock frequency of

16 MHz. If the SCLKDIV register is loaded with the value 3, a

SCLK of 2 MHz is obtained and eight master clock periods will

elapse for every one SCLK period. If the timer registers are

loaded with the value 803, 100.5 SCLKs will occur between

interrupts and subsequently between transmit instructions. This

situation results in nonequidistant sampling because the

transmit instruction is occurring on an SCLK edge. If the

number of SCLKs between interrupts is a whole integer number

of N, equidistant sampling will be implemented by the DSP.

1

AD7887¹

TMS320C5x

CLKX

CLKR

DR

SCLK

DOUT

DIN

DT

CS

FSX

FSR

1

AD7887¹

ADSP-21xx

SCLK

DOUT

DIN

1

ADDITIONAL PINS OMITTED FOR CLARITY.

DR

Figure 22. Interfacing to the TMS320C5x

DT

AD7887 to ADSP-21xx

RFS

TFS

CS

The ADSP-21xx family of DSPs are easily interfaced to the

AD7887 with an inverter between the serial clock of the ADSP-

21xx and the AD7887. This is the only glue logic required. The

SPORT control register should be set up as follows:

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 23. Interfacing to the ADSP-21xx

AD7887 to DSP56xxx

Table 7. SPORT0 Control Register Setup

The connection diagram in Figure 24 shows how the AD7887

can be connected to the SSI (synchronous serial interface) of

the DSP56xxx family of DSPs from Motorola. The SSI is

operated in synchronous mode (SYN bit in CRB = 1) with an

internally generated 1-bit clock period frame sync for both Tx

and Rx (Bits FSL1 = 1 and FSL0 = 0 in CRB). Set the word

length to 16 by setting bits WL1 = 1 and WL0 = 0 in CRA. An

inverter is also necessary between the SCLK from the DSP56xxx

and the SCLK pin of the AD7887, as shown in Figure 24.

Setting

Description

TFSW = RFSW = 1

INVRFS = INVTFS = 1

DTYPE = 00

SLEN = 1111

ISCLK = 1

TFSR = RFSR = 1

IRFS = 0

ITFS = 1

Alternative framing

Active low frame signal

Right justify data

1±-bit data-word

Internal serial clock

Frame every word

1

AD7887¹

DSP56xxx

SCLK

DOUT

DIN

SCK

SRD

STD

SC2

The connection diagram is shown in Figure 23. The ADSP-21xx

has the TFS and RFS of the SPORT tied together, with TFS set

as an output and RFS set as an input. The DSP operates in

alternate framing mode, and the SPORT control register is set

up as described in Table 7. The frame synchronization signal

CS

generated on the TFS is tied to

and, as with all signal

1

ADDITIONAL PINS OMITTED FOR CLARITY.

processing applications, equidistant sampling is necessary. In

Figure 24. Interfacing to the DSP56xxx

Rev. D | Page 18 of 24

AD7887

AD7887 to MC68HC11

1

AD7887¹

8051

P1.0

P1.1

P1.2

P1.3

SCLK

The serial peripheral interface (SPI) on the MC68HC11 is

configured for master mode (MSTR = 1) when the clock

polarity bit (CPOL) = 1 and the clock phase bit (CPHA) = 1.

The SPI is configured by writing to the SPI Control Register

(SPCR)—see the M68HC11 reference manual from Freescale

Semiconductor, Inc., for more information. The serial transfer

takes place as two 8-bit operations. A connection diagram is

shown in Figure 25.

DOUT

DIN

CS

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 26. Interfacing to the 8051 Using Input/Output Ports

AD7887 to PIC16C6x/PIC16C7x

1

AD7887¹

MC68HC11

The PIC16C6x synchronous serial port (SSP) is configured as an

SPI master with the clock polarity bit = 1. This is done by writing to

the synchronous serial port control register (SSPCON). See the

PIC16/PIC17 Microcontroller User Manual. Figure 27 shows the

hardware connections needed to interface to the PIC16C6x/

PIC16C7x. In this example, input/output port RA1 is being used to

pulse . This microcontroller only transfers eight bits of data

during each serial transfer operation. Therefore, two consecutive

read/write operations are needed.

SCLK/PD4

MISO/PD2

MOSI/PD3

SCLK

DOUT

DIN

PA0

CS

1

ADDITIONAL PINS OMITTED FOR CLARITY.

CS

Figure 25. Interfacing to the MC68HC11

AD7887 to 8051

PIC16C6x/

AD7887¹

It is possible to implement a serial interface using the data ports

on the 8051. This allows a full duplex serial transfer to be imple-

mented. The technique involves bit-banging an input/output

port (for example, P1.0) to generate a serial clock and using two

other input/output ports (for example, P1.1 and P1.2) to shift

data in and out—see Figure 26.

1

PIC16C7x

SCK/RC3

SCLK

SDI/RC4

SDO/RC5

RA1

DOUT

DIN

CS

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 27. Interfacing to the PIC16C6x/PIC16C7x

Rev. D | Page 19 of 24

AD7887

and analog signals. Traces on opposite sides of the board should

run at right angles to each other. This reduces the effects of

feedthrough through the board. A microstrip technique is by far

the best approach, but it is not always possible with a double-

sided board. In this technique, the component side of the board

is dedicated to ground planes, and signals are placed on the

solder side.

APPLICATION HINTS

Grounding and Layout

The AD7887 has very good immunity to noise on the power

supplies, as can be seen in Figure 7. However, care should still

be taken with regard to grounding and layout.

The printed circuit board that houses the AD7887 should be

designed so that the analog and digital sections are separated

and confined to certain areas of the board. This facilitates the

use of ground planes that can be easily separated. A minimum

etch technique is generally best for ground planes because it

results in the best shielding. Digital and analog ground planes

should be joined in only one place, as close as possible to the

GND pin of the AD7887. If the AD7887 is in a system where

multiple devices require AGND-to-DGND connections, the

connection should still be made at one point only, a star ground

point, which should be established as close as possible to the

AD7887.

Good decoupling is also important. All analog supplies should

be decoupled with 10 μF tantalum in parallel with 0.1 μF

capacitors to AGND. To achieve the best from these decoupling

components, they must be placed as close as possible to the

device, ideally right up against the device.

Evaluating the AD7887 Performance

The recommended layout for the AD7887 is outlined in the

evaluation board for the AD7887. The evaluation board

package includes a fully assembled and tested evaluation board,

documentation, and software for controlling the board from the

PC via the EVAL-CONTROL BOARD. The EVAL-CONTROL

BOARD can be used in conjunction with the AD7887

evaluation board, as well as many other Analog Devices, Inc.,

evaluation boards ending in the CB designator, to

demonstrate/evaluate the ac and dc performance of the

AD7887.

Avoid running digital lines under the device because these will

couple noise onto the die. The analog ground plane should be

allowed to run under the AD7887 to avoid noise coupling. The

power supply lines to the AD7887 should use as large a trace as

possible to provide low impedance paths and reduce the effects

of glitches on the power supply line. Fast switching signals like

clocks should be shielded with digital ground to avoid radiating

noise to other sections of the board, and clock signals should

never be run near the analog inputs. Avoid crossover of digital

The software allows the user to perform ac (fast Fourier

transform) and dc (histogram of codes) tests on the AD7887.

Rev. D | Page 20 of 24

AD7887

OUTLINE DIMENSIONS

3.20

3.00

2.80

5.00 (0.1968)

4.80 (0.1890)

8

1

5

4

8

1

5

4

5.15

4.90

4.65

6.20 (0.2440)

5.80 (0.2284)

4.00 (0.1574)

3.80 (0.1497)

3.20

3.00

2.80

0.50 (0.0196)

0.25 (0.0099)

1.27 (0.0500)

BSC

45°

PIN 1

1.75 (0.0688)

1.35 (0.0532)

0.65 BSC

0.25 (0.0098)

8°

0°

0.95

0.85

0.75

0.10 (0.0040)

1.10 MAX

0.51 (0.0201)

0.31 (0.0122)

COPLANARITY

0.10

1.27 (0.0500)

0.40 (0.0157)

0.25 (0.0098)

0.17 (0.0067)

0.80

0.60

0.40

SEATING

PLANE

8°

0°

0.15

0.00

0.38

0.22

0.23

0.08

SEATING

PLANE

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MS-012-AA

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 28. 8-Lead Standard Small Outline Package [SOIC_N]

Figure 29. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Narrow Body

(R-8)

Dimensions shown in millimeters

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Linearity

Model

Error¹

±2 LSB

±1 LSB

±2 LSB

Temperature

Package Description

Package Option

Branding

AD7887AR

−40°C to +125°C

8-Lead Standard Small Outline Package [SOIC_N]

8-Lead Mini Small Outline Package [MSOP]

8-Lead Standard Small Outline Package [SOIC_N]

8-Lead Mini Small Outline Package [MSOP]

Evaluation Board

R-8

RM-8

R-8

AD7887AR-REEL

AD7887AR-REEL7

AD7887ARZ²

AD7887ARZ-REEL²

AD7887ARZ-REEL7²

AD7887ARM

AD7887ARM-REEL

AD7887ARM-REEL7

AD7887ARMZ²

AD7887ARMZ-REEL²

AD7887ARMZ-REEL7²

AD7887BR

AD7887BR-REEL

AD7887BR-REEL7

AD7887BRZ²

AD7887BRZ-REEL²

AD7887BRZ-REEL7²

AD7887WARMZ^{2, 3}

EVAL-AD7887CB⁴

EVAL-CONTROL BRD2⁵

C5A

C5A#

R-8

RM-8

C5A#

Controller Board

¹Linearity error here refers to integral linearity error.

²Z = RoHS Compliant Part, # denotes lead-free product, may be top or bottom marked.

³Qualified for automotive.

⁴This can be used as a standalone evaluation board or can be used in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes.

⁵This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator.

Rev. D | Page 21 of 24

AD7887

NOTES

Rev. D | Page 22 of 24

AD7887

NOTES

Rev. D | Page 23 of 24

AD7887

NOTES

registered trademarks are the property of their respective owners.

D06191-0-2/09(D)

Rev. D | Page 24 of 24


型号：	EVAL-AD7887CB4
厂家：	ADI
描述：	2.7 V to 5.25 V, Micropower, 2-Channel, 125 kSPS, 12-Bit ADC in 8-Lead MSOP 2.7 V至5.25 V ，微功耗，双通道， 125 kSPS时， 12位ADC，采用8引脚MSOP
文件：	总24页 (文件大小：444K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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