EVAL-ADF4150EB1Z_技术文档

Fractional-N/Integer-N PLL Synthesizer

ADF4150

FEATURES

GENERAL DESCRIPTION

Fractional-N synthesizer and integer-N synthesizer

Programmable divide-by-1/-2/-4/-8/-16 output

5.0 GHz RF bandwidth

3.0 V to 3.6 V power supply

1.8 V logic compatibility

Separate charge pump supply (V_P) allows extended tuning

voltage in 3 V systems

Programmable dual-modulus prescaler of 4/5 or 8/9

Programmable output power level

RF output mute function

The ADF4150 allows implementation of fractional-N or

integer-N phase-locked loop (PLL) frequency synthesizers

if used with an external voltage-controlled oscillator (VCO),

loop filter, and external reference frequency.

The ADF4150 is for use with external VCO parts and is

software compatible with the ADF4350. The VCO frequency

can be divided by 1/2/4/8/16 to allow the user to generate RF

output frequencies as low as 31.25 MHz. For applications that

require isolation the RF output stage can be muted. The mute

function is both pin and software controllable.

3-wire serial interface

Control of all the on-chip registers is through a simple 3-wire

interface. The device operates with a power supply ranging

from 3.0 V to 3.6 V and can be powered down when not in use.

Analog and digital lock detect

Switched bandwidth fast-lock mode

Cycle slip reduction

The ADF4150 is available in a 4 mm × 4 mm package.

APPLICATIONS

Wireless infrastructure (W-CDMA, TD-SCDMA, WiMax, GSM,

PCS, DCS, DECT)

Test equipment

Wireless LANs, CATV equipment

Clock generation

FUNCTIONAL BLOCK DIAGRAM

SDV

AV

DV

V

R

SET

DD

P

MULTIPLEXER

MUXOUT

10-BIT R

COUNTER

÷2

DIVIDER

×2

REF

IN

DOUBLER

LOCK

DETECT

SW

LD

FL SWITCH

O

CLK

DATA

LE

DATA REGISTER

FUNCTION

LATCH

CHARGE

PUMP

CP

OUT

PHASE

COMPARATOR

RF

+

OUT

OUTPUT

STAGE

DIVIDE-BY-1/

-2/-4/-8/-16

INTEGER

REG

FRACTION

REG

MODULUS

REG

–

OUT

PDB

RF

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

RF

+

–

RF

INPUT

IN

MULTIPLEXER

RF

IN

N COUNTER

ADF4150

CE

A

CP

SD

GND

Figure 1.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADF4150

TABLE OF CONTENTS

Features .............................................................................................. 1

Register 1 ..................................................................................... 18

Register 2 ..................................................................................... 18

Register 3 ..................................................................................... 20

Register 4 ..................................................................................... 20

Register 5 ..................................................................................... 20

Initialization Sequence .............................................................. 20

RF Synthesizer—A Worked Example ...................................... 21

Modulus....................................................................................... 21

Reference Doubler and Reference Divider ............................. 21

12-Bit Programmable Modulus................................................ 21

Cycle Slip Reduction for Faster Lock Times........................... 22

Spurious Optimization and Fast lock ...................................... 22

Fast Lock Timer and Register Sequences................................ 22

Fast Lock—An Example ............................................................ 23

Fast Lock—Loop Filter Topology............................................. 23

Spur Mechanisms ....................................................................... 23

Spur Consistency and Fractional Spur Optimization ........... 24

Phase Resync............................................................................... 24

Applications Information .............................................................. 25

Direct Conversion Modulator .................................................. 25

Interfacing ................................................................................... 26

PCB Design Guidelines for Chip Scale Package .................... 26

Output Matching........................................................................ 27

Outline Dimensions....................................................................... 28

Ordering Guide .......................................................................... 28

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 6

Transistor Count........................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 9

Circuit Description......................................................................... 11

Reference Input Section............................................................. 11

RF N Divider............................................................................... 11

INT, FRAC, MOD, and R Counter Relationship.................... 11

INT N Mode................................................................................ 11

R Counter .................................................................................... 11

Phase Frequency Detector (PFD) and Charge Pump............ 11

MUXOUT and Lock Detect...................................................... 12

Input Shift Registers................................................................... 12

Program Modes .......................................................................... 12

Output Stage................................................................................ 12

Register Maps.................................................................................. 13

Register 0 ..................................................................................... 18

REVISION HISTORY

7/11—Revision 0: Initial Version

Rev. 0 | Page 2 of 28

ADF4150

SPECIFICATIONS

AV_DD= DV_DD= SD_VDD= 3.3 V 10%; V_P= AV_DDto 5.5 V; AGND = DGND = 0 V; T_A= T_MINto T_MAX, unless otherwise noted. The

operating temperature range is −40°C to +85°C.

Table 1.

B Version

Parameter

Min

Typ

Max

Unit

Conditions/Comments

REF_INCHARACTERISTICS

Input Frequency

Input Sensitivity

Input Capacitance

Input Current

10

0.7

250

AV_DD

5.0

MHz

V p-p

pF

For f < 10 MHz ensure slew rate > 21 V/µs

Biased at AV_DD/2¹

60

µA

RF INPUT CHARACTERISTICS

RF Input Frequency (RF_IN), RF Output

Buffer Disabled

RF Input Frequency (RF_IN), RF Output

Buffer Disabled

RF Input Frequency (RF_IN) RF Output

Buffer Enabled

RF Input Frequency (RF_IN) RF Output

Buffer and Dividers Enabled

Prescaler Output Frequency

MAXIMUM PFD FREQUENCY

Fractional-N (Low Spur Mode)

Fractional-N Mode (Low Noise Mode)

Integer-N Mode

0.5

4.0

5.0

3.5

3.0

750

GHz

MHz

−10 dBm ≤ RF input power ≤ +5 dBm

−5 dBm ≤ RF input power ≤ +5 dBm

−10 dBm ≤ RF input power ≤ +5 dBm

26

32

MHz

CHARGE PUMP

I_CPSink/Source

R_SET= 5.1 kΩ

High Value

Low Value

R_SETRange

I_CPLeakage

Sink and Source Current Matching

I_CPvs. V_CP

I_CPvs. Temperature

LOGIC INPUTS

4.65

0.29

mA

kΩ

nA

%

2.7

10

1

2

1

2

V_CP= V_P/2

0.5 V ≤ V_CP≤ V_P− 0.5 V

V_CP= V_P/2

%

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_INH/I_INL

Input Capacitance, C_IN

LOGIC OUTPUTS

1.5

V

µA

pF

0.6

1

3.0

Output High Voltage, V_OH

Output High Current, I_OH

Output Low Voltage, V_O

POWER SUPPLIES

AV_DD

DV_DD− 0.4

V

µA

V

CMOS output chosen

I_OL= 500 µA

500

0.4

3.0

3.6

V

DV_DD, SD_VDD

AV_DD

V_P

AV_DD

5.5

60

V

2

DI_DD+ AI_DD

Output Dividers

I_RFOUT

50

6 to 24

24

1

mA

µA

Each output divide by two consumes 6 mA

RF output stage is programmable

2

32

Low Power Sleep Mode

Rev. 0 | Page 3 of 28

ADF4150

B Version

Typ

Parameter

Min

Max

Unit

Conditions/Comments

RF OUTPUT CHARACTERISTICS

Minimum Output Frequency Using RF 31.25

Output Dividers

Maximum RF_INFrequency Using RF

Output Dividers

MHz

500 MHz VCO input and divide-by-16 selected

4400

Harmonic Content (Second)

Harmonic Content (Third)

Harmonic Content (Second)

Harmonic Content (Third)

Output Power ³

−19

−13

−20

−10

−4

dBc

dBm

dB

Fundamental VCO output

Divided VCO output

Maximum setting

+5

1

Minimum setting

Output Power Variation

Level of Signal With RF Mute Enabled

NOISE CHARACTERISTICS

−40

dBm

−223

dBc/Hz

Normalized Phase Noise Floor

PLL loop BW = 500 kHz (ABP = 3 ns)

4

(PN_SYNTH

Normalized 1/f Noise (PN_{1_f}

)

5

dBc/Hz

)

−123

−222

10 kHz offset. Normalized to 1 GHz. (ABP = 3 ns)

PLL loop BW = 500 kHz (ABP = 6 ns); low noise

mode selected

10 kHz offset; normalized to 1 GHz; (ABP = 6 ns);

low noise mode selected

Normalized Phase Noise Floor

4

(PN_SYNTH

)

5

dBc/Hz

Normalized 1/f Noise (PN_{1_f}

)

−119

Spurious Signals Due to PFD

Frequency⁶

−90

−75

dBc

VCO output

RF output buffers

¹AC coupling ensures AV_DD/2 bias.

²T_A= 25°C; AV_DD= DV_DD= 3.3 V; prescaler = 8/9; f_REFIN= 100 MHz; f_PFD= 26 MHz; f_RF= 1.7422 GHz.

³Using a tuned load.

⁴The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider

value) and 10 log F_PFD. PN_SYNTH= PN_TOT− 10logF_PFD− 20logN.

⁵The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (F_RF)

and at a frequency offset (f) is given by PN = P_{1_f}+ 10log(10 kHz/f) + 20log(F_RF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.

⁶Spurious measured on EVAL-ADF4150EB1Z, using a Rohde & Schwarz FSUP signal source analyzer.

Rev. 0 | Page 4 of 28

ADF4150

TIMING CHARACTERISTICS

AV_DD= DV_DD= SD_VDD= 3.3 V 10%; V_P= AV_DDto 5.5 V; AGND = DGND = 0 V; T_A= T_MINto T_MAX, unless otherwise noted. Operating

temperature range is −40°C to +85°C.

Table 2.

Parameter

Limit (B Version)

Unit

Test Conditions/Comments

LE setup time

DATA to CLK setup time

DATA to CLK hold time

CLK high duration

CLK low duration

t₁

t₂

t₃

t₄

t₅

t₆

t₇

20

10

25

10

20

ns min

CLK to LE setup time

LE pulse width

t₄

t₅

CLK

t₂

t₃

DB2

(CONTROL BIT C3)

DB1

DB0 (LSB)

(CONTROL BIT C1)

DB31 (MSB)

DB30

DATA

LE

(CONTROL BIT C2)

t₇

t₁

t₆

LE

Figure 2. Timing Diagram

Rev. 0 | Page 5 of 28

ADF4150

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 3.

Parameter

AV_DDto GND¹

Rating

−0.3 V to +3.9 V

−0.3 V to +0.3 V

−0.3 V to +5.8 V

−0.3 V to V_DD+ 0.3 V

−40°C to +85°C

−65°C to +125°C

150°C

AV_DDto DV_DD

V_Pto AV_DD

Digital I/O Voltage to GND¹

Analog I/O Voltage to GND¹

REF_INto GND¹

Operating Temperature Range

Storage Temperature Range

Maximum Junction Temperature

LFCSP θ_JAThermal Impedance

(Paddle-Soldered)

TRANSISTOR COUNT

23380 (CMOS) and 809 (bipolar)

ESD CAUTION

27.3°C/W

Reflow Soldering

Peak Temperature

Time at Peak Temperature

260°C

40 sec

¹GND = AGND = DGND = 0 V.

Rev. 0 | Page 6 of 28

ADF4150

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

CLK

DATA

LE

CE

SW

1

2

3

4

5

6

18 DV

17 PDB

16 AV

DD

RF

2

ADF4150

TOP VIEW

(Not to Scale)

DD

15 RF

14 RF

+

−

OUT

V

13 A

P

GND

NOTES

1. THE LFCSP HAS AN EXPOSED PADDLE

THAT MUST BE CONNECTED TO GND.

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

CLK

Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high

impedance CMOS input.

2

3

4

DATA

LE

Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high

impedance CMOS input.

Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register

that is selected by the three LSBs.

Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state

mode. Taking the pin high powers up the device depending on the status of the power-down bits.

CE

5

6

SW

V_P

Fastlock Switch. Make a connection to this pin from the loop filter when using the fastlock mode.

Charge Pump Power Supply. This pin should be greater than or equal to AV_DD. In systems where AV_DDis 3 V, it

can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.

7

CP_OUT

Charge Pump Output. When enabled, this provides I_CPto the external loop filter. The output of the loop filter

is connected to V_TUNEto drive the external VCO.

8

9

CP_GND

Charge Pump Ground. This is the ground return pin for CP_OUT

Analog Power Supply. This pin ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane

.

AV_DD

1

are to be placed as close as possible to this pin. AV_DDmust have the same value as DV_DD

Input to the RF Input. This small signal input is ac-coupled to the external VCO.

Complementary Input to the RF Input. This point must be decoupled to the ground plane with a small bypass

capacitor, typically 100 pF.

.

10

11

RF_IN+

RF_IN−

12, 13

14

A_GND

RF_OUT

Analog Ground. This is a ground return pin for AV_DD1 and AV_DD2.

Complementary RF Output. The output level is programmable. The VCO fundamental output or a divided

down version is available.

RF Output. The output level is programmable. The VCO fundamental output or a divided down version is

available.

Analog Power Supply. This pin ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane

−

+

15

16

RF_OUT

AV_DD

2

are to be placed as close as possible to this pin. AV_DD2 must have the same value as DV_DD

.

17

18

PDB_RF

DV_DD

RF Power-Down. A logic low on this pin mutes the RF outputs. This function is also software controllable.

Digital Power Supply. This pin should be the same voltage as AV_DD. Place decoupling capacitors to the ground

plane as close as possible to this pin.

19

20

21

REF_IN

Reference Input. This is a CMOS input with a nominal threshold of V_DD/2 and a dc equivalent input resistance

of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.

Lock Detect Output Pin. This pin outputs a logic high to indicate PLL lock; a logic low output indicates loss of

PLL lock.

Multiplexer Output. This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference

frequency to be accessed externally.

LD

MUXOUT

Rev. 0 | Page 7 of 28

ADF4150

Pin No.

Mnemonic

Description

22

SDV_DD

Power Supply Pin for the Digital Sigma-Delta (Σ-Δ) Modulator. This pin should be the same voltage as AV_DD

Decoupling capacitors to the ground plane are to be placed as close as possible to this pin.

.

23

24

SD_GND

R_SET

Digital Σ-Δ Modulator Ground. Ground return path for the Σ-Δ modulator.

Connecting a resistor between this pin and GND sets the charge pump output current. The nominal voltage

bias at the R_SETpin is 0.48 V. The relationship between I_CPand R_SETis

23.9

I_CP

=

R_SET

where:

R_SET= 5.1 kΩ.

I_CP= 5 mA.

25

EP

The exposed pad must be connected to GND.

Rev. 0 | Page 8 of 28

ADF4150

TYPICAL PERFORMANCE CHARACTERISTICS

–60

0

–5

–80

–100

–120

–140

–160

–180

–10

–15

–20

–25

–30

–35

–40

+25°C

+85°C

–40°C

–45

–50

1k

10k

100k

1M

10M

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5 5.0

FREQUENCY (GHz)

FREQUENCY (Hz)

Figure 4. RF Input Sensitivity; RF Output Enabled; Output Divide-by-1

Selected

Figure 7. Integer-N Phase Noise and Spur Performance; Low Noise Mode;

VCOOUT = 1750 MHz, REF_IN= 100 MHz, PFD = 25 MHz, Loop Filter

Bandwidth= 50 kHz

10

0

–60

–80

–100

–120

–140

–160

–180

–10

–20

–30

–40

+25°C

+85°C

–40°C

–50

0

1

2

3

4

5

6

1M

10M

100M

1G

10G

FREQUENCY (MHz)

FREQUENCY (Hz)

Figure 5. RF Input Sensitivity; RF Output Disabled

Figure 8. Fractional-N Phase Noise and Spur Performance; Low Noise Mode;

VCOOUT = 1750 MHz, REF_IN= 100 MHz, PFD = 25 MHz, Loop Filter

Bandwidth= 15 kHz, Channel Spacing = 200 kHz. FRAC = 26, MOD = 125

–60

0

–5

–80

–100

–120

–140

–160

–180

–10

–15

–20

–25

–30

–35

+25°C

+85°C

–40°C

–40

1k

10k

100k

1M

10M

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

FREQUENCY (Hz)

FREQUENCY (GHz)

Figure 6. RF Sensitivity; RF Output Enabled (RF Dividers-by-2/-4/-8/-16

Enabled)

Figure 9. Fractional-N Phase Noise and Spur Performance; Low Spur Mode;

VCOOUT = 1750 MHz, REF_IN= 100 MHz, PFD = 25 MHz, Loop Filter

Bandwidth= 50 kHz, Channel Spacing = 200 kHz. FRAC = 26, MOD = 125

Rev. 0 | Page 9 of 28

ADF4150

–60

–80

–100

–120

–140

–160

–100

–120

–140

–160

–180

1k

10k

100k

1M

10M

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 10. RF Output Phase Noise RF Dividers Used; Integer-N; Low Noise

Mode; VCOOUT = 1750 MHz, REF_IN= 100 MHz, PFD = 25 MHz, Loop Filter

Bandwidth = 50 kHz

Figure 12. RF Buffer Output Fractional-N Phase Noise and Spur Performance;

Low Noise Mode; VCOOUT = 1750 MHz, REF_IN= 100 MHz, PFD = 25 MHz,

Loop Filter Bandwidth = 15 kHz, Channel Spacing = 200 kHz; FRAC = 1,

MOD = 5; Output Divider = 2

–60

–80

–60

–80

–100

–120

–140

–160

–180

–100

–120

–140

–160

–180

1k

10k

100k

1M

10M

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 13. RF Buffer Output Fractional-N Phase Noise and Spur Performance;

Low Noise Mode; VCOOUT = 1750 MHz, REF_IN= 100 MHz, PFD = 25 MHz,

Loop Filter Bandwidth = 15 kHz, Channel Spacing = 200 kHz. FRAC = 1,

MOD = 5. Output divider = 4

Figure 11. RF Buffer Output Fractional-N Phase Noise and Spur Performance;

Low Noise Mode; VCOOUT = 1750 MHz, REF_IN= 100 MHz, PFD = 25 MHz,

Loop Filter Bandwidth = 15 kHz, Channel Spacing = 200 kHz; FRAC = 1,

MOD = 5; Output Divider = 1

Rev. 0 | Page 10 of 28

ADF4150

CIRCUIT DESCRIPTION

RF N DIVIDER

N COUNTER

N = INT + FRAC/MOD

REFERENCE INPUT SECTION

FROM

VCO OUTPUT/

OUTPUT DIVIDERS

The reference input stage is shown in Figure 14. SW1 and SW2

are normally closed switches. SW3 is normally open. When

power-down is initiated, SW3 is closed and SW1 and SW2 are

opened. This ensures that there is no loading of the REF_INpin

on power-down.

TO PFD

THIRD ORDER

FRACTIONAL

INTERPOLATOR

POWER-DOWN

CONTROL

INT

REG

MOD

REG

FRAC

VALUE

100kΩ

SW2

NC

TO R COUNTER

REF

IN

Figure 15. RF INT Divider

NC

SW1

BUFFER

SW3

INT N MODE

NO

If the FRAC = 0 and DB8 in Register 2 (LDF) is set to 1, the

synthesizer operates in integer-N mode. The DB8 in Register 2

(LDF) should be set to 1 to get integer-N digital lock detect.

Additionally, lower phase noise is possible if the anti-backlash

pulse width is reduced to 3 ns. This mode is not valid for

fractional-N applications.

Figure 14. Reference Input Stage

RF N DIVIDER

The RF N divider allows a division ratio in the PLL feedback

path. Division ratio is determined by INT, FRAC, and MOD

values, which build up this divider.

R COUNTER

INT, FRAC, MOD, AND R COUNTER RELATIONSHIP

The 10–bit R counter allows the input reference frequency

(REF_IN) to be divided down to produce the reference clock

to the PFD. Division ratios from 1 to 1023 are allowed.

The INT, FRAC, and MOD values, in conjunction with the R

counter, make it possible to generate output frequencies that

are spaced by fractions of the PFD frequency. See the RF

Synthesizer—A Worked Example section for more informa-

tion. The RF VCO frequency (RF_OUT) equation is

PHASE FREQUENCY DETECTOR (PFD) AND

CHARGE PUMP

The phase frequency detector (PFD) takes inputs from the R

counter and N counter and produces an output proportional to

the phase and frequency difference between them. Figure 16 is

a simplified schematic of the phase frequency detector. The

PFD includes a programmable delay element that sets the width

of the antibacklash pulse, which can be either 6 ns (default, for

fractional-N applications) or 3 ns (for integer-N mode). This

pulse ensures there is no dead zone in the PFD transfer function,

and gives a consistent reference spur level.

RF_OUT= f_PFD× (INT + (FRAC/MOD))

where:

RF_OUTis the output frequency of external voltage controlled

(1)

oscillator (VCO).

INT is the preset divide ratio of the binary 16–bit counter

(23 to 65535 for 4/5 prescaler, 75 to 65535 for 8/9 prescaler).

MOD is the preset fractional modulus (2 to 4095).

FRAC is the numerator of the fractional division (0 to MOD − 1).

f_PFD= REF_IN× [(1 + D)/(R × (1 + T))]

(2)

UP

HIGH

D1

Q1

where:

U1

CLR1

REF_INis the reference input frequency.

D is the REF_INdoubler bit.

+IN

T is the REF_INdivide-by-2 bit (0 or 1).

R is the preset divide ratio of the binary 10-bit programmable

reference counter (1 to 1023).

CHARGE

PUMP

CP

U3

DELAY

DOWN

CLR2

D2 Q2

HIGH

U2

–IN

Figure 16. PFD Simplified Schematic

Rev. 0 | Page 11 of 28

ADF4150

MUXOUT AND LOCK DETECT

PROGRAM MODES

The output multiplexer on the ADF4150 allows the user

to access various internal points on the chip. The state of

MUXOUT is controlled by M3, M2, and M1 (for details, see

Figure 22). Figure 17 shows the MUXOUT section in block

diagram form.

Figure 20 through Figure 25 show how the program modes are

to be set up in the ADF4150.

A number of settings in the ADF4150 are double buffered.

These include the modulus value, phase value, R counter

value, reference doubler, reference divide-by-2, and current

setting. This means that two events have to occur before the

part uses a new value of any of the double-buffered settings.

First, the new value is latched into the device by writing to the

appropriate register. Second, a new write must be performed

on Register R0. For example, any time the modulus value is

updated, Register R0 must be written to, thus ensuring the

modulus value is loaded correctly. Divider select in Register 4

(R4) is also double buffered, but only if DB13 of Register 2 (R2)

is high.

R COUNTER INPUT

DV

DD

THREE-STATE-OUTPUT

DV

DD

DGND

R COUNTER OUTPUT

N COUNTER OUTPUT

ANALOG LOCK DETECT

MUX

CONTROL

MUXOUT

DIGITAL LOCK DETECT

RESERVED

OUTPUT STAGE

The RF_OUT+ and RF_OUT− pins of the ADF4150 are connected

to the collectors of an NPN differential pair driven by buffered

outputs of the VCO, as shown in Figure 18. To allow the user

to optimize the power dissipation vs. the output power require-

ments, the tail current of the differential pair is programmable

by Bit D2 and Bit D1 in Register 4 (R4). Four current levels may

be set. These levels give output power levels of −4 dBm, −1 dBm,

+2 dBm, and +5 dBm, respectively, using a 50 Ω resistor to

AV_DDand ac coupling into a 50 Ω load. Alternatively, both

outputs can be combined in a 1 + 1:1 transformer or a 180°

microstrip coupler (see the Output Matching section). If the

outputs are used individually, the optimum output stage

D

GND

Figure 17. MUXOUT Schematic

INPUT SHIFT REGISTERS

The ADF4150 digital section includes a 10-bit RF R counter,

a 16-bit RF N counter, a 12-bit FRAC counter, and a 12-bit

modulus counter. Data is clocked into the 32-bit shift register

on each rising edge of CLK. The data is clocked in MSB first.

Data is transferred from the shift register to one of six latches

on the rising edge of LE. The destination latch is determined

by the state of the three control bits (C3, C2, and C1) in the

shift register. These are the 3 LSBs, DB2, DB1, and DB0, as

shown in Figure 2. The truth table for these bits is shown in

Table 5. Figure 19 shows a summary of how the latches are

programmed.

consists of a shunt inductor to AV_DD

.

Another feature of the ADF4150 is that the supply current

to the RF output stage can be shut down until the part

achieves lock as measured by the digital lock detect circuitry.

This is enabled by the mute-till-lock detect (MTLD) bit in

Register 4 (R4).

Table 5. C3, C2, and C1 Truth Table

Control Bits

RF

+

RF

–

OUT

C3

0

C2

0

1

C1

0

1

0

1

Register

Register 0 (R0)

Register 1 (R1)

Register 2 (R2)

Register 3 (R3)

Register 4 (R4)

Register 5 (R5)

BUFFER/

DIVIDE-BY-1/

-2/-4/-8/-16

VCO

1

0

1

Figure 18. Output Stage

Rev. 0 | Page 12 of 28

ADF4150

REGISTER MAPS

REGISTER 0

CONTROL

BITS

16-BIT INTEGER VALUE (INT)

12-BIT FRACTIONAL VALUE (FRAC)

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

N16 N15 N14 N13 N12 N11 N10

N9

N8

N7

N6

N5

N4

N3

N2

N1

F12 F11

F10

F9

F8

F7

F6

F5

F4

F3

F2

F1 C3(0) C2(0) C1(0)

REGISTER 1

CONTROL

BITS

1

DBR¹

RESERVED

12-BIT PHASE VALUE (PHASE)

12-BIT MODULUS VALUE (MOD)

DBR

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

PR1 P12 P11 P10

P9

P8

P7

P6

P5

P4

P3

P2

P1

M12 M11 M10

M9

M8

M7 M6 M5 M4 M3 M2 M1 C3(0) C2(0) C1(1)

REGISTER 2

LOW

CHARGE

PUMP

CURRENT

SETTING

NOISE AND

LOW SPUR

MODES

DBR¹

CONTROL

BITS

DBR¹

MUXOUT

10-BIT R COUNTER

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

L2

L1

M3

M2

M1 RD2 RD1 R10

R9

R8

R7

R6

R5

R4

R3

R2

R1

D1

CP4 CP3 CP2 CP1 U6

U5

U4

U3

U2

U1 C3(0) C2(1) C1(0)

REGISTER 3

CLK

DIV

MODE

RESERVED

CONTROL

BITS

12-BIT CLOCK DIVIDER VALUE

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

F3

F2

0

F1

0

C2

C1

D12 D11 D10

D9

D8

D7

D6

D5

D4

D3

D2

D1 C3(0) C2(1) C1(1)

REGISTER 4

2

DBB

DIVIDER

SELECT

OUTPUT

POWER

RESERVED

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

D13 D12 D11 D10 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1

D9

D8

D7

D6

D5

D4

D3

D2

D1 C3(1) C2(0) C1(0)

REGISTER 5

LD PIN

MODE

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

D15 D14 C3(1) C2(0) C1(1)

0

1

0

1

2

DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.

DBB = DOUBLE BUFFERED BITS—BUFFERED BY THE WRITE TO REGISTER 0, IF AND ONLY IF DB13 OF REGISTER 2 IS HIGH.

Figure 19. Register Summary

Rev. 0 | Page 13 of 28

ADF4150

CONTROL

BITS

16-BIT INTEGER VALUE (INT)

12-BIT FRACTIONAL VALUE (FRAC)

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

N16

N15

N14

N13

N12

N11

N10

N9

N8

N7

N6

N5

N4

N3

N2

N1

F12

F11

F10

F9

F8

F7

F6

F5

F4

F3

F2

F1 C3(0) C2(0) C1(0)

F12

0

.

F11

0

.

.......... F2

F1

FRACTIONAL VALUE (FRAC)

N16

N15

...

N5

N4

N3

N2

N1

INTEGER VALUE (INT)

..........

.........

0

1

.

0

1

0

1

.

0

.

0

.

0

.

0

.

0

.

0

1

.

0

1

0

.

NOT ALLOWED

1

NOT ALLOWED

2

NOT ALLOWED

3

...

.

0

.

0

.

1

.

0

1

.

1

0

.

1

0

.

0

1

0

.

NOT ALLOWED

23

.

24

.

...

1

0

1

0

1

0

1

4092

4093

4094

4095

1

0

1

0

1

65533

65534

65535

INTmin = 75 with prescaler = 8/9

Figure 20. Register 0 (R0)

CONTROL

BITS

RESERVED

12-BIT PHASE VALUE (PHASE)

DBR

12-BIT MODULUS VALUE (MOD)

DBR

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

PR1

P12

P11

P10

P9

P8

P7

P6

P5

P4

P3

P2

P1

M12 M11 M10

M9

M8

M7 M6

M5

M4

M3

M2

M1 C3(0) C2(0) C1(1)

P1

0

PRESCALER

P12

P11

.......... P2

P1

0

1

0

1

.

PHASE VALUE (PHASE)

M12

M11

..........

M2

M1

INTERPOLATOR MODULUS (MOD)

4/5

8/9

0

.

0

.

..........

0

1

.

0

.

0

.

..........

1

.

0

1

.

2

1

3

1 (RECOMMENDED)

.

2

.

3

.

1

0

1

0

1

0

1

4092

4093

4094

4095

.

1

0

1

0

1

0

1

4092

4093

4094

4095

Figure 21. Register 1 (R1)

Rev. 0 | Page 14 of 28

ADF4150

CHARGE

PUMP

CURRENT

SETTING

LOW

NOISE AND

LOW SPUR

MODES

CONTROL

BITS

MUXOUT

10-BIT R COUNTER

DBR

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

L2

L1

M3

M2

M1 RD2 RD1 R10

R9

R8

R7

R6

R5

R4

R3

R2

R1

D1

CP4 CP3 CP2 CP1 U6

U5

U4

U3

U2

U1 C3(0) C2(1) C1(0)

REFERENCE

RD2

COUNTER

RESET

DOUBLE BUFFER

R4 DB22:DB20

U1

L1

0

L2

NOISE MODE

DOUBLER

D1

U6

0

LDF

0

1

DISABLED

ENABLED

0

1

0

1

LOW NOISE MODE

RESERVED

FRAC-N

INT-N

0

1

DISABLED

ENABLED

0

1

DISABLED

ENABLED

0

1

RESERVED

RD1 REFERENCE DIVIDE BY 2

CP

I

(mA)

1

LOW SPUR MODE

CP

U2

U5

LDP

THREE-STATE

0

1

DISABLED

ENABLED

CP4

CP3

CP2

CP1

4.7kΩ

0

1

10ns

6ns

0

1

DISABLED

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.31

0.63

0.94

1.25

1.56

1.88

2.19

2.50

2.81

3.13

3.44

3.75

4.06

4.38

4.69

5.00

ENABLED

R10

R9

..........

R2

R1

R DIVIDER (R)

U3

POWER-DOWN

U4

0

PD POLARITY

NEGATIVE

POSITIVE

0

.

0

.

..........

0

1

.

1

0

.

1

0

1

DISABLED

ENABLED

2

1

.

1

0

1

0

1

0

1

1020

1021

1022

1023

M3

M2

0

M1

0

OUTPUT

0

1

THREE-STATE OUTPUT

0

1

DV

DD

1

0

DGND

1

R DIVIDER OUTPUT

N DIVIDER OUTPUT

ANALOG LOCK DETECT

DIGITAL LOCK DETECT

RESERVED

0

1

0

1

Figure 22. Register 2 (R2)

Rev. 0 | Page 15 of 28

ADF4150

CLK

DIV

MODE

CONTROL

BITS

RESERVED

12-BIT CLOCK DIVIDER VALUE

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

F1

0

C2

C1

D12 D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1 C3(0) C2(1) C1(1)

F3

F2

0

D12

D11

.......... D2

D1

CLOCK DIVIDER VALUE

CYCLE SLIP

REDUCTION

F1

0

.

0

.

..........

0

1

.

0

1

0

1

.

0

1

DISABLED

ENABLED

1

2

3

.

C2

C1

0

CLOCK DIVIDER MODE

CLOCK DIVIDER OFF

FAST LOCK ENABLE

RESYNC ENABLE

RESERVED

.

0

1

0

1

0

1

0

1

4092

4093

4094

4095

1

0

1

CHARGE

CANCELLATION

F2

0

1

DISABLED

ENABLED

ANTIBACKLASH

PULSE WIDTH

F3

0

1

6ns (FRAC-N)

3ns (INT_N)

Figure 23. Register 3 (R3)

2

DBB

DIVIDER

SELECT

OUTPUT

POWER

RESERVED

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

D13 D12 D11 D10 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1

D9

D8

D7

D6

D5

D4

D3

D2

D1 C3(1) C2(0) C1(0)

FEEDBACK

SELECT

D13

D2

D1

0

OUTPUT POWER

0

1

–4

–1

+2

+5

0

1

DIVIDED

FUNDAMENTAL

1

0

MUTE TILL

LOCK DETECT

D12

D11

D10

RF DIVIDER SELECT

1

D8

0

1

0

1

0

1

0

1

0

÷1

÷2

÷4

÷8

÷16

MUTE DISABLED

D3

RF OUT

1

MUTE ENABLED

0

1

DISABLED

ENABLED

Figure 24. Register 4 (R4)

Rev. 0 | Page 16 of 28

ADF4150

LD PIN

MODE

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

D15

D14

0

C3(1) C2(0) C1(1)

D15

D14

LOCK DETECT PIN OPERATION

0

1

0

1

0

1

LOW

DIGITAL LOCK DETECT

LOW

HIGH

Figure 25. Register 5 (R5)

Rev. 0 | Page 17 of 28

ADF4150

12-Bit Phase Value (Phase)

REGISTER 0

These bits control what is loaded as the phase word. The word

must be less than the MOD value programmed in Register 1.

The word is used to program the RF output phase from 0° to

360° with a resolution of 360°/MOD. See the Phase Resync

section for more information. In most applications, the phase

relationship between the RF signal and the reference is not

important. In such applications, the PHASE value can be used

to optimize the fractional and subfractional spur levels. See the

Spur Consistency and Fractional Spur Optimization section for

more information.

Control Bits

With Bits[C3:C1] set to 0, 0, 0, Register 0 is programmed.

Figure 20 shows the input data format for programming this

register.

16-Bit Integer Value (INT)

These 16 bits set the INT value, which determines the integer

part of the feedback division factor. They are used in Equation 1

(see the INT, FRAC, MOD, and R Counter Relationship section).

All integer values from 23 to 65,535 are allowed for 4/5 prescaler.

For 8/9 prescaler, the minimum integer value is 75.

If neither the PHASE resync nor the spurious optimization

functions are being used, it is recommended that the PHASE

word be set to 1.

12-Bit Fractional Value(FRAC)

The 12 FRAC bits set the numerator of the fraction that is input

to the Σ-Δ modulator. This, along with INT, specifies the new

frequency channel that the synthesizer locks to, as shown in the

RF Synthesizer—A Worked Example section. FRAC values from

0 to MOD − 1 cover channels over a frequency range equal to

the PFD reference frequency.

12-Bit Modulus Value (MOD)

This programmable register sets the fractional modulus. This

is the ratio of the PFD frequency to the channel step resolution

on the RF output. See the RF Synthesizer—A Worked Example

section for more information.

REGISTER 1

Control Bits

REGISTER 2

Control Bits

With Bits[C3:C1] set to 0, 0, 1, Register 1 is programmed.

Figure 21 shows the input data format for programming

this register.

With Bits[C3:C1] set to 0, 1, 0, Register 2 is programmed.

Figure 22 shows the input data format for programming

this register.

Prescaler Value

Low Noise and Spur Modes

The dual modulus prescaler (P/P + 1), along with the INT,

FRAC, and MOD counters, determines the overall division

ratio from the VCO output to the PFD input.

The noise modes on the ADF4150 are controlled by DB30 and

DB29 in Register 2 (see Figure 22). The noise modes allow the

user to optimize a design either for improved spurious perfor-

mance or for improved phase noise performance.

Operating at CML levels, it takes the clock from the VCO

output and divides it down for the counters. It is based on a

synchronous 4/5 core. When set to 4/5, the maximum RF

frequency allowed is 3 GHz. Therefore, when operating the

ADF4150 above 3 GHz, this must be set to 8/9. The prescaler

limits the INT value, where:

When the lowest spur setting is chosen, dither is enabled. This

randomizes the fractional quantization noise so it resembles

white noise rather than spurious noise. As a result, the part is

optimized for improved spurious performance. This operation

would normally be used when the PLL closed-loop bandwidth

is wide, for fast-locking applications. (Wide loop bandwidth is

seen as a loop bandwidth greater than 1/10 of the RF_OUTchannel

step resolution (f_RES)). A wide loop filter does not attenuate the

spurs to the same level as a narrow loop bandwidth.

P = 4/5, N_MIN= 23

P = 8/9, N_MIN= 75

In the ADF4150, P1 in Register 1 sets the prescaler values.

For best noise performance, use the lowest noise setting option.

As well as disabling the dither, it also ensures that the charge

pump is operating in an optimum region for noise performance.

This setting is extremely useful where a narrow loop filter band-

width is available. The synthesizer ensures extremely low noise

and the filter attenuates the spurs. The typical performance

characteristics give the user an idea of the trade-off in a typical

W-CDMA setup for the different noise and spur settings.

Rev. 0 | Page 18 of 28

ADF4150

MUXOUT

Lock Detect Precision (LDP)

The on-chip multiplexer is controlled by Bits[DB28:DB26] (see

Figure 22).

When DB7 is set to 0, the fractional-N digital lock detect is

activated. In this case after setting DB7 to 0, 40 consecutive PFD

cycles of 10 ns must occur before digital lock detect is set. When

DB7 is programmed to 1, 40 consecutive reference cycles of 6 ns

must occur before digital lock detect goes high. Setting DB8 to 1

causes the activation of the integer-N digital lock detect. In this

case, after setting DB7 to 0, 5 consecutive cycles of 10 ns must

occur before digital lock detect is set. When DB7 is set to 1, five

consecutive cycles of 6 ns must occur.

Reference Doubler

Setting DB25 to 0 feeds the REF_INsignal directly to the 10-bit

R counter, disabling the doubler. Setting this bit to 1 multiplies

the REF_INfrequency by a factor of 2 before feeding into the

10-bit R counter. When the doubler is disabled, the REF_IN

falling edge is the active edge at the PFD input to the fractional

synthesizer. When the doubler is enabled, both the rising and

falling edges of REF_INbecome active edges at the PFD input.

Phase Detector Polarity

DB6 sets the phase detector polarity. When a passive loop filter,

or noninverting active loop filter is used, set this bit to 1. If an

active filter with an inverting characteristic is used, this bit

should be set to 0.

When the doubler is enabled and the lowest spur mode is

chosen, the in-band phase noise performance is sensitive to the

REF_INduty cycle. The phase noise degradation can be as much

as 5 dB for the REF_INduty cycles outside a 45% to 55% range.

The phase noise is insensitive to the REF_INduty cycle in the

lowest noise mode. The phase noise is insensitive to the REF_IN

duty cycle when the doubler is disabled.

Power-Down (PD)

DB5 provides the programmable power-down mode. Setting this

bit to 1 performs a power-down. Setting this bit to 0 returns the

synthesizer to normal operation. When in software power-down

mode, the part retains all information in its registers. Only if the

supply voltages are removed are the register contents lost.

The maximum allowable REF_INfrequency when the doubler is

enabled is 30 MHz.

RDIV2

Setting the DB24 bit to 1 inserts a divide-by-2 toggle flip-flop

between the R counter and PFD, which extends the maximum

REF_INinput rate. This function allows a 50% duty cycle signal

to appear at the PFD input, which is necessary for cycle slip

reduction.

When a power-down is activated, the following events occur:

•

The synthesizer counters are forced to their load state

conditions.

•

The charge pump is forced into three-state mode.

The digital lock detect circuitry is reset.

The RF_OUTbuffers are disabled.

The input register remains active and capable of loading

and latching data.

10-Bit R Counter

The 10-bit R counter allows the input reference frequency

(REF_IN) to be divided down to produce the reference clock to

the PFD. Division ratios from 1 to 1023 are allowed.

Charge Pump (CP) Three-State

Double Buffer

DB4 puts the charge pump into three-state mode when

programmed to 1. It should be set to 0 for normal operation.

DB13 enables or disables double buffering of Bits[DB22:DB20]

in Register 4. The Divider Select section explains how double

buffering works.

Counter Reset

DB3 is the R counter and N counter reset bit for the ADF4150.

When this bit is 1, the RF synthesizer N counter and R counter

are held in reset. For normal operation, this bit should be set to 0.

Current Setting

Bits[DB12:DB9] set the charge pump current setting. This

should be set to the charge pump current that the loop filter

is designed with (see Figure 22).

LDF

Setting DB8 to 1 enables integer-N digital lock detect, when

the FRAC part of the divider is zero; setting DB8 to 0 enables

fractional-N digital lock detect.

Rev. 0 | Page 19 of 28

ADF4150

REGISTER 3

REGISTER 4

Control Bits

With Bits[C3:C1] set to 0, 1, 1, Register 3 is programmed.

Figure 23 shows the input data format for programming

this register.

With Bits[C3: C1] set to 1, 0, 0, Register 4 is programmed.

Figure 24 shows the input data format for programming this

register.

Antibacklash Pulse Width

Feedback Select

Setting DB22 to 0 sets the PFD antibacklash pulse width to 6 ns.

This is the recommended mode for fractional-N use. By setting

this bit to 1, the 3 ns pulse width is used and results in a phase

noise and spur improvement in integer-N operation. For

fractional-N mode it is not recommended to use this smaller

setting.

DB23 selects the feedback from VCO output to the N-counter.

When this bit is set to 1, the signal is taken from the VCO directly.

When this bit is set to 0, it is taken from the output of the output

dividers. The dividers enable covering of the wide frequency band

(137.5 MHz to 4.4 GHz). When the divider is enabled and the

feedback signal is taken from the output, the RF output signals

of two separately configured PLLs are in phase. This is useful in

some applications where the positive interference of signals is

required to increase the power.

Charge Cancellation Mode Pulse Width

Setting DB21 to 1 enables charge pump charge cancellation.

This has the effect of reducing PFD spurs in integer-N mode.

In fractional-N mode, this bit should not be used and the

relevant result in a phase noise and spur improvement. For

fractional-N mode, it is not recommended to use this smaller

setting.

Divider Select

Bits[DB22:DB20] select the value of the output divider (see

Figure 24).

Mute-Till-Lock Detect

Cycle Slip Reduction (CSR) Enable

If DB10 is set to 1, the supply current to the RF output stage is shut

down until the part achieves lock as measured by the digital lock

detect circuitry.

Setting DB18 to 1 enables cycle slip reduction. This is a method

for improving lock times. Note that the signal at the phase fre-

quency detector (PFD) must have a 50% duty cycle for cycle slip

reduction to work. The charge pump current setting must also

be set to a minimum. See the Cycle Slip Reduction for Faster

Lock Times section for more information.

RF Output Enable

DB5 enables or disables primary RF output, depending on the

chosen value.

Output Power

Clock Divider Mode

DB4 and DB3 set the value of the primary RF output power

level (see Figure 24).

Bits[DB16:DB15] must be set to 1, 0 to activate PHASE resync

or 0, 1 to activate fast lock. Setting Bits[DB16:DB15] to 0, 0

disables the clock divider. See Figure 23.

REGISTER 5

Control Bits

12-Bit Clock Divider Value

With Bits[C3:C1] set to 1, 0, 1, Register 5 is programmed.

Figure 25 shows the input data form for programming this

register.

The 12-bit clock divider value sets the timeout counter for

activation of PHASE resync. See the Phase Resync section for

more information. It also sets the timeout counter for fast lock.

See the Fast Lock Timer and Register Sequences section for

more information.

Lock Detect PIN Operation

Bits[DB23:DB22] set the operation of the lock detect pin (see

Figure 25).

INITIALIZATION SEQUENCE

The following sequence of registers is the correct sequence for

initial power up of the ADF4150 after the correct application

of voltages to the supply pins:

•

Register 5

Register 4

Register 3

Register 2

Register 1

Register 0

Rev. 0 | Page 20 of 28

ADF4150

RF SYNTHESIZER—A WORKED EXAMPLE

MODULUS

The following is an example how to program the ADF4150

synthesizer:

The choice of modulus (MOD) depends on the reference signal

(REF_IN) available and the channel resolution (f_RES) required at

the RF output. For example, a GSM system with 13 MHz REF_IN

RF_OUT= [INT + (FRAC/MOD)] × [f_PFD]/RF Divider

(3)

sets the modulus to 65. This means the RF output resolution (f_RES

)

where:

is the 200 kHz (13 MHz/65) necessary for GSM. With dither off,

the fractional spur interval depends on the modulus values chosen

(see Table 6).

RF_OUTis the RF frequency output.

INT is the integer division factor.

FRAC is the fractionality.

MOD is the modulus.

REFERENCE DOUBLER AND REFERENCE DIVIDER

The reference doubler on-chip allows the input reference signal

to be doubled. This is useful for increasing the PFD comparison

frequency. Making the PFD frequency higher improves the

noise performance of the system. Doubling the PFD frequency

usually improves noise performance by 3 dB. It is important

to note that the PFD cannot operate above 32 MHz due to a

limitation in the speed of the Σ-Δ circuit of the N-divider.

RF Divider is the output divider that divides down the VCO

frequency.

f_PFD= REF_IN× [(1 + D)/(R × (1 + T))]

(4)

where:

REF_INis the reference frequency input.

D is the RF REF_INdoubler bit.

T is the reference divide-by-2 bit (0 or 1).

R is the RF reference division factor.

The reference divide-by-2 divides the reference signal by 2,

resulting in a 50% duty cycle PFD frequency. This is necessary

for the correct operation of the cycle slip reduction (CSR)

function. See the Cycle Slip Reduction for Faster Lock Times

section for more information.

For example, in a UMTS system, where 2112.6 MHz RF

frequency output (RF_OUT) is required, a 10 MHz reference

frequency input (REF_IN) is available, and a 200 kHz channel

resolution (f_RESOUT) is required, on the RF output. A 2.1 GHz

VCO would be suitable, but a 4.2 GHz VCO would also be

suitable. In the second case, the RF divider of 2 should be used

(VCO frequency = 4225.2 MHz, RF_OUT= VCO frequency/RF

divider = 4225.2 MHz/2 = 2112.6 MHz).

12-BIT PROGRAMMABLE MODULUS

Unlike most other fractional-N PLLs, the ADF4150 allows the

user to program the modulus over a 12-bit range. This means

the user can set up the part in many different configurations for

the application, when combined with the reference doubler and

the 10-bit R counter.

It is also important where the loop is closed. In this example, the

loop is closed as depicted in Figure 26 (from the out divider).

For example, consider an application that requires 1.75 GHz RF

and 200 kHz channel step resolution. The system has a 13 MHz

reference signal.

f_PFD

RF

OUT

PFD

VCO

÷2

One possible setup is feeding the 13 MHz directly to the PFD

and programming the modulus to divide by 65. This results in

the required 200 kHz resolution.

N

DIVIDER

Figure 26. Loop Closed Before Output Divider

Another possible setup is using the reference doubler to create

26 MHz from the 13 MHz input signal. The 26 MHz is then fed

into the PFD programming the modulus to divide by 130. This

also results in 200 kHz resolution and offers superior phase

noise performance over the previous setup.

A channel resolution (f_RESOUT) of 200 kHz is required at the

output of the RF divider. Therefore, channel resolution at

the output of the VCO (f_RES) is to be twice the f_RESOUT, that

is, 400 kHz.

MOD = REF_IN/f_RES

The programmable modulus is also very useful for multi-

standard applications. If a dual-mode phone requires PDC

and GSM 1800 standards, the programmable modulus is a

great benefit. PDC requires 25 kHz channel step resolution,

whereas GSM 1800 requires 200 kHz channel step resolution.

MOD = 10 MHz/400 kHz = 25

From Equation 4

f

_PFD= [10 MHz × (1 + 0)/1] = 10 MHz

2112.6 MHz = 10 MHz × (INT + FRAC/25)/2

where:

(5)

(6)

INT = 422

FRAC = 13

Rev. 0 | Page 21 of 28

ADF4150

A 13 MHz reference signal can be fed directly to the PFD, and

the modulus can be programmed to 520 when in PDC mode

(13 MHz/520 = 25 kHz).

If the phase error increases again to a point where another cycle

slip is likely, the ADF4150 turns on another charge pump cell.

This continues until the ADF4150 detects the VCO frequency

has gone past the desired frequency. The extra charge pump

cells are turned off one by one until all the extra charge pump

cells have been disabled and the frequency is settled with the

original loop filter bandwidth.

The modulus needs to be reprogrammed to 65 for GSM 1800

operation (13 MHz/65 = 200 kHz).

It is important that the PFD frequency remain constant (13 MHz).

This allows the user to design one loop filter for both setups

without running into stability issues. It is important to remem-

ber that the ratio of the RF frequency to the PFD frequency

principally affects the loop filter design, not the actual channel

spacing.

Up to seven extra charge pump cells can be turned on. In most

applications, it is enough to eliminate cycle slips altogether,

giving much faster lock times.

Setting Bit DB18 in Register 3 to 1 enables cycle slip reduction.

Note that the PFD requires a 45% to 55% duty

cycle for CSR to operate correctly.

CYCLE SLIP REDUCTION FOR FASTER LOCK TIMES

As outlined in the Low Noise and Spur Mode section, the

ADF4150 contains a number of features that allow optimization

for noise performance. However, in fast locking applications,

the loop bandwidth generally needs to be wide, and therefore,

the filter does not provide much attenuation of the spurs. If

the cycle slip reduction feature is enabled, the narrow loop

bandwidth is maintained for spur attenuation but faster lock

times are still possible.

SPURIOUS OPTIMIZATION AND FAST LOCK

Narrow loop bandwidths can filter unwanted spurious signals,

but these usually have a long lock time. A wider loop bandwidth

achieves faster lock times, but a wider loop bandwidth may lead

to increased spurious signals inside the loop bandwidth.

The fast lock feature can achieve the same fast lock time as the

wider bandwidth, but with the advantage of a narrow final loop

bandwidth to keep spurs low.

Cycle Slips

Cycle slips occur in integer-N/fractional-N synthesizers when

the loop bandwidth is narrow compared to the PFD frequency.

The phase error at the PFD inputs accumulates too fast for the

PLL to correct, and the charge pump temporarily pumps in the

wrong direction. This slows down the lock time dramatically.

The ADF4150 contains a cycle slip reduction feature that

extends the linear range of the PFD, allowing faster lock

times without modifications to the loop filter circuitry.

FAST LOCK TIMER AND REGISTER SEQUENCES

If the fast lock mode is used, a timer value is to be loaded into

the PLL to determine the duration of the wide bandwidth mode.

When Bits[DB16:DB15] in Register 3 are set to 0, 1 (fast

lock enable), the timer value is loaded by the 12-bit clock

divider value. The following sequence must be programmed

to use fast lock:

1. Initialization sequence (see the Initialization Sequence

section); occurs only once after powering up the part.

2. Load Register 3 by setting Bits[DB16:DB15] to 0, 1 and

the chosen fast lock timer value [DB14:DB3]. Note that

the duration the PLL remains in wide bandwidth is equal

When the circuitry detects that a cycle slip is about to occur,

it turns on an extra charge pump current cell. This outputs a

constant current to the loop filter, or removes a constant

current from the loop filter (depending on whether the VCO

tuning voltage needs to increase or decrease to acquire the

new frequency). The effect is that the linear range of the PFD

is increased. Loop stability is maintained because the current

is constant and is not a pulsed current.

to the fast lock timer/f_PFD

.

Rev. 0 | Page 22 of 28

ADF4150

FAST LOCK—AN EXAMPLE

SPUR MECHANISMS

If a PLL has a reference frequency of 13 MHz, f_PFDof 13 MHz

and a required lock time of 50 µs, the PLL is set to wide bandwidth

for 40 µs. This example assumes a modulus of 65 for channel

spacing of 200 kHz.

This section describes the three different spur mechanisms that

arise with a fractional-N synthesizer and how to minimize them

in the ADF4150.

Fractional Spurs

If the time period set for the wide bandwidth is 40 µs, then

Fast Lock Timer Value = Time In Wide Bandwidth × f_PFD/MOD

Fast Lock Timer Value = 40 µs × 13 MHz/65 = 8

The fractional interpolator in the ADF4150 is a third-order Σ-Δ

modulator (SDM) with a modulus (MOD) that is programmable

to any integer value from 2 to 4095. In low spur mode (dither

enabled), the minimum allowable value of MOD is 50. The

SDM is clocked at the PFD reference rate (f_PFD) that allows PLL

output frequencies to be synthesized at a channel step resolution

of f_PFD/MOD.

Therefore, 8 must be loaded into the clock divider value in

Register 3 in Step 1 of the sequence described in the Fast Lock

Timer and Register Sequences section.

FAST LOCK—LOOP FILTER TOPOLOGY

In low noise mode (dither off), the quantization noise from the

Σ-Δ modulator appears as fractional spurs. The interval between

spurs is f_PFD/L, where L is the repeat length of the code sequence

in the digital Σ-Δ modulator. For the third-order modulator

used in the ADF4150, the repeat length depends on the value

of MOD, as listed in Table 6.

To use fast lock mode, the damping resistor in the loop filter

is reduced to ¼ of its value while in wide bandwidth mode. To

achieve the wider loop filter bandwidth, the charge pump

current increases by a factor of 16. To maintain loop stability,

the damping resistor must be reduced a factor of ¼. To enable

fast lock, the SW pin is shorted to the GND pin by settings

Bits[DB16:DB15] in Register 3 to 0, 1. The following two

topologies are available:

Table 6. Fractional Spurs with Dither Off

Repeat

Length

Condition (Dither Off)

Spur Interval

Channel step/2

Channel step/3

Channel step/6

Channel step

•

The damping resistor (R1) is divided into two values (R1

and R1A) that have a ratio of 1:3 (see Figure 27).

An extra resistor (R1A) is connected directly from SW,

as shown in Figure 28. The extra resistor is calculated

such that the parallel combination of an extra resistor

and the damping resistor (R1) is reduced to ¼ of the

original value of R1 (see Figure 28).

If MOD is divisible by 2 but not 3 2 × MOD

If MOD is divisible by 3 but not 2 3 × MOD

•

If MOD is divisible by 6

Otherwise

6 × MOD

MOD

In low spur mode (dither on), the repeat length is extended to

2²¹cycles, regardless of the value of MOD, which makes the

quantization error spectrum look like broadband noise. This

may degrade the in-band phase noise at the PLL output by as

much as 10 dB. For lowest noise, dither off is a better choice,

particularly when the final loop bandwidth is low enough to

attenuate even the lowest frequency fractional spur.

ADF4150

R2

CP

VCO

C1

C2

R1

C3

SW

Integer Boundary Spurs

R1A

Another mechanism for fractional spur creation is the inte-

ractions between the RF VCO frequency and the reference

frequency. When these frequencies are not integer related (the

point of a fractional-N synthesizer) spur sidebands appear on

the VCO output spectrum at an offset frequency that corres-

ponds to the beat note or difference frequency between an

integer multiple of the reference and the VCO frequency. These

spurs are attenuated by the loop filter and are more noticeable

on channels close to integer multiples of the reference where

the difference frequency can be inside the loop bandwidth,

therefore the name integer boundary spurs.

Figure 27. Fast Lock Loop Filter Topology—Topology 1

ADF4150

R2

CP

VCO

C1

C2

R1

C3

R1A

SW

Figure 28. Fast Lock Loop Filter Topology—Topology 2

Rev. 0 | Page 23 of 28

ADF4150

Reference Spurs

Phase resync is enabled by setting Bit DB16, Bit DB15 in

Register 3 to 1, 0. When PHASE resync is enabled, an internal

timer generates sync signals at intervals of t_SYNCgiven by the

following formula:

Reference spurs are generally not a problem in fractional-N

synthesizers because the reference offset is far outside the loop

bandwidth. However, any reference feedthrough mechanism

that bypasses the loop can cause a problem. Feedthrough of low

levels of on-chip reference switching noise, through the RF_IN

pin back to the VCO, can result in reference spur levels as high

as −90 dBc. PCB layout needs to ensure adequate isolation

between VCO traces and the input reference to avoid a possible

feedthrough path on the board.

t

_SYNC= CLK_DIV_VALUE × MOD × t_PFD

where:

_PFDis the PFD reference period.

t

CLK_DIV_VALUE is the decimal value programmed in

Bits[DB14:DB3] of Register 3 and can be any integer in the

range of 1 to 4095.

MOD is the modulus value programmed in Bits[DB14:DB3] of

Register 1 (R1).

SPUR CONSISTENCY AND FRACTIONAL SPUR

OPTIMIZATION

With dither off, the fractional spur pattern due to the quanti-

zation noise of the SDM also depends on the particular phase

word with which the modulator is seeded.

When a new frequency is programmed, the second sync pulse

after the LE rising edge is used to resynchronize the output

phase to the reference. The t_SYNCtime is to be programmed to

a value that is at least as long as the worst-case lock time. This

guarantees that the PHASE resync occurs after the last cycle slip

in the PLL settling transient.

The phase word can be varied to optimize the fractional and

subfractional spur levels on any particular frequency. Thus, a

look-up table of phase values corresponding to each frequency

can be constructed for use when programming the ADF4150.

In the example shown in Figure 29, the PFD reference is 25 MHz

and MOD is 125 for a 200 kHz channel spacing. t_SYNCis set to

400 µs by programming CLK_DIV_VALUE to 80.

If a look-up table is not used, keep the phase word at a constant

value to ensure consistent spur levels on any particular frequency.

PHASE RESYNC

LE

t_SYNC

The output of a fractional-N PLL can settle to any one of the

MOD phase offsets with respect to the input reference, where

MOD is the fractional modulus. The phase resync feature in the

ADF4150 produces a consistent output phase offset with respect

to the input reference. This is necessary in applications where the

output phase and frequency are important, such as digital beam

forming. See the Phase Programmability section for how to

program a specific RF output phase when using phase resync.

SYNC

(INTERNAL)

LAST CYCLE SLIP

FREQUENCY

PLL SETTLES TO

INCORRECT PHASE

PLL SETTLES TO

CORRECT PHASE

AFTER RESYNC

PHASE

–100

0

100 200 300 400 500 600 700 800 900 1000

TIME (µs)

Figure 29. Phase Resync Example

Phase Programmability

The phase word in Register 1 controls the RF output phase. As

this word is swept from 0 to MOD, the RF output phase sweeps

over a 360° range in steps of 360°/MOD.

Rev. 0 | Page 24 of 28

ADF4150

APPLICATIONS INFORMATION

The LO ports of the ADL5375 can be driven differentially from

the RF_OUT+ and RF_OUT− outputs of the ADF4150. This gives

better performance than a single-ended LO driver and

eliminates the use of a balun to convert from a single-ended LO

input to the more desirable differential LO inputs for the

ADL5375. The typical rms phase noise (100 Hz to 5 MHz) of

the LO in this configuration is 0.61°rms.

DIRECT CONVERSION MODULATOR

Direct conversion architectures are increasingly being used to

implement base station transmitters. Figure 30 shows how Analog

Devices, Inc., parts can be used to implement such a system.

The circuit block diagram shows the AD9788 TxDAC® being

used with the ADL5375. The use of dual integrated DACs, such

as the AD9788 with its specified 0.02 dB and 0.004 dB gain

and offset matching characteristics, ensures minimum error

contribution (over temperature) from this portion of the

signal chain.

The ADL5375 accepts LO drive levels from −10 dBm to 0 dBm.

The optimum LO power can be software programmed on the

ADF4150, which allows levels from −4 dBm to +5 dBm from

each output.

The local oscillator (LO) is implemented using the ADF4150.

The low-pass filter was designed using ADIsimPLL™ for a channel

spacing of 200 kHz and a closed-loop bandwidth of 35 kHz.

The RF output is designed to drive a 50 Ω load but must be

ac-coupled, as shown in Figure 30. If the I and Q inputs are

driven in quadrature by 2 V p-p signals, the resulting output

power from the modulator is approximately 2 dBm.

51Ω

REFIO

IOUTA

IOUTB

LOW-PASS

FILTER

MODULATED

DIGITAL

DATA

AD9788

TxDAC

QOUTA

QOUTB

LOW-PASS

FILTER

FSADJ

51Ω

2kΩ

ADL5375

IBBP

LOCK

DETECT

V

DD

V

VCO

IBBN

21

MUXOUT

4

20

9

18

DV

16

AV

17

6

22

3.9nH

AV

CE PDB

SDV

LD

VP

DD

RF

DD

1nF

1nF 1nF

LOIP

LOIN

RF

+

–

15

14

OUT

QUADRATURE

PHASE

SPLITTER

FREF

REF

19

51Ω

IN

RFOUT

DSOP

RF

OUT

CLK

1

2

3

1nF

V

VCO

DATA

LE

V

VCO

QBBP

QBBN

100pF

CC

VCO

10

11

RF

+

–

OUT

IN

ADF4150

V

TUNE

24

R

RF

SET

IN

4.7kΩ

680Ω

CP

7

5

39nF

2700pF

1200pF

SW

360Ω

CP

A

SD

GND

13

8

12

23

Figure 30. Direct Conversion Modulator

Rev. 0 | Page 25 of 28

ADF4150

ADSP-21xx Interface

INTERFACING

Figure 32 shows the interface between the ADF4150 and a

ADSP-21xx digital signal processor. The ADF4150 needs a

32-bit serial word for each latch write. The easiest way to

accomplish this using the ADSP-21xx family is to use the

autobuffered transmit mode of operation with alternate

framing. This provides a means for transmitting an entire

block of serial data before an interrupt is generated.

The ADF4150 has a simple SPI-compatible serial interface

for writing to the device. CLK, DATA, and LE control the data

transfer. When LE goes high, the 32 bits that have been clocked

into the appropriate register on each rising edge of CLK are

transferred to the appropriate latch. See Figure 2 for the timing

diagram and Table 5 for the register address table.

ADuC812 Interface

Figure 31 shows the interface between the ADF4150 and the

ADuC812 MicroConverter®. Because the ADuC812 is based

on an 8051 core, this interface can be used with any 8051-based

microcontroller. The MicroConverter is set up for SPI master

mode with CPHA = 0. To initiate the operation, the I/O port

driving LE is brought low. Each latch of the ADF4150 needs a

32-bit word, which is accomplished by writing four 8-bit bytes

from the MicroConverter to the device. When the fourth byte

has been written, the LE input should be brought high to

complete the transfer.

SCLK

CLK

MOSI

TFS

SDATA

LE

ADF4150

ADSP-21xx

I/O PORTS

CE

MUXOUT

(LOCK DETECT)

Figure 32. ADSP-21xx to ADF4150 Interface

Set up the word length for 8 bits and use four memory locations

for each 32-bit word. To program each 32-bit latch, store the 8-bit

bytes, enable the autobuffered mode, and write to the transmit

register of the DSP. This last operation initiates the autobuffer

transfer.

SCLOCK

MOSI

CLK

SDATA

ADuC812

I/O PORTS

LE

ADF4150

CE

PCB DESIGN GUIDELINES FOR CHIP SCALE

PACKAGE

MUXOUT

(LOCK DETECT)

The lands on the chip scale package (CP-24-7) are rectangular.

The PCB pad for these is to be 0.1 mm longer than the package

land length and 0.05 mm wider than the package land width.

The land is to be centered on the pad. This ensures the solder

joint size is maximized. The bottom of the chip scale package

has a central thermal pad.

Figure 31. ADuC812 to ADF4150 Interface

I/O port lines on the ADuC812 are also used to control power-

down (CE input) and detect lock (MUXOUT configured as

lock detect and polled by the port input). When operating in

the described mode, the maximum SCLOCK rate of the

ADuC812 is 4 MHz. This means that the maximum rate at

which the output frequency can be changed is 125 kHz.

The thermal pad on the PCB is to be at least as large as the

exposed pad. On the PCB, there is to be a minimum clearance

of 0.25 mm between the thermal pad and the inner edges of the

pad pattern. This ensures that shorting is avoided.

Thermal vias can be used on the PCB thermal pad to improve

the thermal performance of the package. If vias are used, they

are to be incorporated in the thermal pad at 1.2 mm pitch grid.

The via diameter is to be between 0.3 mm and 0.33 mm, and the

via barrel is to be plated with one ounce copper to plug the via.

Rev. 0 | Page 26 of 28

ADF4150

Experiments indicate that the circuit shown in Figure 34

OUTPUT MATCHING

provides an excellent match to 50 Ω for the W-CDMA UMTS

Band 1 (2110 MHz to 2170 MHz). The maximum output power

in that case is about 7 dBm. Both single-ended architectures can

be examined using the EVAL-ADF4150EB1Z evaluation board.

There are a number of ways to match the output of the ADF4150

for optimum operation; the most basic is to use a 50 Ω resistor to

AV_DD. A dc bypass capacitor of 100 pF is connected in series as

shown in Figure 33. Because the resistor is not frequency

dependent, this provides a good broadband match. The output

power in this circuit into a 50 Ω load typically gives values

chosen by Bits[DB4:DB3] in Register 4 (R4).

AV

DD

3.9nH

1nF

RF

OUT

AV

DD

50Ω

100pF

Figure 34. Optimum ADF4150 Output Stage

RF

OUT

If differential outputs are not needed, the unused output can be

terminated or combined with both outputs using a balun.

50Ω

Figure 33. Simple ADF4150 Output Stage

A better solution is to use a shunt inductor (acting as an RF

choke) to AV_DD. This gives a better match and, therefore, more

output power.

Rev. 0 | Page 27 of 28

ADF4150

OUTLINE DIMENSIONS

4.10

4.00 SQ

3.90

0.30

0.25

0.18

PIN 1

INDICATOR

PIN 1

INDICATOR

19

18

24

0.50

BSC

1

2.65

2.50 SQ

2.45

EXPOSED

PAD

13

12

BOTTOM VIEW

6

7

0.50

0.40

0.30

0.25 MIN

TOP VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

SEATING

PLANE

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.

Figure 35. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

4 mm ×4 mm Body, Very Very Thin Quad

(CP-24-7)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

−40°C to +85°C

Package Description

Package Option

CP-24-7

ADF4150BCPZ

ADF4150BCPZ-RL7

EVAL-ADF4150EB1Z

24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

Evaluation Board

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D08226-0-7/11(0)

Rev. 0 | Page 28 of 28


型号：	EVAL-ADF4150EB1Z
厂家：	ADI
描述：	Fractional-N/Integer-N PLL Synthesizer 小数N /整数N分频PLL合成器
文件：	总28页 (文件大小：486K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EVAL-ADF4150EB1Z [ADI]

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