EVAL-ADF4154EB1 [ADI]
Fractional-N Frequency Synthesizer; 小数N分频合成器
| 型号： | EVAL-ADF4154EB1 |
| 厂家： | 
ADI |
| 描述： | Fractional-N Frequency Synthesizer |
| 文件： | 总20页 (文件大小：550K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Fractional-N Frequency Synthesizer
ADF4154
FEATURES
GENERAL DESCRIPTION
RF bandwidth 500 MHz to 4 GHz
2.7 V to 3.3 V power supply
Separate VP allows extended tuning voltage
Programmable dual-modulus prescaler 4/5, 8/9
Programmable charge pump currents
3-wire serial interface
The ADF4154 is a fractional-N frequency synthesizer that
implements local oscillators in the up conversion and down
conversion sections of wireless receivers and transmitters. It
consists of a low noise digital phase frequency detector (PFD),
a precision charge pump, and a programmable reference divider.
There is a Σ-Δ based fractional interpolator to allow program-
mable fractional-N division. The INT, FRAC, and MOD regis-
ters define an overall N divider (N = (INT + (FRAC/MOD))).
In addition, the 4-bit reference counter (R counter) allows
selectable REFIN frequencies at the PFD input. A complete
phase-locked loop (PLL) can be implemented if the synthesizer
is used with an external loop filter and a voltage controlled
oscillator (VCO).
Digital lock detect
Power-down mode
Pin compatible with the ADF4110/ADF4111/
ADF4112/ADF4113, ADF4106 and ADF4153
Programmable modulus on fractional-N synthesizer
Trade-off noise versus spurious performance
Fast-lock mode with built-in timer
APPLICATIONS
CATV equipment
Base stations for mobile radio (GSM, PCS, DCS,
CDMA, WCDMA)
Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANs
A key feature of the ADF4154 is the fast-lock mode with a built-
in timer. The user can program a predetermined count-down
time value so that the PLL will remain in wide bandwidth mode,
instead of having to control this time externally.
Control of all on-chip registers is via a simple 3-wire interface.
The device operates with a power supply ranging from 2.7 V to
3.3 V, and can be powered down when not in use.
Communications test equipment
FUNCTIONAL BLOCK DIAGRAM
AV
DD
DV
DD
V
SDV
R
SET
P
DD
REFERENCE
4-BIT
R COUNTER
+
PHASE
×2
REF
IN
CHARGE
PUMP
FREQUENCY
DETECTOR
DOUBLER
CP
–
V
DD
HIGH Z
DGND
LOCK
DETECT
CURRENT
SETTING
OUTPUT
MUX
MUXOUT
FAST-LOCK
SWITCH
V
RFCP3 RFCP2 RFCP1
DD
R
N
DIV
DIV
RF
RF
A
B
IN
N COUNTER
IN
THIRD ORDER
FRACTIONAL
INTERPOLATOR
FRACTION
REG
MODULUS
REG
INTEGER REG
P = 4/5 OR 8/9
B = 9 BITS; A = 3 BITS
CLOCK
DATA
LE
24-BIT
DATA
REGISTER
ADF4154
AGND
DGND
CPGND
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
ADF4154
TABLE OF CONTENTS
Specifications..................................................................................... 3
R-Divider Register, R1 ............................................................... 15
Control Register, R2 ................................................................... 15
Noise and Spur Register, R3...................................................... 16
Reserved Bits............................................................................... 16
RF Synthesizer: A Worked Example ........................................ 16
Modulus....................................................................................... 17
Reference Doubler and Reference Divider ............................. 17
12-Bit Programmable Modulus................................................ 17
Spurious Optimization and Fast-lock...................................... 17
Fast-Lock Timer and Register Sequences ............................... 17
Fast-Lock: A Worked Example ................................................. 18
Fast-Lock: Loop Filter Topology .............................................. 18
Spurious Signals.......................................................................... 18
Filter Design—ADIsimPLL....................................................... 18
Interfacing ................................................................................... 18
PCB Design Guidelines for Chip Scale Package .................... 19
Outline Dimensions....................................................................... 20
Ordering Guide .......................................................................... 20
Timing Characteristics..................................................................... 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Pin Function Descriptions...................... 6
Typical Performance Characteristics ............................................. 7
Circuit Description........................................................................... 9
Reference Input Section............................................................... 9
RF Input Stage............................................................................... 9
RF INT Divider............................................................................. 9
INT, FRAC, MOD, and R Relationship...................................... 9
RF R Counter ................................................................................ 9
Phase Frequency Detector (PFD) and Charge Pump.............. 9
MUXOUT and Lock Detect...................................................... 10
Input Shift Registers................................................................... 10
Program Modes .......................................................................... 10
Registers........................................................................................... 11
Register Definition..................................................................... 15
Rev. 0 | Page 2 of 20
ADF4154
SPECIFICATIONS
Table 1. AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise
noted; dBm referred to 50 Ω. The operating temperature for the B version is −40°C to +80°C.
Parameter
B Version
Unit
Test Conditions/Comments
RF CHARACTERISTICS (3 V)
RF Input Frequency (RFIN)1
See Figure 18 for input circuit.
−8 dBm/0 dBm min/max. For lower frequencies, ensure slew rate > 396 V/µs.
−10 dBm/0 dBm min/max.
0.5/4.0
1.0/4.0
GHz min/max
GHz min/max
REFERENCE CHARACTERISTICS
REFIN Input Frequency1
See Figure 17 for input circuit.
For f < 10 MHz, use a dc-coupled, CMOS compatible square wave, slew rate >
21 V/µs.
10/250
MHz min/max
REFIN Input Sensitivity
0.7/AVDD
V p-p
min/max
AC-coupled.
0 to AVDD
10
100
V max
pF max
µA max
CMOS compatible.
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency2
CHARGE PUMP
32
MHz max
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
RSET Range
ICP Three-State Leakage Current
Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
Programmable. See Table 5.
With RSET = 5.1 kΩ.
5
mA typ
µA typ
% typ
kΩ min/max
nA typ
% typ
312.5
2.5
1.5/10
1
2
2
2
With RSET = 5.1 kΩ.
Sink and source current.
0.5 V < VCP < VP – 0.5.
0.5 V < VCP < VP – 0.5.
VCP = VP/2.
% typ
% typ
VINH, Input High Voltage
VINL, Input Low Voltage
IINH/IINL, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage
POWER SUPPLIES
AVDD
1.4
0.6
1
V min
V max
µA max
pF max
10
1.4
0.4
V min
V max
Open-drain 1 kΩ pull-up to 1.8 V.
IOL = 500 µA.
2.7/3.3
AVDD
AVDD/5.5
24
V min/V max
DVDD, SDVDD
VP
IDD
V min/V max
mA max
3
20 mA typical.
Low Power Sleep Mode
NOISE CHARACTERISTICS
Phase Noise Figure of Merit4
ADF4154 Phase Noise Floor5
1
µA typ
−213
−143
−139
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
@ 10 MHz PFD frequency.
@ 26 MHz PFD frequency.
@ VCO output.
Phase Noise Performance6
1750 MHz Output7
−102
dBc/Hz typ
@ 1 kHz offset, 26 MHz PFD frequency.
1 Use a square wave for frequencies below fMIN
.
2 Guaranteed by design. Sample tested to ensure compliance.
3 AC coupling ensures AVDD/2 bias. See Figure 17 for typical circuit.
4 This figure can be used to calculate phase noise for any application. Use the formula –213 + 10log(fPFD) + 20logN to calculate in-band phase noise performance, as seen
at the VCO output. The value given is the lowest noise mode.
5 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N-divider value).
The value given is the lowest noise mode.
6 The phase noise is measured with the EVAL-ADF4154EB1 evaluation board and the HP8562E spectrum analyzer.
7 fREFIN = 26 MHz; fPFD = 26 MHz; offset frequency = 1 kHz; RFOUT = 1750 MHz; loop B/W = 20 kHz; lowest noise mode.
Rev. 0 | Page 3 of 20
ADF4154
TIMING CHARACTERISTICS
Table 2. AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise
noted; dBm referred to 50 Ω.
Parameter1
Limit at TMIN to TMAX (B Version)
Unit
Test Conditions/Comments
t1
t2
t3
t4
t5
t6
t7
20
10
10
25
25
10
20
ns min
ns min
ns min
ns min
ns min
ns min
ns min
LE Setup Time
DATA to CLOCK Setup Time
DATA to CLOCK Hold Time
CLOCK High Duration
CLOCK Low Duration
CLOCK to LE Setup Time
LE Pulse Width
1 Guaranteed by design, but not production tested.
t4
t5
CLOCK
t2
t3
DB1
DB0 (LSB)
(CONTROL BIT C1)
DB23 (MSB)
DB22
DB2
DATA
LE
(CONTROL BIT C2)
t7
t1
t6
LE
Figure 2. Timing Diagram
Rev. 0 | Page 4 of 20
ADF4154
ABSOLUTE MAXIMUM RATINGS
Table 3. Absolute Maximum Ratings.1, 2, 3 TA = 25°C, unless
otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to GND
−0.3 V to +4 V
VDD to VDD
VP to GND
VP to VDD
Digital I/O Voltage to GND
Analog I/O Voltage to GND
REFIN, RFIN to GND
−0.3 V to +0.3 V
−0.3 V to +5.8 V
−0.3 V to +5.8 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
1 This device is a high performance RF integrated circuit with an ESD rating of
< 2 kV, and it is ESD sensitive. Proper precautions should be taken for
handling and assembly.
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Maximum Junction Temperature
TSSOP θJA Thermal Impedance
2 GND = AGND = DGND = 0 V.
−40°C to +85°C
−65°C to +150°C
150°C
150.4°C/W
122°C/W
3 VDD = AVDD = DVDD = SDVDD
.
LFCSP θJA Thermal Impedance
(Paddle Soldered)
LFCSP θJA Thermal Impedance
(Paddle Not Soldered)
216°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared
215°C
220°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 5 of 20
ADF4154
PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS
R
1
2
3
4
5
6
7
8
16
V
P
SET
CP
15 DV
DD
CPGND
AGND
14 MUXOUT
13 LE
ADF4154
15 MUXOUT
14 LE
13 DATA
CPGND
AGND
AGND
1
2
3
4
5
PIN 1
INDICATOR
TOP VIEW
RF
RF
B
A
12 DATA
11 CLK
IN
(Not to Scale)
ADF4154
12 CLK
TOP VIEW
RF
RF
B
A
IN
IN
IN
11 SDV
DD
AV
10 SDV
DD
DD
REF
9
DGND
IN
Figure 3. TSSOP Pin Configuration
Figure 4. LFCSP Pin Configuration
Table 4. Pin Function Descriptions
TSSOP
LFCSP
Mnemonic Description
1
19
RSET
Connecting a resistor between this pin and ground sets the maximum charge pump output current.
The relationship between ICP and RSET is
25.5
RSET
ICP max
=
where RSET = 5.1 kΩ and ICPmax = 5 mA.
2
20
CP
Charge Pump Output. When enabled, this provides ICP to the external loop filter, which in turn drives
the external VCO.
3
4
5
1
2, 3
4
CPGND
AGND
RFINB
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler.
Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a
small bypass capacitor, typically 100 pF (see Figure 18).
6
7
5
6, 7
RFINA
AVDD
Input to the RF Prescaler. This small-signal input is normally ac-coupled from the VCO.
Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane should be
placed as close as possible to this pin. AVDD has a value of 3 V 10%. AVDD must have the same voltage
as DVDD
.
8
8
REFIN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input
resistance of 100 kΩ (see Figure 17). This input can be driven from a TTL or CMOS crystal oscillator, or it
can be ac-coupled.
9
10
9, 10
11
DGND
SDVDD
Digital Ground.
Σ-∆ Power. Decoupling capacitors to the digital ground plane should be placed as close as possible to
this pin. SDVDD has a value of 3 V 10%. SDVDD must have the same voltage as DVDD
.
11
12
13
14
15
12
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This input is a
high impedance CMOS input.
Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one of
the four latches, the latch being selected using the control bits.
This multiplexer output allows either the RF lock detect, the scaled RF, or the scaled reference
frequency to be accessed externally.
13
DATA
LE
14
15
MUXOUT
DVDD
16, 17
Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane should
be placed as close as possible to this pin. DVDD has a value of 3 V 10%. DVDD must have the same
voltage as AVDD
.
16
18
VP
Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, it
can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.
Rev. 0 | Page 6 of 20
ADF4154
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 5 to Figure 10, and Figure 12: RFOUT = 1.722 GHz, PFD Frequency = 26 MHz, INT = 66, Channel Spacing = 200 kHz,
Modulus = 130, Fraction = 30/130, and ICP = 5 mA.
Loop Bandwidth = 20 kHz, Reference = 26 MHz, VCO = Vari-L VCO190-1750T, Evaluation Board = EVAL-ADF4154EB1. Measurements
were taken on the HP8562E spectrum analyzer.
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
V
= 3V, V = 5V
P
DD
= 5mA
V
I
= 3V, V = 5V
P
DD
= 5mA
CP
I
CP
REFERENCE
LEVEL = –4.2dBm
REFERENCE
LEVEL = –4dBm
PFD FREQUENCY = 26MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
LOWEST NOISE MODE
N = 66 30/130
PFD FREQUENCY = 26MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
LOWEST NOISE MODE
N = 66 30/130
RBW = 10Hz
RBW = 10Hz
–71dBc@200kHz
–102dBc/Hz
–400kHz
–200kHz
1.722GHz
200kHz
400kHz
–2kHz
–1kHz
1.722GHz
1kHz
2kHz
Figure 5. Phase Noise (Lowest Noise Mode)
Figure 8. Spurs (Lowest Noise Mode)
0
–10
–20
–30
–40
–50
–60
–70
–80
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
V
= 3V, V = 5V
P
DD
= 5mA
V
I
= 3V, V = 5V
P
DD
= 5mA
I
CP
REFERENCE
LEVEL = –4.2dBm
REFERENCE
LEVEL = –4.2dBm
CP
PFD FREQUENCY = 26MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
LOW NOISE AND
PFD FREQUENCY = 26MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
LOW NOISE AND
SPUR MODE
SPUR MODE
N = 66 30/130
RBW = 10Hz
N = 66 30/130
RBW = 10Hz
–74dBc@200kHz
–95dBc/Hz
–90
–100
–2kHz
–1kHz
1.722GHz
1kHz
2kHz
–400kHz
–200kHz
1.722GHz
200kHz
400kHz
Figure 6. Phase Noise (Low Noise Mode and Spur Mode)
Figure 9. Spurs (Low Noise and Spur Mode)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
V
= 3V, V = 5V
P
DD
I = 5mA
CP
V
I
= 3V, V = 5V
P
DD
= 5mA
REFERENCE
LEVEL = –4.2dBm
REFERENCE
LEVEL = –4.2dBm
CP
PFD FREQUENCY = 26MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
LOWEST SPUR NOISE
N = 66 30/130
PFD FREQUENCY = 26MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
LOWEST SPUR MODE
N = 66 30/130
RBW = 10Hz
RBW = 10Hz
–90dBc/Hz
–2kHz
–1kHz
1.722GHz
1kHz
2kHz
–400kHz
–200kHz
1.722GHz
200kHz
400kHz
Figure 7. Phase Noise (Lowest Spur Mode)
Figure 10. Spurs (Lowest Spur Mode)
Rev. 0 | Page 7 of 20
ADF4154
–130
–80
–85
–140
–150
–160
–90
–95
–100
–105
–110
–170
100
0
5
10
15
20
25
30
35
1000
10000
100000
R
VALUE (kΩ)
SET
PHASE DETECTOR FREQUENCY (kHz)
Figure 11. PFD Noise Floor vs. PFD Frequency (Lowest Noise Mode)
Figure 14. Phase Noise vs. RSET
5
–90
–92
–94
–96
0
–5
–10
–15
–20
–25
–30
–35
P = 4/5
–98
–100
P = 8/9
–102
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
–104
–60
–40
–20
0
20
40
60
80
100
FREQUENCY (GHz)
TEMPERATURE(°C)
Figure 12. RF Input Sensitivity
Figure 15. Phase Noise vs. Temperature
6
5
1.700
1.696
1.692
1.688
1.684
1.680
1.676
1.672
1.668
1.664
1.660
1.656
1.652
1.648
1.644
1.640
4
3
A
2
1
B
0
–1
–2
–3
–4
–5
–6
0
1
2
3
4
5
0
10
20
30
40
50
60
65
75
85
95 100
V
(V)
CP
TIME (µs)
Figure 16. A) Lock Time in Fast-lock Mode. Fast Counter = 150, Low Spur
Mode: a 1649.7 MHz to 1686.8 MHz Frequency Jump.
Figure 13. Charge Pump Output Characteristics
Final Loop Bandwidth = 60 kHz
B) Lock Time with the PLL in Normal Mode (Non Fast-lock), Low Spur Mode, a
1649.7 MHz to 1686.8 MHz Frequency Jump. Final Loop Bandwidth = 60 kHz
Rev. 0 | Page 8 of 20
ADF4154
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
FPFD = REFIN
where:
×
1 + D
R
(2)
The reference input stage is shown in Figure 17. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that the REFIN pin is not loaded on
power-down.
REFIN is the reference input frequency.
D is the REFIN doubler bit.
R is the preset divide ratio of binary 4-bit programmable
reference counter (1 to 15).
INT is the preset divide ratio of binary 9-bit counter (31 to 511).
MOD is the preset modulus ratio of binary 12-bit program-
mable FRAC counter (2 to 4095).
FRAC is the preset fractional ratio of binary 12-bit
programmable FRAC counter (0 to MOD).
POWER-DOWN
CONTROL
100kΩ
SW2
NC
TO R COUNTER
REF
IN
NC
BUFFER
SW1
NO
SW3
RF R COUNTER
Figure 17. Reference Input Stage
The 4-bit RF R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock to
the PFD. Division ratios from 1 to 15 are allowed.
RF INPUT STAGE
The RF input stage is shown in Figure 18. It is followed by a
2-stage limiting amplifier to generate the current mode logic
(CML) clock levels needed for the prescaler.
RF N-DIVIDER
N = INT + FRAC/MOD
FROM RF
INPUT STAGE
TO PFD
N COUNTER
1.6V
BIAS
GENERATOR
THIRD ORDER
FRACTIONAL
INTERPOLATOR
AV
DD
2kΩ
2kΩ
INT
REG
MOD
REG
FRAC
VALUE
RF
RF
A
B
IN
Figure 19. A and B Counters
IN
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 20 is a simplified schematic.
The PFD includes a fixed delay element that sets the width of
the antibacklash pulse, which is typically 3 ns. This pulse
ensures that there is no dead zone in the PFD transfer function
AGND
Figure 18. RF Input Stage
RF INT DIVIDER
The RF INT CMOS counter allows a division ratio in the PLL
feedback counter. Division ratios from 31 to 511 are allowed.
and gives a consistent reference spur level.
UP
HI
D1
Q1
U1
CLR1
INT, FRAC, MOD, AND R RELATIONSHIP
+IN
The INT, FRAC, and MOD values, in conjunction with the
R counter, make it possible to generate output frequencies that
are spaced by fractions of the phase frequency detector (PFD).
See the RF Synthesizer: A Worked Example section for more
information. The RF VCO frequency (RFOUT) equation is
CHARGE
PUMP
CP
U3
DELAY
DOWN
CLR2
D2 Q2
RFOUT = FPFD × INT + FRAC MOD
(1)
HI
U2
where RFOUT is the output frequency of the external voltage
–IN
controlled oscillator (VCO).
Figure 20. PFD Simplified Schematic
Rev. 0 | Page 9 of 20
ADF4154
Data is transferred from the shift register to one of four latches
on the rising edge of LE. The destination latch is determined by
the state of the two control bits (C2 and C1) in the shift register.
These are the 2 LSBs, DB1, and DB0, as shown in Figure 2. The
truth table for these bits is shown in Table 5. Table 6 shows a
summary of how the latches are programmed.
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4154 allows the user to
access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 (see Table 9).
Figure 21 shows the MUXOUT section in block diagram form.
The N-channel, open-drain, analog lock detect should be
operated with an external pull-up resistor of 10 kΩ nominal.
When lock has been detected, the lock detect is high with
narrow low-going pulses.
PROGRAM MODES
Table 5 through Table 10 show how to set up the program
modes in the ADF4154.
DV
DD
The ADF4154 programmable modulus is double-buffered. This
means that two events have to occur before the part uses a new
modulus value. First, the new modulus value is latched into the
device by writing to the R-divider register. Second, a new write
must be performed on the N-divider register. Therefore, when-
ever the modulus value is updated, the N-divider register must
then be written to so that the modulus value is loaded correctly.
LOGIC LOW
ANALOG LOCK DETECT
R-DIVIDER OUTPUT
N-DIVIDER OUTPUT
FAST-LOCK CONTROL
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
LOGIC HIGH
MUXOUT
MUX
CONTROL
Table 5. C2 and C1 Truth Table
Control Bits
DGND
C2
0
0
1
1
C1
0
1
0
1
Data Latch
Figure 21. MUXOUT Schematic
N-divider register
R-divider register
Control register
Noise and spur register
INPUT SHIFT REGISTERS
The ADF4154 digital section includes a 4-bit RF R counter, a
9-bit RF N counter, a 12-bit FRAC counter, and a 12-bit
modulus counter. Data is clocked into the 24-bit shift register
on each rising edge of CLK. The data is clocked in MSB first.
Rev. 0 | Page 10 of 20
ADF4154
REGISTERS
Table 6. Register Summary
N-DIVIDER REG
CONTROL
BITS
9-BIT RF INTEGER VALUE
12-BIT RF FRACTIONAL VALUE
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
DB9 DB8
F8 F7
DB7
F6
DB6
F5
DB5
F4
DB4 DB3 DB2
F3 F2 F1
DB1
DB0
FL1
N9
N8
N7
N6
N5
N4
N3
N2
N1
F12
F11
F10
F9
C2 (0) C1 (0)
R-DIVIDER REG
4-BIT
R COUNTER
CONTROL
BITS
MUXOUT
12-BIT MODULUS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
M7
DB7
M6
DB6
M5
DB5
M4
DB4 DB3 DB2
DB1 DB0
P3
M3
M2
M1
P2
P1
R4
R3
R2
R1
M12
M11
M10
M9
M8
M3
M2
M1
C2 (0) C1 (1)
CONTROL REG
CP CURRENT
SETTING
CONTROL
BITS
RESERVED
DB15 DB14 DB13 DB12 DB11 DB10
DB9
CP2
DB8
CP1
DB7
CP0
DB6
U5
DB5
U4
DB4
U3
DB3
U2
DB2
U1
DB1
DB0
0
0
0
0
U6
CP3
C2 (1) C1 (0)
NOISE AND SPUR REG
CONTROL
BITS
NOISE AND SPUR
MODE
RESERVED
DB10
T9
DB9
T8
DB8
T7
DB7 DB6 DB5
T6 T5 T4
DB4
T3
DB3
T2
DB2
T1
DB1 DB0
C2 (1) C1 (1)
Table 7. Noise and Spur Register
NOISE AND SPUR
MODE
CONTROL
BITS
RESERVED
DB10
T9
DB9
T8
DB8
T7
DB7
T6
DB6
T5
DB5
T4
DB4
T3
DB3
T2
DB2
T1
DB1
DB0
C2 (1) C1 (1)
DB10, DB5, DB4, DB3
0
RESERVED
RESERVED
THESE BITS MUST BE SET TO 0
FOR NORMAL OPERATION.
DB9, DB8, DB7, DB6, DB2 NOISE AND SPUR SETTING
00000
11100
11111
LOWEST SPUR MODE
LOW NOISE AND SPUR MODE
LOWEST NOISE MODE
Rev. 0 | Page 11 of 20
ADF4154
Table 8. N-Divider Register Map
CONTROL
BITS
9-BIT INTEGER VALUE (INT)
12-BIT FRACTIONAL VALUE (FRAC)
DB23 DB22
N9
DB21
N8
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
F7
DB7
F6
DB6
F5
DB5
F4
DB4 DB3 DB2
F3 F2 F1
DB1
DB0
N7
N6
N5
N4
N3
N2
N1
C2 (0) C1 (0)
FL1
F8
F12
F11
F10
F9
F12
F11
F10
F3
F2
F1
FRACTIONAL VALUE (FRAC)
0
0
0
0
.
.
.
1
1
1
1
0
0
0
0
.
.
.
1
1
1
1
0
0
0
0
.
.
.
1
1
1
1
..........
0
0
0
0
.
.
.
1
1
1
1
0
0
1
1
.
.
.
0
0
1
1
0
1
0
1
.
.
.
0
1
0
1
0
1
2
3
.
.
.
4092
4093
4094
4095
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
N9
N8
N7
N6
N5
N4
N3
N2
N1
INTEGER VALUE (INT)
0
0
0
0
.
0
0
0
0
.
0
0
0
0
.
0
1
1
1
.
1
0
0
0
.
1
0
0
0
.
1
0
0
0
.
1
0
0
1
.
1
0
1
0
.
31
32
33
34
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
...
1
1
1
.
.
.
.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
509
510
511
FL1
FAST-LOCK
0
1
NORMAL OPERATION
FAST-LOCK ENABLED
Rev. 0 | Page 12 of 20
ADF4154
Table 9. R-Divider Register Map
CONTROL
BITS
MUXOUT
4-BIT R COUNTER
12-BIT INTERPOLATOR MODULUS VALUE (MOD)
DB23 DB22 DB21
DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
DB7 DB6 DB5 DB4 DB3 DB2
M6 M5 M4 M3 M2 M1
DB1
DB0
DB20 DB19
M1 P2
M3
M2
P1
R4
R3
R2
R1
M12
M11
M10
M9
M8
M7
P3
C2 (0) C1 (1)
P3 LOAD CONTROL
P1
PRESCALER
INTERPOLATOR
M12
M11
M10
M3
M2
M1
MODULUS VALUE (MOD)
0
1
NORMAL OPERATION
LOAD FAST-LOCK TIMER
0
1
4/5
8/9
0
0
0
.
.
.
1
1
1
1
0
0
0
.
.
.
1
1
1
1
0
0
0
.
.
.
1
1
1
1
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
0
1
.
.
.
1
1
1
1
1
1
0
.
.
.
0
0
1
1
0
1
0
.
.
.
0
1
0
1
2
3
4
.
.
.
4092
4093
4094
4095
RF R-COUNTER
DIVIDE RATIO
R4
R3
R2
R1
0
0
0
0
.
0
0
0
1
.
0
1
1
0
.
1
0
1
0
.
1
2
3
4
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
12
13
14
15
M3
M2
M1
MUXOUT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
ANALOG LOCK DETECT
N-DIVIDER OUTPUT
LOGIC HIGH
LOGIC LOW
R-DIVIDER OUTPUT
FAST-LOCK SWITCH
Rev. 0 | Page 13 of 20
ADF4154
Table 10. Control Register Map
CP CURRENT
SETTING
CONTROL
BITS
RESERVED
DB15 DB14 DB13 DB12 DB11 DB10 DB9
U6 CP3 CP2
DB8
CP1
DB7
CP0
DB6
U5
DB5
U4
DB4
U3
DB3 DB2
U2 U1
DB1
DB0
0
0
0
0
C2 (1) C1 (0)
REFERENCE
DOUBLER
U6
0
1
DISABLED
ENABLED
U1
COUNTER RESET
0
1
DISABLED
ENABLED
U2
CP THREE-STATE
0
1
DISABLED
THREE-STATE
U3
POWER-DOWN
0
1
NORMAL OPERATION
POWER-DOWN
I
(mA)
CP
÷3
CP0
CP1
CP0
2.700kΩ
5.100kΩ 10.00kΩ
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1.090
2.180
3.260
4.350
5.440
6.530
7.620
8.700
0.630
1.250
1.880
2.500
3.130
3.750
4.380
5.000
0.290
0.590
0.880
1.150
1.470
1.760
2.060
2.350
U4
LDP
0
1
3
5
U5
PD POLARITY
0
1
NEGATIVE
POSITIVE
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0.540
1.100
1.640
2.180
2.730
3.270
3.810
4.350
0.310
0.630
0.940
1.250
1.570
1.880
2.190
2.500
0.150
0.300
0.440
0.588
0.740
0.880
1.030
1.180
Rev. 0 | Page 14 of 20
ADF4154
Prescaler (P/P + 1)
REGISTER DEFINITION
N-Divider Register, R0
The dual-modulus prescaler (P/P + 1), along with the INT,
FRAC, and MOD counters, determines the overall division ratio
from the RFIN to the PFD input. Operating at CML levels, it
takes the clock from the RF input stage and divides it down for
the counters. It is based on a synchronous 4/5 core. When set to
4/5, the maximum RF frequency allowed is 2 GHz. Therefore,
when operating the ADF4154 above 2 GHz, this must be set to
8/9. The prescaler limits the INT value.
The on-chip N-divider register is programmed by setting
R0[1, 0] to [0, 0]. Table 8 shows the input data format for
programming this register.
9-Bit INT Value
These nine bits control what is loaded as the INT value. This is
used to determine the overall feedback division factor (see
Equation 1).
With P = 4/5, NMIN = 31.
With P = 8/9, NMIN = 91.
12-Bit FRAC Value
These 12 bits control what is loaded as the FRAC value into the
fractional interpolator. This value helps determine the overall
feedback division factor (see Equation 1). The FRAC value must
be less than the value loaded into the MOD register.
The prescaler can also influence the phase noise performance. If
INT < 91, a prescaler of 4/5 should be used. For applications
where INT > 91, P = 8/9 should be used for optimum noise
performance (see Table 9).
Fast-Lock
4-Bit RF R Counter
Setting the part to logic high enables fast-lock mode. To use
fast-lock, the required time value for wide bandwidth mode
needs to be loaded into the R-divider register.
The 4-bit RF R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock to
the phase frequency detector (PFD). Division ratios from 1 to
15 are allowed.
The charge pump current increases from 16× the minimum
current and reverts back to 1× the minimum current once the
time value loaded has expired.
12-Bit Interpolator Modulus/Fast-Lock Timer
Bits DB13–DB2 have two functions depending on the value of
the load control bit: modulus or fast lock timer value.
See the Fast-Lock Timer and Register Sequences section for
more information.
When the load control bit = 0 (DB23), the required modulus
may be programmed into the R-divider register (DB13–DB2).
R-DIVIDER REGISTER, R1
The on-chip R-divider register is programmed by setting
R1[1, 0] to [0, 1]. Table 9 shows the input data format for
programming this register.
When the load control bit = 1 (DB23), the required fast-lock
timer value may be programmed into the R-divider register
(DB13–DB2).
Load Control
This programmable register sets the fractional modulus, which
is the ratio of the PFD frequency to the channel step resolution
on the RF output. Refer to the RF Synthesizer: A Worked
Example section for more information.
When set to logic high, the value being programmed in the
modulus is not loaded into the modulus. Instead, it sets the fast-
lock timer. The value of the fast-lock timer/FPFD is the amount
of time the PLL stays in wide bandwidth mode.
The ADF4154 programmable modulus is double-buffered. This
means that two events must occur before the part uses a new
modulus value. First, the new modulus value is latched into the
device by writing to the R-divider register. Second, a new write
must be performed on the N-divider register. Therefore, when-
ever the modulus value is updated, the N-divider register must
be written to so that the modulus value is loaded correctly.
MUXOUT
The on-chip multiplexer is controlled by R1[22...20] on the
ADF4154. Table 9 shows the truth table.
Digital Lock Detect
The digital lock detect output goes high if there are 40
successive PFD cycles with an input error of less than 15 ns. It
stays high until a new channel is programmed or until the error
at the PFD input exceeds 30 ns for one or more cycles. If the
loop bandwidth is narrow compared to the PFD frequency, the
error at the PFD inputs may drop below 15 ns for 40 cycles
around a cycle slip. Therefore, the digital lock detect may go
falsely high for a short period until the error again exceeds
30 ns. In this case, the digital lock detect is reliable only as a
loss-of-lock detector.
CONTROL REGISTER, R2
The on-chip control register is programmed by setting R2[1, 0]
to [0, 1]. Table 10 shows the input data format for programming
this register.
RF Counter Reset
DB3 is the RF counter reset bit for the ADF4154. When this is 1,
the RF synthesizer counters are held in reset. For normal
operation, this bit should be 0.
Rev. 0 | Page 15 of 20
ADF4154
RF Charge Pump Three-State
NOISE AND SPUR REGISTER, R3
This bit puts the charge pump into three-state mode when
programmed to 1. It should be set to 0 for normal operation.
The on-chip noise and spur register is programmed by setting
R3[1, 0] to [1, 1]. Table 7 shows the input data format for
programming this register.
RF Power-Down
Noise and Spur Mode
DB4 on the ADF4154 provides the programmable power-down
mode. Setting Bit DB4 to 1 powers down the device. Setting
Bit DB4 to 0 returns the synthesizer to normal operation. While
in software power-down mode, the part retains all information
in its registers. Only when supplies are removed are the register
contents lost.
Noise and spur mode allows the user to optimize a design either
for improved spurious performance or for improved phase
noise performance. When the lowest spur setting is chosen,
dither is enabled. This randomizes the fractional quantization
noise so that it looks more like white noise rather than spurious
noise. This means that the part is optimized for improved
spurious performance. This operation would normally be used
when the PLL closed-loop bandwidth is wide for fast-locking
applications. A wide-loop bandwidth is seen as a loop
bandwidth greater than 1/10 of the RFOUT channel step
resolution (fRES). A wide-loop filter does not attenuate the spurs
to a level that a narrow-loop bandwidth would. When the low
noise and spur setting is enabled, dither is disabled. This
optimizes the synthesizer to operate with improved noise
performance. However, the spurious performance is degraded
in this mode compared to the lowest spurs setting. To further
improve noise performance, the lowest noise setting option can
be used, which reduces the phase noise. As well as disabling the
dither, it ensures that the charge pump operates in an optimum
region for noise performance. This setting is extremely useful
where a narrow-loop filter bandwidth is available. The
synthesizer ensures extremely low noise and the filter attenuates
the spurs. The typical performance characteristics give the user
an idea of the trade-off in a typical WCDMA setup for the
different noise and spur settings.
When a power-down is activated, the following events occur:
1. All active dc current paths are removed.
2. The synthesizer counters are forced to their load
state conditions.
3. The charge pump is forced into three-state mode.
4. The digital lock detect circuitry is reset.
5. The RFIN input is de-biased.
6. The input register remains active and capable of loading
and latching data.
Lock Detect Precision (LDP)
When the LDP bit is programmed to 0, 24 consecutive reference
cycles of 15 ns must occur before the digital lock detect is set.
When this bit is programmed to 1, 40 consecutive reference
cycles of 15 ns must occur before digital lock detect is set.
Phase Detector Polarity
DB6 in the ADF4154 sets the phase detector polarity. When the
VCO characteristics are positive, this should be set to 1. When
they are negative, it should be set to 0.
RESERVED BITS
Charge Pump Current Setting
These bits should be set to 0 for normal operation.
DB7, DB8, DB9, and DB10 set the charge pump current, which
should be set according to the loop filter design (see Table 10).
RF SYNTHESIZER: A WORKED EXAMPLE
This equation governs how the synthesizer should be
programmed.
REFIN Doubler
Setting the REFIN bit to 0 feeds the REFIN signal directly to the
4-bit RF R counter, which disables the doubler. Setting the REFIN
bit to 1 multiplies the REFIN frequency by a factor of 2 before
feeding into the 4-bit R counter. When the doubler is disabled,
the REFIN falling edge is the active edge at the PFD input to the
fractional synthesizer. When the doubler is enabled, both the
rising and falling edges of REFIN become active edges at the
PFD input.
RFOUT = [INT + (FRAC/MOD)] × [FPFD
]
(3)
(4)
where:
RFOUT is the RF frequency output.
INT is the integer division factor.
FRAC is the fractionality.
MOD is the modulus.
FPFD = [REFIN × (1 = D)/R]
When the doubler is enabled and the lowest spur mode is
chosen, the in-band phase noise performance is sensitive to the
REFIN duty cycle. The phase noise degradation can be as much
as 5 dB for the REFIN duty cycles outside a 45% to 55% range.
The phase noise is insensitive to the REFIN duty cycle in the
lowest noise mode and in the lowest noise and spur mode. The
phase noise is insensitive to the REFIN duty cycle when the
doubler is disabled.
where:
REFIN is the reference frequency input.
D is the RF REFIN doubler bit.
R is the RF reference division factor.
Rev. 0 | Page 16 of 20
ADF4154
For example, in a GSM 1800 system, where a 1.8 GHz RF
frequency output (RFOUT) is required, a 13 MHz reference
frequency input (REFIN) is available and a 200 kHz channel
resolution (fRES) is required on the RF output.
resolution. A 13 MHz reference signal could be fed directly to
the PFD. The modulus would be programmed to 520 when in
PDC mode (13 MHz/520 = 25 kHz). The modulus would be
reprogrammed to 65 for GSM 1800 operation (13 MHz/65 =
200 kHz). It is important that the PFD frequency remains con-
stant (13 MHz). By keeping the PFD constant, the user can
design a one-loop filter that can be used in both setups without
running into stability issues. The ratio of the RF frequency to
the PFD frequency affects the loop design. Keeping this
relationship constant instead of changing the modulus factor
results in a stable filter.
MOD = REFIN fRES
MOD =13 MHz 200 kHz = 65
From Equation 4,
FPFD = [13 MHz × (1 + 0)/1] = 13 MHz
(5)
(6)
1.8 G =13 MHz × INT + FRAC 65
≥
INT =138; ≥ FRAC = 30
SPURIOUS OPTIMIZATION AND FAST-LOCK
MODULUS
The ADF4154 can be optimized for low spurious signals by
using the noise and spur register. However, in order to achieve
fast-lock time, a wider loop bandwidth is needed. Note that a
wider loop bandwidth can lead to notable spurious signals,
which cannot be reduced significantly by the loop filter.
The choice of modulus (MOD) depends on the reference signal
(REFIN) available and the channel resolution (fRES) required at
the RF output. For example, a GSM system with 13 MHz REFIN
would set the modulus to 65, resulting in the RF output resolu-
tion (fRES) of 200 kHz (13 MHz/65) that is necessary for GSM.
Using the fast-lock feature can achieve the same fast-lock time
as the noise and spur register, but with the advantage of lower
spurious signals, since the final loop bandwidth is reduced by
a quarter.
REFERENCE DOUBLER AND REFERENCE DIVIDER
The reference doubler on-chip allows the input reference signal
to be doubled. This is useful for increasing the PFD comparison
frequency. Making the PFD frequency higher improves the
noise performance of the system. Doubling the PFD frequency
usually results in an improvement in noise performance of 3 dB.
It is important to note that the PFD cannot be operated above
32 MHz due to a limitation in the speed of the Σ-Δ circuit of
the N divider.
FAST-LOCK TIMER AND REGISTER SEQUENCES
If the fast-lock mode is used, a timer value needs to be loaded
into the PLL to determine the time of the wide bandwidth.
When the load control bit = 1, the timer value is loaded via the
12-bit modulus value. To use fast-lock, the PLL must be written
to in the following sequence:
12-BIT PROGRAMMABLE MODULUS
Unlike most other fractional-N PLLs, the ADF4154 allows the
user to program the modulus over a 12-bit range. This means
that the user can set up the part in many different configura-
tions for the application, when combined with the reference
doubler and the 4-bit R counter.
1. Load the R-divider register with DB23 = 1 and the chosen
fast-lock timer value (DB13–DB2) instead of the modulus.
Note that the duration of time the PLL remains in wide
bandwidth is equal to the fast-lock timer/FPFD
2. Load the noise and spur register.
3. Load the control register.
.
For example, consider an application that requires a 1.75 GHz
RF and a 200 kHz channel step resolution. The system has a
13 MHz reference signal.
4. Load R-divider register with DB23 = 0 and MUXOUT =
110 (DB22–DB20). All the other needed parameters,
including the modulus, also need to be loaded.
One possible setup is feeding the 13 MHz directly to the PFD
and programming the modulus to divide by 65, which would
result in the required 200 kHz resolution.
5. Load the N-divider register, including fast-lock = 1
(DB23), to activate fast-lock mode.
Another possible setup is using the reference doubler to create
26 MHz from the 13 MHz input signal. The 26 MHz signal is
then fed into the PFD, which programs the modulus to divide
by 130. This setup also results in 200 kHz resolution and offers
superior phase noise performance over the previous setup.
Once this procedure is completed, future frequency jumps
deploying fast-lock need to repeat only Step 5.
The programmable modulus is also very useful for multi-
standard applications. If a dual-mode phone requires PDC and
GSM 1800 standards, the programmable modulus is a huge
benefit. The PDC requires a 25 kHz channel step resolution,
whereas the GSM 1800 requires a 200 kHz channel step
Rev. 0 | Page 17 of 20
ADF4154
If fast-lock is not used, then use the following sequence:
1. Load the noise and spur register.
2. Load the control register.
ADF4154
R2
CP
VCO
C1
C2
R1
C3
R1A
3. Load the R-divider register with DB23 = 0 and other
MUXOUT
necessary parameters.
4. Load the N-divider register, including fast-lock = 0
Figure 23. Fast-lock Loop Filter Topology—Topology 2
(DB23) for normal operation.
SPURIOUS SIGNALS
Predicting Where They Appear
To change frequency, only Step 4 need be repeated.
FAST-LOCK: A WORKED EXAMPLE
As in integer-N PLLs, spurs appear at PFD frequency offsets
from the carrier. In a fractional-N PLL, spurs also appear at
frequencies equal to the RFOUT channel step resolution (fRES).
The third-order fractional interpolator engine of the ADF4154
may also introduce subfractional spurs. If the fractional deno-
minator (MOD) is divisible by 2, spurs appear at ½ fRES. If the
fractional denominator (MOD) is divisible by 3, spurs appear at
1/3 fRES. Harmonics of all spurs mentioned also appear. With the
lowest spur mode enabled, the fractional and subfractional
spurs are attenuated dramatically. The worst-case spurs appear
when the fraction is programmed to 1/MOD. For example, in a
GSM 900 MHz system with a 26 MHz PFD frequency and an
RFOUT channel step resolution (fRES) of 200 kHz, the MOD = 130.
PFD spurs appear at 26 MHz offset and fractional spurs appear
at 200 kHz offset. Since the MOD is divisible by 2, subfractional
spurs are also present at 100 kHz offset.
Consider an example in which PLL has reference frequencies of
13 MHz and FPFD = 13 MHz and a required lock time of 50 µs.
Therefore, the PLL is set to wide bandwidth for 40 µs.
If the time period chosen for the wide bandwidth is 40 µs, then
Fast-lock timer value = time in wide bandwidth × FPFD
Fast-lock timer value = 40 µs × 13 MHz = 520
Therefore, 520 has to be loaded into the R-divider register in
Step 1 of the sequence described in the Fast-Lock Timer and
Register Sequences section.
FAST-LOCK: LOOP FILTER TOPOLOGY
To use fast-lock mode, an extra connection from the PLL to the
loop filter is needed. The MUXOUT must reduce the damping
resistor in the loop filter to ¼ while in wide bandwidth mode.
This is required because the charge pump current is increased
by 16 while in wide bandwidth mode and stability must be
ensured. This can be done with the following two topologies:
FILTER DESIGN—ADISIMPLL
A filter design and analysis program is available to help the user
implement the PLL design. Visit www.analog.com/pll for a free
download of the ADIsimPLL software. The software designs,
simulates, and analyzes the entire PLL frequency and time
domain response. Various passive and active filter architectures
are allowed. Rev. 2 of ADIsimPLL allows analysis of the
ADF4154.
1. Divide the damping resistor (R1) into two values (R1 and
R1A) of ratio 1:3 (see Figure 22).
2. Use an extra resistor (R1A) and connect it directly from the
MUXOUT, as shown in Figure 22. The extra resistor must
be chosen such that the parallel combination of an extra
resistor and the damping resistor (R1) is reduced to ¼ of
the original value of R1 alone (see Figure 23).
INTERFACING
The ADF4154 has a simple, SPI® compatible serial interface for
writing to the device. SCLK, SDATA, and LE control the data
transfer. When LE (latch enable) is high, the 22 bits that have
been clocked into the input register on each rising edge of
SCLK are transferred to the appropriate latch. See Figure 2 for
the timing diagram and Table 5 for the latch truth table.
ADF4154
R2
CP
VCO
C1
C2
R1
C3
MUXOUT
R1A
The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate possible for the device is
909 kHz or one update every 1.1 µs. This is more than adequate
for systems that have typical lock times in the hundreds of
microseconds.
Figure 22 Fast-lock Loop Filter Topology—Topology 1
Rev. 0 | Page 18 of 20
ADF4154
ADuC812 Interface
ADSP-21xx
ADF4154
Figure 24 shows the interface between the ADF4154 and the
ADuC812 MicroConverter®. Since the ADuC812 is based on an
8051 core, this interface can be used with any 8051-based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, bring the I/O
port driving LE low. Each latch of the ADF4154 needs a 24-bit
word, which is accomplished by writing three 8-bit bytes from
the MicroConverter to the device. After the third byte is written,
the LE input should be brought high to complete the transfer.
SCLK
SCLOCK
SDATA
LE
DT
TFS
MUXOUT
(LOCK DETECT)
I/O FLAGS
Figure 25. ADSP-21xx to ADF4154 Interface
PCB DESIGN GUIDELINES FOR CHIP SCALE
PACKAGE
When operating in the mode described, the maximum
SCLOCK rate of the ADuC812 is 4 MHz. This means that the
maximum rate at which the output frequency can be changed is
180 kHz.
The lands on the chip scale package (CP-20) are rectangular.
The printed circuit board pad for these should be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. The land should be centered on the pad.
This ensures that the solder joint size is maximized.
ADuC812
ADF4154
SCLOCK
SCLK
MOSI
SDATA
LE
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edges of the pad pattern to avoid shorting.
I/O PORTS
MUXOUT
(LOCK DETECT)
Thermal vias may be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated into the thermal pad at
1.2 mm pitch grid. The via diameter should be between 0.3 mm
and 0.33 mm, and the via barrel should be plated with 1 oz. of
copper to plug the via.
Figure 24. ADuC812 to ADF4154 Interface
ADSP-2181 Interface
Figure 25 shows the interface between the ADF4154 and the
ADSP-21xx digital signal processor. As discussed previously, the
ADF4154 needs a 24-bit serial word for each latch write. The
easiest way to accomplish this using the ADSP-21xx family is to
use the autobuffered transmit mode of operation with alternate
framing. This provides a means for transmitting an entire block
of serial data before an interrupt is generated. Set up the word
length for eight bits and use three memory locations for each
24-bit word. To program each 24-bit latch, store each of the
three 8-bit bytes, enable the autobuffered mode, and write to the
transmit register of the DSP. This last operation initiates the
autobuffer transfer.
The user should connect the printed circuit board thermal pad
to AGND.
Rev. 0 | Page 19 of 20
ADF4154
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AB
Figure 26. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
0.60
MAX
4.0
BSC SQ
0.60
MAX
16
15
20
1
PIN 1
INDICATOR
2.25
2.10 SQ
1.95
3.75
BSC SQ
TOP
VIEW
BOTTOM
VIEW
11
10
5
0.75
0.55
0.35
6
0.25 MIN
0.80 MAX
0.65 TYP
0.30
0.23
0.18
12° MAX
1.00
0.85
0.80
0.05 MAX
0.02 NOM
0.20
REF
COPLANARITY
0.08
SEATING
PLANE
0.50
BSC
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
Figure 27. 20-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body, (CP-20)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADF4154BRU
ADF4154BRU-REEL
ADF4154BRU-REEL7
ADF4154BCP
ADF4154BCP-REEL
ADF4154BCP-REEL7
EVAL-ADF4154EB1
Description
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Option
RU-16
RU-16
RU-16
CP-20
Thin Shrink Small Outline Package (TSSOP)
Thin Shrink Small Outline Package (TSSOP)
Thin Shrink Small Outline Package (TSSOP)
Lead Frame Chip Scale Package (LFCSP)
Lead Frame Chip Scale Package (LFCSP)
Lead Frame Chip Scale Package (LFCSP)
CP-20
CP-20
Purchase of licensed I2C components of Analog Devices, Inc. or one of its sublicensed Associated Companies conveys a license for the purchaser under the
Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04833–0–4/04(0)
Rev. 0 | Page 20 of 20
相关型号：
EVAL-ADF4158EB1Z
Direct Modulation/Waveform Generating, 6.1 GHz Fractional-N Frequency Synthesizer
ADI
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