EVAL-CONTROLBRD2Z_技术文档

2-Channel, Software-Selectable, True

Bipolar Input, 1 MSPS, 12-Bit Plus Sign ADC

AD7322

FUNCTIONAL BLOCK DIAGRAM

FEATURES

V

REFIN/OUT

V

DD

CC

12-bit plus sign SAR ADC

True bipolar input ranges

AD7322

Software-selectable input ranges

10 V, 5 V, 2.5 V, 0 V to +10 V

1 MSPS throughput rate

Two analog input channels with channel sequencer

Single-ended, true differential, and pseudo differential

analog input capability

2.5V

VREF

V

0

1

13-BIT

IN

I/P

MUX

SUCCESSIVE

APPROXIMATION

ADC

T/H

IN

High analog input impedance

Low power: 21 mW

Full power signal bandwidth: 22 MHz

Internal 2.5 V reference

DOUT

SCLK

CS

CONTROL LOGIC

AND REGISTERS

CHANNEL

SEQUENCER

DIN

High speed serial interface

Power-down modes

V

DRIVE

14-lead TSSOP package

AGND

V

DGND

SS

iCMOS process technology

Figure 1.

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

The AD7322¹is a 2-channel, 12-bit plus sign, successive approx-

imation analog-to-digital converter (ADC) designed on the

iCMOS™ (industrial CMOS) process. iCMOS is a process

combining high voltage silicon with submicron CMOS and

complementary bipolar technologies. It enables the develop-

ment of a wide range of high performance analog ICs capable of

33 V operation in a footprint that no previous generation of high

voltage parts could achieve. Unlike analog ICs using conventional

CMOS processes, iCMOS components can accept bipolar input

signals while providing increased performance, dramatically

reduced power consumption, and reduced package size.

1. The AD7322 can accept true bipolar analog input signals,

±1ꢀ V, ±± V, and ±2.± V, and ꢀ V to +1ꢀ V unipolar signals.

2. The two analog inputs can be configured as two single-

ended inputs, one true differential input, or one pseudo

differential input.

3. 1 MSPS serial interface. SPI-/QSPI™-/DSP-/MICROWIRE™-

compatible interface.

4. Low power, 31 mW maximum, at 1 MSPS throughput rate.

±. Channel sequencer.

Table 1. Similar Devices

Device

Number Rate

Throughput

Number of

Channels

The AD7322 can accept true bipolar analog input signals. The

AD7322 has four software-selectable input ranges, ±1ꢀ V, ±± V,

±2.± V, and ꢀ V to +1ꢀ V. Each analog input channel can be

independently programmed to one of the four input ranges.

The analog input channels on the AD7322 can be programmed

to be single-ended, true differential, or pseudo differential.

Number of bits

12-bit plus sign

AD7329

AD7328

AD7327

AD7324

AD7323

AD7321

1000 kSPS

8

4

2

1000 kSPS

500 kSPS

1000 kSPS

500 kSPS

The ADC contains a 2.± V internal reference. The AD7322 also

allows for external reference operation. If a 3 V reference is

applied to the REFIN/OUT pin, the AD7322 can accept a true

bipolar ±12 V analog input. Minimum ±12 V V_DDand V_SS

supplies are required for the ±12 V input range. The ADC has a

high speed serial interface that can operate at throughput rates

up to 1 MSPS.

¹Protected by U.S. Patent No. 6,731,232.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

AD7322

TABLE OF CONTENTS

Features .............................................................................................. 1

Control Register ......................................................................... 22

Range Register ............................................................................ 24

Sequencer Operation ..................................................................... 2±

Reference ..................................................................................... 26

V_DRIVE............................................................................................ 26

Modes of Operation ....................................................................... 27

Normal Mode (PM1 = PMꢀ = ꢀ) ............................................. 27

Full Shutdown Mode (PM1 = PMꢀ = 1) ................................. 27

Autoshutdown Mode (PM1 = 1, PMꢀ = ꢀ)............................. 28

Autostandby Mode (PM1 = ꢀ, PMꢀ = 1) ................................ 28

Power vs. Throughput Rate....................................................... 29

Serial Interface ................................................................................ 3ꢀ

Microprocessor Interfacing........................................................... 31

AD7322 to ADSP-21xx.............................................................. 31

AD7322 to ADSP-BF±3x........................................................... 31

Application Hints ........................................................................... 32

Layout and Grounding .............................................................. 32

Power Supply Configuration .................................................... 32

Outline Dimensions....................................................................... 33

Ordering Guide .......................................................................... 33

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications .................................................................. 6

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ............................................. 9

Terminology .................................................................................... 13

Theory of Operation ...................................................................... 1±

Circuit Information.................................................................... 1±

Converter Operation.................................................................. 1±

Analog Input Structure.............................................................. 16

Typical Connection Diagram ................................................... 18

Analog Input ............................................................................... 18

Driver Amplifier Choice............................................................ 2ꢀ

Registers........................................................................................... 21

Addressing Registers.................................................................. 21

REVISION HISTORY

1/10—Rev. 0 to Rev. A

Changes to Power Requirements, Normal Mode (Operational),

Changes to Figure 4ꢀ and Figure 41............................................. 2ꢀ

Changes to Autostandby Mode (PM1 = ꢀ, PM = 1) Section.... 28

Changes to Table 14 and Table 1± ................................................ 31

Added Power Supply Configuration Section.............................. 32

Added Table 16; Renumbered Sequentially................................ 32

Added Figure ±3; Renumbered Sequentially .............................. 32

Updated Outline Dimensions....................................................... 33

I

_CCand I_DRIVEParameter; and Power Dissipation, Normal Mode

Parameter, Table 2............................................................................. ±

Changes to Endnote 1, Table 4........................................................ 7

Changes to Table 6.......................................................................... 1±

Changes to Figure 2± and Figure 26............................................. 16

Changes to Figure 3ꢀ and Figure 31............................................. 17

Changes to Figure 33 and Figure 34............................................. 18

Changes to Figure 39...................................................................... 19

12/05—Revision 0: Initial Version

Rev. A | Page 2 of 36

AD7322

SPECIFICATIONS

Unless otherwise noted, V_DD= 12 V to 16.± V, V_SS= −12 V to −16.± V, V_CC= 4.7± V to ±.2± V, V_DRIVE= 2.7 V to ±.2± V, V_REF= 2.± V to 3.ꢀ V

internal/external, f_SCLK= 2ꢀ MHz, f_S= 1 MSPS, T_A= T_MAXto T_MIN; for V_CC< 4.7± V, all specifications are typical.

Table 2.

B Version

Typ

Parameter¹

Min

Max

Unit

Test Conditions/Comments

DYNAMIC PERFORMANCE

Signal-to-Noise Ratio (SNR)²

f_IN= 50 kHz sine wave

Differential mode

76

72.5

dB

Single-ended/pseudo differential mode

Differential mode; 2.5 V and 5 V ranges

Differential mode; 0 V to +10 V and 10 V ranges

Single-ended/pseudo differential mode;

2.5 V and 5 V ranges

Signal-to-Noise + Distortion (SINAD)²75

72

76

72.5

−82

−80

dB

Single-ended/pseudo differential mode;

0 V to +10 V and 10 V ranges

Differential mode; 2.5 V and 5 V ranges

Differential mode; 0 V to +10 V and 10 V ranges

Single-ended/pseudo differential mode;

2.5 V and 5 V ranges

Single-ended/pseudo differential mode;

0 V to +10 V and 10 V ranges

Differential mode; 2.5 V and 5 V ranges

Total Harmonic Distortion (THD)²

−80

−77

dB

Peak Harmonic or Spurious Noise

(SFDR)²

−80

−78

−82

−79

dB

Differential mode; 0 V to +10 V and 10 V ranges

Single-ended/pseudo differential mode;

2.5 V and 5 V ranges

Single-ended/pseudo differential mode;

0 V to +10 V and 10 V ranges

dB

Intermodulation Distortion (IMD)²

Second-Order Terms

Third-Order Terms

fa = 50 kHz, fb = 30 kHz

−88

−90

7

50

−79

dB

ns

ps

dB

Aperture Delay³

Aperture Jitter³

Common-Mode Rejection Ratio

Up to 100 kHz ripple frequency; see Figure 17

(CMRR)²

Channel-to-Channel Isolation²

Full Power Bandwidth

−72

22

5

dB

MHz

f_INon unselected channels up to 100 kHz; see Figure 14

At 3 dB

At 0.1 dB

DC ACCURACY

All dc accuracy specifications are typical for 0 V to

10 V mode

Single-ended/pseudo differential mode:

1 LSB = FSR/4096; unless otherwise noted

Differential mode: 1 LSB = FSR/8192; unless

otherwise noted

Resolution

No Missing Codes

13

Bits

12-bit plus

Differential mode

sign (13 bits)

11-bit plus

Bits

Single-ended/pseudo differential mode

sign (12 bits)

Integral Nonlinearity²

1.1

1

LSB

Differential mode

Single-ended/pseudo differential mode

(LSB = FSR/8192)

−0.7/+1.2

Rev. A | Page 3 of 36

AD7322

B Version

Typ

Parameter¹

Differential Nonlinearity²

Min

Max

Unit

Test Conditions/Comments

−0.9/+1.5 LSB

Differential mode; guaranteed no missing codes to

13 bits

0.9

LSB

Single-ended mode; guaranteed no missing codes

to 12 bits

Single-ended/pseudo differential mode

(LSB = FSR/8192)

−0.7/+1

Offset Error^{2, 4}

−4/+9

−7/+10

0.6

0.5

8

LSB

Single-ended/pseudo differential mode

Differential mode

Single-ended/pseudo differential mode

Differential mode

Single-ended/pseudo differential mode

Differential mode

Single-ended/pseudo differential mode

Differential mode

Single-ended/pseudo differential mode

Differential mode

Single-ended/pseudo differential mode

Differential mode

Single-ended/pseudo differential mode

Differential mode

Single-ended/pseudo differential mode

Differential mode

Offset Error Match^{2, 4}

Gain Error^{2, 4}

14

Gain Error Match^{2, 4}

0.5

4

Positive Full-Scale Error^{2, 5}

Positive Full-Scale Error Match^{2, 5}

Bipolar Zero Error^{2, 5}

7

0.5

8.5

7.5

0.5

4

6

0.5

Bipolar Zero Error Match^{2, 5}

Negative Full-Scale Error^{2, 5}

Negative Full-Scale Error Match^{2, 5}

Single-ended/pseudo differential mode

Differential mode

Single-ended/pseudo differential mode

Differential mode

ANALOG INPUT

Input Voltage Ranges

(Programmed via Range Register)

Reference = 2.5 V; see Table 6

10

5

2.5

V

V_DD= 10 V min, V_SS= −10 V min, V_CC= 2.7 V to 5.25 V

V_DD= 5 V min, V_SS= −5 V min, V_CC= 2.7 V to 5.25 V

V_DD= 5 V min, V_SS= − 5 V min, V_CC= 2.7 V to 5.25 V

V_DD= 10 V min, V_SS= AGND min, V_CC= 2.7 V to 5.25 V

0 to 10

Pseudo Differential V_IN(−) Input

Range

V_DD= 16.5 V, V_SS= −16.5 V, V_CC= 5 V; see Figure 40

and Figure 41

3.5

6

5

V

nA

pF

Reference = 2.5 V; range = 10 V

Reference = 2.5 V; range = 5 V

Reference = 2.5 V; range = 2.5 V

Reference = 2.5 V; range = 0 V to +10 V

V_IN= V_DDor V_SS

Per channel, V_IN= V_DDor V_SS

When in track, 10 V range

When in track, 5 V and 0 V to +10 V range

When in track, 2.5 V range

When in hold, all ranges

+3/−5

DC Leakage Current

Input Capacitance³

80

3

13.5

16.5

21.5

3

REFERENCE INPUT/OUTPUT

Input Voltage Range

Input DC Leakage Current

Input Capacitance

2.5

3

1

V

μA

pF

V

10

2.5

Reference Output Voltage

Reference Output Voltage Error at

25°C

Reference Output Voltage

T_MINto T_MAX

Reference Temperature Coefficient

Reference Output Impedance

5

10

25

mV

3

7

ppm/°C

Ω

Rev. A | Page 4 of 36

AD7322

B Version

Typ

Parameter¹

Min

Max

Unit

Test Conditions/Comments

LOGIC INPUTS

Input High Voltage, V_INH

Input Low Voltage, V_INL

2.4

V

μA

pF

0.8

0.4

1

V_CC= 4.75 V to 5.25 V

V_CC= 2.7 V to 3.6 V

V_IN= 0 V or V_DRIVE

Input Current, I_IN

Input Capacitance, C_IN

3

10

5

LOGIC OUTPUTS

Output High Voltage, V_OH

Output Low Voltage, V_OL

Floating-State Leakage Current

Floating-State Output Capacitance³

Output Coding

V_DRIVE− 0.2

V

μA

pF

I_SOURCE= 200 μA

I_SINK= 200 μA

0.4

1

Straight natural binary

Twos complement

Coding bit set to 1 in control register

Coding bit set to 0 in control register

CONVERSION RATE

Conversion Time

800

305

1

ns

MSPS

kSPS

16 SCLK cycles with SCLK = 20 MHz

Track-and-Hold Acquisition Time^{2, 3}

Throughput Rate

Full-scale step input; see the Terminology section

See the Serial Interface section; V_CC= 4.75 V to 5.25 V

V_CC< 4.75 V

770

POWER REQUIREMENTS

Digital inputs = 0 V or V_DRIVE

V_DD

12

16.5

V

See Table 6

V_SS

V_CC

V_DRIVE

−12

2.7

−16.5

5.25

V

See Table 6

See Table 6; typical specifications for V_CC< 4.75 V

Normal Mode (Static)

0.9

mA

V_DD/V_SS

= 16.5 V, V_CC/V_DRIVE= 5.25 V

Normal Mode (Operational)

f_S= 1 MSPS

I_DD

I_SS

360

410

3.4

μA

mA

V_DD= 16.5 V

V_SS= −16.5 V

V_CC/V_DRIVE= 5.25 V

f_S= 250 kSPS

V_DD= 16.5 V

V_SS= −16.5 V

V_CC/V_DRIVE= 5.25 V

SCLK on or off

V_DD= 16.5 V

V_SS= −16.5 V

V_CC/V_DRIVE= 5.25 V

SCLK on or off

V_DD= 16.5 V

V_SS= −16.5 V

V_CC/V_DRIVE= 5.25 V

I_CCand I_DRIVE

Autostandby Mode (Dynamic)

I_DD

I_SS

I_CCand I_DRIVE

Autoshutdown Mode (Static)

I_DD

I_SS

200

210

1.3

μA

mA

1

μA

I_CCand I_DRIVE

Full Shutdown Mode

I_DD

1

μA

I_SS

I_CCand I_DRIVE

POWER DISSIPATION

Normal Mode

31

mW

μW

V_DD= 16.5 V, V_SS= −16.5 V, V_CC= 5.25 V

V_DD= 12 V, V_SS= −12 V, V_CC= 5 V

V_DD= 16.5 V, V_SS= −16.5 V, V_CC= 5.25 V

21

Full Shutdown Mode

38.25

¹Temperature range is −40°C to +85°C.

²See the Terminology section.

³Sample tested during initial release to ensure compliance.

⁴Unipolar 0 V to 10 V range with straight binary output coding.

⁵Bipolar range with twos complement output coding.

Rev. A | Page 5 of 36

AD7322

TIMING SPECIFICATIONS

Unless otherwise noted, V_DD= 12 V to 16.± V, V_SS= −12 V to −16.± V, V_CC= 2.7 V to ±.2± V, V_DRIVE= 2.7 V to ±.2±, V_DRIVE≤ V_CC

,

1

V

_REF= 2.± V to 3.ꢀ V internal/external, T_A= T_MAXto T_MIN

Table 3.

Parameter V_CC< 4.75 V

.

Limit at T_MIN, T_MAX

V_CC= 4.75 V to 5.25 V

Unit

Description

f_SCLK

50

14

16 × t_SCLK

75

50

20

16 × t_SCLK

60

kHz min

MHz max

ns max

ns min

ns max

ns min

ns max

ns min

ns max

μs max

μs typ

t_CONVERT

t_QUIET

t₁

t_SCLK= 1/f_SCLK

Minimum time between end of serial read and next falling edge of CS

Minimum CS pulse width

12

5

2

t₂

25

20

CS to SCLK setup time; bipolar input ranges ( 10 V, 5 V, 2.5 V)

Unipolar input range (0 V to 10 V)

Delay from CS until DOUT three-state disabled

Data access time after SCLK falling edge

SCLK low pulse width

SCLK high pulse width

SCLK to data valid hold time

SCLK falling edge to DOUT high impedance

DIN setup time prior to SCLK falling edge

DIN hold time after SCLK falling edge

45

26

35

14

t₃

t₄

t₅

t₆

t₇

t₈

57

0.4 × t_SCLK

13

40

10

4

43

0.4 × t_SCLK

8

22

9

4

t₉

t₁₀

t_POWER-UP

2

750

500

25

750

500

25

Power up from autostandby

Power up from full shutdown/autoshutdown mode, internal reference

Power up from full shutdown/autoshutdown mode, external reference

¹Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V_DRIVE) and timed from a voltage level of 1.6 V.

²When using the 0 V to 10 V unipolar range, running at 1 MSPS throughput rate with t₂at 20 ns, the mark space ratio must be limited to 50:50.

t₁

CS

t_CONVERT

t₂

t₆

1

2

3

4

5

13

14

t₅

15

16

SCLK

DOUT

IDENTIFICATION BIT

t₃

t₇

DB10

t₈

t₄

t_QUIET

ZERO

ADD0

SIGN

DB11

DB2

DB1

DB0

THREE-

STATE

ZERO

THREE-STATE

t₁₀

t₉

DON’T

CARE

REG

SEL

WRITE ZERO

MSB

LSB

DIN

Figure 2. Serial Interface Timing Diagram

Rev. A | Page 6 of 36

AD7322

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 4.

Parameter

Rating

V_DDto AGND, DGND

V_SSto AGND, DGND

V_DDto V_CC

V_CCto AGND, DGND

V_DRIVEto AGND, DGND

AGND to DGND

Analog Input Voltage to AGND¹

Digital Input Voltage to DGND

Digital Output Voltage to GND

REFIN to AGND

Input Current to Any Pin

Except Supplies²

−0.3 V to +16.5 V

+0.3 V to −16.5 V

V_CC− 0.3 V to 16.5 V

−0.3 V to +7 V

−0.3 V to +0.3 V

V_SS− 0.3 V to V_DD+ 0.3 V

−0.3 V to +7 V

−0.3 V to V_DRIVE+ 0.3 V

−0.3 V to V_CC+ 0.3 V

10 ꢀA

ESD CAUTION

Operating Teꢀperature Range

Storage Teꢀperature Range

Junction Teꢀperature

TSSOP Package

−40°C to +85°C

−65°C to +150°C

150°C

θ_JATherꢀal Iꢀpedance

θ_JCTherꢀal Iꢀpedance

Pb-Free Teꢀperature, Soldering

Reflow

113.5°C/W

30°C/W

260(0)°C

2.5 kV

ESD

¹If the analog inputs are driven froꢀ alternative V_DDand V_SSsupply circuitry,

Schottky diodes should be placed in series with the AD7322’s V_DDand V_SS

supplies. See the Power Supply Configuration section.

²Transient currents of up to 100 ꢀA do not cause SCR latch-up.

Rev. A | Page 7 of 36

AD7322

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

14

13

12

11

10

9

CS

SCLK

DGND

DOUT

DIN

DGND

AD7322

TOP VIEW

(Not to Scale)

AGND

V

DRIVE

CC

REFIN/OUT

V

SS

DD

V

0

8

1

IN

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic Description

1

CS

Chip Select. Active low logic input. This input provides the dual function of initiating conversions on

the AD7322 and framing the serial data transfer.

2

DIN

Data Input. Data to be written to the on-chip registers is provided on this input and is clocked into the

register on the falling edge of SCLK (see the Registers section).

3, 13

DGND

Digital Ground. Ground reference point for all digital circuitry on the AD7322. The DGND and AGND

voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a

transient basis.

4

5

AGND

Analog Ground. Ground reference point for all analog circuitry on the AD7322. All analog input signals

and any external reference signal should be referred to this AGND voltage. The AGND and DGND

voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a

transient basis.

REFIN/OUT Reference Input/Reference Output. The on-chip reference is available on this pin for use external to the

AD7322. The nominal internal reference voltage is 2.5 V, which appears at the pin. A 680 nF capacitor

should be placed on the reference pin (see the Reference section). Alternatively, the internal reference

can be disabled and an external reference applied to this input. On power-up, the external reference

mode is the default condition.

6

V_SS

Negative Power Supply Voltage. This is the negative supply voltage for the analog input section.

7, 8

V_IN0, V_IN1

Analog Input 0 and Analog Input 1. The analog inputs are multiplexed into the on-chip track-and-hold.

The analog input channel for conversion is selected by programming the ADD0 channel address bit in

the control register. The inputs can be configured as single-ended, true differential, or pseudo differential

(see Table 10). The configuration of the analog inputs is selected by programming the mode bits,

Bit Mode 1 and Bit Mode 0, in the control register. The input range on each input channel is controlled by

programming the range register. Input ranges of 10 V, 5 V, 2.5 V, and 0 V to +10 V can be selected

on each analog input channel when a +2.5 V reference voltage is used (see the Registers section).

9

10

V_DD

V_CC

Positive Power Supply Voltage. This is the positive supply voltage for the analog input section.

Analog Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for the ADC core on the AD7322.

This supply should be decoupled to AGND.

11

12

V_DRIVE

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface

operates. This pin should be decoupled to DGND. The voltage at this pin may be different from that at

V_CC, but it should not exceed V_CCby more than 0.3 V.

Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits

are clocked out on the falling edge of the SCLK input, and 16 SCLKs are required to access the data. The

data stream consists of two leading zero bits, a channel identification bit, the sign bit, and 12 bits of

conversion data. The data is provided MSB first (see the Serial Interface section).

DOUT

14

SCLK

Serial Clock, Logic Input. A serial clock input provides the SCLK used for accessing the data from the

AD7322. This clock is also used as the clock source for the conversion process.

Rev. A | Page 8 of 36

AD7322

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

0.8

0

V

= V

DRIVE

= 5V INT/EXT 2.5V REFERENCE

±10V RANGE

4096 POINT FFT

CC

T = 25°C

A

V

= V

= 5V

CC

DRIVE

V

, V = ±15V

+INL = +0.55LSB

–INL = –0.68LSB

–20

–40

DD SS

, V = ±15V

DD SS

0.6

T

= 25°C

A

INT/EXT 2.5V REFERENCE

±10V RANGE

0.4

f_IN= 50kHz

SNR = 77.30dB

0.2

–60

SINAD = 76.85dB

THD = –86.96dB

SFDR = –88.22dB

0

–80

–0.2

–0.4

–0.6

–0.8

–1.0

–100

–120

–140

0

1024

2048

3072

3584

CODE

4096

5120

6144

7168

8192

0

50

100 150 200 250 300 350 400 450 500

FREQUENCY (kHz)

512

1536

2560

4608

5632

6656

7680

Figure 7. Typical INL True Differential Mode

Figure 4. FFT True Differential Mode

1.0

0.8

0

–20

4096 POINT FFT

V

= V = 5V

CC

DRIVE

, V = ±15V

0.6

DD SS

T

= 25°C

A

INT/EXT 2.5V REFERENCE

±10V RANGE

0.4

–40

f_IN= 50kHz

SNR = 74.67dB

0.2

–60

SINAD = 74.03dB

THD = –82.68dB

SFDR = –85.40dB

0

–0.2

–0.4

–0.6

–0.8

–1.0

–80

–100

–120

–140

V

= V

DRIVE

= 5V

±10V RANGE

CC

T

V

= 25°C

+DNL = +0.79LSB

–DNL = –0.38LSB

A

, V = ±15V

DD SS

INT/EXT 2.5V REFERENCE

0

1024

2048

3072

3584

CODE

4096

5120

6144

7168

8192

512 1536

2560

4608

5632

6656

7680

0

50

100 150 200 250 300 350 400 450 500

FREQUENCY (kHz)

Figure 5. FFT Single-Ended Mode

Figure 8. Typical DNL Single-Ended Mode

1.0

0.8

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

V

= V = 5V

DRIVE

CC

= 25°C

V

= V = 5V

DRIVE

CC

= 25°C

T

A

T

A

V

, V = ±15V

DD SS

V

, V = ±15V

DD SS

INT/EXT 2.5V REFERENCE

±10V RANGE

+INL = +0.87LSB

–INL = –0.49LSB

INT/EXT 2.5V REFERENCE

±10V RANGE

+DNL = +0.72LSB

–DNL = –0.22LSB

0

1024

2048

3072

3584

CODE

4096

5120

6144

7168

8192

0

1024

2048

3072

3584

CODE

4096

5120

6144

7168

8192

512 1536

2560

4608

5632

6656

7680

512

1536 2560

4608

5632

6656

7680

Figure 6. Typical DNL True Differential Mode

Figure 9. Typical INL Single-Ended Mode

Rev. A | Page 9 of 36

AD7322

–50

80

75

70

65

60

55

50

V

= 5V

CC

±5V DIFF

±10V DIFF

/V = ±12V

–55

–60

–65

–70

–75

–80

–85

–90

–95

–100

DD SS

T

f

= 25°C

= 1MSPS

A

±2.5V DIFF

S

±10V SE

0V TO +10V DIFF

0V TO +10V SE

±5V SE

±2.5V SE

±10V DIFF

±10V SE

±5V DIFF

±5V SE

0V TO +10V DIFF

±2.5V DIFF

±2.5V SE

V

= 3V

CC

V

/V = ±12V

DD SS

T

= 25°C

A

f

= 1MSPS

S

10

100

1000

10

100

ANALOG INPUT FREQUENCY (kHz)

1000

ANALOG INPUT FREQUENCY (kHz)

Figure 10. THD vs. Analog Input Frequency for Single-Ended (SE) and True

Differential Mode (Diff) at 5 V V_CC

Figure 13. SINAD vs. Analog Input Frequency for Single-Ended (SE) and

Differential Mode (Diff) at 3 V V_CC

–50

–55

V

= 3V

CC

/V = ±12V

–55

–60

–65

–70

–75

–80

–85

–90

–95

–100

DD SS

T

f

= 25°C

= 1MSPS

A

S

V

= 3V

–60

–65

–70

–75

–80

–85

–90

–95

CC

±10V SE

V

= 5V

CC

0V TO +10V DIFF

±5V SE

0V TO +10V SE

±10V DIFF

±2.5V SE

±5V DIFF

V

/V = ±12V

DD SS

SINGLE-ENDED MODE

= 1MSPS

f

S

T

= 25°C

A

50kHz ON SELECTED CHANNEL

±2.5V DIFF

10

100

ANALOG INPUT FREQUENCY (kHz)

1000

0

100

200

300

400

500

600

FREQUENCY OF INPUT NOISE (kHz)

Figure 11. THD vs. Analog Input Frequency for Single-Ended (SE) and True

Differential Mode (Diff) at 3 V V_CC

Figure 14. Channel-to-Channel Isolation

80

10k

9k

8k

7k

6k

5k

4k

3k

2k

1k

0

9469

V

= 5V

CC

±10V DIFF

±5V DIFF

/V = ±12V

DD SS

RANGE = ±10V

10k SAMPLES

75

70

65

60

55

50

±2.5V DIFF

T

= 25°C

A

±2.5V SE

±5V SE

0V TO +10V SE

±10V SE

0V TO +10V DIFF

V

= 5V

CC

/V = ±12V

DD SS

T

= 25°C

A

f

= 1MSPS

228

–1

303

1

S

0

2

10

100

ANALOG INPUT FREQUENCY (kHz)

1000

–2

0

CODE

Figure 12. SINAD vs. Analog Input Frequency for Single-Ended (SE) and

Differential Mode (Diff) at 5 V V_CC

Figure 15. Histogram of Codes True Differential Mode

Rev. A | Page 10 of 36

AD7322

2.0

1.5

8k

7k

6k

5k

4k

3k

2k

1k

0

7600

V

= 5V

CC

/V = ±12V

DD SS

RANGE = ±10V

10k SAMPLES

INL = 500kSPS

INL = 750kSPS

1.0

T

= 25°C

A

0.5

INL = 1MSPS

0

INL = 750kSPS

–0.5

–1.0

–1.5

–2.0

±5V RANGE

= V

1201

–1

1165

1

INL = 1MSPS

V

= 5V

DRIVE

CC

INTERNAL REFERENCE

SINGLE-ENDED MODE

0

23

–2

11

2

0

3

5

7

9

11

13

15

17

19

–3

0

±V /V SUPPLY VOLTAGE (V)

CODE

DD SS

Figure 16. Histogram of Codes, Single-Ended Mode

Figure 19. INL Error vs. Supply Voltage at 500 kSPS, 750 kSPS, and 1 MSPS

–50

100mV p-p SINE WAVE ON EACH SUPPLY

–55

–60

–65

–70

–75

–80

–85

–90

–95

–100

–55

–60

–65

–70

–75

–80

–85

–90

–95

–100

NO DECOUPLING

SINGLE-ENDED MODE

f

= 1MSPS

S

V

= 5V

CC

V

= 3V

CC

V

= 5V

CC

= 12V

DD

V

= 3V

CC

DIFFERENTIAL MODE

f_IN= 50kHz

V

= –12V

SS

V

/V = ±12V

SS

f_S^D=^D1MSPS

T

= 25°C

A

0

200

400

600

800

1000

1200

0

200

400

600

800

1000

1200

RIPPLE FREQUENCY (kHz)

SUPPLY RIPPLE FREQUENCY (kHz)

Figure 17. CMRR vs. Common-Mode Ripple Frequency

Figure 20. PSRR vs. Supply Ripple Frequency Without Supply Decoupling

2.0

1.5

–50

V

= V = 5V

DRIVE

CC

DNL = 750kSPS

/V = ±12V

DD SS

–55

–60

–65

–70

–75

–80

–85

–90

–95

T

= 25°C

A

DNL = 500kSPS

INTERNAL REFERENCE

RANGE = ±10V AND ±2.5V

R

= 100Ω, ±10V RANGE

IN

1.0

R

= 50Ω,

IN

±10V RANGE

R

= 2000Ω, ±10V RANGE

IN

0.5

DNL = 1MSPS

R

= 4700Ω,

IN

±2.5V RANGE

R

= 1000Ω, ±10V RANGE

IN

DNL = 1MSPS

0

R

= 2000Ω,

IN

±2.5V RANGE

–0.5

–1.0

–1.5

–2.0

R

= 1000Ω,

IN

±2.5V RANGE

DNL = 750kSPS

DNL = 500kSPS

R

= 100Ω,

IN

±2.5V RANGE

±5V RANGE

= V

INTERNAL REFERENCE

SINGLE-ENDED MODE

V

= 5V

DRIVE

CC

R

= 50Ω,

IN

±2.5V RANGE

5

7

9

11

13

15

17

19

10

100

ANALOG INPUT FREQUENCY (kHz)

1000

±V /V SUPPLY VOLTAGE (V)

DD SS

Figure 21. THD vs. Analog Input Frequency for Various Source Impedances,

True Differential Mode

Figure 18. DNL Error vs. Supply Voltage at 500 kSPS, 750 kSPS, and 1 MSPS

Rev. A | Page 11 of 36

AD7322

–50

V

= V = 5V

DRIVE

CC

/V = ±12V

DD SS

–55

–60

–65

–70

–75

–80

–85

–90

–95

T

= 25°C

A

INTERNAL REFERENCE

RANGE = ±10V AND ±2.5V

R

= 100Ω,

IN

±10V RANGE

R

= 2000Ω, ±10V RANGE

IN

R

= 50Ω,

IN

±10V RANGE

R

= 1000Ω, ±10V RANGE

IN

R

= 2000Ω,

IN

±2.5V RANGE

R

= 1000Ω,

IN

±2.5V RANGE

R

= 100Ω,

IN

±2.5V RANGE

R

= 50Ω,

IN

±2.5V RANGE

10

100

INPUT FREQUENCY (kHz)

1000

Figure 22. THD vs. Analog Input Frequency for Various

Source Impedances, Single-Ended Mode

Rev. A | Page 12 of 36

AD7322

TERMINOLOGY

Differential Nonlinearity

Negative Full-Scale Error

This is the difference between the measured and the ideal 1 LSB

change between any two adjacent codes in the ADC.

This applies when using twos complement output coding and

any of the bipolar analog input ranges. This is the deviation of

the first code transition (1ꢀ…ꢀꢀꢀ) to (1ꢀ…ꢀꢀ1) from the ideal

(that is, −4 × V_REF+ 1 LSB, −2 × V_REF+ 1 LSB, −V_REF+ 1 LSB)

after adjusting for the bipolar zero code error.

Integral Nonlinearity

This is the maximum deviation from a straight line passing

through the endpoints of the ADC transfer function. The

endpoints of the transfer function are zero scale (a point 1 LSB

below the first code transition) and full scale (a point 1 LSB

above the last code transition).

Negative Full-Scale Error Match

This is the difference in negative full-scale error between any

two input channels.

Offset Code Error

Track-and-Hold Acquisition Time

This applies to straight binary output coding. It is the deviation

of the first code transition (ꢀꢀ…ꢀꢀꢀ) to (ꢀꢀ…ꢀꢀ1) from the

ideal, that is, AGND + 1 LSB.

The track-and-hold amplifier returns into track mode after the

14^thSCLK rising edge. Track-and-hold acquisition time is the

time required for the output of the track-and-hold amplifier to

reach its final value, within ±1/2 LSB, after the end of a conversion.

For the ±2.± V range, the specified acquisition time is the time

required for the track-and-hold amplifier to settle to within ±1 LSB.

Offset Error Match

This is the difference in offset error between any two input

channels.

Signal-to-(Noise + Distortion) Ratio

Gain Error

This is the measured ratio of signal-to-(noise + distortion) at

the output of the ADC. The signal is the rms amplitude of the

fundamental. Noise is the sum of all nonfundamental signals up

to half the sampling frequency (f_S/2), excluding dc. The ratio is

dependent on the number of quantization levels in the digi-

tization process. The more levels there are, the smaller the

quantization noise becomes. Theoretically, the signal-to-(noise

+ distortion) ratio for an ideal N-bit converter with a sine wave

input is given by

This applies to straight binary output coding. It is the deviation

of the last code transition (111…11ꢀ) to (111…111) from the

ideal (that is, 4 × V_REF− 1 LSB, 2 × V_REF− 1 LSB, V_REF− 1 LSB)

after adjusting for the offset error.

Gain Error Match

This is the difference in gain error between any two input

channels.

Bipolar Zero Code Error

Signal-to-(Noise + Distortion) = (6.ꢀ2 N + 1.76) dB

This applies when using twos complement output coding and a

bipolar analog input. It is the deviation of the midscale transi-

tion (all 1s to all ꢀs) from the ideal input voltage, that is, AGND

− 1 LSB.

For a 13-bit converter, this is 8ꢀ.ꢀ2 dB.

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms sum of

harmonics to the fundamental. For the AD7322, it is defined as

Bipolar Zero Code Error Match

This refers to the difference in bipolar zero code error between

any two input channels.

2

V₂+V₃+V₄+V_±+V₆

THD (dB) = 2ꢀ log

V₁

Positive Full-Scale Error

where V₁is the rms amplitude of the fundamental, and V₂, V₃,

V₄, V₅, and V₆are the rms amplitudes of the second through the

sixth harmonics.

This applies when using twos complement output coding and

any of the bipolar analog input ranges. It is the deviation of the

last code transition (ꢀ11…11ꢀ) to (ꢀ11…111) from the ideal

(4 × V_REF− 1 LSB, 2 × V_REF− 1 LSB, V_REF− 1 LSB) after adjust-

ing for the bipolar zero code error.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the

rms value of the next largest component in the ADC output

spectrum (up to f_S/2, excluding dc) to the rms value of the

fundamental. Normally, the value of this specification is deter-

mined by the largest harmonic in the spectrum, but for ADCs

where the harmonics are buried in the noise floor, the largest

harmonic can be a noise peak.

Positive Full-Scale Error Match

This is the difference in positive full-scale error between any

two input channels.

Rev. A | Page 13 of 36

AD7322

terms are usually at a frequency close to the input frequencies.

As a result, the second- and third-order terms are specified

separately. The calculation of the intermodulation distortion is

per the THD specification, where it is the ratio of the rms sum

of the individual distortion products to the rms amplitude of

the sum of the fundamentals, expressed in decibels.

Channel-to-Channel Isolation

Channel-to-channel isolation is a measure of the level of crosstalk

between any two channels. It is measured by applying a full-scale,

1ꢀꢀ kHz sine wave signal to all unselected input channels and

determining the degree to which the signal attenuates in the

selected channel with a ±ꢀ kHz signal. Figure 14 shows the worst-

case across all eight channels for the AD7322. The analog input

range is programmed to be the same on all channels.

PSR (Power Supply Rejection)

Variations in power supply affect the full-scale transition but

not the linearity of the converter. Power supply rejection is the

maximum change in the full-scale transition point due to a

change in power supply voltage from the nominal value (see the

Typical Performance Characteristics section).

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and

fb, any active device with nonlinearities creates distortion

products at the sum and difference frequencies of mfa ± nfb,

where m, n = ꢀ, 1, 2, 3, and so on. Intermodulation distortion

terms are those for which neither m nor n are equal to ꢀ. For

example, the second-order terms include (fa + fb) and (fa − fb),

whereas the third-order terms include (2fa + fb), (2fa − fb),

(fa + 2fb), and (fa − 2fb).

CMRR (Common-Mode Rejection Ratio)

CMRR is defined as the ratio of the power in the ADC output

at full-scale frequency, f, to the power of a 1ꢀꢀ mV sine wave

applied to the common-mode voltage of the V_IN+ and V_IN−

frequency, f_S, as

The AD7322 is tested using the CCIF standard where two input

frequencies near the top end of the input bandwidth are used.

In this case, the second-order terms are usually distanced in

frequency from the original sine waves, whereas the third-order

CMRR (dB) = 1ꢀ log (Pf/Pf_S)

where Pf is the power at frequency f in the ADC output, and Pf_S

is the power at frequency f_Sin the ADC output (see Figure 17).

Rev. A | Page 14 of 36

AD7322

THEORY OF OPERATION

The serial clock input accesses data from the part and provides

the clock source for the successive approximation ADC. The

AD7322 has an on-chip 2.± V reference. However, the AD7322

can also work with an external reference. On power-up, the exter-

nal reference operation is the default option. If the internal

reference is the preferred option, the user must write to the

reference bit in the control register to select the internal refer-

ence operation.

CIRCUIT INFORMATION

The AD7322 is a fast, 2-channel, 12-bit plus sign, bipolar input,

serial ADC. The AD7322 can accept bipolar input ranges that

include ±1ꢀ V, ±± V, and ±2.± V; it can also accept a ꢀ V to

+1ꢀ V unipolar input range. A different analog input range can

be programmed on each analog input channel via the on-chip

registers. The AD7322 has a high speed serial interface that can

operate at throughput rates up to 1 MSPS.

The AD7322 also features power-down options to allow power

saving between conversions. The power-down modes are selected

by programming the on-chip control register as described in the

Modes of Operation section.

The AD7322 requires V_DDand V_SSdualsupplies for the high voltage

analog input structures. These supplies must be equal to or greater

than the analog input range. See Table 6 for the requirements of

these supplies for each analog input range. The AD7322 requires

a low voltage 2.7 V to ±.2± V V_CCsupply to power the ADC core.

CONVERTER OPERATION

The AD7322 is a successive approximation ADC built around

two capacitive DACs. Figure 23 and Figure 24 show simplified

schematics of the ADC in single-ended mode during the

acquisition and conversion phases, respectively. Figure 2± and

Figure 26 show simplified schematics of the ADC in differential

mode during acquisition and conversion phase, respectively.

Table 6. Reference and Supply Requirements

for Each Analog Input Range

Selected

Analog Input

Range (V)

Full-Scale

Input

Range (V)

Reference

Voltage (V)

Minimum

V_DD/V_SS(V)

V_CC(V)

10

2.5

3.0

2.5

3.0

2.5

3.0

2.5

3.0

10

3/5

10

12

The ADC is composed of control logic, a SAR, and capacitive

DACs. In Figure 23 (the acquisition phase), SW2 is closed and

SW1 is in Position A, the comparator is held in a balanced

condition, and the sampling capacitor array acquires the signal

on the input.

5

6

2.5

5

3

5

0 to +10

0 to +12

+10/AGND

+12/AGND

CAPACITIVE

DAC

To meet the specified performance when the AD7322 is confi-

gured with the minimum V_DDand V_SSsupplies for a chosen analog

input range, the throughput rate should be decreased from the

maximum throughput range (see the Typical Performance

Characteristics section). Figure 18 and Figure 19 show the

change in INL and DNL as the V_DDand V_SSvoltages are varied.

When operating at the maximum throughput rate, as the V_DD

and V_SSsupply voltages are reduced, the INL and DNL error

increases. However, as the throughput rate is reduced with the

minimum V_DDand V_SSsupplies, the INL and DNL error is

reduced.

COMPARATOR

C

S

B

A

V

0

IN

CONTROL

LOGIC

SW1

SW2

AGND

Figure 23. ADC Acquisition Phase (Single-Ended)

When the ADC starts a conversion (see Figure 24), SW2 opens

and SW1 moves to Position B, causing the comparator to become

unbalanced. The control logic and the charge redistribution

DAC are used to add and subtract fixed amounts of charge from

the capacitive DAC to bring the comparator back into a balanced

condition. When the comparator is rebalanced, the conversion

is complete. The control logic generates the ADC output code.

Figure 31 shows the change in THD as the V_DDand V_SSsupplies

are reduced. At the maximum throughput rate, the THD degrades

significantly as V_DDand V_SSare reduced. It is therefore necessary

to reduce the throughput rate when using minimum V_DDand

CAPACITIVE

DAC

V_SSsupplies so that there is less degradation of THD and the

COMPARATOR

specified performance can be maintained. The degradation is

due to an increase in the on resistance of the input multiplexer

when the V_DDand V_SSsupplies are reduced.

C

S

B

A

V

0

IN

CONTROL

LOGIC

SW1

SW2

AGND

The analog inputs can be configured as two single-ended inputs,

one true differential input, or one pseudo differential input.

Selection can be made by programming the mode bits, Mode ꢀ

and Mode 1, in the control register.

Figure 24. ADC Conversion Phase (Single-Ended)

Rev. A | Page 15 of 36

AD7322

Figure 2± shows the differential configuration during the

acquisition phase. For the conversion phase, SW3 opens and

SW1 and SW2 move to Position B (see Figure 26). The output

impedances of the source driving the V_IN+ and V_IN− pins must

be matched; otherwise, the two inputs will have different

settling times, resulting in errors.

The ideal transfer characteristic for the AD7322 when twos

complement coding is selected is shown in Figure 27. The ideal

transfer characteristic for the AD7322 when straight binary

coding is selected is shown in Figure 28.

011...111

011...110

CAPACITIVE

DAC

COMPARATOR

000...001

000...000

111...111

C

S

B

V

+

IN

A

SW1

SW2

CONTROL

LOGIC

SW3

–

IN

B

C

S

100...010

100...001

100...000

V

REF

CAPACITIVE

DAC

AGND – 1LSB

–FSR/2 + 1LSB

AGND + 1LSB

+FSR/2 – 1LSB BIPOLAR RANGES

+FSR – 1LSB UNIPOLAR RANGE

NOTES

1. V + REFERS TO V 0 AND V – REFERS TO V 1.

IN IN IN IN

ANALOG INPUT

Figure 25. ADC Differential Configuration During Acquisition Phase

Figure 27. Twos Complement Transfer Characteristic (Bipolar Ranges)

CAPACITIVE

DAC

111...111

111...110

COMPARATOR

C

S

B

V

+

IN

A

SW1

SW2

CONTROL

LOGIC

SW3

111...000

011...111

–

IN

B

C

S

V

REF

CAPACITIVE

DAC

000...010

000...001

000...000

NOTES

1. V + REFERS TO V 0 AND V – REFERS TO V 1.

IN IN IN IN

–FSR/2 + 1LSB

AGND + 1LSB

+FSR/2 – 1LSB BIPOLAR RANGES

+FSR – 1LSB UNIPOLAR RANGE

Figure 26. ADC Differential Configuration During Conversion Phase

ANALOG INPUT

Output Coding

Figure 28. Straight Binary Transfer Characteristic (Bipolar Ranges)

The AD7322 default output coding is set to twos complement.

The output coding is controlled by the coding bit in the control

register. To change the output coding to straight binary coding,

the coding bit in the control register must be set. When operat-

ing in sequence mode, the output coding for each channel in

the sequence is the value written to the coding bit during the

last write to the control register.

ANALOG INPUT STRUCTURE

The analog inputs of the AD7322 can be configured as single-

ended, true differential, or pseudo differential via the control

register mode bits (see Table 1ꢀ). The AD7322 can accept true

bipolar input signals. On power-up, the analog inputs operate as

two single-ended analog input channels. If true differential or

pseudo differential is required, a write to the control register is

necessary after power-up to change this configuration.

Transfer Functions

The designed code transitions occur at successive integer

LSB values (that is, 1 LSB, 2 LSB, and so on). The LSB size is

dependent on the analog input range selected.

Figure 29 shows the equivalent analog input circuit of the

AD7322 in single-ended mode. Figure 3ꢀ shows the equivalent

analog input structure in differential mode. The two diodes

provide ESD protection for the analog inputs.

Table 7. LSB Sizes for Each Analog Input Range

Input Range

Full-Scale Range/8192 Codes

LSB Size

2.441 mV

1.22 mV

0.61 mV

1.22 mV

V

DD

10 V

5 V

2.5 V

0 V to +10 V

20 V

10 V

5 V

D

C2

R1

V

0

IN

C1

D

10 V

V

SS

Figure 29. Equivalent Analog Input Circuit (Single-Ended)

Rev. A | Page 16 of 36

AD7322

V

DD

The AD7322 enters track mode on the 14^thSCLK rising edge.

When running the AD7322 at a throughput rate of 1 MSPS with

a 2ꢀ MHz SCLK signal, the ADC has approximately

D

C2

R1

V

+

IN

C1

D

1.± SCLK + t₈+ t_QUIET

V

SS

to acquire the analog input signal. The ADC goes back into

V

DD

CS

hold mode on the

falling edge.

D

C2

R1

As the V_DD/V_SSsupply voltage is reduced, the on resistance of

the input multiplexer increases. Therefore, based on the equation

for t_ACQ, it is necessary to increase the amount of acquisition

time provided to the AD7322 and, therefore, decrease the

overall throughput rate. Figure 31 shows that if the throughput

rate is reduced when operating with minimum V_DDand V_SS

supplies, the specified THD performance is maintained.

V

–

IN

C1

D

V

SS

NOTES

1. V + REFERS TO V 0 AND V – REFERS TO V 1.

IN IN IN IN

Figure 30. Equivalent Analog Input Circuit (Differential)

Care should be taken to ensure that the analog input does not

exceed the V_DDand V_SSsupply rails by more than 3ꢀꢀ mV.

Exceeding this value causes the diodes to become forward

biased and to start conducting into either the V_DDsupply rail or

_SSsupply rail. These diodes can conduct up to 1ꢀ mA without

causing irreversible damage to the part.

–50

V

= V

= 5V

CC

DRIVE

INTERNAL REFERENCE

–55

–60

–65

–70

–75

–80

–85

–90

–95

T

= 25°C

f_I^A_N= 10kHz

±5V RANGE

SE MODE

V

In Figure 29 and Figure 3ꢀ, Capacitor C1 is typically 4 pF and

can primarily be attributed to pin capacitance. Resistor R1 is a

lumped component made up of the on resistance of the input

multiplexer and the track-and-hold switch. Capacitor C2 is the

sampling capacitor; its capacitance varies depending on the

analog input range selected (see the Specifications section).

1MSPS

750kSPS

500kSPS

17

5

7

9

11

13

15

19

Track-and-Hold Section

±V /V SUPPLIES (V)

DD SS

The track-and-hold on the analog input of the AD7322 allows

the ADC to accurately convert an input sine wave of full-scale

amplitude to 13-bit accuracy. The input bandwidth of the track-

and-hold is greater than the Nyquist rate of the ADC. The

AD7322 can handle frequencies up to 22 MHz.

Figure 31. THD vs.

V_DD/V_SSSupply Voltage at 500 kSPS, 750 kSPS, and 1 MSPS

Unlike other bipolar ADCs, the AD7322 does not have a

resistive analog input structure. On the AD7322, the bipolar

analog signal is sampled directly onto the sampling capacitor.

This gives the AD7322 high analog input impedance. An

approximation for the analog input impedance can be

calculated from the following formula:

The track-and-hold enters its tracking mode on the 14^thSCLK

CS

rising edge after the falling edge. The time required to acquire

an input signal depends on how quickly the sampling capacitor

is charged. With zero source impedance, 3ꢀ± ns is sufficient to

acquire the signal to the 13-bit level. The acquisition time

required is calculated using the following formula:

Z = 1/(f_S× C_S)

where f_Sis the sampling frequency, and C_Sis the sampling

capacitor value.

t

_ACQ= 1ꢀ × ((R_SOURCE+ R) C)

C_Sdepends on the analog input range chosen (see the

where C is the sampling capacitance and R is the resistance seen

by the track-and-hold amplifier looking back on the input.

Specifications section). When operating at 1 MSPS, the analog

input impedance is typically 7± kꢁ for the ±1ꢀ V range. As the

sampling frequency is reduced, the analog input impedance

further increases. As the analog input impedance increases, the

current required to drive the analog input therefore decreases.

For the AD7322, the value of R includes the on resistance of the

input multiplexer and is typically 3ꢀꢀ Ω. R_SOURCEshould include

any extra source impedance on the analog input.

Rev. A | Page 17 of 36

AD7322

V+

5V

TYPICAL CONNECTION DIAGRAM

Figure 32 shows a typical connection diagram for the AD7322.

In this configuration, the AGND pin is connected to the analog

ground plane of the system, and the DGND pin is connected to

the digital ground plane of the system. The analog inputs on the

AD7322 can be configured to operate in single-ended, true

differential, or pseudo differential mode. The AD7322 can operate

with either an internal or external reference. In Figure 32, the

AD7322 is configured to operate with the internal 2.5 V reference.

A 680 nF decoupling capacitor is required when operating with

the internal reference.

AGND

V

0

IN

V

CC

DD

AD7322¹

V

SS

V–

ADDITIONAL PINS OMITTED FOR CLARITY.

1

Figure 33. Single-Ended Mode Typical Connection Diagram

True Differential Mode

The V_CCpin can be connected to either a 3 V supply voltage or a

5 V supply voltage. V_DDand V_SSare the dual supplies for the

high voltage analog input structures. The voltage on these pins

must be equal to or greater than the highest analog input range

selected on the analog input channels (see Table 6). The V_DRIVE

pin is connected to the supply voltage of the microprocessor.

The voltage applied to the V_DRIVEinput controls the voltage of

the serial interface. V_DRIVEcan be set to 3 V or 5 V.

The AD7322 can have a total of one true differential analog

input pair. Differential signals have some benefits over single-

ended signals, including better noise immunity based on the

device’s common-mode rejection and improvements in

distortion performance. Figure 34 defines the configuration of

the true differential analog inputs of the AD7322.

V

+

IN

+15V

V

+2.7V TO +5.25V

CC

+

AD7322¹

0.1µF

10µF

0.1µF

V

–

IN

1

V

CC

DD

+3V SUPPLY

V

DRIVE

+

10µF

0.1µF

AD7322

NOTES

1. V + REFERS TO V 0 AND V – REFERS TO V 1.

IN IN IN IN

CS

1

ADDITIONAL PINS OMITTED FOR CLARITY.

DOUT

SCLK

DIN

µC/µP

ANALOG INPUTS

±10V, ±5V, ±2.5V

0V TO +10V

V

0

IN

Figure 34. True Differential Inputs

1

IN

The amplitude of the differential signal is the difference

between the signals applied to the V_IN+ and V_IN− inputs in

each differential pair (V_IN+ − V_IN−). V_IN+ and V_IN− should

be simultaneously driven by two signals of equal amplitude,

dependent on the input range selected, that are 180° out of

phase. Assuming the 4 ꢀ V_REFmode, the amplitude of the

differential signal is −20 V to +20 V p-p (2 ꢀ 4 ꢀ V_REF),

regardless of the common mode.

DGND

SERIAL

INTERFACE

REFIN/OUT

1

680nF

AGND

V

SS

–15V

10µF

+

1

MINIMUM V AND V SUPPLY VOLTAGES

DD SS

DEPEND ON THE HIGHEST ANALOG INPUT

RANGE SELECTED.

0.1µF

Figure 32. Typical Connection Diagram

ANALOG INPUT

Single-Ended Inputs

The common mode is the average of the two signals

(V_IN+ + V_IN−)/2

The AD7322 has a total of two analog inputs when operating in

single-ended mode. Each analog input can be independently

programmed to one of the four analog input ranges. In applications

where the signal source is high impedance, it is recommended

to buffer the signal before applying it to the ADC analog inputs.

Figure 33 shows the configuration of the AD7322 in single-

ended mode.

and is therefore the voltage on which the two input signals

are centered.

This voltage is set up externally, and its range varies with

reference voltage. As the reference voltage increases, the

common-mode range decreases. When driving the differential

inputs with an amplifier, the actual common-mode range is

determined by the amplifier’s output swing. If the differential

inputs are not driven from an amplifier, the common-mode

range is determined by the supply voltage on the V_DDsupply pin

and the V_SSsupply pin.

Rev. A | Page 18 of 36

AD7322

8

6

When a conversion takes place, the common mode is rejected,

resulting in a noise-free signal of amplitude −2 ꢀ (4 ꢀ V_REF) to

+2 ꢀ (4 ꢀ V_REF), corresponding to Digital Code −4096 to

Digital Code +4095.

±5V RANGE

±2.5V

RANGE

±10V

RANGE

4

±10V

RANGE

2

5

±5V RANGE

4

0

±5V RANGE

3

2

±2.5V

RANGE

–2

–4

–6

–8

1

±5V RANGE

0

±2.5V

RANGE

V

= 5V

CC

±10V

–1

–2

–3

–4

–5

–6

= 2.5V

RANGE

REF

±2.5V

RANGE

±16.5V V /V

DD SS

±12V V /V

±10V

DD SS

RANGE

Figure 38. Common-Mode Range for V_CC= 5 V and REFIN/OUT = 2.5 V

V

= 3V

CC

Pseudo Differential Inputs

= 3V

REF

The AD7322 can have one pseudo differential pair. The V_IN+

input is coupled to the signal source and must have an amplitude

within the selected range for that channel as programmed in the

range register. A dc input is applied to the V_IN− input. The voltage

applied to this input provides an offset for the V_IN+ input from

ground or a pseudo ground. Pseudo differential inputs separate

the analog input signal ground from the ADC ground, allowing

cancellation of dc common-mode voltages. Figure 39 shows the

AD7322 configured in pseudo differential mode.

±16.5V V /V

DD SS

±12V V /V

DD SS

Figure 35. Common-Mode Range for V_CC= 3 V and REFIN/OUT = 3 V

8

±5V RANGE

6

4

±2.5V

RANGE

±2.5V

RANGE

±10V

RANGE

2

±10V

RANGE

When a conversion takes place, the pseudo ground corresponds

to Code −4096 and the maximum amplitude corresponds to

Code +4095.

0

–2

–4

V+

5V

V

= 5V

CC

= 3V

REF

±16.5V V /V

DD SS

±12V V /V

DD SS

V

+

IN

V

CC

DD

Figure 36. Common-Mode Range for V_CC= 5 V and REFIN/OUT = 3 V

AD7322¹

6

V

–

SS

IN

4

±5V RANGE

2

0

V–

NOTES

1. V + REFERS TO V 0 AND V – REFERS TO V 1.

IN IN IN IN

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 39. Pseudo Differential Inputs

–2

–4

–6

–8

±2.5V

±10V

RANGE RANGE

±10V

±2.5V

RANGE

Figure 40 and Figure 41 show the typical voltage range on the

V_IN− input for the different analog input ranges when

configured in the pseudo differential mode.

RANGE

V

= 3V

CC

= 2.5V

REF

For example, when the AD7322 is configured to operate in

pseudo differential mode and the 5 V range is selected with

16.5 V V_DD/V_SSsupplies and 5 V V_CC, the voltage on the V_IN−

input can vary from −6.5 V to +6.5 V.

±16.5V V /V

DD SS

±12V V /V

DD SS

Figure 37. Common-Mode Range for V_CC= 3 V and REFIN/OUT = 2.5 V

Rev. A | Page 19 of 36

AD7322

8

time of the AD7322. An op amp such as the AD8ꢀ21 meets this

requirement when operating in single-ended mode. The

AD8ꢀ21 needs an external compensating NPO type of

capacitor. The AD8ꢀ22 can also be used in high frequency

applications where a dual version is required.

±5V RANGE

±2.5V

RANGE

±5V RANGE

6

±2.5V

RANGE

±10V

RANGE

4

2

0

For lower frequency applications, op amps such as the AD797,

AD84±, and the AD861ꢀ can be used in the AD7322 single-

ended mode configuration.

–2

–4

–6

±10V

RANGE

Differential operation requires that V_IN+ and the V_IN− be simulta-

neously driven with two signals of equal amplitude that are 18ꢀ°

out of phase. The common mode must be set up externally to the

AD7322. The common-mode range is determined by the REFIN/

OUT voltage, the V_CCsupply voltage, and the particular amplifier

used to drive the analog inputs. Differential mode with either an

ac input or a dc input provides the best THD performance over a

wide frequency range. Because not all applications have a signal

preconditioned for differential operation, there is often a need to

perform the single-ended-to-differential conversion.

0V TO +10V

RANGE

0V TO +10V

RANGE

V

= 5V

REF

CC

= 2.5V

–8

±16.5V V /V

DD SS

±12V V /V

DD SS

Figure 40. Pseudo Input Range with V_CC= 5 V

4

2

±5V RANGE

±2.5V

RANGE

This single-ended-to-differential conversion can be performed

using an op amp pair. Typical connection diagrams for an op

amp pair are shown in Figure 42 and Figure 43. In Figure 42 the

common-mode signal is applied to the noninverting input of

the second amplifier.

0

–2

–4

–6

–8

±10V

RANGE

±2.5V

RANGE

±10V

RANGE

1.5kΩ

0V TO +10V

RANGE

0V TO +10V

RANGE

V

= 3V

= 2.5V

3kΩ

CC

REF

V

IN

V+

±16.5V V /V

DD SS

±12V V /V

DD SS

Figure 41. Pseudo Input Range with V_CC= 3 V

1.5kΩ

10kΩ

DRIVER AMPLIFIER CHOICE

In applications where the harmonic distortion and signal-to-

noise ratio are critical specifications, the analog input of the

AD7322 should be driven from a low impedance source. Large

source impedances significantly affect the ac performance of the

ADC and can necessitate the use of an input buffer amplifier.

V–

V

COM

20kΩ

Figure 42. Single-Ended-to-Differential Configuration with the AD845

When no amplifier is used to drive the analog input, the source

impedance should be limited to low values. The maximum source

impedance depends on the amount of THD that can be tolerated

in the application. The THD increases as the source impedance

increases and performance degrades. Figure 21 and Figure 22

show graphs of the THD vs. the analog input frequency for various

source impedances. Depending on the input range and analog

input configuration selected, the AD7322 can handle source

impedances of up to 4.7 kΩ before the THD starts to degrade.

442Ω

AD8021

V

IN

V+

442Ω

Due to the programmable nature of the analog inputs on the

AD7322, the choice of op amp used to drive the inputs is a

function of the particular application and depends on the input

configuration and the analog input voltage ranges selected.

442Ω

V–

AD8021

100Ω

The driver amplifier must be able to settle for a full-scale step to

a 13-bit level, ꢀ.ꢀ122%, in less than the specified acquisition

Figure 43. Single-Ended-to-Differential Configuration with the AD8021

Rev. A | Page 20 of 36

AD7322

REGISTERS

MSBs consist of the write bit, zero bit, and register select bit.

The AD7322 has two programmable registers, the control

register and the range register. These registers are write-only

registers.

The register select bit is used to determine which of the two on-

board registers is selected. The write bit determines if the data

on the DIN line following the register select bit loads into the

addressed register. If the write bit is 1, the bits are loaded into

the register addressed by the register select bits. If the write bit

is ꢀ, the data on the DIN line does not load into any register.

The zero bit must always be set to ꢀ.

ADDRESSING REGISTERS

A serial transfer on the AD7322 consists of 16 SCLK cycles. The

three MSBs on the DIN line during the 16 SCLK transfer are

decoded to determine which register is addressed. The three

Table 8. Decoding Register Select Bit and Write Bit

Write Zero Register Select Comment

0

1

0

X

0

1

Data on the DIN line during this serial transfer is ignored. Register contents remain unchanged.

This combination selects the control register. The subsequent 12 bits are loaded into the control register.

This combination selects the range register. The subsequent six bits are loaded into the range register.

Rev. A | Page 21 of 36

AD7322

register after the range register has been initialized. The bit

functions of the control register are shown in Table 9 (the

power-up status of all bits is 0).

CONTROL REGISTER

The control register is used to select the analog input channel,

analog input configuration, reference, coding, and power mode.

The control register is a write-only, 12-bit register. Data loaded

on the DIN line corresponds to the AD7322 configuration for

the next conversion. Data should be loaded into the control

The two analog input channels can be configured as one pseudo

differential analog input, one true differential input, or two

single-ended analog inputs (see Table 10).

MSB

LSB

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Write Zero

Register Select

Zero

ADD0 Mode 1 Mode 0 PM1 PM0 Coding Ref Seq1 Seq2 Zero

0

Table 9. Control Register Details

Bit

Mnemonic

Description

12, 11, 1

10

Zero

ADD0

These bits should contain 0 during each write to the control register.

This channel address bit is used to select the analog input channel for the next conversion if the

sequencer is not being used. If the sequencer is being used, this channel address bit is used to select the

final channel in the consecutive sequence (see Table 10).

9, 8

Mode 1,

Mode 0

These two mode bits are used to select the configuration of the two analog input pins, V_IN0 and V_IN1.

These bits are used in conjunction with the channel address bit. On the AD7322, the analog inputs can be

configured as single-ended inputs, true differential inputs, or pseudo differential inputs (see Table 10).

7, 6

5

PM1, PM0

Coding

The power management bits are used to select different power mode options on the AD7322 (see Table 11).

This bit is used to select the type of output coding the AD7322 uses for the next conversion result. If

coding = 0, the output coding is twos complement. If coding = 1, the output coding is straight binary.

When operating in sequence mode, the output coding for each channel is the value written to the coding

bit during the last write to the control register.

4

Ref

The reference bit is used to enable or disable the internal reference. If Ref = 0, the external reference is

enabled and used for the next conversion, and the internal reference is disabled. If Ref = 1, the internal

reference is used for the next conversion. When operating in sequence mode, the reference used for each

channel is the value written to the Ref bit during the last write to the control register.

3, 2

Seq1, Seq2

The Sequence 1 and Sequence 2 bits are used to control the operation of the sequencer (see Table 12).

Table 10. Analog Input Configuration Selection

Mode 1 = 1, Mode 0 = 0

Mode 1 = 1, Mode 0 = 1 1 Fully Differential Input 1 Pseudo Differential Input

Mode 1 = 0, Mode 0 =1

Mode 1 = 0, Mode 0 = 0

2 Single-Ended Inputs

Channel Address Bit

ADD0

V_IN+

V_IN−

Not allowed

V_IN+

V_IN0

V_IN−

V_IN1

V_IN+

V_IN0

V_IN−

V_IN1

V_IN+

V_IN0

V_IN1

V_IN−

0

1

AGND

Rev. A | Page 22 of 36

AD7322

Table 11. Power Mode Selection

PM1

PM0 Description

1

0

1

0

Full shutdown mode. In this mode, all internal circuitry on the AD7322 is powered down. Information in the control register

is retained when the AD7322 is in full shutdown mode.

Autoshutdown mode. The AD7322 enters autoshutdown on the 15^thSCLK rising edge when the control register is updated.

All internal circuitry is powered down in autoshutdown.

Autostandby mode. In this mode, all internal circuitry is powered down excluding the internal reference. The AD7322

enters autostandby mode on the 15^thSCLK rising edge after the control register is updated.

Normal mode. All internal circuitry is powered up at all times.

1

0

Table 12. Sequencer Selection

Seq1 Seq2 Sequence Type

0

X

The channel sequencer is not used. The analog channel, selected by programming the ADD0 bit in the control register,

selects the next channel for conversion.

1

0

This configuration is used in conjunction with the channel address bit in the control register. This allows continuous

conversions on a consecutive sequence of channels, from Channel 0 up to Channel 1, as selected by the channel address

bits in the control register. The range for each channel defaults to the ranges previously written into the range register.

1

The channel sequencer is not used. The analog channel, selected by programming the ADD0 bit in the control register,

selects the next channel for conversion.

Rev. A | Page 23 of 36

AD7322

RANGE REGISTER

register select bit to 1. After the initial write to the range register

occurs, each time an analog input is selected, the AD7322

automatically configures the analog input to the appropriate

range, as indicated by the range register. The ±1ꢀ V input range

is selected by default on each analog input channel (see Table 13).

The range register is used to select one analog input range per

analog input channel. This register is a 6-bit, write-only register

with two dedicated range bits for each of the analog input

channels, Channel ꢀ and Channel 1. There are four analog input

ranges, ±1ꢀ V, ±± V, ±2.± V, and ꢀ V to +1ꢀ V. A write to the

range register is selected by setting the write bit to 1 and the

MSB

LSB

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

Write

Zero

Register Select

V_IN0A

V_IN0B

0

V_IN1A

V_IN1B

0

Table 13. Range Selection

V_INxA

V_INxB

Description

0

1

0

1

0

1

This combination selects the 10 V input range on V_INx.

This combination selects the 5 V input range on V_INx.

This combination selects the 2.5 V input range on V_INx.

This combination selects the 0 V to +10 V input range on V_INx.

Rev. A | Page 24 of 36

AD7322

SEQUENCER OPERATION

The AD7322 can be configured to convert a sequence of

consecutive channels (see Figure 44). This sequence begins by

converting on Channel ꢀ and ends with a final channel selected

by Bit ADDꢀ in the control register. To operate the AD7322 in

this mode, set Seq1 to 1 and Seq2 to ꢀ, and then select the final

channel in the sequence by programming Bit ADDꢀ in the

control register.

When the control register is configured to operate the AD7322

in this mode, the DIN line can be held low, or the write bit can

be set to ꢀ. To return to traditional multichannel operation, a

write to the control register to set Seq1 to ꢀ and Seq2 to ꢀ is

necessary.

When Seq1 and Seq2 are both set to ꢀ, or when both are set to 1,

the AD7322 is configured to operate in traditional multichannel

mode, where a write to Channel Address Bit ADDꢀ in the control

register selects the next channel for conversion.

POWER ON.

CS

DIN: WRITE TO RANGE REGISTER TO SELECT THE RANGE

FOR THE ANALOG INPUT CHANNELS.

DOUT: CONVERSION RESULT FROM CHANNEL 0, ± 10V

RANGE, SINGLE-ENDED MODE.

CS

DIN: WRITE TO CONTROL REGISTER TO SELECT THE FINAL

CHANNEL IN THE CONSECUTIVE SEQUENCE, SET Seq1 = 1

AND Seq2 = 0. SELECT OUTPUT CODING FOR SEQUENCE.

DOUT: CONVERSION RESULT FROM CHANNEL 0,

RANGE SELECTED IN RANGE REGISTER 1,

SINGLE-ENDED MODE.

CS

DIN: WRITE BIT = 0 OR DIN LINE HELD LOWTO CONTINUE TO

CONVERT THROUGH THE SEQUENCE OF

CONSECUTIVE CHANNELS.

DOUT: CONVERSION RESULT FROM CHANNEL 0, RANGE AS

SELECTED IN RANGE REGISTER.

CS

DIN: WRITE BIT = 0 OR DIN LINE HELD LOWTO CONTINUE

THROUGH SEQUENCE OF CONSECUTIVE CHANNELS.

DOUT: CONVERSION RESULT FROM CHANNEL1, RANGE AS

SELECTED IN RANGE REGISTER.

DIN TIED LOW/WRITE BIT = 0.

CONTINUOUSLY CONVERT

ON CONSECUTIVE SEQUENCE

OF CHANNELS.

STOPPING

A SEQUENCE.

CS

DIN: WRITE TO CONTROL

REGISTER TO STOP THE

SEQUENCE, Seq1 = 0, Seq2 = 0.

DOUT: CONVERSION RESULT

FROM CHANNEL IN SEQUENCE.

Figure 44. Flowchart for Consecutive Sequence of Channels

Rev. A | Page 25 of 36

AD7322

conversion result from the first initial conversion is invalid. The

reference buffer requires ±ꢀꢀ ꢂs to power up and charge the 68ꢀ nF

decoupling capacitor during the power-up time.

REFERENCE

The AD7322 can operate with either the internal 2.± V on-chip

reference or an externally applied reference. The internal reference

is selected by setting the Ref bit in the control register to 1. On

power-up, the Ref bit is ꢀ, resulting in the selection of the external

reference for the AD7322 conversion. Suitable reference sources

for the AD7322 include AD78ꢀ, AD1±82, ADR431, REF193,

and ADR391.

The AD7322 is specified for a 2.± V to 3 V reference range.

When a 3 V reference is selected, the ranges are ±12 V, ±6 V,

±3 V, and ꢀ V to +12 V. For these ranges, the V_DDand V_SSsupply

must be equal to or greater than the maximum analog input

range selected (see Table 6).

The internal reference circuitry consists of a 2.± V band gap

reference and a reference buffer. When operating the AD7322 in

internal reference mode, the 2.± V internal reference is available

at the REFIN/OUT pin, which should be decoupled to AGND

using a 68ꢀ nF capacitor. It is recommended that the internal

reference be buffered before applying it elsewhere in the system.

The internal reference is capable of sourcing up to 9ꢀ μA.

V_DRIVE

The AD7322 has a V_DRIVEfeature to control the voltage at which

the serial interface operates. V_DRIVEallows the ADC to easily

interface to both 3 V and ± V processors. For example, if the

AD7322 is operated with a V_CCof ± V, the V_DRIVEpin can be

powered from a 3 V supply. This allows the AD7322 to accept

large bipolar input signals with low voltage digital processing.

On power-up, if the internal reference operation is required for

the ADC conversion, a write to the control register is necessary

to set the Ref bit to 1. During the control register write, the

Rev. A | Page 26 of 36

AD7322

MODES OF OPERATION

The AD7322 has several modes of operation that are designed

to provide flexible power management options. These options

can be chosen to optimize the power dissipation/throughput

rate ratio for different application requirements. The mode of

operation of the AD7322 is controlled by the power manage-

ment bits, Bit PM1 and Bit PMꢀ, in the control register as shown

in Table 11. The default mode is normal mode, in which all

internal circuitry is fully powered up.

The AD7322 remains fully powered up at the end of the

conversion if both PM1 and PMꢀ contain ꢀ in the control

register.

To complete the conversion and access the conversion result,

16 serial clock cycles are required. At the end of the conversion,

CS

can idle either high or low until the next conversion.

When the data transfer is complete, another conversion can be

initiated after the quiet time, t_QUIET, has elapsed.

NORMAL MODE (PM1 = PM0 = 0)

This mode is intended for the fastest throughput rate perfor-

mance, with the AD7322 being fully powered up at all times.

Figure 4± shows the general operation of the AD7322 in

normal mode.

FULL SHUTDOWN MODE (PM1 = PM0 = 1)

In this mode, all internal circuitry on the AD7322 is powered

down. The part retains information in the registers during full

shutdown. The AD7322 remains in full shutdown mode until

the power management bits, Bit PM1 and Bit PMꢀ, in the

control register are changed.

CS

The conversion is initiated on the falling edge of , and the

track-and-hold enters hold mode as described in the Serial

Interface section. Data on the DIN line during the 16 SCLK

transfer is loaded into one of the on-chip registers if the write

bit is set. The register is selected by programming the register

select bits (see Figure 4±).

A write to the control register with PM1 = 1 and PMꢀ = 1 places

the part into full shutdown mode. The AD7322 enters full shut-

down mode on the 1±^thSCLK rising edge when the control register

is updated.

CS

If a write to the control register occurs while the part is in full

shutdown mode with the power management bits, Bit PM1 and

Bit PMꢀ, set to ꢀ (normal mode), the part begins to power up

on the 1±^thSCLK rising edge when the control register is updated.

Figure 46 shows how the AD7322 is configured to exit full

shutdown mode. To ensure the AD7322 is fully powered up,

1

16

SCLK

2 LEADING ZEROS, CHANNEL I.D. BIT, SIGN BIT

+ CONVERSION RESULT

DOUT

DIN

DATA INTO CONTROL/RANGE REGISTER

t_POWER-UPfor full shutdown mode should elapse before the next

CS

falling edge.

Figure 45. Normal Mode

THE PART IS FULLY POWERED UP

ONCE t_POWER-UPHAS ELAPSED

PART IS IN FULL

SHUTDOWN

PART BEGINS TO POWER UP ON THE 15TH

SCLK RISING EDGE AS PM1 = PM0 = 0

t_POWER-UP

CS

1

16

1

16

SCLK

INVALID DATA

CHANNEL IDENTIFIER BITS + CONVERSION RESULT

DATA INTO CONTROL REGISTER

SDATA

DIN

DATA INTO CONTROL REGISTER

CONTROL REGISTER IS LOADED ON THE FIRST 15 CLOCKS,

PM1 = 0, PM0 = 0

TO KEEP THE PART IN NORMAL MODE, LOAD PM1 = PM0 = 0

IN CONTROL REGISTER

Figure 46. Exiting Full Shutdown Mode

Rev. A | Page 27 of 36

AD7322

AUTOSTANDBY MODE (PM1 = 0, PM0 = 1)

AUTOSHUTDOWN MODE (PM1 = 1, PM0 = 0)

In autostandby mode, portions of the AD7322 are powered

down, but the on-chip reference remains powered up. The

reference bit in the control register should be 1 to ensure that

the on-chip reference is enabled. This mode is similar to auto-

shutdown, but allows the AD7322 to power up much faster.

This allows faster throughput rates to be achieved.

Once the autoshutdown mode is selected, the AD7322 auto-

matically enters shutdown on the 1±^thSCLK rising edge. In

autoshutdown mode, all internal circuitry is powered down. The

AD7322 retains information in the registers during autoshutdown.

The track-and-hold is in hold mode during autoshutdown. On

CS

the rising

edge, the track-and-hold, which was in hold during

shutdown, returns to track as the AD7322 begins to power up.

The power-up from autoshutdown is ±ꢀꢀ ꢂs.

As is the case with the autoshutdown mode, the AD7322 enters

standby on the 1±^thSCLK rising edge when the control register

is updated (see Figure 47). The part retains information in the

When the control register is programmed to transition to autoshut-

down mode, it does so on the 1±^thSCLK rising edge. Figure 47

shows the part entering autoshutdown mode. Once in autoshut-

CS

registers during standby. Once in autostandby mode, the

signal must remain low to keep the part in autostandby mode.

CS

The AD7322 remains in standby until it receives a

rising

rising edge. On

rising edge, the track-and-hold, which was in hold mode

CS

down mode, the

autoshutdown mode. The AD7322 automatically begins to power

CS

signal must remain low to keep the part in

CS

edge. The ADC begins to power up on the

CS

the

up on the

required before a valid conversion, initiated by bringing the

CS

rising edge. The t_POWER-UPfor autoshutdown is

while the part was in standby, returns to track. The power-up

time from standby is 7±ꢀ ns.

signal low, can take place. When this valid conversion is

complete, the AD7322 powers down again on the 1±^thSCLK rising

CS

The user should ensure that 7±ꢀ ns have elapsed before bringing

edge. The

signal must remain low again to keep the part in

CS

low to attempt a valid conversion. Once this valid conversion

autoshutdown mode.

is complete, the AD7322 again returns to standby on the 1±^thSCLK

CS

rising edge. The

standby mode.

signal must remain low to keep the part in

Figure 47 shows the part entering autoshutdown mode. The

sequence of events is the same when entering autostandby mode.

In Figure 47, the power management bits are configured for auto-

shutdown. For autostandby mode, the power management bits,

PM1 and PMꢀ, should be set to ꢀ and 1, respectively.

PART BEGINS TO POWER

UP ON CS RISING EDGE

THE PART IS FULLY POWERED UP

ONCE t_POWER-UPHAS ELAPSED

PART ENTERS SHUTDOWN MODE

ON THE 15TH RISING SCLK EDGE

AS PM1 = 1, PM0 = 0

t_POWER-UP

CS

1

15 16

1

15 16

SCLK

VALID DATA

SDATA

DIN

DATA INTO CONTROL REGISTER

CONTROL REGISTER IS LOADED ON THE FIRST 15 CLOCKS,

PM1 = 1, PM0 = 0

Figure 47. Entering Autoshutdown/Autostandby Mode

Rev. A | Page 28 of 36

AD7322

POWER vs. THROUGHPUT RATE

20

18

16

14

12

10

8

The power consumption of the AD7322 varies with throughput

rate. The static power consumed by the AD7322 is very low, and

a significant power savings can be achieved as the throughput

rate is reduced. Figure 48 and Figure 49 shows the power vs.

throughput rate for the AD7322 at a V_CCof 3 V and ± V,

respectively. Both plots clearly show that the average power

consumed by the AD7322 is greatly reduced as the sample

frequency is reduced. This is true whether a fixed SCLK value is

used or if it is scaled with the sampling frequency. Figure 48 and

Figure 49 show the power consumption when operating in

normal mode for a fixed 2ꢀ MHz SCLK and a variable SCLK

that scales with the sampling frequency.

VARIABLE SCLK

20MHz SCLK

6

4

V

= 5V

CC

/V = ±12V

DD SS

2

T

= 25°C

A

INTERNAL REFERENCE

100 200 300 400 500 600 700 800 900 1000

THROUGHPUT RATE (kHz)

0

12

Figure 49. Power vs. Throughput Rate with 5 V V_CC

10

20MHz SCLK

8

VARIABLE SCLK

6

4

V

= 3V

CC

2

0

/V = ±12V

DD SS

T

= 25°C

A

INTERNAL REFERENCE

100 200 300 400 500 600 700 800 900 1000 1100

THROUGHPUT RATE (kSPS)

0

Figure 48. Power vs. Throughput Rate with 3 V V_CC

Rev. A | Page 29 of 36

AD7322

SERIAL INTERFACE

Figure ±ꢀ shows the timing diagram for the serial interface of

the AD7322. The serial clock applied to the SCLK pin provides

the conversion clock and controls the transfer of information to

and from the AD7322 during a conversion.

Data is clocked into the AD7322 on the SCLK falling edge. The

three MSBs on the DIN line are decoded to select which register

is addressed. The control register is a 12-bit register. If the

control register is addressed by the three MSBs, the data on the

DIN line is loaded into the control on the 1±^thSCLK rising edge.

If the range register is addressed, the data on the DIN line is

loaded into the addressed register on the 11^thSCLK falling edge.

CS

The

signal initiates the data transfer and the conversion

CS

process. The falling edge of

puts the track-and-hold into

hold mode and takes the bus out of three-state. Then the analog

input signal is sampled. Once the conversion is initiated, it

requires 16 SCLK cycles to complete.

Conversion data is clocked out of the AD7322 on each SCLK

falling edge. Data on the DOUT line consists of two leading

zero bits, a channel identifier bit, a sign bit, and a 12-bit

conversion result. The channel identifier bit is used to indicate

which channel corresponds to the conversion result. The first

The track-and-hold goes back into track mode on the 14^thSCLK

rising edge. On the 16^thSCLK falling edge, the DOUT line returns

to three-state. If the rising edge of occurs before 16 SCLK cycles

have elapsed, the conversion is terminated, and the DOUT line

returns to three-state. Depending on where the signal is brought

CS

leading zero bit is clocked out on the

falling edge, and the

second zero bit is clocked out on the first SCLK falling edge.

CS

high, the addressed register may be updated.

t₁

CS

t_CONVERT

t₂

t₆

1

2

3

4

5

13

14

t₅

15

16

SCLK

DOUT

IDENTIFICATION BIT

t₇

t₈

t₄

t₃

ZERO

t_QUIET

ADD0

SIGN

DB11

DB10

DB2

DB1

DB0

THREE-

STATE

ZERO

THREE-STATE

t₁₀

t₉

REG

SEL

DON’T

CARE

WRITE ZERO

MSB

LSB

DIN

Figure 50. Serial Interface Timing Diagram (Control Register Write)

Rev. A | Page 30 of 36

AD7322

MICROPROCESSOR INTERFACING

The serial interface on the AD7322 allows the part to be directly

connected to a range of different microprocessors. This section

explains how to interface the AD7322 with some common micro-

controller and DSP serial interface protocols.

The frequency of the serial clock is set in the SCLKDIV register.

When the instruction to transmit with TFS is given (AXꢀ = TXꢀ),

the state of the serial clock is checked. The DSP waits until the

SCLK goes high, low, and then high again before starting the

transmission. If the timer and SCLK are chosen so that the

instruction to transmit occurs on or near the rising edge of

SCLK, data can be transmitted either immediately or at the next

clock edge.

AD7322 TO ADSP-21xx

The ADSP-21xx family of DSPs interface directly to the AD7322

without requiring glue logic. The V_DRIVEpin of the AD7322 takes

the same supply voltage as that of the ADSP-21xx. This allows

the ADC to operate at a higher supply voltage than its serial

interface. The SPORTꢀ on the ADSP-21xx should be configured

as shown in Table 14.

For example, the ADSP-2111 has a master clock frequency of

16 MHz. If the SCLKDIV register is loaded with the value 3,

an SCLK of 2 MHz is obtained, and eight master clock periods

elapse for every one SCLK period. If the timer registers are loaded

with the value 8ꢀ3, 1ꢀꢀ.± SCLKs occur between interrupts and,

subsequently, between transmit instructions. This situation leads

to nonequidistant sampling because the transmit instruction occurs

on an SCLK edge. If the number of SCLKs between interrupts is

an integer of N, equidistant sampling is implemented by the DSP.

Table 14. SPORT0 Control Register Setup

Setting

Description

TFSW = RFSW = 1

INVRFS = INVTFS = 1

DTYPE = 00

SLEN = 1111

ISCLK = 1

TFSR = RFSR = 1

IRFS = 0

ITFS = 1

Alternative framing

Active low frame signal

Right justify data

16-bit data word

Internal serial clock

Frame every word

AD7322 TO ADSP-BF53x

The ADSP-BF±3x family of DSPs interface directly to the

AD7322 without requiring glue logic, as shown in Figure ±2.

The SPORTꢀ Receive Configuration 1 register should be set up

as outlined in Table 1±.

Internal receive frame sync

Internal transmit frame sync

The connection diagram is shown in Figure ±1. The ADSP-21xx

has TFSꢀ and RFSꢀ tied together. TFSꢀ is set as an output, and

RFSꢀ is set as an input. The DSP operates in alternative framing

mode, and the SPORTꢀ control register is set up as described in

Table 14. The frame synchronization signal generated on the

1

AD7322¹

ADSP-BF53x

SCLK

RSCLK0

RFS0

DT0

CS

TFS is tied to

and, as with all signal processing applications,

DIN

requires equidistant sampling. However, as in this example, the

timer interrupt is used to control the sampling rate of the ADC

and under certain conditions equidistant sampling cannot be

achieved.

DR0

DOUT

V

DRIVE

V

DD

1

AD7322¹

ADSP-21xx

1

ADDITIONAL PINS OMITTED FOR CLARITY.

SCLK

SCLK0

Figure 52. Interfacing the AD7322 to the ADSP-BF53x

TFS0

RFS0

CS

Table 15. SPORT0 Receive Configuration 1 Register

DIN

DT0

DR0

Setting

Description

RCKFE = 1

LRFS = 1

RFSR = 1

Sample data with falling edge of RSCLK

Active low frame signal

Frame every word

DOUT

V

DRIVE

IRFS = 1

Internal RFS used

Receive MSB first

Zero fill

Internal receive clock

Receive enable

V

DD

RLSBIT = 0

RDTYPE = 00

IRCLK = 1

RSPEN = 1

SLEN = 1111

TFSR = RFSR = 1

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 51. Interfacing the AD7322 to the ADSP-21xx

The timer registers are loaded with a value that provides an

interrupt at the required sampling interval. When an interrupt

is received, a value is transmitted with TFS/DT (ADC control

word). The TFS is used to control the RFS and, therefore, the

reading of data.

16-bit data-word

Transmit and receive frame sync

Rev. A | Page 31 of 36

AD7322

APPLICATION HINTS

LAYOUT AND GROUNDING

POWER SUPPLY CONFIGURATION

If the supply voltage for the analog input circuitry is different

from that of the AD7322 V_DDand V_SSsupplies or if the analog

input can be applied to the AD7322 before V_DDand V_SSare

established, then it is recommended that Schottky diodes be

placed in series with the AD7322 V_DDand V_SSsupply signals.

Figure ±3 shows this Schottky diode configuration. BAT43

Schottky diodes are used.

The printed circuit board that houses the AD7322 should be

designed so that the analog and digital sections are confined to

certain areas of the board. This design facilitates the use of

ground planes that can easily be separated.

To provide optimum shielding for ground planes, a minimum

etch technique is generally best. All AGND pins on the AD7322

should be connected to the AGND plane. Digital and analog

ground pins should be joined in only one place. If the AD7322

is in a system where multiple devices require an AGND and

DGND connection, the connection should still be made at only

one point. A star point should be established as close as possible

to the ground pins on the AD7322.

V+

3V/5V

V

CC

DD

CS

SCLK

DOUT

DIN

AD7322¹

V

0

1

IN

Good connections should be made to the power and ground

planes. This can be done with a single via or multiple vias for

each supply and ground pin.

V

SS

V–

Avoid running digital lines under the AD7322 device because

this couples noise onto the die. However, the analog ground

plane should be allowed to run under the AD7322 to avoid

noise coupling. The power supply lines to the AD7322 device

should use as large a trace as possible to provide low impedance

paths and reduce the effects of glitches on the power supply line.

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 53. Schottky Diode Connection

In an application where nonsymmetrical V_DDand V_SSsupplies

are being used, adhere to the following guidelines. Table 16

outlines the V_SSsupply range that can be used for particular V_DD

voltages when nonsymmetrical supplies are required. When

operating the AD7322 with low V_DDand V_SSvoltages, it is

recommended that these supplies be symmetrical.

To avoid radiating noise to other sections of the board, com-

ponents with fast switching signals, such as clocks, should be

shielded with digital ground and never run near the analog inputs.

Avoid crossover of digital and analog signals. To reduce the effects

of feedthrough within the board, traces should be run at right

angles to each other. A microstrip technique is the best method,

but its use may not be possible with a double-sided board. In this

technique, the component side of the board is dedicated to ground

planes, and signals are placed on the other side.

For the ꢀ V to 4 × V_REFrange, V_SScan be tied to AGND as per

minimum supply recommendations outlined in Table 6.

Table 16. Nonsymmetrical V_DDand V_SSRequirements

V_DD

Typical V_SSRange

−5 V to −5.5 V

−5 V to −8.5 V

−5 V to −11.5 V

−5 V to −15 V

5 V

6 V

7 V

8 V

Good decoupling is also important. All analog supplies should

be decoupled with 1ꢀ ꢂF tantalum capacitors in parallel with

ꢀ.1 ꢂF capacitors to AGND. To achieve the best results from

these decoupling components, they must be placed as close as

possible to the device, ideally right up against the device. The

ꢀ.1 ꢂF capacitors should have a low effective series resistance

(ESR) and low effective series inductance (ESI), such as is

typical of common ceramic and surface-mount types of

capacitors. These low ESR, low ESI capacitors provide a low

impedance path to ground at high frequencies to handle

transient currents due to internal logic switching.

9 V

−5 V to −16.5 V

10 V to 16.5 V

Rev. A | Page 32 of 36

AD7322

OUTLINE DIMENSIONS

5.10

5.00

4.90

14

8

7

4.50

4.40

4.30

6.40

BSC

1

PIN 1

0.65 BSC

1.05

1.00

0.80

1.20

MAX

0.20

0.09

0.75

0.60

0.45

8°

0°

0.15

0.05

COPLANARITY

0.10

SEATING

PLANE

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153-AB-1

Figure 54. 14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)

Dimensions show in millimeters

ORDERING GUIDE

Model¹

AD7322BRUZ

AD7322BRUZ-REEL

AD7322BRUZ-REEL7

EVAL-AD7322CBZ²

EVAL-CONTROL BRD2Z³

Temperature Range

–40°C to +85°C

Package Description

14-Lead TSSOP

Evaluation Board

Controller Board

Package Option

RU-14

–40°C to +85°C

¹Z = RoHS Compliant Part.

²This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL board for evaluation/demonstration purposes.

³This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete

evaluation kit, the particular ADC evaluation board (for example, EVAL-AD7322CBZ), the EVAL-CONTROL BRD2Z, and a 12 V transformer must be ordered. See the relevant

evaluation board data sheet for more information.

Rev. A | Page 33 of 36

AD7322

NOTES

Rev. A | Page 34 of 36

AD7322

NOTES

Rev. A | Page 35 of 36

AD7322

NOTES

registered trademarks are the property of their respective owners.

D04863-0-1/10(A)

Rev. A | Page 36 of 36


型号：	EVAL-CONTROLBRD2Z
厂家：	ADI
描述：	2-Channel, Software-Selectable, True Bipolar Input, 1 MSPS, 12-Bit Plus Sign ADC 2通道，软件可选的真双极性输入， 1 MSPS ， 12位加符号位ADC
文件：	总36页 (文件大小：592K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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