HMC1031 [ADI]
0.1MHz to 500 MHz Clock Generator with Integer N PLL;
| 型号： | HMC1031 |
| 厂家： | 
ADI |
| 描述： | 0.1MHz to 500 MHz Clock Generator with Integer N PLL |
| 文件： | 总13页 (文件大小：355K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0.1 MHz to 500 MHz Clock Generator
with Integer N PLL
Data Sheet
HMC1031
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Low current consumption: 1.95 mA typical
High phase frequency detector rate: 140 MHz
Hardware pin-programmable clock multiplication ratios:
1×/5×/10×
VCC
1
2
HMC1031
8
7
GND
CP
PFD/CP
REFIN
Lock detect indicator
LKD
1/N
LKDOP
D0
3
4
6
5
VCOIN
D1
Power-down mode (0.8 μA typical)
8-lead MSOP package: 4.9 mm × 3.0 mm
APPLICATIONS
Figure 1.
Low jitter clock generation
Low bandwidth (BW) jitter attenuation
Low frequency phase-locked loops (PLLs)
Frequency translation
Oven controlled crystal oscillator (OCXO) frequency
multipliers
Phase lock clean high frequency references to 10 MHz
equipment
GENERAL DESCRIPTION
Together with an external loop filter and a voltage controlled
crystal oscillator (VCXO), the HMC1031 forms a complete
clock generator solution targeted at low frequency jitter
attenuation and reference clock generation applications.
The integrated phase detector and charge pump are capable of
operating at up to 140 MHz, and a maximum VCXO input of
500 MHz ensures frequency compliance with a wide variety of
system clocks and VCXOs.
The HMC1031 features a low power integer N divider, support-
ing divide ratios of 1, 5, and 10, which is controlled via external
hardware pins and requires no serial port.
Additional features include an integrated lock detect indicator
available on a dedicated hardware pin, and a built in power-
down mode.
The HMC1031 is housed in an 8-lead MSOP package.
Rev. C
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www.analog.com
Tel: 781.329.4700
Technical Support
HMC1031
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................7
Applications Information .............................................................. 10
Jitter Attenuation........................................................................ 10
Frequency Translation ............................................................... 10
Loop Bandwidths with HMC1031........................................... 10
Using VCOs/VCXOs with Negative Tuning Slope ................ 10
Lock Detector ............................................................................. 10
Printed Circuit Board (PCB) .................................................... 11
Outline Dimensions....................................................................... 13
Ordering Guide .......................................................................... 13
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Specifications............................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Interface Schematics..................................................................... 6
REVISION HISTORY
10/15—v02.0215 to Rev. C
This Hittite Microwave Products data sheet has been reformatted
to meet the styles and standards of Analog Devices, Inc.
Changed MS8E to MSOP and VCO Input to VCOIN ...Throughout
Changes to Features Section............................................................ 1
Changes to Figure 3, Figure 4, and Figure 6 ................................. 6
Deleted GND Interface Schematic; Renumbered Sequentially.. 7
Change to Figure 17 ......................................................................... 8
Changes to Lock Detector Section ............................................... 10
Changes to Figure 25...................................................................... 12
Updated Outline Dimensions....................................................... 13
Changes to Ordering Guide .......................................................... 13
Rev. C | Page 2 of 13
Data Sheet
HMC1031
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
TA = 25°C, VCC = 3.3 V, unless otherwise specified.
Table 1.
Parameter
Test Conditions/Comments
Min
2.7
Typ
3.3
Max
Unit
V
POWER SUPPLY VOLTAGE
OPERATING TEMPERATURE
FREQUENCY1
3.5
−40
+27
+85
°C
Reference Input2
140
500
MHz
MHz
VCO Input
CHARGE PUMP
Current
Output Range3
50
µA
V
0.2 to VCC − 0.4
INPUT
Voltage Swing (Reference and
VCOIN Inputs)1
Externally ac-coupled to the chip2
0.5 × VCC approximately
0.1
40
3.5
60
V p-p
REFIN, VCOIN DC Bias
Duty Cycle
1.65
V
%
Impedance at 50 MHz
Applicable to REFIN and VCOIN pins
VCO/VCXO feedback divider
3600||4
1/5/10
Ω||pF
DIVIDE RATIOS
FIGURE OF MERIT (FOM)4
Floor
Divide by 10
−212
−254
−208
−252
−204
−248
dBc/Hz
dBc/Hz
Flicker
PHASE AND FLICKER NOISE
Flicker Noise (PNFLICK
)
PNFLICK = Flicker FOM + 20log(fVCXO) − 10log(fOFFSET),
where fVCXO is the VCXO frequency and fOFFSET is
the offset frequency
Determined by
formula
Phase Noise Floor (PNFLOOR
CURRENT
)
PNFLOOR = Floor FOM + 10log(fPD) + 20log(fVCXO/fPD),
where fPD is the phase detector frequency
Determined by
formula
Supply5
Power-Down6
100 MHz reference = VCXO, VCC = 3.3 V
VCC = 3.0 V, 25°C, D0 = 0, D1 = 0
VCC = 3.3 V, 85°C
1.95
0.05
0.8
1
mA
µA
µA
VCC = 3.6 V, 85°C
µA
LOCK DETECT OUTPUT CURRENT
CMOS output level
3
mA
1 The REFIN and VCOIN inputs must be ac-coupled to the HMC1031. The peak input level must not exceed VCC + 0.4 V with respect to GND.
2 The lower limit of operation, 0.1 MHz, is limited by off chip ac coupling. Select the size of the ac coupling capacitor such that the impedance, relative to the 3.6 kΩ
input impedance of the device and any termination impedances on the evaluation board (50 Ω by default), is insignificant.
3 The PLL may lock in the voltage range of 0.2 V to VCC − 0.4 V. However, the charge pump gain may be reduced. See Figure 14 for charge pump compliance.
4 See Figure 20 and Figure 21 for additional flicker FOM and floor FOM data, respectively.
5 See Figure 17 for additional supply current data. Base frequency: 100 MHz; base VCC: 3.3 V, 0.8 mA/V to 1 mA/V; base phase frequency detector (PFD) current: 1.8 mA,
8 μA/MHz; base divider current: 1.15 mA, 15 μA/MHz. For example, the device current for a 10 MHz reference and 50 MHz VCO at 3.0 V VCC can be calculated as: ΔPFD
current = (10 − 100) × (8 × 10−6) = −0.72 mA, ΔDIV current = (50 − 100) × (15 × 10−6) = −0.75 mA, device current = (1.8 − 0.72) + (1.15 − 0.75) = 1.48 mA at 3.3 V VCC. At
3 V, the VCC device current is approximately: 1.48 – (0.85 × 10−3) × (3.3 − 3.0) = 1.225 mA.
6 In power-down mode, the REFIN/VCOIN inputs and charge pump outputs are tristated. The power-down leakage current is measured without any signal applied to
the HMC1031.
Rev. C | Page 3 of 13
HMC1031
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Parameter
Rating
VCC to GND
−0.3 V to +3.6 V
−0.3 V to +3.6 V
VCC + 0.4 V
VCC + 0.4 V
125°C
D0, D1 Pins to GND
Maximum REFIN Input Voltage
Maximum VCOIN Input Voltage
Maximum Junction Temperature
Maximum Peak Reflow Temperature (MSL1)
Storage Temperature Range
Operating Temperature Range
Thermal Resistance
ESD CAUTION
260°C
−65°C to +150°C
−40°C to +85°C
0.2°C/mW
Reflow Soldering
Peak Temperature
260°C
40 sec
Class 2
Time at Peak Temperature
ESD Sensitivity (Human Body Model (HBM))
Rev. C | Page 4 of 13
Data Sheet
HMC1031
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VCC
1
8
7
GND
CP
REFIN
2
HMC1031
TOP VIEW
(Not to Scale)
LKDOP
D0
3
4
6
5
VCOIN
D1
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic Description
1
VCC
Supply Voltage (3.3 V Typical).
2
REFIN
LKDOP
D0, D1
Reference Input. REFIN is an externally ac-coupled reference frequency input.
Lock Detect Output, CMOS Drive.
3
4, 5
Integer N Division Ratio Selection. D0 and D1 are the CMOS inputs used to specify the integer N division ratio.
See Table 4.
6
7
8
VCOIN
CP
Voltage Controlled Oscillator Input. VCOIN is an ac-coupled VCO/VCXO input.
Charge Pump Output.
Ground.
GND
Table 4. Frequency Multiplication Truth Table
D0
0
D1
0
PLL Feedback Division Ratio (N)1
Power-down mode
Divide by 1
1
0
0
1
Divide by 5
1
1
Divide by 10
1 Set by SW1 in the evaluation PCB schematic (see Figure 24).
Rev. C | Page 5 of 13
HMC1031
Data Sheet
INTERFACE SCHEMATICS
VCC
VCC
REFIN
VCOIN
Figure 3. REFIN Interface Schematic
Figure 6. VCOIN Interface Schematic
VCC VCC
VCC
CP
LKDOP
Figure 7. CP Interface Schematic
Figure 4. LKDOP Interface Schematic
VCC
D0, D1
Figure 5. D0, D1 Interface Schematic
Rev. C | Page 6 of 13
Data Sheet
HMC1031
TYPICAL PERFORMANCE CHARACTERISTICS
T
A
= 25°C, VCC = 3.3 V, unless otherwise specified.
–40
–20
–40
100MHz VCXO LOCKED WITH TINY PLL
10MHz NOISY REFERENCE
50MHz VCXO LOCKED WITH TINY PLL
10MHz NOISY REFERENCE
OPEN LOOP VCXO PHASE NOISE
–60
12kHz TO 20MHz INTEGRATED JITTER
HMC1031/VCXO: 55fs
10MHz INPUT: 4ps
12kHz TO 20MHz INTEGRATED JITTER
HMC1031/VCXO: 190fs
10MHz INPUT: 4ps
–60
–80
–100
–120
–140
–160
–180
–80
–100
–120
–140
–160
–180
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
OFFSET (Hz)
OFFSET (Hz)
Figure 8. 10 MHz to 100 MHz with Noisy Reference Phase Noise;
Loop Filter Value: C8 = 4.7 nF, R7 = 1.2 kΩ, C9 = 62 µF, Loop Filter BW = 8 Hz,
VCXO = 100 MHz Crystek CVHD-950
Figure 11. 10 MHz to 50 MHz with Noisy Reference Phase Noise;
Loop Filter Value: C8 = 220 nF, R7 = 3.3 kΩ, C9 = 2.2 µF, Loop Filter BW =
50 Hz, VCXO = Bliley V105ACACB, 50 MHz
–20
–20
SIM MODEL
OPEN-LOOP VCXO PHASE NOISE
10MHz VERY NOISY REFERENCE
SIM VCXO RESPONSE
–40
–40
–60
SIM PLL CONTRIBUTION
100MHz VCXO LOCKED WITH TINY PLL
SIM REFERENCE RESPONSE
TOTAL MEASURED PHASE NOISE
FREE RUNNING BLILEY 50MHz
10MHz NOISY REFERENCE
12kHz TO 20MHz INTEGRATED JITTER
–60
HMC1031/VCXO: 57.8fs
10MHz INPUT: 16.2ps
12kHz TO 20MHz INTEGRATED JITTER
HMC1031/VCXO: 212fs
–80
–100
–120
–140
–160
–180
–80
–100
–120
–140
–160
–180
1
10
100
1k
10k
100k
1M
1
10
100
1k
10k
100k
1M
10M
100M
OFFSET (Hz)
OFFSET (Hz)
Figure 9. 10 MHz to 100 MHz with Very Noisy Reference Phase Noise;
Loop Filter Value: C8 = 4.7 nF, R7 = 1.2 kΩ, C9 = 62 µF; Loop Filter BW = 8 Hz;
VCXO = 100 MHz Crystek CVHD-950
Figure 12. Typical Closed-Loop Phase Noise, HMC1031 as Jitter Attenuator,
Loop BW = 100 Hz; Refer to Loop Filter Configuration 2 in Table 5
1000
500
200
100
0
0
–500
–1000
–1500
–2000
–100
–200
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
80
TIME (ms)
TIME (ms)
Figure 10. Phase Error During Lock Time for Divide by 5; 10 MHz Input;
50 MHz Output; Loop BW = 100 Hz; Refer to Loop Filter Configuration 2 in Table 5
Figure 13. Frequency Error During Lock Time for Divide by 5; 10 MHz Input;
50 MHz Output; Loop Bandwidth = 100 Hz; Refer to Loop Filter Configuration 2
in Table 5
Rev. C | Page 7 of 13
HMC1031
Data Sheet
60
50
40
30
3.0
2.5
2.0
1.5
1.0
+85°C
+27°C
–40°C
DIV 1, REF/VCXO = 122.88MHz
I
= 2.7V, VCC
SOURCE
DIV 10, REF = 10MHz,
VCXO = 100MHz
I
= 3.0V, VCC
SOURCE
I
SINK
20
10
I
= 3.3V, VCC
SOURCE
I
= 3.5V, VCC
SOURCE
0
DIV 5, REF = 10MHz, VCXO = 50MHz
–10
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
2.6
2.8
3.0
3.2
3.4
3.6
CHARGE PUMP OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 14. Typical Source and Sink Current vs. Charge Pump Output Voltage
Figure 17. Current vs. Supply Voltage, Different Configurations
10
10
0
–10
–20
–30
RECOMMENDED REGION
OF OPERATION
1
RECOMMENDED REGION
OF OPERATION
0.1
0.01
50
100
150
200
50
100
150
200
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
Figure 15. REFIN Input Power vs. Input Frequency
Figure 18. REFIN Input Voltage Swing vs. Input Frequency
10
10
0
1
RECOMMENDED REGION OF OPERATION
RECOMMENDED REGION OF OPERATION
–10
–20
–30
0.1
0.01
80
160
240
320
400
480
560
80
160
240
320
400
480
560
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
Figure 19. VCOIN Input Voltage Swing vs. Input Frequency;
Maximum Frequency Is Guaranteed in the Recommended Region of
Operation Across Temperature and Process Variation
Figure 16. VCOIN Input Power vs. Input Frequency,
Maximum Frequency Is Guaranteed in the Recommended Region of
Operation Across Temperature and Process Variation
Rev. C | Page 8 of 13
Data Sheet
HMC1031
–246
–248
–250
–252
–254
–256
–258
–260
–200
–205
–210
–215
+85°C
+27°C
–40°C
+85°C
+27°C
–40°C
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 20. Flicker FOM
Figure 21. Floor FOM
Rev. C | Page 9 of 13
HMC1031
Data Sheet
APPLICATIONS INFORMATION
VCC
1
HMC1031
8
7
GND
CP
UP TO 140MHz
NOISY CLOCK
REFERENCE
NARROW LOOP FILTER VCXO
PFD/CP
REFIN
2
UP TO 500MHz
CLEAN CLOCK
SIGNAL
LKD
1/N
LKDOP
D0
3
4
6
5
VCOIN
D1
Figure 22. Typical Application Diagram
bandwidths require large filter capacitors. Due to the low charge
pump current design of the HMC1031, smaller loop filter capaci-
tor sizes can be used to implement narrow loop filters. Note that
the HMC1031 is designed to operate in loop bandwidths of only
a few kilohertz in its widest loop bandwidth configuration.
JITTER ATTENUATION
In some cases, reference clocks to the system may come from
external noisy sources with high jitter. The HMC1031 can be
used to attenuate this incoming jitter and distribute a clean
clock in the system. In such a scheme, a narrow loop filter is
selected for the HMC1031. The device frequency locks to the
external VCXO, but the reference jitter is attenuated as defined by
the set loop filter bandwidth. The final output frequency and
phase noise characteristics outside the loop bandwidth is defined
by the phase noise characteristics of the VCXO used. A low
jitter clock reference yields better clocking performance and
better LO performance of the RF PLL VCOs, and improves the
SNR performance of analog-to-digital converters (ADCs) and
digital-to-analog converters (DACs).
USING VCOs/VCXOs WITH NEGATIVE TUNING
SLOPE
In its typical configuration, the HMC1031 works with any
VCO/VCXO that has a positive tuning slope. For any VCO/VCXO
with negative tuning slope, that is, when the frequency decreases
with increasing tuning voltage, connect the loop filter ac ground
to VCC instead of GND.
LOCK DETECTOR
The lock detector measures the arrival times between the divided
VCO edge and reference edge appearing at the phase detector.
When this offset becomes greater than approximately 6 ns, the
lock detector indicates an out of lock condition. Any leakage
current on the CP output causes a phase offset between the two
edges. Due to the relatively small 50 µA charge pump current,
the HMC1031 is sensitive to leakage currents and may indicate
a false out of lock condition if the leakage current from the
charge pump (Pin 7) to ground is too high.
FREQUENCY TRANSLATION
The reference clock in a test and measurement system or a
communications system is often a high accuracy OCXO with
excellent long-term stability. In some applications, the OCXO
frequency must be multiplied up to a higher rate to drive the
primary clock inputs in a system. The HMC1031 offers a very
low power, small package and high performance method to
multiply its incoming frequency in 1×, 5×, and 10× rates. Such
multiplication is required because the higher reference clocks
improve phase noise, ADC/DAC signal-to-noise ratio (SNR),
clock generator jitter, and PHY bit error rates (BERs). In this
scheme, the HMC1031 can be connected to an external low cost
VCXO (for example, at 50 MHz or 100 MHz), and lock this
external VCXO to the excellent long-term stability of the OCXO.
Leakage currents include dc current through the loop filter
capacitors and/or dc current into the VCO tuning voltage pin,
V
TUNE. It is recommended to use low leakage, loop filter multi-
layer ceramic capacitors (MLCCs) and careful VCO selection to
maximize VTUNE resistance. The maximum acceptable leakage is
dependent on the phase detector operating frequency and can
be calculated as follows:
LOOP BANDWIDTHS WITH HMC1031
In typical jitter attenuation applications, an incoming reference
clock is frequency locked with a narrow PLL loop bandwidth
such that its incoming noise is filtered out by the PLL and VCXO
combination. The out of band phase noise of the PLL follows
the VCXO that it is locked to. A narrow PLL loop bandwidth
ensures that the output jitter is determined by the VCXO (or
any other type of high quality factor VCO) and not affected by
the spectral noise of the incoming clock beyond the set loop
bandwidth.
3 ns
ILEAKAGE
=
ICP
tPD
where:
ILEAKAGE is the total leakage current in µA.
ICP is the charge pump current in µA (set to 50 µA).
tPD is the reference frequency period in ns.
Internal delays reduce the available lock detector range from
6 ns to 3 ns.
To facilitate narrow bandwidth loop filter configurations, the
HMC1031 is designed to have a low charge pump current of
50 µA. This architecture offers advantages in low power consump-
tion and loop filter design. Typically, narrow loop filter
Rev. C | Page 10 of 13
Data Sheet
HMC1031
For example, to guarantee correct lock detector operation with
a 10 MHz reference (tPD = 100 ns) and no leakage into the VCO
PRINTED CIRCUIT BOARD (PCB)
Use a sufficient number of via holes to connect the top and
bottom ground planes (see Figure 23). The evaluation circuit
board design is available from Analog Devices upon request.
V
TUNE pin, the total capacitor leakage must be less than 1.5 µA.
A typical MLCC 33 nF, 25 V loop filter capacitor has approxi-
mately 0.5 nA of leakage (Murata GRM155R71E333KA88).
U1
R1
C1
Y4
R2
GND D0
D1 LD
LDO
Y1
D1
R3
R4
R31
J3
J4
TP1
TP2
J3
SW1
D0
C5
C2
C4
EXT REF
C3
R10 R11
VTUNE
R5
R7
J4
R9
R8
R6
TP4
C7
R12
J3
C6
U1
C8
TP3
C9
C10
C27
C12
J5
C11
C14
R16
J6 C13
Y2
TP5
R17
J7
VCO
XTAL
GND
+3V
C16
Y3
R23
R19
C19
C15
C18
J8
C26
R20
C17
TP6
R22
C21
J8
U2
R24
EXT VCO
C25
C20
C22
R30
C23
C24
R25
GND
TP7
TP8
+5.5V
Figure 23. Evaluation PCB
Rev. C | Page 11 of 13
HMC1031
Data Sheet
C22
0.1µF
C20
0.1µF
R28
DEPOP
R27
DEPOP
R29
DEPOP
R26
DEPOP
3V
C10
TP3
DEPOP
U2
R25
0.2kΩ
3V
J6
DEPOP
1
2
TP7
C13
C16
1
12
+5.5V
V
VR1
VR2
VR3
VR4
0.1µF
DD
DEPOP
C23
C24
2
3
4
11
10
9
GND
EN
0.1µF 4.7µF
TP8
TP5
TP6
BAND
GAP
R30
10kΩ
XTAL
2
R18
0.2kΩ
J5
XTAL
1
C25
0.01µF
GND
REF
C12
0.1µF
C21
1µF
C19
DEPOP
C15
DEPOP
R22
HMC860LP3E
VCOVCC
DEPOP
C11
DEPOP
C26
0.1µF
TP4
VCOVCC
DEPOP
J7
R21
DEPOP
1
2
C18
0.1µF
C14
0.1µF
XTAL
Y4
VDD
3
4
FOUT
GND
1
C3
0.1µF
C5
DEPOP
VC
J3
TCXO
EXT_REF
2
122.88MHz
DEPOP
Y1
4
VDD
EN
GND
R6
51kΩ
C1
DEPOP
C4
0.1µF
3V
3
1
OUT
TP2
2
10.000MHz
DEPOP
C2
0.47µF
PLL
DEPOP
R11
DEPOP
LOOP FILTER
1
2
8
HMC1031
VCC
GND
R10
R8
J4
DEPOP
0Ω
7
REFIN
PFD/CP
CP
VTUNE
R7
C8
0.022µF
C6
DEPOP
R9
0Ω
22kΩ
3
4
6
VCOIN
LKDOP
D0
LKD
1/N
C9
R31
1.1kΩ
TP1
LD
0.27µF
3V
5
C7
0.0033µF
D1
DEPOP
SW1
3V
R2
0kΩ
R1
50Ω
CO-PLANAR
TRACE
C27
1
2
4
3
D1
R17
16Ω
R24
0kΩ
J8
0.0033µF
J9
1
LED
16Ω
2
4
6
8
EXT_VCO
R5
DEPOP
R12
51Ω
R16
DEPOP
3
5
7
9
D0
D1
LD
NC
R23
16Ω
TDA02H0SB1
VCOVCC
R19
0Ω
NC
NC
Y2
R3
R4
ATTENUATOR
3
4
1
NC 10
NC 12
100kΩ 100kΩ
FOUT VDD
VC
11 NC
C17
0.1µF
GND
2
SSW-106-01-T-D
DIVIDER CONTROL
D1
POWER-DOWN
DIVIDE BY 1
DIVIDE BY 5
DIVIDE BY 10
D0
0
HEADER TO USB BOARD
50.000MHz
DEPOP
0
0
1
1
Y3
2
R20
0Ω
1
6
1
0
1
VCXO
VCRTL VDD
EN
4
OUT
5
NC
NC
GND
3
Figure 24. Evaluation PCB Schematic
Table 5. Loop Filter Configuration
Configuration
f
REF (MHz)
fVCO (MHz)
Divider
Bandwidth (Hz)
C8
R7
C9
1
2
3
10
10
10
100
50
10
5
10
220 nF
100 nF
300 pF
7.5 kΩ
5.6 kΩ
100 kΩ
4.7 µF
1 µF
100
2000
50
5
3.9 nF
Rev. C | Page 12 of 13
Data Sheet
HMC1031
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.15
0.05
0.23
0.09
6°
0°
0.40
0.25
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 25. 8-Lead Mini Small Outline Package [MSOP]
(HRM-8-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
Branding2
H1031
HMC1031MS8E
−40°C to +85°C
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
HMC1031MS8E Evaluation PCB
HRM-8-1
XXXX
HMC1031MS8ETR
−40°C to +85°C
HRM-8-1
H1031
XXXX
EVAL01-HMC1031MS8E
1 E = RoHS Compliant Part.
2 XXXX is the four-digit lot number.
©2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13353-0-10/15(C)
Rev. C | Page 13 of 13
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