HMC424ACHIPS [ADI]
0.1 GHz to 13.0 GHz,0.5 dB LSB, 6-Bit, GaAs Digital Attenuator;
| 型号： | HMC424ACHIPS |
| 厂家： | 
ADI |
| 描述： | 0.1 GHz to 13.0 GHz,0.5 dB LSB, 6-Bit, GaAs Digital Attenuator |
| 文件： | 总11页 (文件大小：285K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0.1 GHz to 13.0 GHz,0.5 dB LSB, 6-Bit,
GaAs Digital Attenuator
Data Sheet
HMC424ACHIPS
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Attenuation range: 0.5 dB (LSB) steps to 31.5 dB
0.5 dB typical step error
VEE
HMC424ACHIPS
Low insertion loss: 2.8 dB typical at 4.0 GHz
High linearity at VEE = −5 V
RF1
RF2
Input P0.1dB: 25 dBm typical
Input IP3: 45 dBm typical
High RF input power handling: 25 dBm maximum
Low relative phase: 30° at 6.0 GHz
Single-supply operation: −3 V to −5 V
Die size: 1.390 mm × 0.770 mm × 0.102 mm
V6
V5
V4
V3
V2
V1
APPLICATIONS
Figure 1.
Cellular infrastructure
Microwave radios and very small aperture terminals (VSATs)
Test equipment and sensors
Intermediate frequency (IF) and RF designs
Military and space
GENERAL DESCRIPTION
The HMC424ACHIPS is a broadband, 6-bit, gallium arsenide
(GaAs), digital attenuator monolithic microwave integrated
circuit (MMIC) chip with a 31.5 dB attenuation control range in
0.5 dB steps.
The device allows a user to program the attenuation state via six
parallel control inputs toggled between 0 V and VEE.
The HMC424ACHIPS operates with a single negative supply
voltage from −3 V to −5 V, and requires an external driver to
interface with a CMOS/transistor to transistor logic (TTL)
interface.
The HMC424ACHIPS offers excellent attenuation accuracy of
(0.2 dB + 3% of attenuation state) and high input linearity over
the specified frequency range from 0.1 GHz to 13.0 GHz with a
typical insertion loss of ≤4.2 dB. The attenuator bit values are
0.5 dB (LSB), 1 dB, 2 dB, 4 dB, 8 dB, and 16 dB for a total
attenuation of 31.5 dB with a 0.5 dB of typical step error.
The HMC424ACHIPS comes in a RoHS compliant, 9-pad bare die.
Rev. B
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2020 Analog Devices, Inc. All rights reserved.
www.analog.com
HMC424ACHIPS
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Insertion Loss, Return Loss, State Error, Step Error, and
Relative Phase ................................................................................6
Input Power Compression and Third-Order Intercept............8
Theory of Operation .........................................................................9
Power Supply..................................................................................9
RF Input and Output ....................................................................9
Applications Information .............................................................. 10
Mounting and Bonding Techniques ........................................ 10
Assembly Diagram ..................................................................... 10
Outline Dimensions....................................................................... 11
Ordering Guide .......................................................................... 11
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Interface Schematics..................................................................... 5
Typical Performance Characteristics ............................................. 6
REVISION HISTORY
3/2020—Rev. 01.1115 to Rev. B
Deleted Handling Precautions Section, Mounting Section, and
Wire Bonding Section.......................................................................7
Added Input Power Compression and Third-Order Intercept
Section, Figure 18 to Figure 20, and Figure 22..............................8
Changes to Figure 17 and Figure 21 ...............................................8
Added Theory of Operation Section, Power Supply Section, and
RF Input and Output Section...........................................................9
Changes to Figure 23.........................................................................9
Added Applications Information Section ................................... 10
Changed Mounting & Bonding Techniques for Millimeterwave
GaAs MMICs Section to Mounting and Bonding Techniques
Section.............................................................................................. 10
Changes to Mounting and Bonding Techniques Section,
This Hittite Microwave Products data sheet has been reformatted to
meet the styles and standards of Analog Devices, Inc.
Changes to Title, Features Section, Applications Section, and
General Description Section........................................................... 1
Changes to Table 1 ............................................................................ 3
Added Table 2, Figure 2, Thermal Resistance Section, and
Table 3; Renumbered Sequentially................................................. 4
Changes to Table 2 ............................................................................ 4
Deleted Bias Voltage & Current Table and Control Voltage
Table; Renumbered Sequentially .................................................... 5
Added Figure 3, Table 4, and Figure 4 ........................................... 5
Changes to Figure 5.......................................................................... 5
Added Insertion Loss, Return Loss, State Error, Step Error, and
Relative Phase Section, Figure 8, Figure 9, and Figure 12........... 6
Changes to Figure 7, Figure 10, and Figure 11 ............................. 6
Added Figure 13, Figure 14, and Figure 16................................... 7
Changes to Figure 15........................................................................ 7
Figure 24, and Figure 25................................................................ 10
Updated Outline Dimensions....................................................... 11
Changes to Ordering Guide.......................................................... 11
Rev. B | Page 2 of 11
Data Sheet
HMC424ACHIPS
SPECIFICATIONS
Supply voltage (VEE) = -3 V to -5 V, control input voltage (VCTL) = 0 V or VEE, TCASE = 25°C, 50 Ω system, unless otherwise noted.
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min
Typ Max
Unit
GHz
dB
dB
dB
FREQUENCY RANGE
INSERTION LOSS
0.1
13.0
IL
0.1 GHz to 4.0 GHz
4.0 GHz to 8.0 GHz
8.0 GHz to 13.0 GHz
0.1 GHz to 13.0 GHz
Between minimum and
maximum attenuation states
Between any successive
attenuation states
Between any successive
attenuation states
2.8
3.4
4.2
3.3
4.0
4.6
ATTENUATION
Range
31.5
0.5
dB
dB
dB
Step Size
Step Error
State Error
0.5
All attenuation states,
referenced to insertion loss state
0.1 GHz to 8.0 GHz
8.0 GHz to 13.0 GHz
−(0.2 + 3% of
attenuation state)
−(0.2 + 4% of
attenuation state)
+(0.2 + 3% of
attenuation state)
+(0.2 + 4% of
attenuation state)
dB
dB
dB
RETURN LOSS (RF1 AND RF2)
RELATIVE PHASE
All attenuation states,
0.1 GHz to 13.0 GHz
12
Between minimum and
maximum attenuation states
0.1 GHz to 6.0 GHz
6.0 GHz to 13.0 GHz
30
70
Degrees
Degrees
SWITCHING CHARACTERISTICS
Rise and Fall Time
On and Off Time
Between all attenuation states
10% to 90% of RF output
50% VCTL to 90% of RF output
tRISE, tFALL
tON, tOFF
30
50
ns
ns
INPUT LINEARITY1
All attenuation states,
500 MHz to 6.0 GHz
0.1 dB Compression
Third-Order Intercept
P0.1dB
IP3
VEE = −3 V
VEE = −5 V
VEE = −5 V, 10 dBm per tone,
1 MHz spacing
23
25
45
dBm
dBm
dBm
VEE = −3 V, 10 dBm per tone,
1 MHz spacing
35
2
dBm
mA
SUPPLY CURRENT
DIGITAL CONTROL INPUTS
Voltage
IDD
VEE = −3 V to −5 V
V1 to V6
5
Low
VINL
VINH
VEE = −3 V
VEE = −5 V
VEE = −3 V
VEE = −5 V
−1.0
−3.0
−3.0
−5.0
0
0
−2.2
−4.2
V
V
V
V
High
Current
Low
High
VEE = −3 V to −5 V
IINL
IINH
35
1
μA
μA
1 Input linearity performance degrades at frequencies less than 250 MHz; see Figure 17, Figure 21, and Figure 22.
Rev. B | Page 3 of 11
HMC424ACHIPS
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Parameter
Rating
Supply Voltage, VEE
Digital Control Input Voltage
RF Input Power1 (All Attenuation States,
f = 0.8 to 13.0 GHz, TCASE = 85°C,
VEE = −3 V to −5 V)
Continuous Power Dissipation, PDISS
(TCASE = 85°C)
Temperature
Junction, TJ
Storage
−7 V
VEE – 0.5 V
25 dBm
θ
JC is the junction to case thermal resistance.
Table 3. Thermal Resistance
Package Type
0.56 W
θJC
Unit
C-9-21
330
°C/W
1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board with nine thermal vias. See JEDEC JESD51.
150°C
−65°C to +150°C
250 V (Class 1A)
ESD CAUTION
ESD Sensitivity, Human Body Model
(HBM)
1 For power derating at frequencies less than 800 MHz, see Figure 2.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any one
time.
0
V
V
= –5V
= –3V
EE
EE
–2
–4
–6
–8
–10
–12
–14
0.01
0.10
1.00
FREQUENCY (GHz)
Figure 2. Power Derating at Frequencies Less than 0.8 GHz
Rev. B | Page 4 of 11
Data Sheet
HMC424ACHIPS
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
2
HMC424ACHIPS
TOP VIEW
(Not to Scale)
1
3
RF2
RF1
9
8
7
6
5
4
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pad No. Mnemonic Description
1
RF1
Attenuator RF Input. This pin is dc-coupled and ac matched to 50 Ω. An external dc blocking capacitor is required if
the RF line potential is not equal to 0 V.
2
3
VEE
RF2
Power Supply.
Attenuator RF Output. This pin is dc-coupled and ac matched to 50 Ω. An external dc blocking capacitor is
required if the RF line potential is not equal to 0 V.
4 to 9
V1 to V6
Parallel Control Voltage Inputs. These pins select the required attenuation (see Table 5). There is an internal pull-
down resistor on these pins to VEE.
INTERFACE SCHEMATICS
VEE
3pF
2kΩ
RF1, RF2
Figure 4. RF1 and RF2 Interface Schematic
Figure 6. VEE Interface Schematic
100kΩ
V1 TO V6
VEE
Figure 5. V1 to V6 Interface Schematic
Rev. B | Page 5 of 11
HMC424ACHIPS
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
INSERTION LOSS, RETURN LOSS, STATE ERROR, STEP ERROR, AND RELATIVE PHASE
0
0
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
–5
–1
–10
–2
–3
–15
–20
–4
–5
–6
0.5dB
4.0dB
31.5dB
1.0dB
8.0dB
2.0dB
16.0dB
–25
–30
–35
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 7. Insertion Loss vs. Frequency over Temperature
Figure 10. Normalized Attenuation vs. Frequency over Major Attenuation
States
0
–5
0
–10
–20
0dB
0.5dB
2.0dB
8.0dB
31.5dB
1.0dB
4.0dB
16.0dB
–10
–15
–20
–25
–30
–40
–30
–35
–40
–45
–50
–50
0dB
0.5dB
2.0dB
8.0dB
31.5dB
1.0dB
4.0dB
16.0dB
–60
–70
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 8. Input Return Loss vs. Frequency over Major Attenuation States
Figure 11. Output Return Loss vs. Frequency over Major Attenuation States
2.0
2.0
0.1MHz
4.0GHz
8.0GHz
1.5
1.0
0.5
13.0GHz
1.5
1.0
0.5
0
0
–0.5
–1.0
0.5dB
2.0dB
8.0dB
31.5dB
1.0dB
4.0dB
16.0dB
–1.5
–2.0
–0.5
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
ATTENUATION STATE (dB)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
FREQUENCY (GHz)
Figure 9. State Error vs. Attenuation State over Frequency
Figure 12. State Error vs. Frequency over Major Attenuation States
Rev. B | Page 6 of 11
Data Sheet
HMC424ACHIPS
1.0
2.0
0.1MHz
0.5dB
2.0dB
8.0dB
31.5dB
1.0dB
4.0dB
16.0dB
4.0GHz
8.0GHz
13.0GHz
0.8
0.6
1.5
1.0
0.5
0.4
0.2
0
0
–0.5
–1.0
–1.5
–2.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
ATTENUATION STATE (dB)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
FREQUENCY (GHz)
Figure 13. Step Error vs. Attenuation State over Frequency
Figure 15. Step Error vs. Frequency over Major Attenuation States
70
80
0.1MHz
4.0GHz
8.0GHz
13.0GHz
0.5dB
2.0dB
8.0dB
31.5dB
1.0dB
4.0dB
16.0dB
70
60
50
40
30
20
10
60
50
40
30
20
10
0
0
–10
–10
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
ATTENUATION STATE (dB)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
FREQUENCY (GHz)
Figure 14. Relative Phase vs. Attenuation State over Frequency
Figure 16. Relative Phase vs. Frequency over Major Attenuation States
Rev. B | Page 7 of 11
HMC424ACHIPS
Data Sheet
INPUT POWER COMPRESSION AND THIRD-ORDER INTERCEPT
30
50
45
40
25
20
15
10
5
35
30
25
20
15
10
5
V
V
= –5V
= –3V
V
V
= –5V
= –3V
EE
EE
EE
EE
0
0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 17. Input P0.1dB vs. Frequency at Minimum Attenuation State over
Figure 20. Input IP3 vs. Frequency at Minimum Attenuation State over
EE = −5 V and VEE = −3 V
VEE = −5 V and VEE = −3 V
V
30
60
25
20
50
40
15
10
5
30
20
10
0
0dB
1.0dB
4.0dB
16.0dB
0.5dB
2.0dB
8.0dB
31.5dB
0.5dB
1.0dB
4.0dB
16.0dB
IL
2.0dB
8.0dB
31.5dB
0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0
2
4
6
8
10
12
14
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 18. Input P0.1dB vs. Frequency over Major Attenuation States,
EE = −5 V
Figure 21. Input IP3 vs. Frequency over Major Attenuation States,
V
VEE = −5 V
30
60
25
20
50
40
15
10
5
30
20
0dB
0.5dB
2.0dB
8.0dB
31.5dB
0.5dB
2.0dB
8.0dB
31.5dB
1.0dB
4.0dB
16.0dB
IL
10
0
1.0dB
4.0dB
16.0dB
0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0
2
4
6
8
10
12
14
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 19. Input P0.1dB vs. Frequency over Major Attenuation States,
EE = −3 V
Figure 22. Input IP3 vs. Frequency over Major Attenuation States,
EE = −3 V
V
V
Rev. B | Page 8 of 11
Data Sheet
HMC424ACHIPS
THEORY OF OPERATION
The HMC424ACHIPS incorporates a 6-bit attenuator die that
offers an attenuation range of 31.5 dB in 0.5 dB steps. The
attenuation state is changed by the parallel control voltage
inputs (V1 to V6) directly (see Table 5).
RF INPUT AND OUTPUT
The attenuator in the HMC424ACHIPS is bidirectional. The
RF1 and RF2 pins are interchangeable as the RF input and
output ports. The attenuator is internally matched to 50 Ω at
both the input and the output. Therefore, no external matching
components are required.
The HMC424ACHIPS allows the user to program the
attenuation state via six parallel control inputs toggled between
0 V and VEE. When interfacing with a TTL/CMOS interface, an
external level shifter is required. An example simple driver
using standard logic ICs provides fast switching while using
minimum dc current. The series resistance is recommended to
suppress unwanted RF signals at the input of the V1 to V6
control lines.
The RF input and output pins of the HMC424ACHIPS are
internally dc biased to 0 V. T herefore, they require external dc
blocking capacitors if the RF line potential is not equal to 0 V.
Select the value of these dc blocking capacitors based on the
minimum operating frequency. Use larger value capacitors to
extend the operation to lower frequencies.
POWER SUPPLY
V
ZT
= 5.1V
Z
I
= 50µA
COMPENSATED
DEVICES
The HMC424ACHIPS requires a single dc voltage applied to
the VEE pin. The ideal power-up sequence is as follows:
CD4689
V
CC
TO GaAs IC
TTL
OR
CMOS
100Ω
74HCT04 (TTL)
ATTENUATOR
CONTROL INPUTS
V1 TO V6
1. Connect the ground reference.
GND
10kΩ
2. Apply a supply voltage to the VEE pin.
3. Power up the digital control inputs. The relative order of
the digital control inputs is not important.
4. Apply an RF input signal to RF1.
OR 74HC04 (CMOS)
–5V dc
NOTE
CD4689 IS A ZENER DIODE. V IS THE ZENER VOLTAGE, AND I
Z
ZT
IS THE ZENER TEST CURRENT.
The power-down sequence is the reverse of the power-up
sequence.
Figure 23. Suggested Driver Circuit
Table 5. V1 to V6 Truth Table
Control Voltage Input
V1 (16 dB)
Low
V2 (8 dB)
Low
V3 (4 dB)
Low
V4 (2 dB)
Low
V5 (1 dB)
Low
V6 (0.5 dB)
Low
Attenuation State, RF1 to RF2
Reference insertion loss
Low
Low
Low
Low
Low
High
High
Low
Low
Low
Low
High
Low
High
Low
Low
Low
High
Low
Low
Low
High
Low
Low
Low
High
Low
Low
Low
High
Low
Low
Low
Low
0.5 dB
1 dB
2 dB
4 dB
8 dB
Low
High
Low
High
Low
High
Low
High
16 dB
31.5 dB
1 Any combination of the control voltage input states shown in Table 5 provides an attenuation equal to the sum of the bits selected.
Rev. B | Page 9 of 11
HMC424ACHIPS
Data Sheet
APPLICATIONS INFORMATION
(4 mil) thick die to a 0.150 mm (6 mil) thick molybdenum heat
spreader (moly tab), which is then attached to the ground plane
(see Figure 25).
MOUNTING AND BONDING TECHNIQUES
The HMC424ACHIPS is back metallized and must be attached
directly to the ground plane with gold tin (AuSn) eutectic
preforms or with electrically conductive epoxy.
0.102mm (0.004") THICK GaAs MMIC
RIBBON BOND
0.076mm
(0.003")
The die thickness is 0.102 mm (4 mil). The 50 Ω microstrip
transmission lines on 0.127 mm (5 mil) thick alumina thin film
substrates are recommended for bringing RF to and from the
HMC424ACHIPS (see Figure 24).
0.102mm (0.004") THICK GaAs MMIC
RF GROUND PLANE
0.150mm
RIBBON BOND
0.254mm (0.010") THICK ALUMINA
THIN FILM SUBSTRATE
(0.006”) THICK
MOLY TAB
0.076mm
(0.003")
Figure 25. Bonding RF Pads to 10 mil Substrate
Microstrip substrates are placed as close to the
RF GROUND PLANE
HMC424ACHIPS as possible to minimize bond length. Typical
die to substrate spacing is 0.076 mm (3 mil).
0.127mm (0.005") THICK ALUMINA
THIN FILM SUBSTRATE
RF bonds made with 3 mil × 5 mil ribbon are recommended.
DC bonds made with 1 mil diameter wire are recommended.
All bonds must be as short as possible.
Figure 24. Bonding RF Pads to 5 mil Substrate
When using 0.254 mm (10 mil) thick alumina thin film substrates,
the HMC424ACHIPS must be raised 0.150 mm (6 mil) so that the
surface of the HMC424ACHIPS is coplanar with the surface of the
substrate. One way to accomplish this is by attaching the 0.102 mm
ASSEMBLY DIAGRAM
An assembly diagram of the HMC424ACHIPS is shown in
Figure 26.
3mm
NOMINAL
GAP
50Ω
TRANSMISSION
TO –5V SUPPLY
LINE
RF AND DC BONDS
1mm GOLD WIRE
Figure 26. Assembly Diagram
Rev. B | Page 10 of 11
Data Sheet
HMC424ACHIPS
OUTLINE DIMENSIONS
1.390
0.102
0.437
0.788
0.082
0.043
2
0.212
1
3
0.770
0.212
0.227
0.358
9
8
7
6
5
4
0.082
TOP VIEW
(CIRCUIT SIDE)
SIDE VIEW
0.217
0.157
0.170
0.170
0.170
0.170
0.170
Figure 27. 9-Pad Bare Die [CHIP]
(C-9-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
Marking Code2
H424A
HMC424A
−40°C to +85°C
9-Pad Bare Die [CHIP]
C-9-2
XXXX
HMC424A-SX
−40°C to +85°C
9-Pad Bare Die [CHIP]
C-9-2
H424A
XXXX
1 All models are RoHS compliant.
2 XXXX is the 4-digit lot number.
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13970-3/20(B)
Rev. B | Page 11 of 11
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