HMC470A [ADI]
0.1 GHz to 3 GHz,1 dB LSB, 5-Bit, GaAs Digital Attenuator;
| 型号： | HMC470A |
| 厂家： | 
ADI |
| 描述： | 0.1 GHz to 3 GHz,1 dB LSB, 5-Bit, GaAs Digital Attenuator |
| 文件： | 总11页 (文件大小：373K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0.1 GHz to 3 GHz,1 dB LSB, 5-Bit,
GaAs Digital Attenuator
Data Sheet
HMC470A
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Attenuation range: 1 dB LSB steps to 31 dB
Insertion loss: 1.7 dB typical at 3 GHz
Excellent attenuation accuracy: 0.3 dB typical
High Input linearity
0.1dB compression (P0.1dB): 27 dBm typical
Third-order intercept (IP3): 48 dBm typical
High power handling: 27 dBm
VDD
RF1
1
2
3
4
12 V1
11 RF2
Low phase shift: 27° at 3 GHz
10
9
NIC
NIC
Single-supply operation: 3 V to 5 V
CMOS-/TTL-compatible parallel control
16-lead, 3 mm × 3 mm LFCSP package
ACG1
ACG6
HMC470A
APPLICATIONS
PACKAGE
BASE
Cellular infrastructure
Microwave radios and very small aperture terminals (VSATs)
Test equipment and sensors
GND
Figure 1.
IF and RF designs
GENERAL DESCRIPTION
The HMC470A is a 5-bit digital attenuator with a 31 dB
attenuation control range in 1 dB steps.
The HMC470A operates with a single positive supply voltage
from 3 V to 5 V and provides CMOS-/TTL-compatible parallel
control interface by incorporating an on-chip driver. The
HMC470A comes in a RoHS compliant, compact, 3 mm × 3 mm
LFCSP package.
The HMC470A offers excellent attenuation accuracy and high
input linearity over the specified frequency range from 100 MHz to
3 GHz. However, this digital attenuator features ACG pins for
external ac grounding capacitors to extend the operation below
100 MHz.
Rev. A
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2017 Analog Devices, Inc. All rights reserved.
www.analog.com
HMC470A
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Insertion Loss, Return Loss, State Error, Step Error, and
Relative Phase ................................................................................6
Input Power Compression and Third-Order Intercept............8
Theory of Operation .........................................................................9
Power Supply..................................................................................9
RF Input and Output ....................................................................9
ACGx Pins......................................................................................9
Applications Information .............................................................. 10
Evaluation Board ........................................................................ 10
Outline Dimensions ....................................................................... 11
Ordering Guide .......................................................................... 11
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Interface Schematics..................................................................... 5
Typical Performance Characteristics ............................................. 6
REVISION HISTORY
9/2017—Rev. 01.0716 to Rev. A
This Hittite Microwave Products data sheet has been reformatted to
meet the styles and standards of Analog Devices, Inc.
Change to Product Title................................................................... 1
Updated Outline Dimensions....................................................... 11
Rev. A | Page 2 of 11
Data Sheet
HMC470A
SPECIFICATIONS
VDD = 3 V to 5 V, VCTL = 0 V or VDD, TCASE = 25°C, 50 Ω system, unless otherwise noted.
Table 1.
Parameter
Symbol Test Conditions/Comments
Min
Typ
Max
3.0
Unit
GHz
dB
dB
dB
FREQUENCY RANGE
INSERTION LOSS
0.1
0.1 GHz to 1.5 GHz
1.5 GHz to 2.3 GHz
2.3 GHz to 3.0 GHz
1.3
1.5
1.7
1.6
1.8
2.0
ATTENUATION
Range
Between minimum and
maximum attenuation states,
0.1 GHz to 3.0 GHz
Between any successive
attenuation states, 0.1 GHz to
3.0 GHz
Between any successive
attenuation states, 0.1 GHz to
33 GHz
Referenced to insertion loss
state
31
dB
dB
dB
Step Size
Step Error
State Error
1
< 0.2
All attenuation states, 0.1 GHz to −(0.3 + 2% of
+(0.3 + 2% of
attenuation
state)
+(0.3 + 3% of
attenuation
state)
+(0.3 + 6% of
attenuation
state)
dB
dB
dB
dB
2.3 GHz
attenuation
state)
1 dB to 15 dB attenuation states, −(0.3 + 3% of
2.3 GHz to 3.0 GHz
attenuation
state)
16 dB to 31 dB attenuation
states, 2.3 GHz to 3.0 GHz
−(0.3 + 6% of
attenuation
state)
RETURN LOSS
RF1 and RF2 pins, all attenuation
states, 0.1 GHz to 3.0 GHz
14
RELATIVE PHASE
Between minimum and
maximum attenuation states
0.1 GHz to 1.5 GHz
1.5 GHz to 3.0 GHz
12
27
Degrees
Degrees
SWITCHING CHARACTERISTICS
Rise and Fall Time
On and Off Time
Between all attenuation states
tRISE, tFALL 10% to 90% of RF output
50
70
ns
ns
tON, tOFF
50% VCTL to 90% of RF output
INPUT LINEARITY1
All attenuation states, 250 MHz
to 3.0 GHz
0.1 dB Compression
P0.1dB
VDD = 3 V
VDD = 5 V
10 dBm per tone, 1 MHz spacing
25
27
50
1.7
dBm
dBm
dBm
mA
Third-Order Intercept
IP3
IDD
SUPPLY CURRENT
DIGITAL CONTROL INPUTS
V1 to V5 pins
Voltage
Low
High
VINL
VINH
0
2.0
0.8
VDD
V
V
Current
Low
High
IINL
IINH
1
40
µA
µA
1 Input linearity performance degrades at frequencies less than 250 MHz; see Figure 16 to Figure 19.
Rev. A | Page 3 of 11
HMC470A
Data Sheet
ABSOLUTE MAXIMUM RATINGS
1
0
Table 2.
Parameter
Rating
Supply Voltage
7 V
Digital Control Input Voltage
RF Input Power1 (All Attenuation States,
f = 250 MHz to 3 GHz, TCASE = 85°C)
VDD = 3 V
VDD = 5 V
Continuous Power Dissipation, PDISS
(TCASE = 85°C)
Temperature
Junction, TJ
Storage
Reflow2 ((Moisture Sensitivity Level 3
(MSL3) Rating)
−1 V to VDD +1 V
–1
–2
–3
–4
–5
25 dBm
27 dBm
0.5 W
150°C
−65°C to +150°C
260°C
0.1
1
FREQUENCY (GHz)
Figure 2. Power Derating at Frequencies Less Than 250 MHz
ESD Sensitivity
Human Body Model (HBM)
THERMAL RESISTANCE
250 V (Class 1A)
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
1 For power derating at frequencies less than 250 MHz, see Figure 2.
2 See the Ordering Guide for more information.
θJC is the junction to case thermal resistance.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 3. Thermal Resistance
Package Type
HCP-16-11
θJC
1302
Unit
°C/W
1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board with five thermal vias. See JEDEC JESD51.
2 The device is set to maximum attenuation state.
Only one absolute maximum rating can be applied at any one time.
ESD CAUTION
Rev. A | Page 4 of 11
Data Sheet
HMC470A
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD
RF1
1
2
3
4
12 V1
11 RF2
HMC470A
TOP VIEW
10
9
NIC
NIC
(Not to Scale)
ACG1
ACG6
NOTES
1. NIC = THESE PINS ARE NOT INTERNALLY CONNECTED;
HOWEVER, ALL DATA SHOWN HEREIN WAS
MEASURED WHEN THESE PINS CONNECTED TO RF/DC
GROUND OF EVALUATION BOARD.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE
CONNECTED TO GROUND FOR PROPER OPERATION.
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
VDD
RF1
Power Supply.
This pin can be used as RF input or output of attenuator. This pin is dc-coupled to VDD and ac matched to
50 Ω. An external dc blocking capacitor is required. Select the capacitor value for the lowest frequency of
operation.
3, 10
NIC
Not Internally Connected. These pins are not internally connected; however, all data shown herein was
measured when these pins connected to RF/DC ground of evaluation board.
4 to 9
ACG1 to ACG6
AC Grounding Capacitor Pins. These pins can be left no connected when operating above 700 MHz. For
frequencies less than 700 MHz, connect capacitors larger than 100 pF as close to the ACGx pins as
possible. Select the capacitor value for the lowest frequency of operation.
11
RF2
This pin can be used as RF input or output of attenuator. This pin is dc-coupled to VDD V and ac matched
to 50 Ω. An external dc blocking capacitor is required. Select the capacitor value for the lowest frequency
of operation.
12 to 16
V1 to V5
EPAD
Parallel Control Voltage Inputs. These pins select the required attenuation (see Table 5).
Exposed Pad. The exposed pad must be connected to ground for proper operation.
INTERFACE SCHEMATICS
VDD
VDD
RF1,
RF2
1.5kΩ
V1 TO V5
50kΩ
Figure 5. Digital Control Input Interface
Figure 4. RF1, RF2 Interface Schematic
Rev. A | Page 5 of 11
HMC470A
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
INSERTION LOSS, RETURN LOSS, STATE ERROR, STEP ERROR, AND RELATIVE PHASE
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
0
+85°C
+25°C
–40°C
–5
–10
–15
–20
–25
–30
–35
0dB
1dB
2dB
4dB
8dB
16dB
31dB
0
1
2
3
4
0
1
2
3
4
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 6. Insertion Loss vs. Frequency over Temperature
Figure 9. Normalized Attenuation vs. Frequency over Major Attenuation
States
0
0
0dB
1dB
2dB
4dB
8dB
16dB
31dB
0dB
1dB
–5
–10
–15
–20
–25
–30
–35
–40
2dB
–5
–10
–15
–20
–25
–30
–35
–40
4dB
8dB
16dB
31dB
0
1
2
3
4
0
1
2
3
4
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 7. RF1 Return Loss vs. Frequency over Major Attenuation States
Figure 10. RF2 Return Loss vs. Frequency over Major Attenuation States
1.0
2.0
0.1GHz
0dB
0.5GHz
1.0GHz
2.0GHz
3.0GHz
0.8
0.6
1dB
1.5
1.0
2dB
4dB
8dB
16dB
31dB
0.4
0.5
0
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
–2.0
0
4
8
12
16
20
24
28
32
0
1
2
3
4
ATTENUATION STATE (dB)
FREQUENCY (GHz)
Figure 8. State Error vs. Attenuation State over Frequency
Figure 11. State Error vs. Frequency over Major Attenuation States
Rev. A | Page 6 of 11
Data Sheet
HMC470A
1.0
1.0
0.8
0dB
1dB
2dB
4dB
8dB
16dB
31dB
0.1GHz
0.5GHz
1.0GHz
2.0GHz
3.0GHz
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
4
8
12
16
20
24
28
32
0
1
2
3
4
ATTENUATION STATE (dB)
FREQUENCY (GHz)
Figure 12. Step Error vs. Attenuation State over Frequency
Figure 14. Step Error vs. Frequency over Major Attenuation States
40
40
0dB
1dB
2dB
0.1GHz
0.5GHz
1.0GHz
2.0GHz
3.0GHz
30
20
30
20
4dB
8dB
16dB
31dB
10
10
0
0
–10
–20
–10
–20
0
4
8
12
16
20
24
28
32
0
1
2
3
4
ATTENUATION STATE (dB)
FREQUENCY (GHz)
Figure 15. Relative Phase vs. Frequency over Major Attenuation States
Figure 13. Relative Phase vs. Attenuation State over Frequency
Rev. A | Page 7 of 11
HMC470A
Data Sheet
INPUT POWER COMPRESSION AND THIRD-ORDER INTERCEPT
36
36
32
28
24
20
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
32
28
24
20
0
1
2
3
4
0
1
2
3
4
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 16. Input P0.1dB vs. Frequency at Minimum Attenuation State over
Temperature, VDD = 5 V
Figure 18. Input P0.1dB vs. Frequency at Minimum Attenuation State over
Temperature, VDD = 3 V
60
60
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
55
50
45
40
55
50
45
40
0
1
2
3
4
0
1
2
3
4
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 17. Input IP3 vs. Frequency at Minimum Attenuation State over
Temperature, VDD = 5 V
Figure 19. Input IP3 vs. Frequency at Minimum Attenuation State over
Temperature, VDD = 3 V
Rev. A | Page 8 of 11
Data Sheet
HMC470A
THEORY OF OPERATION
The HMC470A incorporates a 5-bit attenuator that offers an
attenuation range of 31 dB in 1 dB steps and a driver for
CMOS-/TTL-compatible parallel control of the 5-bit attenuator.
See Table 5 for the truth table.
RF INPUT AND OUTPUT
The HMC470A is bidirectional. The RF1 and RF2 pins are
internally matched to 50 Ω; therefore, they do not require
external matching components. These pins are dc-coupled to
VDD; therefore, dc blocking capacitors are required on RF lines.
Table 5. P4 to P0 Truth Table
Digital Control Input1
Attenuation
State (dB)
0 dB (reference)
1 dB
2 dB
4 dB
8 dB
16 dB
31 dB
ACGx PINS
V1
V2
V3
V4
V5
The HMC470A is a positive bias GaAs attenuator so it requires
floating capacitors between the attenuator bits and ground. The
HMC470A uses on-chip floating capacitors that are sufficient
for operation at frequencies greater than 700 MHz. The HMC470A
also features the ACGx pins to externally connect larger floating
capacitors. Select the value of external floating capacitors based
on the minimum operating frequency, whereas the ACGx pins
can be left open when operating above 700 MHz.
High
High
High
High
High
Low
Low
High
High
High
High
Low
High
Low
High
High
High
Low
High
High
Low
High
High
Low
High
High
High
Low
High
Low
High
High
High
High
Low
1 Any combination of the control voltage input states shown in Table 5
provides an attenuation equal to the sum of the bits selected.
POWER SUPPLY
The HMC470A requires a single supply voltage applied to the
VDD pin, and CMOS/TTL-compatible control voltages applied
to the V1 to V5 pins. The ideal power-up sequence is as follows:
1. Connect the ground reference.
2. Power up VDD and VSS. The relative order is not
important.
3. Apply the digital control inputs. The relative order of the
digital control inputs is not important.
4. Apply an RF input signal to RF1 or RF2.
The power-down sequence is the reverse of the power-up
sequence.
Rev. A | Page 9 of 11
HMC470A
Data Sheet
APPLICATIONS INFORMATION
thru calibration line connects J9 and J10; this transmission line
is used to measure the loss of the PCB over the environmental
conditions being evaluated.
EVALUATION BOARD
The HMC470A uses a 4-layer evaluation board. The copper
thickness is 0.5 oz (0.7 mil) on each layer. The top dielectric
material is 10 mil Rogers RO4350 for optimal high frequency
performance, whereas the middle and bottom dielectric materials
are FR-4 type materials to achieve an overall board thickness of
62 mil. RF and DC traces are routed on the top copper layer.
The bottom and middle layers are grounded planes that provide
a solid ground for the RF transmission lines. The RF transmission
lines are designed using a coplanar waveguide (CPWG) model
with a width of 16 mil and ground spacing of 13 mil to have a
characteristic impedance of 50 Ω. For enhanced RF and thermal
grounding, as many plated through vias as possible are arranged
around transmission lines and under the exposed pad of the
package.
The ACG pins are connected to ground through 330 pF
capacitors.
Figure 21 and Table 6 show the evaluation board schematic and
bill of materials, respectively.
J3
C3
1nF
VDD
RF1
V1
RF2
C1
1nF
C2
1nF
Figure 20 shows the top view of the populated HMC470A
Evaluation board, available from Analog Devices, Inc., upon
request (see the Ordering Guide).
J1
J2
U1
HMC470A
NIC
NIC
ACG1
ACG6
C7
330pF
C4
330pF
C5
330pF
C6
330pF
C8
1nF
C9
1nF
THRU CAL
J4
J6
Figure 21. Evaluation Board Schematic
Table 6. List of Materials for EVAL-HMC470A
Item
J1, J2
J3,
Description
PCB mount, SMA connector
2 × 6-pin header
Figure 20. Populated Evaluation Board -- Top View
J4, J5
C1, C2
C3
C4 to C7
C8, C9
U1
PCB mount, 2.9mm RF connector, do not insert
1 nF capacitor, 0402 package
1 nF capacitor, 0603package
330 pF capacitor, 0402 package
1 nF capacitor, 0402 package, do not insert
HMC470A Digital Attenuator
The evaluation board is grounded from the 2 × 6-pin header, J3.
The supply and digital control pins are also connected to the J3.
A 1 nF decoupling capacitor is placed on the supply trace to
filter high frequency noise.
The RF1 and RF2 ports are connected through 50 Ω transmission
lines to the SMA connectors, J1 and J2, respectively. The RF1
and RF2 ports are ac-coupled with external 330 pF capacitors. A
PCB
106978-4 Evaluation PCB
Rev. A | Page 10 of 11
Data Sheet
HMC470A
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
3.10
3.00 SQ
2.90
0.30
0.25
0.20
PIN 1
INDICATOR
PIN 1
NS
INDIC ATOR AREA OPTIO
(SEE DETAIL A)
13
16
0.50
BSC
12
1
EXPOSED
PAD
1.95
1.70 SQ
1.50
4
9
8
5
0.45
0.40
0.35
0.20 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.90
0.85
0.80
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT WITH JEDEC STANDARDS MO-220-VEED-4.
Figure 22. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.85 mm Package Height
(HCP-16-1)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
MSL
Package
Option
Model1
Rating2 Package Description
Branding3
H470A
XXXX
HMC470ALP3E
−40°C to +85°C MSL3
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
HCP-16-1
HMC470ALP3ETR
EV1HMC470ALP3
−40°C to +85°C MSL3
HCP-16-1
H470A
XXXX
1 All models are RoHS Compliant.
2 See the Absolute Maximum Ratings section.
3 XXXX is the 4-digit lot number.
©2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14806-0-9/17(A)
Rev. A | Page 11 of 11
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