HMC624ALP4E [ADI]
0.1 GHz to 6.0 GHz,0.5 dB LSB, 6-Bit, GaAs Digital Attenuator;
| 型号： | HMC624ALP4E |
| 厂家： | 
ADI |
| 描述： | 0.1 GHz to 6.0 GHz,0.5 dB LSB, 6-Bit, GaAs Digital Attenuator |
| 文件： | 总15页 (文件大小：578K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0.1 GHz to 6.0 GHz,0.5 dB LSB, 6-Bit,
GaAs Digital Attenuator
Data Sheet
HMC624A
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Attenuation range: 0.5 dB (LSB) steps to 31.5 dB
Low insertion loss: 1.6 dB at 3 GHz
Excellent attenuation accuracy
24
23
22
21
20
19
P/S
CLK
1
2
3
4
5
6
18 VDD
High linearity
PUP1
17
16
15
14
13
Input 0.1dB compression (P0.1dB): 33 dBm typical
Input third-order intercept (IP3): 55 dBm typical
High RF input power handling: 28 dBm
Low phase shift: 25° at 3 GHz
Single-supply operation: 3 V to 5 V
CMOS-/TTL-compatible control
SERIAL/
PARALLEL
INTERFACE
PUP2
SERIN
LE
SEROUT
GND
6-BIT/
DIGITAL
ATTENUATOR
GND
ATTOUT
ATTIN
24-lead, 4 mm × 4 mm LFCSP package
Pin compatible to the HMC1122
7
8
9
10
11
12
PACKAGE
BASE
APPLICATIONS
GND
Cellular infrastructure
Microwave radios and very small aperture terminals (VSATs)
Test equipment and sensors
Figure 1.
Intermediate frequency (IF) and radio frequency (RF) designs
GENERAL DESCRIPTION
The HMC624A is a 6-bit digital attenuator with a 31.5 dB
attenuation control range in 0.5 dB steps.
serial output port for cascading other serial controlled
components.
The HMC624A offers excellent attenuation accuracy and high
input linearity over the specified frequency range from 100 MHz
to 6.0 GHz. However, this digital attenuator features external ac
grounding capacitors to extend the operation below 100 MHz.
The HMC624A operates with a single positive supply voltage
from 3 V to 5 V, and provides a CMOS-/TTL-compatible
control interface.
The HMC624A comes in a RoHS compliant, compact, 4 mm ×
4 mm LFCSP package, and is pin compatible to the HMC1122
except for the ACGx pins.
The HMC624A is integrated with two dies: a CMOS driver and
a gallium arsenide (GaAs) RF attenuator. The CMOS driver
provides both serial and parallel control of the RF attenuator.
The device also features a user-selectable power-up state and a
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2017 Analog Devices, Inc. All rights reserved.
www.analog.com
HMC624A
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Input Power Compression and Third-Order Intercept............9
Theory of Operation ...................................................................... 11
Power Supply............................................................................... 11
Power-Up Interface .................................................................... 11
Serial or Parallel Mode Selection ............................................. 11
Serial Mode Interface................................................................. 11
Parallel Mode Interface.............................................................. 12
RF Input and Output ................................................................. 12
ACGx Pins................................................................................... 12
Applications Information .............................................................. 13
Evaluation Board ........................................................................ 13
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 15
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 4
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Interface Schematics..................................................................... 6
Typical Performance Characteristics ............................................. 7
Insertion Loss, Return Loss, State Error, Step Error, and
Relative Phase................................................................................ 7
REVISION HISTORY
9/2017—Rev. A to Rev. B
Changes to Figure 9, Figure 10, Figure 12, and Figure 13 ...........7
Deleted Application Circuit Figure.................................................8
Added Figure 14, Figure 15, and Figure 17....................................8
Changes to Figure 16 ........................................................................8
Added Figure 20 and Figure 23 .......................................................9
Changes to Figure 21 and Figure 22 ...............................................9
Added Figure 26 and Figure 29 .................................................... 10
Added Theory of Operation Section, Serial or Parallel Mode
Selection Section, Table 8, and Figure 30.................................... 11
Changes to Table 6, Power Supply Section, Power-Up Interface
Section, Table 7, Serial Mode Interface Section ......................... 11
Added RF Input and Output Section and AGCx Pins Section....... 12
Changes to Figure 31, Parallel Mode Interface Section, Direct
Parallel Mode Section, Latched Parallel Mode Section, and
Figure 32 .......................................................................................... 12
Added Applications Information Section ................................... 13
Changes to Evaluation Board Section.......................................... 13
Added Figure 34 ............................................................................. 14
Changes to Table 9.......................................................................... 14
Updated Outline Dimensions....................................................... 15
Changes to Ordering Guide.......................................................... 15
Changed CP-24-2 to CP-24-16.................................... Throughout
Changes to Table 3............................................................................ 5
Updated Outline Dimensions....................................................... 15
Changes to Ordering Guide .......................................................... 15
3/2017—Rev. 00.0912 to Rev. A
This Hittite Microwave Products data sheet has been reformatted to
meet the styles and standards of Analog Devices, Inc.
Changes to Title, Features Section, Applications Section, and
General Description Section........................................................... 1
Changes to Table 1............................................................................ 3
Added Table 2; Renumbered Sequentially .................................... 4
Changes to Table 3............................................................................ 5
Added Figure 2 and Thermal Resistance Section; Renumbered
Sequentially ....................................................................................... 5
Deleted Bias Voltage Table and Control Voltage Table;
Renumbered Sequentially................................................................ 5
Added Figure 3.................................................................................. 6
Changes to Table 5............................................................................ 6
Added Insertion Loss, Return Loss, State Error, and Relative
Phase Section..................................................................................... 7
Rev. B | Page 2 of 15
Data Sheet
HMC624A
SPECIFICATIONS
VDD = 3 V to 5 V, control input voltage (VCTL) = 0 V or VDD, TCASE = 25°C, 50 Ω system, unless otherwise noted.
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
6.0
Unit
GHz
dB
FREQUENCY RANGE
INSERTION LOSS
0.1
0.1 GHz to 3 GHz
3 GHz to 6.0 GHz
0.1 GHz to 6.0 GHz
Between minimum and maximum
attenuation states
Between any successive
attenuation states
Between any successive
attenuation states
1.6
2.3
2.4
3.8
dB
ATTENUATION
Range
31.5
0.5
dB
dB
dB
Step Size
Step Error
State Error
< 0.2
All attenuation states, referenced
to insertion loss state
0.1 GHz to 0.8 GHz
−(0.1 + 5% of
attenuation state)
+(0.1 + 5% of
attenuation state)
dB
0.8 GHz to 6.0 GHz
−(0.3 + 3% of
attenuation state)
+(0.3 + 3% of
attenuation state)
dB
dB
RETURN LOSS (ATTIN and ATTOUT)
RELATIVE PHASE
All attenuation states,
0.1 GHz to 6.0 GHz
15
Between minimum and maximum
attenuation states
100 MHz to 3 GHz
3 GHz to 6.0 GHz
25
50
Degrees
Degrees
SWITCHING CHARACTERISTICS
Rise and Fall Time
On and Off Time
Between all attenuation states
10% to 90% of RF output
50% VCTL to 90% of RF output
tRISE, tFALL
tON, tOFF
60
90
ns
ns
INPUT LINEARITY1
All attenuation states,
250 MHz to 6.0 GHz
0.1 dB Compression
Third-Order Intercept
P0.1dB
VDD = 3 V
VDD = 5 V
VDD = 3 V to 5 V, 10 dBm per tone,
1 MHz spacing
33
27
55
dBm
dBm
dBm
IP3
IDD
SUPPLY CURRENT
VDD = 3 V to 5 V
3
mA
DIGITAL CONTROL INPUTS
P/S, CLK, SERIN, LE, D0 to D5,
PUP1, and PUP2 pins
Voltage
Low
VINL
VINH
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
0
0
2
2
0.5
0.8
3
V
V
V
V
High
5
Current
VDD = 3 V to 5 V
Low
High
IINL
IINH
15
65
µA
µA
DIGITAL CONTROL OUTPUT
SEROUT
Voltage
Low
High
VOUTL
VOUTH
0
VDD
V
V
Current
Low
High
IOUTL
IOUTH
1
1
mA
mA
1 Input linearity performance degrades at frequencies less than 250 MHz; see Figure 18 to Figure 29.
Rev. B | Page 3 of 15
HMC624A
Data Sheet
TIMING SPECIFICATIONS
See Figure 31 and Figure 32 for the timing diagrams.
Table 2.
Parameter
Description
Min
70
15
Typ
Max
Unit
ns
ns
tSCK
tCS
Minimum serial period
Control setup time
tCH
tLN
Control hold time
LE setup time
20
ns
ns
15
tLEW
tLES
tCKN
tPH
Minimum LE pulse width
Minimum LE pulse spacing
Serial clock hold time from LE
Data hold time from LE
Data setup time to LE
10
630
0
10
2
ns
ns
ns
ns
tPS
ns
Rev. B | Page 4 of 15
Data Sheet
HMC624A
ABSOLUTE MAXIMUM RATINGS
2
0
Table 3.
Parameter
Rating
Supply Voltage
5.6 V
Digital Control Input Voltage
RF Input Power1 (All Attenuation States,
f = 250 MHz to 6.0 GHz, TCASE = 85°C)
VDD = 3 V
VDD = 5 V
Continuous Power Dissipation, PDISS
(TCASE = 85°C)
Temperature
Junction, TJ
Storage
Reflow2 ((Moisture Sensitivity Level 1
(MSL1) Rating)
−1 V to VDD + 1 V
0.56 W
–2
–4
–6
–8
–10
25 dBm
28 dBm
0.56 W
150°C
−65°C to +150°C
260°C
0.01
0.1
FREQUENCY (GHz)
1
Figure 2. Power Derating at Frequencies Less Than 250 MHz
ESD Sensitivity
Human Body Model (HBM)
THERMAL RESISTANCE
250 V (Class 1A)
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
1 For power derating at frequencies less than 250 MHz, see Figure 2.
2 See the Ordering Guide for more information.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
θ
JC is the junction to case thermal resistance.
Table 4. Thermal Resistance
Package Type
θJC
Unit
CP-24-161
116
°C/W
1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board with nine thermal vias. See JEDEC JESD51.
Only one absolute maximum rating can be applied at any one time.
ESD CAUTION
Rev. B | Page 5 of 15
HMC624A
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
24
23
22
21
20
19
P/S
CLK
1
2
3
4
5
6
18 VDD
PUP1
17
16
15
14
13
PUP2
SERIN
LE
HMC624A
TOP VIEW
SEROUT
GND
(Not to Scale)
GND
ATTOUT
ATTIN
7
8
9
10
11
12
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO GROUND FOR
PROPER OPERATION.
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
P/S
Parallel/Serial Mode Select. For parallel mode operation, set this pin to low. For serial mode operation, set
this pin to high.
2
CLK
Serial Interface Clock Input.
3
4
SERIN
LE
Serial Interface Data Input.
Latch Enable Input.
5, 14
6
GND
ATTIN
Ground. These pins must be connected to ground.
Attenuator RF Input. This pin can also be used as an output because the design is bidirectional. ATTIN is
dc-coupled and ac matched to 50 Ω. An external dc blocking capacitor is required.
7 to 12
13
ACG1 to ACG6
ATTOUT
AC Grounding Capacitor Pins. These pins can be left unconnected when operating above 700 MHz. For
frequencies less than 700 MHz, connect capacitors larger than 100 pF as close to the ACGx pins as
possible. Select the capacitor value for the lowest frequency of operation.
Attenuator RF Output. This pin can also be used as an input because the design is bidirectional. ATTOUT is
dc-coupled and ac matched to 50 Ω. An external dc blocking capacitor is required.
15
16, 17
18
SEROUT
PUP2, PUP1
VDD
Serial Interface Data Output. Serial input data is delayed by six clock cycles.
Power-Up State Selection Pins. These pins set the attenuation value at power-up (see Table 7).
Power Supply.
19 to 24
D5 to D0
Parallel Control Voltage Inputs. These pins select the required attenuation (see Table 6). There is no
internal pull-up or pull-down resistor on these pins; therefore, they must always be kept at a valid logic level
(VIH or VIL) and not be left floating.
EPAD
Exposed Pad. The exposed pad must be connected to ground for proper operation.
INTERFACE SCHEMATICS
ATTIN,
ATTOUT
ACG1 TO
ACG6
Figure 6. ACGx Pin Interface Schematic
Figure 4. ATTIN, ATTOUT Interface Schematic
VDD
VDD
VDD
VDD
P/S, LE, CLK, SERIN
PUP1, PUP2, D0 TO D5
SEROUT
Figure 7. SEROUT Pin Interface
Figure 5. Digital Control Input Interface
Rev. B | Page 6 of 15
Data Sheet
HMC624A
TYPICAL PERFORMANCE CHARACTERISTICS
INSERTION LOSS, RETURN LOSS, STATE ERROR, STEP ERROR, AND RELATIVE PHASE
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
0
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
–5
–10
–15
–20
–25
–30
–35
0dB
0.5dB
1dB
2dB
4dB
8dB
16dB
31.5dB
0
1
2
3
4
5
6
0
1
2
3
4
5
6
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 8. Insertion Loss vs. Frequency over Temperature
Figure 11. Normalized Attenuation vs. Frequency over Major Attenuation
States
0
0
–10
–20
–30
–10
–20
–30
–40
–50
0dB
0dB
0.5dB
1dB
0.5dB
1dB
–40
–50
2dB
2dB
4dB
4dB
8dB
8dB
16dB
31.5dB
16dB
31.5dB
0
1
2
3
4
5
6
0
1
2
3
4
5
6
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 9. Input Return Loss vs. Frequency over Major Attenuation States
Figure 12. Output Return Loss vs. Frequency over Major Attenuation States
1.0
0.8
0.6
0.4
0.2
0
2.0
0dB
0.5dB
1dB
1.5
1.0
2dB
4dB
8dB
16dB
31.5dB
0.5
0
–0.2
–0.5
–1.0
–1.5
–2.0
–0.4
0.1GHz
0.5GHz
1GHz
2GHz
–0.6
–0.8
4GHz
6GHz
20
ATTENUATION STATE (dB)
–1.0
0
4
8
12
16
24
28
32
0
1
2
3
4
5
6
FREQUENCY (GHz)
Figure 10. State Error vs. Attenuation State over Frequency
Figure 13. State Error vs. Frequency over Major Attenuation States
Rev. B | Page 7 of 15
HMC624A
Data Sheet
1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0dB
0.1GHz
0.5GHz
1GHz
2GHz
4GHz
0.5dB
1dB
2dB
4dB
8dB
16dB
31.5dB
6GHz
0
4
8
12
16
20
24
28
32
0
1
2
3
4
5
6
ATTENUATION STATE (dB)
FREQUENCY (GHz)
Figure 14. Step Error vs. Attenuation State over Frequency
Figure 16. Step Error vs. Frequency over Major Attenuation States
60
60
0dB
0.5dB
0.1GHz
0.5GHz
1GHz
2GHz
4GHz
1dB
50
40
50
40
2dB
4dB
8dB
16dB
31.5dB
6GHz
30
30
20
20
10
10
0
0
–10
–20
–10
–20
0
4
8
12
16
20
24
28
32
0
1
2
3
4
5
6
ATTENUATION STATE (dB)
FREQUENCY (GHz)
Figure 15. Relative Phase vs. Attenuation State over Frequency
Figure 17. Relative Phase vs. Frequency over Major Attenuation States
Rev. B | Page 8 of 15
Data Sheet
HMC624A
INPUT POWER COMPRESSION AND THIRD-ORDER INTERCEPT
36
36
33
30
27
24
21
18
15
33
30
27
24
21
18
15
T
T
T
= +85°C
= +25°C
= –40°C
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
A
A
A
0
1
2
3
4
5
6
0
1
2
3
4
5
6
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 18. Input P0.1dB vs. Frequency at Minimum Attenuation State over
Temperature, VDD = 5 V
Figure 21. Input P0.1dB vs. Frequency at Minimum Attenuation State over
Temperature, VDD = 3 V
36
33
30
27
24
21
36
33
30
27
24
21
18
15
T
T
T
= +85°C
= +25°C
= –40°C
18
15
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
A
A
A
0
0.1
0.2
0.3
0.4
0.5
0
0.1
0.2
0.3
0.4
0.5
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 19. Input P0.1dB vs. Frequency at Minimum Attenuation State over
Temperature, VDD = 5 V (Low Frequency Detail)
Figure 22. Input P0.1dB vs. Frequency at Minimum Attenuation State over
Temperature, VDD = 3 V (Low Frequency Detail)
36
33
30
27
24
36
33
30
27
24
0dB
0dB
21
21
0.5dB
0.5dB
1dB
2dB
1dB
2dB
4dB
4dB
18
15
18
15
8dB
8dB
16dB
31.5dB
16dB
31.5dB
0
1
2
3
4
5
6
0
1
2
3
4
5
6
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 20. Input P0.1dB vs. Frequency over Major Attenuation States,
DD = 5 V
Figure 23. Input P0.1dB vs. Frequency over Major Attenuation States,
DD = 3 V
V
V
Rev. B | Page 9 of 15
HMC624A
Data Sheet
70
70
60
50
40
30
60
50
40
T
T
T
= +85°C
= +25°C
= –40°C
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
A
A
A
30
0
1
2
3
4
5
6
0
1
2
3
4
5
6
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 24. Input IP3 vs. Frequency at Minimum Attenuation State over
Temperature, VDD = 5 V
Figure 27. Input IP3 vs. Frequency at Minimum Attenuation State over
Temperature, VDD = 3 V
70
60
50
40
70
60
50
40
T
T
T
= +85°C
= +25°C
= –40°C
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
A
A
A
30
30
0
0.1
0.2
0.3
0.4
0.5
0
0.1
0.2
0.3
0.4
0.5
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 25. Input IP3 vs. Frequency at Minimum Attenuation State over
Temperature, VDD = 5 V (Low Frequency Detail)
Figure 28. Input IP3 vs. Frequency at Minimum Attenuation State over
Temperature, VDD = 3 V (Low Frequency Detail)
70
70
60
60
50
50
0dB
0dB
0.5dB
0.5dB
40
40
1dB
1dB
2dB
2dB
4dB
4dB
8dB
8dB
16dB
16dB
31.5dB
31.5dB
30
30
0
1
2
3
4
5
6
0
1
2
3
4
5
6
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 26. Input IP3 vs. Frequency over Major Attenuation States,
DD = 5 V
Figure 29. Input IP3 vs. Frequency over Major Attenuation States,
DD = 3 V
V
V
Rev. B | Page 10 of 15
Data Sheet
HMC624A
THEORY OF OPERATION
The HMC624A incorporates a 6-bit attenuator die that offers an
attenuation range of 31.5 dB in 0.5 dB steps. A CMOS driver die
inside the HMC624A enables both serial and parallel mode
control of the 6-bit attenuator (see Figure 30 and Table 6).
device per the truth table shown in Table 7. The attenuator
latches in the desired power-up state approximately 200 ms after
power-up.
Table 7. PUPx Truth Table
Table 6. D5 to D0 Truth Table
Attenuation State
LE
PUP1
Low
High
Low
PUP2
Low
Low
High
High
Digital Control Input1
Attenuation
State (dB)
31.5 dB
24.0 dB
16.0 dB
0 dB (Reference)
Determined by D0 to D5
Low
Low
Low
Low
D5
D4
D3
D2
D1
D0
High High High High High High 0 (reference)
High High High High High Low 0.5
High High High High Low High 1.0
High High High Low High High 2.0
High High Low High High High 4.0
High Low High High High High 8.0
High High High High High 16.0
Low Low Low Low Low 31.5
High
High Don’t care
Don’t care
SERIAL OR PARALLEL MODE SELECTION
The HMC624A can be controlled in either serial or parallel
mode by setting the P/S pin to high or low, respectively (see
Table 8).
Low
Low
Table 8. Mode Selection
1 Any combination of the control voltage input states shown in Table 6
provides an attenuation equal to the sum of the bits selected.
P/S
Control Mode
Low
High
Parallel
Serial
POWER SUPPLY
The HMC624A requires a single dc voltage applied to the VDD
pin. The ideal power-up sequence is as follows:
SERIAL MODE INTERFACE
The HMC624A has a 3-wire serial peripheral interface (SPI):
serial data input (SERIN), clock (CLK), and latch enable (LE).
The serial control interface is activated when P/S is set to high.
1. Connect the ground reference.
2. Apply a supply voltage to the VDD pin.
3. Power up the digital control inputs. The relative order of
the digital control inputs is not important.
In serial mode, the 6-bit SERIN data is clocked MSB first on the
rising CLK edges into the shift register and then LE must be
toggled high to latch the new attenuation state into the device.
LE must be set to low to clock new 6-bit data into the shift
register because CLK is masked to prevent the attenuator value
from changing if LE is kept high (see Figure 31 and Table 2).
4. Apply an RF input signal to ATTIN or ATTOUT.
The power-down sequence is the reverse of the power-up
sequence.
POWER-UP INTERFACE
The HMC624A uses the PUP1 and PUP2 control voltage inputs
to set the attenuation value to a known value at power-up before
the initial control data word is provided in either serial or parallel
mode. When the attenuator powers up with LE set to low, the
state of PUP1 and PUP2 determines the power-up state of the
The HMC624A also features a serial data output pin, SEROUT,
that outputs serial input data delayed by six clock cycles to
control the cascaded attenuator using a single SPI bus.
D0
D1
D2
D3
D4
D5
SERIN
SEROUT
D Q
D Q
D Q
D Q
D Q
D Q
CLK
P/S
P/S SELECT
6-BIT LATCH
LE
RF
INPUT
RF
OUTPUT
0.5dB
1dB
2dB
4dB
8dB
16dB
Figure 30. Simplified Circuit Diagram
Rev. B | Page 11 of 15
HMC624A
Data Sheet
X
P/S
MSB
[FIRST IN]
LSB
[LAST IN]
tCS tCH
D[5:0]
NEXT WORD
SERIN
X
D5
D4
D3
D2
D1
D0
X
X
tLEW
tCKN
tLN
CLK
LE
tSCK
tLES
Figure 31. Serial Mode Timing Diagram
RF INPUT AND OUTPUT
PARALLEL MODE INTERFACE
The attenuator in the HMC624A is bidirectional; the ATTIN
and ATTOUT pins are interchangeable as the RF input and
output ports. The attenuator is internally matched to 50 Ω at
both the input and the output; therefore, no external matching
components are required.
The HMC624A has six digital control inputs, D0 (LSB) to D5
(MSB), to select the desired attenuation state in parallel mode, as
shown in Table 6. The parallel control interface is activated when
P/S is set to low.
There are two modes of parallel operation: direct parallel and
latched parallel.
The RF input and output pins of the HMC624A are internally
dc-biased to VDD; therefore, they require external dc blocking
capacitors. Select the value of these dc blocking capacitors based
on the minimum operating frequency; use larger value capacitors
to extend the operation to lower frequencies.
Direct Parallel Mode
The LE pin must be kept high. The attenuation state is changed
by the control voltage inputs (D0 to D5) directly. This mode is
ideal for manual control of the attenuator.
ACGx PINS
Latched Parallel Mode
The HMC624A is a positive bias GaAs attenuator; therefore, it
requires floating capacitors between the attenuator bits and
ground. The HMC624A uses on-chip floating capacitors that
are sufficient for operation greater than 700 MHz. The HMC624A
also features the ACGx pins to externally connect floating
capacitors larger than 100 pF. Select the value of the external
floating capacitors based on the minimum operating frequency,
whereas the ACGx pins can be left open when operating above
700 MHz.
The LE pin must be kept low when changing the control voltage
inputs (D0 to D5) to set the attenuation state. When the desired
state is set, LE must be toggled high to transfer the 6-bit data to
the bypass switches of the attenuator array, and then toggled
low to latch the change into the device until the next desired
attenuation change (see Figure 32 and Table 2).
P/S
D5 TO D0
LE
X
tPS
tPH
D[5:0]
PARALLEL
CONTROL
X
X
tLEW
Figure 32. Latched Parallel Mode Timing Diagram
Rev. B | Page 12 of 15
Data Sheet
HMC624A
APPLICATIONS INFORMATION
The evaluation board is grounded from the dc pin, J11. The dc
supply must be connected to the dc pin, J8, of the evaluation
board. A 1 nF decoupling capacitor is placed on the supply trace
to filter high frequency noise.
EVALUATION BOARD
The HMC624A uses a 4-layer evaluation board. The copper
thickness is 0.5 oz (0.7 mil) on each layer. The top dielectric
material is 10 mil Rogers RO4350 for optimal high frequency
performance, whereas the middle and bottom dielectric materials
are FR-4 type materials to achieve an overall board thickness of
62 mil. RF traces are routed on the top copper layer, and the
bottom layer is a grounded plane that provides a solid ground
for the RF transmission lines. The RF transmission lines are
designed using a coplanar waveguide (CPWG) model with a
width of 16 mil and ground spacing of 13 mil to have a characteris-
tic impedance of 50 Ω. For enhanced RF and thermal grounding,
as many plated through vias as possible are arranged around
transmission lines and under the exposed pad of the package.
The RF input and output ports (ATTIN and ATTOUT) are
connected through 50 Ω transmission lines to the SMA connect-
ors, J1 and J2, respectively. The ATTIN and ATTOUT ports are
ac-coupled with 330 pF capacitors. A thru calibration line is
used to estimate the loss of the PCB over the environmental
conditions being evaluated.
All the digital control pins are connected through digital signal
traces to the 2 × 9-pin header, J3. The HMC624A evaluation
board also uses two dual inline package (DIP), and four-position,
single-pole dual-throw (SPDT) switches for the manual control
of the device in direct parallel mode.
Figure 33 shows the top view of the populated HMC624A
evaluation board, available from Analog Devices, Inc., upon
request (see the Ordering Guide).
Figure 34 and Table 9 show the evaluation board schematic and
bill of materials, respectively.
Figure 33. Populated Evaluation Board—Top View
Rev. B | Page 13 of 15
HMC624A
Data Sheet
Figure 34. Evaluation Board Schematic
Table 9. Evaluation Board Bill of Materials
Component
Default Value
Not applicable
Not applicable
Not applicable
Do not insert
330 pF
1 nF
Do not insert
100 kΩ
Description
J1, J2
J3
SMA connector
2 × 9-pin header
DC pins
SMA connector
Capacitor, 0402 package
Capacitor, 0402 package
Capacitor, 0402 package
Resistor, 0402 package
SPDT four-position DIP switch
Digital attenuator, Analog Devices, Inc.
Evaluation PCB, Analog Devices
J8, J11
J9, J10
C1 to C6
C8
C9, C10
R1 to R14
SW1, SW2
U1
Not applicable
HMC624A
117210-2
PCB
Rev. B | Page 14 of 15
Data Sheet
HMC624A
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
4.10
4.00 SQ
3.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
24
19
18
1
0.50
BSC
2.85
2.70 SQ
2.55
EXPOSED
PAD
13
12
6
7
0.50
0.40
0.30
0.20 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.90
0.85
0.80
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-8.
Figure 35. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.85 mm Package Height
(CP-24-16)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
MSL
Package
Option
Model1
Rating2 Package Description
Branding3
H624A
XXXX
H624A
XXXX
HMC624ALP4E
−40°C to +85°C MSL1
24-Lead Lead Frame Chip Scale Package [LFCSP]
24-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
CP-24-16
HMC624ALP4ETR
−40°C to +85°C MSL1
CP-24-16
117212-HMC624ALP4
1 E = RoHS Compliant Part.
2 See the Absolute Maximum Ratings section.
3 XXXX is the 4-digit lot number.
©2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15353-0-9/17(B)
Rev. B | Page 15 of 15
相关型号：
©2020 ICPDF网 联系我们和版权申明