HMC7229 [ADI]
Point to point radios;
| 型号： | HMC7229 |
| 厂家： | 
ADI |
| 描述： | Point to point radios 射频 微波 |
| 文件： | 总16页 (文件大小：275K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
33 GHz to 40 GHz, GaAs, pHEMT, MMIC, 1 W
Power Amplifier with Power Detector
Data Sheet
HMC7229CHIPS
FEATURES
GENERAL DESCRIPTION
32 dBm PSAT with 22% PAE
P1dB POUT: 31.5 dBm
High OIP3: 39.5 dBm
High gain: 24.5 dB
The HMC7229CHIPS is a four-stage, gallium arsenide (GaAs),
pseudomorphic high electron mobility transfer (pHEMT),
monolithic microwave integrated circuit (MMIC), 1 W power
amplifier with an integrated temperature compensated on-chip
power detector, operating between 33 GHz and 40 GHz. The
HMC7229CHIPS provides a typical range of 23 dB to 24.5 dB of
gain and a range of 30 dBm to 32 dBm of saturated output power
(PSAT) with 12% to 22% (typical) power added efficiency (PAE)
range across a band of 33 GHz to 40 GHz from a 6 V supply. With
an excellent OIP3 with a range of 37 dBm to 39.5 dBm across a
band of 33 GHz to 40 GHz, the HMC7229CHIPS is ideal for linear
applications such as high capacity point to point or point to
multipoint radios or very small aperture terminal (VSAT)/satellite
communications (SATCOM) applications demanding 32 dBm of
efficient saturated output power. The radio frequency (RF) input/
output ports are internally matched and dc blocked for easy
integration into higher level assemblies.
50 Ω matched input/output
APPLICATIONS
Point to point radios
Point to multipoint Radio
VSAT and SATCOM
FUNCTIONAL BLOCK DIAGRAM
V
V
V
V
V
DD1
GG1
DD2
DD3
DD4
2
3
4
5
6
V
7
REF
HMC7229CHIPS
1
8
RFIN
RFOUT
V
9
DET
14
13
12
11
10
V
V
V
V
V
DD8
GG2
DD5
DD6
DD7
Figure 1.
Rev. 0
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Tel: 781.329.4700
Technical Support
©2016 Analog Devices, Inc. All rights reserved.
www.analog.com
HMC7229CHIPS
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................8
Theory of Operation ...................................................................... 12
Applications Information .............................................................. 13
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
33 GHz to 35 GHz Frequency Range......................................... 3
35 GHz to 37 GHz Frequency Range......................................... 3
37 GHz to 40 GHz Frequency Range......................................... 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Interface Schematics..................................................................... 7
Mounting and Bonding Techniques for Millimeter Wave
GaAs MMICs.............................................................................. 13
Handling Precautions ................................................................ 13
Mounting..................................................................................... 13
Biasing Procedures..................................................................... 13
Typical Application Circuit....................................................... 14
Assembly Diagram ..................................................................... 15
Outline Dimensions....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
6/2016—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
Data Sheet
HMC7229CHIPS
SPECIFICATIONS
33 GHz TO 35 GHz FREQUENCY RANGE
TA = 25°C, VDD = VDD1 = VDD2 = VDD3 = VDD4 = VDD5 = VDD6 = VDD7 = VDD8 = 6 V, IDQ = 1200 mA.1, 2
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min
33
Typ
Max
Unit
GHz
dB
FREQUENCY RANGE
GAIN
35
21
23
Gain Variation Over Temperature
RETURN LOSS
0.035
dB/°C
Input
Output
7
15
dB
dB
OUTPUT
Output Power for 1 dB Compression
Saturated Output Power
Power Added Efficiency
Output Third-Order Intercept
SUPPLY CURRENT
SUPPLY VOLTAGE
P1dB
PSAT
PAE
29.5 31.5
dBm
dBm
%
32
22
39.5
PAE taken at saturated output power
Measurement taken at POUT/tone = 20 dBm
OIP3
dBm
3
IDQ
800
5
1200 mA
VDD
6
V
1 Recommended bias conditions.
2 Adjust the VGGx supply voltage between −2 V and 0 V to achieve IDQ = 1200 mA.
3 IDQ is the drain current without applying RF power.
35 GHz TO 37 GHz FREQUENCY RANGE
TA = 25°C, VDD = VDD1 = VDD2 = VDD3 = VDD4 = VDD5 = VDD6 = VDD7 = VDD8 = 6 V, IDQ = 1200 mA.1, 2
Table 2.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
GHz
dB
FREQUENCY RANGE
GAIN
Gain Variation Over Temperature
RETURN LOSS
35
37
22.5 24.5
0.044
dB/°C
Input
Output
9.5
20
dB
dB
OUTPUT
Output Power for 1 dB Compression
Saturated Output Power
Power Added Efficiency
Output Third-Order Intercept
SUPPLY CURRENT
SUPPLY VOLTAGE
P1dB
PSAT
PAE
28.5 30.5
dBm
dBm
%
31
16
39
PAE taken at saturated output power
Measurement taken at POUT/tone = 20 dBm
OIP3
dBm
3
IDQ
800
5
1200 mA
VDD
6
V
1 Recommended bias conditions.
2Adjust the VGGx supply voltage between −2 V and 0 V to achieve IDQ = 1200 mA.
3 IDQ is the drain current without applying RF power.
Rev. 0 | Page 3 of 16
HMC7229CHIPS
Data Sheet
37 GHz TO 40 GHz FREQUENCY RANGE
TA = 25°C, VDD = VDD1 = VDD2 = VDD3 = VDD4 = VDD5 = VDD6 = VDD7 = VDD8 = 6 V, IDQ = 1200 mA.1, 2
Table 3.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
GHz
dB
FREQUENCY RANGE
GAIN
Gain Variation Over Temperature
RETURN LOSS
37
40
21.5 23.5
0.045
dB/°C
Input
Output
9.5
13
dB
dB
OUTPUT
Output Power for 1 dB Compression
Saturated Output Power
Power Added Efficiency
Output Third-Order Intercept
SUPPLY CURRENT
SUPPLY VOLTAGE
P1dB
PSAT
PAE
27.5 29.5
dBm
dBm
%
30
12
37
PAE taken at saturated output power
Measurement taken at POUT/tone = 20 dBm
OIP3
dBm
3
IDQ
800
5
1200 mA
VDD
6
V
1 Recommended bias conditions.
2 Adjust the VGGx supply voltage between −2 V and 0 V to achieve IDQ = 1200 mA.
3 IDQ is the drain current without applying RF power.
Rev. 0 | Page 4 of 16
Data Sheet
HMC7229CHIPS
ABSOLUTE MAXIMUM RATINGS
Table 4.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Parameter
Rating
Drain Bias Voltage (VDD)
RF Input Power (RFIN)
Channel Temperature
7 V
21 dBm
175°C
9.7 W
Continuous Power Dissipation (PDISS),
TA = 85°C (Derate 107 mW/°C Above 85°C)
Thermal Resistance, θJC (Channel to
Bottom Die)
9.3°C/W
ESD CAUTION
Storage Temperature Range
Operating Temperature Range
−65°C to +150°C
−55°C to +85°C
ESD Sensitivity, Human Body Model (HBM) Class 0, passed 150 V
Rev. 0 | Page 5 of 16
HMC7229CHIPS
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
2
3
4
5
6
V
V
V
V
V
DD4
GG1
DD1
DD2
DD3
V
7
REF
HMC7229CHIPS
1
8
RFOUT
RFIN
V
DET
9
V
V
V
V
V
DD8
GG2
DD5
13
DD6
12
DD7
14
11
10
Figure 2. Pad Configuration
Table 5. Pad Function Descriptions
Pad No.
Mnemonic
Description
1
RFIN
RF Input. This pad is ac-coupled and matched to 50 Ω.
2, 14
VGG1, VGG2
Gate Controls for the Power Amplifier. Adjust the VGG1 or VGG2 supply voltage to achieve recommended bias
current. External 100 pF, 10 nF, and 4.7 μF bypass capacitors are required.
3 to 6,
10 to 13
7
VDD1 to VDD8
VREF
Drain Bias Voltages. External 100 pF, 10 nF, and 4.7 μF bypass capacitors are required.
DC Voltage of the Diode. This pad is biased through an external detector circuit used for temperature
compensation of VDET (see Figure 36).
8
9
RFOUT
VDET
RF Output. This pin is ac-coupled and matched to 50 Ω.
DC Voltage Representing the RF Output Power. This pad is rectified by the diode that is biased through
an external resistor (see Figure 36).
Die Bottom GND
Die Bottom. The die bottom must be connected to RF/dc ground. See Figure 9 for the interface schematic.
Rev. 0 | Page 6 of 16
Data Sheet
HMC7229CHIPS
INTERFACE SCHEMATICS
RFIN
V
REF
Figure 3. RFIN Interface Schematic
Figure 6. VREF Interface Schematic
RFOUT
Figure 7. RFOUT Interface Schematic
V
, V
GG1 GG2
Figure 4. VGG1,VGG2 Interface Schematic
V
DET
Figure 8. VDET Interface Schematic
V
TO V
DD8
DD1
GND
Figure 9. GND Interface Schematic
Figure 5. VDD1 to VDD8 Interface Schematic
Rev. 0 | Page 7 of 16
HMC7229CHIPS
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
30
28
26
24
22
20
18
30
S21
–55°C
+25°C
+85°C
20
10
0
S11
–10
S22
–20
–30
–40
33
34
35
36
37
38
39
40
32
33
34
35
36
37
38
39
40
41
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 10. Response Gain and Return Loss vs. Frequency
Figure 13. Gain vs. Frequency at Various Temperatures
0
0
–5
–5
–10
–15
–20
–25
–30
–55°C
+25°C
+85°C
–55°C
+25°C
+85°C
–10
–15
–20
33
34
35
36
37
38
39
40
33
34
35
36
37
38
39
40
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 14. Output Return Loss vs. Frequency at Various Temperatures
Figure 11. Input Return Loss vs. Frequency at Various Temperatures
34
34
–55°C
32
30
28
26
24
+25°C
+85°C
32
30
28
26
24
5.0V
5.5V
6.0V
33
34
35
36
37
38
39
40
33
34
35
36
37
38
39
40
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 12. P1dB vs. Frequency at Various Temperatures
Figure 15. P1dB vs. Frequency at Various Supply Voltages
Rev. 0 | Page 8 of 16
Data Sheet
HMC7229CHIPS
34
32
30
28
26
24
34
32
30
28
26
24
5.0V
5.5V
6.0V
–55°C
+25°C
+85°C
33
34
35
36
37
38
39
40
33
34
35
36
37
38
39
40
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 16. PSAT vs. Frequency at Various Temperatures
Figure 19. PSAT vs. Frequency at Various Supply Voltages
34
32
30
28
26
24
34
32
30
28
26
24
800mA
1000mA
1200mA
800mA
1000mA
1200mA
33
34
35
36
37
38
39
40
33
34
35
36
37
38
39
40
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 17. P1dB vs. Frequency at Various Supply Currents
Figure 20. PSAT vs. Frequency at Various Supply Currents
1430
1375
1320
1265
1210
1155
1100
1045
1530
1475
1420
1365
1310
1255
1200
1145
35
30
25
20
15
10
5
35
30
25
20
15
10
5
P
GAIN
PAE
OUT
P
GAIN
PAE
OUT
I
DD
I
DD
0
0
–10 –8
–6
–4
–2
0
2
4
6
8
10
12
–10 –8
–6
–4
–2
0
2
4
6
8
10
12
INPUT POWER (dBm)
INPUT POWER (dBm)
Figure 18. Power Compression at 34 GHz
(IDD is Drain Current With RF Power Applied)
Figure 21. Power Compression at 39 GHz
Rev. 0 | Page 9 of 16
HMC7229CHIPS
Data Sheet
44
42
40
38
36
34
32
30
44
42
40
38
36
34
32
30
–55°C
+25°C
+85°C
5.0V
5.5V
6.0V
33
34
35
36
37
38
39
40
33
34
35
36
37
38
39
40
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 22. Output IP3 vs. Frequency at Various Temperatures
Figure 25. Output IP3 vs. Frequency at Various Supply Voltages
44
42
40
38
60
55
50
45
40
800mA
1000mA
1200mA
36
33GHz
35
30
25
20
34GHz
36GHZ
38GHz
39GHz
40GHz
34
32
30
10
12
14
16
18
20
22
24
33
34
35
36
37
38
39
40
P
/TONE (dBm)
FREQUENCY (GHz)
OUT
Figure 23. Output IP3 vs. Frequency at Various Supply Current
Figure 26. IM3 vs. POUT/Tone for Various Frequencies at VDD = 5.5 V
60
55
50
60
55
50
45
45
33GHz
34GHz
36GHZ
38GHz
39GHz
40GHz
40
35
30
25
20
40
33GHz
35
30
25
20
34GHz
36GHZ
38GHz
39GHz
40GHz
10
12
14
16
18
20
22
24
10
12
14
16
18
20
22
24
P
/TONE (dBm)
P
/TONE (dBm)
OUT
OUT
Figure 24. Third-Order Intermodulation (IM3) vs. POUT/Tone for Various
Frequencies at VDD = 6 V
Figure 27. IM3 vs. POUT/Tone for Various Frequencies at VDD = 5 V
Rev. 0 | Page 10 of 16
Data Sheet
HMC7229CHIPS
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
33GHz
34GHz
36GHZ
37GHz
39GHz
40GHz
–55°C
+25°C
+85°C
33
34
35
36
37
38
39
40
–10 –8
–6 –4 –2
0
2
4
6
8
10 12 14
FREQUENCY (GHz)
INPUT POWER (dBm)
Figure 28. Reverse Isolation vs. Frequency for Various Temperatures
Figure 31. Power Dissipation vs. Input Power for Various Frequencies
at TA = 85°C
35
10
32
29
1
–55°C
+25°C
+85°C
100m
P
SAT
P1dB
GAIN
26
23
20
10m
1m
0.1m
5.0
5.2
5.4
5.6
5.8
6.0
–20
–10
0
10
20
30
V
(V)
DD
OUTPUT POWER (dBm)
Figure 29. Gain, P1dB, and PSAT vs Supply Voltage (VDD) at 36 GHz
Figure 32. Detector Voltage (VDET) vs. Output Power at 38.5 GHz at Various
Temperatures
35
25
20
15
10
5
32
29
P
P1dB
GAIN
SAT
26
23
20
0
800
900
1000
(mA)
1100
1200
33
34
35
36
37
38
39
40
I
DQ
FREQUENCY (GHz)
Figure 30. Gain, P1dB, and PSAT vs. Supply Current (IDQ) at 36 GHz
Figure 33. PAE at PSAT vs Frequency
Rev. 0 | Page 11 of 16
HMC7229CHIPS
Data Sheet
THEORY OF OPERATION
The HMC7229CHIPS is a GaAs, pHEMT, MMIC, 1 W power
amplifier consisting of four gain stages in series. Figure 34
shows a simplified functional block diagram of the
HMC7229CHIPS.
Similarly, multiple HMC7229CHIPS can be used with power
dividers at the RF input and power combiners at the RF output
to obtain higher output power levels.
The input and output impedances are sufficiently stable compared
to the variations in temperature and supply voltage that no
impedance matching compensation is required.
The input signal of the HMC7229CHIPS is evenly divided into
two paths and each path is amplified through the four independent
gain stages. The amplified signals are then combined at the RF
output.
It is critical to supply very low inductance ground connections
to the backside of the HMC7229CHIPS, ensuring stable
operation. Guidance on mounting the HMC7229CHIPS is given
in the Mounting and Bonding Techniques for Millimeter Wave
GaAs MMICs section.
The HMC7229CHIPS has single-ended input and output ports
with impedances nominally matched to 50 Ω internally over the
frequency range from 33 GHz to 40 GHz. Consequently, the
HMC7229CHIPS can be directly inserted into a 50 Ω system
with no impedance matching circuitry required.
To achieve the best performance from the HMC7229CHIPS
and not to damage the device, do not exceed the absolute
maximum ratings.
Impedences nominally matched to a 50 Ω system also means
that multiple HMC7229CHIPS amplifiers can be cascaded back
to back without external matching circuitry.
V
V
V
V
GG1
GG1
GG1
GG1
OR
GG2
OR
GG2
OR
GG2
OR
V
V
V
V
DD4
GG2
V
V
V
V
DD1
DD2
DD3
RFIN
RFOUT
V
V
V
V
GG1
V
V
V
V
DD8
GG1
GG1
GG1
DD5
DD6
DD7
OR
GG2
OR
GG2
OR
GG2
OR
GG2
V
V
V
V
Figure 34. Simplified Functional Block Diagram
Rev. 0 | Page 12 of 16
Data Sheet
HMC7229CHIPS
APPLICATIONS INFORMATION
MOUNTING AND BONDING TECHNIQUES FOR
MILLIMETER WAVE GaAs MMICs
Eutectic Die Attach
It is best to use an 80% Au/20% Sn preform with a work surface
temperature of 255°C and a tool temperature of 265°C. When the
work surface is 255°C and tool temperature is 265°C, 90% nitrogen/
10% hydrogen gas is applied to the work surface, maintain the
tool tip temperature at 290°C. Do not expose the HMC7229CHIPS
to a temperature greater than 320°C for more than 20 sec. No
more than 3 sec of scrubbing is required for attachment.
Attach the HMC7229CHIPS directly to the ground plane
eutectically or with a conductive epoxy. To route the RF signal
to and from the HMC7229CHIPS, use a 50 Ω microstrip
transmission line on 0.127 mm (0.005 inches) thick alumina, thin
film substrates (see Figure 35).
0.102mm (0.004") THICK GaAs MMIC
Epoxy Die Attach
The ABLETHERM 2600BT is recommended for chip attachment.
Apply a minimum amount of epoxy to the mounting surface so
a thin epoxy fillet is observed around the perimeter of the
HMC7229CHIPS after placing the device into position on
the surface. Cure the epoxy per the schedule provided by the
manufacturer.
RIBBON BOND
0.076mm
(0.003")
RF GROUND PLANE
Wire Bonding
RF bonds made with 0.003 in. × 0.0005 in. Au ribbon are recom-
mended for the RF ports. These bonds must be thermosonically
bonded with a force of 40 g to 60 g. DC bonds of 1 mil (0.025 mm)
diameter, thermosonically bonded, are recommended. Create ball
bonds with a force of 40 g to 50 g and wedge bonds with a force of
18 g to 22 g. Create all bonds with a nominal stage temperature of
150°C. Apply a minimum amount of ultrasonic energy to achieve
reliable bonds. Keep all bonds as short as possible, less than 12 mil
(0.31 mm).
0.127mm (0.005") THICK ALUMINA,
THIN FILM SUBSTRATE
Figure 35. Routing RF Signals
To minimize the bond wire length, place microstrip substrates
as close to the HMC7229CHIPS as possible. Typical chip to
substrate spacing is 0.076 mm to 0.152 mm (0.003 inches and
0.006 inches).
HANDLING PRECAUTIONS
BIASING PROCEDURES
To avoid permanent damage to the device, adhere to the following
precautions:
The basic connections for operating the HMC7229CHIPS are
shown in the Typical Application Circuit section and the Theory
of Operation section. The RF input and RF output are ac-coupled
by internal dc block capacitors. Follow the recommended bias
sequencing to avoid damaging the amplifier.
•
All bare HMC7229CHIPS ship in either waffle or gel-based
ESD protective containers, sealed in an ESD protective bag.
After opening the sealed ESD protective bag, store all chips in
a dry nitrogen environment.
The amplifier gate bias can be supplied using either the VGG1 pin
or VGG2 pin. Use the VDD1 to VDD8 pins while applying the drain bias
to the amplifier. Testing to gather data for the HMC7229CHIPS
data sheet used the VGG1 pin with the VDD1 to VDD8 pins connected
together.
•
Handle the HMC7229CHIPS in a clean environment.
Never use liquid cleaning systems to clean the chip.
Follow ESD precautions to protect against ESD strikes.
While applying bias, suppress instrument and bias supply
transients. To minimize inductive pickup, use shielded
signal and bias cables.
•
•
Use the following recommended bias sequence during power-up:
1. Connect GND to RF/dc ground.
2. Set VGG1 or VGG2 to −2 V.
3. Set VDD1 to VDD8 to 6 V.
4. Increase VGG1 or VGG2 to achieve a typical IDQ = 1200 mA.
5. Apply an RF signal the device.
•
Handle the HMC7229CHIPS along the edges with a vacuum
collet or a sharp pair of bent tweezers. The surface of the chip
has fragile air bridges and must not be touched with a vacuum
collet, tweezers, or fingers.
MOUNTING
Use the following recommended bias sequence during power-
down:
The HMC7229CHIPS is back metallized and can be die mounted
onto a system with Au/Sn eutectic preforms or with electrically
conductive epoxy. The mounting surface must be clean and flat.
1. Turn off the RF signal
2. Decrease VGG1 or VGG2 to −2 V to achieve IDQ = 0 mA.
3. Decrease VDD1, VDD2, VDD3, and VDD4 to 0 V.
4. Increase VGG1 or VGG2 to 0 V.
Rev. 0 | Page 13 of 16
HMC7229CHIPS
Data Sheet
The bias conditions listed at VDD = 6 V, IDQ = 1200 is a
recommended operating point to receive optimum performance
from the HMC7229CHIPS. The data used in this data sheet is
taken with the recommended bias conditions (see the
Specifications section).
The VDET and VREF pins are the output pins for the internal
power detector. The VDET pin is the dc voltage output pin
representing the RF output power rectified by the internal
diode, biased through an external resistor.
The VREF pin is the dc voltage output pin representing the
reference diode voltage, which is biased through an external
resistor. The reference diode voltage compensates the temperature
variation effects on both the VREF and VDET diodes. Figure 36
shows a suggested circuit to read out the output voltage in
correlation with the RF output power.
Using the HMC7229CHIPS in a different bias condition may
provide different performance than the performance shown in
the Typical Performance Characteristics section.
TYPICAL APPLICATION CIRCUIT
V
, V
V
, V
+
DD1
DD2
DD3
DD4
+
4.7µF
0.1µF
100pF
100pF
SUGGESTED CIRCUIT
OPTION 1
V
GG1
4.7µF
100pF
100pF
0.1µF
–5V
10kΩ
10kΩ
4.7µF
0.1µF
100pF
+
2
1
3
V
V
= V
– V
REF
4
OUT
REF DET
5
HMC7229CHIPS
6
7
9
RFIN
8
RFOUT
10
10kΩ
10kΩ
11
V
DET
12
13
100kΩ 100kΩ
+5V
14
OPTION 2
V
+5V
GG2
+
+
100pF
4.7µF
4.7µF
0.1µF
0.1µF
100pF
100pF
V
, V
DD8
DD7
V
, V
DD6
+
DD5
100pF
4.7µF
0.1µF
100pF
Figure 36. Typical Application Circuit
Rev. 0 | Page 14 of 16
Data Sheet
HMC7229CHIPS
ASSEMBLY DIAGRAM
Figure 37. Assembly Diagram
Rev. 0 | Page 15 of 16
HMC7229CHIPS
Data Sheet
OUTLINE DIMENSIONS
2.794
0.102
0.130
0.130
0.0178
0.102
2
3
4
5
6
7
0.150
0.391
2.380
0.201
0.201
0.201
8
1
0.201
0.391
0.150
0.350
9
0.890
13
12
11
14
10
0.135
SIDE VIEW
0.150
0.851
0.0102
0.0813
0.150
0.350
0.216
0.350
0.150
0.150
0.150
0.201
Figure 38. 14-Pad Bare Die [CHIP]
(C-14-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
−55°C to +85°C
Package Description
14-Pad Bare Die [CHIP]
14-Pad Bare Die [CHIP]
Package Option
HMC7229
C-14-4
C-14-4
HMC7229SX
−55°C to +85°C
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14566-0-6/16(0)
Rev. 0 | Page 16 of 16
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