HSC-ADC-EVALCZ [ADI]
High Speed Converter Evaluation Platform;
| 型号： | HSC-ADC-EVALCZ |
| 厂家： | 
ADI |
| 描述： | High Speed Converter Evaluation Platform |
| 文件： | 总32页 (文件大小：2104K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Speed Converter Evaluation Platform
HSC-ADC-EVALC
PRODUCT HIGHLIGHTS
FEATURES
Xilinx Virtex-4 FPGA-based buffer memory board
Used for capturing digital data from high speed ADC
evaluation boards to simplify evaluation
64 kB FIFO depth
1. Easy to Set Up. Connect the included power supply along
with the CLK and AIN signal sources to the two evaluation
boards. Then connect to the PC via the USB port and
evaluate the performance instantly.
Parallel input at 644 MSPS SDR and 800 MSPS DDR
Supports 1.8 V, 2.5 V, and 3.3 V CMOS and LVDS interfaces
Supports multiple ADC channels up to 18 bits
Measures performance with VisualAnalog
Real-time FFT and time domain analysis
Analyzes SNR, SINAD, SFDR, and harmonics
Simple USB port interface (2.0)
Supports ADCs with serial port interfaces (SPI)
FPGA reconfigurable via JTAG, on-board EPROM, or USB
On-board regulator circuit speeds setup
5 V, 3 A switching power supply included
Compatible with Windows 98 (2nd edition), Windows 2000,
Windows ME, and Windows XP
2. USB Port Connection to PC. PC interface is via a USB 2.0
connection (1.1 compatible) to the PC. A USB cable is
provided in the kit.
3. 64 kB FIFO. The on-board FPGA contains an integrated
FIFO to store data captured from the ADC for subsequent
processing.
4. Up to 644 MSPS SDR/800 MSPS DDR Encode Rates on
Each Channel. Multichannel ADCs with encode rates up
to 644 MSPS SDR and 800 MSPS DDR can be used with
the ADC capture board.
5. Supports ADCs with Serial Port Interface or SPI. Some
ADCs include a feature set that can be changed via the
SPI. The ADC capture board supports these SPI-driven
features through the existing USB connection to the
computer without additional cabling needed.
EQUIPMENT NEEDED
Analog signal source and antialiasing filter
6. VisualAnalog™. VisualAnalog supports the HSC-ADC-
EVALC hardware platform as well as enabling virtual ADC
evaluation using ADIsimADC™, Analog Devices proprietary
behavioral modeling technology. This allows rapid compari-
son between multiple ADCs, with or without hardware
evaluation boards. For more information, see AN-737 at
www.analog.com/VisualAnalog.
Low jitter clock source
High speed ADC evaluation board and ADC data sheet
PC running Windows 98 (2nd edition), Windows 2000,
Windows ME, or Windows XP
Latest version of VisualAnalog
USB 2.0 port recommended (USB 1.1 compatible)
FUNCTIONAL BLOCK DIAGRAM
ON-BOARD
VOLTAGE
REGULATORS
HSC-ADC-EVALC
POWER
CONNECTOR
USB
SINGLE OR MULTICHANNEL
HIGH SPEED ADC
FPGA
CONFIGURATION
MODE
LED2
LED1
UPLOAD CAPTURE
EVALUATION BOARD
PORTB
PORTD
DATA(16)
FIFO
CONTROL(9)
DATA BUS 2(18)
CLKA(2)
n
FILTERED
ANALOG
INPUT
J6
J3*
USB
CONTROLLER
FPGA
ADC
USB
CONNECTOR
DATA BUS 1(18)
CLKB(2)
PORTC
PORTE
PORTA
n
J2*
STANDARD
USB 2.0
EXT SYNC1
EXT SYNC2
FPGA
DONE
CLOCK
CIRCUIT
USB
CONFIG
PROM
ONBOARD
VOLTAGE
REGULATORS
J4
FPGA
CONFIG
PROM
POWER
CONNECTOR
FPGA GPIO(8)
SPI(7)
J1*
RECONFIG
SPI
USB DIRECT(5)
J10
*DATA CONVERTER I/O CONNECTORS
JTAG
CONNECTOR
CLOCK INPUT
Figure 1.
Rev. 0
Evaluation boards are only intended for device evaluation and not for production purposes.
Evaluation boards as supplied “as is” and without warranties of any kind, express, implied, or
statutory including, but not limited to, any implied warranty of merchantability or fitness for a
particular purpose. No license is granted by implication or otherwise under any patents or other
intellectual property by application or use of evaluation boards. Information furnished by Analog
Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result
from its use. Analog Devices reserves the right to change devices or specifications at any time
without notice. Trademarks and registered trademarks are the property of their respective owners.
Evaluation boards are not authorized to be used in life support devices or systems.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
HSC-ADC-EVALC
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation .........................................................................8
Configuration ................................................................................8
Input Circuitry...............................................................................8
Data Capture..................................................................................8
Code Description ..........................................................................8
FPGA Configuration and Customization..................................8
Evaluation Board Schematics and Artwork...................................9
HSC-ADC-EVALC Schematics...................................................9
PCB Layout ................................................................................. 23
I/O Connector—J1, J2, and J3 Pin Mapping .......................... 24
Ordering Information.................................................................... 28
Bill of Materials (RoHS Compliant) ........................................ 28
Ordering Guide .......................................................................... 30
ESD Caution................................................................................ 30
Equipment Needed........................................................................... 1
Product Highlights ........................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Product Description......................................................................... 3
Evaluation Board Description......................................................... 3
Evaluation Board Hardware............................................................ 4
HSC-ADC-EVALC ADC Capture Board Easy Start............... 4
Power Supplies .............................................................................. 4
Connection and Setup ................................................................. 4
Jumpers .......................................................................................... 5
HSC-ADC-EVALC ADC Capture Board Features.................. 6
HSC-ADC-EVALC Supported ADC Evaluation Boards........ 7
REVISION HISTORY
4/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
HSC-ADC-EVALC
The FPGA contains an integrated FIFO memory that allows
PRODUCT DESCRIPTION
capture of data record lengths up to a total of 64 kB. A USB 2.0
microcontroller communicating with VisualAnalog allows
for easy interfacing to newer computers using the USB 2.0
(USB 1.1 compatible) interface.
The Analog Devices, Inc. high speed converter evaluation
platform (HSC-ADC-EVALC) includes the latest version of
VisualAnalog and an FPGA-based buffer memory board to capture
blocks of digital data from the Analog Devices high speed
analog-to-digital converter (ADC) evaluation boards. The ADC
capture board is connected to the PC through a USB port and is
used with VisualAnalog to quickly evaluate the performance of
high speed ADCs. Users can view an FFT for a specific analog
input and encode rate to analyze SNR, SINAD, SFDR, and
harmonic information.
EVALUATION BOARD DESCRIPTION
The ADC capture board provides all of the support circuitry
required to accept two 18-bit channels from an ADC’s parallel
CMOS or LVDS outputs. Various functions such as FPGA
configuration load options and I/O logic levels can be selected by
proper connection of various jumpers or switches (see Table 1).
When using the HSC-ADC-EVALC in conjunction with an
ADC evaluation board, it is critical that the signal sources used
for the ADC board’s analog input and clock have very low phase
noise (<1 ps rms jitter) to achieve the ultimate performance of
the converter.
The ADC capture board is easy to set up. Additional equipment
needed includes an Analog Devices high speed ADC evaluation
board, a signal source, and a clock source. Once the kit is
connected and powered, the evaluation is enabled instantly on
the PC.
Proper filtering of the analog input signal to remove harmonics
and lower the integrated or broadband noise at the input is also
necessary to achieve the specified noise performance.
The ADC capture board enables numerous expansion and
evaluation possibilities by virtue of its powerful reconfigurable
FPGA core.
See Figure 5 to Figure 20 for complete schematics and layout plots.
The system can acquire digital data at speeds up to 644 MSPS
single data rate (SDR) and 800 MSPS double data rate (DDR).
Rev. 0 | Page 3 of 32
HSC-ADC-EVALC
EVALUATION BOARD HARDWARE
6. Once the USB cable is connected to both the computer and
the HSC-ADC-EVALC board, and power is applied, the
USB driver starts to install. The Found New Hardware
Wizard opens and prompts you through the automated
install process.
7. (Optional) Verify in the Windows device manager that
Analog Devices ADC-HSC-EVALC is listed under the
USB hardware.
8. Refer to the instructions included in the respective ADC
data sheet found at www.analog.com/FIFO for more
information about connecting the ADC evaluation board’s
power supply and other requirements. After verification of
power supply connections, apply power to the ADC
evaluation board and check the voltage levels on the ADC
board to make sure they are correct.
9. Make sure the evaluation boards are powered on before
connecting the analog input and clock. Connect the
appropriate analog input (which should be filtered with a
band-pass filter) and low jitter clock signal.
HSC-ADC-EVALC ADC CAPTURE BOARD
EASY START
Requirements
•
HSC-ADC-EVALC ADC capture board, VisualAnalog, 5 V
wall transformer, and USB cable
•
•
•
•
High speed ADC evaluation board and ADC data sheet
Power supply for ADC evaluation board
Analog signal source and appropriate filtering
Low jitter clock source applicable for specific ADC
evaluation, typically <1 ps rms jitter
•
PC running Windows® 98 (2nd edition), Windows 2000,
Windows ME, or Windows XP
•
PC with a USB 2.0 port recommended (USB 1.1 compatible)
Easy Start Steps
Important Note
Administrative rights for the Windows operating systems are
needed during the entire easy start procedure.
10. Refer to the VisualAnalog User Manual at
www.analog.com/FIFO for detailed software operating
instructions.
Completion of every step before reverting to a normal user
mode is recommended.
1. Install VisualAnalog from the CD provided in the ADC
capture board kit or download the latest version from the
Web. For the latest updates to the software, check the
Analog Devices website at www.analog.com/FIFO.
2. Connect the ADC capture board to the ADC evaluation
board. If an adapter is required, insert the adapter between
the ADC evaluation board and the ADC capture board.
3. Connect the provided USB cable to the ADC capture board
and to an available USB port on the computer.
POWER SUPPLIES
The ADC capture board is supplied with a wall mount switch-
ing power supply that provides a 5 V, 3 A maximum output.
Connect the supply to the rated 100 Vac to 240 Vac wall outlet at
47 Hz to 63 Hz. The other end is a 2.1 mm inner diameter jack
that connects to the PCB at J4. On the PC board, the supply is
fused and conditioned before connecting to the regulators that
supply the proper bias to the entire ADC capture board.
4. Refer to Table 1 for setting the ADC capture board’s I/O
logic level to match the level coming from the ADC evalua-
tion board. 1.8 V is default; 2.5 V and 3.3 V are jumper
selectable. Most evaluation boards can be used with the
default settings.
5. The ADC capture board is supplied with a wall mount
switching power supply. Connect the supply end to an ac
wall outlet rated for 100 Vac to 240 Vac at 47 Hz to 63 Hz.
The other end is a 2.1 mm inner diameter jack that connects
to the PCB at J4.
CONNECTION AND SETUP
The ADC capture board has two 40-pin connectors (J2 and J3)
that accept two 18-bit channels of parallel CMOS or LVDS
inputs from the ADC (see Figure 2). The third 40-pin connector
(J1) is used to pass SPI and other USB/FPGA control signals
across to adjacent ADC evaluation boards that support these
features.
Rev. 0 | Page 4 of 32
HSC-ADC-EVALC
WALL OUTLET
100V TO 240V AC
47Hz TO 63Hz
ONBOARD POWER
SUPPLY
PS
–
+
5V DC
3A MAX
SWITCHING
POWER
SUPPLY
DATA BUS 2
PARALLEL
LVDS/CMOS
OUTPUTS
PC
HSC-ADC-EVALC
DATA CAPTURE
BOARD
RUNNING
VisualAnalog
EVALUATION
BOARD
ROHDE & SCHWARZ,
SMHU,
BAND-PASS
FILTER
XFMR
INPUT
2V p-p SIGNAL
SYNTHESIZER
DATA BUS 1
USB
CONNECTION
PARALLEL
LVDS/CMOS
OUTPUTS
ROHDE & SCHWARZ,
SMHU,
CLK
2V p-p SIGNAL
SYNTHESIZER
SPI
SPI
Figure 2. Example Setup Using ADC Evaluation Board and HSC-ADC-EVALC ADC Capture Board
JUMPERS
Default Settings
Table 1 lists the default settings for the HSC-ADC-EVALC evaluation kit.
Table 1. Jumper Configurations
Jumper Number
Description
J9, Pin 1 to Pin 2 (1.8 V)
J9, Pin 3 to Pin 4 (2.5 V)
J9, Pin 5 to Pin 6 (3.3 V)
Default. Sets FPGA I/O voltage to 1.8 V logic (hardwired, do not remove).
Install single jumper here to set FPGA I/O voltage to 2.5 V logic.
Install single jumper here to set FPGA I/O voltage to 3.3 V logic.
Table 2. FPGA Configuration Mode
U4 DIP Switch Setting
FPGA Configured via EEPROM
FPGA Configured via USB (Default)
M0
On
On
M1
On
Off
M2
On
Off
M3
M4
Reserved
Reserved
Reserved
Reserved
Rev. 0 | Page 5 of 32
HSC-ADC-EVALC
HSC-ADC-EVALC ADC CAPTURE BOARD FEATURES
GENERAL PURPOSE I/O,
USB/SPI CONTROL
DATA BUS 1
DATA BUS 2
FPGA LOAD
SELECT
XILINX
VIRTEX-4
FPGA
DEBUG
PINS
ON BOARD
POWER SUPPLY
100MHz
OSCILLATOR
EXTERNAL
SYNC I/O
FPGA I/O
VOLTAGE MODE
FPGA CONFIG
PROM
CYPRESS USB
CONTROLLER
USB CONNECTOR
FPGA JTAG
CONNECTOR
5VDC POWER
INPUT
Figure 3. HSC-ADC-EVALC Components (Top View)
Rev. 0 | Page 6 of 32
HSC-ADC-EVALC
Figure 4. HSC-ADC-EVALC Components (Bottom View)
HSC-ADC-EVALC SUPPORTED ADC EVALUATION BOARDS
Refer to the Analog Devices ADC capture board product page at www.analog.com/FIFO for a list of HSC-ADC-EVALC-compatible ADC
evaluation boards. Some legacy ADC boards may require interposer cards to facilitate proper pin mapping to the ADC capture board. If
needed, the interposer part number is noted in the compatibility table at www.analog.com/FIFO for the respective data converter.
Rev. 0 | Page 7 of 32
HSC-ADC-EVALC
THEORY OF OPERATION
The HSC-ADC-EVALC evaluation platform is based around
the Virtex-4 FPGA (XC4VFX20-10FFG672C) from Xilinx®,
which can be programmed through VisualAnalog to operate
with a variety of data converters. Another key component, the
Cypress USB device (U3), communicates with a host PC and
provides the SPI interface used for configuration.
Connector J3. Refer to the HSC-ADC-EVALC I/O connector
pin mappings shown in Figure 21 and Figure 22.
DATA CAPTURE
The process of filling the FIFO and reading the data back
requires several steps.
1. VisualAnalog initiates the FIFO fill process by resetting
the FIFOs.
CONFIGURATION
Some converter devices require programming for mode or
feature selection, which the SPI controller accomplishes using
SPI-accessible register maps. U3 drives the 4-wire SPI (SCLK,
SDI, SDO, CSB1) signals to the converter board via connector
(J1). For more information on serial port interface (SPI) func-
tions, consult the user manual titled Interfacing to High Speed
ADCs via SPI at www.analog.com/FIFO.
2. The 48 MHz USB read clock (RCLK) is then suspended to
ensure that it does not add noise to the ADC input.
3. VisualAnalog waits approximately 30 ms to allow for data
capture before beginning the readback process. This wait
time is an adjustable parameter in VisualAnalog.
4. VisualAnalog reads the data from the FIFO through the
USB interface to the PC.
The SPI interface designed on the Cypress IC can communicate
with up to five different SPI-enabled devices including the
FPGA. The CLK and SDI/SDO data lines are common to all SPI
devices. The desired SPI-enabled device is selected for control
by using one of the five active low chip select (CS) pins. This
functionality is controlled by selecting a SPI channel in the SPI
Controller software.
CODE DESCRIPTION
FPGA configuration files are provided by ADI for all ADCs
supported by the HSC-ADC-EVALC evaluation platform.
These files are designed and tested to facilitate quick
performance evaluations of Analog Devices data converters. No
additional FPGA programming is required from the user for
typical operation.
At power-up, VisualAnalog attempts to autodetect the converter
that is attached to the ADC capture board using the SPI
interface. If a recognized device is found, VisualAnalog selects
the appropriate FPGA configuration; otherwise, the user is
prompted to make the device selection. In either case,
VisualAnalog then programs the FPGA using the SPI interface
of U3. The configurations typically program a FIFO data capture
function within the FPGA.
FPGA CONFIGURATION AND CUSTOMIZATION
Users can manually customize or update the FPGA code
through a JTAG connector (J10) provided on the ADC capture
board, as shown in Figure 17. However, Analog Devices
provides no support or guarantee of performance if the
provided code is customized by the user.
The HSC-ADC-EVALC hardware platform may contain addi-
tional circuit functions to support future developments and
capabilities. These functions are not supported beyond the
scope of this data sheet and the Analog Devices supplied data-
capture FPGA routines at this time.
INPUT CIRCUITRY
The parallel data input pins of the FPGA, which interface to the
converter, are configurable. They can operate with 1.8 V, 2.5 V,
or 3.3 V logic levels and can accept LVDS or CMOS inputs.
Each channel of the ADC capture board requires a clock signal
to capture data. These clock signals are normally provided by
the attached ADC evaluation board and are passed along with
the data through one or more pins on Connector J2 and/or
Additional FPGA programming support may be available
through the user’s local Xilinx representative or distributor.
1 Note that CSB1 is the default CSB line used.
Rev. 0 | Page 8 of 32
HSC-ADC-EVALC
EVALUATION BOARD SCHEMATICS AND ARTWORK
HSC-ADC-EVALC SCHEMATICS
TYCO AND DSP EZ–KIT CONNECTOR TO FPGA
XC4VFX20-10FFG672C
XC4VFX20-10FFG672C
XC4VFX20-10FFG672C
R50
51.1Ω
XC4VFX20-10FFG672C
R38
100Ω
R39
100Ω
Figure 5.
Rev. 0 | Page 9 of 32
HSC-ADC-EVALC
SRAM ADDRESS AND CONTROL
R25
3.74KΩ
R27
249Ω
R28
3.74KΩ
R31
3.74KΩ
R33
249Ω
U21
NC7SZ05M5X
R1
100Ω
FPGA CONTROLS
R40
R44
R42
R41
R43
3.74KΩ 3.74KΩ 3.74KΩ 3.74KΩ 3.74KΩ
XC4VFX20-10FFG672C
Figure 6.
Rev. 0 | Page 10 of 32
HSC-ADC-EVALC
FPGA TO SRAM DATA
XC4VFX20-10FFG672C
XC4VFX20-10FFG672C
Figure 7.
Rev. 0 | Page 11 of 32
HSC-ADC-EVALC
AD19 TO BE USED WITH HIGHER
DENSITY SRAM DEVICES
Figure 8.
Rev. 0 | Page 12 of 32
HSC-ADC-EVALC
SRAM AND FPGA POWER
R63
R64
499Ω
499Ω
R66
R65
499Ω
499Ω
XC4VFX20-10FFG672C
XC4VFX20-10FFG672C
Figure 9.
Rev. 0 | Page 13 of 32
HSC-ADC-EVALC
SRAM A BYPASS CAP
REFCLK Oscillator for IDELAYCTRL
R15
24Ω
SRAM B BYPASS CAP
FPGA BYPASS CAP
Figure 10.
Rev. 0 | Page 14 of 32
HSC-ADC-EVALC
UNUSED ROCKET I/0 CONNECTIONS
XC4VFX20-10FFG672C
XC4VFX20-10FFG672C
DEBUG PINS
Figure 11.
Rev. 0 | Page 15 of 32
HSC-ADC-EVALC
ROCKET I/0 CONNECTIONS
Figure 12.
Rev. 0 | Page 16 of 32
HSC-ADC-EVALC
USB CONNECTIONS
R49
3.74Ω
R71
3.74Ω
R48
100KΩ
SDI & SDO DIRECTIONS ARE WITH
RESPECT TO THE DEVICE UNDER
CONTROL.
Figure 13.
Rev. 0 | Page 17 of 32
HSC-ADC-EVALC
USB CONNECTIONS (CONTINUED)
J6
R46
499Ω
R52
3.74KΩ
R72
3.74KΩ
1
2
3
4
5
6
XC4VFX20-10FFG672C
XC4VFX20-10FFG672C
Figure 14.
Rev. 0 | Page 18 of 32
HSC-ADC-EVALC
EZ–KIT EXPANSION INTERFACE – FOR DSPs
P1
P2
P3
Figure 15.
Rev. 0 | Page 19 of 32
HSC-ADC-EVALC
6
0 1 6 - 6 7 0 6
,
Figure 16.
Rev. 0 | Page 20 of 32
HSC-ADC-EVALC
CONFIGURATION EEPROM
R77
100Ω
R78
100Ω
R73
ZERO
R75
3.74KΩ
R76
3.74KΩ
JTAG CONNECTOR
EEPROM HARDWARE
RECONFIGURATION
PUSHBUTTON
R57
3.74KΩ
Figure 17.
Rev. 0 | Page 21 of 32
HSC-ADC-EVALC
1 0 8 6 - 6 7 0 6
+
+
+
+
+
+
+
V E O R E M
N O D O
T
+
+
Figure 18.
Rev. 0 | Page 22 of 32
HSC-ADC-EVALC
PCB LAYOUT
GENERAL PURPOSE I/O,
USB/SPI CONTROL
DATA BUS 1
DATA BUS 2
XILINX
VIRTEX-4
FPGA
FPGA LOAD
SELECT
ON BOARD
POWER SUPPLY
DEBUG
PINS
100MHz
OSCILLATOR
FPGA I/O
VOLTAGE MODE
EXTERNAL
SYNC I/O
CYPRESS USB
CONTROLLER
FPGA CONFIG
PROM
USB CONNECTOR
FPGA JTAG
CONNECTOR
5VDC POWER
INPUT
Figure 19. Top Silkscreen
Figure 20. Bottom Silkscreen
Rev. 0 | Page 23 of 32
HSC-ADC-EVALC
I/O CONNECTOR—J1, J2, AND J3 PIN MAPPING
1
0 2 6 - 6 7 0 6
Figure 21. J2 and J3 Pin Mapping
Rev. 0 | Page 24 of 32
HSC-ADC-EVALC
D
C
D
C
B
A
B
A
MGTCLK1– SD1–
MGTCLK1+ SD1+
SD2–
SD2+
SD3–
SD3+
SD4–
SD4+
SD5–
SD5+
SD6–
SD6+
SD7–
SD7+
SD8– MGTCLK2–
SD8+ MGTCLK2+
HIGH SPEED SERIAL
REFERENCE CLK
HIGH SPEED SERIAL
DATA INPUTS
I/O_1
I/O_2
I/O_3
I/O_4
I/O_5
I/O_6
I/O_7
I/O_8
SCLK
SDI
SDO
USB_1 USB_2 USB_4
FUTURE HIGH SPEED
SERIAL DATA INPUTS
CSB_1 CSB_2 CSB_3 CSB_4 USB_3 USB_5
FPGA GENERAL
PURPOSE I/O
(J1) HS-SERIAL/SPI/AUX
SPI CONTROL (3.3V)
USB DIRECT I/O (3.3V)
Figure 22. J1 Pin Mapping
13.843mm
38mm
32mm
43.155mm
1.4mm
J1
J2
J3
HS-SERIAL/SPI/AUX
DATA BUS 1
DATA BUS 2
Figure 23. Data Converter I/O Connector Placement (Top View)
Rev. 0 | Page 25 of 32
HSC-ADC-EVALC
Table 3. HSC-ADC-EVALC J1 I/O Connections to FPGA (U1)
Table 4. HSC-ADC-EVALC J2 I/O Connections to FPGA (U1)
Connector J1
(HS-Serial, SPI, AUX)
Connector J2
(DATA BUS 1)
Schematic Net Name
USB_5
USB_4
MGTCLK2+
MGTCLK2−
USB_3
USB_2
none
FPGA Pin
none
none
AF10
AF11
none
none
none
none
none
none
none
none
none
H12
none
none
none
K12
Schematic Net Name
DCLKB2+
DCLKB2−
D0B+
D0B−
D1B+
D1B−
D2B+
D2B−
D3B+
D3B−
D4B+
D4B−
D5B+
D5B−
D6B+
D6B−
D7B+
FPGA Pin
C13
C12
T4
A1
B1
C1
D1
A2
B2
C2
D2
A3
B3
C3
D3
A4
B4
C4
D4
A5
B5
C5
D5
A6
B6
C6
D6
A7
B7
C7
D7
A8
B8
A1
B1
C1
D1
A2
B2
C2
D2
A3
B3
C3
D3
A4
B4
C4
D4
A5
B5
C5
D5
A6
B6
C6
D6
A7
B7
C7
D7
A8
B8
C8
T3
M4
N4
P4
R3
M5
L5
L4
L3
K3
J3
L7
M6
J4
H3
K6
J5
none
CSB_4
USB_1
none
none
CSB_3
SDO
none
none
CSB_2
SDI
none
none
CSB_1
SCLK
SD4+
SD4−
I/O_8
I/O_7
SD3+
SD3−
I/O_6
I/O_5
SD2+
SD2−
I/O_4
I/O_3
SD1+
SD1−
I/O_2
I/O_1
MGTCLK1+
MGTCLK1−
D7B−
D8B+
D8B−
D9B+
none
none
none
H13
AF7
G5
F4
D9B−
D10B+
D10B−
D11B+
D11B−
D12B+
D12B−
D13B+
D13B−
D14B+
D14B−
D15B+
D15B−
D16B+
D16B−
DCLKB1+
DCLKB1−
D17B+
D17B−
H4
G4
H8
H7
G7
H6
F8
F7
K8
K7
B9
A9
A8
A7
A12
B12
B10
A10
AF8
AD3
AC3
AC1
AD1
AA3
Y3
G1
H1
W3
V3
A4
A3
P3
N3
K1
L1
C8
D8
A9
B9
C9
D9
A10
B10
C10
D10
D8
A9
B9
C9
D9
A10
B10
C10
D10
Rev. 0 | Page 26 of 32
HSC-ADC-EVALC
Table 5. HSC-ADC-EVALC J3 I/O Connections to FPGA (U1)
Connector J3
(DATA BUS 2)
Schematic Net Name
DCLKA2+
DCLKA2−
D0A+
FPGA Pin
C14
B14
D6
A1
B1
C1
D1
A2
D0A−
D1A+
E6
H9
B2
D1A−
G9
C2
D2A+
E8
D2
A3
B3
D2A−
D3A+
D3A−
E7
L10
L9
C3
D4A+
J9
D3
A4
D4A−
D5A+
K10
C3
B4
D5A−
D3
C4
D6A+
E3
D4
A5
D6A−
D7A+
F3
D5
B5
D7A−
E5
C5
D8A+
C4
D5
A6
D8A−
D9A+
D4
B7
B6
D9A−
C7
C6
D6
A7
B7
C7
D7
A8
B8
C8
D8
A9
D10A+
D10A−
D11A+
D11A−
D12A+
D12A−
D13A+
D13A−
D14A+
D14A−
D15A+
D15A−
D16A+
D16A−
DCLKA1+
DCLKA1−
D17A+
D17A−
B6
C6
D9
C9
D8
C8
C11
B11
E10
D10
G10
F10
E11
D11
A14
A13
G12
G11
B9
C9
D9
A10
B10
C10
D10
Rev. 0 | Page 27 of 32
HSC-ADC-EVALC
ORDERING INFORMATION
BILL OF MATERIALS (RoHS COMPLIANT)
Table 6.
Qty Reference Designator Description
Manufacturer
MOOG/PCSM
NEC
Part Number
GS09156x8
PD44164362F5-EQ1
1
0
PCB
BGA1, BGA2
PCB, ADC evaluation platform
IC, 18-bit DDRII SRAM 2-word burst
operation (MOS integrated circuit),
do not install
2
C1, C2
Capacitor, 470 pF, 50 V ceramic
X7R 0402
Panasonic/ECG
ECJ-0EB1H471K
3
2
C10, C17, C33
C21, C22
Capacitor, 330 μF, 10 V TG SMD
Capacitor, 68 pF, 50 V, ceramic
0402 SMD
Panasonic/ECG
Panasonic/ECG
EEETG1A331P
ECU-E1H680JCQ
67
C3, C25 to C30, C34,
C37 to C45, C59, C60,
C63 to C72, C74 to
C76, C78 to C85, C88
to C92, C96 to C98,
C100 to C106, C113 to
C118, C120 to C125
Capacitor, 0.1 μF, 10 V, ceramic
X5R 0402
Panasonic/ECG
ECJ-0EB1A104K
1
C32
Capacitor, 10 μF, 6.3 V, tantalum
TE series
Capacitor, 12 pF, 50 V, ceramic
0402 SMD
Capacitor, 0402 chip, X5R, 6.3 V,
1 μF, 20ꢀ
Kemet
T491A106M006AT
ECJ-0EC1H120J
ECJ-0EB0J105M
2
C35, C36
Panasonic/ECG
Panasonic
18
C4, C6, C7, C9, C11 to
C14, C16, C18, C20,
C62, C77, C87, C93,
C95, C99, C119
7
C46, C48, C52, C61,
C73, C86, C126
Capacitor, 10 μF, 20 V, tantalum TEL SMD AVX
TPSC106K025R0500
2
2
C47, C51
C49, C50
Capacitor, 47 μF, 10 V, tantalum TEL SMD Epcos, Inc.
B45197A2476K309
ECJ-0EF1H102Z
Capacitor, 1000 pF, 50 V, ceramic Y5V
0402
Panasonic/ECG
17
1
C5, C19, C23, C24, C31, Capacitor, 0402 chip, X5R, 6.3 V,
Panasonic
ECJ-0EB0J224K
ECJ-0EB1E471K
C53 to C58, C107 to
C112
0.22 μF, 10ꢀ
C94
Capacitor, 470 pF, 25 V, ceramic
0402 SMD
Panasonic/ECG
Panasonic
7
1
2
D1, D2, D6 to D10
LED green, clear lens SMD
LNJ308G8TRA
30BQ015TRPBF
ZHCS2000
D3
PolySwitch surface-mount (PTC devices) International IRF Rectifiers
D4, D5
40 V silicon high current Schottky
barrier diode
Zetex Semiconductors
1
1
J1, J2, J3
J10
Connector, 2-pair 10 column high speed Tyco
HM-Zd PCB mount
Connector, 2 mm, 2 × 7 pin SMT vertical Molex
male, with shroud
6469028-1
87832-1420-TB32
1
1
2
J4
J6
J5,J7
Connector, DC power jack
Connector, USB Type B
Connector, end launch jack/PCB, 62 mil,
gold
CUI Inc.
Mill-Max
Emerson
PJ-102AH
897-43-004-90-000000
142-0701-801
1
J8
Connector, 25 mil square postheader,
100 mil, 2 × 7
Connector, 2 × 2 header, 100 mil
Solder wire jumper (Pin 1 indicator to
1.8 V on silkscreen)
Samtec, Inc.
Samtec, Inc.
TSW-107-08-G-D
TSW-102-08-G-D
1
1
J9 (2.5 V and 3.3 V)
J9 (Jumper Pin 1 to
Jumper Pin 2)
1
1
L1
L2
Inductor, 4.6 μH SMD, Code 0004
Inductor, 3.6 μH SMD, Code 0003
Sumida
Sumida
CDR7D28MN4R6
CDR7D28MN3R6
Rev. 0 | Page 28 of 32
HSC-ADC-EVALC
Qty Reference Designator Description
Manufacturer
TDK
Samtec, Inc.
Part Number
17
3
L3 to L19
P1 to P3
Ferrite chip, 220 Ω, 2 A, 0603, 100 MHz
Connector, 0.050 in × 0.050 in, Samtec
TFM series, 2R
MPZ1608S221A
TFM-145-32-S-D-A
13
R1, R3, R4, R34 to R39,
R61, R67, R77, R78
Resistor, 100 Ω, 1/16 W, 1ꢀ, 0402 SMD
Panasonic/ECG
ERJ-2RKF1000X
3
1
5
10
R15, R56, R74
R16
Resistor, 24 Ω, 1/16 W, 5ꢀ, 0402 SMD
Resistor, 75 kΩ, 1/16 W, 1ꢀ, 0402 SMD
Panasonic/ECG
Panasonic/ECG
Panasonic/ECG
Panasonic/ECG
ERJ-2GEJ240X
ERJ-2RKF7502X
ERJ-2RKF51R1X
ERJ-2RKF4990X
R17, R18, R23, R24, R50 Resistor, 51.1 Ω, 1/16 W, 1ꢀ, 0402 SMD
R19 to R22, R46, R62 to Resistor, 499 Ω, 1/16 W, 1ꢀ, 0402 SMD
R66
1
17
R2
Resistor, 40.2 kΩ, 1/16 W, 1ꢀ, 0402 SMD Panasonic/ECG
Resistor, 3.74 kΩ, 1/16 W, 1ꢀ, 0402 SMD Panasonic/ECG
ERJ-2RKF4022X
ERJ-2RKF3741X
R25, R28, R31, R40 to
R45, R49, R52, R57,
R58, R71, R72, R75, R76
1
2
1
1
0
R26
R27, R33
R68
R29
R30
Resistor, 169 kΩ, 1/16 W, 1ꢀ, 0402 SMD
Resistor, 249 Ω, 1/16 W, 1ꢀ, 0402 SMD
Resistor, 147 kΩ, 1/16 W, 1ꢀ, 0402 SMD
Resistor, 226 kΩ, 1/16 W, 1ꢀ, 0402 SMD
Resistor, 140 kΩ, 1/16 W, 1ꢀ, 0402 SMD,
do not install
Panasonic/ECG
Panasonic/ECG
Panasonic/ECG
Panasonic/ECG
Panasonic/ECG
ERJ-2RKF1693X
ERJ-2RKF2490X
ERJ-2RKF1473X
ERJ-2RKF2263X
ERJ-2RKF1403X
1
(R32), R79
Resistor, 107 kΩ, 1/16 W, 1ꢀ, 0402 SMD,
do not install R32
Panasonic/ECG
ERJ-2RKF1073X
1
2
3
2
1
1
2
2
1
1
R47
Resistor, 76.8 kΩ, 1/16 W, 1ꢀ, 0402 SMD Panasonic/ECG
ERJ-2RKF7682X
ERJ-2RKF1003X
ERJ-2GE0R00X
ERJ-2RKF8062X
LRC-LR1206LF-01-R040-F
LRC-LR1206LF-01-R060-F
ERJ-2RKF2552X
EXB-2HV220JV
SMD250F-2
R48, R59
R5, R6, R73
R53, R70
R54
Resistor, 100 kΩ, 1/16 W, 1ꢀ, 0402 SMD
Resistor 0 Ω, 1/16 W, 5ꢀ, 0402 SMD
Resistor 80.6 kΩ, 1/16 W, 1ꢀ, 0402 SMD
Resistor, low value, 1206 SMD, 0.04 Ω
Resistor, low value, 1206 SMD, 0.06 Ω
Panasonic/ECG
Panasonic/ECG
Panasonic/ECG
TT Electronics
TT Electronics
R55
R60, R69
R7, R8
S1
Resistor, 25.5K Ω, 1/16 W, 1ꢀ, 0402 SMD Panasonic/ECG
Resistor array network, 8 Ω to 22 Ω chip
Fuse, PolySwitch SMT (PTC devices)
Panasonic
Tyco
T1
Choke, common-mode coils, wire-
wound type for large current
DLW5AH/DLW5BS series
(2014/2020 Size)
Murata
DLW5BSN191SQ2
1
2
U1
U10, U20
Virtex-4 FPGA
Xilinx
XC4VFX20-10FFG672C
ADP3334ACPZ-REEL7
Voltage regulator, high accuracy, low IQ, Analog Devices
adjustable
2
U11, U15
Voltage regulator, high accuracy
ultralow IQ, 1.5 A
Analog Devices
ADP3339AKCZ-2.5R7
1
1
1
U12
U13
U16
Crystal oscillator, 24 Mhz, 12 pF, SMD
1.8 V, 8 Mb, platform flash-in system
Voltage regulator, 1.5 A ultralow
dropout linear regulator
ECS
Xilinx
ECS-240-12-4X
XCF08PFSG48C
LP38842S-1.2
National Semiconductor
1
0
2
1
U18
Crystal controlled oscillator (100 MHz
fixed frequency oscillator)
156.25 MHz low jitter saw crystal
oscillator, do not install
IC, constant frequency current-mode,
step-down, dc-to-dc controller in TSOT
IC, single inverter buffer/driver with
open-drain output
Connor-Winfield Corp.
Epson Electronics America
Analog Devices
CWX823-100.0M
U19
EG-2121CA 156.2500M-PHPAL3
ADP1864AUJZ-R7
U2, U17
U21
Fairchild Semiconductor
NC7SZ05M5X
1
1
1
U3
U4
U5
IC, EZ-USB FX2LP USB microcontroller
Switch, 5-position, SMT, DIP
IC, 128-bit I2C bus serial EEPROM
Cypress Semiconductor Corp. CY7C68013A-128AXC
CTS
219-5MST
Microchip
24LC00-I/SN
Rev. 0 | Page 29 of 32
HSC-ADC-EVALC
Qty Reference Designator Description
Manufacturer
Part Number
2
U6, U7
IC, P-channel enhancement mode field
effect transistor
Fairchild Semiconductor
NDT456P
1
U8
Voltage regulator, high accuracy
ultralow IQ, 1.5 A
Analog Devices
ADP3339AKCZ-3.3
1
4
1
0
U9
Switch, 6 mm light touch SW, N.O.
Circuit board support on base
Transformer 5 V, 3 A switcher P5
1.2 V precision low noise shunt voltage
references, SOT-23 (RT-3), do not install
Alps
Richco, Inc.
CUI, Inc.
SKHHAKA010
CBSB-14-01
DPS050300U-P5P-TK
ADR512ART
H1, H2, H3, H4
Packed with PCB
U14
Analog Devices
0
0
0
0
0
0
R9
Resistor, 6.2 kΩ, 1/16 W, 5ꢀ, 0402 SMD,
do not install
Resistor, 0 Ω, 1/16 W, 5ꢀ, 0402 SMD,
do not install
Resistor 13 k Ω, 1/16 W, 5ꢀ, 0402 SMD,
do not install
Resistor 1.0 kΩ, 1/16 W, 5ꢀ, 0402 SMD,
do not install
Panasonic/ECG
Panasonic/ECG
Panasonic/ECG
Panasonic/ECG
ERJ-2GEJ622X
ERJ-2GE0R00X
ERJ-2GEJ133X
ERJ-2GEJ102X
ECJ-0EB0J224K
ECJ-0EB0J105M
R12, R13, R14, R51
R11
R10
C8
Capacitor, 0402 SMD, X5R, 6.3 V, 0.22 μF, Panasonic
10ꢀ, do not install
C15
0402 chip capacitor, X5R, 6.3 V, 1 μF,
20ꢀ, do not install
Panasonic
ORDERING GUIDE
Model
ESD CAUTION
Description
HSC-ADC-EVALC
HSC-ADC-EVALCZ1
Data Converter Evaluation Platform
Data Converter Evaluation Platform
1Z = RoHS Compliant Part.
Rev. 0 | Page 30 of 32
HSC-ADC-EVALC
NOTES
Rev. 0 | Page 31 of 32
HSC-ADC-EVALC
NOTES
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
EB06676-0-4/07(0)
Rev. 0 | Page 32 of 32
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