IA186EBPQF80IR2 [ADI]
IC MCU 8BIT ROMLESS 80QFP;
| 型号： | IA186EBPQF80IR2 |
| 厂家： | 
ADI |
| 描述： | IC MCU 8BIT ROMLESS 80QFP 时钟 外围集成电路 |
| 文件： | 总85页 (文件大小：1254K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IA186EB/IA188EB
Data Sheet
8-Bit/16-Bit Microcontrollers
July 10, 2011
IA186EB/IA188EB
8-Bit/16-Bit Microcontrollers
Data Sheet
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Data Sheet
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July 10, 2011
Copyright 2011 by Innovasic Semiconductor, Inc.
Published by Innovasic Semiconductor, Inc.
3737 Princeton Drive NE, Suite 130, Albuquerque, NM 87107
MILES™ is a trademark Innovasic Semiconductor, Inc.
Intel is a registered trademark of Intel Corporation
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July 10, 2011
TABLE OF CONTENTS
Introduction.............................................................................................................................7
1.
2.
1.1 General Description.......................................................................................................7
1.2 Features .........................................................................................................................8
Packaging, Pin Descriptions, and Physical Dimensions.........................................................9
2.1 Packages and Pinouts ....................................................................................................9
2.1.1 IA186EB 84 PLCC Package...........................................................................10
2.1.2 IA188EB 84 PLCC Package...........................................................................12
2.1.3 PLCC Physical Dimensions............................................................................14
2.1.4 IA186EB 80 PQFP Package ...........................................................................15
2.1.5 IA188EB 80 PQFP Package ...........................................................................17
2.1.6 PQFP Physical Dimensions............................................................................19
2.1.7 IA186EB 80 LQFP Package...........................................................................20
2.1.8 IA188EB 80 LQFP Package...........................................................................22
2.1.9 LQFP Physical Dimensions............................................................................24
2.2 IA186EB Pin/Signal Descriptions...............................................................................25
2.3 IA188EB Pin/Signal Descriptions...............................................................................34
Maximum Ratings, Thermal Characteristics, and DC Parameters .......................................42
Functional Description..........................................................................................................44
4.1 Device Architecture.....................................................................................................44
4.1.1 Bus Interface Unit...........................................................................................44
4.1.2 Clock Generator..............................................................................................46
4.1.3 Interrupt Control Unit.....................................................................................47
4.1.4 Timer/Counter Unit ........................................................................................47
4.1.5 Serial Communications Unit...........................................................................47
4.1.6 Chip-Select Unit .............................................................................................47
4.1.7 I/O Port Unit ...................................................................................................48
4.1.8 Refresh Control Unit.......................................................................................48
4.1.9 Power Management Unit ................................................................................48
4.2 Peripheral Architecture ...............................................................................................48
4.3 Reference Documents .................................................................................................51
AC Specifications .................................................................................................................51
5.1 AC Test Conditions.....................................................................................................55
5.2 Clock Input and Clock Output Timing Characteristics...............................................56
5.3 Serial Port Mode 0 Timing Characteristics.................................................................58
Reset Operation ....................................................................................................................59
Bus Timing ...........................................................................................................................59
Instruction Execution Times.................................................................................................69
Errata.....................................................................................................................................77
9.1 Summary .....................................................................................................................77
9.2 Detail ...........................................................................................................................78
3.
4.
5.
6.
7.
8.
9.
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10. Revision History...................................................................................................................83
11. For Additional Information...................................................................................................85
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IA186EB/IA188EB
Data Sheet
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July 10, 2011
LIST OF FIGURES
Figure 1. IA186EB 84-Pin PLCC Package Diagram....................................................................10
Figure 2. IA188EB 84-Pin PLCC Package Diagram....................................................................12
Figure 3. 84-Pin PLCC Physical Package Dimensions ................................................................14
Figure 4. IA186EB 80-Pin PQFP Package Diagram ....................................................................15
Figure 5. IA188EB 80-Pin PQFP Package Diagram ....................................................................17
Figure 6. 80-Pin PQFP Physical Package Dimensions.................................................................19
Figure 7. IA186EB 80-Pin LQFP Package Diagram....................................................................20
Figure 8. IA188EB 80-Pin LQFP Package Diagram....................................................................22
Figure 9. 80-Pin LQFP Physical Package Dimensions.................................................................24
Figure 10. IA186EB/IA188EB Functional Block Diagram..........................................................45
Figure 11. Clock Circuit Connection Options ..............................................................................46
Figure 12. AC Input Characteristics .............................................................................................51
Figure 13. AC Output Characteristics...........................................................................................52
Figure 14. Relative Timing Characteristics ..................................................................................54
Figure 15. AC Test Load ..............................................................................................................55
Figure 16. Clock Input and Clock Output Timing Characteristics ...............................................56
Figure 17. Serial Port Mode 0 Timing Characteristics .................................................................58
Figure 18. Cold Reset Timing.......................................................................................................60
Figure 19. Warm Reset Timing ....................................................................................................61
Figure 20. Read, Fetch, and Refresh Cycle Timing......................................................................62
Figure 21. Write Cycle Timing.....................................................................................................63
Figure 22. Halt Cycle Timing .......................................................................................................64
Figure 23. Interrupt Acknowledge (inta1_n, inta0_n) Cycle Timing ...........................................65
Figure 24. hold/hlda Timing .........................................................................................................66
Figure 25. Refresh During Hold Acknowledge Timing ...............................................................67
Figure 26. Ready Timing..............................................................................................................68
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LIST OF TABLES
Table 1. IA186EB 84-Pin PLCC Pin Listing................................................................................11
Table 2. IA188EB 84-Pin PLCC Pin Listing................................................................................13
Table 3. IA186EB 80-Pin PQFP Pin Listing ................................................................................16
Table 4. IA188EB 80-Pin PQFP Pin Listing ................................................................................18
Table 5. IA186EB 80-Pin LQFP Pin Listing................................................................................21
Table 6. IA188EB 80-Pin LQFP Pin Listing................................................................................23
Table 7. IA186EB Pin/Signal Descriptions ..................................................................................25
Table 8. IA188EB Pin/Signal Descriptions ..................................................................................34
Table 9. IA186EB and IA188EB Absolute Maximum Ratings....................................................42
Table 10. IA186EB and IA188EB Thermal Characteristics.........................................................42
Table 11. IA186EB and IA188EB DC Parameters.......................................................................43
Table 12. Peripheral Control Block Registers ..............................................................................49
Table 13. AC Input Characteristics for 5.0-Volt Operation..........................................................52
Table 14. AC Input Characteristics for 3.3-Volt Operation..........................................................52
Table 15. AC Output Characteristics for 5.0-Volt Operation.......................................................53
Table 16. AC Output Characteristics for 3.3-Volt Operation.......................................................53
Table 17. Relative Timing Characteristics....................................................................................55
Table 18. Clock Input and Clock Output Timing Characteristics for 5.0-Volt Operation ...........56
Table 19. Clock Input and Output Characteristics for 3.3-Volt Operation...................................57
Table 20. Serial Port Mode 0 Timing Characteristics...................................................................58
Table 21. Instruction Set Timing ..................................................................................................69
Table 22. Innovasic Part Number Cross-Reference for the PLCC ...............................................74
Table 23. Innovasic Part Number Cross-Reference for the PQFP................................................75
Table 24. Innovasic Part Number Cross-Reference for the LQFP ...............................................76
Table 25. Summary of Errata........................................................................................................77
Table 26. Revision History ...........................................................................................................83
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IA186EB/IA188EB
Data Sheet
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July 10, 2011
1.
Introduction
The Innovasic Semiconductor IA186EB and IA188EB microcontrollers are form, fit, and
function replacements for the original Intel® 80C186EB, 80C188EB, 80L186EB, and 80L188EB
16-bit high-integration embedded processors.
These devices are produced using Innovasic’s Managed IC Lifetime Extension System
(MILES™). This cloning technology, which produces replacement ICs beyond simple
emulations, ensures complete compatibility with the original device, including any
―undocumented features.‖ Additionally, the MILES process captures the clone design in such a
way that production of the clone can continue even as silicon technology advances.
The IA186EB and IA188EB microcontrollers replace the obsolete Intel 80C186EB and
80C188EB devices, allowing users to retain existing board designs, software
compilers/assemblers, and emulation tools, thereby avoiding expensive redesign efforts.
1.1
General Description
The Innovasic Semiconductor IA186EB and IA188EB microcontrollers are an upgrade for the
80C186EB/80C188EB microcontroller designs with integrated peripherals to provide increased
functionality and reduce system costs. The IA186EB and IA188EB devices are designed to
satisfy requirements of embedded products designed for telecommunications, office automation
and storage, and industrial controls.
The IA186EB and IA188EB microcontrollers have a set of base peripherals beneficial to many
embedded applications and include a standard numeric interface, an interrupt control unit, a chip-
select unit, a DRAM refresh control unit, a power management unit, and three 16-bit
timer/counters.
The IA186EB and IA188EB microcontrollers are capable of operating at 5.0 or 3.3 volts. This
datasheet discusses both modes of operation. Where applicable, characteristics specific to either
3.3 or 5.0 volt operation are identified separately throughout this datasheet.
Additionally, the IA186EB and IA188EB include two integrated serial ports that support both
synchronous and asynchronous communications, simplifying inter-processor and display
communications. The IA186EB and IA188EB also have an enhanced chip-select unit and two
multiplexed I/O ports. The enhanced chip-select unit offers 10 general chip selects, each with
the ability to address up to 1 Mbyte. This enhanced unit enables memory-bank switching to
expand the IA186EB/IA188EB 1 Mbyte address space. The I/O ports allow for basic functions
such as scanning keypads for input. The ports can also be used to control system power
consumption, disabling unneeded components.
The serial ports, I/O capabilities, and enhanced chip selects make the IA186EB/IA188EB an
excellent processor for portable data acquisition or communication applications.
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1.2
Features
The primary features of the IA186EB and IA188EB microcontrollers are as follows:
Low-Power Operating Modes
– Idle (freezes CPU clocks; peripherals are kept active)
– Power-Down (freezes all internal clocks)
Low-Power CPU Core (static)
Direct Addressing Capability
– Memory: 1 Mbyte
– I/O: 64 Kbyte
I/O Ports
– 2 each, 8-Bit
– Multiplexed
Clock Generator
Chip Selects
– 10 each, Programmable
– Integral Wait-State Generator
Memory Refresh Control Unit
Interrupt Controller, Programmable
Counter/Timers
– 3 each, 16-Bit
– Programmable
Serial Channels
– 2 each, UARTs
– Integral Baud Rate Generator
Operating Frequency (system clock input)
– 50 MHz @ 5V
– 32 MHz @ 3.3V
Chapter 4, Functional Description, provides details of the IA186EB and IA188EB
microcontrollers, including the features listed above.
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July 10, 2011
2.
Packaging, Pin Descriptions, and Physical Dimensions
Information on the packages and pin descriptions for the IA186EB and the IA188EB is provided
separately. Refer to sections, figures, and tables for information on the device of interest.
2.1
Packages and Pinouts
The Innovasic Semiconductor IA186EB and IA188EB microcontroller is available in the
following packages:
84-Pin Plastic Leaded Chip Carrier (PLCC), equivalent to original PLCC package
80-Pin Plastic Quad Flat Pack (PQFP), equivalent to original PQFP package
80-Pin Low-Profile Quad Flat Pack (LQFP), equivalent to original SQFP package
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2.1.1 IA186EB 84 PLCC Package
The pinout for the IA186EB 84 PLCC Package is as shown in Figure 1. The corresponding
pinout is provided in Table 1.
Figure 1. IA186EB 84-Pin PLCC Package Diagram
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Table 1. IA186EB 84-Pin PLCC Pin Listing
Pin
1
2
3
4
5
6
7
8
Name
Pin
22 Vss
23 Vcc
24 p1.4/gcs4_n
25 p1.3/gcs3_n
26 p1.2/gcs2_n
27 p1.1/gcs1_n
28 p1.0/gcs0_n
29 lcs_n
30 ucs_n
31 int0
32 int1
33 int2/inta0_n
34 int3/inta1_n
35 int4
36 pdtmr
37 resin_n
38 resout
Name
Pin
43 Vss
44 clkout
45 t0out
46 t0in
47 t1out
48 t1in
49 p2.7
50 p2.6
Name
Pin
64 Vcc
65 Vss
Name
Vcc
Vss
error_n
rd_n
wr_n
ale
bhe_n
s2_n
s1_n
66 ad1
67 ad9
68 ad2
69 ad10
70 ad3
71 ad11
72 ad4
73 ad12
74 ad5
75 ad13
76 ad6
77 ad14
78 ad7
79 ad15
80 a16
81 a17
82 a18
83 a19/once_n
84 Vss
9
51 cts0_n
52 txd0
53 rxd0
10 s0_n
11 den_n
12 hlda
13 hold
14 test_n/busy
15 lock_n
16 dt/r_n
17 nmi
18 ready
54 p2.5/bclk0
55 p2.3/sint1
56 p2.4/cts1_n
57 p2.0/rxd1
58 p2.1/txd1
59 p2.2/bclk1
60 ncs_n
61 ad0
39 pereq
40 oscout
41 clkin
19 p1.7/gcs7_n
20 p1.6/gcs6_n
21 p1.5/gcs5_n
62 ad8
63 Vss
42 Vcc
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2.1.2 IA188EB 84 PLCC Package
The pinout for the IA188EB 84 PLCC Package is as shown in Figure 2. The corresponding
pinout is provided in Table 2.
Figure 2. IA188EB 84-Pin PLCC Package Diagram
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Table 2. IA188EB 84-Pin PLCC Pin Listing
Pin
1
2
3
4
5
6
7
8
Name
Pin
22 Vss
23 Vcc
24 p1.4/gcs4_n
25 p1.3/gcs3_n
26 p1.2/gcs2_n
27 p1.1/gcs1_n
28 p1.0/gcs0_n
29 lcs_n
30 ucs_n
31 int0
32 int1
33 int2/inta0_n
34 int3/inta1_n
35 int4
36 pdtmr
37 resin_n
38 resout
Name
Pin
43 Vss
44 clkout
45 t0out
46 t0in
47 t1out
48 t1in
49 p2.7
50 p2.6
Name
Pin
64 Vcc
65 Vss
66 ad1
67 a9
Name
Vcc
Vss
Not Connected
rd_n
wr_n
68 ad2
69 a10
70 ad3
71 a11
72 ad4
73 a12
74 ad5
75 a13
76 ad6
77 a14
78 ad7
79 a15
80 a16
81 a17
82 a18
ale
rfsh_n
s2_n
s1_n
9
51 cts0_n
52 txd0
53 rxd0
10 s0_n
11 den_n
12 hlda
54 p2.5/bclk0
55 p2.3/sint1
56 p2.4/cts1_n
57 p2.0/rxd1
58 p2.1/txd1
59 p2.2/bclk1
60 Not Connected
61 ad0
13 hold
14 test_n
15 lock_n
16 dt/r_n
17 nmi
18 ready
19 p1.7/gcs7_n
20 p1.6/gcs6_n
21 p1.5/gcs5_n
39 Not Connected
40 oscout
41 clkin
62 a8
63 Vss
83 a19/once_n
84 Vss
42 Vcc
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2.1.3 PLCC Physical Dimensions
The physical dimensions for the 84 PLCC are as shown in Figure 3.
Legend:
Symbol
Min
0.165˝
0.090˝
Nom
–
–
1.190˝
1.154˝
1.190˝
1.154˝
1.110˝
1.110˝
Max
0.180˝
0.120˝
Note: The bottom package is bigger
than the top package by 0.004
inches (0.002 inches per side).
Bottom package dimensions follow
those stated in this drawing.
A
A1
D
D1
E
E1
F
F1
–
–
–
–
–
–
–
–
–
–
–
–
Figure 3. 84-Pin PLCC Physical Package Dimensions
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2.1.4 IA186EB 80 PQFP Package
The pinout for the IA186EB 80 PQFP Package is as shown in Figure 4. The corresponding
pinout is provided in Table 3.
Figure 4. IA186EB 80-Pin PQFP Package Diagram
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Table 3. IA186EB 80-Pin PQFP Pin Listing
Pin
1
2
3
4
5
6
7
8
Name
cts0_n
txd0
Pin
Name
Pin
41 s1_n
42 s0_n
43 den_n
44 hlda
45 hold
46 test_n
47 lock_n
48 nmi
49 ready
50 p1.7/gcs7_n
51 p1.6/gcs6_n
52 p1.5/gcs5_n
53 Vss
Name
Pin
61 ucs_n
62 int0
Name
21 ad4
22 ad12
23 ad5
24 ad13
25 ad6
26 ad14
27 ad7
28 ad15
29 a16
30 a17
31 a18
32 a19/once_n
33 Vss
34 Vcc
35 Vss
36 rd_n
37 wr_n
38 ale
rxd0
63 int1
p2.5/bclk0
p2.3/sint1
p2.4/cts1_n
p2.0/rxd1
p2.1/txd1
p2.2/bclk1
64 int2/inta0_n
65 int3/inta1_n
66 int4
67 pdtmr
68 resin_n
69 resout
70 oscout
71 clkin
72 Vcc
9
10 ad0
11 ad8
12 Vss
13 Vcc
14 Vss
15 ad1
16 ad9
17 ad2
18 ad10
19 ad3
20 ad11
73 Vss
54 Vcc
74 clkout
75 t0out
76 t0in
77 t1out
78 t1in
55 p1.4/gcs4_n
56 p1.3/gcs3_n
57 p1.2/gcs2_n
58 p1.1/gcs1_n
59 p1.0/gcs0_n
60 lcs_n
39 bhe_n
40 s2_n
79 p2.7
80 p2.6
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2.1.5 IA188EB 80 PQFP Package
The pinout for the IA188EB 80 PQFP Package is as shown in Figure 5. The corresponding
pinout is provided in Table 4.
Figure 5. IA188EB 80-Pin PQFP Package Diagram
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Table 4. IA188EB 80-Pin PQFP Pin Listing
Pin
1
2
3
4
5
6
7
8
Name
cts0_n
txd0
Pin
Name
Pin
41 s1_n
42 s0_n
43 den_n
44 hlda
45 hold
46 test_n
47 lock_n
48 nmi
49 ready
50 p1.7/gcs7_n
51 p1.6/gcs6_n
52 p1.5/gcs5_n
53 Vss
Name
Pin
61 ucs_n
62 int0
Name
21 ad4
22 a12
23 ad5
24 a13
25 ad6
26 a14
27 ad7
28 a15
29 a16
30 a17
31 a18
32 a19/once_n
33 Vss
34 Vcc
35 Vss
36 rd_n
37 wr_n
38 ale
rxd0
63 int1
p2.5/bclk0
p2.3/sint1
p2.4/cts1_n
p2.0/rxd1
p2.1/txd1
p2.2/bclk1
64 int2/inta0_n
65 int3/inta1_n
66 int4
67 pdtmr
68 resin_n
69 resout
70 oscout
71 clkin
72 Vcc
9
10 ad0
11 a8
12 Vss
13 Vcc
14 Vss
15 ad1
16 a9
17 ad2
18 a10
19 ad3
20 a11
73 Vss
54 Vcc
74 clkout
75 t0out
76 t0in
77 t1out
78 t1in
55 p1.4/gcs4_n
56 p1.3/gcs3_n
57 p1.2/gcs2_n
58 p1.1/gcs1_n
59 p1.0/gcs0_n
60 lcs_n
39 rfsh_n
40 s2_n
79 p2.7
80 p2.6
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2.1.6 PQFP Physical Dimensions
The physical dimensions for the 80 PQFP are as shown in Figure 6.
Legend:
Millimeter
Inch
Symbol Min Nom Max Min Nom Max
A
A1
A2
D
D1
E
–
0.25
–
–
3.40
– 0.010
–
–
–
0.134
–
2.55 2.72 3.050.1000.1070.120
23.90 Basic
20.00 Basic
17.90 Basic
14.00 Basic
0.941 Basic
0.787 Basic
0.705 Basic
0.551 Basic
E1
R2 0.013
R1 0.013
–
–
0.300.005
– 0.005
–
–
0.012
–
θ
0° 3.5° 7° 0° 3.5° 7°
θ1
0°
–
–
0°
–
–
a
b
7° REF
7° REF
θ2, θ3
15° REF
15° REF
θ2, θ3
c
L
0.11 0.15 0.230.0040.0060.009
0.73 0.88 1.030.0290.0350.041
L1
S
b
1.95 REF
0.40
0.30 0.35 0.450.0120.0140.018
0.077 REF
–
– 0.016
–
–
e
D2
E2
0.80 BSC
18.40 REF
12.00 REF
0.031 BSC
0.724
0.472
Tolerances of Form and Position
Notes:
aaa
bbb
ccc
0.25
0.20
0.20
0.010
0.008
0.008
1. Dimension D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25mm per side. Dimension D1
and E1 do not include mold mismatch and are determined
a datum plane –H– .
2. Dimension b does not include dambar protrusion.
Allowable dambar protrusion will not cause the lead width
to exceed the maximum b dimension by more than
0.08mm. Dambar cannot be located on the lower radius of
the lead foot.
a
b
Alloy 42 L/F.
Copper L/F.
Figure 6. 80-Pin PQFP Physical Package Dimensions
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2.1.7 IA186EB 80 LQFP Package
The pinout for the IA186EB 80 LQFP Package is as shown in Figure 7. The corresponding
pinout is provided in Table 5.
Figure 7. IA186EB 80-Pin LQFP Package Diagram
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Table 5. IA186EB 80-Pin LQFP Pin Listing
Pin
1
2
3
4
5
6
7
8
Name
hlda
hold
test_n
lock_n
nmi
ready
p1.7/gcs7_n
p1.6/gcs6_n
p1.5/gcs5_n
Pin
Name
Pin
Name
Pin
61 ad13
62 ad6
63 ad14
64 ad7
65 ad15
66 a16
67 a17
68 a18
69 a19/once_n
70 Vss
Name
21 int2/inta0_n
22 int3/inta1_n
23 int4
24 pdtmr
25 resin_n
26 resout
27 oscout
28 clkin
41 p2.5/bclk0
42 p2.3/sint1
43 p2.4/cts1_n
44 p2.0/rxd1
45 p2.1/txd1
46 p2.2/bclk1
47 ad0
48 ad8
49 Vss
50 Vcc
9
29 Vcc
30 Vss
10 Vss
11 Vcc
31 clkout
32 t0out
33 t0in
34 t1out
35 t1in
36 p2.7
37 p2.6
38 cts0_n
39 txd0
40 rxd0
51 Vss
52 ad1
53 ad9
54 ad2
55 ad10
56 ad3
57 ad11
58 ad4
59 ad12
60 ad5
71 Vcc
72 Vss
12 p1.4/gcs4_n
13 p1.3/gcs3_n
14 p1.2/gcs2_n
15 p1.1/gcs1_n
16 p1.0/gcs0_n
17 lcs_n
18 ucs_n
19 int0
20 int1
73 rd_n
74 wr_n
75 ale
76 bhe_n
77 s2_n
78 s1_n
79 s0_n
80 den_n
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2.1.8 IA188EB 80 LQFP Package
The pinout for the IA188EB 80 LQFP Package is as shown in Figure 8. The corresponding
pinout is provided in Table 6.
Figure 8. IA188EB 80-Pin LQFP Package Diagram
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Table 6. IA188EB 80-Pin LQFP Pin Listing
Pin
1
2
3
4
5
6
7
8
Name
hlda
hold
test_n
lock_n
nmi
ready
p1.7/gcs7_n
p1.6/gcs6_n
p1.5/gcs5_n
Pin
Name
Pin
Name
Pin
Name
21 int2/inta0_n
22 int3/inta1_n
23 int4
24 pdtmr
25 resin_n
26 resout
27 oscout
28 clkin
29 Vcc
41 p2.5/bclk0
42 p2.3/sint1
43 p2.4/cts1_n
44 p2.0/rxd1
45 p2.1/txd1
46 p2.2/bclk1
47 ad0
48 a8
49 Vss
50 Vcc
61 a13
62 ad6
63 a14
64 ad7
65 a15
66 a16
67 a17
68 a18
69 a19/once_n
70 Vss
9
10 Vss
30 Vss
11 Vcc
31 clkout
32 t0out
33 t0in
34 t1out
35 t1in
36 p2.7
37 p2.6
38 cts0_n
39 txd0
40 rxd0
51 Vss
52 ad1
53 a9
54 ad2
55 a10
56 ad3
57 a11
58 ad4
71 Vcc
72 Vss
12 p1.4/gcs4_n
13 p1.3/gcs3_n
14 p1.2/gcs2_n
15 p1.1/gcs1_n
16 p1.0/gcs0_n
17 lcs_n
18 ucs_n
19 int0
20 int1
73 rd_n
74 wr_n
75 ale
76 rfsh_n
77 s2_n
78 s1_n
79 s0_n
80 den_n
59 a12
60 ad5
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2.1.9 LQFP Physical Dimensions
The physical dimensions for the 80 LQFP are as shown in Figure 9.
Legend:
Dimension in mm
Dimension in Inch
. To be determined at seating plane C.
. Dimensions D1 and E1 do not include
mold protrusion. D1 and E1 are
maximum plastic body size
dimensions including mold mismatch.
. Dimension b does not include dambar
protrusion. Dambar cannot be located
on the lower radius of the foot.
. Exact shape of each corner is
optional.
. These dimensions apply to the flat
section of the lead between 0.10 and
0.25mm from the lead tip.
. A1 is defined as the distance from the
seating plane to the lowest point of the
package body.
Symbol Min Nom Max
Min
–
Mom
–
–
Max
0.063
0.006
A
A1
A2
b
b1
c
c1
D
D1
E
–
–
1.60
0.05
–
0.15 0.002
1.35 1.40 1.45 0.053 0.055 0.057
0.17 0.22 0.27 0.007 0.009 0.011
0.17 0.20 0.23 0.007 0.008 0.009
0.09
0.09
–
–
0.20 0.004
0.16 0.004
–
–
0.008
0.006
14.00 BSC
12.00 BSC
14.00 BSC
12.00 BSC
0.50 BSC
0.551 BSC
0.472 BSC
0.551 BSC
0.472 BSC
0.020 BSC
E1
e
L
0.45 0.60 0.75 0.018 0.024 0.030
L1
R1
R2
S
1.00 REF
0.039 REF
0.08
0.08
0.20
0°
–
–
–
3.5°
–
–
0.003
–
–
–
3.5°
–
12°
12°
–
0.008
–
7°
–
13°
13°
0.20 0.003
–
7°
–
0.008
0°
0°
11°
11°
θ
Notes:
θ 1
θ 2
θ 3
0°
1. Exact shape of each corner is optional.
11°
11°
12°
12°
13°
13°
2. Controlling dimension: mm.
Figure 9. 80-Pin LQFP Physical Package Dimensions
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2.2
IA186EB Pin/Signal Descriptions
Descriptions of the pin and signal functions for the IA186EB microcontroller are provided in
Table 7.
Several of the IA186EB pins have different functions depending on the operating mode of the
device. Each of the different signals supported by a pin is listed and defined in Table 7—
indexed alphabetically in the first column of the table. Additionally, the name of the pin
associated with the signal as well as the pin numbers for the PLCC, LQFP, and PQFP packages
are provided in the ―Pin‖ column. Signals not used in a specific package type are designated
―NA.‖
Table 7. IA186EB Pin/Signal Descriptions
Pin
Signal
Description
Name
a16
PLCC
80
LQFP
66
PQFP
29
a16
(output
only)
address Bits [16–19]. Input/Output. These pins
provide the four most-significant bits of the
Address Bus. During the address portion of the
IA186EB bus cycle, Address Bits [16–19] are
presented on the bus and can be latched using
the ale signal (see table entry). During the data
portion of the IA186EB bus cycle, these lines
are driven to a logic 0.
a17
(output
only)
a17
a18
81
82
83
67
68
69
30
31
32
a18
(output
only)
a19
a19/once_n
ad0
ad1
ad2
ad3
ad4
ad5
ad6
ad7
ad8
ad0
ad1
ad2
ad3
ad4
ad5
ad6
ad7
ad8
61
66
68
70
72
74
76
78
62
67
69
71
73
75
77
79
47
52
54
56
58
60
62
64
48
53
55
57
59
61
63
65
10
15
17
19
21
23
25
27
11
16
18
20
22
24
26
28
address/data Bits [0–15]. Input/Output. These
pins provide the multiplexed Address Bus and
Data Bus. During the address portion of the
IA186EB bus cycle, Address Bits [0–15] are
presented on the bus and can be latched using
the ale signal (see next table entry). During the
data portion of the IA186EB bus cycle, 8- or
16-bit data are present on these lines.
ad9
ad9
ad10
ad11
ad12
ad13
ad14
ad15
ad10
ad11
ad12
ad13
ad14
ad15
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Table 7. IA186EB Pin/Signal Descriptions (Continued)
Pin
Signal
ale
Description
Name
ale
PLCC
6
LQFP
75
PQFP
38
address latch enable. Output. Active High.
This signal is used to latch the address
information during the address portion of a bus
cycle.
bclk0
bclk1
bhe_n
p2.5/bclk0
p2.2/bclk1
bhe_n
54
59
7
41
46
76
4
9
baud clock, Serial Port 0. Input. The bclk0 pin
can be used to provide an alternate clock
source for Serial Port 0. The input clock rate
cannot be greater than one-half the operating
frequency of the IA186EB.
baud clock, Serial Port 1. Input. The bclk1 pin
can be used to provide an alternate clock
source for Serial Port 1. The input clock rate
cannot be greater than one-half the operating
frequency of the IA186EB.
39
byte high enable. Output. Active Low. When
bhe_n is asserted (low), it indicates that the
bus cycle in progress is transferring data over
the upper half of the data bus.
bhe_n is
multi-
bhe_n is
multi-
Additionally, bhe_n and ad0 encode the
following bus information:
plexed
with
plexed with
refresh_n
ad0
bhe_n
Bus Status
refresh_n
0
0
1
1
0
1
0
1
Word Transfer
Even Byte Transfer
Odd Byte Transfer
Refresh Operation
Note: bhe_n is multiplexed with refresh_n.
busy
test_n/busy
14
NA
NA
busy. Input. Active High. When the busy
input is asserted, it causes the IA186EB to
suspend operation during the execution of the
Intel 80C187 Numerics Coprocessor
instructions. Operation resumes when the pin
is sampled low. This applies to the PLCC
package only.
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Table 7. IA186EB Pin/Signal Descriptions (Continued)
Pin
Signal
clkin
Description
Name
clkin
PLCC
41
LQFP
28
PQFP
71
clock input. Input. The clkin pin is the input
connection for an external clock. An external
oscillator operating at two times the required
processor operating frequency can be
connected to this pin.
If a crystal is used to supply the clock, it is
connected between the clkin pin and the
oscout pin (see oscout table entry). When a
crystal is connected, it drives an internal Pierce
oscillator to the IA186EB.
clkout
clkout
44
31
74
clock output. Output. The clkout pin provides
a timing reference for inputs and outputs of the
IA186EB. This clock output is one-half the
input clock (clkin) frequency. The clkout
signal has a 50% duty cycle, transitioning every
falling edge of clkin.
cts0_n
cts1_n
den_n
dt/r_n
cts0_n
p2.4/cts1_n
den_n
51
56
11
16
38
43
80
NA
1
6
clear to send, Serial Port 0. Input. Active Low.
When this input is high (i.e., not asserted), data
transmission from Serial Port 0 is inhibited.
When the signal is asserted (low), data
transmission is permitted.
clear to send, Serial Port 1. Input. Active Low.
When this input is high (i.e., not asserted), data
transmission from Serial Port 1 is inhibited.
When the signal is asserted (low), data
transmission is permitted.
data enable. Output. Active Low. This signal
is used to enable of bidirectional transceivers in
a buffered system. The den_n signal is
asserted (low) only when data is to be
transferred on the bus.
data transmit/receive. Output. This signal is
used to control the direction of data flow for
bidirectional buffers in a buffered system.
When dt/r_n is high, the direction indicated is
transmit; when dt/t_n is low, the direction
indicated is receive.
43
NA
dt/r_n
error_n
error_n
3
NA
NA
error. Input. Active Low. When this signal is
asserted (low), it indicates that the last
numerics coprocessor operation resulted in an
exception condition.
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Table 7. IA186EB Pin/Signal Descriptions (Continued)
Pin
Signal
gcs0_n
gcs1_n
gcs2_n
gcs3_n
gcs4_n
gcs5_n
gcs6_n
gcs7_n
hlda
Description
Name
PLCC
28
27
26
25
24
21
20
19
LQFP
16
15
14
13
12
9
PQFP
59
58
57
56
55
52
51
50
p1.0/gcs0_n
p1.1/gcs1_n
p1.2/gcs2_n
p1.3/gcs3_n
p1.4/gcs4_n
p1.5/gcs5_n
p1.6/gcs6_n
p1.7/gcs7_n
hlda
generic chip select n (n = 0–7). Output. Active
Low. When programmed and enabled, each of
these pins provide a chip select signal that will
be asserted (low) whenever the address of a
memory or I/O bus cycle is within the address
space programmed for that output.
8
7
1
12
44
hold acknowledge. Output. Active High.
When hlda is asserted (high), it indicates that
the IA186EB has relinquished control of the
local bus to another bus master in response to
a HOLD request (see next table entry).
When hlda is asserted, the IA186EB data bus
and control signals float, allowing another bus
master to drive the signals directly.
hold
hold
13
2
45
hold. Input. Active High. This signal is a
request indicating that an external bus master
wishes to gain control of the local bus. The
IA186EB will relinquish control of the local bus
between instruction boundaries not conditioned
by a LOCK prefix.
int0
(input)
int1
(input)
int0
(input only)
int1
(input only)
31
32
19
20
62
63
interrupt n (n = 0-4). Input/Output. Active
High. These maskable inputs interrupt program
flow and cause execution to continue at an
interrupt vector of a specific interrupt type as
follows:
int2
int3
int2/inta0_n
int3/inta1_n
33
34
35
21
22
23
64
65
66
int0: Type 12
int1: Type 13
int2: Type 14
int3: Type 15
int4: Type 17
int4
int4
To allow interrupt expansion, int0 and int1 can
be used with the interrupt acknowledge signals
inta0_n and inta1_n (see next table entries) to
serve as external interrupt inputs or interrupt
acknowledge outputs.
(input)
(input only)
inta0_n
int2/inta0_n
33
21
64
interrupt acknowledge 0. Input/Output. Active
Low. This pin provides an interrupt
acknowledge handshake in response to an
interrupt request on the int0 pin (see previous
table entry).
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Table 7. IA186EB Pin/Signal Descriptions (Continued)
Pin
Signal
inta1_n
Description
Name
int3/inta1_n
PLCC
34
LQFP
22
PQFP
65
interrupt acknowledge 1. Input/Output. Active
Low. This pin provides an interrupt
acknowledge handshake in response to an
interrupt request on the int1 pin (see previous
table entry).
lcs_n
lcs_n
29
15
17
4
60
47
lower chip select. Output. Active Low. This
pin provides a chip select signal that will be
asserted (low) whenever the address of a
memory bus cycle is within the address space
programmed for that output.
lock. Output. Active Low. When asserted
(low), this signal indicates that the bus cycle in
progress is cannot be interrupted. While
lock_n is active, the IA186EB will not service
bus requests such as HOLD.
lock_n
lock_n
ncs_n
nmi
ncs_n
nmi
60
17
NA
5
NA
48
numerics coprocessor select. Output. Active
Low. This signal is asserted (low) when the
IA186EB accesses an Intel 80C187 Numerics
Coprocessor.
non-maskable interrupt. Input. Active High.
When the nmi signal is asserted (high) it
causes a Type 2 interrupt to be serviced by the
IA186EB.
Note: The assertion of nmi is latched internally
by the IA186EB.
once_n
a19/once_n
83
69
32
on-circuit emulation. Input. Active Low. Note:
ONCE Mode is used for device testing.
If the once_n pin is driven low during a reset
operation, all IA186EB output and input/output
pins are placed in a high-impedance state.
This pin is weakly held high while resin_n is
active.
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Table 7. IA186EB Pin/Signal Descriptions (Continued)
Pin
Signal
oscout
Description
Name
oscout
PLCC
40
LQFP
27
PQFP
70
oscillator output. Output. The oscout pin is
the output connection for an external crystal
that drives the IA186EB internal Pierce
oscillator. (When an external crystal is used, it
is connected between this pin and the clkin pin.
See clkin table entry.)
Note: If an external oscillator or clock source is
used to drive the IA186EB instead of a crystal,
oscout must be left unconnected (i.e., must
float). When the IA186EB is operating in the
ONCE mode, oscout does not float.
p1.0
p1.1
p1.2
p1.3
p1.4
p1.5
p1.6
p1.7
p2.0
p1.0/gcs0_n
p1.1/gcs1_n
p1.2/gcs2_n
p1.3/gcs3_n
p1.4/gcs4_n
p1.5/gcs5_n
p1.6/gcs6_n
p1.7/gcs7_n
p2.0/rxd1
28
27
26
25
24
21
20
19
57
16
15
14
13
12
9
8
7
44
59
58
57
56
55
52
51
50
7
port 1, Bit [N] (N = 0–7). Output. Each pin of
Port 1, p1.0–p1.7, can function individually as a
general-purpose output line.
port 2, Bit [0]. Input/Output. This pin functions
as a general-purpose I/O line.
p2.1
p2.2
p2.3
p2.4
p2.5
p2.6
p2.1/txd1
p2.2/bclk1
p2.3/sint1
p2.4/cts1_n
p2.5/bclk0
p2.6
58
59
55
56
54
50
45
46
42
43
41
37
8
9
port 2, Bit [1]. Output. This pin functions as a
general-purpose output line.
port 2, Bit [2]. Input. This pin functions as a
general-purpose input line.
port 2, Bit [3]. Output. This pin functions as a
general-purpose output line.
port 2, Bit [4]. Input. This pin functions as a
general-purpose input line.
port 2, Bit [5]. Input. This pin functions as a
general-purpose input line.
port 2, Bit [6]. Input/Output (open drain). This
pin functions as a general-purpose bidirectional
input/output line.
5
6
4
80
p2.7
p2.7
49
36
79
port 2, Bit [7]. Input/Output (open drain). This
pin functions as a general-purpose bidirectional
input/output line.
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Table 7. IA186EB Pin/Signal Descriptions (Continued)
Pin
Signal
pdtmr
Description
Name
pdtmr
PLCC
36
LQFP
24
PQFP
67
power-down timer. Input/Output (push-pull).
Note: The IA186EB enters Powerdown Mode
when the PWRDN bit in the Power Control
Register is set to 1 and a HALT instruction is
executed. Exit from the Powerdown Mode
occurs upon receipt of a non-maskable interrupt
(i.e., assertion of the nmi input) or a reset (i.e.,
assertion of the resin_n input).
The pdtmr pin, which is normally connected to
an external capacitor, determines the amount of
time that the IA186EB waits before resuming
normal operation after an exit from the
Powerdown when a non-maskable interrupt is
received—essentially a delay between the
assertion of the nmi input and the enabling of
the IA186EB internal clocks. The delay
required depends on the start-up characteristics
of the crystal oscillator.
The pdtmr pin does not apply when the
Powerdown Mode is exited by the receipt of a
reset (i.e., the assertion resin_n).
pereq
pereq
39
NA
NA
numerics coprocessor external request. Input.
Active High. When asserted (high), this signal
indicates that a data transfer between an Intel
80C187 Numerics Coprocessor.and memory is
pending. This applies to the PLCC only.
rd_n
rd_n
4
73
6
36
49
read. Output. Active Low. When asserted
(low), rd_n indicates that the accessed memory
or I/O device must drive data from the location
being accessed onto the data bus.
ready. Input. Active High. When asserted
(high) the ready line indicates a bus-cycle
completion. This signal must be active to
terminate any bus cycle unless the IA186EB
Chip-Select Unit is configured to ignore ready.
ready
ready
18
resin_n
resin_n
37
25
68
reset input. Input. Active Low. When resin_n
is asserted (low), the IA186EB immediately
terminates any bus cycle in progress and
assumes an initialized state. All pins are driven
to a known state, and resout (see next table
entry) is asserted.
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Table 7. IA186EB Pin/Signal Descriptions (Continued)
Pin
Signal
resout
Description
Name
resout
PLCC
38
LQFP
26
PQFP
69
reset output. Output. Active High. When
resout is asserted, it indicates that the
IA186EB is being reset. The resout signal will
remain active (high) as long as resin_n
remains active (low).
rxd0
rxd1
rxd0
53
57
40
44
3
7
Receive (rx) data, Serial Port 0. Input/Output.
This pin is the serial data input for Serial Port 0.
During synchronous serial communications,
rxd0 is bidirectional and functions an output for
data transmission (txd0 becomes the clock).
Receive (rx) data, Serial Port 1. Input/Output.
This pin is the serial data input for Serial Port 1.
During synchronous serial communications,
rxd1 is bidirectional and functions an output for
data transmission (txd1 becomes the clock).
p2.0/rxd1
s0_n
s1_n
s2_n
s0_n
s1_n
s2_n
10
9
79
78
77
42
41
40
statusN (N = 0–2). Output. During a bus cycle
the status (i.e., type) of cycle is encoded on
these lines as follows:
s2_n s1_n s0_n Bus Cycle Status
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Interrupt Acknowledge
Read I/O
Write I/O
Processor HALT
Queue Instruction Fetch
Read Memory
Write Memory
8
No Bus Activity
sint1
t0in
p2.3/sint1
t0in
55
46
45
42
33
32
5
serial interrupt, Serial Port 1. Output. Active
High. When sint1 is asserted (high), it
indicates that Serial Port 1 requires service.
timer 0 input. Input. Depending on the Timer
Mode programmed for Timer 0, this input is
used either as clock input or a control signal.
timer 0 output. Output. Depending on the
Timer Mode programmed for Timer 0, this
output can provide a single clock or a
continuous waveform.
76
75
t0out
t0out
t1in
t1in
48
35
78
timer 1 input. Input. Depending on the Timer
Mode programmed for Timer 1, this input is
used either as clock input or a control signal.
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Table 7. IA186EB Pin/Signal Descriptions (Continued)
Pin
Signal
t1out
Description
Name
t1out
PLCC
47
LQFP
34
PQFP
77
timer 1 output. Output. Depending on the
Timer Mode programmed for Timer 1, this
output can provide a single clock or a
continuous waveform.
test_n
test_n/busy
14
3
46
test. Input. Active Low. When the test_n
input is high (i.e., not asserted), it causes the
IA186EB to suspend operation during the
execution of the WAIT instruction. Operation
resumes when the pin is sampled low
(asserted).
txd0
txd1
txd0
p2.1/txd1
ucs_n
52
58
30
39
45
18
2
8
Transmit (tx) data, Serial Port 0. Output. This
pin is the serial data output for Serial Port 0.
During synchronous serial communications,
txd0 becomes the transmit clock (rxd0
functions as an output for data transmission).
Transmit (tx) data, Serial Port 1. Output. This
pin is the serial data output for Serial Port 1.
During synchronous serial communications,
txd1 becomes the transmit clock (rxd1
functions as an output for data transmission).
ucs_n
61
upper chip select. Output. Active Low. This
pin provides a chip select signal that will be
asserted (low) whenever the address of a
memory bus cycle is within the address space
programmed for that output.
vcc
vss
vcc
vss
1, 23, 11, 29, 13, 34, Power (vcc). This pin provides power for the
42, 64 50, 71 54, 72 IA186EB device. It must be connected to a
+5V DC power source.
2, 22, 10, 30, 12, 14, Ground (vss). This pin provides the digital
43, 63, 49, 51, 33, 35, ground (0V) for the IA186EB. It must be
65, 84 70, 72 53, 73 connected to a vss board plane.
wr_n
wr_n
5
74
37
write. Output. Active Low. When asserted
(low), wr_n indicates that data available on the
data bus are to be latched into the accessed
memory or I/O device.
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2.3
IA188EB Pin/Signal Descriptions
Descriptions of the pin and signal functions for the IA188EB microcontroller are provided in
Table 8.
Several of the IA188EB pins have different functions depending on the operating mode of the
device. Each of the different signals supported by a pin is listed and defined in Table 8—
indexed alphabetically in the first column of the table. Additionally, the name of the pin
associated with the signal as well as the pin numbers for the PLCC, LQFP, and LQFP packages
are provided in the ―Pin‖ column.
Table 8. IA188EB Pin/Signal Descriptions
Pin
Signal
a8
a9
Name
a8
a9
a10
a11
a12
a13
a14
a15
PLCC
62
67
69
71
73
75
77
79
80
81
82
83
61
66
68
70
72
74
76
78
6
LQFP
48
53
55
57
59
61
63
65
66
67
68
69
47
52
54
56
58
60
62
64
75
PQFP
11
16
18
20
22
24
26
28
29
30
31
32
10
15
17
19
21
23
25
27
38
Description
address Bits [8-19]. Output. These pins
provide the 12 most-significant bits of the
Address Bus. During the entire IA188EB bus
cycle, Address Bits [8–19] are presented on the
bus and can be latched using the ale signal
(see table entry).
a10
a11
a12
a13
a14
a15
a16
a17
a18
a19
ad0
ad1
ad2
ad3
ad4
ad5
ad6
ad7
ale
a16
a17
a18
a19/once_n
ad0
address/data Bits [0–7]. Input/Output. These
pins provide a multiplexed Address Bus and
Data Bus. During the address portion of the
IA188EB bus cycle, Address Bits [0–7] are
presented on the bus and can be latched using
the ale signal (see next table entry). During the
data portion of the IA188EB bus cycle, 8-bit
data are present on these lines.
ad1
ad2
ad3
ad4
ad5
ad6
ad7
ale
address latch enable. Output. Active High.
This signal is used to latch the address
information during the address portion of a bus
cycle.
bclk0
p2.5/bclk0
54
41
4
baud clock, Serial Port 0. Input. The bclk0 pin
can be used to provide an alternate clock
source for Serial Port 0. The input clock rate
cannot be greater than one-half the operating
frequency of the IA188EB.
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Table 8. IA188EB Pin/Signal Descriptions (Continued)
Pin
Signal
bclk1
Name
p2.2/bclk1
PLCC
59
LQFP
46
PQFP
9
Description
baud clock, Serial Port 1. Input. The bclk1 pin
can be used to provide an alternate clock
source for Serial Port 1. The input clock rate
cannot be greater than one-half the operating
frequency of the IA188EB.
clkin
clkin
41
28
71
clock input. Input. The clkin pin is the input
connection for an external clock. An external
oscillator, operating at two times the required
processor operating frequency, can be
connected to this pin.
If a crystal is used to supply the clock, it is
connected between the clkin pin and the
oscout pin (see oscout table entry). When a
crystal is connected, it drives an internal Pierce
oscillator to the IA188EB.
clkout
clkout
44
31
74
clock output. Output. The clkout pin provides
a timing reference for inputs and outputs of the
IA188EB. This clock output is one-half the input
clock (clkin) frequency. The clkout signal has
a 50% duty cycle, transitioning every falling
edge of clkin.
cts0_n
cts1_n
den_n
dt/r_n
cts0_n
p2.4/cts1_n
den_n
51
56
11
16
38
43
80
NA
1
6
clear to send, Serial Port 0. Input. Active Low.
When this input is high (i.e., not asserted), data
transmission from Serial Port 0 is inhibited.
When the signal is asserted (low), data
transmission is permitted.
clear to send, Serial Port 1. Input. Active Low.
When this input is high (i.e., not asserted), data
transmission from Serial Port 1 is inhibited.
When the signal is asserted (low), data
transmission is permitted.
data enable. Output. Active Low. This signal
is used to enable of bidirectional transceivers in
a buffered system. The den_n signal is
asserted (low) only when data are to be
transferred on the bus.
data transmit/receive. Output. This signal is
used to control the direction of data flow for
bidirectional buffers in a buffered system.
When dt/r_n is high, the direction indicated is
transmit; when dt/t_n is low, the direction
indicated is receive.
43
NA
dt/r_n
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Table 8. IA188EB Pin/Signal Descriptions (Continued)
Pin
Signal
Name
PLCC
28
27
26
25
24
21
20
19
LQFP
16
15
14
13
12
9
PQFP
59
58
57
56
55
52
51
50
Description
gcs0_n p1.0/gcs0_n
gcs1_n p1.1/gcs1_n
gcs2_n p1.2/gcs2_n
gcs3_n p1.3/gcs3_n
gcs4_n p1.4/gcs4_n
gcs5_n p1.5/gcs5_n
gcs6_n p1.6/gcs6_n
gcs7_n p1.7/gcs7_n
generic chip select n (n = 0–7). Output. Active
Low. When programmed and enabled, each of
these pins provide a chip select signal that will
be asserted (low) whenever the address of a
memory or I/O bus cycle is within the address
space programmed for that output.
8
7
hlda
hlda
12
1
44
hold acknowledge. Output. Active High.
When hlda is asserted (high), it indicates that
the IA188EB has relinquished control of the
local bus to another bus master in response to
a HOLD request (see next table entry).
When hlda is asserted, the IA188EB data bus
and control signals are floated, allowing another
bus master to drive the signals directly.
hold
(input)
hold
(input)
13
2
45
hold. Input. Active High. This signal is a
request indicating that an external bus master
wishes to gain control of the local bus. The
IA188EB will relinquish control of the local bus
between instruction boundaries not conditioned
by a lock prefix.
int0
(input)
int1
(input)
int0
(input only)
int1
(input only)
31
32
19
20
62
63
interrupt N (N = 0–4). Input/Output. Active
High. These maskable inputs interrupt program
flow and cause execution to continue at an
interrupt vector of a specific interrupt type as
follows:
int2
int2/inta0_n
int3/inta1_n
33
34
35
21
22
23
64
65
66
int0: Type 12
int1: Type 13
int2: Type 14
int3: Type 15
int4: Type 17
int3
int4 (input)
int4
(input only)
To allow interrupt expansion, int0 and int1 can
be used with the interrupt acknowledge signals
inta0_n and inta1_n (see next table entries) to
serve as external interrupt inputs or interrupt
acknowledge outputs.
inta0_n
int2/inta0_n
33
21
64
interrupt acknowledge 0. Output. Active Low.
This pin provides an interrupt acknowledge
handshake in response to an interrupt request
on the int0 pin (see previous table entry).
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Table 8. IA188EB Pin/Signal Descriptions (Continued)
Pin
Signal
inta1_n
Name
int3/inta1_n
PLCC
34
LQFP
22
PQFP
65
Description
interrupt acknowledge 1. Input/Output. Active
Low. This pin provides an interrupt
acknowledge handshake in response to an
interrupt request on the int1 pin (see previous
table entry).
lcs_n
lcs_n
29
15
17
4
60
47
lower chip select. Input/Output. Active Low.
This pin provides a chip select signal that will be
asserted (low) whenever the address of a
memory bus cycle is within the address space
programmed for that output.
lock. Output. Active Low. When asserted
(low), this signal indicates that the bus cycle in
progress is cannot be interrupted. While
lock_n is active, the IA188EB will not service
bus requests such as HOLD.
lock_n
lock_n
nmi
nmi
17
83
5
48
32
non-maskable interrupt. Input. Active High.
When the nmi signal is asserted (high), it
causes a Type 2 interrupt to be serviced by the
IA188EB.
Note: The assertion of nmi is latched internally
by the IA188EB.
on-circuit emulation. Input. Active Low. Note:
once_n
a19/once_n
69
ONCE Mode is used for device testing.
If the once_n pin is driven low during reset, all
IA188EB output and input/output pins are
placed in a high-impedance state.
This pin is weakly held high while resin_n is
active.
oscout
oscout
40
27
70
oscillator output. Output. The oscout pin is
the output connection for an external crystal
that drives the IA188EB internal Pierce
oscillator. (When an external crystal is used, it
is connected between this pin and the clkin
pin—see clkin table entry.)
Note: If an external oscillator or clock source is
used to drive the IA188EB instead of a crystal,
oscout must be left unconnected (i.e., must
float). When the IA188EB is operating in the
ONCE mode, oscout does not float.
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Table 8. IA188EB Pin/Signal Descriptions (Continued)
Pin
Signal
p1.0
p1.1
p1.2
p1.3
p1.4
p1.5
p1.6
p1.7
p2.0
Name
PLCC
28
27
26
25
24
21
20
19
LQFP
16
15
14
13
12
9
8
7
44
PQFP
59
58
57
56
55
52
51
50
7
Description
p1.0/gcs0_n
p1.1/gcs1_n
p1.2/gcs2_n
p1.3/gcs3_n
p1.4/gcs4_n
p1.5/gcs5_n
p1.6/gcs6_n
p1.7/gcs7_n
p2.0/rxd1
port 1, Bit [N] (N = 0–7). Output. Each pin of
Port 1, p1.0–p1.7, can function individually as a
general-purpose output line.
57
port 2, Bit [0]. Input/Output. This pin functions
as a general-purpose I/O line.
p2.1
p2.2
p2.3
p2.4
p2.5
p2.6
p2.1/txd1
p2.2/bclk1
p2.3/sint1
p2.4/cts1_n
p2.5/bclk0
p2.6
58
59
55
56
54
50
45
46
42
43
41
37
8
9
port 2, Bit [1]. Output. This pin functions as a
general-purpose output line.
port 2, Bit [2]. Input. This pin functions as a
general-purpose input line.
port 2, Bit [3]. Output. This pin functions as a
general-purpose output line.
port 2, Bit [4]. Input. This pin functions as a
general-purpose input line.
port 2, Bit [5]. Input. This pin functions as a
general-purpose input line.
port 2, Bit [6]. Input/Output (open drain). This
pin functions as a general-purpose bidirectional
input/output line.
5
6
4
80
p2.7
p2.7
49
36
79
port 2, Bit [7]. Input/Output (open drain). This
pin functions as a general-purpose bidirectional
input/output line.
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Table 8. IA188EB Pin/Signal Descriptions (Continued)
Pin
Signal
pdtmr
Name
pdtmr
PLCC
36
LQFP
24
PQFP
67
Description
Power-down timer. Input/Output (push-pull).
Note: The IA188EB enters Powerdown Mode
when the PWRDN bit in the Power Control
Register is set to 1 and a HALT instruction is
executed. Exit from the Powerdown Mode
occurs upon receipt of a non-maskable interrupt
(i.e., assertion of the nmi input) or a reset (i.e.,
assertion of the resin_n input).
The pdtmr pin, which is normally connected to
an external capacitor, determines the amount of
time that the IA188EB waits before resuming
normal operation after an exit from the
Powerdown when a non-maskable interrupt is
received—essentially a delay between the
assertion of the nmi input and the enabling of
the IA188EB internal clocks. The delay
required depends on the start-up characteristics
of the crystal oscillator.
The pdtmr pin does not apply when the
Powerdown Mode is exited by the receipt of a
reset (i.e., the assertion resin_n).
rd_n
rd_n
4
73
6
36
49
read. Output. Active Low. When asserted
(low), rd_n indicates that the accessed memory
or I/O device must drive data from the location
being accessed onto the data bus.
ready. Input. Active High. When asserted
(high) the ready line indicates the completion of
a bus cycle. This signal must be active to
terminate any bus cycle unless the IA188EB
Chip-Select Unit is configured to ignore ready.
ready
ready
18
resin_n
resin_n
37
25
68
reset input. Input. Active Low. When resin_n
is asserted (low), the IA188EB immediately
terminates any bus cycle in progress and
assumes an initialized state. All pins are driven
to a known state, and resout (see next table
entry) is asserted.
resout
rfsh_n
resout
rfsh_n
38
7
26
76
69
39
reset output. Output. Active High. When
resout is asserted, it indicates that the IA188EB
is being reset. The resout signal will remain
active (high) as long as resin_n remains active
(low).
refresh. Output. Active Low. When rfsh_n is
asserted (low), it indicates that a refresh cycle is
in progress.
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Table 8. IA188EB Pin/Signal Descriptions (Continued)
Pin
Signal
rxd0
Name
rxd0
PLCC
53
LQFP
40
PQFP
3
Description
Receive (rx) data, Serial Port 0. Input/Output.
This pin is the serial data input for Serial Port 0.
During synchronous serial communications,
rxd0 is bidirectional and functions an output for
data transmission (txd0 becomes the clock).
rxd1
p2.0/rxd1
57
44
7
Receive (rx) data, Serial Port 1. Input/Output.
This pin is the serial data input for Serial Port 1.
During synchronous serial communications,
rxd1 is bidirectional and functions an output for
data transmission (txd1 becomes the clock).
s0_n
s1_n
s2_n
s0_n
s1_n
s2_n
10
9
79
78
77
42
41
40
statusN (N = 0–2). Output. During a bus cycle
the status (i.e., type) of cycle is encoded on
these lines as follows:
s2_n s1_n s0_n Bus Cycle Status
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Interrupt Acknowledge
Read I/O
Write I/O
Processor HALT
Queue Instruction Fetch
Read Memory
Write Memory
8
1
No Bus Activity
sint1
t0in
p2.3/sint1
t0in
55
46
45
42
33
32
5
serial interrupt, Serial Port 1. Output. Active
High. When sint1 is asserted (high), it
indicates that Serial Port 1 requires service.
timer 0 input. Input. Depending on the Timer
Mode programmed for Timer 0, this input is
used either as clock input or a control signal.
timer 0 output. Output. Depending on the
Timer Mode programmed for Timer 0, this
output can provide a single clock or a
continuous waveform.
76
75
t0out
t0out
t1in
t1in
48
47
35
34
78
77
timer 1 input. Input. Depending on the Timer
Mode programmed for Timer 1, this input is
used either as clock input or a control signal.
timer 1 output. Output. Depending on the
Timer Mode programmed for Timer 1, this
output can provide a single clock or a
continuous waveform.
t1out
t1out
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Table 8. IA188EB Pin/Signal Descriptions (Continued)
Pin
Signal
test_n
Name
test_n
PLCC
14
LQFP
3
PQFP
46
Description
test. Input. Active Low. When the test_n input
is high (i.e., not asserted), it causes the
IA188EB to suspend operation during the
execution of the WAIT instruction. Operation
resumes when the pin is sampled low
(asserted).
txd0
txd1
txd0
p2.1/txd1
ucs_n
52
58
30
39
45
18
2
8
Transmit (tx) data, Serial Port 0. Output. This
pin is the serial data output for Serial Port 0.
During synchronous serial communications,
txd0 becomes the transmit clock (rxd0
functions as an output for data transmission).
Transmit (tx) data, Serial Port 1. Output. This
pin is the serial data output for Serial Port 1.
During synchronous serial communications,
txd1 becomes the transmit clock (rxd1
functions as an output for data transmission).
ucs_n
61
upper chip select. Output. Active Low. This
pin provides a chip select signal that will be
asserted (low) whenever the address of a
memory bus cycle is within the address space
programmed for that output.
vcc
vss
vcc
vss
1, 23, 11, 29, 13, 34, Power (vcc). This pin provides power for the
42, 64 50, 71 54, 72 IA188EB device. It must be connected to a +5V
DC power source.
2, 22, 10, 30, 12, 14, Ground (vss). This pin provides the digital
43, 63, 49, 51, 33, 35, ground (0V) for the IA188EB. It must be
65, 84 70, 72 53, 73 connected to a vss board plane.
wr_n
wr_n
5
74
37
write. Output. Active Low. When asserted
(low), wr_n indicates that data available on the
data bus are to be latched into the accessed
memory or I/O device.
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3.
Maximum Ratings, Thermal Characteristics, and DC Parameters
For the Innovasic Semiconductor IA186EB and IA188EB microcontrollers, the absolute
maximum ratings, thermal characteristics, and DC parameters are provided in Tables 9
through 11, respectively.
Table 9. IA186EB and IA188EB Absolute Maximum Ratings
Parameter
Storage Temperature
Supply Voltage with Respect to vss
Rating
−40°C to +125°C
−0.3V to +6.0V
Voltage on Pins other than Supply with Respect to vss −0.3V to +(Vcc + 0.3)V
Table 10. IA186EB and IA188EB Thermal Characteristics
Symbol
TA
PD
ΘJa
Characteristic
Ambient Temperature
Power Dissipation
84-Pin PLCC Package
80-Pin PQFP Package
80-Pin LQFP Package
Average Junction Temperature
Value
-40°C to 85°C
MHz ICC V/1000
30.7
46
52
Units
°C
W
°C/W
TJ
°C
TA + (PD ΘJa)
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Table 11. IA186EB and IA188EB DC Parameters
Symbol
5.0V
Operation
VCC
3.3V
Operation
VCC
Parameter
Min
4.5
Max
5.5
Units
V
Notes
Supply Voltage
Supply Voltage
Input Low Voltage
–
3.0
3.6
V
V
–
VIL
−0.3
0.3
VCC
input
hysteresis on
resin_n =
0.50V
VIH
Input High Voltage
0.7
VCC
–
3.5/2.4
–
VCC
0.3
0.4
–
+
V
–
VOL
VOH
ILEAK
Output Low Voltage Vcc = 5.5V or 3.6V
Output High Voltage Vcc = 4.5V/3.0V
Input Leakage Current for Pins: ad15–ad0,
ad7–ad0 (IA188EB), ready, hold, resin_n; clkin,
test_n, nmi, int4–int0, t0in, t1in, rdx0, bclk0_n,
cts0_n, rxd1, bclk1_n, cts1_n, p2.6, p2.7
Input Leakage Current for Pins (@3.3V): pereq
V
V
µA
IOL = 12mA
IOH = −12 mA
0V ≤ VIN ≤ VCC
± 1
+ .147 +.625
− .147 −.625
mA
mA
VIN = VCC
VIN =0V
Input Leakage Current for Pins (@3.3V):
a19/once_n, a18–a16, lock_n, error_n
Input Leakage Current for Pins (@5V): pereq
+ .227 +.833
− .227 −.833
mA
mA
VIN = VCC
VIN =0V
Input Leakage Current for Pins (@5V):
a19/once_n, a18–a16, lock_n, error_n
Output Leakage Current
ILO
–
± 10
µA
0.45 ≤ VOUT ≤
VCC
IID
CIN
COUT
Supply Current (IDLE) - @ 50 MHz
Input Pin Capacitance
Output Pin Capacitance
–
0
0
90
5
5
mA
pF
pF
–
TF = 1 MHz
TF = 1 MHz
Operating temperature is -40°C to +85°C.
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4.
Functional Description
4.1
Device Architecture
Architecturally, the IA186EB and IA188EB microcontrollers include the following functional
modules:
Bus Interface Unit
Clock Generator
Interrupt Control Unit
Timer/Counter Unit
Serial Communications Unit
Chip-Select Unit
I/O Port Unit
Refresh Control Unit
Power Management Unit
A functional block diagram of the IA186EB/IA188EB is shown in Figure 10. Descriptions of
the functional modules are provided in the following subsections.
4.1.1 Bus Interface Unit
The IA186EB/IA188EB bus controller that generates local bus control signals and uses a
hold/hlda protocol to share the local bus with other bus masters. The bus controller generates
20 address bits, read and write control signals, and bus-cycle status information. A ready input is
used to extend a bus cycle beyond the minimum four clock cycles.
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Figure 10. IA186EB/IA188EB Functional Block Diagram
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4.1.2 Clock Generator
The IA186EB/IA188EB uses an on-chip clock generator to supply internal and external clocks.
The clock generator makes use of a crystal oscillator and includes a divide-by-two counter.
Figure 11 shows the various operating modes of the clock circuit. The clock circuit can use
either a parallel resonant fundamental mode crystal network (A) or a third-overtone mode crystal
network (B), or it can be driven by an external clock source (C).
The following parameters are recommended when choosing a crystal:
Temperature Range
– Application Specific
– ESR (Equivalent Series Resistance): 40 max
– C0 (Shunt Capacitance of Crystal): 7.0 pF max
– CL (Load Capacitance): 20 pF ± 2 pF
– Drive Level: 1 mW max
Figure 11. Clock Circuit Connection Options
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4.1.3 Interrupt Control Unit
The IA186EB/IA188EB can receive interrupts from a number of sources, both internal and
external. The interrupt control unit serves to merge these requests on a priority basis, for
individual service by the CPU. Each interrupt source can be independently masked by the
Interrupt Control Unit (ICU) or all interrupts can be globally masked by the CPU.
Internal interrupt sources include the Timers and Serial Channel 0. External interrupt sources
come from the five input pins int0–int4. The NMI interrupt pin is not controlled by the ICU and
is passed directly to the CPU. Although the Timer and Serial channel each have only one request
input to the ICU, separate vector types are generated to service individual interrupts within the
Timer and Serial channel units.
4.1.4 Timer/Counter Unit
The IA186EB/IA188EB Timer/Counter Unit (TCU) provides three 16-bit programmable timers.
Two of these are highly flexible and are connected to external pins for control or clocking. A
third timer is not connected to any external pins and can only be clocked internally. However, it
can be used to clock the other two timer channels. The TCU can be used to count external
events, time external events, generate non-repetitive waveforms, and generate timed interrupts,
etc.
4.1.5 Serial Communications Unit
The Serial Control Unit (SCU) of the IA186EB/IA188EB contains two independent channels.
Each channel is identical in operation except that only Channel 0 is supported by the integrated
interrupt controller (Channel 1 has an external interrupt pin). Each channel has its own baud rate
generator that is independent of the Timer/Counter Unit, and can be internally or externally
clocked at up to one half the IA186EB/IA188EB operating frequency.
Independent baud rate generators are provided for each of the serial channels. For the
asynchronous modes, the generator supplies an 8x baud clock to both the receive and transmit
register logic. A 1x baud clock is provided in the synchronous mode.
4.1.6 Chip-Select Unit
The IA186EB/IA188EB Chip-Select Unit (CSU) integrates logic that provides up to ten
programmable chip-selects to access both memories and peripherals. In addition, each chip
select can be programmed to automatically insert additional clocks (wait-states) into the current
bus cycle and automatically terminate a bus cycle independent of the condition of the ready input
pin.
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4.1.7 I/O Port Unit
The I/O Port Unit (IPU) on the IA186EB/IA188EB supports two 8-bit channels of input, output,
or input/output operation. Port 1 is multiplexed with the chip select pins and is output only.
Most of Port 2 is multiplexed with the serial channel pins.
4.1.8 Refresh Control Unit
The Refresh Control Unit (RCU) automatically generates a periodic memory read bus cycle to
keep dynamic or pseudo-static memory refreshed. A 9-bit counter controls the number of clocks
between refresh requests.
A 12-bit address generator is maintained by the RCU and is presented on the a1–a12 address
lines during the refresh bus cycle. Address Bits [a13–a19] are programmable to allow the refresh
address block to be located on any 8-Kbyte boundary.
4.1.9 Power Management Unit
The IA186EB/IA188EB Power Management Unit (PMU) is provided to control the power
consumption of the device. The PMU provides three power modes: Active, Idle, and
Powerdown.
Active Mode indicates that all units on the IA186EB/IA188EB are functional and the device
consumes maximum power (depending on the level of peripheral operation). Idle Mode freezes
the clocks of the execution and bus units at a logic zero state (all peripherals continue to operate
normally).
The Powerdown mode freezes all internal clocks at a logic zero level and disables the crystal
oscillator. All internal registers hold their values provided VCC is maintained. Current
consumption is reduced to just transistor junction leakage.
4.2
Peripheral Architecture
The IA186EB/IA188EB has integrated several common system peripherals with a CPU core to
create a compact, yet powerful system. The integrated peripherals are designed to be flexible
and provide logical interconnections between supporting units (e.g., the interrupt control unit
supports interrupt requests from the timer/counters or serial channels). The list of integrated
peripherals includes:
7-Input Interrupt Control Unit
3-Channel Timer/Counter Unit
2-Channel Serial Communications Unit
10-Output Chip-Select Unit
I/O Port Unit
Refresh Control Unit
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Power Management Unit
The registers associated with each integrated peripheral are contained within a 128 16 register
file called the Peripheral Control Block (PCB). The PCB can be located in either memory or I/O
space on any 256-byte address boundary.
Table 12 provides a list of the registers associated with the PCB.
Table 12. Peripheral Control Block Registers
PCB
PCB
PCB
PCB
Offset
Function
Offset
Function
Offset
Function
Offset
Function
00H
02H
Reserved
40H
42H
Timer2
Count
Timer2
80H
82H
GCS0 Start
C0H
C2H
Reserved
End Of
GCS0 Stop
Reserved
Interrupt
Compare
04H
06H
Poll
Poll Status
44H
46H
Reserved
Timer2
Control
84H
86H
GCS1 Start
GCS1 Stop
C4H
C6H
Reserved
Reserved
08H
0AH
Interrupt
Mask
Priority
Mask
48H
4AH
Reserved
88H
8AH
GCS2 Start
GCS2 Stop
C8H
CAH
Reserved
Reserved
Reserved
0CH
0EH
In-Service
Interrupt
Request
4CH
4EH
Reserved
Reserved
8CH
8EH
GCS3 Start
GCS3 Stop
CCH
CEH
Reserved
Reserved
10H
12H
14H
16H
18H
1AH
1CH
1EH
Interrupt
Status
Timer
Control
Serial
Control
INT4
Control
INT0
Control
INT1
Control
INT2
Control
INT3
50H
52H
54H
56H
58H
5AH
5CH
5EH
Port 1
Direction
Port 1 Pin
90H
92H
94H
96H
98H
9AH
9CH
9EH
GCS4 Start
GCS4 Stop
GCS5 Start
GCS5 Stop
GCS6 Start
GCS6 Stop
GCS7 Start
GCS7 Stop
D0H
D2H
D4H
D6H
D8H
DAH
DCH
DEH
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Port 1
Control
Port 1 Latch
Port 2
Direction
Port 2 Pin
Port 2
Control
Port 2 Latch
Control
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Table 12. Peripheral Control Block Registers (Continued)
PCB
PCB
PCB
PCB
Offset
Function
Offset
Function
Offset
Function
Offset
Function
20H
Reserved
60H
Serial0
Baud
A0H
LCS Start
E0H
Reserved
22H
Reserved
Offset
62H
Serial0
Count
Function
A2H
LCS Stop
Function
E2H
Reserved
Function
Reserved
Reserved
Reserved
Reserved
PCB
Offset
PCB
Offset
PCB
Offset
PCB
Offset
24H
26H
28H
2AH
Reserved
Reserved
Reserved
Reserved
64H
66H
68H
6AH
Serial0
Control
Serial0
Status
Serial0
RBUF
Serial0
TBUF
A4H
A6H
A8H
AAH
UCS Start
UCS Stop
Relocation
Reserved
E4H
E6H
E8H
EAH
2CH
2EH
30H
Reserved
Reserved
Timer0
Count
6CH
6EH
70H
Reserved
Reserved
Serial1
Baud
ACH
AEH
B0H
Reserved
Reserved
Refresh
Base
ECH
EEH
F0H
Reserved
Reserved
Reserved
32H
34H
36H
38H
3AH
3CH
3EH
Timer0
Compare A
Timer0
Compare B
Timer0
Control
Timer1
Count
Timer1
Compare A
72H
74H
76H
78H
7AH
7CH
7EH
Serial1
Count
Serial1
Control
Serial1
Status
Serial1
RBUF
B2H
B4H
B6H
B8H
BAH
BCH
BEH
Refresh
Time
Refresh
Control
Refresh
Address
Power
F2H
F4H
F6H
F8H
FAH
FCH
FEH
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Control
Reserved
Serial1
TBUF
Reserved
Timer1
Compare B
Timer1
Control
Step ID1
Reserved
Reserved
Note:
1The Step ID register (offset 0xBC) for Revision 2 of the Innovasic device is read-only, and is
uniquely identified in software by having a value of 0x0080. The original Intel device
established a value between 0x0000 and 0x0002, depending on the revision of the part.
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4.3
Reference Documents
Additional information on the operation and programming of the 80C186EB/80C188EB can be
found in the following Intel publications:
80C186EB/80C188EB and 80L186EB/80L188EB 16-Bit High-Integration Embedded
Processors (272433-006)
80C186EB/80C188EB Microprocessor User’s Manual (270830-00n)
5.
AC Specifications
This chapter defines the AC specifications of the IA186EB/IA188EB. Input characteristics are
provided in Figure 12 and Tables 13 and 14. Output characteristics are provided in Figure 13
and Tables 15 and 16. Relative timing characteristics are provided in Figure 14 and Table 17.
Clock input and clock output timing characteristics are provided in Figure 18 and Tables 18
and 19. Additional timing information is provided in Chapter 7, Bus Timing, and Chapter 8,
Instruction Execution Times.
The following test conditions were used to derive the values in Tables 13 – 16: Rev. 0 was tested
at 100C and 4.75V; Rev. 2 was tested at 100C and 4.5V.
clkout
50%
tCHIH
Min
tCHIS
Min
Valid
tCLIH
Min
tCLIS
Min
Valid
Figure 12. AC Input Characteristics
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For specific 5.0- and 3.3-volt characteristics, refer to Tables 13 and 14, respectively.
Table 13. AC Input Characteristics for 5.0-Volt Operation
Symbol
tCHIS
tCHIH
tCLIS
tCLIS
tCLIH
Pins
Min Max Units
test_n, nmi, int4–int0, bclk1–bclk0, t1in–t0in, ready, cts1_n–cts0_n, p2.6, p2.7 10
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
test_n, nmi, int4–int0, bclk1–bclk0, t1in–t0in, ready, cts1_n–cts0_n
ad15–ad0, ad7–ad0 (IA188EB), ready
hold, pereq, error_n
ad15–ad0, ad7–ad0 (IA188EB), ready
hold, pereq, error_n
3
10
10
3
tCLIH
3
Table 14. AC Input Characteristics for 3.3-Volt Operation
Symbol
tCHIS
tCHIH
tCLIS
tCLIS
tCLIH
Pins
Min Max Units
test_n, nmi, int4–int0, bclk1–bclk0, t1in–t0in, ready, cts1_n–cts0_n, p2.6, p2.7 10
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
test_n, nmi, int4–int0, bclk1–bclk0, t1in–t0in, ready, cts1_n–cts0_n
ad15–ad0, ad7–ad0 (IA188EB), ready
hold, pereq, error_n
ad15–ad0, ad7–ad0 (IA188EB), ready
hold, pereq, error_n
3
10
10
3
tCLIH
3
Figure 13. AC Output Characteristics
For specific 5.0- and 3.3-volt characteristics, refer to Tables 15 and 16, respectively.
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Table 15. AC Output Characteristics for 5.0-Volt Operation
Symbol
tCHOV
Parameter
Min Max Units
ale, s2–s0_n, den_n, dt/r_n, bhe_n, rfsh_n (IA188EB), lock_n, a19–a16
gcs0–gcs7_n, lcs_n, ucs_n, ncs_n, rd_n, wr_n
bhe_n, rfsh_n (IA188EB), den_n, lock_n, resout, hlda, t0out, t1out, a19–a16
rd_n , wr_n, gcs7–gcs0_n, lcs_n, ucs_n, ad15–ad0, ad7–ad0 (IA188EB),
a15–a8 (IA188EB), ncs_n, inta1_n–inta0_n, s2_n–s0_n
3
3
3
3
17
20
17
20
ns
ns
ns
ns
tCLOV
tCHOF
tCLOF
re_n, wr_n, bhe_n, rfsh_n (IA188EB), dt/r_n, lock_n, s2_n–s0_n, a19–a16
den_n, ad15–ad0, ad7–ad0 (IA188EB), a15–a8 (IA188EB)
0
0
20
20
ns
ns
Table 16. AC Output Characteristics for 3.3-Volt Operation
Symbol
tCHOV
Parameter
Min Max Units
ale, s2–s0_n, den_n, dt/r_n, bhe_n, rfsh_n (IA188EB), lock_n, a19–a16
gcs0–gcs7_n, lcs_n, ucs_n, ncs_n, rd_n, wr_n
bhe_n, rfsh_n (IA188EB), den_n, lock_n, resout, hlda, t0out, t1out, a19–a16
rd_n , wr_n, gcs7–gcs0_n, lcs_n, ucs_n, ad15–ad0, ad7–ad0 (IA188EB),
a15–a8 (IA188EB), ncs_n, inta1_n–inta0_n, s2_n–s0_n
3
3
3
3
25
30
25
30
ns
ns
ns
ns
tCLOV
tCHOF
tCLOF
re_n, wr_n, bhe_n, rfsh_n (IA188EB), dt/r_n, lock_n, s2_n–s0_n, a19–a16
0
0
30
30
ns
ns
den_n, ad15–ad0, ad7–ad0 (IA188EB), a15–a8 (IA188EB)
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Figure 14. Relative Timing Characteristics
For specific relative timing characteristics, refer to Table 17.
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Table 17. Relative Timing Characteristics
Symbol
tLHLL
tAVLL
tPLLL
tLLAX
Parameter
ale Rising to ale Falling
Min
Max Units
t – 15
½t –10
½t –10
½t –10
½t –15
½t –15
½t –10
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Ns
Address Valid to ale Falling
Chip Selects Valid to ale Falling
Address Hold from ale Falling
ale Falling to wr_n Falling
ale Falling to rd_n Falling
wr_n Rising to ale Rising
Address Float to rd_n Falling
rd_n Falling to rd_n Rising
wr_n Falling to wr_n Rising
rd_n Rising to Address Active
tLLWL
tLLRL
tWHLH
tAFRL
tRLRH
tWLWH
tRHAV
tWHDX
tWHPH
tRHPH
tPHPL
tOVRH
tRHOX
(2t) – 5
(2t) – 5
t – 15
Output Data Hold after wr_n Rising t – 15
wr_n Rising to Chip Select Rising
rd_n Rising to Chip Select Rising
cs_n inactive to cs_n active
once_n Active to resin_n Rising
once_n Hold to resin_n Rising
½t –10
½t –10
½t –10
t
t
5.1
AC Test Conditions
The AC specifications are tested with the 50-pF load shown in Figure 15. Specifications are
measured at the VCC/2 crossing point unless otherwise specified.
Figure 15. AC Test Load
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5.2
Clock Input and Clock Output Timing Characteristics
For clock input and clock output timing characteristics for both 5.0- and 3.3-volt operation, see
Tables 18 and 19, respectively.
Figure 16. Clock Input and Clock Output Timing Characteristics
Table 18. Clock Input and Clock Output Timing Characteristics for 5.0-Volt Operation
Item
–
Symbol
XTF
Parameter
clkin
Frequency
clkin Period
Min
0
Max
50
Units
MHz
Notes
–
–
1
2
TCKIN
20
10
∞
∞
ns
ns
TCHCK
clkin High
Time
Measure for VIH for high time, NIL for
low time.
3
4
TCLCK
TCKLH
clkin Low
Time
clkin Rise
Time
10
1
∞
ns
ns
Measure for VIH for high time, NIL for
low time.
Only required to guarantee ICC.
Maximum limits are bounded for TC,
TCH, and TCL.
5
5
6
TCKHL
TCICO
clkin Fall
Time
1
5
ns
Only required to guarantee ICC.
Maximum limits are bounded for TC,
TCH, and TCL.
clkin to clkout
Delay
clkout Period
clkout High (TCLCL/2) (TCLCL/2) ns
Time – 5 + 5
clkout Low (TCLCL/2) (TCLCL/2) ns
Time
clkout Rise
Time
0
11.5
ns
ns
Specified for a 50-pF load.
7
8
TCLCL
TCHCL
–
2TCKIN
–
Measure for VIH for high time, NIL for
low time.
Measure for VIH for high time, NIL for
low time.
9
TCCCH
– 5
1
+ 5
6
10 TCH1CH2
11 TCL2CL1
ns
ns
Specified for a 50-pF load.
clkout Fall
Time
1
6
Specified for a 50-pF load.
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Table 19. Clock Input and Output Characteristics for 3.3-Volt Operation
Item Symbol Parameter
Min
0
Max
32
Units Notes
–
XTF
clkin
MHz
–
Frequency
clkin Period
clkin High
Time
1
2
TC
TCH
30
15
∞
∞
ns
ns
–
Measure for VIH for high time, NIL for low
time.
3
4
5
6
TCL
TCR
TCF
clkin Low Time
15
1
∞
5
ns
ns
ns
ns
Measure for VIH for high time, NIL for low
time.
clkin Rise
Time
clkin Fall Time
Only required to guarantee ICC. Maximum
limits are bounded for TC, TCH and TCL.
Only required to guarantee ICC. Maximum
limits are bounded for TC, TCH and TCL.
Specified for a 50-pF load.
1
5
XTCD clkin to clkout
Delay
0
14.5
7
8
T
TPH
clkout Period
clkout High
Time
clkout Low
Time
clkout Rise
Time
clkout Fall
Time
–
2TC
(T/2)
+ 5
(T/2)
+ 5
ns
ns
–
(T/2)
– 5
(T/2)
– 5
1
Measure for VIH for high time, NIL for low
time.
Measure for VIH for high time, NIL for low
time.
Specified for a 50-pF load.
9
TPL
TPR
TPF
ns
ns
ns
10
11
6
1
6
Specified for a 50-pF load.
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5.3
Serial Port Mode 0 Timing Characteristics
Serial Port Mode 0 timing characteristics are illustrated in Figure 17 and collected in Table 20.
Figure 17. Serial Port Mode 0 Timing Characteristics
Table 20. Serial Port Mode 0 Timing Characteristics
Symbol
tXLXL
Parameter
Minimum
t (n +1)
2t – 35
t – 35
Maximum
–
2t + 35
t + 35
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
txd Clock Period
tXLXH
tXLXH
tXHXL
tXHXL
tQVXH
tQVXH
tXHQX
tXHQX
tXHQZ
tDVXH
tXHDX
txd Clock Low to Clock High (n > 1)
txd Clock Low to Clock High (n = 1)
txd Clock High to Clock Low (n > 1)
txd Clock High to Clock Low (n = 1)
rxd Output Data Setup to txd Clock High (n > 1)
rxd Output Data Setup to txd Clock High (n = 1)
rxd Output Data Hold after txd Clock High (n > 1)
rxd Output Data Hold after txd Clock High (n = 1)
rxd Output Data Float after Last txd Clock High
rxd Input Data Setup to txd Clock High
rxd Input Data Hold after txd Clock High
(n – 1) t – 35 (n – 1) t + 35
t – 35
(n – 1) t – 35
t – 35
2t – 35
t – 35
–
t + 35
–
–
–
–
t + 20
–
t + 20
0
–
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6.
Reset Operation
The IA186EB/IA188EB will perform a reset operation any time the resin_n pin is active.
Figure 18 shows the reset sequence when power is applied to the IA186EB/IA188EB. An
external clock connected to clkin must not exceed the VCC threshold being applied to the
processor. This is normally not a problem if the clock driver is supplied with the same VCC that
supplies the processor. When attaching a crystal to the device, resin_n must remain active until
both VCC and clkout are stable (the length of time is application-specific and depends on the
startup characteristics of the crystal circuit). The resin_n pin is designed to operate correctly
using an RC reset circuit, but the designer must ensure that the ramp time for VCC is not so long
that resin_n is never really sampled at a logic low level when VCC reaches minimum operating
conditions.
Note: Failure to assert resin_n while the device is powering up will result in unpredictable
operation.
Figure 19, Warm Reset Timing, shows the timing sequence when resin_n is applied after Vcc is
stable and the device has been operating. Any bus operation that is in progress at the time
resin_n is asserted will terminate immediately.
While resin_n is active, bus signals lock_n, a19/once_n, and a18–a16 are configured as inputs
and weakly held high by internal pull-up transistors. Only a19/ once_n can be overdriven to a
low-to-enable ONCE Mode.
7.
Bus Timing
Figures 18 through 26 on the following pages present the various bus cycles that are generated
by the processor. The figures show the relationship of the various bus signals to clkout.
Together with the information present in AC Characteristics, the figures allow the user to
determine all the critical timing analysis needed for a given application.
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Figure 18. Cold Reset Timing
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Figure 19. Warm Reset Timing
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ad15-ad0 (IA186EB);
ad7-ad0 (IA188EB)
gcs7_n - gcs0_n,
lcs_n, ucs_n
Figure 20. Read, Fetch, and Refresh Cycle Timing
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gcs7_n - gcs0_n,
lcs_n, ucs_n
Figure 21. Write Cycle Timing
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Figure 22. Halt Cycle Timing
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Figure 23. Interrupt Acknowledge (inta1_n, inta0_n) Cycle Timing
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s2_n–s0_n
a19/once_n,
a18–a16
bhe_n (IA186EB),
rfsh_n (IA188EB)
ad15–ad0 (IA186EB);
a15–a8, ad7–ad0
(IA188EB)
gcs7_n–gcs0_n,
ucs_n, lcs_n
Figure 24. hold/hlda Timing
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s2_n–s0_n
a19/once_n,
a18–a16
wr_n, lock_n;
bhe_n (IA186EB);
rfsh_n (IA188EB)
ad15–ad0 (IA186EB);
a15–a8, ad7–ad0
(IA188EB)
gcs7_n–gcs0_n,
ucs_n, lcs_n
Figure 25. Refresh During Hold Acknowledge Timing
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Figure 26. Ready Timing
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8.
Instruction Execution Times
Table 21 provides IA186EB and IA188EB execution times, mnemonic instruction, and
additional information on execution, if required. The execution times apply to all versions of the
parts.
Table 21. Instruction Set Timing
Clock Cycles
Instruction
IA186EB
IA188EB
Comments
AAA
AAD
AAM
AAS
3
6
40
3
3
6
40
3
–
–
–
–
ADC Immediate to accumulator
1
1
–
–
ADC Immediate to
register/memory
3
13
ADC Register/memory with
register to either
1/16
1/24
register/memory
ADD Immediate to accumulator
1
1
–
ADD Immediate to
1/19
1/32
register/memory
register/memory
ADD Register/memory with
register either
1/20
1/28
AND Immediate to accumulator
1
1
–
AND Immediate to
register/memory
AND Register/memory and
register to either
BOUND
1/24
1/33
register/memory
1/12
1/15
Interrupt not taken/Interrupt taken
20/40
24/64
CBW
CLC
1
1
4
1
–
–
CLD
1
1
–
CLI
1
1
–
CMC
2
2
–
CMPS
CS
9
1
20
1
–
–
CWD
1
1
–
DAA
4
4
–
DAS
2
2
–
DEC Register
DEC Register/memory
1
1/24
1
1/32
–
register/memory
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Table 21. Instruction Set Timing (Continued)
Clock Cycles
Instruction
DIV Memory-Byte
IA186EB
IA188EB
46
Comments
46
49
39
39
46
49
39
39
–
–
–
–
–
–
–
DIV Memory-Word
DIV Register-Byte
DIV Register-Word
IDIV Memory-Byte
IDIV Memory-Word
IDIV Register-Byte
IDIV Register-Word
51
39
39
46
51
39
39
–
IMUL Immediate (signed)
IMUL Memory-Byte
5/24
4
5/33
20
register/memory
–
IMUL Memory-Word
IMUL Register-Byte
13
5
28
5
–
–
IMUL Register-Word
5
5
–
INC Register
1
1
–
INS
8
16
–
INS (repeated n times)
INT Type specified
INT Type 3
INTO
IRET
JA
JAE
JB
JBE
JCXZ
JE
JG
JGE
JL
JLE
8+8n
33
33
33
30
3/5
3/5
3/5
3/5
3/4
3/5
3/5
3/5
3/5
3/5
3
16+16n
41
–
–
–
–
41
48
30
–
3/5
3/5
3/5
3/5
3/4
3/5
3/5
3/5
3/5
3/5
3
Jump not taken/Jump taken
Jump not taken/Jump taken
Jump not taken/Jump taken
JMP Direct intersegment
–
JMP Direct within segment
3
3
–
JMP Short/long
JNA
JNAE
JNB
JNBE
JNE
JNG
JNGE
JNL
JNLE
JNO
4
4
–
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
Jump not taken/Jump taken
JNP
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Table 21. Instruction Set Timing (Continued)
Clock Cycles
IA186EB
Instruction
IA188EB
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
2
Comments
Jump not taken/Jump taken
JNS
JNZ
JO
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
2
JP
JPE
JPO
JS
JZ
LAHF
LDS
LEA
LEAVE
LES
LOCK
LODS
–
1/24
3
12
12
1
1/33
3
12
32
1
register/memory
–
–
–
–
8
12
–
LODS (repeated n times)
LOOP
LOOPE
LOOPNE
LOOPNZ
8+8n
3/4
3/4
3/4
3/4
3/4
5
12+12n
3/4
3/4
3/4
3/4
3/4
8/12
1
–
Loop not taken/Loop taken
Loop not taken/Loop taken
LOOPZ
MOV Accumulator to memory
MOV Immediate to register
MOV Immediate to
register/memory
MOV Memory to accumulator
MOV Register to
Register/Memory
MOV Register/memory to
register
MOV Register/memory to
segment register
MOV Segment register to
register/memory
MOVS
MOVS (repeated n times)
MUL Memory-Byte
MUL Memory-Word
MUL Register-Byte
MUL Register-Word
NEG
8-bit/16-bit
1
1/5
-
register/memory
1/12
5
2/5
8-bit/16-bit
register/memory
8/12
2/20
2/5
2/5
2/5
2/20
2/20
2/20
24
24+24n
16
15
5
5
1/32
1
–
–
–
–
–
–
32
32+32n
20
25
5
5
1/15
1
register/memory
NOP
–
NOT
1/24
1
register/memory
1/24
1
OR Immediate to accumulator
–
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Table 21. Instruction Set Timing (Continued)
Clock Cycles
Instruction
OR Immediate to
IA186EB
1/32
IA188EB
1/32
Comments
register/memory
register/memory
OR Register/memory and
register to either
1/32
1/24
OUT Fixed port
OUT Variable port
OUTS
5
5
8
8-bit/16-bit
8/12
12
12/20
–
8-bit/16-bit
OUTS (repeated n times)
POP Memory
POP Register
POP Segment register
POPA
POPF
PUSH Immediate
PUSH Memory
PUSH Register
PUSH Segment register
PUSHA
PUSHF
RET Inter-segment
RET Inter-segment adding
immediate to SP
RET Within segment
RET Within segment adding
immediate to SP
ROL Register/Memory by 1
ROL Register/Memory by CL
ROL Register/Memory by
Count
8+8n
10
10
16
80
13
8
15
4
4
8-bit/16-bit
12/20+12/20n
–
–
–
–
–
–
–
–
–
–
–
–
–
20
12
12
93
13
12
28
12
12
72
16
21
21
64
4
14
25
14
16
–
–
13
13
1/8
1/8
1/8
register/memory
1/16
1/16
1/24
ROR Register/Memory by 1
ROR Register/Memory by CL
ROR Register/Memory by
Count
1/8
1/8
1/8
1/16
1/16
1/24
SAHF
SBB Immediate from
accumulator
2
1
–
–
2
1
SBB Immediate from
register/memory
SBB Register/memory and
register to either
1/15
1/11
register/memory
register/memory
1/28
1/40
SCAS
11
11+8n
5
8-bit/16-bit
8-bit/16-bit
register/memory
8/12
8/12+8/12n
1/32
SCAS (repeated n times)
SHL Register/Memory by 1
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Table 21. Instruction Set Timing (Continued)
Clock Cycles
Instruction
SHL Register/Memory by CL
IA186EB
1/20
IA188EB
1/24
Comments
register/memory
SHL Register/Memory by
Count
1/11
1/24
SHR Register/Memory by 1
1/5
1/24
1/28
1/24
SHR Register/Memory by CL
1/20
1/11
SHR Register/Memory by
Count
SS
STC
1
1
1
–
–
-
1
1
1
SUB Immediate from
accumulator
SUB Immediate from
register/memory
SUB Register/memory and
register to either
STD
STI
STOS
STOS (repeated n times)
TEST Immediate data and
accumulator
1/11
1/15
register/memory
1/28
1/40
1
1
6
–
–
–
–
–
1
1
8
6+4n
1
8+8n
1
TEST Immediate data and
register/memory
TEST Register/memory and
register
1/16
1/12
register/memory
register/memory
1/16
1/20
WAIT
XCHG Register with
accumulator
1
2
test_n = 0
1
2
–
XCHG Register/memory with
register
3/16
register/memory
3/20
XLAT
16
1
–
8
1
XOR Immediate to accumulator
–
XOR Immediate to
register/memory
1/11
1/32
register/memory
XOR Register/memory and
register to either
1/16
1/32
register/memory
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Innovasic Part Number Cross-Reference
Tables 22 through 24 cross-reference the Innovasic part number with the corresponding Intel part
number.
Table 22. Innovasic Part Number Cross-Reference for the PLCC
Innovasic Part Number
IA186EBPLC84IR2
lead free (RoHS-compliant) EE80C186EB20
EN80C186EB25
EN80C186EB20
EN80C186EB13
N80C186EB25
Intel Part Number
EE80C186EB25
Package Type
84-Pin PLCC
Temperature Grades
Commercial and
industrial
N80C186EB20
N80C186EB13
TN80C186EB25
TN80C186EB20
TN80C186EB13
N80L186EB16
N80L186EB13
TN80L186EB16
TN80L186EB13
EN80L186EB13
IA188EBPLC84IR2
EE80C188EB25
84-Pin PLCC
Commercial and
industrial
lead free (RoHS-compliant) EE80C188EB20
EE80C188EB13
EN80C188EB25
EN80C188EB20
EN80C188EB13
N80C188EB25
N80C188EB20
N80C188EB13
TN80C188EB25
TN80C188EB20
TN80C188EB13
EE80L188EB16
EN80L188EB13
N80L188EB16
N80L188EB13
TN80L188EB16
TN80L188EB13
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Table 23. Innovasic Part Number Cross-Reference for the PQFP
Innovasic Part Number
IA186EBPQF80IR2
lead free (RoHS-compliant) ES80C186EB20
ES80C186EB13
S80C186EB25
Intel Part Number
EG80C186EB25
Package Type
80-Pin PQFP
Temperature Grades
Commercial and
industrial
S80C186EB20
S80C186EB13
TS80C186EB25
TS80C186EB20
TS80C186EB13
EG80L186EB16
EG80L186EB13
S80L186EB16
S80L186EB13
TS80L186EB16
TS80L186EB13
IA188EBPQF80IR2
lead free (RoHS-compliant) ES80C188EB20
S80C188EB25
EG80C188EB25
80-Pin PQFP
Commercial and
industrial
S80C188EB20
S80C188EB13
TS80C188EB25
TS80C188EB20
TS80C188EB13
ES80L188EB13
TS80L188EB16
TS80L188EB13
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Table 24. Innovasic Part Number Cross-Reference for the LQFP
Innovasic Part Number
Intel Part
Package Type
Temperature Grades
Number
YW80C186EB25
YW80C186EB20
SB80C186EB25
SB80C186EB20
SB80C186EB13
YW80L186EB16
YW80L186EB13
SB80L186EB16
SB80L186EB13
YW80C188EB25
YW80C188EB20
SB80C188EB25
SB80C188EB20
SB80C188EB13
YW80L188EB16
YW80L188EB13
SB80L188EB16
SB80L188EB13
IA186EBPLQ80IR2
lead free (RoHS-compliant)
Commercial and
industrial
80-Pin LQFP
IA188EBPLQ80IR2
lead free (RoHS-compliant)
Commercial and
industrial
80-Pin LQFP
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9.
Errata
The following errata are associated with Version 0 of the IA186EB/IA188EB. A workaround to
the identified problem has been provided where possible.
9.1
Summary
Table 25 presents a summary of errata.
Table 25. Summary of Errata
Errata No.
Problem
Ver. 0
Exists
Ver. 2
Fixed
Alternate Mode (TxCON[1] == 1) for timer 0 and 1 has some functional
issues.
1
2
3
When the extension byte (mod field) is set to ―11,‖ some instructions will
Exists
Exists
Fixed
Fixed
cause the CPU to hang.
When the chip is put in SFNM mode for INT0 or INT1, the LVL bit is
automatically set for those interrupts.
4
5
6
Timer 2 will stop or not start counting.
Exists
Exists
Exists
Fixed
Fixed
Fixed
Write does not occur when counter is actively counting.
Program Counter can become corrupted if an interrupt occurs.
Bound instruction uses bad data when index addresses are on odd
boundary in memory.
7
8
9
Exists
Exists
Exists
Fixed
Exists
Exists
Pin LOCK_n does not have an internal pullup and will float during reset
and bus hold.
The Relocation Register (RELREG, PCB offset 0xA8) can only be modified
by an 8-bit write.
When the timer compare register for any of the timers is set to x0000, the
max count is xFFFF instead of x10000 as in the OEM part.
10
11
Exists
-
Exists
Exists
NMI cannot bring chip out of powerdown mode.
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Errata No.
Problem
Ver. 0
Exists
Ver. 2
Exists
12
13
14
Illegal serial port modes do not match OEM part.
Non-maskable interrupt (NMI) can be pre-empted by maskable interrupt.
Ready signal may not be recognized in bus cycles with zero wait states.
Exists
Exists
Exists
Exists
9.2
Detail
Errata No. 1
Problem: Alternate Mode (TxCON[1] == 1) for timer 0 and 1 has some functional issues.
Description:
TxOUT will continuously toggle at 1/2 CLKOUT regardless of count register values.
The maxcount compare will not work. The live count will compare against TxCMPA and
TxCMPB in alternate cycles. This could cause a compare (and the associated interrupt,
or switch the intended compare, or stop counting altogether) to occur early or not at all.
The TxOUT pin may start in the wrong state if the user writes to TxCON register
Bit [12].
When in retrigger mode, Timer 1 will not function correctly. Input pulses on T0IN will
cause counter to begin counting.
Workaround: None.
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Errata No. 2
Problem: When the extension byte (mod field) is set to ―11,‖ some instructions will cause the
CPU to hang.
Description: Although there are faster versions of each instruction (these are not commonly
used by compilers), the following instructions will cause the CPU to hang when the extension
byte (mod field) is set to ―11‖:
8D (LEA)
8F (POP memory)
C6 (MOV immediate8 to memory/register)
C7 (MOV immediate16 to memory/register)
FE (PUSH memory)
FF (PUSH memory)
Workaround: Substitute instructions in the following table.
Instruction
Workaround
Use MOV register (89 or 8B)
8D (LEA)
8F (POP memory)
Use POP register (0101_0xxx)
C6 (MOV immediate8 to memory/register)
Use MOV immediate8 to register (1011_0xxx)
C7 (MOV immediate16 to memory/register) Use MOV immediate16 to register (1011_1xxx)
FE (PUSH memory)
FF (PUSH memory)
Use PUSH register (0101_0xxx)
Use PUSH register (0101_0xxx)
Errata No. 3
Problem: When the chip is put in SFNM mode for INT0 or INT1, the LVL bit is automatically
set for those interrupts.
Workaround: None.
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Errata No. 4
Problem: Timer 2 will stop or not start counting.
Description: Writing a logic ―1‖ to unused bits in the timer control register can cause the timer
to stop counting or to never start counting.
Workaround: Do not write a logic ―1‖ to any unused or reserved bits in the timer control
register.
Errata No. 5
Problem: Write does not occur when counter is actively counting.
Description: If a timer incremented its count register to the currently active compare register
during a write to that count register, the write would not occur.
Workaround: Do not write count register while that counter is actively counting.
Errata No. 6
Problem: Program Counter can become corrupted if an interrupt occurs.
Description: If an interrupt occurs during the decode stage of a TEST instruction using an
opcode of the form 1111_0111_1100_0xxx, the Program Counter could become corrupted upon
returning from the interrupt handler.
Workaround: None.
Errata No. 7
Problem: Bound instruction uses bad data when index addresses are on odd boundary in
memory.
Description: BOUND instruction will use bad data if index address LSB is a ―1‖ in memory.
Workaround: None.
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Errata No. 8
Problem: Pin LOCK_n does not have an internal pullup.
Description: Because Pin LOCK_n does not have an internal pullup, it will float during reset
and bus hold.
Workaround: An external pullup may be necessary if there is high external load on the signal.
Errata No. 9
Problem:
The Relocation Register (RELREG, PCB offset 0xA8) can only be modified by an 8-bit write.
Description: The Relocation Register (RELREG, PCB offset 0xA8) can only be modified by an
8-bit write. A 16-bit write will have no effect. The 186 EB is unaffected.
Workaround: Use an 8-bit access to affect the RELREG register.
Errata No. 10
Problem:
When the timer compare register for any of the timers is set to x0000, the max count is xFFFF
instead of x10000 as in the OEM part.
Description: The timer output will change one count earlier than it should when the max count
is set to x0000.
Workaround: The workaround is application dependent. Please contact Innovasic Technical
Support if this erratum is an issue.
Errata No. 11
Problem:
NMI cannot bring chip out of powerdown mode.
Description: Only a reset brings the part out of powerdown after a HLT instruction is executed
with the PWRDN bit set in the PWRCON register.
Workaround: Use IDLE instead of PWRDN.
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Errata No. 12
Problem:
Illegal serial port modes do not match OEM part.
Description: If the mode bits of the serial control register (S1CON, S0CON) are set to an
illegal encoding (0x5, 0x6, or 0x7), the Innovasic part acts as though it were in mode 4. The
OEM part acts as if it were in mode 1.
Workaround: Use a valid encoding for serial mode.
Errata No. 13
Problem:
Non-maskable interrupt (NMI) can be pre-empted by maskable interrupt.
Description: When instruction execution unit is in Decode state for 2 or more consecutive
cycles and an NMI is recognized, it could be pre-empted by a maskable interrupt.
Workaround: None.
Errata No. 14
Problem:
Ready signal may not be recognized in bus cycles with zero wait states.
Description: When a chip select is set to use the ready signal to extend a bus cycle that
normally has no wait states (Start register bits 3-0 == 0000), the ready signal may not be
recognized in time to extend the bus cycle.
Workaround: Set wait states to 1 or more if using ready to extend bus cycles.
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Revision History
Table 26 presents the sequence of revisions to document IA211080314.
Table 26. Revision History
Date
Revision
Description
First edition released.
Page(s)
July 30, 2008
00
NA
Pin number range ―ad15–a8‖ corrected to ―a15–
a8‖ in Figures 26 and 27. Errata No. 4 added.
[Also cover page, header, footer, and errata
chapter reformatted to meet publication
standards.]
October 13, 2008
January 14, 2009
01
02
66, 67, 78, 79, 80, 81
Updated errata table for Version 00 – added 3
errata (#5 – 7).
81, 83
Updated instruction set timing for 186EB;
Changed 188EB column to TBD pending
completion of new tests; Updated Table 9 ratings;
Updated Table 11 parameters and ratings;
Removed Figures 16 and 17, and reordered
subsequent figures; Updates Table 18 ratings and
notes; Updated Table 19 parameters, ratings and
notes.
March 29, 2009
03
42, 43, 55, 56, 68-72
Added availability of a non-RoHS compliant
version of the 188EB in the 80-pin LQFP package.
Added two errata for Version 2 of the device.
Noted that all other errata have been fixed in
Version 2.
April 24, 2009
May 5, 2009
04
05
75, 76, 79
51, 68
Noted the test conditions used to derive the
values in Tables 13 -16; Noted that the Instruction
Set Timing in Table 21 applies to all versions of
the parts.
Updated Figures 4, 5 and 10. Updated Tables 3,
4, 6, 7, 8, 12. Updated Table 21 to provide revised
instruction set timing for the 186EB and to add
instruction set timing for the 188EB, based on the
most recent test results.
15-18, 23, 25-41, 45,
48, 50, 68-72
May 18, 2009
June 4, 2009
06
07
Updated VOH parameter on Table 11; corrected
labels on Figures 20-21; Added Errata 10.
43, 61, 62, 80
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Date
Revision
Description
Page(s)
Added a note to Table 12 regarding the Step ID
register.
September 4, 2009
08
50
Elimination of pages with SnPb lead plating
options
February 25, 2011
March 23, 2011
09
10
74-76
70
Updated Instruction Set Timing Table to
incorporate DIV and IDIV values.
June 12, 2011
July 5, 2011
July 10, 2011
11
12
13
Added Errata 11 and 12.
Added Errata 13.
77, 78, 81
78, 82
Added Errata 14.
78, 82
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10. For Additional Information
The Innovasic Semiconductor IA186EB and IA188EB microcontrollers are form, fit, and
function replacements for the original Intel® 80C186EB, 80C188EB, 80L186EB, and 80L188EB
16-bit high-integration embedded processors.
The Innovasic Support Team wants our information to be complete, accurate, useful, and easy to
understand. Please feel free to contact our experts at Innovasic at any time with suggestions,
comments, or questions.
Innovasic Support Team
3737 Princeton NE
Suite 130
Albuquerque, NM 87107
(505) 883-5263
Fax: (505) 883-5477
Toll Free: (888) 824-4184
E-mail: support@innovasic.com
Website: http://www.Innovasic.com
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