JM13903BCA [ADI]
Internally Trimmed Integrated Circuit Multiplier; 内部微调集成电路乘法器
| 型号： | JM13903BCA |
| 厂家： | 
ADI |
| 描述： | Internally Trimmed Integrated Circuit Multiplier |
| 文件： | 总7页 (文件大小：139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Internally Trimmed
a
Integrated Circuit Multiplier
AD532
FEATURES
PIN CONFIGURATIONS
Pretrimmed to ؎1.0% (AD532K)
Y
2
No External Components Required
Guaranteed ؎1.0% max 4-Quadrant Error (AD532K)
Diff Inputs for (X1 – X2) (Y1 – Y2)/10 V Transfer Function
Monolithic Construction, Low Cost
1
2
3
4
5
6
7
14 +V
S
Z
V
OS
Y
1
13
12
11
10
9
OUT
Y
1
2
+V
S
GND
–V
Y
S
AD532
TOP VIEW
(Not to Scale)
AD532
TOP VIEW
(Not to Scale)
NC
NC
NC
V
OS
APPLICATIONS
Multiplication, Division, Squaring, Square Rooting
Algebraic Computation
Power Measurements
Instrumentation Applications
Available in Chip Form
Z
X
2
GND
X
2
X
8
X
1
NC
OUT
1
–V
S
NC = NO CONNECT
2
3
1
20 19
18
Y
4
5
6
–V
2
S
17
16
NC
V
NC
NC
AD532
TOP VIEW
OS
15 NC
14
NC 7
(Not to Scale)
PRODUCT DESCRIPTION
8
GND
NC
The AD532 is the first pretrimmed single chip monolithic multi-
plier/divider. It guarantees a maximum multiplying error of
±1.0% and a ±10 V output voltage without the need for any
external trimming resistors or output op amp. Because the
AD532 is internally trimmed, its simplicity of use provides
design engineers with an attractive alternative to modular multi-
pliers, and its monolithic construction provides significant ad-
vantages in size, reliability and economy. Further, the AD532
can be used as a direct replacement for other IC multipliers that
require external trim networks (such as the AD530).
9
10 11 12 13
NC = NO CONNECT
GUARANTEED PERFORMANCE OVER TEMPERATURE
The AD532J and AD532K are specified for maximum multi-
plying errors of ±2% and ±1% of full scale, respectively at
+25°C, and are rated for operation from 0°C to +70°C. The
AD532S has a maximum multiplying error of ±1% of full scale
at +25°C; it is also 100% tested to guarantee a maximum error
of ±4% at the extended operating temperature limits of –55°C
and +125°C. All devices are available in either the hermetically-
sealed TO-100 metal can, TO-116 ceramic DIP or LCC packages.
J, K and S grade chips are also available.
FLEXIBILITY OF OPERATION
The AD532 multiplies in four quadrants with a transfer func-
tion of (X1 – X2)(Y1 – Y2)/10 V, divides in two quadrants with
a 10 V Z/(X1 – X2) transfer function, and square roots in one
quadrant with a transfer function of ±√10 V Z. In addition to
these basic functions, the differential X and Y inputs provide
significant operating flexibility both for algebraic computation and
transducer instrumentation applications. Transfer functions,
such as XY/10 V, (X2 – Y2)/10 V, ±X2/10 V and 10 V Z/(X1 – X2),
are easily attained and are extremely useful in many modulation
and function generation applications, as well as in trigonometric
calculations for airborne navigation and guidance applications,
where the monolithic construction and small size of the AD532
offer considerable system advantages. In addition, the high
CMRR (75 dB) of the differential inputs makes the AD532
especially well qualified for instrumentation applications, as it
can provide an output signal that is the product of two transducer-
generated input signals.
ADVANTAGES OF ON-THE-CHIP TRIMMING OF THE
MONOLITHIC AD532
1. True ratiometric trim for improved power supply rejection.
2. Reduced power requirements since no networks across sup-
plies are required.
3. More reliable since standard monolithic assembly techniques
can be used rather than more complex hybrid approaches.
4. High impedance X and Y inputs with negligible circuit
loading.
5. Differential X and Y inputs for noise rejection and additional
computational flexibility.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
(@ +25؇C, VS = ؎15 V, R ≥ 2 k⍀ VOS grounded)
AD532–SPECIFICATIONS
AD532J
Typ
AD532K
Typ
AD532S
Typ
Model
Min
Max
Min
Max
Min
Max
Units
MULTIPLIER PERFORMANCE
(X1 – X2 )(Y1 –Y2 )
10V
(X1 – X2 )(Y1 –Y2 )
10V
(X1 – X2 )(Y1 –Y2 )
10V
Transfer Function
Total Error (–10 V ≤ X, Y ≤ +10 V)
TA = Min to Max
Total Error vs. Temperature
Supply Rejection (±15 V ± 10%)
Nonlinearity, X (X = 20 V pk-pk, Y = 10 V)
Nonlinearity, Y (Y = 20 V pk-pk, X = 10 V)
Feedthrough, X (Y Nulled,
±1.5
±2.5
±0.04
±0.05
±0.8
±0.3
؎2.0
±0.7
±1.5
±0.03
±0.05
±0.5
±0.2
؎1.0
±0.5
؎1.0
%
%
%/°C
%/%
%
؎4.0
؎0.04
±0.01
±0.05
±0.5
±0.2
%
X = 20 V pk-pk 50 Hz)
Feedthrough, Y (X Nulled,
Y = 20 V pk-pk 50 Hz)
Feedthrough vs. Temperature
Feedthrough vs. Power Supply
50
200
150
30
100
80
30
100
80
mV
30
2.0
±0.25
25
1.0
±0.25
25
1.0
±0.25
mV
mV p-p/°C
mV/%
DYNAMICS
Small Signal BW (VOUT = 0.1 rms)
1% Amplitude Error
Slew Rate (VOUT 20 pk-pk)
Settling Time (to 2%, ∆VOUT = 20 V)
1
1
1
MHz
kHz
V/µs
µs
75
45
1
75
45
1
75
45
1
NOISE
Wideband Noise f = 5 Hz to 10 kHz
Wideband Noise f = 5 Hz to 5 MHz
0.6
3.0
0.6
3.0
0.6
3.0
mV (rms)
mV (rms)
OUTPUT
Output Voltage Swing
Output Impedance (f ≤ 1 kHz)
Output Offset Voltage
Output Offset Voltage vs. Temperature
Output Offset Voltage vs. Supply
±10
±13
1
±40
0.7
±2.5
±10
±13
1
±10
±13
1
V
Ω
mV
mV/°C
mV/%
؎30
؎30
2.0
0.7
±2.5
±2.5
±10
INPUT AMPLIFIERS (X, Y and Z)
Signal Voltage Range (Diff. or CM
Operating Diff)
±10
±10
V
CMRR
40
50
50
dB
Input Bias Current
X, Y Inputs
X, Y Inputs TMIN to TMAX
Z Input
Z Input TMIN to TMAX
Offset Current
Differential Resistance
3
10
±10
±30
±0.3
10
1.5
8
±5
±25
±0.1
10
4
1.5
8
±5
±25
±0.1
10
4
µA
µA
µA
µA
µA
MΩ
؎15
؎15
DIVIDER PERFORMANCE
Transfer Function (X > X2)
10 V Z/(X1 – X2)
10 V Z/(X1 – X2)
10 V Z/(X1 – X2)
l
Total Error
(VX = –10 V, –10 V ≤ VZ ≤ +10 V)
(VX = –1 V, –10 V ≤ VZ ≤ +10 V)
±2
±4
±1
±3
±1
±3
%
%
SQUARE PERFORMANCE
(X1 – X2 )2
10V
(X1 – X2 )2
(X1 – X2 )2
10V
Transfer Function
Total Error
10V
±0.4
±0.8
±0.4
%
%
SQUARE ROOTER PERFORMANCE
Transfer Function
Total Error (0 V ≤ VZ ≤ 10 V)
–√10 V Z
±1.5
–√10 V Z
±1.0
–√10 V Z
±1.0
POWER SUPPLY SPECIFICATIONS
Supply Voltage
Rated Performance
Operating
Supply Current
±15
±15
±10
±15
V
V
±10
؎18
؎18
±10
±22
Quiescent
4
6
4
6
4
6
mA
PACKAGE OPTIONS
TO-116 (D-14)
TO-100 (H-10A)
LCC (E-20A)
AD532JD
AD532JH
AD532KD
AD532KH
AD532SD
AD532SH
AD532SE/883B
Specifications subject to change without notice.
Thermal Characteristics
Specifications shown in boldface are tested on all production units at final
electrical test. Results from those tests are used to calculate outgoing quality
levels. All min and max specifications are guaranteed, although only those shown
in boldface are tested on all production units.
H-10A: θJC = 25°C/W; θJA = 150°C/W
E-20A: θJC = 22°C/W; θJA = 85°C/W
D-14: θJC = 22°C/W; θJA = 85°C/W
REV. B
–2–
AD532
ORDERING GUIDE
CHIP DIMENSIONS AND BONDING DIAGRAM
Contact factory for latest dimensions.
Temperature
Ranges
Package
Descriptions
Package
Options
Dimensions shown in inches and (mm).
Model
AD532JD
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
–55°C to +125°C
–55°C to +125°C
Side Brazed DIP
Side Brazed DIP
Side Brazed DIP
Side Brazed DIP
Header
Header
Chip
Side Brazed DIP
Side Brazed DIP
Side Brazed DIP
LCC
Header
Header
D-14
D-14
D-14
D-14
H-10A
H-10A
AD532JD/+
AD532KD
AD532KD/+
AD532JH
AD532KH
AD532J Chip
AD532SD
AD532SD/883B
JM38510/13903BCA –55°C to +125°C
AD532SE/883B
AD532SH
AD532SH/883B
D-14
D-14
D-14
E-20A
H-10A
H-10A
H-10A
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
JM38510/13903BIA –55°C to +125°C
AD532S Chip –55°C to +125°C
Header
Chip
FUNCTIONAL DESCRIPTION
The functional block diagram for the AD532 is shown in Figure
1, and the complete schematic in Figure 2. In the multiplying
and squaring modes, Z is connected to the output to close the
feedback around the output op amp. (In the divide mode, it is
used as an input terminal.)
The X and Y inputs are fed to high impedance differential am-
plifiers featuring low distortion and good common-mode rejec-
tion. The amplifier voltage offsets are actively laser trimmed
to zero during production. The product of the two inputs is
resolved in the multiplier cell using Gilbert’s linearized trans-
conductance technique. The cell is laser trimmed to obtain
VOUT = (X1 – X2)(Y1 – Y2)/10 volts. The built-in op amp is used
to obtain low output impedance and make possible self-contained
operation. The residual output voltage offset can be zeroed at
VOS in critical applications . . . otherwise the VOS pin should be
grounded.
Figure 1. Functional Block Diagram
Figure 2. Schematic Diagram
–3–
REV. B
AD532
AD532 PERFORMANCE CHARACTERISTICS
AC FEEDTHROUGH
Multiplication accuracy is defined in terms of total error at
+25°C with the rated power supply. The value specified is in
percent of full scale and includes XIN and YIN nonlinearities,
feedback and scale factor error. To this must be added such
application-dependent error terms as power supply rejection,
common-mode rejection and temperature coefficients (although
worst case error over temperature is specified for the AD532S).
Total expected error is the rms sum of the individual compo-
nents since they are uncorrelated.
AC feedthrough is a measure of the multiplier’s zero suppres-
sion. With one input at zero, the multiplier output should be
zero regardless of the signal applied to the other input. Feed-
through as a function of frequency for the AD532 is shown in
Figure 5. It is measured for the condition VX = 0, VY = 20 V
(p-p) and VY = 0, VX = 20 V (p-p) over the given frequency
range. It consists primarily of the second harmonic and is mea-
sured in millivolts peak-to-peak.
Accuracy in the divide mode is only a little more complex. To
achieve division, the multiplier cell must be connected in the
feedback of the output op amp as shown in Figure 13. In this
configuration, the multiplier cell varies the closed loop gain of
the op amp in an inverse relationship to the denominator volt-
age. Thus, as the denominator is reduced, output offset, band-
width and other multiplier cell errors are adversely affected. The
divide error and drift are then ⑀m × 10 V/X1 – X2) where ⑀m
represents multiplier full-scale error and drift, and (X1–X2) is
the absolute value of the denominator.
NONLINEARITY
Nonlinearity is easily measured in percent harmonic distortion.
The curves of Figures 3 and 4 characterize output distortion as
a function of input signal level and frequency respectively, with
one input held at plus or minus 10 V dc. In Figure 4 the sine
wave amplitude is 20 V (p-p).
Figure 5. Feedthrough vs. Frequency
COMMON-MODE REJECTION
The AD532 features differential X and Y inputs to enhance its
flexibility as a computational multiplier/divider. Common-mode
rejection for both inputs as a function of frequency is shown in
Figure 6. It is measured with X1 = X2 = 20 V (p-p), (Y1 – Y2) =
+10 V dc and Y1 = Y2 = 20 V (p-p), (X1 – X2) = +10 V dc.
Figure 6. CMRR vs. Frequency
Figure 3. Percent Distortion vs. Input Signal
Figure 4. Percent Distortion vs. Frequency
Figure 7. Frequency Response, Multiplying
REV. B
–4–
AD532
DYNAMIC CHARACTERISTICS
NOISE CHARACTERISTICS
The closed loop frequency response of the AD532 in the multi-
plier mode typically exhibits a 3 dB bandwidth of 1 MHz and
rolls off at 6 dB/octave thereafter. Response through all inputs is
essentially the same as shown in Figure 7. In the divide mode,
the closed loop frequency response is a function of the absolute
value of the denominator voltage as shown in Figure 8.
All AD532s are screened on a sampling basis to assure that
output noise will have no appreciable effect on accuracy. Typi-
cal spot noise vs. frequency is shown in Figure 10.
Stable operation is maintained with capacitive loads to 1000 pF
in all modes, except the square root for which 50 pF is a safe
upper limit. Higher capacitive loads can be driven if a 100 Ω
resistor is connected in series with the output for isolation.
Figure 10. Spot Noise vs. Frequency
APPLICATIONS CONSIDERATIONS
The performance and ease of use of the AD532 is achieved
through the laser trimming of thin-film resistors deposited di-
rectly on the monolithic chip. This trimming-on-the-chip tech-
nique provides a number of significant advantages in terms of
cost, reliability and flexibility over conventional in-package
trimming of off-the-chip resistors mounted or deposited on a
hybrid substrate.
Figure 8. Frequency Response, Dividing
First and foremost, trimming on the chip eliminates the need
for a hybrid substrate and the additional bonding wires that are
required between the resistors and the multiplier chip. By trim-
ming more appropriate resistors on the AD532 chip itself, the
second input terminals that were once committed to external
trimming networks (e.g., AD530) have been freed to allow fully
differential operation at both the X and Y inputs. Further, the
requirement for an input attenuator to adjust the gain at the Y
input has been eliminated, letting the user take full advantage of
the high input impedance properties of the input differential
amplifiers. Thus, the AD532 offers greater flexibility for both
algebraic computation and transducer instrumentation
applications.
POWER SUPPLY CONSIDERATIONS
Although the AD532 is tested and specified with ±15 V dc
supplies, it may be operated at any supply voltage from ±10 V
to ±18 V for the J and K versions, and ±10 V to ±22 V for the S
version. The input and output signals must be reduced propor-
tionately to prevent saturation; however, with supply voltages
below ±15 V, as shown in Figure 9. Since power supply sensitiv-
ity is not dependent on external null networks as in the AD530
and other conventionally nulled multipliers, the power supply
rejection ratios are improved from 3 to 40 times in the AD532.
Finally, provision for fine trimming the output voltage offset has
been included. This connection is optional, however, as the
AD532 has been factory-trimmed for total performance as
described in the listed specifications.
REPLACING OTHER IC MULTIPLIERS
Existing designs using IC multipliers that require external trim-
ming networks (such as the AD530) can be simplified using the
pin-for-pin replaceability of the AD532 by merely grounding
the X2, Y2 and VOS terminals. (The VOS terminal should always
be grounded when unused.)
Figure 9. Signal Swing vs. Supply
REV. B
–5–
AD532
single-ended positive inputs (0 V to +10 V), connect the input
to X2 and the offset null to X1. For optimum performance, gain
(S.F.) and offset (X0) adjustments are recommended as shown
and explained in Table I.
APPLICATIONS
MULTIPLICATION
Z
X
1
For practical reasons, the useful range in denominator input is
approximately 500 mV ≤ |(X1 – X2)| ≤ 10 V. The voltage offset
adjust (VOS), if used, is trimmed with Z at zero and (X1 – X2) at
full scale.
X
2
V
AD532
OUT
OUT
Y
1
V
Y
2
OS
(X – X ) (Y – Y )
1
2
10V
1
2
V
=
OUT
(OPTIONAL)
20k⍀
Table I. Adjust Procedure (Divider or Square Rooter)
+V
–V
S
S
Figure 11. Multiplier Connection
DIVIDER
SQUARE ROOTER
Adjust
Adjust
for:
For operation as a multiplier, the AD532 should be connected
as shown in Figure 11. The inputs can be fed differentially to
the X and Y inputs, or single-ended by simply grounding the
unused input. Connect the inputs according to the desired po-
larity in the output. The Z terminal is tied to the output to close
the feedback loop around the op amp (see Figure 1). The offset
adjust VOS is optional and is adjusted when both inputs are zero
volts to obtain zero out, or to buck out other system offsets.
With:
With:
for:
Adjust
X
Z
VOUT
Z
VOUT
–10 V
–1 V
Scale Factor –10 V +10 V –10 V
+10 V
+0.1 V
X0 (Offset)
–1 V
+0.1 V –1 V
Repeat if required.
SQUARE ROOT
SQUARE
Z
V
=
10VZ
V
OUT
Z
X
X
1
X
X
Z
1
2
AD532
OUT
OUT
2
Y
V
1
2
AD532
V
OUT
OUT
Y
Y
+V
+V
–V
S
1
2
S
2
V
IN
Y
+V
+V
–V
S
1k⍀
(SF)
S
OS
V
=
OUT
10V
(OPTIONAL)
V
IN
47k⍀
2.2k⍀
10k⍀
20k⍀
20k⍀
(X )
–V
0
S
S
–V
S
S
Figure 12. Squarer Connection
Figure 14. Square Rooter Connection
The squaring circuit in Figure 12 is a simple variation of the
multiplier. The differential input capability of the AD532, how-
ever, can be used to obtain a positive or negative output re-
sponse to the input . . . a useful feature for control applications,
as it might eliminate the need for an additional inverter somewhere
else.
The connections for square root mode are shown in Figure 14.
Similar to the divide mode, the multiplier cell is connected in
the feedback of the op amp by connecting the output back to
both the X and Y inputs. The diode D1 is connected as shown
to prevent latch-up as ZIN approaches 0 volts. In this case, the
VOS adjustment is made with ZIN = +0.1 V dc, adjusting VOS to
obtain –1.0 V dc in the output, VOUT = – √10 V Z. For optimum
performance, gain (S.F.) and offset (X0) adjustments are recom-
mended as shown and explained in Table I.
DIVISION
Z
X
10VZ
X
V
=
OUT
Z
X
X
1
2
DIFFERENCE OF SQUARES
V
AD532
OUT
OUT
Y
1
2
Y
+V
+V
–V
S
S
X
X
Z
X
Y
1
1k⍀
(SF)
2
V
AD532
V
OUT
OUT
47k⍀
Y
2.2k⍀
10k⍀
1
2
20k⍀
20k⍀
2
2
X
– Y
10V
20k⍀
Y
+V
+V
–V
S
V
=
S
OS
OUT
–Y
(X )
0
–V
S
S
10k⍀
(OPTIONAL)
20k⍀
Figure 13. Divider Connection
AD741KH
–V
S
S
The AD532 can be configured as a two-quadrant divider by
connecting the multiplier cell in the feedback loop of the op
amp and using the Z terminal as a signal input, as shown in
Figure 13. It should be noted, however, that the output error is
given approximately by 10 V ⑀m/(X1 – X2), where ⑀m is the total
error specification for the multiply mode; and bandwidth by
fm × (X1 – X2)/10 V, where fm is the bandwidth of the multiplier.
Further, to avoid positive feedback, the X input is restricted to
negative values. Thus for single-ended negative inputs (0 V to
–10 V), connect the input to X and the offset null to X2; for
Figure 15. Differential of Squares Connection
The differential input capability of the AD532 allows for the
algebraic solution of several interesting functions, such as the
difference of squares, X2 – Y2/10 V. As shown in Figure 15, the
AD532 is configured in the square mode, with a simple unity
gain inverter connected between one of the signal inputs (Y)
and one of the inverting input terminals (–YIN) of the multiplier.
The inverter should use precision (0.1%) resistors or be other-
wise trimmed for unity gain for best accuracy.
REV. B
–6–
AD532
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Side Brazed DIP
(D-14)
0.005 (0.13) MIN
14
0.098 (2.49) MAX
8
0.310 (7.87)
0.220 (5.59)
1
7
0.320 (8.13)
0.290 (7.37)
PIN 1
0.060 (1.52)
0.015 (0.38)
0.785 (19.94) MAX
0.200 (5.08)
MAX
0.150
(3.81)
MAX
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
SEATING
PLANE
0.100
(2.54)
BSC
0.023 (0.58)
0.014 (0.36)
0.070 (1.78)
0.030 (0.76)
0.008 (0.20)
Leadless Chip Carrier
(E-20A)
0.200 (5.08)
BSC
0.075
(1.91)
REF
0.100 (2.54)
0.064 (1.63)
0.358 (9.09)
0.100 (2.54) BSC
0.015 (0.38)
0.342 (8.69)
SQ
0.095 (2.41)
0.075 (1.90)
3
MIN
19
20
18
4
0.028 (0.71)
0.358
1
0.011 (0.28)
TOP
VIEW
0.022 (0.56)
(9.09)
MAX
SQ
BOTTOM
VIEW
0.007 (0.18)
R TYP
0.075 (1.91)
REF
0.050 (1.27)
BSC
14
13
8
9
45° TYP
0.055 (1.40)
0.045 (1.14)
0.088 (2.24)
0.054 (1.37)
0.150 (3.81)
BSC
Metal Can
(H-10A)
REFERENCE PLANE
0.750 (19.05)
0.500 (12.70)
0.185 (4.70)
0.165 (4.19)
0.250 (6.35)
MIN
0.050
(1.27)
MAX
0.160 (4.06)
0.110 (2.79)
6
5
7
0.335 (8.51)
0.305 (7.75)
8
4
3
0.230
(5.84)
BSC
0.045 (1.14)
0.027 (0.69)
9
0.370 (9.40)
0.335 (8.51)
2
10
1
0.115
(2.92)
BSC
0.019 (0.48)
0.016 (0.41)
0.040 (1.02) MAX
0.034 (0.86)
0.027 (0.69)
0.045 (1.14)
0.010 (0.25)
0.021 (0.53)
0.016 (0.41)
36°
BSC
BASE & SEATING PLANE
REV. B
–7–
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