LT3966 [ADI]
I2C Programmable Quad Monolithic Boost LED Driver;
| 型号： | LT3966 |
| 厂家： | 
ADI |
| 描述： | I2C Programmable Quad Monolithic Boost LED Driver |
| 文件： | 总36页 (文件大小：2437K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3966
2
I C Programmable Quad
Monolithic Boost LED Driver
FEATURES
DESCRIPTION
2
The LT®3966 is an I C programmable monolithic boost
n
Four Independent DC/DC Channels
2
n
I C Programmable
LED driver with four independent channels. Each chan-
nel provides a 60V current mode boost converter with
an internal 1.6A DMOS power switch, as well as inter-
n
8192:1 True Color PWM™ Dimming
n
8-Bit Analog Dimming Pin Scaled by DAC
2
n
11-Channel, 8-Bit ADC with 2 External Inputs
nal and external analog and PWM dimming features. I C
n
1.6A, 60V Internal DMOS Switches
Input Voltage: 3V to 60V
programmable features include a 13-bit (8192:1) digital
PWM generator, 8-bit analog dimming DAC, and flexible
fault reporting and handling.
n
n
Output Voltage and Current Monitoring to 60V
n
High Side PMOS Disconnect and PWM Switch Driver
An onboard 8-bit ADC allows measurement of each
channel’s output voltage and output current, as well
as chip input voltage and two external measurements.
In addition, independent shutdown and standby con-
trol of each channel provides flexible solutions for
multitopology applications.
n
Adjustable Frequency: 300kHz to 4MHz with Optional
Frequency Synchronization
n
Thermally Enhanced 6mm × 6mm 40-Lead QFN Package
n
AEC-Q100 Qualification in Progress
APPLICATIONS
The LT3966 is available in a thermally enhanced 6mm ×
6mm 40-Lead QFN package.
n
Backlighting
Heads Up Displays
n
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
100W Buck Mode LED Driver with I2C Dimming
V
IN
44V TO 52V
ISP1
330mΩ
ISN1
ISP2
330mΩ
ISN2
ISP3
330mΩ
ISN3
ISP4
Efficiency
4.7μF
×4
330mΩ
ꢀ00
ISN4
TG1
TG2
TG3
TG4
ꢀꢁ
ꢀ0
1μF
1μF
1μF
1μF
ꢀꢁ
68μH
68μH
68μH
68μH
ꢀ0
ꢀ
ꢀ ꢁꢂ0ꢃꢄꢅ
ꢀꢁ
ꢀꢁ
ꢀꢁ
SW1
SW2
SW3
SW4
ISP1–4
V
IN
ꢀ
ꢀ ꢁꢂꢃ
1MΩ
33k
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁꢂ
ꢀ0
EN/UVLO
0.0
0.ꢀ
ꢀ.0
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.0
ISN1–4
TG1–4
FB1–4
LT3966
RT
ꢀꢁꢂ ꢃꢄRRꢁꢅꢆ ꢇꢈꢉ
ꢇꢊ ꢋ ꢌꢍ0ꢎꢈꢏꢊ ꢃꢐꢉ
GND
ꢀꢁꢂꢂ ꢃꢄ0ꢅꢆ
EXT1
CTRL/
PWM1–4
EXT2
SDA SCL ALERT
SYNC ADR1–2 INTV
CC
3966 TA01a
97.6k
150k
2
360kHz
MULTI-
PHASE
I C
4.7μF
BUS
22.1k
INTV
CC
Rev. 0
1
Document Feedback
For more information www.analog.com
LT3966
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
ꢉꢊꢋ ꢌꢍꢎꢏ
V , EN/UVLO, SW1, SW2, SW3, SW4, ISP1, ISP2,
IN
ISP3, ISP4, ISN1, ISN2, ISN3, ISN4......................62V
ISP–ISN (Any Channel)...............................................2V
TG1–4................................................................(Note 2)
ꢂ0 ꢀꢁ ꢀꢃ ꢀꢄ ꢀꢅ ꢀꢆ ꢀꢂ ꢀꢀ ꢀꢇ ꢀꢈ
ꢍꢞꢋꢈ
ꢉꢐꢈ
ꢈ
ꢇ
ꢀ
ꢂ
ꢆ
ꢅ
ꢄ
ꢃ
ꢁ
ꢀ0
ꢇꢁ
ꢇꢃ
ꢍꢞꢋꢇ
ꢉꢐꢇ
INTV ............................................................... (Note 3)
CC
FB1–4, EXT1–2, CTRL/PWM1–4, ADR1–2, ALERT,
SDA, SCL, SYNC..................................................5.5V
RT...............................................................................2V
Operating Junction Temperature Range (Notes 4, 5)
LT3966E ............................................ –40°C to 125°C
LT3966J............................................. –40°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
ꢞꢏꢈ
ꢞꢏꢈ
ꢞꢏꢀ
ꢞꢏꢀ
ꢉꢐꢀ
ꢞꢏꢇ
ꢇꢄ ꢞꢏꢇ
ꢇꢅ ꢞꢏꢂ
ꢂꢈ
ꢐꢑꢒ
ꢇꢆ
ꢞꢏꢂ
ꢇꢂ ꢉꢐꢂ
ꢇꢀ
ꢍꢞꢋꢀ
ꢍꢞꢑꢀ
ꢍꢞꢋꢂ
ꢇꢇ ꢍꢞꢑꢂ
ꢇꢈ
ꢔꢟꢀ ꢈ0
ꢔꢟꢂ
ꢈꢈ ꢈꢇ ꢈꢀ ꢈꢂ ꢈꢆ ꢈꢅ ꢈꢄ ꢈꢃ ꢈꢁ ꢇ0
ꢓꢔꢑ ꢋꢕꢖꢗꢕꢐꢎ
ꢂ0ꢘꢙꢎꢕꢒ ꢚꢅꢛꢛ ꢜ ꢅꢛꢛꢝ ꢋꢙꢕꢞꢉꢍꢖ ꢓꢔꢑ
T
= 150°C, θ = 33°C/W EXPOSED PAD (PIN 41) IS GND
JMAX
JA
AND MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LT3966EUJ#PBF
LT3966JUJ#PBF
TAPE AND REEL
PART MARKING
LT3966UJ
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 125°C
LT3966EUJ#TRPBF
LT3966JUJ#TRPBF
40-Lead (6mm × 6mm) Plastic QFN
40-Lead (6mm × 6mm) Plastic QFN
LT3966UJ
–40°C to 150°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
ELECTRICAL CHARACTERISTICS The l denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VIN = 12V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
60
UNITS
V
l
V
IN
V
IN
V
IN
Operating Range
Quiescent Current
Shutdown Current
3
CTRL/PWM = 0V, EN/UVLO = 1.3V
2.7
3.3
mA
EN/UVLO = 0V
EN/UVLO = 1.15V, CTRL/PWM = 0V
0
190
1
230
µA
µA
l
EN/UVLO Shutdown Threshold Falling
EN/UVLO Rising Hysteresis
1.20
1.23
15
1.26
V
mV
V
EN/UVLO Rising
EN/UVLO Input Low Voltage
I
< 1μA
0.4
VIN
Rev. 0
2
For more information www.analog.com
LT3966
ELECTRICAL CHARACTERISTICS The l denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VIN = 12V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
2
MAX
100
3.1
UNITS
µA
EN/UVLO Bias Current Low
EN/UVLO Bias Current High
LDO Regulator
EN/UVLO = 1.15V
EN/UVLO = 1.3V
10
nA
l
l
INTV Regulation Voltage
I
= –1mA, Not Switching
INTVCC
2.9
2.6
3
V
%/V
%/mA
V
CC
INTV Line Regulation
3V ≤ V ≤ 60V
0.03
0.04
2.7
75
CC
IN
INTV Load Regulation
–20mA ≤ I
≤ 0mA, Not Switching
INTVCC
CC
INTV Undervoltage Lockout
INTV Falling
2.8
CC
CC
INTV Undervoltage Lockout Hysteresis
INTV Rising
mV
CC
CC
INTV Current Limit
V
V
= 12V, INTV = 2.8V
36
mA
CC
IN
IN
CC
INTV Dropout Voltage
= 3V, I
= –15mA
320
mV
CC
INTVCC
Analog-to-Digital Converter
Converter Resolution
8
1.275
5
Bits
V
Converter Full-Scale Voltage
Converter LSB Size
1.266
4.95
1.284
5.05
mV
µs
Conversion Time (t
)
R = 100kΩ, MPHASE = 0, AUTO = 0
t
20
CONV
EXT1, EXT2 Input Impedance
V
= V
= 1V
10
100
1.7
2.2
MΩ
V
EXT1
EXT1
EXT2
l
l
EXT1, EXT2 Internal Voltage Clamp
EXT1, EXT2 Internal Voltage Clamp Impedance
Channel 1–4 LED Current Sense Amplifiers
ISP Common Mode Voltage Range
Full-Scale Current Sense Threshold
I
= I
EXT2
= 100μA
1.4
1.9
V
EXT1
= V
= 2V to 5.5V
kΩ
EXT2
3
55
V
ISP = 55V, CTRL/PWM =1.5V, ADIM[7:0] = 0xFF
ISP = 3V, CTRL/PWM = 1.5V, ADIM[7:0] = 0xFF
l
l
242
242
250
250
255
255
mV
mV
(V –V
ISP ISN
)
Externally Adjusted Half-Scale Threshold
(V –V
ISP = 55V, CTRL/PWM = 0.7V, ADIM[7:0] = 0xFF
ISP = 3V, CTRL/PWM = 0.7V, ADIM[7:0] = 0xFF
l
l
122
122
125
125
128
128
mV
mV
)
ISP ISN
Externally Adjusted 1/10th Scale Threshold
(V –V
ISP = 55V, CTRL/PWM = 0.3V, ADIM[7:0] = 0xFF
ISP = 3V, CTRL/PWM = 0.3V, ADIM[7:0] = 0xFF
l
l
20
20
25
25
31
31
mV
mV
)
ISP ISN
Internally Adjusted Half-Scale Threshold
(V –V
ISP = 55V, CTRL/PWM = 1.5V, ADIM[7:0] =
0x7F
ISP = 3V, CTRL/PWM = 1.5V, ADIM[7:0] = 0x7F
l
l
121
121
125
125
129
129
mV
mV
)
ISP ISN
Internally Adjusted 1/10th Scale Threshold
(V –V
ISP = 55V, CTRL/PWM = 1.5V, ADIM[7:0] =
0x19
ISP = 3V, CTRL/PWM = 1.5V, ADIM[7:0] = 0x19
l
l
20
20
25
25
31
31
mV
mV
)
ISP ISN
Overcurrent Protection Threshold (V –V
)
ISP = 60V
ISP = 60V
370
22
mV
mV
ISP ISN
C/10 Threshold
14
90
30
ISP/ISN Input Bias Current (Combined)
CTRL/PWM = 3V (Active), ISP = ISN = 55V
CTRL/PWM = 0V (Standby), ISP = ISN = 55V
440
13
µA
µA
17
l
PWM Threshold
CTRL/PWM Falling
103
115
mV
Rev. 0
3
For more information www.analog.com
LT3966
ELECTRICAL CHARACTERISTICS The l denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VIN = 12V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ISP Voltage Regulation Threshold
Channel 1–4 Voltage Feedback Amplifiers
62
V
FB Regulation Threshold (V
)
FB
CTRL/PWM = 2V
1.188
1.170
1.200
1.200
1.208
1.218
V
V
l
l
FB Overvoltage Threshold
FB Open LED Threshold
FB Shorted LED Threshold
FB Input Bias Current
FB Line Regulation
Oscillator
V
+ 50mV
– 40mV
280
V
+ 60mV
– 50mV
300
V
+ 70mV
– 60mV
320
V
V
FB
FB
FB
FB
FB
V
V
V
FB
mV
nA
Current Out of Pin, FB = 1V
10
100
3.3V ≤ V ≤ 60V
0.0004
%/V
IN
RT Pin Voltage
1.0
V
Switching Frequency in Single-Phase Mode
R = 261kΩ
l
l
l
370
0.93
1.85
400
1.00
2.00
430
1.07
2.15
kHz
MHz
MHz
T
R = 100kΩ
T
R = 47.5kΩ
T
Switching Frequency in Multiphase Mode
R = 174kΩ
l
l
l
279
0.93
1.85
300
1.00
2.00
321
1.07
2.15
kHz
MHz
MHz
T
R = 47.5kΩ
T
R = 21kΩ
T
Minimum Off Time
30
35
50
60
65
75
ns
ns
V
Minimum On Time
SYNC Input High (SYNC In Mode)
SYNC Input Low (SYNC In Mode)
SYNC Input Duty Cycle
SYNCOUT = 0
SYNCOUT = 0
1.5
0.4
90
V
10
%
kΩ
%
V
SYNC Resistance to GND (SYNC In Mode)
SYNC Output Mode Duty Cycle
SYNC Output Voltage High (SYNC Out Mode)
SYNC Output Voltage Low (SYNC Out Mode)
Channel 1–4 Power Switch
SW On-Resistance
SYNCOUT = 0
95
55
SYNCOUT = 1
45
65
l
l
SYNCOUT = 1, Load = 3kΩ
SYNCOUT = 1, Load = 3kΩ
2.4
0.4
V
I
= 200mA
= 62V
200
2
mΩ
A
SW
l
SW Current Limit
1.6
7.4
2.4
3
SW Leakage Current
V
μA
SW
External PMOS Gate Driver
TG ON Voltage (V –V
)
ISP = 24V
ISP = 24V
8.2
0
9
V
V
ISP TG
TG OFF Voltage (V –V
)
0.3
ISP TG
TG Turn-On Time
TG Turn-Off Time
C
LOAD
C
LOAD
= 470pF, ISP = 24V
= 470pF, ISP = 24V
50
60
ns
ns
2
I C Port
2
I C Address
Programmed by ADR2, ADR1 Pins
101XXXX[R/W]
l
l
l
l
l
l
ADR1, ADR2 Input High Voltage
ADR1, ADR2 Input Low Voltage
0.9 • V
V
V
INTVCC
0.1 • V
INTVCC
ADR1, ADR2 Pull-Down Current in HIGH State
ADR1, ADR2 Pull-Up Current in LOW State
SDA, SCL Input High Voltage
V
V
, V
= 3V, Current Into Pin
9
9
13
13
17
µA
µA
V
ADR1 ADR2
, V
= 0V, Current Out of Pin
17
ADR1 ADR2
1.5
SDA ,SCL Input Low Voltage
0.4
V
Rev. 0
4
For more information www.analog.com
LT3966
ELECTRICAL CHARACTERISTICS The l denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VIN = 12V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
50
UNITS
nA
nA
V
SDA, SCL Input Low Leakage
SDA, SCL Input High Leakage
SDA Output Low Voltage
ALERT Output Low Voltage
Current Out of Pin, SDA = SCL = 0V
Current Into Pin, SDA = SCL = 3V
50
I
I
= 3mA
0.4
0.4
400
SDA
= 3mA
V
ALERT
2
I C Clock Operating Frequency
kHz
µs
Bus Free Time Between Stop and Start
1.3
Condition (t
)
BUF
Hold Time After Repeated Start Condition (t
)
0.6
µs
µs
µs
ns
ns
ns
µs
µs
ns
ns
ns
ms
HD_SDA
Repeated Start Condition Set-Up Time (t
)
0.6
SU_STA
Stop Condition Set-Up Time (t
)
0.6
SU_STO
Data Hold Time Output (t
)
0
0
900
HD_DAT(O)
Data Hold Time Input (t
)
HD_DAT(I)
Data Set-Up Time (t
)
100
SU_DAT
SCL Clock Low Period (t
)
1.3
LOW
SCL Clock High Period (t
Clock/Data Fall Time
Clock/Data Rise Time
)
0.6
HIGH
C = Capacitance of One Bus Line (pF)
20 + 0.1C
20 + 0.1C
300
300
50
B
B
C = Capacitance of One Bus Line (pF)
B
B
Input Spike Suppression Pulse Width (t
Watchdog Timeout Period
)
SP
WDTEN = 1
75
100
125
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
design, characterization and correlation with statistical process controls.
The LT3966J is guaranteed to meet performance specifications over the
full –40°C to 150°C operating junction temperature range. High junction
temperatures degrade operating lifetimes. Operating lifetime is derated at
junction temperatures greater than 125°C.
Note 2: Do not apply a positive or negative voltage source to TG pins,
otherwise permanent damage may occur.
Note 3: Do not apply a positive or negative voltage source to INTV pin,
otherwise permanent damage may occur. I
external load that can be applied.
Note 4: The LT3966E is guaranteed to meet performance specifications
from the 0°C to 125°C junction temperature. Specifications over the
–40°C to 125°C operating junction temperature range are assured by
Note 5: The LT3966 includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed the maximum operating junction temperature
when overtemperature is active. Continuous operating above the specified
maximum operating junction temperature may impair device reliability.
Note 6: Guaranteed by a combination of design, testing, and
characterization over the operating temperature range, and automated
testing at ambient temperature.
CC
= 2mA is the maximum
INTVCC
ꢁꢊꢋ
ꢀ
ꢁꢂ
ꢀ
ꢀ
ꢀ
ꢀ
ꢁꢄꢆꢊꢋꢇ
ꢁꢄꢆꢁꢇꢋ
ꢃꢄꢅ
ꢉꢊꢆꢊꢋꢇꢈ
ꢉꢊꢆꢊꢋꢇꢎ
ꢀ
ꢉꢊꢆꢁꢇꢋ
ꢀ
ꢀ
ꢁꢄꢆꢁꢇꢈ
ꢀ
ꢁꢂ
ꢑꢒꢓꢓ ꢇꢊ
ꢁꢌꢐ
ꢀ
ꢉꢊꢆꢁꢇꢋ
Rꢏꢂꢏꢋꢇꢏꢊ ꢁꢇꢋRꢇ
ꢌꢈꢍꢊꢎꢇꢎꢈꢍ
Rꢏꢂꢏꢋꢇꢏꢊ ꢁꢇꢋRꢇ
ꢌꢈꢍꢊꢎꢇꢎꢈꢍ
ꢁꢇꢈꢂ
ꢌꢈꢍꢊꢎꢇꢎꢈꢍ
ꢁꢇꢋRꢇ
ꢌꢈꢍꢊꢎꢇꢎꢈꢍ
Rev. 0
5
For more information www.analog.com
LT3966
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Shutdown and Standby Current
vs Input Voltage
Shutdown and Standby Current
vs Temperature
EN/UVLO Thresholds
vs Temperature
ꢀ.ꢁ0
ꢀꢁ0
ꢀ00
ꢀꢁ0
ꢀ00
ꢀ0
ꢀꢁ0
ꢀ00
ꢀꢁ0
ꢀ00
ꢀ0
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
Rꢀꢁꢀꢂꢃ ꢄꢅRꢆꢁꢅꢇꢈꢉ
ꢀꢁꢂꢃꢄꢅꢆ ꢇ 0ꢄ
ꢀꢁꢂꢃꢄꢅꢆ ꢇ ꢈ.ꢈꢉꢄ
ꢀꢁꢂꢃꢄꢅꢆ ꢇ 0ꢄ
ꢀꢁꢂꢃꢄꢅꢆ ꢇ ꢈ.ꢈꢉꢄ
ꢀ.ꢁꢂ
ꢀꢁꢂꢂꢃꢄꢅ ꢆꢇRꢈꢉꢇꢊꢂꢋ
ꢀ.ꢁꢁ
ꢀꢁꢂꢃꢄꢅꢆꢇ
ꢀꢁꢂꢃꢄꢅꢆꢇ
0
ꢀ.ꢁ0
0
0
ꢀ0
ꢀ0
ꢀ0
ꢀꢁꢂ
ꢀ0
ꢀ0
ꢀ0
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀ
ꢀꢁ
ꢀꢁꢂꢂ ꢃ0ꢄ
ꢀꢁꢂꢂ ꢃ0ꢀ
ꢀꢁꢂꢂ ꢃ0ꢄ
EN/UVLO Hysteresis Current
vs Temperature
Quiescent Current vs Input Voltage
INTVCC Voltage vs Input Voltage
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢀ
ꢀ.0
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢀ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀꢁꢂꢃꢄꢅꢆ ꢇ ꢈ.ꢈꢉꢄ
ꢀꢁꢂꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢊꢋRꢅꢂꢌꢍꢎꢏ ꢐꢑ ꢇ 0 ꢉ
ꢀꢁꢂꢃꢄ ꢅ ꢂ.ꢆꢇ
ꢀ
ꢅ ꢆꢇꢈꢉꢊ
ꢀꢁꢂꢃꢄꢄ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
0
ꢀ0
ꢀ0
ꢀ0
ꢃꢀꢄ
ꢀ0
ꢀ0
ꢀ0
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀ
ꢀꢁꢂ ꢃꢀꢄ
ꢁꢂ
ꢀꢁꢂꢂ ꢃ0ꢄ
ꢀꢁꢂꢂ ꢃ0ꢄ
ꢀꢁꢂꢂ ꢃ0ꢂ
INTVCC Current Limit
vs Temperature
INTVCC Dropout vs
Temperature
INTVCC Voltage vs Temperature
ꢀ.ꢁ0
ꢀ.0ꢁ
ꢀ.0ꢁ
ꢀ.0ꢁ
ꢀ.0ꢁ
ꢀ.00
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ.ꢁꢀ
ꢀ.ꢁ0
ꢀ0
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
0
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂꢃ ꢀ ꢁ.ꢂꢃ
ꢀꢀ
ꢀ
ꢀꢁꢂꢃ ꢀ ꢁꢂꢃꢄꢅ
ꢀꢀ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢂ ꢃ0ꢄ
ꢀꢁꢂꢂ ꢃ0ꢄ
ꢀꢁꢂꢂ ꢃ0ꢁ
Rev. 0
6
For more information www.analog.com
LT3966
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
INTVCC Dropout vs
Temperature Load
Switching Frequency
vs Temperature
ꢀ0ꢁ0
Switching Frequency vs RT
ꢀ0
ꢀ00
ꢀꢁ0
ꢀ00
ꢀꢁ0
ꢀ00
ꢀꢁ0
ꢀ00
ꢀ0
R
ꢀ ꢁ00ꢂ
ꢀ
ꢀ0ꢁ0
ꢀ0ꢁ0
ꢀ000
ꢀꢁ0
ꢀ
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
0.ꢀ
0
ꢀ00
ꢀ0
ꢀ00
(kΩ)
ꢀꢁ
0
ꢀ
ꢀ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
R
ꢀ
ꢀ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃ ꢀꢁꢂꢃ
ꢀꢀ
ꢀꢁꢂꢂ ꢃꢄꢄ
ꢀꢁꢂꢂ ꢃꢄ0
ꢀꢁꢂꢂ ꢃꢄꢅ
V
FB vs Temperature
ISP Voltage Limit vs Temperature
VISP–ISN vs Temperature
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢀ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁꢀ
ꢀꢁ0
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ.ꢁꢁ
ꢀ.ꢁꢀ
ꢀ.ꢁ0
ꢀ.ꢀꢁ
ꢀ.ꢀꢁ
ꢀ.ꢀꢁ
ꢀ.ꢀꢁ
ꢀꢁꢂ ꢃ ꢄꢅꢆ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢂ ꢃꢄꢅ
ꢀꢁꢂꢂ ꢃꢄꢅ
ꢀꢁꢂꢂ ꢃꢄꢀ
VISP–ISN Threshold vs
Temperature Overcurrent Protection
VISP–ISN vs VISP
VISP–ISN vs ADIM VCTRL/PWM
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢁ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁ0
ꢀꢀꢁ
ꢀ00
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢂ
ꢀ00
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢀ
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ ꢃ ꢄꢅꢆ
ꢀꢁꢂ ꢃ ꢄꢅꢆ
ꢀ0
ꢀꢁ
0
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
0
0.ꢀ 0.ꢀ 0.ꢀ 0.ꢀ
ꢀ
ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.0
0
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀ0 ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀ0
ꢀꢁꢂ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢁRꢂꢃꢄꢅꢆ
ꢀꢁꢂ
ꢀꢁꢂꢂ ꢃꢄꢅ
ꢀꢁꢂꢂ ꢃꢄꢅ
ꢀꢁꢂꢂ ꢃꢄꢂ
Rev. 0
7
For more information www.analog.com
LT3966
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
V
ISP–ISN vs ADIM VFB
VISP–ISN vs VFB
ILED Measured Code vs VISP–ISN
ꢀꢁꢂ
ꢀꢁ0
ꢀꢀꢁ
ꢀ00
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢂ
ꢀ00
ꢀꢁ
ꢀꢁꢂ
ꢀꢀꢁ
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ0
ꢀꢀꢁ
ꢀ00
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢂ
ꢀ00
ꢀꢁ
ꢀꢁꢂ ꢃ ꢄꢅꢆ
ꢀꢁꢂ ꢃ ꢄꢅꢆ
ꢀꢁ
ꢀ0
ꢀ0
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂ ꢃ ꢄꢅꢆ
0
0
0
ꢀ.ꢀ0 ꢀ.ꢀꢁ ꢀ.ꢀꢁ ꢀ.ꢀꢁ ꢀ.ꢀꢁ ꢀ.ꢁ0 ꢀ.ꢁꢁ
0
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢂ ꢀꢁ0 ꢀꢁꢂ ꢀꢀꢁ ꢀꢁꢂ ꢀꢁꢁ ꢀꢁ0
0
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢂ ꢀꢁ0 ꢀꢁꢂ ꢀꢀꢁ ꢀꢁꢂ
ꢀꢁꢂꢃ ꢄꢅꢁꢆ
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂꢃꢀꢁꢄ
ꢀꢁꢂꢂ ꢃꢄ0
ꢀꢁꢂꢂ ꢃꢄꢅ
ꢀꢁꢂꢂ ꢃꢄꢁ
Switch On-Resistance
vs Temperature
Switch Current Limit
vs Temperature
FB Measured Code vs VFB
ꢀ00
ꢀꢁ0
ꢀ00
ꢀꢁ0
ꢀ00
ꢀꢁ0
ꢀ00
ꢀ0
ꢀ.ꢁ
ꢀ.ꢀ
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀꢁꢂ
ꢀꢀꢁ
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁ
0
0
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
0
0.ꢀꢁꢁ
0.ꢀꢁ0
0.ꢀꢁꢂ
ꢀꢁꢂ
ꢀ.0ꢁ0
ꢀ.ꢁꢂꢃ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀ
ꢀꢁ
ꢀꢁꢂꢂ ꢃꢄꢀ
ꢀꢁꢂꢂ ꢃꢄꢅ
ꢀꢁꢂꢂ ꢃꢄꢄ
Switch Current Limit
vs Duty Cycle
Minimum On/Off Time
vs Temperature
TG Rise/Fall Time vs CLOAD
ꢀꢁ0
ꢀꢁ0
ꢀ00
ꢀ0
ꢀ.ꢁ
ꢀ.ꢀ
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
Rꢀꢁꢂ
ꢀꢁꢂꢂ
ꢀꢁꢂꢁꢀꢃꢀ ꢄꢂ
ꢀꢁꢂꢁꢀꢃꢀ ꢄꢅꢅ
ꢀꢁꢂ ꢃ ꢄꢅꢆ
ꢀ0
ꢀ0
ꢀ0
0
0
ꢀ00
ꢀ00
ꢀ00
ꢀꢁꢂꢃ
ꢀ00
ꢀ000
0
ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ00
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀ
ꢀꢁꢂꢃ ꢄꢃꢄꢅꢆ ꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃ
ꢀꢁꢂꢂ ꢃꢄꢂ
ꢀꢁꢂꢂ ꢃꢄꢅ
ꢀꢁꢂꢂ ꢃꢄꢅ
Rev. 0
8
For more information www.analog.com
LT3966
PIN FUNCTIONS
2
FB1, FB2, FB3, FB4 (Pins 39, 32, 10, 21): Voltage
Feedback Pin. The FB pin is used for output voltage regu-
lation and limiting. Tie to a resistor divider from the output
voltage. When FB reaches 1.2V, the switch current will
reduce in order to maintain the output voltage at this level.
If ISP/ISN senses less than 10% of full output current
when FB reaches regulation, an OPENLED condition will
be flagged for that channel. If FB is driven above 1.26V,
the external PMOS will be switched off and an OVFB con-
dition will be flagged. If FB remains below 0.3V after the
internal soft start has completed, a SHORTLED condition
will be flagged. See the Applications Information section
for more information on faults and fault handling.
ADR1, ADR2, (Pins 16, 17): I C Address Select. These
pins are configured as three-state inputs (HIGH, LOW,
FLOAT). See Table 1 for address selection.
ALERT (Pin 20): Chip Status Reporting Pin. Depending
on channel configuration, the ALERT pin can be pulled
low due to any of the following faults: FB Overvoltage,
Open LED, Shorted LED, and LED Overcurrent. See the
Applications Information section for more information on
faults and fault handling.
2
SDA (Pin 18): Serial Data Line for I C Communications.
Combination input and open-drain output.
2
SCL (Pin 19): Serial Clock for I C Communications.
ISP1, ISP2, ISP3, ISP4 (Pins 1, 30, 8, 23): Positive
Terminal of the LED Current Sense Amplifier. Also serves
as the positive supply of the TG gate driver. Connect to
positive side of LED current sense resistor and minimize
resistance in this path.
SYNC (Pin 34): Oscillator Synchronization Pin. By default,
this pin acts as an input for an external clock to define
the switching frequency of the LT3966. By setting the
SYNCOUT configuration bit, the input function is disabled
and instead SYNC becomes a clock output for driving
other external circuits.
ISN1, ISN2, ISN3, ISN4 (Pins 40, 31, 9, 22): Negative
Terminal of the LED Current Sense Amplifier. Kelvin con-
nects to negative side of LED current sense resistor.
RT (Pin 33): Timing Resistor Set Pin. Set the master clock
frequency using a resistor to GND. Do not leave the RT
pin open.
TG1, TG2, TG3, TG4 (Pins 2, 29, 7, 24): Top Gate Driver
Output. Connect to gate of external PMOS pass transistor.
TG is an inverted and level-shifted version of the PWM
EN/UVLO (Pin 36): Enable/Undervoltage Lockout Pin.
This pin is used for general ON/OFF control and to enable
the LT3966 at a specific input voltage. Drive with a logic
level greater than 1.5V for simple ON/OFF control, or tie to
a resistor divider of input voltage for precision shutdown
threshold. This pin has a falling threshold of 1.23V, rising
hysteresis of roughly 15mV, and a 2µA hysteresis current
dimming signal, and drives between VISP (OFF) and VISP
–
8.2V (ON) for LED PWM dimming as well as fault mode
disconnect. Leave unconnected if not used.
SW1, SW2, SW3, SW4 (Pins 3–4, 27–28, 5–6, 25–26):
Power DMOS Drain. Connect to switching end of the
inductor. Minimize copper area to increase efficiency and
reduce EMI.
when below threshold. Tie this pin to V if unused.
IN
INTV (Pin 37): Internal 3V LDO Output. This pin is the
LDO CoCutput and power supply for all internal circuitry.
Place a 4.7μF filter capacitor to GND as close to this pin
as possible. Do not drive this pin externally. Users may
apply a load of up to 2mA to this pin.
CTRL/PWM1, CTRL/PWM2, CTRL/PWM3, CTRL/PWM4
(Pins 11, 12, 13, 14): Combination Analog/PWM Dimming
Input. Drive from below 100mV to above 1.5V for full-
scale PWM dimming. Or drive with an analog voltage from
0.2V to 1.2V for 0% to 100% analog dimming. Do not
V (Pin 38): Input Voltage Supply. This pin is the power
IN
leave these pins floating, tie to INTV if unused.
CC
supply input to the LDO and the rest of the internal cir-
cuitry. It must be locally bypassed with a capacitor to GND
as close to the pin as possible.
EXT1, EXT2 (Pins 15, 35): External Input to ADC. The
working range of the EXT input is 0V (Code 0) to 1.275V
(Code 255). These pins are internally clamped to 1.7V.
Tie to GND if unused.
Rev. 0
9
For more information www.analog.com
LT3966
BLOCK DIAGRAM
R
ꢊ
Rꢊ
ꢍꢠꢃꢀ
ꢄꢃꢝꢇꢓꢅꢖ
ꢓ
ꢉꢃ
ꢂꢆRꢏ
ꢂꢆRꢒ
ꢔꢂꢇꢅꢊꢏꢐꢋ
ꢌꢀꢅꢟ
ꢢ
ꢐ
ꢉꢃꢊꢓ
ꢄꢃꢇꢓ
ꢀꢀ
ꢏ.ꢒꢓ
ꢢ
ꢐ
ꢛꢂꢃꢆꢕꢂꢈ
ꢖꢍꢀꢉꢅꢅꢂꢊꢖR
ꢀꢅꢟꢏꢐꢋ
ꢒ
ꢍꢀꢅ
ꢍꢀꢅ
ꢍꢆꢂ
ꢉ ꢀ ꢉꢃꢊꢄRꢔꢂꢀꢄ
ꢂꢃꢆ
ꢉꢃꢊꢓ
ꢧꢓ
ꢀꢀ
ꢍꢆꢂ
ꢕꢅꢖꢛꢂꢅ ꢅꢖꢕꢉꢀ
ꢂꢀꢟꢝꢍꢆꢂ0
ALERT
ꢢ
ꢐ
ꢓꢀꢀꢇꢓ
ꢂꢅꢄRꢊ
ꢏ.0ꢑꢓ
ꢓ
ꢄꢜꢊꢏ
ꢄꢜꢊꢒ
ꢉꢃ
ꢄꢜꢊꢏ
ꢄꢜꢊꢒ
ꢂꢆꢀ
ꢌꢇꢜ
ꢂꢆꢀꢑ
ꢔꢛꢏꢐꢋ
ꢓꢅꢄꢆꢏꢐꢋ
ꢆꢂꢊꢂ
Rꢝꢎ
ꢀꢅꢟꢏ
ꢦ
ꢍꢅꢖꢈꢄ ꢀꢖꢌꢈ
ꢍꢎꢏ
ꢐ
ꢢ
ꢀWꢁꢂ
ꢍ
ꢐ
ꢢ
R
ꢔꢛꢏ
ꢐ
ꢢ
ꢏ.ꢒꢡꢓ
ꢀꢇRRꢄꢃꢊ
ꢍꢄꢃꢍꢖR
ꢏ.ꢡꢂ
ꢢ
ꢐ
ꢐ
ꢢ
ꢔꢛꢏ
ꢖꢓꢔꢛꢏ
ꢏ.ꢏꢤꢓ
ꢐ
ꢢ
ꢔꢛꢏ
ꢖꢈꢄꢃꢅꢄꢆꢏ
ꢅꢄꢆꢖꢀꢏ
ꢔꢂꢇꢅꢊꢏ
ꢀꢁꢂꢃꢃꢄꢅ
ꢓꢅꢄꢆꢏ
0.ꢏꢓ
ꢏ.ꢒꢓ
ꢢ
ꢅꢖꢕꢉꢀ ꢨ ꢔꢂꢇꢅꢊ
ꢓꢅꢄꢆꢏ
ꢤ0ꢥꢓ
ꢐꢣꢋ
Rꢇꢃꢏ
ꢍꢁꢖRꢊꢏ
ꢊꢍꢆ
ꢁꢂꢃꢆꢅꢉꢃꢕ
ꢓꢀꢏ
Rꢏ
ꢐ
ꢢ
ꢐ
ꢢ
ꢉꢍꢈꢏ
ꢉꢍꢃꢏ
ꢓꢅꢄꢆꢏ
ꢏ.ꢤꢓ
ꢢ
ꢐ
R
ꢉꢍꢈ
ꢓꢀꢀꢇꢓ
ꢐ
ꢢ
ꢉ
ꢖꢇꢊ
ꢔꢛꢏ
ꢀꢊRꢅꢝ
ꢈꢎꢌꢏ
ꢍꢖꢔꢊꢞ
ꢍꢊꢂRꢊ
ꢉ
Rꢄꢔ
ꢅꢂꢊꢖꢔꢔ
0.ꢧꢓ
ꢏ.ꢒꢓ
ꢢ
ꢢ
ꢐ
ꢆꢂꢀꢑ
ꢐ
ꢢ
ꢍꢍꢆꢖꢃꢄꢏ
ꢏ.ꢚꢓ
Rꢏ
ꢣꢋ
ꢍꢍꢏ
ꢂꢆꢉꢌꢏꢗꢚꢘ0ꢙ
ꢢ
ꢐ
ꢈꢎꢄꢜꢊꢏ
0.ꢏꢓ
ꢉꢍꢈꢏ
ꢊꢕꢏ
ꢈꢎꢌꢏ
ꢔꢂꢇꢅꢊꢏ
ꢈꢎꢉꢃꢊꢏ
ꢆꢉꢌꢌꢉꢃꢕ
ꢕꢄꢃꢄRꢂꢊꢖR
ꢆꢉꢌꢄꢃꢏ
ꢛꢂꢌꢏ
ꢉꢍꢈꢏ ꢐꢑ.ꢒꢓ
ꢍꢄꢅꢏꢗꢒꢘ0ꢙ
ꢆꢉꢌꢏꢗꢏꢒꢘ0ꢙ
ꢀꢁꢂꢃꢃꢄꢅ ꢆꢇꢈꢅꢉꢀꢂꢊꢄꢆ ꢋ ꢊꢉꢌꢄꢍ
Rev. 0
10
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LT3966
OPERATION
PWM dimming can be controlled externally by toggling
CTRL/PWM, or internally programmed using the LT3966
onboard PWM generator. This PWM generator offers res-
olution from 6-bit (64:1) to 13-bit (8192:1), as well as the
choice between standard PWM modulation and optional
BAM (Bit Angle Modulation) control.
OVERVIEW
The LT3966 is a 4-channel monolithic boost LED driver
2
with I C programmability and onboard ADC. The 4 inde-
pendent LED driver channels each consist of a 1.6A
monolithic boost converter with high side LED current
sensing and high side gate driver for PWM dimming and
fault protection. The analog LED current setpoint can be
The LED drivers have detection and protection from
overvoltage, overcurrent, open LED, and shorted LED
conditions. Fault handling is autonomous, with optional
2
controlled externally and also programmed through I C.
The LED dimming can be controlled with an external PWM
2
2
readback, fault reporting, and latchoff functions using I C.
signal or through I C using the internal PWM generator.
Additionally, the LT3966 contains an 11-input, 8-bit ADC
used to measure regulation parameters of each of the LED
driver channels as well as input voltage, die temperature,
and two external inputs.
2
The device I C address is programmable to one of eight
different addresses or standalone mode using the two tri-
mode ADR pins. Reliable and robust I C communication
is ensured by use of CRC error checking and an optional
watchdog timer.
2
LT3966 operates from input voltages of 3V to 60V. The
1.23V EN threshold allows programmable external UVLO
using a resistor divider from the input voltage. All inter-
nal circuitry is powered from an onboard LDO regulator
2
I C OPERATION
2
supplying 3V at the INTV pin. Although the internal cir-
I C Transactions and Error Correction Operation
CC
cuitry operates at 3V, all I/O pins are 5V tolerant. The LDO
is current limited to 36mA and should not be externally
loaded, and the device provides an internal UVLO to pre-
2
I C communication revolves around read and write trans-
actions. In LT3966, Packet Error Checking (PEC) is used
to guarantee reliable communication between the host
system and the device. This consists of a trailing byte on
both the read and write transactions that offers a CRC
check of all bytes since the last start. The CRC polyno-
mial used in LT3966 is identical to that used in SMBus:
vent switching when INTV falls below 2.7V. Bypass and
CC
filtering of the LDO require a capacitor of at least 4.7μF
from INTV to GND located close to the pins.
CC
The boost converters are internally compensated current
mode converters with a 1.6A power FET each. The boost
converters can operate from 300Hz to 4MHz, and switch-
8
2
1
X + X + X + 1.
2
The structure of an I C write is shown in Figure 1. Data
being written to LT3966 must follow this format. The PEC
code (Figure 2) should be computed by the host system
using the CRC formula on the Chip Address, Sub Address,
and Data Bytes. If a valid PEC is received, the LT3966 will
acknowledge (ACK) on the 9th clock of the PEC transfer,
and the data will be transferred to the LT3966 register. If
an invalid PEC is received, the LT3966 will not ACK, and
the data will be discarded.
2
ing can be synchronized to an external clock. Through I C,
the LT3966 allows the options of multiphase switching for
lower input ripple as well as clock sync output.
The LED drivers use high side current sensing with a
250mV threshold. This analog threshold is externally
adjustable by using the CTRL/PWM pin, and is also inter-
nally programmable through I2C. A high side gate driver
for an external PMOS transistor allows accurate PWM
dimming, fast fault protection, and output disconnect.
Rev. 0
11
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LT3966
OPERATION
ꢋꢓꢔꢐ ꢊꢑꢑRꢕꢍꢍ
ꢍꢖꢗ ꢊꢑꢑRꢕꢍꢍ
ꢑꢊꢎꢊ
ꢐꢕꢋ ꢘꢋRꢋꢙ
ꢀ
0
ꢀ
ꢊ
ꢂ
ꢊ
ꢁ
ꢊ
ꢀ
ꢊ
0
0
ꢍꢆ ꢍꢅ ꢍꢄ ꢍꢃ ꢍꢂ ꢍꢁ ꢍꢀ ꢍ0
ꢑꢆ ꢑꢅ ꢑꢄ ꢑꢃ ꢑꢂ ꢑꢁ ꢑꢀ ꢑ0
ꢐꢄ ꢐꢃ ꢐꢂ ꢐꢁ
ꢐꢆ ꢐꢅ
ꢐꢀ ꢐ0
ꢍꢎꢊRꢎ
ꢍꢎꢏꢐ
ꢍꢑꢊ
ꢍꢋꢒ
ꢀ
ꢀ
0
ꢀ
0 ꢊꢋꢌ
ꢊꢋꢌ
ꢈ
ꢊꢋꢌ
ꢈ
ꢊꢋꢌ
ꢈ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢂꢈꢅꢅ ꢉ0ꢀ
Figure 1. I2C Write Transaction with PEC
// Bytewise CRC-8 for LT3966 using X8 + X2 + X + 1
// Takes a running sum (or 0) as <in>, and current byte to CRC as <data>
// Returns the CRC-8 of <in> and <data> for sending or further CRC’ing
int8_t doCRC(int8_t in, int8_t data){
int8_t crc;
int8_t i;
crc = in ^ data;
for(i = 0; i < 8; i++){
if (crc & 0x80) {
crc <<= 1;
crc ^= 0x07;
} else {
// XOR the incoming bytes
// Step through each bit
// If MSB is set
// Shift up, then
// XOR with the low byte of polynomial
// If MSB is unset
// Simply shift up
crc <<= 1;
}
}
// Repeat for rest of bits
// Finally, send back the result
return crc;
}
// Usage, where CHIPADDR, SUBADDR, and DATA are the bytes to send to LT3966
int8_t myCRC;
myCRC = doCRC(0, CHIPADDR);
myCRC = doCRC(myCRC, SUBADDR);
myCRC = doCRC(myCRC, DATA);
// myCRC now holds the completed PEC byte for sending to LT3966
Figure 2. Example Linduino® Code for Calculating CRC-8 PEC
2
Multiple transactions can take place before an I C stop by
using the repeated start signaling. Any start, including a
repeated start, restarts the CRC calculation for the new
transaction. The host system should calculate a new PEC
code for the bytes of that transaction, and the LT3966 will
evaluate the PEC code on a per transaction basis. A failure
in a single transaction will cause only that transaction’s
data to be discarded, and other successful transaction
data would be accepted.
several writes can take place with their action occurring
simultaneously upon execution of the stop signal.
2
Structure of an I C read is shown in Figure 3. It begins
with a write of Chip Address and Sub Address to set the
internal pointer. No PEC is required to set the pointer. A
stop/start pair, or repeated start, ends the write portion
and starts the read portion of the transaction. During a
read transaction, the PEC code is generated by LT3966
over the Chip Address and Data bytes, and is sent to the
host after the data byte. Reading the PEC code is manda-
tory. The host system should evaluate the PEC for validity
and respond accordingly.
Once all transactions are completed, the host system
can execute a stop signal to transfer the written data to
the output of the registers. The written data does not
take effect until a stop signal is detected. In this manner,
Rev. 0
12
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LT3966
OPERATION
I C OPERATION – I C ADDRESS SETTINGS
2
2
All other address selections start up with channels and
dimming generators enabled, but with the PWM DIM reg-
ister set to code 0 (0% on time). The converter channels
are active, but not switching since the DIM register is set
to 0. To enable light output, write a value to the chan-
nel’s DIM register, or write a channel’s DIMEN bit to 0 to
disable dimming and provide 100% LED on time. Faults
will be indicated in a channel’s STATUS register, but not
indicated on the ALERT pin unless the mask bit is enabled
for that channel.
Normal and Standalone Mode
ADR2, ADR1 = GND, GND programs the LT3966 into a
special standalone mode that does not require I C com-
2
munication. All channels are enabled, and all channel dim-
ming generators are disabled (100% on time). The device
will start up and immediately begin soft-start switching.
Analog and PWM dimming in standalone mode are con-
trolled by the channel CTRL/PWM pins. Faults are not
latched, but are indicated on the ALERT line.
ꢋꢖꢗꢐ ꢊꢑꢑRꢓꢍꢍ
ꢍꢘꢙ ꢊꢑꢑRꢓꢍꢍ
ꢀ
0
ꢀ
ꢊ
ꢂ
ꢊ
ꢁ
ꢊ
ꢀ
ꢊ
0
0
ꢍꢆ ꢍꢅ ꢍꢄ ꢍꢃ ꢍꢂ ꢍꢁ ꢍꢀ ꢍ0
ꢍꢎꢊRꢎ
ꢍꢎꢏꢐ
ꢊꢋꢌ
ꢍꢑꢊ
ꢍꢋꢒ
ꢀ
ꢀ
0
ꢀ
0 ꢊꢋꢌ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢊꢑꢑRꢓꢍꢍ
ꢑꢊꢎꢊ
ꢐꢓꢋ ꢔꢋRꢋꢕ
ꢀ
0
ꢀ
ꢊ
ꢂ
ꢊ
ꢁ
ꢊ
ꢊ
0
ꢀ
ꢑꢆ ꢑꢅ ꢑꢄ ꢑꢃ ꢑꢂ ꢑꢁ ꢑꢀ ꢑ0
ꢐꢄ ꢐꢃ ꢐꢂ ꢐꢁ
ꢐꢆ ꢐꢅ
ꢐꢀ ꢐ0
ꢀ
ꢍꢎꢊRꢎ
ꢍꢎꢏꢐ
ꢍꢑꢊ
ꢍꢋꢒ
ꢀ
ꢀ
0
ꢀ
ꢂ
ꢀ ꢊꢋꢌ
ꢊꢋꢌ
ꢊꢋꢌ
ꢈ
ꢁ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢂꢈꢅꢅ ꢉ0ꢂ
Figure 3. I2C Read Transaction with PEC
Table 1. I2C Address Settings
Write
Read
ADR2
GND
GND
GND
Float
Float
Float
ADR1
GND
Float
A3
A2
0
A1
0
A0
0
Address
Address
Mode
0
0
0
0
0
0
1
1
1
0xA0
0xA2
0xA6
0xA8
0xAA
0xAE
0xB8
0xBA
0xBE
0xA1
0xA3
0xA7
0xA9
0xAB
0xAF
0xB9
0xBB
0xBF
Standalone
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
0
0
1
V
0
1
1
CC
GND
Float
1
0
0
1
0
1
V
1
1
1
CC
V
V
V
GND
Float
1
0
0
CC
CC
CC
1
0
1
V
1
1
1
CC
Rev. 0
13
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LT3966
APPLICATIONS INFORMATION
PROGRAMMING THE LED CURRENT
On the high side of the CTRL/PWM range, the threshold
adjustment will roll over to a fixed maximum of 250mV
threshold as the CTRL/PWM pin exceeds 1.2V. To use
the fixed 250mV threshold, it is recommended to tie the
CTRL/PWM pin to a voltage higher than 1.2V. For conve-
The LED current is programmed using an external current
sense resistor and an adjustable sense threshold. The full-
scale value of this threshold is 250mV. Choose a current
sense resistor which will develop 250mV at the maximum
nience, the CTRL/PWM pin can simply be tied to INTV .
CC
LED current, I , Equation 1.
LED
The required CTRL/PWM voltage for a desired current
0.250mV
RISP
=
(1)
sense threshold is given by Equation 2.
(2)
ILED
VCTRLPWM = 4 • V
+ 0.2V
(ISP–ISN)
Adjustment of this current sense threshold in LT3966 is
generated from the combination of the external CTRL/
PWM pin voltage and the register value of an internal
multiplying DAC (MDAC). The relevant circuitry from the
block diagram is shown in Figure 4.
The overall profile of current sense threshold vs CTRL/
PWM voltage is shown in Figure 5.
The ADIM register takes the setpoint programmed by
the CTRL/PWM pin and applies to it an 8-bit DAC func-
tion, where code 0 is equal to 1/256th of the CTRL/PWM
threshold and code 255 is equal to the full CTRL/PWM
threshold. For the case of the fixed 250mV threshold, the
ADIM-adjusted threshold can be computed by Equation 3.
Both the CTRL/PWM pin and the ADIM register have the
ability to adjust the current sense threshold, and they
can be used independently or in combination. In gen-
eral, the CTRL/PWM pin is used for externally controlled
applications and the ADIM register is used for internally
controlled applications.
250mV • (ADIM + 1)
V
=
(3)
(ISP–ISN)
256
The CTRL/PWM pin provides a linear adjustment of the
current sense threshold over the range of 0.2V to 1.2V.
The low side of the CTRL/PWM range is set to allow a true
zero current setting while tolerating offset in any external
circuitry. Below 0.2V, the CTRL/PWM pin will be request-
ing zero LED current, and below 0.1V on CTRL/PWM will
be interpreted as a PWM off signal.
When adjusting with both external and internal control
in combination, it is important to consider the accuracy
of the overall system: Although it is possible to program
both the CTRL/PWM pin and the ADIM register to very
small values, the product of those two small values may
be too tiny for the amplifier to accurately regulate.
ꢀꢁꢂ
ꢀꢁ0
ꢀꢀꢁ
ꢀ00
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢂ
ꢀ00
ꢀꢁ
ꢝ0ꢞꢛ
Rꢙ
ꢉꢗꢕ
ꢟ
ꢟ
ꢠ
ꢠ
R
ꢉꢗꢕ
ꢉꢗꢘ
ꢉ
ꢐꢑꢆ
ꢙ.ꢚꢛ
ꢟ
ꢟ
ꢠ
ꢒꢆRꢅꢔ
ꢕꢖꢊ
ꢉ
Rꢏꢃ
ꢈꢇꢒꢓ
ꢅꢆꢀꢁꢂꢂ
ꢀ0
ꢇꢈꢉꢊꢋꢌꢍ0ꢎ
ꢀꢁ
Rꢙ
ꢜꢄ
0
0
0.ꢀ 0.ꢀ 0.ꢀ 0.ꢀ
ꢀ
ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.0
ꢀ
ꢀꢁꢂ
ꢀꢁRꢂꢃꢄꢅꢆ
ꢀꢁꢂꢂ ꢃ0ꢄ
ꢀꢁꢂꢂ ꢃ0ꢄ
Figure 4.
Figure 5.
Rev. 0
14
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LT3966
APPLICATIONS INFORMATION
FAULT DETECTION USING ISP, ISN
Since the gate charging current passes through the LED
current sense resistor, 2µs blanking time is added to the
LED overcurrent sensing to avoid false tripping during TG
transitions. This problem is most often seen when using
a high value sense resistor for a small LED current. An
alternative for this case is to use a smaller value sense
resistor and a lower ISP–ISN threshold by adjusting the
CTRL/PWM pin or ADIM register.
LT3966 uses the ISP, ISN sense amplifier to detect over-
current conditions in the LED. If the voltage between ISP/
ISN exceeds 150% of the regulation threshold (370mV),
an overcurrent fault is detected. The LT3966 will terminate
switching on the faulted channel and pull TG high to dis-
connect the output. The fault status will be latched in the
channel’s OC status bit, and the ALERT flag will assert if
reporting is enabled by the channel’s OC_EN bit.
PWM DIMMING
Response to overcurrent will depend on the state of that
channel’s LATOFF bit. If LATOFF is not set, the channel
will enter a 7168-cycle cooldown mode before retrying
a new soft-start cycle. This is commonly referred to as
“hiccup” mode. If the LATOFF bit is set, the channel will
stay in the off state until the fault or the LATOFF bit is
cleared by the host.
PWM dimming of LEDs provides efficiency, accuracy,
and color rendering benefits over analog dimming. The
LT3966 provides both internal and external control of LED
dimming. During PWM dimming off time, the switching
is suspended, the TG pin is pulled up to turn off the
external PMOS, and the internal control voltages are tri-
stated to hold their value. In this manner, the chip can
quickly resume its appropriate operating condition at next
LED turn-on.
For the case of a problem with the LT3966 voltage feed-
back, an additional limiter is incorporated to regulate the
ISP pin to a maximum of 62V. If the ISP pin reaches 62V,
the switching setpoint will be reduced to prevent the ISP
pin from exceeding 62V.
External LED dimming is controlled using the CTRL/PWM
pin, and internal dimming is controlled using the onboard
dimming generator. The final dimming control signal is
the logical AND of both the CTRL/PWM input and the
internal dimming generator. When the dimming generator
is disabled by the DIMEN bit or by standalone mode, the
dimming is controlled solely by the CTRL/PWM pin. The
logical representation is shown in Figure 7.
TG DRIVER AND EXTERNAL PMOS SELECTION
PWM dimming and output disconnect are controlled
by the TG pin through the use of an external PMOS
pass device. TG provides a level-shifted MOSFET driver
intended to drive the gate of the external PMOS between
V
and V – 8.2V.
ISP
ISP
ꢅꢆꢀꢁꢂꢂ
ꢒꢆRꢅꢗ
ꢘꢙꢌ
0.ꢇꢈ
ꢑꢒꢅꢓꢔꢕ0ꢖ
ꢊꢋꢌꢓꢇꢔꢕ0ꢖ
ꢃꢄꢅ
R
ꢃꢄꢅ
ꢚꢏꢌ
ꢃꢄꢏ
ꢊꢀꢒꢓꢔꢔ
ꢅꢐꢑ
ꢊꢋꢌꢌꢋꢍꢉ
ꢉꢎꢍꢎRꢏꢆꢐR
ꢆꢉꢇ
ꢃLR
ꢊꢋꢌꢎꢍ
ꢀꢁꢂ
ꢀAꢁLTꢂ
ꢊꢋꢌ
ꢊꢍꢎꢌ
ꢃꢄꢅ ꢆ ꢇ.ꢈꢉ
ꢒꢓꢔꢔ ꢕ0ꢔ
ꢀꢁꢂꢂ ꢃ0ꢄ
Figure 6.
Figure 7.
Rev. 0
15
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LT3966
APPLICATIONS INFORMATION
It is important to note that both the DIMEN signal and
the CTRL/PWM pin have the ability to clear the dimming
generator’s counter. This is advantageous when using a
combination of internal dimming and external ON/OFF
control with CTRL/PWM. By restarting the dimming gen-
erator’s counter in sync with the external ON/OFF signal,
light output remains flicker free from full duty cycle to zero.
the dimming resolution, and also the dimming frequency
based on the MCLK value set by R , Equation 4.
T
fSW
2(6+SCL)
(4)
fDIM
=
For example, a 13-bit dimming cycle using SCL = 111b
would provide 8192:1 resolution at a dimming frequency
of 244Hz using a 2MHz MCLK frequency (R = 47.5k).
T
The CTRL/PWM threshold for PWM dimming is 0.1V. For
simple on/off control, the PWM pin can be driven with any
standard logic signal between 1.5V and 5V. For dimming
with analog control, drive the pin with a DAC providing
output shutdown, or simply shunt a resistor divider using
a small NMOS transistor (Figure 8).
The DIM[12:0] and BAM registers control the duty
cycle and modulation strategy of the dimming genera-
tor. In PWM (Pulse-Width Modulation) dimming mode
(BAM = 0), the PWMOUT signal is high while the value
in the DIM register is greater than the Counter. In BAM
(Bit-Angle Modulation) mode, the PWMOUT signal is high
anytime the MSB of the Counter matches the position of
a 1 in the value in the DIM register.
ꢅꢆꢀꢁꢂꢂ
ꢌꢍꢆꢎ
ꢇꢇ
A comparison of the resulting waveforms of each of these
strategies is shown in Figure 10. For a DIM value of 13,
PWM mode provides a single pulse of 13 clock cycles
starting at the 1st counter cycle. BAM mode provides
pulses of duration 1, 4, and 8 cycles at the 1st, 4th, and
8th counter cycle, respectively. The total pulse duration
in BAM mode still equals 13-clock cycles.
ꢇꢆRꢅꢈ
ꢉꢊꢋ
ꢀWꢁ
ꢀꢁꢂꢂ ꢃ0ꢄ
Figure 8.
The internal dimming generator is based on a vari-
able-length counter updated at the master clock rate, deter-
mined by R . An overview of the logic is shown in Figure 9.
ꢄꢀ
T
ꢅꢆꢇ
ꢄ
ꢌ
ꢋ
ꢊ
ꢈꢉꢇ
ꢀꢁꢂꢂ ꢃꢄ0
ꢆꢇꢈꢉꢊꢋꢌ0ꢍ
Figure 10.
ꢘꢀꢑꢉꢋꢌ0ꢍ
ꢎꢏRꢇꢏꢐꢑꢅ ꢑꢅꢃꢒꢄꢓ
ꢔꢕꢖꢊꢗ ꢐꢇꢄꢘꢙ ꢀꢁꢈꢚꢏRꢅ
ꢚꢝꢈꢁꢂꢄ
The duty cycle of the dimming generator can be com-
puted using Equation 5.
ꢐꢏꢈ
ꢀꢁꢂꢃꢄꢅR
DIM
2(6+SCL)
(5)
Duty =
ꢆꢇꢈꢈꢇꢃꢒ ꢒꢅꢃꢅRꢏꢄꢁR
ꢗꢛꢕꢕ ꢜ0ꢛ
Figure 9.
The system should be aware of the counter scale as
defined by SCL, and avoid writing DIM values larger than
the maximum value of counter. In the case where a DIM
value is larger than the counter range, the DIM value will
be truncated below bit (6+SCL). A DIM value of 0 0000
0000 0001 would be interpreted as 0 in all cases except
SCL = 111b.
The scale (SCL[2:0]) bits set the compare length and cycle
length of the dimming generator, from 6-bit at SCL = 000b,
to 13-bit at SCL = 111b. This cycle length determines
Rev. 0
16
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LT3966
APPLICATIONS INFORMATION
DIMMING CODE CHANGES AND DIMMING
SYNCHRONIZATION
Choose R1 and R2 so that the output voltage reaches the
desired maximum when FB reaches its 1.2V regulation point,
Equation 6.
To ensure glitch-free changes of the DIM, a new value
of DIM is only loaded upon completion of the previous
dimming cycle, at the rollover of the counter to 0. This
prevents short or otherwise malformed pulses at the out-
put, but will introduce a small latency depending on the
dimming cycle length.
R1
R2
⎛
⎝
⎞
(6)
VOUT = 1.2 • 1+
⎜
⎟
⎠
For the case of driving LEDs, the output voltage setting
should be programmed higher than the maximum forward
voltage of the LEDs being driven, when accounting for
process and temperature variation.
If a channel’s dimming generator is disabled by setting the
DIMEN bit to 0 or by bringing the channel’s CTRL/PWM pin
low, the counter for that channel will be halted and cleared
to 0. Upon re-enabling the dimming generator, the counter
value may not be synchronized to the other channels.
LT3966 allows all dimming generators on the I2C bus
to be synchronized by initiating a write to the broadcast
address, 0x18 (Figure 11).
FAULT DETECTION USING FB
LT3966 uses the FB pin voltage to detect shorted and
overvoltage output conditions, as well as open output
conditions. The conditions for these faults and response
are as follows:
n
A shorted output is detected by the FB voltage remain-
ꢓRꢏꢊꢑꢋꢊꢍꢎ ꢊꢑꢑRꢔꢍꢍ ꢕꢖRꢗꢎꢔꢘ
ing at 300mV or lower after the device’s soft-start has
completed. In response, the channel’s SHORT status
bit will be asserted, and the device’s ALERT pin will
also assert if SHORT_EN is set. The device will either
latchoff or enter a hiccup retry cycle dependent on the
state of the faulted channel’s LATOFF bit.
0
0
0
ꢀ
ꢀ
0
0
0
ꢍꢎꢊRꢎ
ꢍꢎꢏꢐ
ꢍꢑꢊ
ꢍꢋꢒ
0
ꢀ
0
0
ꢀ
ꢀ
0
0
ꢆ
0 ꢊꢋꢌ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢇ
ꢈ
ꢂꢈꢅꢅ ꢉꢀꢀ
Figure 11. I2C Broadcast Write
n
Output overvoltage is detected by the FB pin exceeding
the regulation point by 60mV (1.26V total). In response,
the channel’s OVFB status bit will be asserted, and the
device’s ALERT pin will also assert if OVFB_EN is set.
The device will stop switching and raise TG to discon-
nect the output, and will resume normal operation once
the FB has fallen by 25mV.
When synchronizing the dimming generators or enabling a
dimming generator by changing the DIMEN bit from 0 to 1,
a one-clock low time will be seen at the output as the
device clears the counter and loads the latest DIM code.
FB OUTPUT VOLTAGE SETTING
n
An open output is detected by the combination of FB
An output voltage limit is required for the case of an
open LED strand. By connecting FB to a resistor divider
between the output voltage and GND, a maximum output
voltage limit can be set (see Figure 12).
voltage reaching at least 1.15V and the LED current
falling to less than 10% of full-scale value. In response,
the channel’s OPEN status bit will be asserted, and
the ALERT pin will also assert if OPEN_EN is set. This
condition is considered to be standard constant voltage
regulation, and the channel will continue to switch
while regulating FB to 1.2V.
ꢉ
ꢊꢋꢇ
ꢆꢇꢀꢁꢂꢂ
Rꢄ
Rꢅ
ꢃꢈ
ꢀꢁꢂꢂ ꢃꢄꢅ
Figure 12.
Rev. 0
17
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LT3966
APPLICATIONS INFORMATION
ENABLE AND EXTERNAL UVLO
If the EN pin is used in a multiple-tap resistor divider,
be aware that although the pin voltage may safely reach
60V, a small amount of current will be drawn when EN is
greater than 6V.
The LT3966 enable pin provides a high voltage tolerant
precision comparator and a 2µA hysteresis current source
for generating programmable external UVLO.
The EN pin can be driven with a logic level signal greater than
1.5V for simple ON/OFF control, or can be tied to the input
(up to 60V) for always-on operation. The pin is internally
clamped to 6V through a 1MEG resistor, and will draw a small
amount of current when driven to a voltage greater than 6V.
FREQUENCY SETTING USING RT
LT3966 uses a single master oscillator from which all
internal clocks and the switching clocks are derived.
2
Through I C, the channels can be programmed to switch
90° out of phase.
To use the EN pin as an external UVLO, simply tie the EN
pin to a resistor divider between VIN and GND (Figure 13).
The shutdown (falling threshold) is 1.23V and the ris-
ing threshold provides 15mV internal hysteresis plus
user-programmable external hysteresis through the use
of a 2µA hysteresis current that is active anytime the EN
pin is below the threshold.
Switching frequency is set with a single resistor from the
RT pin to GND.
ꢆꢇꢀꢁꢂꢂ
Rꢇ
ꢀꢁꢂꢂ ꢃꢄꢅ
ꢉ
ꢊꢈ
ꢅꢆꢀꢁꢂꢂ
R
ꢇ
Rꢀ
Rꢋ
ꢇꢈ
Figure 14.
ꢀꢁꢂꢂ ꢃꢄꢀ
Determine the proper RT value for a desired switching
frequency using Table 2 or Table 3.
Figure 13.
To select an appropriate resistor divider for the EN pin, first
determine the top resistor required for the desired hystere-
sis. Larger value resistors provide more external hysteresis
due to the 2µA hysteresis current source, Equation 7.
Table 2. Single-Phase Switching Frequency vs RT Value
SWITCHING FREQUENCY (SINGLE-PHASE)
R (kΩ)
T
300kHz
400kHz
500kHz
600kHz
700kHz
800kHz
900kHz
1MHz
499
261
205
174
147
127
113
100
82.5
69.8
59
VHYST – 0.015V
(7)
R3 =
2µA
A common choice is 487k for roughly 1V total hysteresis.
Next, determine the bottom resistor value by program-
ming the accurate falling UVLO threshold based on R3
and the 1.23V EN falling threshold, Equation 8.
1.2MHz
1.4MHz
1.6MHz
1.8MHz
2MHz
R3
R4 =
(8)
V
⎛
⎜
⎝
⎞
⎟
⎠
EN-FALL
1.23
–1
52.3
47.5
The UVLO rising threshold will therefore be given by Equation 9.
1 + R3
R4
(9)
VEN-RISE
=
+ 2µA • R3
Rev. 0
18
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LT3966
APPLICATIONS INFORMATION
Table 3. Multi-Phase Switching Frequency vs RT Value
system. In this mode, the SYNC pin outputs a 50% duty
square wave of 0V to 2.5V. To use SYNC as an output,
the SYNCOUT register bit should be set to 1. Do not drive
the SYNC pin with an external clock when the SYNCOUT
bit is set.
SWITCHING FREQUENCY (MULTI-PHASE)
R (kΩ)
T
300kHz
400kHz
500kHz
600kHz
700kHz
800kHz
900kHz
1MHz
174
127
100
82.5
69.8
59
MULTIPHASE SWITCHING
To reduce input ripple current, the four boost converters
can operate in 4-phase mode, where the rising edge of
each converter’s switching cycle is separated by 90° of
phase shift.
52.3
47.5
37.4
31.6
27.4
23.7
21
1.2MHz
1.4MHz
1.6MHz
1.8MHz
2MHz
To enable multiphase operation, set the MPHASE reg-
ister bit to 1. In multiphase operation, the boost con-
verter clocks run at half the speed of MCLK set by R ,
T
and their phase is shifted by 90° per channel as illustrated
in Figure 15.
RT LIMITS
ꢀꢁꢂꢃꢄ
In order to provide safe and reliable operation, both min-
imum and maximum limits are set on the oscillator range
using RT. For the case of an open circuit on RT, a low limit
of roughly 230kHz is provided through a small internal
bias. The RT pin itself is also current limited to provide
an upper limit and to protect against a short circuit on the
RT pin. This limit is 125µA, corresponding to a maximum
frequency of roughly 7.5MHz.
ꢅꢆꢇꢈꢂꢉꢊꢋꢌꢍꢅꢉ
ꢀꢎꢂꢏꢆꢋꢌꢍꢅꢉ
ꢅꢐꢑ
ꢅꢐꢒ
ꢅꢐꢓ
ꢅꢐꢔ
ꢓꢕꢖꢖ ꢗꢑꢘ
Figure 15.
FREQUENCY SYNCHRONIZATION INPUT AND OUTPUT
Typically, the MCLK frequency is set using R to be equal
T
The LT3966 provides a bidirectional clock synchroniza-
tion pin, SYNC, for synchronization input and output. The
default state of SYNC is an input, used to synchronize
the LT3966 to an external clock source. Drive the SYNC
input with any logic-level clock output from 1.5V to 5V
to provide external synchronization. Duty cycle of the
external clock is not critical as long as the high time of
the incoming clock is greater than 100ns. When synchro-
to 2× the desired switching frequency when multiphase
switching is used.
Although the boost channels operate at half frequency,
the system MCLK continues to operate at the frequency
determined by RT. This simplifies synchronization to other
LT3966 devices, since the SYNC output and SYNC input
always uses the full MCLK frequency determined by R
T
nizing to an external clock, the R resistor should be set
T
regardless of the multiphase setting of any individual
LT3966. However, since the ADC converter is clocked from
the master clock, using very high frequency MCLK set-
tings may require the use of the ADC clock prescaler. More
details on this setting are available in the ADC section.
to give an unsynchronized frequency roughly 5% lower
than the expected synchronization frequency. This mini-
mizes disturbances during any transitions from internal
to external clock.
The SYNC pin can also be programmed as an output, to
provide a synchronization signal to other LT3966 in the
Rev. 0
19
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LT3966
APPLICATIONS INFORMATION
IN PHASE/OUT OF PHASE DIMMING
frequency allows the use of smaller inductance value at
the expense of increased switching loss.
To reduce input ripple current, each channel’s dimming
operation can be independently programmed in one of
the two modes: in-phase mode and out-of-phase mode
(see Figure 16). When operating in in-phase mode, the
start of CH2/CH3/CH4’s dimming cycle is aligned with
CH1’s. When operating in out-of-phase mode, the start
of CH2/CH3/CH4’s dimming cycle is behind of CH1’s by a
quarter/a half/three quarters of CH2/CH3/CH4’s dimming
cycle. To enable the in-phase/out-of-phase operation, set
the INPH register bit to 1/0. Please note that after the
The saturation current rating of the inductor should be
selected appropriately for the 2.4A current limit of the
LT3966. An approximation for maximum inductor cur-
rent (efficiency = 100%) is based on the maximum LED
current and the input-output ratio, Equation 10.
VOUT
IL =
•ILED
(10)
V
IN
The desired inductance is determined by the steady-state
current ripple. A typical rule of thumb is to set the inductor
current ripple to a maximum of 20% of the maximum induc-
tor current, Equation 11, Equation 12 and Equation 13.
2
INPH bit change, an I C broadcast write (see Figure 11) is
required to reset all dimming generators for this function
to work properly.
Boost:
POWER COMPONENT SELECTION
⎛
⎞
V
IN(MIN) •(VOUT(MAX) – V
)
IN(MIN)
Since the LT3966 is an internally-compensated converter,
the external power components are selected to ensure
system stability. By following a few simple guidelines, this
process can be made simple and streamlined.
LBOOST
≥
(11)
(12)
⎜
⎟
VOUT(MAX) • 0.45A • fSW
⎝
⎠
Buck:
⎛
⎞
VOUT(MAX) •(VIN(MIN) – VOUT(MAX)
)
Inductor Selection
LBUCK
≥
⎜
⎟
VIN(MIN) • 0.45A • fSW
⎝
⎠
Inductor selection consists of two parameters: saturation
current rating, and inductance value. Higher switching
ꢆꢇ ꢈꢁꢉꢊꢋ ꢌꢆꢍꢍꢆꢇꢎ ꢏꢆꢇꢈꢁ ꢐ ꢂꢑ
ꢀꢁꢂ
ꢀꢁꢃ
ꢀꢁꢄ
ꢀꢁꢅ
ꢂꢖꢅ ꢌꢆꢍꢍꢆꢇꢎ
ꢀꢗꢀꢘꢋ
ꢒꢓꢔ ꢒꢕ ꢈꢁꢉꢊꢋ ꢌꢆꢍꢍꢆꢇꢎ ꢏꢆꢇꢈꢁ ꢐ 0ꢑ
ꢀꢁꢂ
ꢀꢁꢃ
ꢀꢁꢄ
ꢀꢁꢅ
ꢄꢙꢚꢚ ꢕꢂꢚ
Figure 16.
Rev. 0
20
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LT3966
APPLICATIONS INFORMATION
Buck-Boost:
FAULTS AND FAULT HANDLING
V
IN(MIN) •VOUT(MAX) / VIN(MIN) + VOUT(MAX)
⎛
⎞
Status Bits and ALERT
LBUCK
≥
(13)
⎜
⎟
0.45A • fSW
⎝
⎠
The LT3966 has independent fault handling for each
LED driver channel. Four types of faults are detected:
LED Overcurrent, Shorted LED, Open LED, and Output
Overvoltage. Additional information on the detection con-
ditions is provided in the LED current sense amplifier, and
FB amplifier sections.
Table 4 provides some recommended inductor vendors.
Table 4. Inductor Manufacturers
VENDOR
WEB
Wurth Elektronik
Coilcraft
www.we-online.com
www.coilcraft.com
www.cooperet.com
As described, each type of fault is indicated in a channel’s
status bit and can optionally be indicated on the open-
drain ALERT pin through the setting of fault enable bits in
the same register. When a fault’s enable bit is set, the fault
status will be latched and the ALERT pin will be asserted
if a fault is detected. Write a 0 to the status bit to clear, or
write a 0 to the status bit enable bit to clear and disable
the fault. If a fault’s EN mask bit is not set, reading the
status bit will always give the status of the fault at that
time, but the status will not be latched nor indicated on
the ALERT pin.
Cooper
Output Capacitor Selection
In addition to smoothing the output voltage, the output
capacitor in combination with the small signal forward
resistance of the LEDs provides an output pole for the
frequency compensation.
The LED forward resistance (RLED) is determined from
the LED data sheet, and is roughly 10Ω for the case of
a typical 150mA LED. Forward resistance is highest at
low currents, and lowest at the maximum drive current.
The total forward resistance of a series strand of LED is
In standalone mode, the mask bits are ignored and the
logical OR of all faults is indicated on the ALERT pin. This
indicator is not latched, and will only be asserted as long as
a fault is present. The ALERT pin will return to high imped-
ance when no faults are detected in standalone mode.
n • R , where n is the number of LEDs in the strand.
LED
For the LT3966, we choose C
to keep the minimum
OUT
frequency of the output pole > 2kHz, Equation 14.
1
Hiccup and Latchoff Mode
(14)
COUT
≤
12500•n • RLED
The LED overcurrent and shorted LED conditions result in
an internal fault response that is dependent on the state
of the channels’ latchoff (LATOFF) bit. In the case of one
of these faults, switching is terminated, the channel’s TG
pin is pulled high to disconnect the output, and the device
waits for a 7168-cycle cooldown period.
In most cases, a 2.2µF output capacitor is a suitable choice.
Schottky Rectifier Diode
The power Schottky diode conducts the switching current
during the power switch off time. Select a diode rated for
at least 1.5 • ILED to provide operating margin. The reverse
breakdown voltage should be at least 20% greater than
the maximum output voltage expected in circuit. Keep in
mind that in the case of disconnected LEDs, the output
voltage will be driven to the limit defined by the FB divider.
At this point if the channel’s LATOFF bit is set, the device
will stay in this non-switching rest state until reset by tog-
gling the EN pin or system power, toggling the channel’s
OFF bit, or by clearing the LATOFF bit itself.
If the channel’s LATOFF bit is not set, the device will
attempt a new soft-start cycle after completion of the
cooldown period. Sustained faults will result in continuing
cooldown and retry attempts, often referred to as “hic-
cup” mode (see Figure 17 and Figure 18).
Rev. 0
21
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LT3966
APPLICATIONS INFORMATION
a new broadcast attempt while keeping the ALERT line
asserted. Once LT3966 successfully completes arbitration
it will release its’ pull-down on the ALERT line. The fault
status bits can then be read by the host to determine the
cause of the ALERT.
ꢀ
ꢁꢂꢃꢄꢅꢆ
ꢇ0ꢀꢈꢉꢃꢀ
ꢀꢁꢂRꢃ
ꢄꢅꢆꢇꢈꢅ
ꢀꢁꢂRꢃꢄꢅ ꢂꢆꢃꢇꢆꢃ
ꢀꢁꢂꢂꢃꢄꢅ
Once an ARA arbitration has released the ALERT line, the
LT3966 will not pull the ALERT line low again until the
faulted status bit has been cleared, and a new fault has
been detected.
ꢀ
ꢁꢂꢃ
ꢄꢅꢆꢃꢀꢇ
ꢀꢁꢂꢂ ꢃꢄꢅ
ꢀꢁꢂꢃꢄꢅꢆ
Figure 17. Scope Shot – HICCUP
ADDITIONAL FEATURES
Watchdog Timer
ꢀ
ꢁꢂꢃꢄꢅꢆ
ꢇ0ꢀꢈꢉꢃꢀ
2
To ensure reliability against a break in the I C bus, an
optional watchdog timer feature is available. The watchdog
timer is enabled through the WDTEN bit in register 0x00.
ꢀꢁꢂRꢃ
ꢄꢅꢆꢇꢈꢅ
ꢀꢁꢂRꢃꢄꢅ ꢂꢆꢃꢇꢆꢃ
The watchdog timer contains a standalone 40kHz oscil-
lator and 100ms counter that is reset by the detection
ꢀ
ꢁꢂꢃ
ꢄꢅꢆꢃꢀꢇ
2
ꢀꢁꢂꢂ ꢃꢄꢅ
of any I C start condition on the bus. Once enabled, the
ꢀꢁꢂꢃꢄꢅꢆ
watchdog requires the host to occasionally initiate an
I2C transaction using an I2C start. Data transfer is not
required to reset the watchdog timer.
Figure 18. Scope Shot – LATOFF
Broadcast Alert Response
In the event that the 100ms watchdog period expires
2
In order to determine which device on a common bus is
faulted, the LT3966 supports Broadcast Alert Response
on the standard address of 0001100 (Figure 19). Any
LT3966 with a fault on an enabled fault status bit will
enter arbitration upon receiving a broadcast read com-
mand (0x19). PEC is not used during arbitration. It is
neither sent, not expected. During arbitration, the faulted
LT3966 will attempt to clock out its own address to the
without detecting an I C start, the LT3966 will reset to
the power-on default conditions and the watchdog flag
bit (WDTFLAG) will be set in register 0x00.
Device ID Register
The LT3966 contains a device identifier in the highest
three addresses in the register space. When read, the
addresses 0xFD, 0xFE, and 0xFF will contain the BCD-
encoded values 03, 96 and 60, respectively.
2
host. Since the I C data line is common drain, the device
with the lowest address will eventually win arbitration by
outputting a 0 when other devices attempt to output a
1. If the LT3966 fails arbitration, it will stop and wait for
ANALOG-TO-DIGITAL CONVERTER OPERATION
ADC Structure and Operation
ꢊRꢋꢇꢌꢈꢇꢅꢆ ꢇꢌꢌRꢍꢅꢅ ꢎRꢍꢇꢌꢏ
ꢇꢖꢍRꢆ Rꢍꢅꢕꢋꢘꢅꢍ ꢃRꢋꢙ ꢖꢆꢀꢁꢂꢂ
0
ꢗ
ꢗ
ꢄ
0
0
0
ꢄ
ꢄ
0
0
ꢄ
ꢄ
ꢗ
ꢗ
ꢄ
LT3966 contains an 11-input, 8-bit SAR ADC used to mea-
sure various parameters of the system. These parameters
include FB voltage and LED current for each of the 4 LED
driver channels, scaled input voltage, and two uncommit-
ted external inputs. An overview of the ADC architecture
ꢅꢆꢋꢕ
ꢅꢆꢇRꢆ
ꢇꢈꢉ
ꢁ
0
0
ꢄ
0
ꢐ
0
ꢀ
ꢄ
ꢑ
ꢄ
ꢒ
0
0
ꢄ
ꢔ
ꢄ
ꢅꢌꢇ
ꢅꢈꢖ
ꢄ
ꢀ
ꢄ ꢘꢇꢈꢉ
ꢂ
ꢓ
ꢄ
ꢐ
ꢑ
ꢒ
ꢂ
ꢓ
ꢔ
ꢁ
ꢀꢁꢂꢂ ꢃꢄꢁ
Figure 19. I2C Broadcast Alert Response
is shown in Figure 20.
Rev. 0
22
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LT3966
APPLICATIONS INFORMATION
ꢚꢙꢏꢢꢙꢏ RꢍꢗꢉꢅꢏꢍRꢅ
and enters sleep mode. Reading the ADC result without
clearing the RUN bit will trigger a new conversion at the
0ꢎꢖꢐ
0ꢎꢖꢛ
0ꢎꢖꢋ
0ꢎꢖꢖ
0ꢎꢖꢝ
0ꢎꢖꢕ
0ꢎꢖꢌ
0ꢎꢖꢜ
0ꢎꢖꢄ
0ꢎꢖꢓ
0ꢎꢖꢂ
ꢈꢉꢊꢋꢌ
ꢍꢎꢏꢐ
ꢍꢎꢏꢑ
ꢈꢒꢓꢐ
ꢉꢔꢍꢃꢐ
ꢈꢒꢓꢑ
ꢉꢔꢍꢃꢑ
ꢈꢒꢓꢛ
ꢉꢔꢍꢃꢛ
ꢈꢒꢓꢋ
ꢉꢔꢍꢃꢋ
2
ꢏꢗꢏꢞꢛꢟ0ꢠ ꢂꢔꢡꢅꢍꢔꢞꢐꢟ0ꢠ
I C Stop signal following the data read. In this manner,
an unlimited number of conversions and reads can be
executed in series.
ꢂꢚꢊꢏRꢚꢔ
ꢔꢚꢗꢉꢂ
ꢄꢙꢏꢚ
ꢅꢇꢉꢒꢏ RꢍꢗꢉꢅꢏꢍR
ꢂꢃꢄꢂ
When repeated conversions are used, a conversion time
2
(t
) of at least 20ADC clock periods between an I C
CONV
ꢐ.ꢑꢕꢖꢈ
ꢗꢊꢃ
2
ꢀ
ꢁ
Stop and the next I C Start is required to complete the
conversion before data can be read. This time is depen-
ꢈꢉꢊꢆꢋꢌ
ꢍꢎꢏꢐ
ꢍꢎꢏꢑ
ꢄꢃꢂ
ꢘꢙꢎ
dent upon R and the value in the ADC’s CLKSEL register
T
ꢅꢆꢇ
ꢛꢜꢝꢝ ꢒꢐꢕ
2
ꢒꢓꢐꢁꢋ
bits. If a new I C Start occurs before the data is ready,
ꢈꢔꢍꢃꢐꢁꢋ
the data read will be the prior conversion’s data, and the
2
new data will be transferred upon the next I C Stop. The
Figure 20. Scope Shot – LATOFF
appropriate timing is shown in Figure 21.
When measuring a voltage, the range of the ADC is 0V to
1.275V and the LSB is 5mV.
Automatic Mode
The ADC will operate in automatic mode when the AUTO
bit is set. In this mode, the ADC runs continuously, mea-
suring each active input and updating the target data reg-
ister. This sequence repeats indefinitely, and does not wait
The ADC can be used in manual (single) or automatic
mode. In manual mode, one conversion is taken for a
single target specified by the TGT[3:0] register, and the
result is stored in the target’s data register. The ADC pow-
ers down after completion. In automatic mode (RUN =
AUTO = 1), all active targets will be continuously mea-
sured in a round-robin fashion. When the last target is
completed, the converter will start again with the first
target. This ensures that fresh data is available for all
enabled targets at any given time.
2
for an I C Stop to begin the next round of conversions.
Additionally, data can be read at any time. In this man-
ner, automatic mode will always provide fresh data for all
active targets.
In the case of a disabled channel (OFF = 1), both the FB
and I
measurements for that channel will be skipped.
LED
For a channel that is enabled, but is in a PWM off time
from either CTRL/PWM or dimming generator low time,
the converter will not skip that channel but will instead wait
for the channel’s PWM signal to rise before sampling. Be
aware that when using CTRL/PWM for external dimming,
long off times in the external signal will result in equivalent
pauses in the ADC converter’s measurement sequence.
Manual Mode – Repeated Conversions
In manual mode (RUN = 1, AUTO = 0), multiple repeated
conversions on the same target can be performed with lit
tle overhead. The first conversion starts upon detection of
the I2C Stop signal in the transfer in which the ADC’s RUN
bit is written to 1. The ADC completes one conversion
-
ꢀ
ꢀ
ꢁꢂꢃꢄ
ꢁꢂꢃꢄ
ꢁꢇꢍ ꢅꢇꢎꢋꢍꢈ
ꢁꢂꢃꢄꢈRꢅꢉꢂꢃ ꢃ
ꢆRꢇꢃꢅꢏꢈR
ꢁꢇꢍ ꢅꢇꢎꢋꢍꢈ
ꢁꢂꢃꢄꢈRꢅꢉꢂꢃ ꢃ ꢐ ꢑ ꢆRꢇꢃꢅꢏꢈR
ꢅꢆꢇRꢆ ꢁꢂꢃꢄꢈRꢅꢉꢂꢃ
ꢅꢆꢇRꢆ ꢁꢂꢃꢄꢈRꢅꢉꢂꢃ
ꢅꢌꢇ
ꢅꢁꢍ
ꢁꢖꢉꢋ ꢇꢌꢌRꢈꢅꢅ
ꢌꢇꢆꢇ ꢃ
ꢋꢈꢁ
ꢒꢓꢔꢔ ꢏꢑꢕ
ꢊ
ꢊ
ꢊ
ꢉ ꢁ ꢅꢆꢂꢋ
ꢉ ꢁ ꢅꢆꢇRꢆ
Rꢈꢇꢌ ꢇꢌꢁ Rꢈꢅꢗꢍꢆ
ꢉ ꢁ ꢅꢆꢂꢋ
Figure 21.
Rev. 0
23
For more information www.analog.com
LT3966
APPLICATIONS INFORMATION
When switching from manual to automatic mode, con-
version will start from the target specified by TGT[3:0].
the EXT1 and EXT2 inputs will draw current but no dam-
age will occur. For any voltage above 1.275V, the ADC
conversion will read full scale, 0xF F.
ADC Target 0 – VIN/48
ADC Targets 4–11 – LED Driver Parameters
The first target (TGT = 000) is a 1/48th scaled version
of the chip input voltage, suitable for monitoring input
voltage or battery state. The resolution of 5mV/LSB and
48× scale results in a resolution at the input of roughly
The final 8 targets are FB voltage, and LED current for
each of the 4 channels in turn. The FB measurement is a
direct representation of the voltage at the FB pin, and the
LED current measurement is a 4× multiplied version of
the sense voltage between ISP and ISN.
240mV/LSB. Input range for V is 3V to 60V, resulting in
IN
a code range of roughly 12 to 250 decimal. To determine
the input voltage from the conversion data, use Equation
15.
ADC Clock Selection
The ADC clock is derived from the system master clock,
MCLK, programmed by RT. For best results, an ADC clock
between 1μs and 2μs is recommended. Scaling down of
MCLK to ADC clock is accomplished through the use of
the CLKSEL[1:0] bits.
(15)
V
(V) = 0.24 • V [7:0]
IN
IN
ADC Targets 2–3 – External Inputs
LT3966 provides two external analog inputs to the ADC,
on EXT1 and EXT2. The working range of these inputs are
0V to 1.275V, and the conversion resolution is 5mV/LSB.
CLKSEL[1:0]
ADC CLOCK
MCLK
00
01
10
11
The EXT1 and EXT2 inputs are internally clamped to 1.7V
with a 2k series resistance, but the pins are rated up to
5.5V ABSMAX. If the clamp voltage of 1.7V is exceeded,
MCLK/2
MCLK/4
MCLK/8
Rev. 0
24
For more information www.analog.com
LT3966
REGISTER TABLE
ADDR
NAME
DESCRIPTION
b7
b6
b5
b4
b3
b2
b1
b0
Global Registers
0x00
Channel 1
0x10
GLBCFG
Global Config
WDTFLAG
WDTEN
MPHASE
CLKOUT
OFF4
OFF3
OFF2
OFF1
STAT1
CFG1
Status/Status CFG
Channel 1 Config
OC_EN 1
x
SHORT_EN1
x
OPEN_EN1
x
OVFB_EN1
x
OC1
SHORT1
FLAT1
OPEN1
BAM1
OVFB1
DIMEN1
DIM10
0x11
INPH1
DIM13
DIM18
ADIM13
0x12
DIM1H
DIM1L
ADIM1
PWM Dim Value CH1
PWM Dim Value CH1
Analog Dimming CH1
SCL12
DIM112
ADIM17
SCL11
SCL10
DIM110
ADIM15
DIM14
DIM19
ADIM14
DIM12
DIM17
ADIM12
DIM11
DIM16
ADIM11
0x13
DIM111
ADIM16
DIM15
0x14
ADIM10
Channel 2
0x20
STAT2
CFG2
Status/Status CFG
Channel 2 Config
OC_EN 2
x
SHORT_EN2
x
OPEN_ EN2
x
OVFB_EN2
x
OC2
SHORT2
FLAT2
OPEN2
BAM2
OVFB2
DIMEN2
DIM20
0x21
INPH2
DIM23
DIM28
ADIM23
0x22
DIM2H
DIM2L
ADIM2
PWM Dim Value CH2
PWM Dim Value CH2
Analog Dimming CH2
SCL22
DIM212
ADIM27
SCL21
SCL20
DIM210
ADIM25
DIM24
DIM29
ADIM24
DIM22
DIM27
ADIM22
DIM21
DIM26
ADIM21
0x23
DIM211
ADIM26
DIM25
0x24
ADIM20
Channel 3
0x30
STAT3
CFG3
Status/Status CFG
Channel 3 Config
OC_EN3
x
SHORT_EN3
x
OPEN_EN3
x
OVFB_EN3
x
OC3
SHORT3
FLAT3
OPEN3
BAM3
OVFB3
DIMEN3
DIM30
0x31
INPH3
DIM33
DIM38
ADIM33
0x32
DIM3H
DIM3L
ADIM3
PWM Dim Value CH3
PWM Dim Value CH3
Analog Dimming CH3
SCL32
DIM312
ADIM37
SCL31
SCL30
DIM310
ADIM35
DIM34
DIM39
ADIM34
DIM32
DIM37
ADIM32
DIM31
DIM36
ADIM31
0x33
DIM311
ADIM36
DIM35
0x34
ADIM30
Channel 4
0x40
STAT4
CFG4
Status/Status CFG
Channel 4 Config
OC_EN4
x
SHORT_EN4
x
OPEN_EN4
x
OVFB_EN4
x
OC4
SHORT4
FLAT4
OPEN4
BAM4
OVFB4
DIMEN4
DIM40
0x41
INPH4
DIM43
DIM48
ADIM43
0x42
DIM4H
DIM4L
ADIM4
PWM Dim Value CH4
PWM Dim Value CH4
Analog Dimming CH4
SCL42
DIM412
ADIM47
SCL41
SCL40
DIM410
ADIM45
DIM44
DIM49
ADIM44
DIM42
DIM47
ADIM42
DIM41
DIM46
ADIM41
0x43
DIM411
ADIM46
DIM45
0x44
ADIM40
Analog-to-Digital Converter
0x50
0x51
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
ADCCFG
VIN
ADC Config
Scaled Input Voltage
External Voltage 1
External Voltage 2
Ch 1 FB Voltage
Ch 1 LED Current
Ch 2 FB Voltage
Ch 2 LED Current
Ch 3 FB Voltage
Ch 3 LED Current
Ch 4 FB Voltage
Ch 4 LED Current
RUN
AUTO
VIN6
CLKSEL1
VIN5
CLKSEL0
VIN4
TGT3
VIN3
TGT2
VIN2
TGT1
VIN1
TGT0
VIN0
VIN7
EXT1
EXT2
VFB1
ILED1
VFB2
ILED2
VFB3
ILED3
VFB4
ILED4
EXT17
EXT27
VFB17
ILED17
VFB27
ILED27
VFB37
ILED37
VFB47
ILED47
EXT16
EXT26
VFB16
ILED16
VFB26
ILED26
VFB36
ILED36
VFB46
ILED46
EXT15
EXT25
VFB15
ILED15
VFB25
ILED25
VFB35
ILED35
VFB45
ILED45
EXT14
EXT24
VFB14
ILED14
VFB24
ILED24
VFB34
ILED34
VFB44
ILED44
EXT13
EXT23
VFB13
ILED13
VFB23
ILED23
VFB33
ILED33
VFB43
ILED43
EXT12
EXT22
VFB12
ILED12
VFB22
ILED22
VFB32
ILED32
VFB42
ILED42
EXT11
EXT21
VFB11
ILED11
VFB21
ILED21
VFB31
ILED31
VFB41
ILED41
EXT10
EXT20
VFB10
ILED10
VFB20
ILED20
VFB30
ILED30
VFB40
ILED40
Rev. 0
25
For more information www.analog.com
LT3966
REGISTER TABLE
ADDR
NAME
DESCRIPTION
b7
b6
b5
b4
b3
b2
b1
b0
Part ID (BCD Encoded, “03 96 60”)
0xFD
0xFE
0xFF
ID0
ID1
ID2
Part ID High
Part ID Mid
Part ID Low
0
1
0
0
0
1
0
0
1
0
1
0
0
0
0
0
1
0
1
1
0
1
0
0
GLOBAL CONFIGURATION REGISTER
Default Value: 0000 0000
ADDR
NAME
DESCRIPTION
b7
WDTFLAG
b6
WDTEN
b5
b4
CLKOUT
b3
OFF3
b2
OFF2
b1
OFF1
b0
0x00
GLBCFG
Channel Config
MPHASE
OFF0
Bit Description
b[7]
WDTFLAG: Watchdog Timer Status. This bit indicates if the device has been reset by the WDT. It is cleared
by disabling the WDT.
2
b[6]
WDTEN: Watchdog Timer Enable. When set, LT3966 requires an I C start condition every 100ms to verify
2
the communication interface is good. If the WDT expires without an I C start being detected, the chip will
force a power-on-reset to the default state.
b[5]
b[4]
MPHASE: Multiphase DC/DC Converter Clocking. When MPHASE is set, the 4 DC/DC channels operate at
MCLK/2, with 90° of phase shift between each channel.
CLKOUT: SYNC Pin Direction. Default = 0, SYNC = Input. When set, the SYNC pin becomes an output and
drives the MCLK signal, for synchronizing other devices. The output frequency is always that of MLCK,
regardless of the state of MPHASE. This allows a slave LT3966 to run at equal frequency to the master
LT3966 even in multiphase mode.
b[3:0]
OFF[3:0]: OFF/ON Control for Each Channel. Channels are all on by default, and controlled by EN. Set the
OFF bit to disable a channel.
Rev. 0
26
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LT3966
REGISTER DETAILS
LED DRIVER CHANNEL REGISTERS
Each of the 4 LED driver channels is configured through its 4-register bank. The channel registers are located at address
0x10–0x13, 0x20–0x23, 0x30–0x33, and 0x40–0x43 for the 4 channels, respectively.
Default Values: 0000 0000, 0000 0000, 0000 0000, 1111 1111
OFFSET
0x00
NAME
STAT
CFG
DESCRIPTION
Status/Status CFG
Channel Config
PWM Dim Value
PWM Dim Value
Analog Dimming
b7
b6
SHORT_EN
x
b5
b4
b3
OC
b2
b1
b0
OC_EN
x
OPEN_EN OVFB_EN
SHORT
LATOFF
DIM2
OPEN
BAM
OVFB
DIMEN
DIM0
DIM5
ADIM0
0x01
x
x
INPH
DIM3
DIM8
ADIM3
0x02
DIMH
DIML
ADIM
SCL2
DIM12
ADIM7
SCL1
SCL0
DIM10
ADIM5
DIM4
DIM9
ADIM4
DIM1
DIM6
ADIM1
0x03
DIM11
ADIM6
DIM7
0x04
ADIM2
Bit Descriptions
STAT
OFFSET NAME
DESCRIPTION
b7
OC_EN
b6
b5
b4
OVFB_EN
b3
OC
b2
b1
b0
0x00
STAT
Status/Status CFG
SHORT_EN OPEN_EN
SHORT
OPEN
OVFB
b[7] OC_EN: LED Overcurrent Reporting Enable. Set this bit high to enable LED overcurrent fault reporting on the
ALERT pin. If clear, ALERT is not triggered during an LED overcurrent event.
b[6] SHORT_EN: Shorted LED Reporting Enable. Set this bit high to enable SHORTLED fault reporting on the
ALERT pin. If clear, ALERT is not triggered during a SHORTLED event.
b[5] OPEN_EN: Open LED Reporting Enable. Set this bit high to enable OPENLED fault reporting on the ALERT
pin. If clear, ALERT is not triggered during an OPENLED event.
b[4] OVFB_EN: FB Overvoltage Reporting Enable. Set this bit high to enable FB overvoltage fault reporting on the
ALERT pin. If clear, ALERT is not triggered during an OPENLED event.
b[3] OC: LED Overcurrent Status. This bit is asserted when a differential of 375mV or greater is detected at the
ISP–ISN sense amplifier. If the corresponding OC_EN bit is enabled, ALERT is asserted and the status bit is
latched until either OC or OC_EN is written to 0 by the host. If the corresponding enable bit is clear, the status
is not latched and will reflect the present state of the LED overcurrent detector.
If the channel’s LATOFF (latchoff) bit is set, an LED overcurrent fault will result in latched shutdown of the
faulted channel until either OC or LATOFF is written to 0 by the host. If the channel’s LATOFF bit is not set,
the faulted channel will enter the hiccup cycle of shutdown and attempted restart.
Rev. 0
27
For more information www.analog.com
LT3966
REGISTER TABLE
b[2] SHORT: Shorted LED Status. This bit is asserted when the corresponding channel’s FB pin is below 300mV
and the internal soft start has completed. If the corresponding SHORT_EN bit is enabled, ALERT is asserted
and the fault status is latched until either SHORT or SHORT_EN is written to 0 by the host. If the correspond-
ing enable bit is clear, the status is not latched and will reflect the present state of the Shorted LED detector.
If the channel’s LATOFF (latchoff) bit is set, a Shorted LED fault will result in latched shutdown of the faulted
channel until either SHORT or LATOFF is written to 0 by the host. If the channel’s LATOFF bit is not set, the
faulted channel will enter the hiccup cycle of shutdown and attempt to restart.
b[1] OPEN: OPENLED Status. This bit is asserted when the corresponding channel’s FB pin is above 1.15V and
ISP–ISN is less than 25mV. If the corresponding OPEN_EN bit is enabled, ALERT is asserted and the fault
status is latched until either OPEN or OPEN_EN is written to 0 by the host. If the corresponding enable bit is
clear, the status is not latched and will reflect the present state of the open LED detector.
Open LED does not generate a hiccup or latchoff event.
b[0] OVFB: FB Overvoltage Status. This bit is asserted when the corresponding channel’s FB pin is above 1.26V. If
the corresponding OVFB_EN bit is enabled, ALERT is asserted and the status bit is latched until either OVFB
or OVFB_EN is written to 0 by the host. If the corresponding enable bit is clear, the status is not latched and
will reflect the present state of the FB overvoltage detector.
FB overvoltage does not generate a hiccup or latchoff event.
LED Driver Configuration
OFFSET
NAME
DESCRIPTION
b7
b6
b5
b4
b3
b2
b1
b0
0x01
CFG
Channel Config
x
x
x
x
INPH
LATOFF
BAM
DIMEN
Bit Description
b[7:4] RFU: Reserved for Future Use. Bits read as 0, writes do nothing.
b[3]
INPH: In Phase Mode Select. When set to 1, the dimming is in phase, which means that the start of the
channel’s dimming cycle is aligned with CH1’s. When set to 0, the dimming is out of phase. In this case,
the start of CH2/CH3/CH4’s dimming cycle is behind of CH1’s by a quarter/a half/three quarters of CH2/
CH3/CH4’s dimming cycle.
b[2]
b[1]
LATOFF: Latchoff Mode. When set, OC or SHORT fault cause channel to latchoff until the fault bit is cleared
by master. When LATOFF is clear, channel will enter hiccup mode to retry.
BAM: Bit Angle Modulation Select. When set to 1, the dimming generator outputs Bit-Angle-Modulation.
When set to 0, the dimming generator outputs Pulse Width Modulation.
b[3:0] DIMEN: Dimming Generator Enable Bits. PWM dimming is the logical AND of the dimming generator output
and the CTRL/PWM comparator output. When DIMEN = 0, the PWM generator is disabled and bypassed
and dimming is controlled solely by the CTRL/PWM comparator.
Rev. 0
28
For more information www.analog.com
LT3966
REGISTER TABLE
LED Driver Dimming Generator
OFFSET
NAME
DIMH
DIML
DESCRIPTION
PWM Dim Value
PWM Dim Value
b7
b6
b5
b4
b3
b2
b1
b0
0x02
SCL2
DIM12
SCL1
DIM11
SCL0
DIM10
DIM4
DIM9
DIM3
DIM8
DIM2
DIM7
DIM1
DIM6
DIM0
DIM5
0x03
Bit Description
b[7]
SCL[2:0]: PWM Cycle Length Select. Value from 0 to 7 chooses PWM counter length from 6 to 13 bits. This
(6 + SEL)
sets the period of the PWM generator to n = 2
counts of the master clock. In the case where a DIM
value is larger than the counter length, the DIM value will be truncated below bit (6+SCL). A DIM value of
0 0000 0000 0001 would be interpreted as 0 in all cases except SCL = 111b.
b[4]
DIM[12:0]: PWM Dimming Setpoint. Specifies the on time of the PWM generator, where period is defined
by SEL. PWM duty cycle is therefore: DIM/n and ranges from 0 to (n-1)/n. To reach 100% on time, simply
disable the dimming generator using the DIMEN bit.
LED Driver Analog Dimming
Offset
Name
Description
b7
b6
b5
b4
b3
b2
b1
b0
0x04
ADIM
Analog Dimming
ADIM7
ADIM6
ADIM5
ADIM4
ADIM3
ADIM2
ADIM1
ADIM0
Bit Description
b[7]
ADIM[7:0]: Modulates the external current sense threshold set by CTRL by the value in the ADIM register.
The default value for ADIM[7:0] is 255.
ANALOG-TO-DIGITAL CONVERTER REGISTERS
ADC Configuration
Default Value: 0000 0000
ADDR
NAME
DESCRIPTION
b7
b6
b5
b4
b3
b2
b1
b0
0x50
ADCCFG
ADC Config
RUN
AUTO
CLKSEL1
CLKSEL0
TGT3
TGT2
TGT1
TGT0
Rev. 0
29
For more information www.analog.com
LT3966
REGISTER TABLE
Bit Description
ADCCFG1
b[7]
b[6]
RUN: Set to 1 to start conversion.
AUTO: Set to 0 for single conversion on a target specified by TGT[3:0]. Set to 1 for automatic continuous
conversion. In automatic continuous mode, all active inputs will be repeatedly measured in a round-robin
fashion. Any channels that are disabled (OFF) will be skipped, but channels that are enabled yet in PWM
low will cause the ADC to wait for the next PWM high. Upon PWM high, a conversion will take place
and the sequence will continue. Data is double-buffered so result registers will always contain valid data.
b[5:4] CLKSEL[1:0]: Choose ADC clock divider. For best results, set ADC bit time >1μs.
CLKSEL[1:0]
ADC CLOCK
MCLK
00
01
10
11
MCLK/2
MCLK/4
MCLK/8
b[3:0] TGT[3:0]: Only used in single conversion mode. Sets conversion target as shown in the table below.
TGT[3:0]
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
TARGET
Scaled V
TGT[3:0]
0x08
TARGET
CH3 V
IN
FB
Not Valid
External 1
External 2
0x09
CH3 I
LED
0x0A
0x0B
0x0C
0x0D
0x0E
CH4 V
FB
CH4 I
LED
CH1 V
Not valid
Not valid
Not valid
Not valid
FB
CH1 I
LED
CH2 V
FB
CH2 I
0x0F
LED
Rev. 0
30
For more information www.analog.com
LT3966
REGISTER TABLE
ADC Result Registers
Default Value: Indeterminate Until Written by ADC
ADDR
0x51
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
NAME
VIN
DESCRIPTION
VIN/48
b7
b6
b5
b4
b3
b2
b1
b0
VIN7
VIN6
VIN5
VIN4
VIN3
VIN2
VIN1
VIN0
EXT1
EXT2
VFB1
ILED1
VFB2
ILED2
VFB3
ILED3
VFB4
ILED4
External Voltage 1
External Voltage 2
Ch 1 FB Voltage
Ch 1 LED Current
Ch 2 FB Voltage
Ch 2 LED Current
Ch 3 FB Voltage
Ch 3 LED Current
Ch 4 FB Voltage
Ch 4 LED Current
EXT17
EXT27
VFB17
ILED17
VFB27
ILED27
VFB37
ILED37
VFB47
ILED47
EXT16
EXT26
VFB16
ILED16
VFB26
ILED26
VFB36
ILED36
VFB46
ILED46
EXT15
EXT25
VFB15
ILED15
VFB25
ILED25
VFB35
ILED35
VFB45
ILED45
EXT14
EXT24
VFB14
ILED14
VFB24
ILED24
VFB34
ILED34
VFB44
ILED44
EXT13
EXT23
VFB13
ILED13
VFB23
ILED23
VFB33
ILED33
VFB43
ILED43
EXT12
EXT22
VFB12
ILED12
VFB22
ILED22
VFB32
ILED32
VFB42
ILED42
EXT11
EXT21
VFB11
ILED11
VFB21
ILED21
VFB31
ILED31
VFB41
ILED41
EXT10
EXT20
VFB10
ILED10
VFB20
ILED20
VFB30
ILED30
VFB40
ILED40
Registers 0x51 and 0x53–0x5C hold the ADC results for the 11 channels. They are read-only registers.
All measurements are 5mV per LSB
0x51: V . A scaled (1/48) measurement of the chip input voltage.
IN
0x53: EXT1. External Input 1. Working range is 0V–1.275V, pin is clamped at 1.7V.
0x54: EXT2. External Input 1. Working range is 0V–1.275V, pin is clamped at 1.7V.
0x55, 0x57, 0x59, 0x5A: FB1–4. Channel feedback voltage measurement.
0x56, 0x58, 0x5A, 0x5C: VLED1–4. LED current measurement. Equal to 4× the sensed voltage on ISP–ISN.
Rev. 0
31
For more information www.analog.com
LT3966
TYPICAL APPLICATIONS
100W, Quad 750mA × 12 LED Buck Mode Driver with I2C Dimming
V
IN
44V TO 52V
ISP1
330mΩ
ISN1
ISP2
330mΩ
ISN2
ISP3
330mΩ
ISN3
ISP4
330mΩ
ISN4
4.7μF
4×
TG1
TG2
TG3
TG4
M1
M2
M3
M4
10μF
10μF
10μF
10μF
L1
68μH
L2
68μH
L3
68μH
L4
68μH
D1
D2
D3
D4
SW1
SW2
SW3
SW4
V
IN
1MΩ
33k
ISP1–4
ISN1–4
TG1–4
FB1–4
EN/UVLO
LT3966
RT
GND
EXT1
CTRL/
PWM1–4 SDA SCL ALERT
EXT2
SYNC ADR1–2 INTV
CC
3966 TA03a
97.6k
150k
2
360kHz
MULTI-
PHASE
I C
22.1k
BUS
4.7μF
INTV
CC
D1, D2, D3, D4: PMEG6020
M1, M2, M3, M4: SI7309
L1, L2, L3, L4: WURTH 744 373 49680
Multiphase
Efficiency
8192:1 Dimming
ꢀ00
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ ꢂ
ꢃ0ꢄꢅꢆꢇꢄ
ꢀ
ꢁꢂꢃꢄꢅꢆ
ꢇ0ꢀꢈꢉꢃꢀ
ꢀꢁ ꢂ
ꢃ0ꢄꢅꢆꢇꢄ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆR
ꢇꢈꢉꢂꢀꢊ
ꢀꢁ ꢂ
ꢃ0ꢄꢅꢆꢇꢄ
ꢀ
ꢁꢂꢃ
ꢄ00ꢅꢆꢇꢃꢀꢈ
ꢀꢁ ꢂ
ꢃ0ꢄꢅꢆꢇꢄ
ꢀꢁꢂꢂ ꢃꢄ0ꢀꢅ
ꢀꢁꢂꢂ ꢃꢄ0ꢀꢅ
ꢀ
ꢀ ꢁꢂ0ꢃꢄꢅ
ꢀ ꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢆ
0.ꢀꢁꢂꢃꢄꢅꢆ
ꢀ
ꢀ ꢁꢂꢃ ꢄ ꢅꢆꢇeꢈ
ꢀ
ꢀ
ꢃ ꢄ0ꢀ
ꢃ ꢈꢉꢀ
ꢁꢂ
ꢅꢆꢇ
ꢀ
ꢀ ꢁꢂꢃ
ꢉ
ꢉ
ꢄ ꢌꢍꢉ
ꢄ ꢅꢌꢉ
ꢄ 0.ꢓꢔꢕ
ꢊꢋ
ꢎꢏꢀ
0.0
0.ꢀ
ꢀ.0
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.0
ꢊ
ꢐꢑꢒ
ꢀꢁꢂ ꢃꢄRRꢁꢅꢆ ꢇꢈꢉ
ꢇꢊ ꢋ ꢌꢍ0ꢎꢈꢏꢊ ꢃꢐꢉ
ꢀꢁꢂꢂ ꢃꢄ0ꢀꢅ
Rev. 0
32
For more information www.analog.com
LT3966
TYPICAL APPLICATIONS
2.2MHz, 4 × 150mA × 12 Boost White LED Backlight with 8192:1 Dimming Ratio
V
IN
7V TO 25V
L1
6.8μH
L2
6.8μH
L3
6.8μH
L4
6.8μH
4.7μF
4×
D1
D2
D3
D4
ISP1
4.7μF 1.67Ω
ISN1
ISP2
4.7μF 1.67Ω
ISN2
ISP3
4.7μF 1.67Ω
ISN3
ISP4
4.7μF 1.67Ω
ISN4
M1
M2
M3
M4
TG1
TG2
TG3
TG4
SW1
SW2
SW3
SW4
V
IN
1MΩ
220k
ISP1–4
ISN1–4
TG1–4
FB1–4
ISP1–4
EN/UVLO
LT3966
1MΩ
GND
EXT1
CTRL/
EXT2
PWM1–4
SDA
SCL
ALERT
RT
SYNC ADR1–2 INTV
CC
21.5k
3966 TA04a
42.2k
2.2MHz
SINGLE-
PHASE
INTV
2
CC
I C
BUS
4.7μF
INTV
CC
2
I C–8192:1
D1, D2, D3, D4: PMEG6020
M1, M2, M3, M4: SI2309
PWM DIMMING
L1, L2, L3, L4: WURTH 744 778 5006
Efficiency
8192:1 Dimming
ꢀ00
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ
ꢀꢁꢂꢃꢄꢅꢆR
ꢇ00ꢈꢉꢊꢂꢀꢋ
ꢀ
ꢁꢂꢃ
ꢄ00ꢅꢆꢇꢃꢀꢈ
ꢀ
ꢃ ꢄꢅꢀ
ꢁꢂ
ꢁꢂ
ꢀ
ꢃ ꢄꢅꢀ
ꢀꢁꢂꢂ ꢃꢄ0ꢅꢆ
ꢀ
ꢀ ꢁ.ꢁꢂꢃꢄ
ꢀ ꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁ0ꢂꢃꢄꢅꢆꢇ
ꢀ
ꢀ ꢁꢂꢃ ꢄ ꢅ00ꢆꢇeꢈ
ꢀ
ꢀ ꢁꢁꢂ
ꢉ
ꢉ
ꢄ ꢌꢍꢉ
ꢄ ꢐꢐꢉ
ꢊꢋ
ꢎꢏꢀ
0
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀꢁꢂ ꢃꢄRRꢁꢅꢆ ꢇꢈꢉꢊ
ꢇꢋꢈꢉ ꢌ ꢍꢎ0ꢈꢉꢏꢋ ꢃꢐꢊ
ꢀꢁꢂꢃ ꢄꢅ0ꢆꢇ
Rev. 0
33
For more information www.analog.com
LT3966
TYPICAL APPLICATIONS
5V to 40V Buck-Boost Mode Driver for 4 Series 330mA LEDs
V
= 5V
IN
TO 40V
4.7μF
4×
L1
47μH
L2
47μH
L3
47μH
L4
47μH
M1
M2
M3
M4
TG1
ISN1
TG2
TG3
TG4
ISN2
ISN3
ISN4
750mΩ
D1
750mΩ
D2
750mΩ
D3
750mΩ
D4
ISP1
ISP2
ISP3
ISP4
1M
1M
1M
1M
4.7μF
2×
4.7μF
2×
4.7μF
2×
4.7μF
2×
FB1
FB2
FB3
FB4
21.5k
21.5k
21.5k
21.5k
SW1
SW2
SW3
SW4
V
IN
ISP1–4
ISN1–4
TG1–4
FB1–4
EN/UVLO
1MΩ
LT3966
GND
EXT1
EXT2
CTRL/
PWM1–4
SDA
SCL
ALERT
RT
SYNC ADR1–2 INTV
CC
3966 TA05a
EXTERNAL
POTENTIOMETER
MEASUREMENT
100k
1MHz
SINGLE-
PHASE
2
I C
4.7μF
INTV
BUS
CC
D1, D2, D3, D4: PMEG6020
M1, M2, M3, M4: SI2309
L1, L2, L3, L4: WURTH 744 373 49470
8192:1 Dimming
Efficiency
Hiccup Mode
ꢀ00
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢀ
ꢀ0
ꢀ
ꢁꢂꢃꢄꢅꢆ
ꢀ
ꢀꢁꢂꢃꢄꢅ
ꢇ0ꢀꢈꢉꢃꢀ
ꢀ0ꢁꢂꢃꢄꢁ
ꢀꢁꢂRꢃ
ꢀꢁꢂꢃꢄꢁ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆR
0.ꢇꢈꢉꢂꢀꢊ
ꢀꢁꢂRꢃꢄꢅ ꢂꢆꢃꢇꢆꢃ
ꢀꢁꢂꢂꢃꢄꢅ
ꢀ ꢁꢂꢃ ꢄ ꢅꢆꢇeꢈ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅ
ꢀ
ꢁꢂꢃ
ꢀ
ꢃ ꢄꢅ ꢆ ꢀ
ꢃꢄꢅ ꢆ ꢁ ꢃ 0.ꢍꢍꢎ
ꢊꢋꢌ
0.ꢄꢅꢆꢃꢀꢇ
ꢁꢂ
ꢇꢈꢉ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀꢁꢂꢂ ꢃꢄ0ꢅe
ꢀꢁ
ꢀꢁ
ꢀꢁꢂꢂ ꢃꢄ0ꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀ
ꢀ ꢁꢂꢃ
ꢀ.0ꢁꢂꢃꢄꢅꢆ
ꢀ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁꢂ
ꢀ ꢁꢂꢃ
ꢀ 0.ꢁꢁꢂ
ꢀ
ꢀꢁꢂ
0
0.ꢀ 0.ꢀ 0.ꢀ 0.ꢀ ꢀ.0 ꢀ.ꢁ ꢀ.ꢁ
ꢀꢁꢂ ꢃꢄRRꢁꢅꢆ ꢇꢈꢉ
ꢇꢊꢋꢈ ꢌ ꢍꢍ0ꢋꢈꢎꢊ ꢃꢏꢉ
ꢀꢁꢂꢂ ꢃꢄ0ꢅꢆ
Rev. 0
34
For more information www.analog.com
LT3966
PACKAGE DESCRIPTION
UJ Package
40-Lead Plastic QFN (6mm × 6mm)
ꢂReꢫeꢬeꢭꢮe ꢕꢋꢑ ꢆꢎꢏ ꢯ 0ꢢꢘ0ꢰꢘꢁꢧꢙꢰ Rev ꢪꢈ
0.ꢧ0 0.0ꢢ
ꢀ.ꢢ0 0.0ꢢ
ꢢ.ꢁ0 0.0ꢢ
ꢃ.ꢃꢙ 0.0ꢢ
ꢃ.ꢢ0 0.0ꢢ
ꢂꢃ ꢄꢅꢆꢇꢄꢈ
ꢃ.ꢃꢙ 0.0ꢢ
ꢒꢍꢑꢓꢍꢏꢇ ꢊꢔꢋꢕꢅꢉꢇ
0.ꢙꢢ 0.0ꢢ
0.ꢢ0 ꢝꢄꢑ
Rꢇꢑꢊꢛꢛꢇꢉꢆꢇꢆ ꢄꢊꢕꢆꢇR ꢒꢍꢆ ꢒꢅꢋꢑꢞ ꢍꢉꢆ ꢆꢅꢛꢇꢉꢄꢅꢊꢉꢄ
ꢍꢒꢒꢕꢡ ꢄꢊꢕꢆꢇR ꢛꢍꢄꢓ ꢋꢊ ꢍRꢇꢍꢄ ꢋꢞꢍꢋ ꢍRꢇ ꢉꢊꢋ ꢄꢊꢕꢆꢇRꢇꢆ
0.ꢧꢢ 0.0ꢢ
R ꢣ 0.ꢁꢁꢢ
ꢋꢡꢒ
ꢀ.00 0.ꢁ0
ꢂꢃ ꢄꢅꢆꢇꢄꢈ
R ꢣ 0.ꢁ0
ꢋꢡꢒ
ꢚꢥ ꢃ0
0.ꢃ0 0.ꢁ0
ꢒꢅꢉ ꢁ ꢋꢊꢒ ꢛꢍRꢓ
ꢂꢄꢇꢇ ꢉꢊꢋꢇ ꢀꢈ
ꢁ
ꢙ
ꢒꢅꢉ ꢁ ꢉꢊꢋꢑꢞ
R ꢣ 0.ꢃꢢ ꢊR
0.ꢚꢢ × ꢃꢢꢤ
ꢑꢞꢍꢛꢗꢇR
ꢃ.ꢃꢙ 0.ꢁ0
ꢃ.ꢢ0 Rꢇꢗ
ꢂꢃꢘꢄꢅꢆꢇꢄꢈ
ꢃ.ꢃꢙ 0.ꢁ0
ꢂꢔꢐꢃ0ꢈ ꢩꢗꢉ Rꢇꢖ ꢪ 0ꢃ0ꢀ
0.ꢙ00 Rꢇꢗ
0.ꢙꢢ 0.0ꢢ
0.ꢢ0 ꢝꢄꢑ
0.00 ꢨ 0.0ꢢ
ꢉꢊꢋꢇꢌ
ꢝꢊꢋꢋꢊꢛ ꢖꢅꢇꢎꢦꢇꢜꢒꢊꢄꢇꢆ ꢒꢍꢆ
ꢁ. ꢆRꢍꢎꢅꢉꢏ ꢅꢄ ꢍ ꢐꢇꢆꢇꢑ ꢒꢍꢑꢓꢍꢏꢇ ꢊꢔꢋꢕꢅꢉꢇ ꢖꢍRꢅꢍꢋꢅꢊꢉ ꢊꢗ ꢂꢎꢐꢐꢆꢘꢙꢈ
ꢙ. ꢆRꢍꢎꢅꢉꢏ ꢉꢊꢋ ꢋꢊ ꢄꢑꢍꢕꢇ
ꢚ. ꢍꢕꢕ ꢆꢅꢛꢇꢉꢄꢅꢊꢉꢄ ꢍRꢇ ꢅꢉ ꢛꢅꢕꢕꢅꢛꢇꢋꢇRꢄ
ꢃ. ꢆꢅꢛꢇꢉꢄꢅꢊꢉꢄ ꢊꢗ ꢇꢜꢒꢊꢄꢇꢆ ꢒꢍꢆ ꢊꢉ ꢝꢊꢋꢋꢊꢛ ꢊꢗ ꢒꢍꢑꢓꢍꢏꢇ ꢆꢊ ꢉꢊꢋ ꢅꢉꢑꢕꢔꢆꢇ
ꢛꢊꢕꢆ ꢗꢕꢍꢄꢞ. ꢛꢊꢕꢆ ꢗꢕꢍꢄꢞꢟ ꢅꢗ ꢒRꢇꢄꢇꢉꢋꢟ ꢄꢞꢍꢕꢕ ꢉꢊꢋ ꢇꢜꢑꢇꢇꢆ 0.ꢙ0ꢠꢠ ꢊꢉ ꢍꢉꢡ ꢄꢅꢆꢇꢟ ꢅꢗ ꢒRꢇꢄꢇꢉꢋ
ꢢ. ꢇꢜꢒꢊꢄꢇꢆ ꢒꢍꢆ ꢄꢞꢍꢕꢕ ꢝꢇ ꢄꢊꢕꢆꢇR ꢒꢕꢍꢋꢇꢆ
ꢀ. ꢄꢞꢍꢆꢇꢆ ꢍRꢇꢍ ꢅꢄ ꢊꢉꢕꢡ ꢍ RꢇꢗꢇRꢇꢉꢑꢇ ꢗꢊR ꢒꢅꢉ ꢁ ꢕꢊꢑꢍꢋꢅꢊꢉ ꢊꢉ ꢋꢞꢇ ꢋꢊꢒ ꢍꢉꢆ ꢝꢊꢋꢋꢊꢛ ꢊꢗ ꢒꢍꢑꢓꢍꢏꢇ
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
35
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LT3966
TYPICAL APPLICATIONS
30W Boost RGBW Digital Color Blending Circuit Featuring BAM Modulation
V
= 7V
IN
TO 17V
L1
L2
6.8μH
L3
6.8μH
L4
6.8μH
3.3μF
4×
6.8μH
D1
D2
D3
D4
ISP1
1Ω
ISP2
1Ω
ISP3
1Ω
ISP4
1Ω
ISN4
TG4
4.7μF
4.7μF
4.7μF
M4
4.7μF
ISN1
ISN2
ISN3
TG1
TG2
TG3
M1
M2
M3
NOTE: CURRENTS
SET USING ADIM CODE.
RED
250mA
GREEN
156mA
BLUE
180mA
WHITE
200mA
SW1
SW2
SW3
SW4
V
IN
1MΩ
221k
ISP1–4
ISN1–4
TG1–4
FB1–4
ISP1–4
EN/UVLO
LT3966
1MΩ
GND
EXT1
EXT2
CTRL/
SDA
SCL
ALERT
RT
SYNC ADR1–2 INTV
CC
PWM1–4
34k
3966 TA02a
69.8k
1.4MHz
SINGLE-
PHASE
D1, D2, D3, D4: PMEG6020
M1, M2, M3, M4: SI2309
L1, L2, L3, L4: WURTH 744 778 5006
2
I C
BUS
4.7μF
INTV
CC
Efficiency
ꢀ00
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
BAM Modulation
ꢀ
ꢀꢁꢂꢃꢄꢅꢆR
ꢇ00ꢈꢉꢊꢂꢀꢋ
ꢀ
ꢁꢂꢃ
ꢀ
ꢀ ꢁ.ꢂꢃꢄꢅ
ꢀꢁ
ꢀꢁ
ꢄ00ꢅꢆꢇꢃꢀꢈ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁꢂꢂ ꢃꢄ0ꢅꢆ
ꢀ
ꢀ ꢁ0ꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢆ
0
0.ꢀ
0.ꢀ
0.ꢀ
0.ꢀ
ꢀ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂ ꢃꢄRRꢁꢅꢆ ꢇꢈꢉ
ꢀꢁ ꢂ ꢃꢄ0ꢅꢆꢇꢁ ꢈꢉꢊ
ꢀ
ꢀ ꢁ0ꢂ
ꢀꢁꢂ
ꢀꢁꢂꢂ ꢃꢄ0ꢅꢆ
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
V : 4V to 40V, V
2
LT3964
LT3492
LT3476
Dual 1.5A/40V Sync Buck LED Driver with I C
= 40V, 3000:1 True Color PWM Dimming,
OUT(MAX)
IN
ISD < 1μA, 5mm × 6mm QFN-36 Package
60V, Triple Output 750mA, 1MHz High Current LED Driver with
3000:1 Dimming with PMOS Disconnect FET Drivers
V : 3V to 30V, V = 60V, 3000:1 True Color PWM Dimming,
IN
OUT(MAX)
ISD < 1μA, TSSOP-28 and 4mm × 5mm QFN-28 Packages
Quad Output 1.5A, 2MHz High Current LED Driver with 1,000:1 V : 2.8V to 16V, V
True Color PWM Dimming
= 36V, ISD< 10μA, 5mm × 7mm
IN
OUT(MAX)
QFN Package
Rev. 0
10/20
www.analog.com
ANALOG DEVICES, INC. 2020
36
相关型号：
LT3970EDDB#PBF
LT3970 Series - 40V, 350mA Step-Down Regulator with 2.5µA Quiescent Current and Integrated Diodes; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C
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LT3970EDDB#TRMPBF
LT3970 Series - 40V, 350mA Step-Down Regulator with 2.5µA Quiescent Current and Integrated Diodes; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C
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LT3970EDDB#TRPBF
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LT3970EDDB-3.3#PBF
LT3970 Series - 40V, 350mA Step-Down Regulator with 2.5µA Quiescent Current and Integrated Diodes; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C
Linear
LT3970EDDB-3.3#TRMPBF
LT3970 Series - 40V, 350mA Step-Down Regulator with 2.5µA Quiescent Current and Integrated Diodes; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C
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