LT8391 [ADI]
60VIN, 100VOUT Synchronous 4-Switch Buck-Boost LED Driver Controller with Low EMI;
| 型号： | LT8391 |
| 厂家： | 
ADI |
| 描述： | 60VIN, 100VOUT Synchronous 4-Switch Buck-Boost LED Driver Controller with Low EMI |
| 文件： | 总32页 (文件大小：2696K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT8393
60V , 100V Synchronous
IN
OUT
4-Switch Buck-Boost LED Driver
Controller with Low EMI
FEATURES
DESCRIPTION
The LT®8393 is a synchronous 4-switch buck-boost LED
n
4-Switch Single Inductor Architecture Allows V
IN
controller that regulates LED current from input volt-
age above, below, or equal to the output voltage. The
proprietary peak-buck peak-boost current mode control
scheme allows adjustable and synchronizable 350kHz to
2MHz fixed frequency operation, or internal 25% triangle
spread spectrum operation for low EMI. With 4V to 60V
input, 0V to 100V output, and seamless low noise transi-
tions between operation regions, the LT8393 is ideal for
LEDdriverandbatterychargerapplicationsinautomotive,
industrial, and battery-powered systems.
Above, Below or Equal to V
Up to 95% Efficiency
OUT
n
n
n
n
n
n
n
n
n
n
n
n
Proprietary Peak-Buck Peak-Boost Current Mode
Wide V Range: 4V to 60V
IN
Wide V
Range: 0V to 100V
OUT
4% LED Current Accuracy
2000:1 External and 128:1 Internal PWM Dimming
10V High Side PMOS PWM Switch Driver
No Top MOSFET Refresh Noise in Buck or Boost
Adjustable and Synchronizable: 350kHz to 2MHz
Flicker-Free Spread Spectrum for Low EMI
Open and Short LED Protection with Fault Reporting
AEC-Q100 Qualification in Progress
The LT8393 provides both internal (up to 128:1) and
external (up to 2000:1) LED current PWM dimming with
10V of high side PMOS gate drive. The CTRL pin provides
flexible 20:1 analog dimming with 4% LED current ac-
curacy at 100mV full scale. Fault protection is provided to
detect an open or short LED condition, during which the
LT8393 retries, latches off, or keeps running.
APPLICATIONS
n
Automotive Head Lamps/Running Lamps
High Voltage LED Lighting
n
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
93% Efficient 24W (80V, 300mA) 350kHz Buck-Boost LED Driver
ꢀꢀꢁꢂ
10mΩ
ꢀ
ꢁꢂ
ꢃꢀ ꢄꢅ ꢆꢇꢀ
ꢀ.ꢁꢂꢃ
ꢄꢅꢆ
ꢇꢈ
ꢀ.ꢁꢂꢃ
ꢀ.ꢁꢂꢃ
ꢀꢁꢂ.ꢃꢄꢅ
ꢆꢇꢇꢈ
ꢀꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃ
Efficiency vs VIN
ꢀꢁꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂꢃ
ꢄꢄ
ꢀꢁꢂꢃ
ꢄꢄ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁꢂꢃꢄꢃ
ꢀꢁꢂ
ꢀ
ꢀꢁꢁꢂ
ꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁ
ꢀꢀꢁꢂ ꢃꢁꢁ
ꢀꢁ.ꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢀꢅRꢆ
ꢀꢁ
ꢀꢀꢁꢂ ꢃꢄ
ꢀꢁꢂꢃ
ꢄꢄ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀꢁꢂ
ꢀ.ꢁꢂꢃ
ꢀꢁꢁꢂ
330mΩ
FAULT
AꢀAꢁꢂꢃ ꢄꢅꢆ
FAULT
ꢀꢁꢂ
ꢀ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ
ꢀꢁRꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄAꢈꢉ ꢊꢅꢋ
ꢀꢁꢁꢂ
ꢀꢁꢂꢁ ꢃAꢄꢅꢆ
ꢀ
Rꢀꢁ
ꢀ
ꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂ ꢃꢄꢂ
ꢀ.ꢁꢂꢃꢄ
Rꢀ
ꢀꢁꢁꢂ
ꢀꢀ
ꢀ
ꢀ
Rꢀ
ꢀꢁ ꢂꢃ ꢄꢅꢁ
ꢆꢅꢅꢇA
ꢈꢉꢊꢋ
ꢀꢁꢂ
ꢀꢁꢁꢂ
ꢃꢄꢅꢂꢆꢇ
ꢀꢁꢂ
ꢀ.ꢁꢂ
ꢀꢁꢂꢃ
0.1μF
ꢀꢁꢂ
ꢃꢄꢅꢆꢇ
ꢀꢁꢂꢁ ꢃAꢄꢅꢆ
Rev. A
1
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LT8393
ABSOLUTE MAXIMUM RATINGS
(Note 1)
INTV , (BST1-SW1), (BST2-SW2).............................6V
CC
V , EN/UVLO............................................................60V
IN
OUT
(BST1-LSP), (BST1-LSN) ............................................6V
FB, PWM, SYNC/SPRD, CTRL, FAULT .........................6V
Operating Junction Temperature Range (Notes 2, 3)
LT8393E ............................................ –40°C to 125°C
LT8393J............................................. –40°C to 150°C
LT8393H............................................ –40°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
V
, ISP, ISN .........................................................100V
(ISP-ISN) .........................................................–1V to 1V
BST1.........................................................................66V
BST2.......................................................................106V
SW1, LSP, LSN.............................................. –6V to 60V
SW2........................................................... –6V to 100V
PIN CONFIGURATION
ꢊꢋꢌ ꢍꢎꢏꢐ
ꢃꢄꢅ ꢆꢇꢈꢉ
ꢀ
ꢁ
ꢤꢔꢁ
ꢤꢘꢊꢁ
ꢘꢐꢁ
ꢊꢔꢁ
ꢁꢇ
ꢁꢆ
ꢁꢅ
ꢁꢄ
ꢁꢃ
ꢁꢂ
ꢁꢁ
ꢁꢀ
ꢁꢉ
ꢀꢈ
ꢀꢇ
ꢀꢆ
ꢀꢅ
ꢀꢄ
ꢤꢔꢀ
ꢤꢘꢊꢀ
ꢘꢐꢀ
ꢊꢔꢀ
ꢂ
ꢑꢒ ꢑꢥ ꢑꢦ ꢑꢘ ꢑꢖ ꢑꢠ
ꢃ
ꢃꢐꢁ
ꢔꢚꢅ
ꢔꢚꢝ
ꢁ
ꢑ
ꢠ
ꢖ
ꢘ
ꢦ
ꢥ
ꢒ
ꢑꢑ
ꢑꢁ
ꢑꢂ
ꢃꢐꢑ
ꢄ
ꢍ
ꢋꢣꢊ
ꢖꢘꢌ
ꢆ
ꢄꢊꢃ
ꢅ
ꢌꢐꢢꢊꢔ
ꢘꢥꢠꢒꢜꢘꢌRꢗ
Rꢊ
ꢖꢘꢠ
ꢅꢉꢍꢃꢐ
ꢆ
ꢆ
ꢑꢀ
ꢐꢝꢌ
ꢁꢀ ꢚꢧꢝꢎꢢꢚꢅRꢌ
ꢍ
ꢎꢠ
ꢇꢝ
ꢁꢈ
ꢔꢠꢗ
ꢇꢝꢃꢆ
ꢁꢒ
ꢁꢥ
ꢁꢦ
ꢁꢘ
Rꢃ
ꢇ
ꢎꢠꢊꢍ
ꢎꢎ
ꢒꢒ
ꢈꢝꢢꢊꢆꢔꢄ
ꢆ
ꢎ
ꢈ
ꢍ
ꢒ
ꢏꢠꢜꢣꢍꢖꢋ
Rꢅ
ꢋꢛ
ꢀꢉ
ꢀꢀ
ꢀꢁ
ꢀꢂ
ꢀꢃ
ꢑꢤ
Rꢌ
ꢅꢉꢍ
ꢚꢚ
ꢘꢘ
ꢌꢐꢢ
ꢀ
ꢁꢂ ꢁꢁ ꢁꢑ ꢁꢠ ꢁꢖ
ꢊꢋꢌꢍ ꢅAꢎꢏAꢐꢈ
FAULT
ꢔꢠꢗ
ꢎꢘꢠ
ꢍ
Rꢏꢑ
ꢒꢊRꢖ
ꢎꢘꢌ
ꢑꢒꢓꢔꢈAꢌ ꢕꢖꢗꢗ × ꢘꢗꢗꢙ ꢅꢔAꢚꢃꢇꢎ ꢚꢇꢌꢈ ꢉꢈꢃꢃAꢛꢔꢈ ꢜꢋꢝ
ꢟ ꢠꢖꢡꢎꢢꢉꢣ θ ꢟ ꢠ.ꢖꢡꢎꢢꢉ
ꢑꢏ ꢌAꢒꢓAꢔꢏ
θ
ꢞA
ꢞꢎ
ꢁꢇꢕꢖꢏAꢗ ꢌꢖAꢘꢊꢎꢒ ꢊꢘꢘꢋꢌ
ꢈꢤꢅꢄꢚꢈꢌ ꢅAꢌ ꢕꢅꢇꢝ ꢑꢀꢙ ꢇꢚ ꢐꢝꢌꢣ ꢍꢊꢚꢃ ꢛꢈ ꢚꢄꢔꢌꢈRꢈꢌ ꢃꢄ ꢅꢎꢛ
θ
ꢙA
ꢚ ꢂꢉꢛꢒꢜꢐꢝ θ ꢚ ꢄꢛꢒꢜꢐ
ꢙꢒ
ꢏꢞꢌꢋꢘꢏꢗ ꢌAꢗ ꢟꢌꢎꢠ ꢁꢈꢡ ꢎꢘ ꢔꢠꢗꢝ ꢢꢣꢘꢊ ꢤꢏ ꢘꢋꢖꢗꢏRꢏꢗ ꢊꢋ ꢌꢒꢤ
Rev. A
2
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LT8393
ORDER INFORMATION
LEAD FREE FINISH
LT8393EFE#PBF
LT8393JFE#PBF
LT8393HFE#PBF
LT8393EUFDM#PBF
TAPE AND REEL
PART MARKING*
LT8393FE
LT8393FE
LT8393FE
8393
PACKAGE DESCRIPTION
28-Lead Plastic TSSOP
28-Lead Plastic TSSOP
28-Lead Plastic TSSOP
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 150°C
–40°C to 150°C
–40°C to 125°C
LT8393EFE#TRPBF
LT8393JFE#TRPBF
LT8393HFE#TRPBF
LT8393EUFDM#TRPBF
28-Lead (4mm x 5mm) Plastic Side
Wettable QFN
LT8393JUFDM#PBF
LT8393HUFDM#PBF
LT8393JUFDM#TRPBF
LT8393HUFDM#TRPBF
8393
8393
28-Lead (4mm x 5mm) Plastic Side
Wettable QFN
–40°C to 150°C
–40°C to 150°C
28-Lead (4mm x 5mm) Plastic Side
Wettable QFN
AUTOMOTIVE PRODUCTS**
LT8393JFE#WPBF
LT8393JFE#WTRPBF
LT8393HFE#WTRPBF
LT8393FE
LT8393FE
28-Lead Plastic TSSOP
28-Lead Plastic TSSOP
–40°C to 150°C
–40°C to 150°C
–40°C to 150°C
LT8393HFE#WPBF
LT8393JUFDM#WPBF
LT8393JUFDM#WTRPBF 8393
28-Lead (4mm x 5mm) Plastic Side
Wettable QFN
LT8393HUFDM#WPBF
LT8393HUFDM#WTRPBF 8393
28-Lead (4mm x 5mm) Plastic Side
Wettable QFN
–40°C to 150°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by aLabel on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
these models.
Rev. A
3
For more information www.analog.com
LT8393
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2). VIN = 12V, VEN/UVLO = 1.5V unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
60
UNITS
l
V
IN
V
IN
Operating Voltage Range
Quiescent Current
4
V
V
V
= 0.3V
= 1.1V
1
270
2.4
2
µA
µA
mA
EN/UVLO
EN/UVLO
Not Switching
4
l
V
V
Voltage Range
0
100
V
OUT
Quiescent Current
V
= 0.3V, V
= 12V
0.1
50
0.5
70
µA
µA
OUT
EN/UVLO
OUT
Not Switching, V
= 12V
30
OUT
Linear Regulators
INTV Regulation Voltage
I
= 20mA
= 4.5V
4.85
110
5.0
150
3.54
0.24
2.00
2.5
5.15
190
V
mA
V
CC
INTVCC
INTV Current Limit
V
INTVCC
CC
INTV Undervoltage Lockout Threshold
Falling
3.44
3.64
CC
INTV Undervoltage Lockout Hysteresis
V
CC
l
V
REF
V
REF
V
REF
V
REF
Regulation Voltage
I
= 100µA
= 1.8V
1.96
2
2.04
3.2
V
VREF
Current Limit
V
mA
V
REF
Undervoltage Lockout Threshold
Undervoltage Lockout Hysteresis
Falling
1.78
1.84
50
1.90
mV
Control Inputs/Outputs
EN/UVLO Shutdown Threshold
l
l
0.3
0.6
1.220
13
1.0
V
V
EN/UVLO Enable Threshold
EN/UVLO Enable Hysteresis
EN/UVLO Hysteresis Current
Falling
1.196
1.244
mV
V
V
= 1.1V
= 1.3V
2.1
–0.1
2.5
0
2.9
0.1
µA
µA
EN/UVLO
EN/UVLO
CTRL Input Bias Current
CTRL Dim-Off Threshold
CTRL Dim-Off Hysteresis
V
= 0.75V, Current Out of Pin
0
20
200
28
50
nA
mV
mV
CTRL
l
l
Falling
180
220
PWM Dimming
External PWM Dimming Threshold
External PWM Dimming Hysteresis
Internal PWM Dimming Duty Cycle
Rising, R = 30k
1.3
1.4
1.5
V
P
R = 30k
220
mV
P
V
V
V
= 1V, R ≥ 51k
3
53
%
%
%
PWM
PWM
PWM
P
= 1.5V, R ≥ 51k
47
97
P
= 2V, R ≥ 51k
P
Switching Frequency to Internal PWM Dimming
Frequency Ratio
R = 51k
1024
2048
4096
8192
16384
P
R = 82k
P
R = 130k
P
R = 200k
P
R = 300k
P
Minimum V
for PWMTG to be On
PWM Dimming On
2.4
10
0
4
V
V
OUT
PWMTG On Voltage V
PWMTG Off Voltage V
V
V
C
C
= 12V
= 12V
8.5
11.5
0.1
(VOUT-PWMTG)
(VOUT-PWMTG)
OUT
OUT
–0.1
V
PWM to PWMTG Turn On Propagation Delay
PWM to PWMTG Turn Off Propagation Delay
= 3.3nF to V , 50% to 50%
180
50
ns
ns
PWMTG
PWMTG
OUT
= 3.3nF to V , 50% to 50%
OUT
PWMTG Turn On Fall Time
PWMTG Turn Off Rise Time
C
C
= 3.3nF to V , 10% to 90%
180
70
ns
ns
PWMTG
PWMTG
OUT
= 3.3nF to V , 90% to 10%
OUT
Rev. A
4
For more information www.analog.com
LT8393
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2). VIN = 12V, VEN/UVLO = 1.5V unless otherwise noted.
SYMBOL PARAMETER
Error Amplifier
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
Full Scale LED Current Regulation V
V
V
= 2V, V = 12V
96
96
100
100
104
104
mV
mV
(ISP-ISN)
CTRL
CTRL
ISP
= 2V, V = 0V
ISP
l
l
1/2 LED Current Regulation V
V
V
= 0.75V, V = 12V
47
47
50
50
53
53
mV
mV
(ISP-ISN)
CTRL
CTRL
ISP
= 0.75V, V = 0V
ISP
l
l
1/20th LED Current Regulation V
V
V
= 0.30V, V = 12V
3
3
5
5
7
7
mV
mV
(ISP-ISN)
CTRL
CTRL
ISP
= 0.30V, V = 0V
ISP
l
ISP/ISN Input Common Mode Range
ISP Input Bias Current
0
100
V
V
V
V
= 5V, V = V = 12V
23
–10
0
µA
µA
µA
PWM
PWM
ISP
ISN
= 5V, V = V = 0V
ISP
ISN
= 0V, V = V = 12V or 0V
EN/UVLO
ISP
ISN
ISN Input Bias Current
V
V
V
= 5V, V = V = 12V
23
–10
0
µA
µA
µA
PWM
PWM
ISP
ISN
= 5V, V = V = 0V
ISP
ISN
= 0V, V = V = 12V or 0V
EN/UVLO
ISP
ISN
LED Current Regulation Amplifier g
FB Regulation Voltage
1700
1.00
615
20
µS
V
m
l
V = 1.2V
0.98
–10
1.02
40
C
FB Voltage Regulation Amplifier g
FB Input Bias Current
µS
nA
MΩ
nA
m
FB in Regulation, Current Out of Pin
V Output Impedance
C
15
V Standby Leakage Current
C
V = 1.2V, PWM Dimming Off
C
0
10
Current Comparator
Maximum Current Sense Threshold V
l
l
Buck, V = 0.8V
34
38
48
48
62
58
mV
mV
(LSP-LSN)
FB
Boost, V = 0.8V
FB
Fault
FB Overvoltage Threshold (V
FB Overvoltage Hysteresis
)
Rising
1.03
15
1.05
25
1.07
35
V
mV
V
FB
FB Open LED Threshold (V
FB Open LED Hysteresis
)
Rising, V
= 0V
0.93
35
0.95
50
0.97
65
FB
(ISP-ISN)
V
= 0V
mV
V
(ISP-ISN)
FB Short LED Threshold (V
FB Short LED Hysteresis
)
Falling
Hysteresis
= 12V
0.24
35
0.25
50
0.26
65
FB
mV
mV
mV
mV
Ω
ISP/ISN Over Current Threshold V
V
ISP
750
10
(ISP-ISN)
ISP/ISN Open LED Threshold V
ISP/ISN Open LED Hysteresis
FAULT Pull-Down Resistance
SS Hard Pull-Down Resistance
SS Pull-Up Current
Falling, V = 1.0V
7
3
13
7
(ISP-ISN)
FB
V
FB
= 1.0V
5
100
100
12.5
1.25
1.7
0.2
200
200
15
V
V
V
= 1.1V
Ω
EN/UVLO
= 0.8V, V = 0V
10
1
µA
µA
V
FB
FB
SS
SS Pull-Down Current
= 1.0V, V = 2V
1.5
SS
SS Fault Latch-Off Threshold
SS Fault Reset Threshold
Falling
V
Rev. A
5
For more information www.analog.com
LT8393
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2). VIN = 12V, VEN/UVLO = 1.5V unless otherwise noted.
SYMBOL PARAMETER
Oscillator
CONDITIONS
MIN
TYP
MAX
UNITS
l
Switching Frequency
V
V
= 0V, R = 422k
330
1900
350
2000
370
2100
kHz
kHz
SYNC/SPRD
SYNC/SPRD
T
= 0V, R = 51.1k
T
SYNC Frequency
350
0.4
2000
1.5
kHz
V
SYNC/SPRD Threshold Voltage
Region Transition
Buck-Boost to Boost (V /V
)
)
0.72
0.82
1.22
1.30
0.96
1.00
0.75
0.85
1.25
1.33
0.98
1.02
0.78
0.88
1.28
1.36
1.00
1.04
IN OUT
Boost to Buck-Boost (V /V
IN OUT
Buck to Buck-Boost (V /V
)
)
IN OUT
Buck-Boost to Buck (V /V
IN OUT
Peak-Buck to Peak-Boost (V /V
)
)
IN OUT
Peak-Boost to Peak-Buck (V /V
IN OUT
NMOS Drivers
TG1, TG2 Gate Driver On-Resistance
Gate Pull-Up
V = 5V
(BST-SW)
2.6
1.4
Ω
Ω
Gate Pull-Down
BG1, BG2 Gate Driver On-Resistance
Gate Pull-Up
V
= 5V
INTVCC
3.2
1.2
Ω
Ω
Gate Pull-Down
TG Off to BG On Delay
BG Off to TG On Delay
C = 3.3nF
60
60
ns
ns
L
C = 3.3nF
L
Rev. A
6
For more information www.analog.com
LT8393
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2). VIN = 12V, VEN/UVLO = 1.5V unless otherwise noted.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT8393E is guaranteed to meet performance specifications
from 0°C to 125°C operating junction temperature. Specifications over
the –40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LT8393J and LT8393H are guaranteed over the –40°C to 150°C
operating junction temperature range. High junction temperatures degrade
operating lifetimes. Operating lifetime is derated at junction temperatures
greater than 125°C.
Note 3: The LT8393 includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 150°C when overtemperature protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability.
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs LED Current
(Buck Region)
Efficiency vs LED Current
(Buck-Boost Region)
Efficiency vs LED Current
(Boost Region)
ꢖꢉꢉ
ꢏꢉ
ꢖꢉꢉ
ꢖꢉꢉ
ꢏꢉ
ꢏꢉ
ꢐꢉ
ꢐꢉ
ꢐꢉ
ꢑꢉ
ꢒꢉ
ꢑꢉ
ꢒꢉ
ꢑꢉ
ꢒꢉ
ꢓꢉ
ꢔꢉ
ꢓꢉ
ꢔꢉ
ꢓꢉ
ꢔꢉ
ꢕꢉ
ꢊꢉ
ꢕꢉ
ꢊꢉ
ꢕꢉ
ꢊꢉ
ꢘ
ꢙ ꢐꢘꢚ ꢘ
ꢙ ꢖꢒꢘꢚ ꢛ ꢙ ꢕꢓꢉꢞꢟꢠ
ꢘ
ꢙ ꢕꢊꢘꢚ ꢘ
ꢙ ꢖꢒꢘꢚ ꢛ ꢙ ꢕꢓꢉꢞꢟꢠ
ꢜꢝ
ꢘ
ꢙ ꢖꢒꢘꢚ ꢘ
ꢙ ꢖꢒꢘꢚ ꢛ ꢙ ꢕꢓꢉꢞꢟꢠ
ꢜꢝ
ꢌꢅ
ꢀꢁꢂ ꢜꢝ
ꢌꢅ
ꢀꢁꢂ
ꢌꢅ
ꢀꢁꢂ
ꢉ
ꢉ.ꢓ
ꢖ
ꢖ.ꢓ
ꢊ
ꢉ
ꢉ.ꢓ
ꢖ
ꢖ.ꢓ
ꢊ
ꢉ
ꢉ.ꢓ
ꢖ
ꢖ.ꢓ
ꢊ
ꢀꢁꢂ ꢃꢄRRꢁꢅꢆ ꢇAꢈ
ꢀꢁꢂ ꢃꢄRRꢁꢅꢆ ꢇAꢈ
ꢀꢁꢂ ꢃꢄRRꢁꢅꢆ ꢇAꢈ
ꢐꢕꢏꢕ ꢗꢉꢕ
ꢐꢕꢏꢕ ꢗꢉꢖ
ꢐꢕꢏꢕ ꢗꢉꢊ
Rev. A
7
For more information www.analog.com
LT8393
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Switching Waveforms
(Buck Region)
Switching Waveforms
(Buck-Boost Region)
Switching Waveforms
(Boost Region)
ꢆ
ꢇꢈꢉ
ꢆ
ꢆ
ꢇꢈꢉ
ꢀꢊꢆꢃꢄꢅꢆ
ꢇꢈꢉ
ꢀꢊꢆꢃꢄꢅꢆ
ꢀꢊꢆꢃꢄꢅꢆ
ꢆ
ꢇꢈꢀ
ꢆ
ꢆ
ꢇꢈꢀ
ꢀꢊꢆꢃꢄꢅꢆ
ꢇꢈꢀ
ꢀꢊꢆꢃꢄꢅꢆ
ꢀꢊꢆꢃꢄꢅꢆ
ꢅ
ꢋ
ꢀAꢃꢄꢅꢆ
ꢅ
ꢅ
ꢋ
ꢋ
ꢀAꢃꢄꢅꢆ
ꢀAꢃꢄꢅꢆ
ꢌꢍꢎꢍ ꢏꢊꢐ
ꢌꢍꢎꢍ ꢏꢊꢐ
ꢌꢍꢎꢍ ꢏꢊꢐ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆ
ꢒ ꢉꢐꢆꢓ ꢅ ꢒ ꢀA
ꢆ
ꢒ ꢍꢀꢆꢓ ꢆ
ꢒ ꢉꢕꢆꢓ ꢅ
ꢒ ꢀA
ꢆ
ꢅꢑ
ꢒ ꢉꢓꢆꢔ ꢆ
ꢒ ꢉꢓꢆꢔ ꢅ
ꢒ ꢀA
ꢆ ꢒ ꢌꢆꢓ ꢆ
ꢅꢑ ꢋꢔꢄ
ꢅꢑ
ꢋꢔꢄ
ꢋꢔꢄ
ꢋꢕꢄ
ꢋꢕꢄ
ꢋꢔꢄ
LED Current vs VIN
VIN Shutdown Current
VIN Quiescent Current
ꢑ.ꢑꢌ
ꢑ.ꢍꢒ
ꢑ.ꢋ
ꢏ.ꢊ
ꢏ.ꢋ
ꢐ.ꢊ
ꢐ.ꢋ
ꢋ.ꢊ
ꢋ.ꢋ
ꢑ.ꢋ
ꢏ.ꢊ
ꢏ.ꢋ
ꢐ.ꢊ
ꢐ.ꢋ
ꢋ.ꢊ
ꢋ.ꢋ
ꢑ.ꢍꢌ
ꢖ
ꢖ
ꢘ ꢙꢋꢖ
ꢘ ꢐꢏꢖ
ꢌꢗ
ꢌꢗ
ꢑ.ꢌꢒ
ꢑ.ꢌꢌ
ꢖ
ꢖ
ꢘ ꢙꢋꢖ
ꢘ ꢐꢏꢖ
ꢌꢗ
ꢌꢗ
ꢍ.ꢓꢒ
ꢍ.ꢓꢌ
ꢖ
ꢌꢗ
ꢘ ꢚꢖ
ꢖ
ꢌꢗ
ꢘ ꢚꢖ
ꢍ.ꢎꢒ
ꢍ.ꢎꢌ
ꢌ
ꢍꢌ
ꢑꢌ
ꢔꢌ
ꢕꢌ
ꢒꢌ
ꢖꢌ
ꢉꢊꢋ ꢉꢏꢊ
ꢋ
ꢏꢊ ꢊꢋ ꢒꢊ ꢐꢋꢋ ꢐꢏꢊ ꢐꢊꢋ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢉꢊꢋ ꢉꢏꢊ
ꢋ
ꢏꢊ ꢊꢋ ꢒꢊ ꢐꢋꢋ ꢐꢏꢊ ꢐꢊꢋ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄAꢈꢉ ꢊꢅꢋ
ꢎꢔꢓꢔ ꢈꢌꢗ
ꢓꢑꢔꢑ ꢕꢋꢓ
ꢓꢑꢔꢑ ꢕꢋꢔ
INTVCC Voltage vs Temperature
INTVCC Voltage vs VIN
INTVCC UVLO Threshold
ꢊ.ꢑꢊ
ꢊ.ꢑꢋ
ꢊ.ꢋꢊ
ꢊ.ꢋꢋ
ꢌ.ꢒꢊ
ꢌ.ꢒꢋ
ꢌ.ꢍꢊ
ꢈ.ꢋꢈ
ꢈ.ꢋꢅ
ꢈ.ꢅꢈ
ꢈ.ꢅꢅ
ꢆ.ꢌꢈ
ꢆ.ꢌꢅ
ꢆ.ꢇꢈ
ꢕ.ꢋ
ꢌ.ꢑ
ꢌ.ꢒ
ꢌ.ꢓ
ꢌ.ꢔ
ꢌ.ꢊ
ꢌ.ꢕ
ꢌ.ꢌ
ꢌ.ꢍ
Rꢏꢘꢏꢐꢗ
ꢁ
ꢑ ꢐꢅꢒA
ꢁꢂꢉꢀꢊꢊ
ꢏ
ꢗ ꢋꢘA
ꢏꢐꢀꢎꢇꢇ
ꢙAꢚꢚꢏꢐꢗ
ꢏ
ꢗ ꢍꢋꢘA
ꢏꢐꢀꢎꢇꢇ
ꢉꢊꢋ ꢉꢓꢊ
ꢋ
ꢓꢊ ꢊꢋ ꢔꢊ ꢑꢋꢋ ꢑꢓꢊ ꢑꢊꢋ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢅ
ꢋꢅ
ꢐꢅ
ꢍꢅ
ꢃꢀꢄ
ꢆꢅ
ꢈꢅ
ꢎꢅ
ꢉꢊꢋ ꢉꢍꢊ
ꢋ
ꢍꢊ ꢊꢋ ꢓꢊ ꢖꢋꢋ ꢖꢍꢊ ꢖꢊꢋ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀ
ꢁꢂ
ꢍꢕꢒꢕ ꢖꢑꢋ
ꢇꢍꢌꢍ ꢏꢋꢋ
ꢒꢌꢑꢌ ꢗꢖꢍ
Rev. A
8
For more information www.analog.com
LT8393
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
VREF Voltage vs Temperature
VREF Voltage vs VIN
VREF UVLO Threshold
ꢑ.ꢋꢕ
ꢑ.ꢋꢒ
ꢑ.ꢋꢑ
ꢑ.ꢋꢌ
ꢑ.ꢋꢋ
ꢌ.ꢍꢍ
ꢌ.ꢍꢓ
ꢌ.ꢍꢔ
ꢌ.ꢍꢎ
ꢋ.ꢅꢏ
ꢋ.ꢅꢌ
ꢋ.ꢅꢋ
ꢋ.ꢅꢆ
ꢋ.ꢅꢅ
ꢆ.ꢇꢇ
ꢆ.ꢇꢍ
ꢆ.ꢇꢎ
ꢆ.ꢇꢈ
ꢒ.ꢋꢋ
ꢌ.ꢐꢊ
ꢌ.ꢐꢋ
ꢌ.ꢑꢊ
ꢌ.ꢑꢋ
ꢌ.ꢍꢊ
ꢌ.ꢍꢋ
ꢗ
ꢗ
ꢘ ꢋꢙA
ꢘ ꢌꢙA
ꢏRꢁꢐ
ꢏRꢁꢐ
ꢁ
ꢒ ꢆꢅꢅꢓA
Rꢕꢖꢕꢗꢔ
ꢀRꢉꢊ
ꢏAꢘꢘꢕꢗꢔ
ꢉꢊꢋ ꢉꢑꢊ
ꢋ
ꢑꢊ ꢊꢋ ꢔꢊ ꢌꢋꢋ ꢌꢑꢊ ꢌꢊꢋ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢅ
ꢆꢅ
ꢋꢅ
ꢌꢅ
ꢃꢀꢄ
ꢏꢅ
ꢐꢅ
ꢈꢅ
ꢉꢊꢋ ꢉꢒꢊ
ꢋ
ꢒꢊ ꢊꢋ ꢍꢊ ꢌꢋꢋ ꢌꢒꢊ ꢌꢊꢋ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀ
ꢁꢂ
ꢓꢒꢍꢒ ꢖꢌꢒ
ꢍꢌꢇꢌ ꢑꢆꢏ
ꢑꢓꢐꢓ ꢔꢌꢊ
EN/UVLO Enable Threshold
EN/UVLO Hysteresis Current
CTRL Dim-Off Threshold
ꢋ.ꢐꢋ
ꢋ.ꢏꢊ
ꢋ.ꢏꢋ
ꢋ.ꢌꢊ
ꢋ.ꢌꢋ
ꢌ.ꢍꢔꢋ
ꢌ.ꢍꢓꢊ
ꢌ.ꢍꢓꢋ
ꢌ.ꢍꢍꢊ
ꢌ.ꢍꢍꢋ
ꢌ.ꢍꢌꢊ
ꢌ.ꢍꢌꢋ
ꢌ.ꢍꢋꢊ
ꢌ.ꢍꢋꢋ
ꢕ.ꢋ
ꢌ.ꢒ
ꢌ.ꢓ
ꢌ.ꢔ
ꢌ.ꢌ
ꢌ.ꢋ
Rꢚꢛꢚꢏꢘ
Rꢕꢖꢕꢗꢔ
ꢘAꢎꢎꢕꢗꢔ
ꢜAꢑꢑꢚꢏꢘ
ꢉꢊꢋ ꢉꢏꢊ
ꢋ
ꢏꢊ ꢊꢋ ꢑꢊ ꢌꢋꢋ ꢌꢏꢊ ꢌꢊꢋ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢉꢊꢋ ꢉꢍꢊ
ꢋ
ꢍꢊ ꢊꢋ ꢕꢊ ꢌꢋꢋ ꢌꢍꢊ ꢌꢊꢋ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢉꢊꢋ ꢉꢌꢊ
ꢋ
ꢌꢊ ꢊꢋ ꢖꢊ ꢗꢋꢋ ꢗꢌꢊ ꢗꢊꢋ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢒꢐꢓꢐ ꢔꢌꢒ
ꢖꢓꢗꢓ ꢘꢌꢙ
ꢒꢕꢘꢕ ꢙꢗꢖ
V(ISP-ISN) Regulation
vs Temperature
V
(ISP-ISN) Regulation vs VCTRL
V(ISP-ISN) Regulation vs VISP
ꢍꢐꢏ
ꢍꢆꢆ
ꢎꢏ
ꢏꢆ
ꢐꢏ
ꢆ
ꢌꢆꢏ
ꢌꢆꢈ
ꢌꢆꢍ
ꢌꢆꢆ
ꢇꢎ
ꢔꢋꢗ
ꢔꢋꢍ
ꢔꢋꢕ
ꢔꢋꢋ
ꢌꢖ
ꢏꢐꢃꢛꢋꢎ
ꢏꢐꢃꢛꢔꢕꢎ
ꢏꢐꢃꢛꢔꢋꢋꢎ
ꢇꢏ
ꢌꢗ
ꢇꢈ
ꢌꢍ
ꢆ.ꢆꢆ ꢆ.ꢐꢏ ꢆ.ꢏꢆ ꢆ.ꢎꢏ ꢍ.ꢆꢆ ꢍ.ꢐꢏ ꢍ.ꢏꢆ ꢍ.ꢎꢏ ꢐ.ꢆꢆ
ꢄꢀꢅ
ꢆ
ꢍꢆ
ꢈꢆ
ꢏꢆ
ꢄꢀꢅ
ꢎꢆ
ꢌꢆꢆ
ꢉꢊꢋ ꢉꢕꢊ
ꢋ
ꢕꢊ ꢊꢋ ꢚꢊ ꢔꢋꢋ ꢔꢕꢊ ꢔꢊꢋ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀ
ꢀ
ꢁꢂꢃ
ꢁꢂRꢃ
ꢑꢒꢓꢒ ꢔꢍꢓ
ꢎꢐꢇꢐ ꢑꢍꢆ
ꢖꢘꢌꢘ ꢙꢕꢔ
Rev. A
9
For more information www.analog.com
LT8393
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Maximum Current Sense
V(ISP-ISN) Regulation vs VFB
FB Regulation vs Temperature
vs Temperature
ꢎꢑꢅ
ꢎꢅꢅ
ꢏꢅ
ꢇꢅ
ꢐꢅ
ꢑꢅ
ꢅ
ꢑ.ꢋꢔ
ꢑ.ꢋꢒ
ꢑ.ꢋꢑ
ꢑ.ꢋꢋ
ꢋ.ꢌꢌ
ꢋ.ꢌꢓ
ꢋ.ꢌꢍ
ꢔꢋ
ꢒꢊ
ꢒꢋ
ꢊꢊ
ꢊꢋ
ꢓꢊ
ꢓꢋ
ꢎ
ꢎ
ꢎ
ꢘ ꢚꢎ
ꢘ ꢑꢒꢎ
ꢘ ꢙꢋꢎ
ꢖꢗ
ꢖꢗ
ꢖꢗ
ꢚꢄꢇꢝ
ꢚꢛꢛꢜꢀ
ꢌꢊ
ꢌꢋ
ꢅ.ꢆꢇ ꢅ.ꢆꢒ ꢅ.ꢆꢏ ꢅ.ꢆꢆ ꢎ.ꢅꢅ ꢎ.ꢅꢎ ꢎ.ꢅꢑ ꢎ.ꢅꢓ ꢎ.ꢅꢐ
ꢃꢀꢄ
ꢉꢊꢋ ꢉꢒꢊ
ꢋ
ꢒꢊ ꢊꢋ ꢍꢊ ꢑꢋꢋ ꢑꢒꢊ ꢑꢊꢋ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢉꢊꢋ ꢉꢕꢊ
ꢋ
ꢕꢊ ꢊꢋ ꢔꢊ ꢖꢋꢋ ꢖꢕꢊ ꢖꢊꢋ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀ
ꢁꢂ
ꢏꢓꢆꢓ ꢔꢑꢑ
ꢓꢔꢌꢔ ꢕꢒꢔ
ꢗꢌꢘꢌ ꢙꢕꢓ
FB Overvoltage Threshold
FB Open LED Threshold
FB Short LED Threshold
ꢋ.ꢒꢋ
ꢋ.ꢐꢊ
ꢋ.ꢐꢋ
ꢋ.ꢑꢊ
ꢋ.ꢑꢋ
ꢋ.ꢌꢊ
ꢋ.ꢌꢋ
ꢐ.ꢐꢋ
ꢐ.ꢋꢊ
ꢐ.ꢋꢋ
ꢋ.ꢑꢊ
ꢋ.ꢑꢋ
ꢋ.ꢌꢊ
ꢋ.ꢌꢋ
ꢐ.ꢐꢋ
ꢐ.ꢋꢊ
ꢐ.ꢋꢋ
ꢋ.ꢑꢊ
ꢋ.ꢑꢋ
ꢋ.ꢌꢊ
ꢋ.ꢌꢋ
Rꢖꢗꢖꢘꢕ
ꢎAꢙꢙꢖꢘꢕ
Rꢗꢘꢗꢙꢖ
Rꢗꢘꢗꢙꢕ
ꢎAꢚꢚꢗꢙꢖ
ꢎAꢚꢚꢗꢙꢕ
ꢉꢊꢋ ꢉꢑꢊ
ꢋ
ꢑꢊ ꢊꢋ ꢓꢊ ꢌꢋꢋ ꢌꢑꢊ ꢌꢊꢋ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢉꢊꢋ ꢉꢓꢊ
ꢋ
ꢓꢊ ꢊꢋ ꢒꢊ ꢐꢋꢋ ꢐꢓꢊ ꢐꢊꢋ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢉꢊꢋ ꢉꢓꢊ
ꢋ
ꢓꢊ ꢊꢋ ꢒꢊ ꢐꢋꢋ ꢐꢓꢊ ꢐꢊꢋ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢔꢐꢕꢐ ꢖꢑꢓ
ꢌꢔꢑꢔ ꢕꢓꢊ
ꢌꢔꢑꢔ ꢕꢓꢖ
Oscillator Frequency
vs Temperature
ISP/ISN Open LED Threshold
SS Current vs Temperature
ꢔꢋ
ꢒꢊ
ꢒꢋ
ꢓꢊ
ꢓꢋ
ꢊ
ꢏꢊ.ꢋ
ꢏꢐ.ꢊ
ꢏꢋ.ꢋ
ꢑ.ꢊ
ꢖ.ꢊ
ꢖ
ꢃꢄꢖꢖꢗꢄꢃ
R ꢜꢊꢗ.ꢗꢝ
ꢀ
ꢗ.ꢊ
ꢗ
Rꢍꢎꢍꢐꢘ
ꢊ.ꢋ
ꢙAꢚꢚꢍꢐꢘ
ꢋ.ꢊ
ꢐ.ꢊ
ꢃꢄꢖꢖꢗꢘꢙꢚꢛ
R ꢜꢞꢖꢖꢝ
ꢀ
ꢋ
ꢋ.ꢋ
ꢋ
ꢉꢊꢋ ꢉꢒꢊ
ꢋ
ꢒꢊ ꢊꢋ ꢕꢊ ꢓꢋꢋ ꢓꢒꢊ ꢓꢊꢋ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢉꢊꢋ ꢉꢐꢊ
ꢋ
ꢐꢊ ꢊꢋ ꢑꢊ ꢏꢋꢋ ꢏꢐꢊ ꢏꢊꢋ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢉꢊꢋ ꢉꢖꢊ
ꢋ
ꢖꢊ ꢊꢋ ꢘꢊ ꢗꢋꢋ ꢗꢖꢊ ꢗꢊꢋ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢖꢔꢗꢔ ꢘꢒꢖ
ꢒꢓꢔꢓ ꢕꢐꢔ
ꢙꢚꢛꢚ ꢑꢚꢋ
Rev. A
10
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LT8393
PIN FUNCTIONS
EN/UVLO: Enable and Undervoltage Lockout. Force the
pin below 0.3V to shut down the part and reduce V qui-
modes during open or short LED fault conditions: hiccup
(no resistor), latchoff (499k), and keep-running (100k).
See more details in the Typical Application section.
IN
escent current below 2µA. Force the pin above 1.233V for
normal operation. The accurate 1.220V falling threshold
can be used to program an undervoltage lockout (UVLO)
V : Error Amplifier Output to Set Inductor Current Com-
C
parator Threshold. The V pin is used to compensate the
C
threshold with a resistor divider from V to ground. An
IN
control loop with an external RC network. During PWM
accurate2.5µApull-downcurrentallowstheprogramming
low state, the V pin is disconnected from all internal
C
of V UVLO hysteresis. If neither function is used, tie this
IN
loads to store its voltage information for the highest PWM
pin directly to V .
IN
dimming performance.
ISP: Positive Terminal of the LED Current Sense Resistor
FB: Voltage Loop Feedback Input. The FB pin is used for
constant-voltage regulation and LED fault protection. The
(R ). Ensure accurate current sense with Kelvin con-
LED
nection.
internal error amplifier with its output V regulates V
C
FB
ISN: Negative Terminal of the LED Current Sense Resis-
to 1.00V through the DC/DC converter. During open LED
tor (R ). Ensure accurate current sense with Kelvin
(V > 0.95V & V
< 10mV) or short LED (V
<
LED
FB
(ISP-ISN)
FB
connection.
0.25V) fault conditions, the part pulls the FAULT pin low
and gets into one fault mode per customer setting. During
an overvoltage (V > 1.05V) condition, the part turns off
CTRL:ControlInputforLEDCurrentSenseThreshold.The
CTRL pin is used to program the LED regulation current:
FB
all TG1, BG1, TG2, BG2, and PWMTG.
Min V
–0.25V,1V
)
10•RLED
(
CTRL
RT: Switching Frequency Setting. Connect a resistor from
this pin to ground to set the internal oscillator frequency
from 350kHz to 2MHz.
ILED
=
The V
can be set by an external voltage reference or
CTRL
SYNC/SPRD: Switching Frequency Synchronization or
Spread Spectrum. Ground this pin for switching at inter-
nal oscillator frequency. Apply a clock signal for external
a resistor divider from V to ground. For 0.25V ≤ V
REF
CTRL
≤ 1.15V, the current sense threshold linearly goes up
from 0mV to 90mV. For V ≥ 1.35V, the current sense
CTRL
frequency synchronization. Tie to INTV for 25% triangle
CC
threshold is constant at 100mV full scale value. For 1.15V
spread spectrum above internal oscillator frequency.
≤ V ≤ 1.35V, the current sense threshold smoothly
CTRL
transitions from the linear function of V
to the 100mV
CTRL
FAULT: LED Fault Open Drain Output. The FAULT pin is
pulled low when any of the following conditions happens:
constant value. Tie CTRL to V for the 100mV full scale
REF
threshold. Force the pin below 0.2V to stop switching.
1. Open LED (V > 0.95V & V
< 10mV)
FB
(ISP-ISN)
V
: Voltage Reference Output. The V pin provides an
REF
REF
2. Short LED (V < 0.25V)
FB
accurate 2V reference capable of supplying 1mA current.
Locally bypass this pin to ground with a 0.47µF ceramic
capacitor.
To function, the pin requires an external pull-up resistor.
The FAULT status is updated only during PWM high state
and latched during PWM low state.
SS: Soft-Start Timer Setting. The SS pin is used to set
soft-start timing by connecting a capacitor to ground. An
internal 12.5µA pull-up current charging the external SS
capacitor gradually ramps up FB regulation voltage. A
0.1µF capacitor is recommended on this pin. Any UVLO or
thermalshutdownimmediatelypullsSSpintogroundand
RP: Internal PWM Dimming Frequency Setting. The RP
pin is used to set the internal PWM dimming frequency
with a resistor to ground. Do not use a resistor larger
than 1MΩ and do not leave this pin open. If an external
PWM dimming pulse is available at the PWM pin, tie this
pin to ground.
stops switching. Using a single resistor from SS to V
the LT8393 can be set in three different fault protection
,
REF
Rev. A
11
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LT8393
PIN FUNCTIONS
PWM: PWM Dimming Input. The PWM pin can be used
in two ways: external PWM dimming and internal PWM
dimming. For external PWM dimming, drive this pin with
a digital pulse from 0V to a voltage higher than 1.5V to
control PWM dimming of the LED string. Make sure the
RP pin is tied to ground in this case. For internal PWM
dimming, apply an analog voltage between 1V and 2V to
generate an internal digital pulse by comparing with the
internal ramp. If PWM dimming is not used, tie this pin to
INTV : Internal 5V Linear Regulator Output. The INTV
CC CC
linear regulator is supplied from the V pin, and powers
IN
the internal control circuitry and gate drivers. Locally
bypass this pin to ground with a minimum 4.7µF ceramic
capacitor.
BG1:BuckSideBottomGateDrive. Drivesthegateofbuck
sidebottomN-channelMOSFETwithavoltageswingfrom
ground to INTV .
CC
SW1: Buck Side Switch Node.
INTV . Forcing the pin low turns off TG1 and TG2, turns
CC
on BG1 and BG2, disconnects the V pin from all internal
C
TG1: Buck Side Top Gate Drive. Drives the gate of buck
side top N-channel MOSFET with a voltage swing from
SW1 to BST1.
loads, and turns off PWMTG.
PWMTG: PWM Dimming Top Gate Drive. A buffered and
inverted version of the PWM input signal, the PWMTG
pin drives an external high side PMOS PWM switch with
BST1: Buck Side Bootstrap Floating Driver Supply. The
BST1 pin has an integrated bootstrap Schottky diode
a voltage swing from the higher voltage of (V
–10V)
OUT
from the INTV pin and requires an external bootstrap
CC
and 1V to V . Leave this pin unconnected if not used.
OUT
capacitor to the SW1 pin.
V
: Output Supply. The V
pin must be tied to the
OUT
OUT
LSN: Negative Terminal of the Buck Side Inductor Current
power output to determine the buck, buck-boost, or boost
Sense Resistor (R
). Ensure accurate current sense
SENSE
operationregions.TheV pinalsoservesaspositiverail
OUT
with Kelvin connection.
LSP: Positive Terminal of the Buck Side Inductor Current
Sense Resistor (R ). Ensure accurate current sense
for the PWMTG drive. Locally bypass this pin to ground
with a minimum 1µF ceramic capacitor.
SENSE
BST2: Boost Side Bootstrap Floating Driver Supply. The
with Kelvin connection.
BST2 pin requires an external bootstrap Schottky diode
V : Input Supply. The V pin must be tied to the power
IN
IN
from the INTV pin and requires an external bootstrap
CC
inputtodeterminethebuck,buck-boost,orboostoperation
regions.Locallybypassthispintogroundwithaminimum
1µF ceramic capacitor.
capacitor to the SW2 pin.
TG2: Boost Side Top Gate Drive. Drives the gate of boost
side top N-Channel MOSFET with a voltage swing from
SW2 to BST2.
GND (Exposed Pad): Ground. Solder the exposed pad
directly to the ground plane.
SW2: Boost Side Switch Node.
BG2: Boost Side Bottom Gate Drive. Drives the gate of
boost side bottom N-Channel MOSFET with a voltage
swing from ground to INTV .
CC
Rev. A
12
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LT8393
BLOCK DIAGRAM
ꢉ
ꢎꢏ
ꢊꢒꢏ
ꢊꢒꢕ
ꢎꢏꢐꢉ
ꢑꢑ
ꢎꢏꢐꢉ
ꢑꢑ
ꢀ
ꢁ
ꢈꢉ ꢊꢋꢌ
ꢃꢉ Rꢂꢍ
ꢖꢒꢐꢄ
ꢐꢞꢄ
ꢀ
ꢁ
Aꢄ
Aꢇ
ꢉ
Rꢂꢍ
ꢒꢛꢄ
ꢕꢂAꢙꢚꢖꢝꢑꢙ
ꢖꢝꢑꢙ
ꢊꢌꢞꢎꢑ
ꢎꢏꢐꢉ
ꢑꢑ
ꢕꢛꢜ
ꢌꢏ
Rꢐ
ꢖꢞꢄ
ꢌꢒꢑ
ꢉ
ꢌꢒ
ꢒꢓꢏꢑꢔꢒꢕRꢋ
ꢞꢏꢋ
ꢔꢖꢒꢐꢃ
ꢆ.ꢃꢉ
ꢀ
ꢁ
ꢉ
ꢑꢢARꢞꢂ
ꢑꢌꢏꢐRꢌꢊ
ꢌꢝꢐ
ꢉ
ꢑꢐRꢊ
ꢔꢖꢒꢐꢄ
ꢎꢏ
ꢀ
ꢁ
ꢍꢖ
ꢍꢖꢌꢉ
ꢞꢏꢋ
ꢄ.ꢆꢈꢉ
ꢎꢏꢢꢎꢖꢎꢐ
ꢒꢛꢎꢐꢑꢢ
ꢖꢞꢃ
ꢂꢏꢔꢝꢉꢊꢌ
ꢄ.ꢃꢃꢆꢉ
ꢁ
ꢀ
ꢕꢛꢜ
ꢌꢏ
ꢀ
ꢁ
ꢉ
ꢎꢒꢕꢗꢎꢒꢏ
ꢖꢌꢌꢒꢐ
ꢊꢌꢞꢎꢑ
ꢎꢏꢐꢉ
ꢑꢑ
ꢎꢒꢌꢑ
ꢒꢛꢃ
ꢐꢞꢃ
ꢆ.ꢘꢈꢉ
ꢕꢂAꢙꢚꢖꢌꢌꢒꢐ
ꢃ.ꢈꢡA
ꢀ
Aꢤ
ꢖꢒꢐꢃ
ꢁ
ꢕꢛꢜ
Rꢕ
ꢎꢏꢐꢔꢂꢣꢐ
ꢕꢛꢜ
ꢉ
ꢕꢛꢜ
Rꢂꢍ
ꢌꢏ
ꢄꢃ.ꢈꢡA
ꢆ.ꢄꢉ
ꢀ
ꢉ
ꢌꢝꢐ
ꢀ
ꢀ
ꢁ
ꢉ
ꢁ
ꢎꢒ
ꢂAꢄ
ꢄꢉ
ꢕꢛꢜꢐꢞ
ꢍꢖ
ꢌꢕꢂꢏ
ꢊꢂꢋ
ꢍAꢝꢊꢐ
ꢊꢌꢞꢎꢑ
ꢄꢆꢡA
ꢍꢖ
ꢀ
ꢁ
ꢉ
ꢁꢄꢆꢉ
ꢆ.ꢠꢈꢉ
ꢌꢝꢐ
ꢑꢐRꢊ
ꢀ
ꢀ
ꢁ
FAULT
ꢄ.ꢃꢈꢡA
ꢂAꢃ
ꢄ.ꢃꢈꢉ
ꢎꢒꢕ
ꢆ.ꢃꢈꢉ
ꢍꢖ
ꢀ
ꢁ
ꢀ
ꢒꢢꢌRꢐ
Aꢃꢅꢄꢆ
ꢀ
ꢕꢛꢜ
ꢌꢏ
ꢎꢒꢏ
ꢁ
ꢉ
ꢎꢒ
ꢒꢒ
ꢉ
ꢞꢏꢋ
ꢆ.ꢃꢈꢉ
ꢑ
ꢟꢇꢠꢇ ꢖꢋ
Rev. A
13
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LT8393
OPERATION
The LT8393 is a current mode LED controller that can
regulate LED current from input voltages above, below,
or equal to the LED string voltage. The LTC proprietary
peak-buck peak-boost current mode control scheme uses
a single inductor current sense resistor and provides
smooth transition between the buck region, buck-boost
region, and boost region. Its operation is best understood
by referring to the Block Diagram.
ꢀꢁAꢂꢃꢄꢅꢆꢂ
ꢀꢁAꢂꢃꢄꢇꢇꢈꢉ
Power Switch Control
ꢐꢓꢏꢓ ꢔꢎꢒ
ꢎ.ꢏꢐ ꢑ.ꢎꢎ ꢑ.ꢎꢒ
ꢍꢊ
ꢊ
ꢋꢌ ꢇꢅꢉ
Figure1showsasimplifieddiagramofhowthefourpower
switches A, B, C, and D are connected to the inductor L,
Figure 2. Current Mode vs VIN/VOUT Ratio
the current sense resistor R
, power input V , power
SENSE
IN
outputV ,andground.ThecurrentsenseresistorR
OUT
SENSE
ꢄꢅꢆ
connected to the LSP and LSN pins provides inductor cur-
rent information for both peak current mode control and
reverse current detection in the buck region, buck-boost
region,andboostregion.Figure2showsthecurrentmode
ꢀꢁꢂꢃ
ꢄꢈꢆ
ꢀꢁꢂꢃꢌꢀꢉꢉꢊꢋ
control as a function of V /V
ratio and Figure 3 shows
IN OUT
ꢄꢇꢆ
the operation region as a function of V /V
ratio. The
IN OUT
powerswitchesareproperlycontrolledtosmoothlytransi-
tion between modes and regions. Hysteresis is added to
prevent chattering between modes and regions.
ꢀꢉꢉꢊꢋ
ꢄꢗꢆ
ꢑ.ꢔꢓ ꢑ.ꢒꢓ
ꢅ.ꢑꢑ
ꢐꢍ
ꢅ.ꢇꢓ ꢅ.ꢈꢈ
ꢒꢈꢕꢈ ꢖꢑꢈ
ꢍ
ꢎꢏ ꢉꢁꢋ
ꢀ
ꢀ
ꢁꢂꢃ
ꢒꢓ
Figure 3. Operation Region vs VIN/VOUT Ratio
ꢃꢉꢇ
ꢊꢉꢇ
A
ꢄ
ꢃꢉꢈ
ꢊꢉꢈ
R
ꢑ
ꢅꢔꢓꢅꢔ
ꢅꢆꢇ
ꢅꢆꢈ
Peak-Buck in Buck Region (V >> V
)
IN
OUT
ꢊ
ꢐ
WhenV ismuchhigherthanV ,theLT8393usespeak-
IN
OUT
buck current mode control in the buck region (Figure 4).
Switch C is always off and switch D is always on. At the
beginning of every cycle, switch A is turned on and the
inductor current ramps up. When the inductor current
hits the peak buck current threshold commanded by the
ꢋꢌꢍꢌ ꢎꢏꢇ
Figure 1. Simplified Diagram of the Power Switches
There are total four states: (1) peak-buck current mode
controlinbuckregion,(2)peak-buckcurrentmodecontrol
inbuck-boostregion,(3)peak-boostcurrentmodecontrol
in buck-boost region, and (4) peak-boost current mode
controlinboostregion.Thefollowingsectionsgivedetailed
descriptionforeachstatewithwaveforms, withtheshoot-
through protection dead time between switches A and B,
and between switches C and D ignored for simplification.
V voltage at buck current comparator A3 during “A+D”
C
phase, switch A is turned off and switch B is turned on
for the rest of the cycle. Switches A and B will alternate,
behaving like a typical synchronous buck regulator.
Rev. A
14
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LT8393
OPERATION
A
ꢀ
A
ꢆ
ꢁ
ꢆ
ꢇ
ꢈ
ꢀꢁꢁꢂ ꢃꢄꢄ
ꢀꢁꢁꢂ ꢃꢅ
ꢂꢃꢄ
ꢂꢃꢄ
ꢅꢃꢄ
ꢅꢃꢄ
ꢇ
ꢉ
ꢈ
ꢊ
Aꢉꢆ
Aꢉꢆ
ꢆꢋꢈ
ꢆꢋꢈ
Aꢉꢁ
Aꢉꢁ
ꢀꢉꢆ
ꢀꢉꢆ
Aꢋꢈ
Aꢋꢈ
ꢅꢊꢋꢊ ꢌꢃꢍ
ꢌꢍꢎꢍ ꢄꢁꢏ
Figure 4. Peak-Buck in Buck Region (VIN >> VOUT
)
Figure 5. Peak-Buck in Buck-Boost Region (VIN ~> VOUT)
Peak-Buck in Buck-Boost Region (V ~> V
)
OUT
IN
A
ꢀ
ꢅꢃꢄ
ꢅꢃꢄ
When V is slightly higher than V , the LT8393 uses
IN
OUT
peak-buck current mode control in the buck-boost region
(Figure 5). Switch C is always turned on for the beginning
20% of the cycle and switch D is always turned on for the
remaining80%ofthecycle.Atthebeginningofeverycycle,
switches A and C are turned on and the inductor current
ramps up. After 20% of the cycle, switch C is turned off
and switch D is turned on, and the inductor keeps ramping
up. When the inductor current hits the peak buck current
ꢂꢃꢄ
ꢂꢃꢄ
ꢁ
ꢆ
threshold commanded by the V voltage at buck current
C
Aꢉꢆ
Aꢉꢆ
comparator A3 during the “A+D” phase, switch A is turned
ꢇ
ꢈ
Aꢉꢁ
Aꢉꢁ
off and switch B is turned on for the rest of the cycle.
ꢀꢉꢆ
ꢀꢉꢆ
ꢅꢊꢋꢊ ꢌꢃꢍ
Peak-Boost in Buck-Boost Region (V <~ V
)
OUT
IN
Figure 6. Peak-Boost in Buck-Boost Region (VIN <~ VOUT
)
When V is slightly lower than V , the LT8393 uses
IN
OUT
peak-boostcurrentmodecontrolinthebuck-boostregion
(Figure 6). Switch A is always turned on for the beginning
80% of the cycle and switch B is always turned on for the
remainingofthe20%cycle.Atthebeginningofeverycycle,
switches A and C are turned on and the inductor current
ramps up. When the inductor current hits the peak boost
Peak-Boost in Boost Region (V << V
)
IN
OUT
When V is much lower than V , the LT8393 uses peak-
IN
OUT
boost current mode control in the boost region (Figure 7).
SwitchAisalwaysonandswitchBisalwaysoff.Atthebegin-
ning of every cycle, switch C is turned on and the inductor
current ramps up. When the inductor current hits the peak
current threshold commanded by the V voltage at boost
C
boost current threshold commanded by the V voltage at
C
current comparator A4 during the “A+C” phase, switch C
is turned off and switch D is turned on for the rest of the
cycle. After 80% cycle completion, switch A is turned off
and switch B is turned on for the rest of the cycle.
boostcurrentcomparatorA4duringthe“A+C”phase,switch
C is turned off and switch D is turned on for the rest of
Rev. A
15
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LT8393
OPERATION
the cycle. Switches C and D will alternate, behaving like a
typical synchronous boost regulator.
Light Load Current Operation
At light load, the LT8393 typically still runs at its full
switching frequency in either continuous conduction
modeordiscontinuousconductionmodebecauseboththe
buck and boost reverse current sense thresholds are set
to –4mV. The negative reverse current sense thresholds
allow a small amount of energy flowing from the output
to the input on every cycle, thereby preventing the pulse-
skip frequency from going below 100Hz, which causes
the LED string to flicker.
A
ꢀ
ꢂꢃꢃꢄ ꢅꢆ
ꢂꢃꢃꢄ ꢅꢇꢇ
ꢁ
ꢈ
In the buck region, switch B is turned off whenever the
buck reverse current threshold is triggered during the
“B+D” phase. In the boost region, switch D is turned off
whenever the boost reverse current threshold is triggered
duringthe“A+D”phase.Inthebuck-boostregion,switchD
isturnedoffwhenevertheboostreversecurrentthreshold
is triggered during the “A+D” phase, and both switches B
and D are turned off whenever the buck reverse current
threshold is triggered during the “B+D” phase.
ꢉ
ꢊ
Aꢋꢁ
Aꢋꢈ
Aꢋꢁ
Aꢋꢈ
ꢌꢍꢎꢍ ꢇꢃꢏ
Figure 7. Peak-Boost in Boost Region (VIN << VOUT
)
Main Control Loop
However, when a smaller value inductor is used and the
inductor current ripple is bigger, the LT8393 may run in
pulse-skip mode, where the switches are held off for mul-
tiple cycles (i.e., skipping pulses) to maintain regulation.
The LT8393 is a fixed frequency current mode control-
ler. The inductor current is sensed through the inductor
sense resistor between the LSP and LSN pins. The current
sense voltage is gained up by amplifier A1 and added to
a slope compensation ramp signal from the internal os-
cillator. The summing signal is then fed into the positive
terminals of the buck current comparator A3 and boost
current comparator A4. The negative terminals of A3 and
Internal Charge Path
Each of the two top MOSFET drivers is biased from its
floating bootstrap capacitor, which is normally recharged
byINTV throughboththeexternalandinternalbootstrap
CC
A4 are controlled by the voltage on the V pin, which is
the diode-OR of error amplifiers EA1 and EA2.
C
diodes when the top MOSFET is turned off. When the
LT8393 operates exclusively in the buck or boost regions,
oneofthetopMOSFETsisconstantlyon.Aninternalcharge
Depending on the state of the peak-buck peak-boost cur-
rent mode control, either the buck logic or the boost logic
is controlling the four power switches so that either the
FB voltage is regulated to 1V or the current sense voltage
between the ISP and ISN pins is regulated by the CTRL
pin during normal operation. The gains of EA1 and EA2
have been balanced to ensure smooth transition between
constant-voltage and constant-current operation with the
same compensation network.
path, from V
and BST2 to BST1 or from V and BST1
OUT
IN
to BST2, charges the bootstrap capacitor to 4.6V so that
the top MOSFET can be kept on.
Rev. A
16
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LT8393
OPERATION
Shutdown and Power-On-Reset
dition for the LED string before delivering any switching
energy. In the case of a higher voltage output capacitor
connected to a lower voltage LED string, the excessive
current flowing through the LED string and current sense
resistortriggerstheISP/ISNovercurrent(ISOC)signaland
resets the LT8393 back into the POR state. The LT8393
will hiccup with SS pin between 0V and 0.25V and bypass
the POR, INIT, UP/PRE, and UP/TRY states to slowly
discharge the voltage output capacitor until its voltage
gets closer to the lower voltage LED string. After 10µs in
the UP/TRY state without triggering the ISOC signal, the
LT8393 enters the UP/RUN state.
The LT8393 enters shutdown mode and drains less than
2µA quiescent current when the EN/UVLO pin is below its
shutdown threshold (0.3V minimum). Once the EN/UVLO
pin is above its shutdown threshold (1V maximum), the
LT8393 wakes up startup circuitry, generates bandgap
reference, and powers up the internal INTV LDO. The
CC
INTV LDO supplies the internal control circuitry and
CC
gatedrivers. NowtheLT8393entersundervoltagelockout
(UVLO) mode with a hysteresis current (2.5µA typical)
pulled into the EN/UVLO pin. When the INTV pin is
CC
charged above its rising UVLO threshold (3.78V typi-
cal), the EN/UVLO pin passes its rising enable threshold
(1.233V typical), and the junction temperature is less than
its thermal shutdown (165°C typical), the LT8393 enters
enable mode, in which the EN/UVLO hysteresis current is
ꢋꢎR ꢚ ꢉꢀ ꢎR
ꢀꢃꢎꢐ ꢚ ꢉꢀ
ꢋꢎR
ꢀꢁꢀꢂ
ꢈ ꢃꢃ ꢉARꢊ ꢋꢌꢍꢍ ꢊꢎꢏꢁ
ꢈ ꢃꢏꢀꢂꢐꢉꢀꢁꢑ ꢊꢀꢃAꢒꢍꢓꢊ
ꢈ ꢋꢏꢔꢂꢑ ꢂꢌRꢁꢓꢊ ꢎꢕꢕ
ꢈ ꢃꢃ ꢉARꢊ ꢋꢌꢍꢍ ꢊꢎꢏꢁ
ꢈ ꢃꢏꢀꢂꢐꢉꢀꢁꢑ ꢊꢀꢃAꢒꢍꢓꢊ
ꢈ ꢋꢏꢔꢂꢑ ꢂꢌRꢁꢓꢊ ꢎꢕꢕ
ꢃꢃ ꢄ ꢅ.ꢆꢇ
ꢃꢃ ꢞ ꢅ.ꢆꢟꢇ
ꢃꢃ ꢞ ꢗ.ꢠꢟꢇ
ꢃꢃ ꢄ ꢗ.ꢠꢇ
turned off and the voltage reference V is being charged
REF
up from ground. From the time entering enable mode to
ꢈ ꢁꢎ ꢎꢋꢓꢁꢖꢃꢉꢎRꢂ ꢊꢓꢂꢓꢐꢂꢀꢎꢁ
ꢈ ꢁꢎ ꢎꢋꢓꢁꢖꢃꢉꢎRꢂ ꢊꢓꢂꢓꢐꢂꢀꢎꢁ
the time V
passes its rising UVLO threshold (1.89V
REF
ꢏAꢀꢂ ꢗꢅꢘꢙ Aꢁꢊ
typical),theLT8393goesthroughapower-on-reset(POR),
waking up the entire internal control circuitry and settling
to the right initial conditions. After the POR, the LT8393 is
ready and waiting for the signals on the CTRL and PWM
pins to start switching.
ꢋꢏꢔ ꢚ ꢉꢀ
ꢎꢁ
ꢌꢋꢖꢂRꢢ
ꢌꢋꢖꢋRꢓ
ꢈ ꢃꢃ ꢗꢆ.ꢟꢘA ꢋꢌꢍꢍ ꢌꢋ
ꢈ ꢃꢏꢀꢂꢐꢉꢀꢁꢑ ꢊꢀꢃAꢒꢍꢓꢊ
ꢈ ꢋꢏꢔꢂꢑ ꢂꢌRꢁꢓꢊ ꢎꢁ
ꢈ ꢃꢃ ꢗꢆ.ꢟꢘA ꢋꢌꢍꢍ ꢌꢋ
ꢈ ꢃꢏꢀꢂꢐꢉꢀꢁꢑ ꢊꢀꢃAꢒꢍꢓꢊ
ꢈ ꢋꢏꢔꢂꢑ ꢂꢌRꢁꢓꢊ ꢎꢕꢕ
ꢈ ꢁꢎ ꢎꢋꢓꢁꢖꢃꢉꢎRꢂ ꢊꢓꢂꢓꢐꢂꢀꢎꢁ
ꢈ ꢁꢎ ꢎꢋꢓꢁꢖꢃꢉꢎRꢂ ꢊꢓꢂꢓꢐꢂꢀꢎꢁ
ꢏAꢀꢂ ꢗꢅꢘꢙ
ꢌꢋꢖRꢌꢁ
Start-Up and Fault Protection
Figure 8 shows the start-up and fault sequence for the
LT8393. During the POR state, the SS pin is hard pulled
down with a 100Ω to ground. In a pre-biased condition,
the SS pin has to be pulled below 0.2V to enter the INIT
state, where the LT8393 wait 10µs so that the SS pin can
be fully discharged to ground. After the 10µs, the LT8393
ꢎꢡꢖRꢌꢁ
ꢈ ꢃꢃ ꢗꢆ.ꢟꢘA ꢋꢌꢍꢍ ꢌꢋ
ꢈ ꢃꢃ ꢗꢆ.ꢟꢘA ꢋꢌꢍꢍ ꢌꢋ
ꢈ ꢃꢏꢀꢂꢐꢉꢀꢁꢑ ꢓꢁAꢒꢍꢓꢊ
ꢈ ꢋꢏꢔꢂꢑ ꢂꢌRꢁꢓꢊ ꢎꢁ
ꢈ ꢁꢎ ꢎꢋꢓꢁꢖꢃꢉꢎRꢂ ꢊꢓꢂꢓꢐꢂꢀꢎꢁ
ꢈ ꢃꢏꢀꢂꢐꢉꢀꢁꢑ ꢓꢁAꢒꢍꢓꢊ
ꢈ ꢋꢏꢔꢂꢑ ꢂꢌRꢁꢓꢊ ꢎꢁ
ꢈ ꢎꢋꢓꢁꢖꢃꢉꢎRꢂ ꢊꢓꢂꢓꢐꢂꢀꢎꢁ
ꢃꢃ ꢄ ꢅ.ꢆꢇ Aꢁꢊ
ꢎꢋꢓꢁ ꢍꢓꢊ ꢎR
ꢃꢉꢎRꢂ ꢍꢓꢊ
ꢋꢏꢔ ꢚ ꢉꢀ
ꢎꢁ
ꢊꢎꢏꢁꢖꢃꢂꢎꢋ
ꢕAꢌꢍꢂꢖRꢌꢁ
enters the UP/PRE state when the PWM signal goes
ON
ꢈ ꢃꢃ ꢗ.ꢆꢟꢘA ꢋꢌꢍꢍ ꢊꢎꢏꢁ
ꢈ ꢃꢏꢀꢂꢐꢉꢀꢁꢑ ꢊꢀꢃAꢒꢍꢓꢊ
ꢈ ꢋꢏꢔꢂꢑ ꢂꢌRꢁꢓꢊ ꢎꢁ
ꢈ ꢃꢃ ꢗ.ꢆꢟꢘA ꢋꢌꢍꢍ ꢊꢎꢏꢁ
ꢈ ꢃꢏꢀꢂꢐꢉꢀꢁꢑ ꢓꢁAꢒꢍꢓꢊ
ꢈ ꢋꢏꢔꢂꢑ ꢂꢌRꢁꢓꢊ ꢎꢁ
ꢈ ꢎꢋꢓꢁꢖꢃꢉꢎRꢂ ꢊꢓꢂꢓꢐꢂꢀꢎꢁ
high. The PWM high signal happens when CTRL pin
ON
is above its rising dim-off threshold (0.228V typical) and
ꢈ ꢁꢎ ꢎꢋꢓꢁꢖꢃꢉꢎRꢂ ꢊꢓꢂꢓꢐꢂꢀꢎꢁ
the external or internal PWM dimming is on.
ꢛꢜꢝꢜ ꢂAꢅꢛ
During the UP/PRE state, the SS pin is charged up by a
12.5µA pull-up current while the switching is disabled
and the PMWTG is turned off. Once the SS pin is charged
above 0.25V, the LT8393 enters the UP/TRY state, where
the PMWTG is turned on first while the switching is still
disabled. This is to check for an output overvoltage con-
Figure 8. Start-Up and Fault Sequence
Rev. A
17
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LT8393
OPERATION
During the UP/RUN state, the switching is enabled and
the start-up of the output voltage V
RUN state, where a 1.25µA pull-down current slowly dis-
charges the SS pin with the other conditions the same as
the OK/RUN state. Once the SS pin is discharged below
1.7V, the LT8393 enters the DOWN/STOP state, where
the switching is disabled and the LED fault detection is
deactivated with the previous fault latched. Once the SS
is controlled by
OUT
the voltage on the SS pin. When the SS pin voltage is less
than 1V, the LT8393 regulates the FB pin voltage to the
SS pin voltage instead of the 1V reference. This allows the
SS pin to be used to program soft-start by connecting an
external capacitor from the SS pin to GND. The internal
12.5µA pull-up current charges up the capacitor, creating
a voltage ramp on the SS pin. As the SS pin voltage rises
linearly from 0.25V to 1V (and beyond), the output voltage
pin is discharged below 0.2V and the PWM signal is still
ON
high, the LT8393 goes back to the UP/RUN state.
In an open or short LED condition, the LT8393 can be set
tohiccup,latch-off,orkeep-runningfaultprotectionmode
V
OUT
rises smoothly to its final LED string voltage.
with a resistor between the SS and V pins. Without any
REF
Once the SS pin is charged above 1.75V, the LT8393
enters the OK/RUN state, where the LED fault (both open
LED and short LED) detection is activated. The open LED
resistor, the LT8393 will hiccup with SS pin between 0.2V
and 1.75V and go around the UP/RUN, OK/RUN, FAULT/
RUN, and DOWN/STOP states until the fault condition is
cleared.Witha499kresistor,theLT8393willlatchoffuntil
the EN/UVLO is toggled. With a 100k resistor, the LT8393
will keep running regardless of the fault.
fault means that V > 0.95V and V
< 10mV, and
FB
(ISP-ISN)
the short LED fault means that V < 0.25V. Both the open
FB
LED and short LED faults are combined to the FAULT pin.
When either fault happens, the LT8393 enters the FAULT/
APPLICATIONS INFORMATION
The front page shows a typical LT8393 application circuit.
ThisApplicationsInformationsectionservesasaguideline
of selecting external components for typical applications.
The examples and equations in this section assume
continuous conduction mode unless otherwise specified.
Switching Frequency Setting
The switching frequency of the LT8393 can be set by the
internal oscillator. With the SYNC/SPRD pin pulled to
ground, the switching frequency is set by a resistor from
the RT pin to ground. Table 1 shows R resistor values
for common switching frequencies.
T
Switching Frequency Selection
Table 1. Switching Frequency vs RT Value (1% Resistor)
The LT8393 uses a constant frequency control scheme
between 350kHz and 2MHz. Selection of the switching
frequency is a tradeoff between efficiency and component
size. Low frequency operation improves efficiency by
reducing MOSFET switching losses, but requires larger
inductor and capacitor values. For high power applica-
tions, consideroperatingatlowerfrequenciestominimize
MOSFET heating from switching losses. For low power
applications, consider operating at higher frequencies to
minimize the total solution size.
f
(MHz)
R (k)
T
OSC
0.4
374
237
169
130
102
84.5
71.5
60.4
51.1
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Inaddition,thespecificapplicationalsoplaysanimportant
role in switching frequency selection. In a noise-sensitive
system,theswitchingfrequencyisusuallyselectedtokeep
the switching noise out of a sensitive frequency band.
Rev. A
18
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LT8393
APPLICATIONS INFORMATION
Spread Spectrum Frequency Modulation
edge of the synchronization clock represents the begin-
ning of a switching cycle, turning on switches A and C,
or switches A and D.
Switching regulators can be particularly troublesome for
applications where electromagnetic interference (EMI) is
a concern. To improve the EMI performance, the LT8393
implementsatrianglespreadspectrumfrequencymodula-
Inductor Selection
The switching frequency and inductor selection are inter-
relatedinthathigherswitchingfrequenciesallowtheuseof
smaller inductor and capacitor values. The inductor value
has a direct effect on ripple current. The highest current
tion scheme. With the SYNC/SPRD pin tied to INTV , the
CC
LT8393startstospreaditsswitchingfrequency25%above
the internal oscillator frequency. Figure 9 and Figure 10
show the noise spectrum comparison of the front page
application with spread spectrum enabled.
ripple∆I %happensinthebuckregionatV
,andthe
L
IN(MAX)
lowest current ripple ∆I % happens in the boost region at
L
ꢌꢍ
V
. For any given ripple allowance set by customers,
IN(MIN)
ꢠꢠꢀꢈ ꢕꢄ ꢢꢘꢗꢉ ꢀꢘꢡꢗꢁR
ꢄꢕꢘꢠꢁ ꢀꢡꢕꢕR
ꢅꢡAꢠꢠ ꢐ ꢡꢘꢈꢘꢗꢠ
ꢏꢍ
the minimum inductance can be calculated as:
ꢎꢍ
ꢐꢍ
ꢑꢍ
VOUT•(VIN(MAX)− VOUT
)
LBUCK
>
ꢒꢍ
f•ILED(MAX)•ΔIL %•V
IN(MAX)
ꢜꢍ
ꢝꢍ
V
2•(VOUT− V
)
2
ꢍ
IN(MIN)
IN(MIN)
LBOOST
>
ꢞꢝꢍ
ꢞꢜꢍ
f•ILED(MAX)•ΔIL %•VOUT
ꢍ.ꢝ
ꢝ
ꢝꢍ
ꢝꢍꢍ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ
ꢌꢒꢟꢒ ꢀꢍꢟ
where:
f is switching frequency
∆I % is allowable inductor current ripple
Figure 9. CISPR 25 Average Conducted EMI
ꢌꢍ
L
ꢡꢡꢀꢈ ꢔꢄ ꢣꢗꢖꢉ ꢀꢗꢢꢖꢁR
ꢄꢔꢗꢡꢁ ꢀꢢꢔꢔR
ꢅꢢAꢡꢡ ꢐ ꢢꢗꢈꢗꢖꢡ
ꢎꢍ
ꢏꢍ
V
V
V
is minimum input voltage
is maximum input voltage
IN(MIN)
IN(MAX)
ꢐꢍ
ꢑꢍ
ꢜꢍ
is output voltage
ꢝꢍ
OUT
ꢞꢍ
I
is maximum LED current
LED(MAX)
ꢍ
ꢟꢞꢍ
ꢟꢝꢍ
Slope compensation provides stability in constant fre-
quency current mode control by preventing subharmonic
oscillationsatcertaindutycycles.Theminimuminductance
required for stability can be calculated as:
ꢍ.ꢞ
ꢞ
ꢞꢍ
ꢞꢍꢍ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ
ꢌꢜꢠꢜ ꢀꢞꢍ
Figure 10. CISPR 25 Peak Conducted EMI
Frequency Synchronization
10•VOUT•RSENSE
L >
f
The LT8393 switching frequency can be synchronized to
an external clock using the SYNC/SPRD pin. Driving the
SYNC/SPRD with a 50% duty cycle waveform is always a
good choice, otherwise maintain the duty cycle between
10%and90%.Duetotheuseofaphase-lockedloop(PLL)
inside, there is no restriction between the synchronization
frequency and the internal oscillator frequency. The rising
For high efficiency, choose an inductor with low core
loss, such as ferrite. Also, the inductor should have low
DC resistance to reduce the I R losses, and must be able
to handle the peak inductor current without saturating. To
minimize radiated noise, use a shielded inductor.
2
Rev. A
19
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LT8393
APPLICATIONS INFORMATION
R
SENSE
Selection and Maximum Output Current
Power MOSFET Selection
R
is chosen based on the required output current.
TheLT8393requiresfourexternalN-channelpowerMOS-
FETs, two for the top switches (switches A and D shown
in Figure 1) and two for the bottom switches (switches B
and C shown in Figure 1). Important parameters for the
SENSE
The duty cycle independent maximum current sense
thresholds (50mV in peak-buck and 50mV in peak-boost)
set the maximum inductor peak current in buck region,
buck-boost region, and boost region.
power MOSFETs are the breakdown voltage V
,
BR(DSS)
, reverse
threshold voltage V
, on-resistance R
GS(TH)
transfercapacitanceC
DS(ON)
andmaximumcurrentI
Inboostregion,thelowestmaximumaverageloadcurrent
happens at V
.
RSS
DS(MAX)
and can be calculated as:
IN(MIN)
To achieve high frequency operation, the power MOSFET
selection is critical. With typical 60ns shoot-through
protection dead time, high performance power MOSFETs
ΔIL(BOOST)
V
⎛
⎞
50mV
IN(MIN)
IOUT(MAX_BOOST)
=
−
•
⎜
⎟
R
2
VOUT
⎝
⎠
SENSE
with low Q and low R
must be used.
g
DS(ON)
where ∆I
is peak-to-peak inductor ripple current
in boost region and can be calculated as:
L(BOOST)
Sincethegatedrivevoltageissetbythe5VINTV supply,
CC
logic-level threshold MOSFETs must be used in LT8393
V
IN(MIN)•(V − V
)
IN(MIN)
OUT
applications.SwitchingfourMOSFETsathigherfrequency,
ΔIL(BOOST)
=
f•L•VOUT
the substantial gate charge current from INTV can be
CC
estimated as:
In buck region, the lowest maximum average load current
happens at V and can be calculated as:
IN(MAX)
I
= f • QgA +QgB +Q +QgD
INTVCC
gC
ΔIL(BUCK)
⎛
⎞
50mV
R
IOUT(MAX_BUCK)
=
−
where:
f is the switching frequency
Q ,Q ,Q ,Q arethetotalgatechargesofMOSFETs
⎜
⎟
2
⎝
⎠
SENSE
where ∆I
is peak-to-peak inductor ripple current in
buck region and can be calculated as:
L(BUCK)
gA gB gC gD
A, B, C, D at 5V V
GS
VOUT•(VIN(MAX)− VOUT
)
ΔIL(BUCK)
=
Make sure the total required INTV current not exceeding
CC
f•L•V
IN(MAX)
the INTV current limit in the data sheet.
CC
The maximum current sense R
in boost region is:
SENSE
The LT8393 uses the V /V
ratio to transition between
IN OUT
modes and regions. Bigger IR drop in the power path
caused by improper MOSFET and inductor selection may
prevent the LT8393 from smooth transition. Make sure
RSENSE(BOOST)
=
2•50mV•V
IN(MIN)
that low R
MOSFETs and low DCR inductor are
2•ILED(MAX)•VOUT+ ΔIL(BOOST)•V
DS(ON)
IN(MIN)
used to satisfy:
ILED(MAX)
where:
The maximum current sense R
in buck region is
SENSE
0.025 • VOUT
RA,B+RC,D+RSENSE+RL
≤
2•50mV
2•ILED(MAX)+ ΔIL(BUCK)
RSENSE(BUCK)
=
The final R
SENSE
margin is usually recommended.
value should be lower than the calculated
SENSE
R
A,B
R
C,D
is the maximum R
is the maximum R
of MOSFETs A or B at 25°C
of MOSFETs C or D at 25°C
DS(ON)
R
in both buck and boost regions. A 20% to 30%
DS(ON)
R is the maximum DCR resistor of inductor at 25°C
L
Rev. A
20
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LT8393
APPLICATIONS INFORMATION
The R
and DCR increase at higher junction tem-
where C
is usually specified by the MOSFET manufac-
DS(ON)
RSS
peratures and the process variation have been included
turers. The constant k, which accounts for the loss caused
by reverse recovery current, is inversely proportional to
the gate drive current and has an empirical value of 1.7.
in the calculation above.
In order to select the power MOSFETs, the power dis-
sipated by the device must be known. For switch A, the
maximumpowerdissipationhappensinboostregion,when
it remains on all the time. Its maximum power dissipation
at maximum output current is given by:
For switch D, the maximum power dissipation happens in
boost region, when its duty cycle is higher than 50%. Its
maximum power dissipation at maximum output current
is given by:
2
V
V
PD(BOOST)
=
OUT •ILED(MAX)2•ρ •RDS(ON)
⎛
⎜
⎝
⎞
⎟
⎠
I
LED(MAX)•VOUT
T
PA(BOOST)
=
•ρT •RDS(ON)
IN
V
IN
For the same output voltage and current, typically switch
A has the highest power dissipation in buck region at
where ρ is a normalization factor (unity at 25°C) ac-
T
counting for the significant variation in on-resistance with
temperature, typically 0.4%/°C as shown in Figure 11. For
a maximum junction temperature of 125°C, using a value
V
and switch C has the highest power dissipation
IN(MAX)
in boost region at V
.
IN(MIN)
From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
formula:
of ρ = 1.5 is reasonable.
T
2.0
1.5
1.0
0.5
0
T = T + P • R
TH(JA)
J
A
The junction-to-ambient thermal resistance R
in-
TH(JC)
. This
TH(JA)
cludes the junction-to-case thermal resistance R
and the case-to-ambient thermal resistance R
TH(CA)
value of T can then be compared to the original, assumed
J
value used in the iterative calculation process.
–50
50
100
150
0
JUNCTION TEMPERATURE (°C)
8393 F11
Optional Schottky Diode (D , D ) Selection
B
D
Figure 11. Normalized RDS(ON) vs Temperature
The optional Schottky diodes D (in parallel with switch B)
B
and D (in parallel with switch D) conduct during the
D
Switch B operates in buck region as the synchronous
rectifier. Its power dissipation at maximum output cur-
rent is given by:
dead time between the conduction of the power MOSFET
switches. They are intended to prevent the body diode of
synchronousswitchesBandDfromturningonandstoring
V −V
OUT •ILED(MAX)2•ρT •RDS(ON)
B
IN
charge during the dead time. In particular, D significantly
PB(BUCK)
=
V
reduces reverse recovery current between switch B turn-
IN
off and switch A turn-on, and D significantly reduces
D
Switch C operates in boost region as the control switch.
Its power dissipation at maximum current is given by:
reverse recovery current between switch D turn-off and
switch C turn-on. They improve converter efficiency and
reduce switch voltage stress. In order for the diode to be
effective, the inductance between it and the synchronous
switch must be as small as possible, mandating that these
components be placed adjacently.
(VOUT−V )•V
IN
PC(BOOST)
=
OUT •ILED(MAX)2•ρT
2
V
IN
ILED(MAX)
3
•RDS(ON)+k•VOUT
•
•CRSS•f
V
IN
Rev. A
21
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LT8393
APPLICATIONS INFORMATION
C and C
Selection
output ripple voltage. The maximum steady state ripple
due to charging and discharging the bulk capacitance is
given by:
IN
OUT
Input and output capacitance is necessary to suppress
voltage ripple caused by discontinuous current moving
in and out the regulator. A parallel combination of capaci-
tors is typically used to achieve high capacitance and low
equivalent series resistance (ESR). Dry tantalum, special
polymer,aluminumelectrolyticandceramiccapacitorsare
all available in surface mount packages. Capacitors with
low ESR and high ripple current ratings, such as OS-CON
and POSCAP are also available.
I
LED•(V − V
)
IN(MIN)
OUT
Δ VCAP(BOOST)
=
C
OUT•VOUT•f
⎛
⎞
VOUT
V
OUT • ⎜1–
⎟
V
⎝
⎠
IN(MAX)
ΔVCAP(BUCK)
=
8 •L • f2 •COUT
Ceramic capacitors should be placed near the regulator
input and output to suppress high frequency switching
spikes. Ceramic capacitors, of at least 1µF, should also
Themaximumsteadyrippleduetothevoltagedropacross
the ESR is given by:
be placed from V to GND and V
to GND as close to
IN
OUT
VOUT•ILED(MAX)
Δ VESR(BOOST)
=
•ESR
the LT8393 pins as possible. Due to their excellent low
ESR characteristics, ceramic capacitors can significantly
reduce input ripple voltage and help reduce power loss in
the higher ESR bulk capacitors. X5R or X7R dielectrics are
preferred, as these materials retain their capacitance over
wide voltage and temperature ranges. Many ceramic ca-
pacitors,particularly0805or0603casesizes,havegreatly
reduced capacitance at the desired operating voltage.
V
IN(MIN)
⎛
⎞
VOUT
V
OUT • ⎜1–
⎟
V
⎝
⎠
IN(MAX)
ΔV
=
•ESR
ESR(BUCK)
L • f
INTV Regulator
CC
Input Capacitance C
An internal P-channel low dropout regulator produces
5V at the INTV pin from the V supply pin. The INTV
CC
IN
CC
IN
Discontinuous input current is highest in buck region due
to the switch A toggling on and off. Make sure that the
powers internal circuitry and gate drivers in the LT8393.
The INTV regulator can supply a peak current of 145mA
CC
C capacitor network has low enough ESR and is sized
IN
and must be bypassed to ground with a minimum of
4.7µF ceramic capacitor. Good local bypass is necessary
to supply the high transient current required by MOSFET
gate drivers.
to handle the maximum RMS current. In buck region, the
input RMS current is given by:
VOUT
V
V
IN
VOUT
IRMS ≈ILED(MAX)
The formula has a maximum at V = 2V , where I
RMS
•
•
−1
IN
Higher input voltage applications with large MOSFETs
being driven at higher switching frequencies may cause
the maximum junction temperature rating for the LT8393
to be exceeded. The system supply current is normally
dominated by the gate charge current. Additional external
IN
OUT
= I /2. This simple worst-case condition is com-
LED(MAX)
monlyusedfordesignbecauseevensignificantdeviations
do not offer much relief.
loading of the INTV also needs to be taken into account
CC
for the power dissipation calculation. The total LT8393
Output Capacitance C
OUT
power dissipation in this case is V • I
, and overall
IN INTVCC
Discontinuous current shifts from the input to the output
in the boost region. Make sure that the C capacitor
efficiency is lowered. The junction temperature can be
estimated by using the equation:
OUT
network is capable of reducing the output voltage ripple.
The effects of ESR and the bulk capacitance must be
considered when choosing the right capacitor for a given
T = T + P • θ
JA
J
A
D
where θ (in °C/W) is the package thermal resistance.
JA
Rev. A
22
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LT8393
APPLICATIONS INFORMATION
ꢋ
ꢒꢆ
To prevent maximum junction temperature from being
exceeded, the input supply current must be checked op-
Rꢍ
Rꢔ
erating in continuous mode at maximum V .
IN
ꢈꢆꢉꢊꢋꢀꢌ
ꢀUꢁꢉꢎꢁꢌꢏ
Top Gate MOSFET Driver Supply (C
, C
BST1 BST2
)
ꢐꢌꢆꢁRꢌꢀ
ꢀꢁꢂꢃꢄꢃ
ꢑꢌꢏꢁꢒꢌꢆAꢀꢓ
The top MOSFET drivers, TG1and TG2, are driven between
their respective SW and BST pin voltages. The boost volt-
ꢅꢆꢇ
ꢂꢃꢄꢃ ꢕꢍꢔ
ages are biased from floating bootstrap capacitors C
BST1
Figure 12. VIN Undervoltage Lockout (UVLO)
and C
, which are normally recharged through both the
BST2
external and internal bootstrap diodes when the respec-
tive top MOSFET is turned off. External bootstrap diode is
required (no internal bootstrap diode) for boost side and
optional for buck side. External bootstrap diodes are rec-
ommended because the internal bootstrap diodes are not
always strong enough to refresh top MOSFETs at 2MHz.
Both capacitors are charged to the same voltage as the
by the ISP and ISN pins. The CTRL pin should be tied to
a voltage higher than 1.35V to get the full-scale 100mV
(typical) threshold across the sense resistor. The CTRL
pin can be used to dim the LED current to zero, although
relative accuracy decreases with the decreasing sense
threshold. When the CTRL pin voltage is less than 1.15V,
the LED current is:
INTV voltage. ThebootstrapcapacitorsC
andC
,
CC
BST1
BST2
V
CTRL−250mV
10•RLED
need to store about 100 times the gate charge required by
the top switches A and D. In most applications, a 0.1µF to
0.47µF, X5R or X7R dielectric capacitor is adequate.
ILED
=
where V
is the CTRL pin voltage. When V
is be-
CTRL
CTRL
Programming V UVLO
tween 1.15V and 1.35V, the LED current varies with the
IN
V
, but departs from the equation above by an increas-
CTRL
ing amount as V
AresistordividerfromV totheEN/UVLOpinimplements
IN
increases. Ultimately, when V
>
CTRL
CTRL
V
IN
undervoltage lockout (UVLO). The EN/UVLO enable
1.35V, the LED current no longer varies. The typical V
CTRL
falling threshold is set at 1.220V with 10mV hysteresis. In
addition, the EN/UVLO pin sinks 2.5µA when the voltage
on the pin is below 1.220V. This current provides user
programmable hysteresis based on the value of R1. The
programmable UVLO thresholds are:
threshold vs V
is listed in Table 2.
CTRL
Table 2. V(ISP-ISN) Threshold vs VCTRL
V
(V)
V
(mV)
(ISP-ISN)
CTRL
1.15
90
1.20
1.25
1.30
1.35
94.5
98
R1+R2
V
IN(UVLO+) =1.233V•
+2.5µA•R1
R2
99.5
100
R1+R2
VIN(UVLO−) =1.220V•
R2
When V
is higher than 1.35V, the LED current is
CTRL
regulated to:
Figure12showstheimplementationofexternalshut-down
control while still using the UVLO function. The NMOS
grounds the EN/UVLO pin when turned on, and puts the
LT8393inshutdownwithquiescentcurrentlessthan2µA.
100mV
RLED
ILED
=
The CTRL pin should not be left open (tie to V
if not
REF
Programming LED Current
used). The CTRL pin can also be used in conjunction with
athermistortoprovideovertemperatureprotectionforthe
The LED current is programmed by placing an appropriate
LED load, or with a resistor divider to V to reduce output
value current sense resistor, R , in series with the LED
IN
LED
string. The voltage drop across R
is (Kelvin) sensed
LED
Rev. A
23
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LT8393
APPLICATIONS INFORMATION
powerandswitchingcurrentwhenV islow.Thepresence
and PWM signals must have synchronized rising edges to
achieve flicker-free PWM dimming performance.
IN
of a time varying differential voltage ripple signal across
ISP and ISN at the switching frequency is expected. The
amplitude of this signal is increased by higher LED load
current,lowerswitchingfrequency,orsmallervalueoutput
filter capacitor. Some level of ripple signal is acceptable,
The LT8393 provides both external PWM dimming and
internalPWMdimming.ForexternalPWMdimming,choose
R resistor less than 30k and apply external PWM clock
P
signalonthePWMpin.ForinternalPWMdimming,choose
and the compensation capacitor on the V pin filters the
C
R resistor to one of the five resistor values in Table 3 and
P
signal so the average difference between ISP and ISN is
regulated to the user-programmed value. The ripple volt-
age amplitude (peak-to-peak) in excess of 20mV should
not cause mis-operation, but may lead to noticeable offset
betweentheaveragevalueandtheuser-programmedvalue.
apply analog DC voltage or a resistor divider from V
REF
to the PWM pin. The R resistor sets the internal PWM
P
dimming frequency, and the analog DC voltage on the
PWM pin from 1V to 2V sets the internal PWM dimming
duty ratio from 0% to 100% with a discrete 1/128 step
size in Figure 13. A 1µF ceramic capacitor on the PWM pin
is recommended to minimize the internal PWM dimming
duty ratio jitter caused by switching noise.
Dimming Control
There are two methods to control the LED current for dim-
ming using the LT8393. One method uses the CTRL pin to
adjust the current regulated in the LEDs. A second method
uses the PWM pin to modulate the LED current between
zero and full current to achieve a precisely programmed
average current.
Table 3. Internal PWM Dimming Frequency vs RP Value
(5% Resistor)
5% R (kΩ) <30
51
82
130
200
300
P
f
SW
External f /1024 f /2048 f /4096 f /8192 f /16384
SW
SW
SW
SW
SW
f
f
= 2MHz External 1953Hz 977Hz 488Hz 244Hz
122Hz
SW
Compared to the analog dimming method, the PWM dim-
ming method offers much higher dimming ratio without
anycolorshift.TomakePWMdimmingmoreaccurate,the
= 1MHz External 977Hz
488Hz 244Hz 122Hz
195Hz 98Hz 49Hz
61Hz
24Hz
SW
f
= 400kHz External 391Hz
SW
switch demand current is stored on the V node when the
C
PWM signal is low. This feature minimizes recovery time
when the PWM signal goes high. To further improve the
recovery time, a high side PMOS PWM switch should be
used in the LED current path to prevent the output capaci-
tor from discharging during the PWM signal low phase.
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ꢖꢓꢓ
AꢍꢁAꢇꢎ
ꢉꢏ
ꢀꢁꢂꢃꢄ ꢅꢆꢃꢇ
RAꢃꢈꢉ ꢊꢋꢌ
ꢘꢓ
ꢓ
AꢍꢁAꢇꢎ
ꢉꢐꢐ
The choice of switching frequency, inductor value, and
loop compensation affects the minimum PWM on time,
below which the LT8393 loses the LED current regulation.
For the same application, the LT8393 achieves the highest
PWM dimming ratio (up to 2000:1) in buck region, the
mediumPWMdimmingratio(upto2000:1)inbuck-boost
region, and the lowest PWM dimming ratio (up to 1000:1)
in boost region.
ꢓ.ꢓ
ꢓ.ꢘ
ꢖ.ꢓ
ꢖ.ꢘ
ꢗ.ꢓ
ꢗ.ꢘ
ꢒ.ꢓ
ꢀꢁꢂ ꢊꢑꢌ
ꢔꢒꢕꢒ ꢐꢖꢒ
Figure 13. Internal PWM Dimming Duty Ratio vs PWM Voltage
High Side PMOS PWM Switch Selection
A high side PMOS PWM switch is recommended in most
LT8393 applications to maximize the PWM dimming
ratio and protect the LED string during fault conditions.
Compared to a low side NMOS PWM switch, the high side
PMOS PWM switch allows a single wire to the LED string
and ground return path through chassis. The high side
PMOS PWM switch is typically selected for drain-source
In either fixed frequency operation set by R resistor or
T
spreadspectrumfrequencyoperation,theinternaloscillator
is synchronized to the PWM signal rising edge, thereby
providing flicker-free PWM dimming performance. In
external frequency synchronization operation, both SYNC
Rev. A
24
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LT8393
APPLICATIONS INFORMATION
voltage V , gate-source threshold voltage V
, and
FAULT Pin
DS
GS(TH)
continuous drain current I . For proper operations, V
D
DS
The LT8393 provides an open-drain status pin, FAULT,
which is pulled low during either open LED or short LED
conditions. The open LED condition happens when the FB
rating should exceed the open LED regulation voltage set
by the FB pin, the absolute value of V should be less
GS(TH)
than 5V, and I rating should be above I
.
D
LED(MAX)
pin is above 0.95V and the voltage across V
is less
(ISP-ISN)
than 10mV. The short LED condition happens when the
FB pin is below 0.25V. The FAULT status is updated when
the SS pin is above 1.75V and the PWM signal is high.
Programming Output Voltage and Thresholds
The LT8393 has a voltage feedback pin FB that can be
used to program a constant-voltage output. The output
voltage can be set by selecting the values of R3 and R4
(Figure 14) according to the following equation:
Soft-Start and Fault Protection
As shown in and explained in the Operation section, the
SS pin can be used to program soft-start by connecting an
external capacitor from the SS pin to ground. The internal
12.5µA pull-up current charges up the capacitor, creat-
ing a voltage ramp on the SS pin. As the SS pin voltage
rises linearly from 0.25V to 1V (and beyond), the output
voltage rises smoothly and transitions into LED current
regulation. Thesoft-startrangeisdefinedtobethevoltage
range from 0V to the FB voltage in LED current regulation.
The soft-start time can be calculated as:
R3+R4
VOUT =1.00V•
R4
Inaddition, theFBpinalsosetsoutputovervoltagethresh-
old, open LED threshold, and short LED threshold. For an
ꢅ
ꢆꢇꢁ
Rꢃ
ꢀꢁꢂꢃꢄꢃ
ꢉꢋ
Rꢈ
R4
CSS
ꢂꢃꢄꢃ ꢉꢊꢈ
tSS = VLED
•
•
R3+R4 12.5µA
Figure 14. Feedback Resistor Connection
LED driver application with small output capacitors, the
output voltage usually overshoots a lot during an open
LED event. Although the 1.00V FB regulation loop tries to
regulate the output, the loop is usually too slow to prevent
the output from overshooting. Once the FB pin hits its
overvoltage threshold 1.05V, the LT8393 stops switching
by turning off TG1, BG1, TG2, and BG2, and also turns off
PWMTG to disconnect the LED string for protection. The
output overvoltage threshold can be set as:
Make sure the C is at least five to ten times larger than
SS
the compensation capacitor on the V pin. A 22nF ceramic
C
capacitor is a good starting point.
The SS pin is also used as a fault timer. Once an open
LED or a short LED fault is detected, a 1.25µA pull-down
current source is activated. Using a single resistor from
the SS pin to the V pin, the LT8393 can be set to three
REF
different fault protection modes: hiccup (no resistor),
latch-off (499k), and keep-running (100k).
R3+R4
VOUT(OVP) =1.05V•
With a 100k resistor in keep-running mode, the LT8393
continues switching normally, either regulating the pro-
R4
grammed V
during open LED fault or regulating the
OUT
MakesuretheexpectedV duringnormaloperationstays
FB
current during short LED fault. With a 499k resistor in
latch-off mode, the LT8393 stops switching until the EN/
UVLOpinispulledlowandhightorestart. Withnoresistor
inhiccupmode,theLT8393enterslowdutycycleauto-retry
operation. The 1.25µA pull-down current discharges the
SS pin to 0.2V and then 12.5µA pull-up current charges
the SS pin up. If the fault condition has not been removed
between the short LED rising threshold 0.3V and the open
LED falling threshold 0.9V:
R4
R3+R4
0.3V ≤ VLED
•
≤0.9V
These equations set the maximum LED string voltage
with full open LED protection for the LT8393 to be 51V.
Rev. A
25
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LT8393
APPLICATIONS INFORMATION
when the SS pin reaches 1.75V, the 1.25µA pull-down
current turns on again, initiating a new hiccup cycle. This
will continue until the fault is removed.
4. C and C
loss. The input capacitor has the dif-
OUT
IN
ficult job of filtering the large RMS input current to the
regulator in buck region. The output capacitor has the
difficult job of filtering the large RMS output current in
Loop Compensation
boost region. Both C and C
are required to have
IN
OUT
2
low ESR to minimize the AC I R loss and sufficient
capacitance to prevent the RMS current from causing
additional upstream losses in fuses or batteries.
The LT8393 uses an internal transconductance error am-
plifier, the output of which, V , compensates the control
C
loop. The external inductor, output capacitor, and the
compensation resistor and capacitor determine the loop
stability.
5. Other losses. Schottky diode D and D are respon-
B
D
sible for conduction losses during dead time and light
load conduction periods. Inductor core loss occurs
predominately at light loads. Switch A causes reverse
recovery current loss in buck region, and switch C
causes reverse recovery current loss in boost region.
The inductor and output capacitor are chosen based on
performance, size and cost. The compensation resistor
and capacitor on the V pin are set to optimize control
C
loop response and stability. For a typical LED application,
a 3.3nF to 22nF compensation capacitor on the V pin is
Whenmakingadjustmentstoimproveefficiency,theinput
current is the best indicator of changes in efficiency. If you
make a change and the input current decreases, then the
efficiency has increased. If there is no change in the input
current, then there is no change in efficiency.
C
adequate, and a series resistor should always be used to
increase the slew rate on the V pin to maintain tighter
C
regulation of LED current during fast transients on the
input supply of the converter.
Efficiency Considerations
PC Board Layout Checklist
The power efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Although all dissipative
elements in circuits produce losses, four main sources
account for most of the losses in LT8393 circuits:
The basic PC board layout requires a dedicated ground
plane layer. Also, for high current, a multilayer board
provides heat sinking for power components.
n
The ground plane layer should not have any traces
and it should be as close as possible to the layer with
power MOSFETs.
n
Place C , switch A, switch B and D in one com-
IN
B
2
1. DC I R losses. These arise from the resistances of
pact area. Place C , switch C, switch D and D in
OUT
D
the MOSFETs, sensing resistor, inductor and PC board
traces and cause the efficiency to drop at high output
currents.
one compact area.
n
Use immediate vias to connect the components to
the ground plane. Use several large vias for each
power component.
2.Transitionloss.Thislossarisesfromthebriefamount
of time switch A or switch C spends in the saturated
region during switch node transitions. It depends upon
the input voltage, load current, driver strength and
MOSFET capacitance, among other factors.
n
n
Use planes for V and V
to maintain good voltage
IN
OUT
filtering and to keep power losses low.
Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise
of power components. Connect the copper areas to
3. INTV current. ThisisthesumoftheMOSFETdriver
CC
any DC net (V or GND).
IN
and control currents.
Rev. A
26
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LT8393
APPLICATIONS INFORMATION
n
n
n
Separate the signal and power grounds. All small-
Connect the input capacitors C and output capaci-
IN
signal components should return to the exposed
GND pad from the bottom, which is then tied to the
power GND close to the sources of switch B and
switch C.
tors C
closely to the power MOSFETs. These
OUT
capacitors carry the MOSFET AC current.
Route LSP and LSN traces together with minimum
PCB trace spacing. Avoid sense lines pass through
noisy areas, such as switch nodes. The filter capaci-
tor between LSP and LSN should be as close as pos-
sible to the IC. Ensure accurate current sensing with
n
Place switch A and switch C as close to the control-
ler as possible, keeping the power GND, BG and SW
traces short.
n
Keep the high dV/dT SW1, SW2, BST1, BST2, TG1
Kelvin connections at the R
resistor. A low ESL
SENSE
and TG2 nodes away from sensitive small-signal
sense resistor is recommended.
n
nodes.
Connect the V pin compensation network close
C
n
The path formed by switch A, switch B, D and the
to the IC, between V and the signal ground. The
B
C
C capacitor should have short leads and PCB trace
capacitor helps to filter the effects of PCB noise and
output voltage ripple voltage from the compensation
loop.
IN
lengths. The path formed by switch C, switch D, D
D
and the C
capacitor also should have short leads
OUT
n
and PCB trace lengths.
Connect the INTV bypass capacitor, C
, close
CC
INTVCC
n
n
The output capacitor (–) terminals should be con-
to the IC, between the INTV and the power ground.
CC
nected as close as possible to the (–) terminals of the
input capacitor.
This capacitor carries the MOSFET drivers’ current
peaks.
Connect the top driver bootstrap capacitor C
BST1
closely to the BST1 and SW1 pins. Connect the top
driver bootstrap capacitor C
and SW2 pins.
closely to the BST2
BST2
Rev. A
27
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LT8393
TYPICAL APPLICATIONS
93% Efficient 350kHz 2.5V to 80V Buck-Boost LED Driver with Low EMI
ꢀꢁ
ꢀꢀꢁꢂ
ꢀꢁ
ꢀꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ
10mΩ
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3.3Ω
3.3Ω
3.3Ω
3.3Ω
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330mΩ
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ꢀꢁꢂꢃ
ꢀꢁ
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FAULT
FAULT
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ꢀ.ꢁꢂꢃ
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢈꢆRꢉA ꢊAꢋꢌꢍꢎꢏ
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100Hz 1000:1 External PWM
Dimming (VIN = 32V, fSW = 350kHz)
100Hz 1000:1 External PWM
Dimming (VIN = 16V, fSW = 350kHz)
100Hz 500:1 External PWM
Dimming (VIN = 8V, fSW = 350kHz)
A
A
A
A
A
A
A
A
A
OPEN LED Protection: Hiccup
Mode (RSS = Open)
OPEN LED Protection:
Latch-Off Mode (RSS = 499k)
OPEN LED Protection: Keep
Running Mode (RSS = 100k)
R
R
R
FAULT
FAULT
FAULT
A
A
A
A
A
A
e
Rev. A
28
For more information www.analog.com
LT8393
PACKAGE DESCRIPTION
FE Package
28-Lead Plastic TSSOP (4.4mm)
ꢀReꢁeꢂeꢃꢄe ꢅꢆꢇ ꢈꢉꢊ ꢋ ꢌꢍꢎꢌꢏꢎꢐꢑꢑꢒ Rev ꢅꢓ
Exposed Pad Variation EB
9.60 – 9.80*
(.378 – .386)
4.75
(.187)
4.75
(.187)
28 27 26 2524 23 22 21 20 1918 17 16 15
2.74
6.60 ±0.10
EXPOSED
PAD HEAT SINK
ON BOTTOM OF
PACKAGE
(.108)
4.50 ±0.10
SEE NOTE 4
6.40
2.74
(.252)
(.108)
BSC
0.45 ±0.05
1.05 ±0.10
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
5
7
1
2
3
4
6
8
9 10 12 13 14
11
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
FE28 (EB) TSSOP REV L 0117
0.195 – 0.30
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
2. DIMENSIONS ARE IN
FOR EXPOSED PAD ATTACHMENT
MILLIMETERS
(INCHES)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
3. DRAWING NOT TO SCALE
Rev. A
29
For more information www.analog.com
LT8393
PACKAGE DESCRIPTION
UFDM Package
28-Lead Plastic Side Wettable QFN (4mm × 5mm)
ꢃReꢨeꢩeꢪꢫe ꢓꢎꢒ ꢇꢐꢑ ꢬ ꢁꢊꢭꢁꢡꢭꢂꢟꢡꢄ Rev ꢧꢉ
ꢗꢆꢌ ꢂ ꢌꢍꢎꢒꢛ
R ꢤ ꢁ.ꢄꢁ ꢍR ꢁ.ꢕꢊ
× ꢀꢊ° ꢒꢛAꢔꢋꢈR
ꢄ.ꢊꢁ Rꢈꢋ
R ꢤ ꢁ.ꢂꢂꢊ
ꢎꢞꢗ
R ꢤ ꢁ.ꢁꢊ
ꢎꢞꢗ
ꢁ.ꢠꢊ ±ꢁ.ꢁꢊ
ꢀ.ꢁꢁ ±ꢁ.ꢂꢁ
ꢃꢄ ꢅꢆꢇꢈꢅꢉ
ꢄꢠ
ꢄꢡ
ꢁ.ꢀꢁ ±ꢁ.ꢂꢁ
ꢗꢆꢌ ꢂ
ꢎꢍꢗ ꢔARꢙ
ꢃꢌꢍꢎꢈ ꢟꢉ
ꢂ
ꢄ
ꢊ.ꢁꢁ ±ꢁ.ꢂꢁ
ꢃꢄ ꢅꢆꢇꢈꢅꢉ
ꢕ.ꢊꢁ Rꢈꢋ
ꢕ.ꢟꢊ ±ꢁ.ꢂꢁ
ꢄ.ꢟꢊ ±ꢁ.ꢂꢁ
ꢇꢈꢎAꢆꢓ A
ꢃꢚꢋꢇꢔꢄꢡꢉ ꢦꢋꢌ ꢂꢄꢂꢡ Rꢈꢢ ꢧ
ꢁ.ꢄꢊ ±ꢁ.ꢁꢊ
ꢁ.ꢄꢁꢁ Rꢈꢋ
ꢁ.ꢊꢁ ꢘꢅꢒ
ꢁ.ꢁꢁ ꢥ ꢁ.ꢁꢊ
ꢘꢍꢎꢎꢍꢔ ꢢꢆꢈꢐꢣꢈꢖꢗꢍꢅꢈꢇ ꢗAꢇ
ꢌꢍꢎꢈꢏ
ꢇꢈꢎAꢆꢓ A
ꢂ. ꢇRAꢐꢆꢌꢑ ꢌꢍꢎ ꢎꢍ ꢅꢒAꢓꢈ
ꢎꢈRꢔꢆꢌAꢓ ꢓꢈꢌꢑꢎꢛ
ꢁ.ꢀꢁ ꢁ.ꢂꢁ
ꢄ. Aꢓꢓ ꢇꢆꢔꢈꢌꢅꢆꢍꢌꢅ ARꢈ ꢆꢌ ꢔꢆꢓꢓꢆꢔꢈꢎꢈRꢅ
ꢕ. ꢇꢆꢔꢈꢌꢅꢆꢍꢌꢅ ꢍꢋ ꢈꢖꢗꢍꢅꢈꢇ ꢗAꢇ ꢍꢌ ꢘꢍꢎꢎꢍꢔ ꢍꢋ ꢗAꢒꢙAꢑꢈ ꢇꢍ ꢌꢍꢎ ꢆꢌꢒꢓꢚꢇꢈ
ꢔꢍꢓꢇ ꢋꢓAꢅꢛ. ꢔꢍꢓꢇ ꢋꢓAꢅꢛꢜ ꢆꢋ ꢗRꢈꢅꢈꢌꢎꢜ ꢅꢛAꢓꢓ ꢌꢍꢎ ꢈꢖꢒꢈꢈꢇ ꢁ.ꢂꢊꢝꢝ ꢍꢌ Aꢌꢞ ꢅꢆꢇꢈ
ꢀ. ꢅꢛAꢇꢈꢇ ARꢈA ꢆꢅ ꢍꢌꢓꢞ A RꢈꢋꢈRꢈꢌꢒꢈ ꢋꢍR ꢗꢆꢌ ꢂ ꢓꢍꢒAꢎꢆꢍꢌ
ꢍꢌ ꢎꢛꢈ ꢎꢍꢗ Aꢌꢇ ꢘꢍꢎꢎꢍꢔ ꢍꢋ ꢗAꢒꢙAꢑꢈ
ꢁ.ꢄꢁꢕ Rꢈꢋ
ꢎꢈRꢔꢆꢌAꢓ ꢎꢛꢆꢒꢙꢌꢈꢅꢅ
ꢁ.ꢂꢁ Rꢈꢋ
ꢁ.ꢁꢊ Rꢈꢋ
ꢗꢓAꢎꢈꢇ ARꢈA
ꢁ.ꢠꢁ ±ꢁ.ꢁꢊ
ꢀ.ꢊꢁ ±ꢁ.ꢁꢊ
ꢕ.ꢂꢁ ±ꢁ.ꢁꢊ
ꢄ.ꢊꢁ Rꢈꢋ
ꢄ.ꢟꢊ ±ꢁ.ꢁꢊ
ꢕ.ꢟꢊ ±ꢁ.ꢁꢊ
ꢗAꢒꢙAꢑꢈ ꢍꢚꢎꢓꢆꢌꢈ
ꢁ.ꢄꢊ ±ꢁ.ꢁꢊ
ꢁ.ꢊꢁ ꢘꢅꢒ
ꢕ.ꢊꢁ Rꢈꢋ
ꢀ.ꢂꢁ ±ꢁ.ꢁꢊ
ꢊ.ꢊꢁ ±ꢁ.ꢁꢊ
Rꢈꢒꢍꢔꢔꢈꢌꢇꢈꢇ ꢅꢍꢓꢇꢈR ꢗAꢇ ꢗꢆꢎꢒꢛ Aꢌꢇ ꢇꢆꢔꢈꢌꢅꢆꢍꢌꢅ
Aꢗꢗꢓꢞ ꢅꢍꢓꢇꢈR ꢔAꢅꢙ ꢎꢍ ARꢈAꢅ ꢎꢛAꢎ ARꢈ ꢌꢍꢎ ꢅꢍꢓꢇꢈRꢈꢇ
Rev. A
30
For more information www.analog.com
LT8393
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
10/20 Changed 170kHz to 350kHz in the bottom front page schematic.
1
Changed 1.214V to 1.220V in the Programming V UVLO paragraph.
23
IN
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
31
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LT8393
TYPICAL APPLICATION
Highly Efficient 2MHz Buck-Boost Controller Driving LEDs at High Current (1.5A)
ꢀꢁ
ꢀ.ꢀꢁꢂ
Rꢀ
6mΩ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢂꢃ ꢄꢅꢁ ꢆꢃꢇꢂꢈꢇꢉꢃꢉꢊ
ꢀꢁ ꢂꢃ ꢄꢅꢁ ꢂRAꢆꢇꢈꢉꢆꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁ
ꢀ.ꢁꢂꢃ
ꢀꢁꢁꢂ
ꢀꢁ
ꢀ.ꢁꢂꢃ
ꢀ.ꢁꢂꢃ
ꢀꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁꢂꢃꢄꢃ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢀꢂ
ꢀꢁ.ꢂꢃ
ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢀꢁꢂ ꢃꢁꢁ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢀꢅRꢆ
ꢀꢀꢁꢂ ꢃꢄ
68mΩ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀꢁꢂ
ꢀ.ꢁꢂꢃ
ꢀꢁꢁꢂ
ꢀꢁ
ꢀꢁꢂꢃꢄ
FAULT
AꢀAꢁꢂꢃ ꢄꢅꢆ
FAULT
ꢀꢁRꢂ
ꢀꢁꢂ
ꢀꢁꢂ ꢃꢄꢂ
ꢀꢁꢁꢂ
ꢀ
Rꢀꢁ
ꢀ.ꢁꢂꢃꢄ
ꢀꢁꢂ ꢃꢄꢅꢀꢃRAꢆꢇ ꢈAꢀꢉꢊꢋꢊꢌꢍꢍꢍꢎꢏꢐ ꢍ.ꢍꢑꢒ
ꢀꢁꢂ ꢀꢃꢄ ꢅꢆꢇ ꢈꢉꢊꢋꢀꢌꢃꢍꢎꢏꢐ
ꢀꢁꢂ ꢀꢃꢄ ꢅꢆꢇꢅꢆꢈꢉꢆ ꢅꢊꢋꢃꢌꢆꢌꢃꢍꢎꢏꢐꢑRꢃ
ꢀꢁꢂ ꢃꢄꢅꢆAꢇ ꢅꢈꢉꢊꢋꢊꢌꢍꢅ
ꢀꢁꢂ ꢀꢃꢄ ꢅꢆꢇ ꢈAꢉꢊꢋꢌꢍ
Rꢀꢁ ꢂꢃꢂꢃꢄꢃ ꢅRꢆꢇꢈꢀꢉꢊꢋꢌꢋRꢍꢍꢉꢋꢎ
ꢀꢁꢂ ꢃꢄꢅꢅꢆꢇꢈ
ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢂ
ꢀ.ꢁA
ꢀꢁꢂꢃ
Rꢀ
ꢀꢀ
ꢀ
ꢀ
Rꢀ
ꢀꢁ.ꢁꢂ
ꢀꢁꢂꢃ
ꢀꢀꢁꢂ
ꢀ.ꢁꢂ
ꢀ.ꢀꢁꢂ
ꢀꢁꢁꢂ
ꢀꢁꢁꢂꢃ
A
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
V : 4V to 60V, V : 0V to 60V, 3% Current Accuracy, Internal and External
PWM Dimming, TSSOP-28 and 4mm × 5mm QFN-28
LT8391/LT8391A
60V, Synchronous 4-Switch Buck-Boost LED
Controller with Spread Spectrum
IN
OUT
LT8390/LT8390A
LT3922
High Efficiency, 2MHz, Synchronous, 4-Switch
Buck-Boost Controller
V : 4V to 60V, V : 1V to 60V, I = <1µA, TSSOP-28E and 4mm × 5mm
QFN-28
IN
OUT
SD
36V, 2A, 2MHz Synchronous Step Up LED Driver with V : 2.8V to 36V, V : 4V to 34V, I = 1µA, Internal 128:1 PWM Dimming,
Internal 128:1 PWM Dimming
IN
OUT
SD
Ext 5000:1, 4mm × 5mm QFN-28
LT3755/LT3755-1/ 40V , 75V , 1MHz Non-Synchronous Boost LED
V : 4.5V to 40V, V : V to 75V, 4% Current Accuracy, 3mm × 3mm
QFN-16 and MSE-16
IN
OUT
IN
OUT IN
LT3755-2
Controller
LT3761
60V , 80V , 1MHz Non-Synchronous Boost LED
Controller with Internal PWM Generator
V : 4.5V to 60V, V : V to 80V, 3% Current Accuracy, External and
Internal PWM dimming, MSE-16
IN
OUT
IN
OUT IN
LT3762
LT3763
LT3795
60V, Synchronous Boost LED Driver Controller with
Spread Spectrum
V : 2.5V to 38.5V, V : 0V to 60V, +/-3.5% Current Accuracy, Internal and
External PWM Dimming, TSSOP-28 and 4mm × 5mm QFN-28
IN
OUT
60V, Synchronous Step-Down LED Controller
V : 6V to 60V, V : 0V to 55V, Internal and External PWM Dimming,
IN
OUT
TSSOP-28
110V, 1MHz Non-Synchronous Boost LED Controller V : 4.5V to 110V, V : V to 110V, 3% Current Accuracy, Internal Spread
with Spread Spectrum Frequency Modulation
IN
OUT IN
Spectrum, TSSOP-28
Rev. A
10/20
www.analog.com
32
ANALOG DEVICES, INC. 2019-2020
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