LTC2220IUP#PBF [ADI]
12-Bit, 170Msps ADCs;型号: | LTC2220IUP#PBF |
厂家: | ADI |
描述: | 12-Bit, 170Msps ADCs 转换器 |
文件: | 总32页 (文件大小:797K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC2220/LTC2221
12-Bit,170Msps/
135Msps ADCs
U
FEATURES
DESCRIPTIO
TheLTC®2220andLTC2221are170Msps/135Msps,sam-
pling 12-bit A/D converters designed for digitizing high
frequency, wide dynamic range signals. The LTC2220/
LTC2221 are perfect for demanding communications
applications with AC performance that includes 67.5dB
SNR and 80dB spurious free dynamic range for signals
up to 170MHz. Ultralow jitter of 0.15psRMS allows
undersampling of IF frequencies with excellent noise
performance.
■
Sample Rate: 170Msps/135Msps
■
67.5dB SNR up to 140MHz Input
■
80dB SFDR up to 170MHz Input
■
775MHz Full Power Bandwidth S/H
■
Single 3.3V Supply
■
Low Power Dissipation: 890mW/660mW
■
LVDS, CMOS, or Demultiplexed CMOS Outputs
■
Selectable Input Ranges: ±0.5V or ±1V
■
No Missing Codes
■
Optional Clock Duty Cycle Stabilizer
DC specs include ±0.4LSB INL (typ), ±0.3LSB DNL (typ)
■
Shutdown and Nap Modes
and no missing codes over temperature. The transition
■
Data Ready Output Clock
noise is a low 0.5LSBRMS
.
■
Pin Compatible Family
The digital outputs can be either differential LVDS, or
single-ended CMOS. There are three format options for
theCMOSoutputs:asinglebusrunningatthefulldatarate
or two demultiplexed buses running at half data rate with
either interleaved or simultaneous update. A separate
output power supply allows the CMOS output swing to
range from 0.5V to 3.6V.
The ENC+ and ENC– inputs may be driven differentially or
singleendedwithasinewave, PECL, LVDS, TTL, orCMOS
inputs. An optional clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
185Msps: LTC2220-1 (12-Bit)
170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit)
135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit)
64-Pin 9mm × 9mm QFN Package
■
U
APPLICATIO S
■
Wireless and Wired Broadband Communication
■
Cable Head-End Systems
■
Power Amplifier Linearization
Communications Test Equipment
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
U
TYPICAL APPLICATIO
SFDR vs Input Frequency
3.3V
V
DD
100
90
0.5V
TO 3.6V
REFH
REFL
FLEXIBLE
REFERENCE
OV
DD
4th OR HIGHER
80
70
60
50
40
D11
+
12-BIT
PIPELINED
ADC CORE
CMOS
OR
•
•
•
CORRECTION
LOGIC
ANALOG
INPUT
OUTPUT
DRIVERS
INPUT
S/H
LVDS
–
D0
2nd OR 3rd
OGND
CLOCK/DUTY
CYCLE
CONTROL
22201 TA01
200
300
0
100
400
500
600
ENCODE
INPUT
INPUT FREQUENCY (MHz)
22201 TA01b
22201fa
1
LTC2220/LTC2221
W W U W
U
W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
OV = V (Notes 1, 2)
DD
DD
TOP VIEW
Supply Voltage (VDD)................................................. 4V
Digital Output Ground Voltage (OGND) .......–0.3V to 1V
Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V)
Digital Input Voltage .................... –0.3V to (VDD + 0.3V)
Digital Output Voltage............... –0.3V to (OVDD + 0.3V)
Power Dissipation............................................ 1500mW
Operating Temperature Range
LTC2220C, LTC2221C ............................. 0°C to 70°C
LTC2220I, LTC2221I ...........................–40°C to 85°C
Storage Temperature Range ..................–65°C to 125°C
+
+
A
1
2
3
4
48 D9 /DA6
IN
+
–
–
–
A
IN
A
IN
A
IN
47 D9 /DA5
+
46 D8 /DA4
–
45 D8 /DA3
+
REFHA 5
REFHA 6
REFLB 7
REFLB 8
REFHB 9
REFHB 10
REFLA 11
REFLA 12
44 D7 /DA2
–
43 D7 /DA1
42 OV
DD
41 OGND
65
+
40 D6 /DA0
–
39 D6 /CLOCKOUTA
+
38 D5 /CLOCKOUTB
–
37 D5 /OFB
36 CLOCKOUT /DB11
35 CLOCKOUT /DB10
+
V
DD
V
DD
V
DD
13
14
15
–
34 OV
DD
33 OGND
GND 16
UP PACKAGE
64-LEAD (9mm × 9mm) PLASTIC QFN
TJMAX = 125°C, θJA = 20°C/W
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
UP PART MARKING*
LTC2220UP
ORDER PART NUMBER
LTC2220CUP
LTC2220IUP
LTC2221CUP
LTC2221IUP
LTC2220UP
LTC2221UP
LTC2221UP
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
The temperature grade is identified by a label on the shipping container.
U
CO VERTER CHARACTERISTICS The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. (Note 4)
A
LTC2220
TYP
LTC2221
TYP
PARAMETER
CONDITIONS
MIN
12
MAX
MIN
12
MAX
UNITS
Bits
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Integral Linearity Error
Differential Linearity Error
Offset Error
●
●
●
Differential Analog Input (Note 5)
Differential Analog Input
Single-Ended Analog Input (Note 5)
Single-Ended Analog Input
(Note 6)
–1.5
–1
±0.4
±0.3
±1
1.5
1
–1
±0.4
±0.2
±1
1
1
LSB
LSB
LSB
LSB
mV
–1
±0.3
±3
±0.2
±3
●
●
–35
35
–35
35
Gain Error
External Reference
–2.5
±0.5
±10
2.5
–2.5
±0.5
±10
2.5
%FS
µV/C
Offset Drift
Full-Scale Drift
Internal Reference
External Reference
±30
±15
±30
±15
ppm/C
ppm/C
Transition Noise
SENSE = 1V
0.5
0.5
LSB
RMS
22201fa
2
LTC2220/LTC2221
U
U
A ALOG I PUT
The
●
denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at T = 25°C. (Note 4)
A
SYMBOL
PARAMETER
Analog Input Range (A – A
CONDITIONS
MIN
TYP
MAX
UNITS
+
–
V
V
)
3.1V < V < 3.5V (Note 7)
●
±0.5 to ±1
V
IN
IN
IN
DD
+
–
Analog Input Common Mode (A + A )/2
Differential Input (Note 7)
Single Ended Input (Note 7)
●
●
1
0.5
1.6
1.6
1.9
2.1
V
V
IN, CM
IN
IN
+
–
I
I
I
I
t
t
Analog Input Leakage Current
SENSE Input Leakage
0 < A , A < V
DD
●
●
–1
–1
1
1
µA
µA
µA
µA
ns
IN
IN
IN
0V < SENSE < 1V
SENSE
MODE
LVDS
AP
MODE Pin Pull-Down Current to GND
LVDS Pin Pull-Down Current to GND
10
10
Sample and Hold Acquisition Delay Time
Sample and Hold Acquisition Delay Time Jitter
Analog Input Common Mode Rejection Ratio
Full Power Bandwidth
0
0.15
80
ps
RMS
JITTER
CMRR
dB
Figure 8 Test Circuit
775
MHz
U W
DY A IC ACCURACY
The
IN
●
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T = 25°C. A = –1dBFS. (Note 4)
A
LTC2220
TYP
LTC2221
TYP
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
SNR
Signal-to-Noise Ratio
(Note 10)
5MHz Input (1V Range)
5MHz Input (2V Range)
62.7
67.7
62.8
67.8
dB
dB
70MHz Input (1V Range)
70MHz Input (2V Range)
62.7
67.6
62.8
67.8
dB
dB
●
●
●
●
65.8
65.8
140MHz Input (1V Range)
140MHz Input (2V Range)
62.4
67.5
62.5
67.5
dB
dB
250MHz Input (1V Range)
250MHz Input (2V Range)
61.8
66.1
61.8
66.1
dB
dB
SFDR
Spurious Free Dynamic Range 5MHz Input (1V Range)
84
84
84
84
dB
dB
2nd or 3rd Harmonic
(Note 11)
5MHz Input (2V Range)
70MHz Input (1V Range)
70MHz Input (2V Range)
84
84
84
84
dB
dB
70
75
65
70
75
65
140MHz Input (1V Range)
140MHz Input (2V Range)
84
84
84
84
dB
dB
250MHz Input (1V Range)
250MHz Input (2V Range)
74
73
77
77
dB
dB
SFDR
Spurious Free Dynamic Range 5MHz Input (1V Range)
90
90
90
90
dB
dB
4th Harmonic or Higher
(Note 11)
5MHz Input (2V Range)
70MHz Input (1V Range)
70MHz Input (2V Range)
90
90
90
90
dB
dB
140MHz Input (1V Range)
140MHz Input (2V Range)
87
87
90
90
dB
dB
250MHz Input (1V Range)
250MHz Input (2V Range)
85
85
90
90
dB
dB
S/(N+D)
IMD
Signal-to-Noise Plus
Distortion Ratio (Note 12)
5MHz Input (1V Range)
5MHz Input (2V Range)
62.7
67.5
62.8
67.6
dB
dB
70MHz Input (1V Range)
70MHz Input (2V Range)
62.7
67.3
62.8
67.4
dB
dB
Intermodulation Distortion
f
= 138MHz, f = 140MHz
81
81
dBc
IN1
IN2
22201fa
3
LTC2220/LTC2221
U U
U
(Note 4)
I TER AL REFERE CE CHARACTERISTICS
PARAMETER
CONDITIONS
= 0
MIN
TYP
1.600
±25
3
MAX
UNITS
V
V
V
V
V
Output Voltage
Output Tempco
Line Regulation
Output Resistance
I
1.570
1.630
CM
CM
CM
CM
OUT
ppm/°C
mV/V
Ω
3.1V < V < 3.5V
DD
–1mA < I
< 1mA
4
OUT
U
U
DIGITAL I PUTS A D DIGITAL OUTPUTS
The
●
denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T = 25°C. (Note 4)
A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
–
ENCODE INPUTS (ENC , ENC )
V
V
Differential Input Voltage
●
●
0.2
1.1
V
ID
Common Mode Input Voltage
Internally Set
Externally Set (Note 7)
1.6
1.6
V
V
ICM
2.5
R
Input Resistance
Input Capacitance
6
3
kΩ
IN
C
(Note 7)
pF
IN
LOGIC INPUTS (OE, SHDN)
V
V
High Level Input Voltage
Low Level Input Voltage
Input Current
V
V
V
= 3.3V
= 3.3V
●
●
●
2
V
V
IH
IL
DD
DD
IN
0.8
10
I
= 0V to V
–10
µA
pF
IN
DD
C
Input Capacitance
(Note 7)
3
IN
LOGIC OUTPUTS (CMOS MODE)
OV = 3.3V
DD
C
Hi-Z Output Capacitance
Output Source Current
Output Sink Current
OE = High (Note 7)
3
pF
mA
mA
OZ
I
I
V
V
= 0V
50
50
SOURCE
SINK
OUT
OUT
= 3.3V
V
High Level Output Voltage
I = –10µA
O
3.295
3.29
V
V
OH
O
I = –200µA
●
●
3.1
V
Low Level Output Voltage
I = 10µA
0.005
0.09
V
V
OL
O
I = 1.6mA
0.4
O
OV = 2.5V
DD
V
V
High Level Output Voltage
Low Level Output Voltage
I = –200µA
2.49
0.09
V
V
OH
OL
O
I = 1.6mA
O
OV = 1.8V
DD
V
V
High Level Output Voltage
Low Level Output Voltage
I = –200µA
1.79
0.09
V
V
OH
OL
O
I = 1.6mA
O
LOGIC OUTPUTS (LVDS MODE)
V
V
Differential Output Voltage
100Ω Differential Load
100Ω Differential Load
●
●
247
350
454
mV
V
OD
OS
Output Common Mode Voltage
1.125
1.250
1.375
22201fa
4
LTC2220/LTC2221
W U
POWER REQUIRE E TS
The
●
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T = 25°C. (Note 9)
A
LTC2220
TYP
LTC2221
TYP
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
V
V
P
P
Analog Supply Voltage
Shutdown Power
Nap Mode Power
(Note 8)
●
3.1
3.3
2
3.5
3.1
3.3
2
3.5
DD
SHDN = High, OE = High, No CLK
SHDN = High, OE = Low, No CLK
mW
mW
SHDN
NAP
35
35
LVDS OUTPUT MODE
OV
Output Supply Voltage
Analog Supply Current
Output Supply Current
Power Dissipation
(Note 8)
(Note 8)
●
●
●
●
3
3.3
264
55
3.6
288
70
3
3.3
196
55
3.6
212
70
V
mA
DD
I
I
VDD
OVDD
mA
P
1050
1182
828
931
mW
DISS
CMOS OUTPUT MODE
OV
Output Supply Voltage
Analog Supply Current
Power Dissipation
●
●
0.5
3.3
264
890
3.6
0.5
3.3
196
660
3.6
V
mA
DD
I
288
212
VDD
P
mW
DISS
W U
TI I G CHARACTERISTICS The
●
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T = 25°C. (Note 4)
A
LTC2220
TYP
LTC2221
TYP
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
f
t
Sampling Frequency
ENC Low Time (Note 7)
(Note 8)
●
1
170
1
135
MHz
S
L
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
●
●
2.8
2
2.94
2.94
500
500
3.5
2
3.7
3.7
500
500
ns
ns
t
ENC High Time (Note 7)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
●
●
2.8
2
2.94
2.94
500
500
3.5
2
3.7
3.7
500
500
ns
ns
H
t
t
Sample-and-Hold Aperture Delay
Output Enable Delay
0
5
0
5
ns
ns
AP
OE
(Note 7)
●
10
10
LVDS OUTPUT MODE
t
t
ENC to DATA Delay
ENC to CLOCKOUT Delay
DATA to CLOCKOUT Skew
Rise Time
(Note 7)
(Note 7)
●
●
●
1.3
1.3
2.2
2.2
0
3.5
3.5
0.6
1.3
1.3
2.2
2.2
0
3.5
3.5
0.6
ns
ns
D
C
(t - t ) (Note 7)
–0.6
–0.6
ns
C
D
0.5
0.5
5
0.5
0.5
5
ns
Fall Time
ns
Pipeline Latency
Cycles
CMOS OUTPUT MODE
t
t
ENC to DATA Delay
(Note 7)
(Note 7)
●
●
●
1.3
1.3
2.1
3.5
3.5
0.6
1.3
1.3
2.1
3.5
3.5
0.6
ns
ns
D
C
ENC to CLOCKOUT Delay
DATA to CLOCKOUT Skew
2.1
2.1
(t - t ) (Note 7)
–0.6
0
–0.6
0
ns
C
D
Pipeline Latency Full Rate CMOS
Demuxed Interleaved
Demuxed Simultaneous
5
5
5
5
Cycles
Cycles
Cycles
5 and 6
5 and 6
22201fa
5
LTC2220/LTC2221
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when the
output code flickers between 0000 0000 0000 and 1111 1111 1111 in 2’s
complement output mode.
Note 7: Guaranteed by design, not subject to test.
Note 8: Recommended operating conditions.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 9: V = 3.3V, f
differentialENC /ENC =2V sinewave, inputrange=1V withdifferential
= 170MHz (LTC2220) or 135MHz (LTC2221),
P-P P-P
DD
SAMPLE
+
–
Note 3: When these pin voltages are taken below GND or above V , they will
DD
be clamped by internal diodes. This product can handle input currents of
drive, output C
= 5pF.
LOAD
greater than 100mA below GND or above V without latchup.
DD
Note 10: SNR minimum and typical values are for LVDS mode. Typical values
for CMOS mode are typically 0.3dB lower.
Note 11: SFDR minimum values are for LVDS mode. Typical values are for
both LVDS and CMOS modes.
Note 12: SINAD minimum and typical values are for LVDS mode. Typical
values for CMOS mode are typically 0.3dB lower.
Note 4: V = 3.3V, f
LVDS outputs, differential ENC /ENC = 2V
= 170MHz (LTC2220) or 135MHz (LTC2221),
DD
SAMPLE
+
–
sine wave, input range =
P-P
2V with differential drive, unless otherwise noted.
P-P
Note 5: Integral nonlinearity is defined as the deviation of a code from a “best
straight line” fit to the transfer curve. The deviation is measured from the
center of the quantization band.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
(T = 25°C unless otherwise noted, Note 4)
A
LTC2220: Shorted Input Noise
Histogram
LTC2220: INL, 2V Range
LTC2220: DNL, 2V Range
1.0
0.8
1.0
0.8
100000
93571
0.6
0.6
80000
60000
0.4
0.4
0.2
0.2
0
0
– 0.2
– 0.4
– 0.6
– 0.8
– 1.0
– 0.2
– 0.4
– 0.6
– 0.8
– 1.0
40000
24266
20000
12866
229
140
2060
–0
0
1024
2048
3072
4096
0
1024
2048
3072
4096
2056
2057
2058
2059
OUTPUT CODE
OUTPUT CODE
CODE
2220 G01
2220 G02
2220 G03
LTC2220: SNR vs Input
Frequency, –1dB, 2V Range,
LVDS Mode
LTC2220: SNR vs Input
Frequency, –1dB, 1V Range,
LVDS Mode
LTC2220: SFDR (HD2 and HD3)
vs Input Frequency, –1dB, 2V
Range, LVDS Mode
70
69
68
67
66
65
64
63
62
61
60
70
69
68
67
66
65
64
63
62
61
60
100
90
80
70
60
50
40
200
300
200
300
200
300
0
100
400
500
600
0
100
400
500
600
0
100
400
500
600
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
2220 G04
2220 G05
2220 G06
22201fa
6
LTC2220/LTC2221
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2220: SFDR (HD2 and HD3)
vs Input Frequency, –1dB, 1V
Range, LVDS Mode
LTC2220: SFDR (HD4+) vs Input
Frequency, –1dB, 2V Range,
LVDS Mode
LTC2220: SFDR (HD4+) vs Input
Frequency, –1dB, 1V Range,
LVDS Mode
100
90
100
90
100
90
80
70
60
50
40
80
70
60
50
40
80
70
60
50
40
200
300
200
300
200
300
0
100
400
500
600
0
100
400
500
600
0
100
400
500
600
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
2220 G07
2220 G08
2220 G09
LTC2220: SFDR and SNR
LTC2220: SFDR and SNR
vs Sample Rate, 2V Range,
= 30MHz, –1dB, LVDS Mode
vs Sample Rate, 1V Range,
LTC2220: I
vs Sample Rate,
VDD
f
IN
= 30MHz, –1dB, LVDS Mode
f
IN
5MHz Sine Wave Input, –1dB
95
90
85
80
75
70
65
60
55
50
95
90
85
80
75
70
65
60
55
50
290
280
270
260
250
240
230
220
210
SFDR
SFDR
2V RANGE
1V RANGE
SNR
SNR
80
SAMPLE RATE (Msps)
80
80
SAMPLE RATE (Msps)
0
40
120
160
200
0
40
120
160
200
0
40
120
160
200
SAMPLE RATE (Msps)
2220 G10
2220 G11
2220 G12
LTC2220: SFDR vs Input Level,
fIN = 70MHz, 2V Range
LTC2220: I
vs Sample Rate,
OVDD
5MHz Sine Wave Input, –1dB
100
90
80
70
60
50
40
30
20
10
0
60
50
40
30
20
10
0
LVDS OUTPUTS, 0V = 3.3V
DD
dBFS
dBc
CMOS OUTPUTS, 0V = 1.8V
DD
80
SAMPLE RATE (Msps)
0
40
120
160
200
–60
–50
–30
–20
–10
0
–40
INPUT LEVEL (dBFS)
2220 G13
2220 G14
22201fa
7
LTC2220/LTC2221
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2220: 8192 Point FFT,
= 30MHz, –1dB, 2V Range,
LTC2220: 8192 Point FFT,
f = 30MHz, –1dB, 1V Range,
IN
LVDS Mode
LTC2220: 8192 Point FFT,
= 70MHz, –1dB, 2V Range,
f
f
IN
IN
LVDS Mode
LVDS Mode
0
–20
0
–20
0
–20
–40
–40
–40
–60
–60
–60
–80
–80
–80
–100
–120
–100
–120
–100
–120
50
FREQUENCY (MHz)
70
50
70
70
70
50
70
70
70
0
10 20 30
80
2220 • G15
0
10 20 30
80
2220 • G16
0
10 20 30
80
2220 • G17
40
60
40
60
40
60
FREQUENCY (MHz)
FREQUENCY (MHz)
LTC2220: 8192 Point FFT,
= 70MHz, –1dB, 1V Range,
LVDS Mode
LTC2220: 8192 Point FFT,
LTC2220: 8192 Point FFT,
f
f
= 140MHz, –1dB, 2V
f = 140MHz, –1dB, 1V
IN
IN
IN
Range, LVDS Mode
Range, LVDS Mode
0
–20
0
–20
0
–20
–40
–40
–40
–60
–60
–60
–80
–80
–80
–100
–120
–100
–120
–100
–120
50
70
50
FREQUENCY (MHz)
50
FREQUENCY (MHz)
0
10 20 30
80
0
10 20 30
80
0
10 20 30
80
40
60
40
60
40
60
FREQUENCY (MHz)
2220 • G18
2220 • G19
2220 • G20
LTC2220: 8192 Point FFT,
LTC2220: 8192 Point FFT,
= 250MHz, –1dB, 1V
Range, LVDS Mode
LTC2220: 8192 Point FFT,
f = 500MHz, –6dB, 1V
IN
Range, LVDS Mode
f
= 250MHz, –1dB, 2V
f
IN
IN
Range, LVDS Mode
0
–20
0
–20
0
–20
–40
–40
–40
–60
–60
–60
–80
–80
–80
–100
–120
–100
–120
–100
–120
50
FREQUENCY (MHz)
70
50
FREQUENCY (MHz)
50
FREQUENCY (MHz)
0
10 20 30
80
0
10 20 30
80
0
10 20 30
80
40
60
40
60
40
60
2220 • G21
2220 • G22
2220 • G23
22201fa
8
LTC2220/LTC2221
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2221: Shorted Input Noise
Histogram
LTC2221: INL, 2V Range
LTC2221: DNL, 2V Range
100000
1.0
0.8
1.0
0.8
79331
80000
0.6
0.6
0.4
0.4
60000
0.2
0.2
0
0
40000
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
29529
21767
20000
322
123
0
2048
3072
2048
3072
2057
2058
2059
2060
2061
0
4096
0
4096
1024
1024
OUTPUT CODE
OUTPUT CODE
CODE
2221 G01
2221 G02
2221 G03
LTC2221: SNR vs Input
Frequency, –1dB, 2V Range,
LVDS Mode
LTC2221: SNR vs Input
Frequency, –1dB, 1V Range,
LVDS Mode
LTC2221: SFDR (HD2 and HD3)
vs Input Frequency, –1dB, 2V
Range, LVDS Mode
95
69
67
65
63
61
59
57
55
69
67
65
63
61
59
57
55
90
85
80
75
70
65
60
55
50
200
300
200
300
200
300
0
100
400
500
600
0
100
400
500
600
0
100
400
500
600
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
2221 G04
2221 G05
2221 G06
LTC2221: SFDR (HD2 and HD3)
vs Input Frequency, –1dB, 1V
Range, LVDS Mode
LTC2221: SFDR (HD4+) vs Input
Frequency, –1dB, 2V Range,
LVDS Mode
LTC2221: SFDR (HD4+) vs Input
Frequency, –1dB, 1V Range,
LVDS Mode
95
90
85
80
75
70
65
60
55
50
95
90
85
80
75
70
65
60
55
50
95
90
85
80
75
70
65
60
55
50
200
300
200
300
200
300
0
100
400
500
600
0
100
400
500
600
0
100
400
500
600
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
2221 G07
2221 G08
2221 G09
22201fa
9
LTC2220/LTC2221
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2221: SFDR and SNR
LTC2221: SFDR and SNR
vs Sample Rate, 2V Range,
vs Sample Rate, 1V Range,
LTC2221: I
vs Sample Rate,
VDD
f
IN
= 30MHz, –1dB, LVDS Mode
f
IN
= 30MHz, –1dB, LVDS Mode
5MHz Sine Wave Input, –1dB
220
210
200
190
180
170
160
150
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
SFDR
SFDR
2V RANGE
1V RANGE
SNR
SNR
0
20 40 60 80 100 120 140 160
SAMPLE RATE (Msps)
2221 G10
0
20 40 60 80 100 120 140 160
SAMPLE RATE (Msps)
2221 G11
0
20 40 60
120 140 160 180
80 100
SAMPLE RATE (Msps)
2221 G12
LTC2221: SFDR vs Input Level,
fIN = 70MHz, 2V Range
LTC2221: I
vs Sample Rate,
OVDD
5MHz Sine Wave Input, –1dB
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
LVDS OUTPUTS, OV = 3.3V
DD
dBFS
dBc
CMOS OUTPUTS, OV = 1.8V
DD
0
20 40 60 80 100 120 140 160 180
SAMPLE RATE (Msps)
–60 –50
–30
–20
–10
0
–40
INPUT LEVELS (dBFS)
2221 G13
2221 G14
22201fa
10
LTC2220/LTC2221
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2221: 8192 Point FFT,
= 30MHz, –1dB, 2V Range,
LTC2221: 8192 Point FFT,
f = 30MHz, –1dB, 1V Range,
IN
LVDS Mode
LTC2221: 8192 Point FFT,
f
f
= 70MHz, –1dB, 2V Range,
IN
IN
LVDS Mode
LVDS Mode
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
5
10 15 20 25 30 35 40 45 50 55 60 65
FREQUENCY (MHz)
0
5
10 15 20 25 30 35 40 45 50 55 60 65
FREQUENCY (MHz)
0
5
10 15 20 25 30 35 40 45 50 55 60 65
FREQUENCY (MHz)
2221 G15
2221 G16
2221 G17
LTC2221: 8192 Point FFT,
= 70MHz, –1dB, 1V Range,
LTC2221: 8192 Point FFT,
= 140MHz, –1dB, 2V
LTC2221: 8192 Point FFT,
f = 140MHz, –1dB, 1V
IN
Range, LVDS Mode
f
f
IN
IN
LVDS Mode
Range, LVDS Mode
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
5
10 15 20 25 30 35 40 45 50 55 60 65
0
5
10 15 20 25 30 35 40 45 50 55 60 65
0
5
10 15 20 25 30 35 40 45 50 55 60 65
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
2221 G19
2221 G20
2221 G18
LTC2221: 8192 Point FFT,
= 250MHz, –1dB, 2V
LTC2221: 8192 Point FFT,
= 250MHz, –1dB, 1V
LTC2221: 8192 Point FFT,
f = 500MHz, –6dB, 1V
IN
Range, LVDS Mode
f
f
IN
IN
Range, LVDS Mode
Range, LVDS Mode
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
5
10 15 20 25 30 35 40 45 50 55 60 65
0
5
10 15 20 25 30 35 40 45 50 55 60 65
0
5
10 15 20 25 30 35 40 45 50 55 60 65
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
2221 G21
2221 G22
2221 G23
22201fa
11
LTC2220/LTC2221
U
U
U
PI FU CTIO S
DB0 - DB11 (Pins 21, 22, 23, 24, 27, 28, 29, 30, 31, 32,
35, 36): Digital Outputs, B Bus. DB11 is the MSB. At high
impedance in full rate CMOS mode.
(CMOS Mode)
AIN+ (Pins 1, 2): Positive Differential Analog Input.
AIN– (Pins 3, 4): Negative Differential Analog Input.
OGND (Pins 25, 33, 41, 50): Output Driver Ground.
REFHA (Pins 5, 6): ADC High Reference. Bypass to
Pins 7, 8 with 0.1µF ceramic chip capacitor, to Pins 11, 12
with a 2.2µF ceramic capacitor and to ground with 1µF
ceramic capacitor.
REFLB (Pins 7, 8): ADC Low Reference. Bypass to Pins 5,
6 with 0.1µF ceramic chip capacitor. Do not connect to
Pins 11, 12.
OVDD (Pins 26, 34, 42, 49): Positive Supply for the
Output Drivers. Bypass to ground with 0.1µF ceramic chip
capacitor.
OFB (Pin 37): Over/Under Flow Output for B Bus. High
when an over or under flow has occurred. At high imped-
ance in full rate CMOS mode.
CLKOUTB (Pin 38): Data Valid Output for B Bus. In demux
mode with interleaved update, latch B bus data on the
falling edge of CLKOUTB. In demux mode with simulta-
neous update, latch B bus data on the rising edge of
CLKOUTB. This pin does not become high impedance in
full rate CMOS mode.
CLKOUTA (Pin 39): Data Valid Output for A Bus. Latch A
bus data on the falling edge of CLKOUTA.
DA0 - DA11 (Pins 40, 43, 44, 45, 46, 47, 48, 51, 52, 53,
54, 55): Digital Outputs, A Bus. DA11 is the MSB.
REFHB (Pins 9, 10): ADC High Reference. Bypass to
Pins 11, 12 with 0.1µF ceramic chip capacitor. Do not
connect to Pins 5, 6.
REFLA (Pins 11, 12): ADC Low Reference. Bypass to
Pins 9, 10 with 0.1µF ceramic chip capacitor, to Pins 5, 6
with a 2.2µF ceramic capacitor and to ground with 1µF
ceramic capacitor.
VDD (Pins 13, 14, 15, 62, 63): 3.3V Supply. Bypass to
GND with 0.1µF ceramic chip capacitors.
GND (Pins 16, 61, 64): ADC Power Ground.
OFA (Pin 56): Over/Under Flow Output for A Bus. High
when an over or under flow has occurred.
ENC+ (Pin 17): Encode Input. Conversion starts on the
positive edge.
LVDS (Pin 57): Output Mode Selection Pin. Connecting
LVDS to 0V selects full rate CMOS mode. Connecting
LVDS to 1/3VDD selects demux CMOS mode with simulta-
neous update. Connecting LVDS to 2/3VDD selects demux
CMOS mode with interleaved update. Connecting LVDS to
VDD selects LVDS mode.
MODE (Pin 58): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and turns the clock duty cycle
stabilizer off. Connecting MODE to 1/3VDD selects offset
binary output format and turns the clock duty cycle stabi-
lizer on. Connecting MODE to 2/3VDD selects 2’s comple-
ment output format and turns the clock duty cycle stabi-
lizer on. Connecting MODE to VDD selects 2’s complement
output format and turns the clock duty cycle stabilizer off.
ENC– (Pin 18): Encode Complement Input. Conversion
starts on the negative edge. Bypass to ground with 0.1µF
ceramic for single-ended ENCODE signal.
SHDN (Pin 19): Shutdown Mode Selection Pin. Connect-
ing SHDN to GND and OE to GND results in normal
operation with the outputs enabled. Connecting SHDN to
GND and OE to VDD results in normal operation with the
outputs at high impedance. Connecting SHDN to VDD and
OE to GND results in nap mode with the outputs at high
impedance. Connecting SHDN to VDD and OE to VDD
results in sleep mode with the outputs at high impedance.
OE (Pin 20): Output Enable Pin. Refer to SHDN pin
function.
22201fa
12
LTC2220/LTC2221
U
U
U
PI FU CTIO S
ENC+ (Pin 17): Encode Input. Conversion starts on the
SENSE(Pin59):ReferenceProgrammingPin.Connecting
SENSE to VCM selects the internal reference and a ±0.5V
input range. Connecting SENSE to VDD selects the internal
reference and a ±1V input range. An external reference
greater than 0.5V and less than 1V applied to SENSE
selects an input range of ±VSENSE. ±1V is the largest valid
input range.
VCM (Pin 60): 1.6V Output and Input Common Mode Bias.
Bypass to ground with 2.2µF ceramic chip capacitor.
GND (Exposed Pad) (Pin 65): ADC Power Ground. The
exposed pad on the bottom of the package needs to be
soldered to ground.
positive edge.
ENC– (Pin 18): Encode Complement Input. Conversion
starts on the negative edge. Bypass to ground with 0.1µF
ceramic for single-ended ENCODE signal.
SHDN (Pin 19): Shutdown Mode Selection Pin. Connect-
ing SHDN to GND and OE to GND results in normal
operation with the outputs enabled. Connecting SHDN to
GND and OE to VDD results in normal operation with the
outputs at high impedance. Connecting SHDN to VDD and
OE to GND results in nap mode with the outputs at high
impedance. Connecting SHDN to VDD and OE to VDD
results in sleep mode with the outputs at high impedance.
(LVDS Mode)
OE (Pin 20): Output Enable Pin. Refer to SHDN pin
AIN+ (Pins 1, 2): Positive Differential Analog Input.
AIN– (Pins 3, 4): Negative Differential Analog Input.
function.
D0–/D0+ to D11–/D11+ (Pins 21, 22, 23, 24, 27, 28, 29,
30, 31, 32, 37, 38, 39, 40, 43, 44, 45, 46, 47, 48, 51, 52,
53, 54): LVDS Digital Outputs. All LVDS outputs require
differential 100Ω termination resistors at the LVDS re-
ceiver. D11–/D11+ is the MSB.
REFHA (Pins 5, 6): ADC High Reference. Bypass to
Pins 7, 8 with 0.1µF ceramic chip capacitor, to Pins 11, 12
with a 2.2µF ceramic capacitor and to ground with 1µF
ceramic capacitor.
REFLB (Pins 7, 8): ADC Low Reference. Bypass to Pins 5,
6 with 0.1µF ceramic chip capacitor. Do not connect to
Pins 11, 12.
OGND (Pins 25, 33, 41, 50): Output Driver Ground.
OVDD (Pins26, 34, 42, 49):PositiveSupplyfortheOutput
Drivers. Bypass to ground with 0.1µF ceramic chip
capacitor.
CLKOUT–/CLKOUT+ (Pins 35 to 36): LVDS Data Valid
Output.LatchdataonrisingedgeofCLKOUT–,fallingedge
of CLKOUT+.
REFHB (Pins 9, 10): ADC High Reference. Bypass to
Pins 11, 12 with 0.1µF ceramic chip capacitor. Do not
connect to Pins 5, 6.
REFLA (Pins 11, 12): ADC Low Reference. Bypass to
Pins 9, 10 with 0.1µF ceramic chip capacitor, to Pins 5, 6
with a 2.2µF ceramic capacitor and to ground with 1µF
ceramic capacitor.
OF–/OF+ (Pins 55 to 56): LVDS Over/Under Flow Output.
High when an over or under flow has occurred.
LVDS (Pin 57): Output Mode Selection Pin. Connecting
LVDS to 0V selects full rate CMOS mode. Connecting
LVDS to 1/3VDD selects demux CMOS mode with simulta-
neous update. Connecting LVDS to 2/3VDD selects demux
CMOS mode with interleaved update. Connecting LVDS to
VDD selects LVDS mode.
VDD (Pins 13, 14, 15, 62, 63): 3.3V Supply. Bypass to
GND with 0.1µF ceramic chip capacitors.
GND (Pins 16, 61, 64): ADC Power Ground.
22201fa
13
LTC2220/LTC2221
U
U
U
PI FU CTIO S
MODE (Pin 58): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and turns the clock duty cycle
stabilizer off. Connecting MODE to 1/3VDD selects offset
binary output format and turns the clock duty cycle stabi-
lizer on. Connecting MODE to 2/3VDD selects 2’s comple-
ment output format and turns the clock duty cycle stabi-
lizer on. Connecting MODE to VDD selects 2’s complement
output format and turns the clock duty cycle stabilizer off.
input range. Connecting SENSE to VDD selects the internal
reference and a ±1V input range. An external reference
greater than 0.5V and less than 1V applied to SENSE
selects an input range of ±VSENSE. ±1V is the largest valid
input range.
VCM (Pin 60): 1.6V Output and Input Common Mode Bias.
Bypass to ground with 2.2µF ceramic chip capacitor.
GND (Exposed Pad) (Pin 65): ADC Power Ground. The
exposed pad on the bottom of the package needs to be
soldered to ground.
SENSE(Pin59):ReferenceProgrammingPin.Connecting
SENSE to VCM selects the internal reference and a ±0.5V
22201fa
14
LTC2220/LTC2221
U
U
W
FUNCTIONAL BLOCK DIAGRA
+
A
IN
V
DD
INPUT
S/H
FIRST PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
THIRD PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
–
A
IN
GND
V
CM
1.6V
REFERENCE
2.2µF
SHIFT REGISTER
AND CORRECTION
RANGE
SELECT
REFH
REFL
INTERNAL CLOCK SIGNALS
REF
BUF
OV
DD
SENSE
+
OF
–
+
DIFFERENTIAL
INPUT
LOW JITTER
CLOCK
DRIVER
D11
–
+
DIFF
•
•
•
CONTROL
LOGIC
OUTPUT
DRIVERS
REF
AMP
D0
–
+
CLKOUT
–
22201 F01
REFLB REFHA
REFLA REFHB
OGND
2.2µF
+
–
LVDS SHDN
ENC
ENC
M0DE
OE
0.1µF
1µF
0.1µF
1µF
Figure 1. Functional Block Diagram
22201fa
15
LTC2220/LTC2221
W U
W
TI I G DIAGRA S
LVDS Output Mode Timing
All Outputs Are Differential and Have LVDS Levels
t
AP
N + 4
N + 2
ANALOG
INPUT
N
N + 3
t
H
N + 1
t
L
–
ENC
+
ENC
t
D
N – 5
N – 4
N – 3
N – 2
N – 1
D0-D11, OF
t
C
–
CLOCKOUT
22201 TD01
+
CLOCKOUT
Full-Rate CMOS Output Mode Timing
All Outputs Are Single-Ended and Have CMOS Levels
t
AP
N + 4
N + 2
ANALOG
INPUT
N
N + 3
t
H
N + 1
t
L
–
ENC
+
ENC
t
t
D
N – 5
N – 4
N – 3
N – 2
N – 1
DA0-DA11, OFA
C
CLOCKOUTB
CLOCKOUTA
HIGH IMPEDANCE
DB0-DB11, OFB
22201 TD02
22201fa
16
LTC2220/LTC2221
W U
W
TI I G DIAGRA S
Demultiplexed CMOS Outputs with Interleaved Update
All Outputs Are Single-Ended and Have CMOS Levels
t
AP
N + 4
N + 2
ANALOG
INPUT
N
N + 3
t
H
N + 1
t
L
–
ENC
+
ENC
t
D
N – 5
N – 3
N – 1
DA0-DA11, OFA
DB0-DB11, OFB
t
t
D
C
N – 6
N – 4
N – 2
t
C
CLOCKOUTB
CLOCKOUTA
22201 TD03
Demultiplexed CMOS Outputs with Simultaneous Update
All Outputs Are Single-Ended and Have CMOS Levels
t
AP
N + 4
N + 2
ANALOG
INPUT
N
N + 3
t
H
N + 1
t
L
–
ENC
+
ENC
t
t
t
D
D
C
N – 6
N – 4
N – 2
N – 1
DA0-DA11, OFA
DB0-DB11, OFB
N – 5
N – 3
CLOCKOUTB
CLOCKOUTA
22201 TD04
22201fa
17
LTC2220/LTC2221
U
W
U U
APPLICATIO S I FOR ATIO
DYNAMIC PERFORMANCE
input tone to the RMS value of the largest 3rd order
intermodulation product.
Signal-to-Noise Plus Distortion Ratio
Spurious Free Dynamic Range (SFDR)
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited
to frequencies above DC to below half the sampling
frequency.
Spurious free dynamic range is the peak harmonic or
spurious noise that is the largest spectral component
excluding the input signal and DC. This value is expressed
in decibels relative to the RMS value of a full scale input
signal.
Signal-to-Noise Ratio
Full Power Bandwidth
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC.
The full power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is re-
duced by 3dB for a full scale input signal.
Aperture Delay Time
Total Harmonic Distortion
The time from when a rising ENC+ equals the ENC– voltage
totheinstantthattheinputsignalisheldbythesampleand
hold circuit.
Total harmonic distortion is the ratio of the RMS sum of all
harmonicsoftheinputsignaltothefundamentalitself.The
out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:
Aperture Delay Jitter
Thevariationintheaperturedelaytimefromconversionto
conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
THD = 20Log (√(V22 + V32 + V42 + . . . Vn2)/V1)
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through Vn are the amplitudes of the
secondthroughnthharmonics. TheTHDcalculatedinthis
data sheet uses all the harmonics up to the fifth.
SNRJITTER = –20log (2π • fIN • tJITTER
)
CONVERTER OPERATION
Intermodulation Distortion
As shown in Figure 1, the LTC2220/LTC2221 is a CMOS
pipelined multistep converter. The converter has five
pipelined ADC stages; a sampled analog input will result in
a digitized value five cycles later (see the Timing Diagram
section). For optimal AC performance the analog inputs
should be driven differentially. For cost sensitive applica-
tions, the analog inputs can be driven single-ended with
slightly worse harmonic distortion. The encode input is
differential for improved common mode noise immunity.
The LTC2220/LTC2221 has two phases of operation,
determinedbythestateofthedifferentialENC+/ENC– input
pins. For brevity, the text will refer to ENC+ greater than
ENC– as ENC high and ENC+ less than ENC– as ENC low.
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at the sum and differ-
ence frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,
etc. The 3rd order intermodulation products are 2fa + fb,
2fb + fa, 2fa – fb and 2fb – fa. The intermodulation
distortion is defined as the ratio of the RMS value of either
22201fa
18
LTC2220/LTC2221
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APPLICATIO S I FOR ATIO
U
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
outputbytheresidueamplifier.Successivestagesoperate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When ENC transitions from low to high, the sampled input
voltageisheldonthesamplingcapacitors.Duringthehold
phase when ENC is high, the sampling capacitors are
disconnectedfromtheinputandtheheldvoltageispassed
to the ADC core for processing. As ENC transitions from
high to low, the inputs are reconnected to the sampling
capacitors to acquire a new sample. Since the sampling
capacitors still hold the previous sample, a charging glitch
proportionaltothechangeinvoltagebetweensampleswill
be seen at this time. If the change between the last sample
and the new sample is small, the charging glitch seen at
the input will be small. If the input change is large, such as
the change seen with input frequencies near Nyquist, then
a larger charging glitch will be seen.
WhenENCislow,theanaloginputissampleddifferentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that ENC transitions from low to high, the sampled input
is held. While ENC is high, the held input voltage is
bufferedbytheS/Hamplifierwhichdrivesthefirstpipelined
ADC stage. The first stage acquires the output of the S/H
during this high phase of ENC. When ENC goes back low,
the first stage produces its residue which is acquired by
the second stage. At the same time, the input S/H goes
back to acquiring the analog input. When ENC goes back
high, the second stage produces its residue which is
acquired by the third stage. An identical process is re-
peated for the third and fourth stages, resulting in a fourth
stage residue that is sent to the fifth stage ADC for final
evaluation.
LTC2220/LTC2221
V
DD
C
SAMPLE
1.6pF
15Ω
15Ω
+
–
A
IN
IN
C
PARASITIC
1pF
V
DD
C
SAMPLE
1.6pF
A
C
PARASITIC
1pF
V
DD
1.6V
6k
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
thattheresultscanbeproperlycombinedinthecorrection
logic before being sent to the output buffer.
+
–
ENC
ENC
6k
1.6V
22201 F02
Figure 2. Equivalent Input Circuit
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Single-Ended Input
For cost sensitive applications, the analog inputs can be
driven single-ended. With a single-ended input the har-
monic distortion and INL will degrade, but the SNR and
Figure 2 shows an equivalent circuit for the LTC2220/
LTC2221 CMOS differential sample-and-hold. The analog
inputsareconnectedtothesamplingcapacitors(CSAMPLE
through NMOS transistors. The capacitors shown at-
tached to each input (CPARASITIC) are the summation of all
other capacitance associated with each input.
+
)
DNLwillremainunchanged.Forasingle-endedinput,AIN
should be driven with the input signal and AIN– should be
connected to 1.6V or VCM
.
Common Mode Bias
During the sample phase when ENC is low, the transistors
connect the analog inputs to the sampling capacitors and
they charge to, and track the differential input voltage.
For optimal performance the analog inputs should be
driven differentially. Each input should swing ±0.5V for
22201fa
19
LTC2220/LTC2221
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APPLICATIO S I FOR ATIO
Figure 4 demonstrates the use of a differential amplifier to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides low
frequencyinputresponse;however,thelimitedgainbandwidth
of most op amps will limit the SFDR at high input frequencies.
the 2V range or ±0.25V for the 1V range, around a
common mode voltage of 1.6V. The VCM output pin (Pin
60) may be used to provide the common mode bias level.
V
CM can be tied directly to the center tap of a transformer
tosettheDCinputlevelorasareferenceleveltoanopamp
differentialdrivercircuit. TheVCM pinmustbebypassedto
ground close to the ADC with a 2.2µF or greater capacitor.
Figure 5 shows a single-ended input circuit. The imped-
ance seen by the analog inputs should be matched. This
circuit is not recommended if low distortion is required.
Input Drive Impedance
The25Ωresistorsand12pFcapacitorontheanaloginputs
serve two purposes: isolating the drive circuitry from the
sample-and-hold charging glitches and limiting the
wideband noise at the converter input. For input frequen-
cies higher than 100MHz, the capacitor may need to be
decreased to prevent excessive signal loss.
As with all high performance, high speed ADCs, the
dynamic performance of the LTC2220/LTC2221 can be
influenced by the input drive circuitry, particularly the
second and third harmonics. Source impedance and input
reactance can influence SFDR. At the falling edge of ENC,
the sample-and-hold circuit will connect the 1.6pF sam-
pling capacitor to the input pin and start the sampling
period.ThesamplingperiodendswhenENCrises,holding
the sampled input on the sampling capacitor. Ideally the
input circuitry should be fast enough to fully charge
the sampling capacitor during the sampling period
1/(2FENCODE);however, thisisnotalwayspossibleandthe
incomplete settling may degrade the SFDR. The sampling
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.
V
CM
2.2µF
0.1µF T1
+
+
25Ω
A
A
IN
1:1
ANALOG
INPUT
LTC2220/
LTC2221
0.1µF
IN
25Ω
25Ω
12pF
–
–
A
IN
IN
25Ω
A
T1 = MA/COM ETC1-1T
22201 F03
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
Figure 3. Single-Ended to Differential
Conversion Using a Transformer
For the best performance, it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
V
CM
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
2.2µF
+
+
25Ω
A
A
IN
IN
LTC2220/
LTC2221
ANALOG
INPUT
+
+
3pF
12pF
A
CM
–
–
–
–
IN
IN
Input Drive Circuits
25Ω
A
AMPLIFIER = LTC6600-20, LT1993, ETC.
22201 F04
Figure 3 shows the LTC2220/LTC2221 being driven by an
RF transformer with a center tapped secondary. The sec-
ondary center tap is DC biased with VCM, setting the ADC
input signal at its optimum DC level. Terminating on the
transformer secondary is desirable, as this provides a
common mode path for charging glitches caused by the
sample and hold. Figure 3 shows a 1:1 turns ratio trans-
former. Other turns ratios can be used if the source
impedanceseenbytheADCdoesnotexceed100Ωforeach
ADC input. A disadvantage of using a transformer is the
loss of low frequency response. Most small RF transform-
ers have poor performance at frequencies below 1MHz.
3pF
Figure 4. Differential Drive with an Amplifier
V
CM
2.2µF
1k
1k
0.1µF
LTC2220/
LTC2221
+
25Ω
A
IN
IN
IN
IN
ANALOG
INPUT
+
–
–
A
12pF
A
A
25Ω
22201 F05
0.1µF
Figure 5. Single-Ended Drive
22201fa
20
LTC2220/LTC2221
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APPLICATIO S I FOR ATIO
The AIN and AIN– inputs each have two pins to reduce
Reference Operation
+
package inductance. The two AIN+ and the two AIN– pins
should be shorted together.
Figure 9 shows the LTC2220/LTC2221 reference circuitry
consisting of a 1.6V bandgap reference, a difference
amplifier and switching and control circuit. The internal
voltage reference can be configured for two pin selectable
input ranges of 2V (±1V differential) or 1V (±0.5V differ-
ential). Tying the SENSE pin to VDD selects the 2V range;
typing the SENSE pin to VCM selects the 1V range.
For input frequencies above 100MHz the input circuits of
Figure 6, 7 and 8 are recommended. The balun trans-
former gives better high frequency response than a flux
coupled center tapped transformer. The coupling capaci-
tors allow the analog inputs to be DC biased at 1.6V. In
Figure 8 the series inductors are impedance matching
elements that maximize the ADC bandwidth.
The 1.6V bandgap reference serves two functions: its
output provides a DC bias point for setting the common
mode voltage of any external input circuitry; additionally,
the reference is used with a difference amplifier to gener-
ate the differential reference levels needed by the internal
ADC circuitry. An external bypass capacitor is required for
the 1.6V reference output, VCM. This provides a high
frequency low impedance path to ground for internal and
external circuitry.
V
CM
2.2µF
0.1µF
0.1µF
+
+
12Ω
A
IN
IN
ANALOG
INPUT
LTC2220/
LTC2221
A
8pF
A
0.1µF
25Ω
25Ω
T1
–
–
IN
IN
12Ω
A
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
22201 F06
The difference amplifier generates the high and low refer-
ence for the ADC. High speed switching circuits are
connected to these outputs and they must be externally
bypassed. Each output has four pins: two each of REFHA
and REFHB for the high reference and two each of REFLA
and REFLB for the low reference. The multiple output pins
are needed to reduce package inductance. Bypass capaci-
tors must be connected as shown in Figure 9.
Figure 6. Recommended Front End Circuit for
Input Frequencies Between 100MHz and 250MHz
V
CM
2.2µF
0.1µF
0.1µF
+
+
A
IN
ANALOG
INPUT
LTC2220/
LTC2221
A
0.1µF
IN
25Ω
25Ω
T1
LTC2220/LTC2221
–
–
A
A
IN
IN
4Ω
V
CM
1.6V BANDGAP
REFERENCE
1.6V
2.2µF
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
22201 F07
1V
0.5V
RANGE
DETECT
AND
Figure 7. Recommended Front End Circuit for
Input Frequencies Between 250MHz and 500MHz
CONTROL
TIE TO V FOR 2V RANGE;
DD
SENSE
REFLB
TIE TO V FOR 1V RANGE;
CM
RANGE = 2 • V
FOR
< 1V
SENSE
SENSE
BUFFER
0.5V < V
V
CM
INTERNAL ADC
HIGH REFERENCE
0.1µF
REFHA
1µF
2.2µF
0.1µF
0.1µF
+
+
4.7nH
0.1µF
A
IN
IN
ANALOG
INPUT
LTC2220/
LTC2221
A
2pF
A
2.2µF
25Ω
25Ω
DIFF AMP
T1
–
–
1µF
IN
IN
4.7nH
REFLA
A
0.1µF
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
INTERNAL ADC
LOW REFERENCE
22201 F08
REFHB
22201 F09
Figure 8. Recommended Front End Circuit for
Input Frequencies Above 500MHz
Figure 9. Equivalent Reference Circuit
22201fa
21
LTC2220/LTC2221
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APPLICATIO S I FOR ATIO
Other voltage ranges in between the pin selectable ranges
can be programmed with two external resistors as shown
inFigure10.Anexternalreferencecanbeusedbyapplying
its output directly or through a resistor divider to SENSE.
It is not recommended to drive the SENSE pin with a logic
device. The SENSE pin should be tied to the appropriate
levelasclosetotheconverteraspossible. IftheSENSEpin
is driven externally, it should be bypassed to ground as
close to the device as possible with a 1µF ceramic capacitor.
2. Use as large an amplitude as possible; if transformer
coupled use a higher turns ratio to increase the amplitude.
3. If the ADC is clocked with a sinusoidal signal, filter the
encode signal to reduce wideband noise.
4. Balance the capacitance and series resistance at both
encodeinputssothatanycouplednoisewillappearatboth
inputs as common mode noise. The encode inputs have a
common mode range of 1.1V to 2.5V. Each input may be
driven from ground to VDD for single-ended drive.
1.6V
V
CM
V
LTC2220/LTC2221
DD
2.2µF
12k
0.8V
LTC2220/
LTC2221
TO INTERNAL
ADC CIRCUITS
SENSE
1µF
12k
1.6V BIAS
V
V
DD
DD
22201 F10
6k
+
ENC
Figure 10. 1.6V Range ADC
0.1µF
50Ω
1:4
CLOCK
INPUT
Input Range
1.6V BIAS
6k
The input range can be set based on the application. The
2Vinputrangewillprovidethebestsignal-to-noiseperfor-
mance while maintaining excellent SFDR. The 1V input
range will have better SFDR performance, but the SNR will
degrade by 5dB. See the Typical Performance Character-
istics section.
–
ENC
22201 F11
+
–
Figure 11. Transformer Driven ENC /ENC
Maximum and Minimum Encode Rates
Driving the Encode Inputs
The maximum encode rate for the LTC2220/LTC2221 is
170Msps (LTC2220) and 135Msps (LTC2221). For the
ADC to operate properly, the encode signal should have a
50% (±5%) duty cycle. Each half cycle must have at least
2.8ns (LTC2220) or 3.5ns (LTC2221) for the ADC internal
circuitrytohaveenoughsettlingtimeforproperoperation.
Achievingaprecise50%dutycycleiseasywithdifferential
sinusoidal drive using a transformer or using symmetric
differential logic such as PECL or LVDS.
The noise performance of the LTC2220/LTC2221 can
depend on the encode signal quality as much as on the
analog input. The ENC+/ENC– inputs are intended to be
driven differentially, primarily for noise immunity from
commonmodenoisesources.Eachinputisbiasedthrough
a 6k resistor to a 1.6V bias. The bias resistors set the DC
operating point for transformer coupled drive circuits and
can set the logic threshold for single-ended drive circuits.
Any noise present on the encode signal will result in
additionalaperturejitterthatwillbeRMSsummedwiththe
inherent ADC aperture jitter.
An optional clock duty cycle stabilizer circuit can be used
if the input clock has a non 50% duty cycle. This circuit
uses the rising edge of the ENC+ pin to sample the analog
input. The falling edge of ENC+ is ignored and the internal
fallingedgeisgeneratedbyaphase-lockedloop. Theinput
In applications where jitter is critical (high input frequen-
cies) take the following into consideration:
1. Differential drive should be used.
clock duty cycle can vary from 30% to 70% and the clock
22201fa
22
LTC2220/LTC2221
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APPLICATIO S I FOR ATIO
U
duty cycle stabilizer will maintain a constant 50% internal
duty cycle. If the clock is turned off for a long period of
time, the duty cycle stabilizer circuit will require one
hundred clock cycles for the PLL to lock onto the input
clock. To use the clock duty cycle stabilizer, the MODE pin
should be connected to 1/3VDD or 2/3VDD using external
resistors.
Digital Output Modes
The LTC2220/LTC2221 can operate in several digital out-
put modes: LVDS, CMOS running at full speed, and CMOS
demultiplexed onto two buses, each of which runs at half
speed. In the demultiplexed CMOS modes the two buses
(referred to as bus A and bus B) can either be updated on
alternateclockcycles(interleavedmode)orsimultaneously
(simultaneousmode).Fordetailsontheclocktiming,refer
to the timing diagrams.
The lower limit of the LTC2220/LTC2221 sample rate is
determined by droop of the sample-and-hold circuits. The
pipelined architecture of this ADC relies on storing analog
signals on small valued capacitors. Junction leakage will
discharge the capacitors. The specified minimum operat-
ing frequency for the LTC2220/LTC2221 is 1Msps.
The LVDS pin selects which digital output mode the part
uses. This pin has a four-level logic input which should be
connected to GND, 1/3VDD, 2/3VDD or VDD. An external
resistor divider can be used to set the 1/3VDD or 2/3VDD
logic values. Table 2 shows the logic states for the LVDS
pin.
+
ENC
V
= 1.6V
THRESHOLD
–
LTC2220/
LTC2221
1.6V
ENC
Table 2. LVDS Pin Function
0.1µF
LVDS
Digital Output Mode
22201 F12Ía
GND
Full-Rate CMOS
Figure 12a. Single-Ended ENC Drive,
Not Recommended for Low Jitter
1/3V
2/3V
Demultiplexed CMOS, Simultaneous Update
Demultiplexed CMOS, Interleaved Update
LVDS
DD
DD
3.3V
V
DD
3.3V
MC100LVELT22
130Ω
Q0
130Ω
+
Digital Output Buffers (CMOS Modes)
ENC
D0
Figure 13a shows an equivalent circuit for a single output
buffer in the CMOS output mode. Each buffer is powered
by OVDD and OGND, which are isolated from the ADC
power and ground. The additional N-channel transistor in
theoutputdriverallowsoperationdowntovoltagesaslow
as 0.5V. The internal resistor in series with the output
makes the output appear as 50Ω to external circuitry and
may eliminate the need for external damping resistors.
–
LTC2220/
LTC2221
ENC
Q0
83Ω
83Ω
22201 F12b
Figure 12b. ENC Drive Using a CMOS to PECL Translator
DIGITAL OUTPUTS
Table 1. Output Codes vs Input Voltage
+
–
A
– A
D11 – D0
(Offset Binary)
D11 – D0
(2’s Complement)
IN
IN
LTC2220/LTC2221
(2V Range)
OF
OV
DD
0.5V
TO 3.6V
>+1.000000V
+0.999512V
+0.999024V
1
0
0
1111 1111 1111
1111 1111 1111
1111 1111 1110
0111 1111 1111
0111 1111 1111
0111 1111 1110
V
DD
V
DD
0.1µF
OV
DD
+0.000488V
0.000000V
–0.000488V
–0.000976V
0
0
0
0
1000 0000 0001
1000 0000 0000
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
DATA
FROM
LATCH
PREDRIVER
LOGIC
43Ω
TYPICAL
DATA
OUTPUT
OE
OGND
–0.999512V
–1.000000V
<–1.000000V
0
0
1
0000 0000 0001
0000 0000 0000
0000 0000 0000
1000 0000 0001
1000 0000 0000
1000 0000 0000
22201 F13a
Figure 13a. Digital Output Buffer in CMOS Mode
22201fa
23
LTC2220/LTC2221
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APPLICATIO S I FOR ATIO
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2220/LTC2221 should drive a
minimal capacitive load to avoid possible interaction be-
tween the digital outputs and sensitive input circuitry. The
output should be buffered with a device such as an
ALVCH16373 CMOS latch. For full speed operation the
capacitive load should be kept under 10pF.
Data Format
The LTC2220/LTC2221 parallel digital output can be se-
lected for offset binary or 2’s complement format. The
format is selected with the MODE pin. Connecting MODE
to GND or 1/3VDD selects offset binary output format.
Connecting MODE to 2/3VDD or VDD selects 2’s comple-
ment output format. An external resistor divider can be
used to set the 1/3VDD or 2/3VDD logic values. Table 3
shows the logic states for the MODE pin.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
Table 3. MODE Pin Function
Clock Duty
MODE Pin
Digital Output Buffers (LVDS Mode)
Output Format
Cycle Stablizer
Figure 13b shows an equivalent circuit for a differential
output pair in the LVDS output mode. A 3.5mA current is
steered from OUT+ to OUT– or vice versa which creates a
±350mV differential voltage across the 100Ω termination
resistor at the LVDS receiver. A feedback loop regulates
the common mode output voltage to 1.25V. For proper
operation each LVDS output pair needs an external 100Ω
termination resistor, even if the signal is not used (such as
OF+/OF– or CLKOUT+/CLKOUT–). To minimize noise the
PC board traces for each LVDS output pair should be
routedclosetogether.TominimizeclockskewallLVDSPC
board traces should have about the same length.
0
Offset Binary
Off
On
On
Off
1/3V
2/3V
Offset Binary
DD
DD
2’s Complement
2’s Complement
V
DD
Overflow Bit
An overflow output bit indicates when the converter is
overranged or underranged. In CMOS mode, a logic high
on the OFA pin indicates an overflow or underflow on the
A data bus, while a logic high on the OFB pin indicates an
overflow or underflow on the B data bus. In LVDS mode,
a differential logic high on the OF+/OF– pins indicates an
overflow or underflow.
LTC2220/LTC2221
OV
DD
Output Clock
The ADC has a delayed version of the ENC+ input available
as a digital output, CLKOUT. The CLKOUT pin can be used
tosynchronizetheconverterdatatothedigitalsystem.This
is necessary when using a sinusoidal encode. In all CMOS
modes,AbusdatawillbeupdatedjustafterCLKOUTArises
andcanbelatchedonthefallingedgeofCLKOUTA.Indemux
CMOS mode with interleaved update, B bus data will be
updatedjustafterCLKOUTBrisesandcanbelatchedonthe
falling edge of CLKOUTB. In demux CMOS mode with si-
multaneous update, B bus data will be updated just after
CLKOUTB falls and can be latched on the rising edge of
CLKOUTB. In LVDS mode, data will be updated just after
CLKOUT+/CLKOUT– rises and can be latched on the falling
edge of CLKOUT+/CLKOUT–.
D
D
D
+
OUT
–
+
10k
10k
100Ω
1.25V
LVDS
RECEIVER
–
OUT
D
3.5mA
OGND
22201 F13b
Figure 13b. Digital Output in LVDS Mode
22201fa
24
LTC2220/LTC2221
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35mW. In nap mode, the on-chip reference circuit is kept
on,sothatrecoveryfromnapmodeisfasterthanthatfrom
sleepmode,typicallytaking100clockcycles.Inbothsleep
and nap mode all digital outputs are disabled and enter the
Hi-Z state.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same power supply as for the logic being driven. For
exampleiftheconverterisdrivingaDSPpoweredbya1.8V
supply then OVDD should be tied to that same 1.8V supply.
GROUNDING AND BYPASSING
TheLTC2220/LTC2221requiresaprintedcircuitboardwith
a clean unbroken ground plane. A multilayer board with an
internal ground plane is recommended. Layout for the
printed circuit board should ensure that digital and analog
signal lines are separated as much as possible. In particu-
lar,careshouldbetakennottorunanydigitalsignalalong-
side an analog signal or underneath the ADC.
In the CMOS output mode, OVDD can be powered with any
voltageupto3.6V. OGNDcanbepoweredwithanyvoltage
from GND up to 1V and must be less than OVDD. The logic
outputs will swing between OGND and OVDD.
In the LVDS output mode, OVDD should be connected to a
3.3V supply and OGND should be connected to GND.
High quality ceramic bypass capacitors should be used at
theVDD,OVDD,VCM,REFHA,REFHB,REFLAandREFLBpins
asshownintheblockdiagramonthefrontpageofthisdata
sheet. Bypass capacitors must be located as close to the
pins as possible. Of particular importance are the capaci-
tors between REFHA and REFLB and between REFHB and
REFLA. These capacitors should be as close to the device
aspossible(1.5mmorless).Size0402ceramiccapacitors
arerecommended.The2.2µFcapacitorbetweenREFHAand
REFLAcanbesomewhatfurtheraway.Thetracesconnect-
ing the pins and bypass capacitors must be kept short and
should be made as wide as possible.
Output Enable
Theoutputsmaybedisabledwiththeoutputenablepin,OE.
In CMOS or LVDS output modes OE high disables all data
outputsincludingOFandCLKOUT.Thedataaccessandbus
relinquish times are too slow to allow the outputs to be
enabledanddisabledduringfullspeedoperation.Theoutput
Hi-Z state is intended for use during long periods of
inactivity.
TheHi-Zstateisnotatrulyopencircuit;theoutputpinsthat
make an LVDS output pair have a 20k resistance between
them. Therefore in the CMOS output mode, adjacent data
bits will have 20k resistance in between them, even in the
Hi-Z state.
The LTC2220/LTC2221 differential inputs should run par-
allel and close to each other. The input traces should be as
shortaspossibletominimizecapacitanceandtominimize
noise pickup.
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normaloperation. ConnectingSHDNtoVDD andOEtoVDD
results in sleep mode, which powers down all circuitry
includingthereferenceandtypicallydissipates1mW.When
exiting sleep mode it will take milliseconds for the output
datatobecomevalidbecausethereferencecapacitorshave
torechargeandstabilize. ConnectingSHDNtoVDD andOE
to GND results in nap mode, which typically dissipates
HEAT TRANSFER
Most of the heat generated by the LTC2220/LTC2221 is
transferred from the die through the bottom-side exposed
pad and package leads onto the printed circuit board. For
goodelectricalandthermalperformance, theexposedpad
shouldbesolderedtoalargegroundedpadonthePCboard.
It is critical that all ground pins are connected to a ground
plane of sufficient area.
22201fa
25
LTC2220/LTC2221
W U U
U
APPLICATIO S I FOR ATIO
Clock Sources for Undersampling
must be very stable, or propagation delay variation with
supply will translate into phase noise. Even though these
clock sources may be regarded as digital devices, do not
operate them on a digital supply. If your clock is also used
todrivedigitaldevicessuchasanFPGA, youshouldlocate
the oscillator, and any clock fan-out devices close to the
ADC, and give the routing to the ADC precedence. The
clock signals to the FPGA should have series termination
at the source to prevent high frequency noise from the
FPGA disturbing the substrate of the clock fan-out device.
If you use an FPGA as a programmable divider, you must
re-time the signal using the original oscillator, and the re-
timing flip-flop as well as the oscillator should be close to
the ADC, and powered with a very quiet supply.
Undersampling raises the bar on the clock source and the
higher the input frequency, the greater the sensitivity to
clock jitter or phase noise. A clock source that degrades
SNR of a full-scale signal by 1dB at 70MHz will degrade
SNR by 3dB at 140MHz, and 4.5dB at 190MHz.
In cases where absolute clock frequency accuracy is
relatively unimportant and only a single ADC is required,
a 3V canned oscillator from vendors such as Saronix or
Vectron can be placed close to the ADC and simply
connected directly to the ADC. If there is any distance to
the ADC, some source termination to reduce ringing that
mayoccurevenoverafractionofaninchisadvisable.You
must not allow the clock to overshoot the supplies or
performance will suffer. Do not filter the clock signal with
a narrow band filter unless you have a sinusoidal clock
source, as the rise and fall time artifacts present in typical
digital clock signals will be translated into phase noise.
For cases where there are multiple ADCs, or where the
clock source originates some distance away, differential
clock distribution is advisable. This is advisable both from
the perspective of EMI, but also to avoid receiving noise
from digital sources both radiated, as well as propagated
in the waveguides that exist between the layers of multi-
layer PCBs. The differential pairs must be close together,
and distanced from other signals. The differential pair
should be guarded on both sides with copper distanced at
least 3x the distance between the traces, and grounded
with vias no more than 1/4 inch apart.
The lowest phase noise oscillators have single-ended
sinusoidal outputs, and for these devices the use of a filter
close to the ADC may be beneficial. This filter should be
close to the ADC to both reduce roundtrip reflection times,
as well as reduce the susceptibility of the traces between
thefilterandtheADC. Ifyouaresensitivetoclose-inphase
noise, the power supply for oscillators and any buffers
22201fa
26
LTC2220/LTC2221
W U U
APPLICATIO S I FOR ATIO
U
22201fa
27
LTC2220/LTC2221
W U U
U
APPLICATIO S I FOR ATIO
Silkscreen Top
22201fa
28
LTC2220/LTC2221
W U U
APPLICATIO S I FOR ATIO
U
Layer 1 Component Side
Layer 2 GND Plane
22201fa
29
LTC2220/LTC2221
W U U
U
APPLICATIO S I FOR ATIO
Layer 3 Power Plane
Layer 4 Bottom Side
22201fa
30
LTC2220/LTC2221
U
PACKAGE DESCRIPTIO
UP Package
64-Lead Plastic QFN (9mm × 9mm)
(Reference LTC DWG # 05-08-1705)
0.70 ±0.05
7.15 ±0.05
8.10 ±0.05 9.50 ±0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.75 ± 0.05
R = 0.115
TYP
9 .00 ± 0.10
(4 SIDES)
63 64
0.40 ± 0.10
PIN 1 TOP MARK
(SEE NOTE 5)
1
2
PIN 1
CHAMFER
7.15 ± 0.10
(4-SIDES)
(UP64) QFN 1003
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5
2. ALL DIMENSIONS ARE IN MILLIMETERS
BOTTOM VIEW—EXPOSED PAD
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
6. DRAWING NOT TO SCALE
22201fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
31
LTC2220/LTC2221
RELATED PARTS
PART NUMBER
LTC1748
DESCRIPTION
COMMENTS
14-Bit, 80Msps, 5V ADC
14-Bit, 80Msps, 5V Wideband ADC
High Speed Differential Op Amp
76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package
Up to 500MHz IF Undersampling, 90dB SFDR
800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain
Low Distortion: –94dBc at 1MHz
LTC1750
LT1993-2
LT®1994
Low Noise, Low Distortion Fully Differential Input/
Output Amplifier/Driver
LTC2202
LTC2208
LTC2220
LTC2220-1
LTC2221
LTC2224
LTC2230
LTC2231
LTC2255
LTC2284
LT5512
16-Bit, 10Msps, 3.3V ADC, Lowest Noise
16-Bit, 130Msps, 3.3V ADC, LVDS Outputs
12-Bit, 170Msps, 3.3V ADC, LVDS Outputs
12-Bit, 185Msps, 3.3V ADC, LVDS Outputs
12-Bit, 135Msps, 3.3V ADC, LVDS Outputs
12-Bit, 135Msps, 3.3V ADC, High IF Sampling
10-Bit, 170Msps, 3.3V ADC, LVDS Outputs
10-Bit, 135Msps, 3.3V ADC, LVDS Outputs
14-Bit, 125Msps, 3V ADC, Lowest Power
14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk
DC-3GHz High Signal Level Downconverting Mixer
150mW, 81.6dB SNR, 100dB SFDR, 48-pin QFN
1250mW, 78dB SNR, 100dB SFDR, 64-pin QFN
890mW, 67.7dB SNR, 84dB SFDR, 64-pin QFN
910mW, 67.7dB SNR, 80dB SFDR, 64-pin QFN
660mW, 67.8dB SNR, 84dB SFDR, 64-pin QFN
630mW, 67.6dB SNR, 84dB SFDR, 48-pin QFN
890mW, 61.2dB SNR, 78dB SFDR, 64-pin QFN
660mW, 61.2dB SNR, 78dB SFDR, 64-pin QFN
395mW, 72.5dB SNR, 88dB SFDR, 32-pin QFN
540mW, 72.4dB SNR, 88dB SFDR, 64-pin QFN
DC to 3GHz, 21dBm IIP3, Integrated LO Buffer
LT5514
Ultralow Distortion IF Amplifier/ADC Driver with Digitally
Controlled Gain
450MHz to 1dB BW, 47dB OIP3, Digital Gain Control
10.5dB to 33dB in 1.5dB/Step
LT5515
LT5516
LT5517
LT5522
1.5GHz to 2.5GHz Direct Conversion Quadrature Demodulator High IIP3: 20dBm at 1.9GHz, Integrated LO Quadrature Generator
800MHz to 1.5GHz Direct Conversion Quadrature Demodulator High IIP3: 21.5dBm at 900MHz, Integrated LO Quadrature Generator
40MHz to 900MHz Direct Conversion Quadrature Demodulator High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator
600MHz to 2.7GHz High Linearity Downconverting Mixer
4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz. NF = 12.5dB, 50Ω
Single Ended RF and LO Ports
22201fa
LT 0106 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
32
●
●
© LINEAR TECHNOLOGY CORPORATION 2004
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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