LTC3888-1 [ADI]
Dual Loop 8-Phase Step-Down DC/DC Controller with Digital Power System Management;
| 型号： | LTC3888-1 |
| 厂家： | 
ADI |
| 描述： | Dual Loop 8-Phase Step-Down DC/DC Controller with Digital Power System Management |
| 文件： | 总110页 (文件大小：2463K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3888-1
Dual Loop 8-Phase Step-Down DC/DC
Controller with Digital Power System Management
FEATURES
DESCRIPTION
2
The LTC®3888-1 is a PMBus-compliant dual loop DC/DC
synchronous step-down switching regulator controller
with eight expandable phases supporting a wide range of
master/slave configurations. The controller uses constant
frequency current mode architecture to provide excellent
transient response and output regulation. Each PWM
master is capable of producing output voltages from 0.3V
to 3.45V with multiple phase configurations using DrMOS
devices that provide an output current monitor.
n
PMBus/I C Compliant Serial Interface
n
Monitor Voltage, Current, Temperature and Faults
n
Digitally Program V , Margins, UV, OV, Current
OUT
Limit, Soft-Start/Stop and Sequencing
n
n
n
n
n
n
n
n
n
n
n
n
n
n
Expandable to >16 Phases
External Resistor Divider Programs Output Voltage
4.5V ≤ V ≤ 26.5V, 0.3V ≤ V
≤ 3.45V
IN
OUT
0.5ꢀ Output Voltage Accuracy
Programmable PWM Loop Compensation
Accurate PolyPhase® Current Sharing
Internal EEPROM with ECC and Fault Logging
DrMOS Output Current Monitor Interface
DrMOS Temperature/Fault Bus Interface
DrMOS Gate Drive Supply Monitor
Output voltage is set with an external voltage divider.
PMBus configuration and monitoring is supported by
LTpowerPlay™ software. Programmable loop compen-
sation and built-in load step emulation facilitate setting
bandwidth based on input voltage and output load capaci-
tance. PMBus commands allow read back of input volt-
age, output voltage and current, and operating status.
Operating parameters can be set via PMBus command or
stored in internal EEPROM for use at power up. Switching
frequency, phase configuration, output current limit and
device address can also be set using external program-
ming resistors.
Load Step Emulation
Internal or External PWM Clock from 250kHz to 1MHz
52-Pin (5mm × 8mm) QFN Package
AEC-Q100 Qualified for Automotive Applications
APPLICATIONS
n
High Current Distributed Power Systems
Servers, Network and Storage Equipment
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents, including 7420359, 8786265, 8786268 and 8823352. Licensed under U.S.
Patent 7000125 and other related patents worldwide.
n
SPI
V
SET BY PMBus
OPTIONAL
OUT
TYPICAL APPLICATION
ADJUST ANALOG V
CONTROL COMPENSATION
FB
OF V
OF V
ZERO
OUT
OUT
Dual 4-phase PSM Rails
ꢓ
ꢕꢓ ꢁꢖ ꢐꢗꢓ
ꢔꢍ
ꢘꢍꢖꢉꢔꢍꢑꢀꢙ
LTC3888
•
•
•
•
ꢐ.ꢐꢊꢋ
ꢗ.ꢧꢊꢋ
ꢆꢊꢋ
LTC3888-1
LTC3888-2
•
•
•
ꢓ
ꢔꢍ
ꢔꢍꢁꢓ
ꢂꢂ
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ꢖꢚꢁ0
ꢔꢍ
0.ꢗꢓ ꢁꢖ
0.ꢗꢓ ꢁꢖ
ꢃ.ꢗꢕꢓ
ꢌꢈ
ꢔ
ꢔ
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ꢌꢈ
ꢌꢛꢍꢌꢛꢆ
ꢃ.ꢗꢕꢓ
ꢑꢁ ꢆꢐ0ꢑ
Efficiency vs Load Current
(8-Phase Using LTC7051)
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Rꢛꢋ
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ꢀ00
ꢀꢁ
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ꢀꢁꢂ ꢃ ꢄꢅꢀ
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ꢋꢣ0
ꢓ
ꢋꢣꢆ
ꢌꢝꢍꢂ
ꢇꢎꢖꢖꢏ0
ꢇꢎꢖꢖꢏꢆ
FAULT0
FAULT1
Rꢚꢍ0
ꢇꢌꢉ
ꢌꢞꢑRꢛꢏ
ꢇꢔꢍꢌ
ꢌꢂꢀ
ꢌꢏꢑ
ꢇꢉꢣꢤꢥ
Rꢚꢍꢆ
ꢍꢖꢁꢛꢜ ꢌꢖꢉꢛ ꢏꢛꢁꢑꢔꢀꢌ ꢖꢉꢔꢁꢁꢛꢏ ꢋꢖR ꢂꢀꢑRꢔꢁꢝ
ꢖꢍꢀꢝ ꢁꢈꢖ ꢖꢋ ꢛꢔꢎꢞꢁ ꢂꢞꢑꢍꢍꢛꢀꢌ ꢌꢞꢖꢈꢍ
ꢌꢞꢑRꢛꢟꢂꢀꢠ ALERT
0.ꢀꢁ
0.ꢀꢁ
ꢀ.0ꢁ
ꢀ.ꢁꢂ
ꢔ
ꢔ
ꢔ
ꢁꢞRꢆ
ꢁꢞꢆ
ꢁꢞR0
ꢁꢞ0
ꢐꢐ00ꢦꢋ
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ꢆ00ꢦꢋ
ꢆ00ꢦꢋ
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ꢏꢏꢃꢃ
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ꢆꢊꢋ
ꢎꢍꢏ
ꢀ0
0
ꢀ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀ00
ꢃꢄꢄꢄꢆꢐ ꢁꢑ0ꢆꢒ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢁꢁꢂꢃ ꢄ0ꢃ
Rev. 0
1
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LTC3888-1
TABLE OF CONTENTS
Features..................................................... 1
Applications ................................................ 1
Typical Application ........................................ 1
Description.................................................. 1
Absolute Maximum Ratings.............................. 5
Order Information.......................................... 5
Pin Configuration .......................................... 5
Electrical Characteristics................................. 6
Typical Performance Characteristics ..................10
Pin Functions..............................................13
Block Diagram.............................................15
Test Circuit.................................................16
Operation...................................................18
Overview................................................................. 18
About This Document......................................... 18
Major Product Features .......................................... 18
Main Control Loop.................................................. 19
Power-Up and Initialization ..................................... 19
Testing Integrity of Output Voltage Sense ..........21
Analog Output Voltage Control ...............................21
PMBus Output Voltage Control...............................21
Soft-Start................................................................21
Time-Based Output Sequencing .............................22
Output Ramping Control.........................................22
Voltage-Based Output Sequencing .........................22
Output Disable........................................................22
Minimum Output Disable Times .........................23
Output Short Cycle .................................................23
Switching Frequency and Phase.............................23
PolyPhase Load Sharing.........................................24
Voltage Control Loop Compensation ......................24
Load Step Emulation...............................................24
Input Supply Monitoring.........................................24
Output Voltage Sensing and Monitoring.................25
Output Current Sensing and Monitoring.................25
Temperature Sense .................................................25
Resistor Configuration Pins....................................25
Internal EEPROM with CRC.....................................26
Fault Detection........................................................26
Input Supply Faults.............................................26
Hardwired PWM Response to Power
Hardwired PWM Response to I
Faults ..........27
OUT
Hardwired PWM Response to Internal
Temperature Faults.............................................28
External Temperature Faults...............................28
Timing Faults......................................................28
External Faults....................................................28
Higher-Level Fault Handling....................................28
Status Registers and ALERT Masking.....................29
FAULT Pin I/O..........................................................29
Fault Log Operation ................................................31
Fault Log Details.................................................31
Factory Default Operation.......................................34
Serial Interface .......................................................35
Serial Bus Addressing ........................................39
Serial Bus Timeout .............................................39
Serial Communication Errors..............................39
PMBus Command Summary ............................40
PMBus Commands.............................................40
Data Formats......................................................40
Applications Information ................................45
Efficiency Considerations .......................................45
Power Stage Selection and Interface......................45
Using The VDR Monitor..........................................47
Unused TSNS Inputs ..............................................47
PWM Frequency and Inductor Selection.................47
C Selection...........................................................48
IN
OUT
C
Selection........................................................49
Programmable Loop Compensation .......................49
PCB Layout Considerations .................................... 51
Output Voltage Sensing ..........................................52
Classical Analog Output Voltage Control ................52
PMBus Output Voltage Control...............................53
Using Output Voltage Servo....................................54
Soft-Start and Stop.................................................54
Time-Based Output Sequencing and Ramping .......54
Voltage-Based Output Sequencing .........................56
PWM Frequency Synchronization...........................56
PolyPhase Operation and Load Sharing..................57
Resistor Configuration Pins....................................60
Internal Regulator Outputs......................................61
IC Junction Temperature.........................................61
Derating EEPROM Retention at Temperature..........62
Configuring Open-Drain Pins..................................62
PMBus Communication and Command Processing63
Stage Faults........................................................26
Hardwired PWM Response to Power Stage UV..27
Hardwired PWM Response to V
Power Good Indication .......................................27
Faults .........27
OUT
Rev. 0
2
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LTC3888-1
TABLE OF CONTENTS
Status and Fault Log Management .........................64
LTpowerPlay – An Interactive Digital Power GUI.....64
Interfacing to the DC1613 .......................................65
Design Example......................................................66
PMBus Command Details ...............................70
Addressing and Write Protect.................................70
PAGE ..................................................................70
PAGE_PLUS_WRITE ..........................................70
PAGE_PLUS_READ............................................71
WRITE_PROTECT...............................................71
MFR_ADDRESS .................................................72
MFR_RAIL_ADDRESS .......................................72
General Device Configuration .................................72
PMBUS_REVISION.............................................72
CAPABILITY........................................................72
MFR_CONFIG_ALL.............................................73
On, Off and Margin Control.....................................73
ON_OFF_CONFIG................................................73
OPERATION ........................................................ 74
MFR_RESET....................................................... 74
PWM Configuration ................................................75
FREQUENCY_SWITCH........................................75
MFR_CHAN_CONFIG..........................................76
MFR_PWM_CONFIG_LTC3888-1 .......................76
MFR_PWM_MODE_LTC3888-1 .........................79
MFR_PWM_COMP.............................................80
Input Voltage and Limits.........................................81
VIN_ON ..............................................................81
VIN_OFF .............................................................81
VIN_OV_FAULT_LIMIT........................................81
VIN_UV_WARN_LIMIT .......................................81
Output Voltage and Limits ......................................82
VOUT_MODE ......................................................82
VOUT_COMMAND..............................................82
VOUT_MAX ........................................................82
MFR_VOUT_MAX ...............................................83
VOUT_MARGIN_HIGH........................................83
VOUT_MARGIN_LOW.........................................83
VOUT_SCALE_LOOP ..........................................83
VOUT_OV_FAULT_LIMIT ....................................83
VOUT_OV_WARN_LIMIT....................................83
VOUT_UV_WARN_LIMIT....................................84
VOUT_UV_FAULT_LIMIT ....................................84
Output Current and Limits ......................................85
IOUT_CAL_GAIN ................................................85
MFR_LOAD_EMULATION...................................85
MFR_LOAD_EMULATION.......................................85
IOUT_OC_FAULT_LIMIT .....................................86
IOUT_OC_WARN_LIMIT.....................................86
Output Timing, Delays, and Ramping .....................87
MFR_RESTART_DELAY......................................87
TON_DELAY .......................................................87
TON_MAX_FAULT_LIMIT...................................87
VOUT_TRANSITION_RATE .................................88
TOFF_DELAY ......................................................88
TOFF_MAX_WARN_LIMIT..................................88
External Temperature and Limits............................89
MFR_TEMP_1_GAIN ...........................................89
MFR_TEMP_1_OFFSET.......................................89
OT_FAULT_LIMIT................................................89
OT_WARN_LIMIT ...............................................89
Status Reporting.....................................................90
STATUS_BYTE....................................................90
STATUS_WORD..................................................91
STATUS_VOUT ...................................................91
STATUS_IOUT ....................................................92
STATUS_INPUT..................................................92
STATUS_TEMPERATURE....................................92
STATUS_CML .....................................................93
STATUS_MFR_SPECIFIC....................................93
MFR_PADS_LTC3888-1 .....................................94
MFR_COMMON..................................................94
MFR_INFO..........................................................95
CLEAR_FAULTS..................................................95
Telemetry................................................................96
READ_VIN ..........................................................96
MFR_VIN_PEAK .................................................97
READ_VOUT.......................................................97
MFR_VOUT_PEAK ..............................................97
READ_IOUT........................................................97
MFR_IOUT_PEAK...............................................97
MFR_TOTAL_IOUT .............................................97
MFR_READ_ALL_IOUT......................................97
READ_TEMPERATURE_1 ...................................98
MFR_TEMPERATURE_1_PEAK ..........................98
READ_TEMPERATURE_2...................................98
MFR_TEMPERATURE_2_PEAK..........................98
READ_FREQUENCY............................................98
Rev. 0
3
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LTC3888-1
TABLE OF CONTENTS
MFR_CLEAR_PEAKS .........................................98
Fault Response and Communication.......................99
VIN_OV_FAULT_RESPONSE...............................99
VOUT_OV_FAULT_RESPONSE.......................... 100
VOUT_UV_FAULT_RESPONSE..........................100
IOUT_OC_FAULT_RESPONSE........................... 101
OT_FAULT_RESPONSE..................................... 102
MFR_OT_FAULT_RESPONSE ........................... 102
TON_MAX_FAULT_RESPONSE........................ 102
MFR_RETRY_DELAY........................................ 103
SMBALERT_MASK ........................................... 103
MFR_FAULT_PROPAGATE................................104
MFR_FAULT_RESPONSE.................................. 105
MFR_FAULT_LOG............................................. 105
MFR_FAULT_LOG_CLEAR................................ 105
EEPROM User Access...........................................106
STORE_USER_ALL ..........................................106
RESTORE_USER_ALL......................................106
MFR_COMPARE_USER_ALL ........................... 107
MFR_FAULT_LOG_STORE ............................... 107
MFR_EE_xxxx.................................................. 107
USER_DATA_0x ............................................... 107
Unit Identification ................................................. 107
MFR_ID ............................................................ 107
IC_DEVICE_ID.................................................. 107
MFR_SPECIAL_ID............................................ 107
Package Description ................................... 108
Typical Applications.................................... 109
Related Parts............................................ 110
Rev. 0
4
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LTC3888-1
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
(Note 1)
ꢈꢉꢊ ꢋꢌꢍꢎ
V Supply Voltage..................................... –0.3V to 40V
IN
+
V
V
, DAOUTn .................................... –0.3V to 4.2V
SENSEn
SENSEn
–
................................................... –0.3V to 0.3V
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ꢊꢎꢡꢏ
ꢊꢎꢡꢂ
ꢁ
ꢂ
ꢃꢏ
ꢃꢂ
ꢃꢁ
ꢃ0
ꢌ
ꢝꢍꢑꢝꢍꢁ
I
, V ............................................. –0.3V to 3.6V
SENSEn FBn
ꢊꢎꢡꢁ
TSNSn, VDR_MON ................................... –0.3V to 6.0V
SYNC, FAULTn, PGOODn, CLKOUT,
ꢨ
ꢩ
ꢌ
ꢌ
ꢏ
ꢋ
ꢝꢍꢑꢝꢍꢂ
ꢝꢍꢑꢝꢍꢁ
ꢃ
ꢋ
ꢝꢍꢑꢝꢍ0
ꢊꢎꢡ0
ꢨ
ꢝꢍꢑꢝꢍꢁ
ꢀ
ꢏꢄ ꢈꢝꢑꢝꢁ
SHARE_CLK.............................................. –0.3V to 3.6V
SCL, SDA, RUNn, ALERT........................... –0.3V to 5.5V
ꢋ
ꢋ
ꢇ
ꢏꢅ
ꢏꢆ
ꢏꢇ
ꢏꢀ
ꢏꢃ
ꢌ
ꢌ
ꢝꢍꢑꢝꢍ0
ꢈꢔꢁ
ꢩ
ꢆ
ꢝꢍꢑꢝꢍ0
ꢈꢔRꢁ
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ꢅ
ꢒꢕꢉꢓꢈꢁ
ꢀꢏ
INTV ...............................................................(Note 4)
CC
DD33
ꢐꢑꢒ
ꢌ
ꢄ
ꢋ
ꢈꢔꢉ
ꢟꢧꢁ
V
.................................................................(Note 5)
ꢌ
ꢁ0
ꢁꢁ
ꢁꢂ
ꢁꢏ
ꢁꢃ
ꢁꢀ
ꢊꢐꢉꢉꢒꢁ
ꢈꢔRꢉ
IREF, PWMn.......................................................(Note 6)
, I , I , R , ASELn,
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ꢋ
ꢏꢂ
ꢏꢁ
ꢏ0
ꢂꢄ
ꢂꢅ
ꢂꢆ
ꢋ
ꢟꢧ0
ꢌꢑ
V
DD25 THn THRn SET
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ꢌꢑꢈꢋ
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ꢒꢒꢏꢏ
ꢝꢔꢕRꢍꢪꢖꢙꢗ
ILIMn_CFG, PWM_CFG......................................(Note 7)
Operating Junction Temperature Range
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ꢋ
ꢝꢒꢕ ꢁꢇ
ꢋ
ꢒꢒꢂꢀ
(Notes 2, 3).......................................... –40°C to 125°C*
Storage Temperature Range ................ –65°C to 150°C*
ALERT ꢁꢆ
ꢊꢎꢡꢪꢖꢟꢐ
ꢁꢅ ꢁꢄ ꢂ0 ꢂꢁ ꢂꢂ ꢂꢏ ꢂꢃ ꢂꢀ ꢂꢇ
*See Derating EEPROM Retention at Temperature in the
Applications Information section for junction tempera-
tures in excess of 125°C.
ꢓꢔꢐ ꢊꢕꢖꢗꢕꢐꢍ
ꢀꢂꢘꢙꢍꢕꢒ ꢚꢀꢛꢛ × ꢅꢛꢛꢜ ꢊꢙꢕꢝꢈꢌꢖ ꢞꢟꢑ
ꢈ
ꢣ ꢁꢂꢀꢤꢖꢥ θ ꢣ ꢏꢇꢤꢖꢦꢎꢥ θ ꢣ ꢏ.ꢅꢤꢖꢦꢎ
ꢠꢕ ꢠꢖ
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ꢠꢡꢕꢢ
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
38881
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 125°C
LTC3888EUHG-1#PBF
LTC3888IUHG-1#PBF
AUTOMOTIVE PRODUCTS**
LTC3888IUHG-1#WPBF
LTC3888EUHG-1#TRPBF
LTC3888IUHG-1#TRPBF
52-Lead (5mm × 8mm) Plastic QFN
52-Lead (5mm × 8mm) Plastic QFN
38881
–40°C to 125°C
LTC3888IUHG-1#WTRPBF
38881
52-Lead (5mm × 8mm) Plastic QFN
–40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
these models.
Rev. 0
5
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LTC3888-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
+
–
junction temperature range, otherwise specifications are at TA = 25°C (Notes 2, 8). VIN = 12V, VSENSEn = 1V, VSENSEn = GND = 0V,
fSYNC = 500kHz (externally driven) unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
IN
Supply
l
V
IN
V
Operating Range
IN
4.5
26.5
V
I
IC Operating Current
RUN0,1 = 0V
RUN0,1 = 3.3V, C
24
28
mA
mA
Q
= 0pF
PWMn
INTV Linear Regulator Supply
CC
INTV
INTV Output Voltage
V
V
V
≥ 6V (Note 4)
5.2
V
V
CC
CC
IN
l
l
EXTV
INTV Input Voltage Range
= INTV (Note 4)
4.5
5.5
CC
CC
IN
CC
V5
PWM Undervoltage
Lockout Threshold
Rising
4.45
V
mV
UVLO
DD33
Hysteresis
300
V
Linear Regulator Supply
DD33
l
l
V
V
Output Voltage
INTV ≥ 4.5V (Note 5)
3.15
3.3
3.45
3.10
V
DD33
DD33
CC
V3
PMBus Undervoltage
Lockout Threshold
V
Rising
DD33
V
mV
UVLO
Hysteresis
275
V
Linear Regulator
DD25
V
V
Output Voltage
DD25
2.5
V
(Note 7)
DD25
PWM Control Loops
V
Regulated Feedback Voltage
Input Current
VOUT_SCALE_LOOP Not Programmed
= 0.4V
400
mV
nA
%
FB
l
l
I
V
V
FB
–100
–1.5
100
1.5
FB
FB
V
Accuracy without Servo (Note 10)
Accuracy with Servo
(Notes 9, 10, See Test Circuit)
Servo Resolution
1V ≤ V
≤ 3.45V
OUT
OUT
0.3V ≤ V
0.3V ≤ V
≤ 3.45V
≤ 3.45V
0.2
%
%
Bits
OUT
OUT
–0.5
0.5
l
l
12
R
V
Input Resistance
SENSE
30
43.3
kΩ
%/V
%
VSENSE
LINEREG
LOADREG
m
V
V
Line Regulation
Load Regulation
6V ≤ V ≤ 24V (Note 10)
–0.02
–0.1
0.02
0.1
IN
Δ
=
600mV (Note 10)
= 1.35V
TH
ITHn
g
Resolution
3
Bits
mmho
mmho
mmho
Error Amplifier g
Error Amplifier g
LSB Step Size
I
5.76
1
m(MAX)
m(MIN)
0.68
R
Resolution (nonlinear) Compensation
5
62
1
Bits
kΩ
kΩ
ITH
Resistance R
Resistance R
Compensation
TH(MAX)
TH(MIN)
l
l
I
I
Phase-to-Phase Output Current
Sharing Accuracy
I
– IREF ≥ 150mV
SENSEn
–6.5
6.5
%
%
SHARE_TOL
3
I
Input Current
1.5V ≤ I
≤ 1.9V
SENSEn
–1
3
µA
V
ISENSE
SENSEn
V
Current Monitor Reference Output
Voltage
I
= 3mA
IREF
1.52
1.68
IREF
(Note 6)
I
IREF Output Current
Source, IREF ≥ 1.52V
Sink, IREF ≤ 1.68V
–500
µA
IREF
10
–7.5
30
mA
l
l
f
t
SYNC Output Frequency Accuracy
Minimum On-Time
7.5
60
%
SYNC
MFR_PWM_MODE_LTC3888-1[3] = 1
MFR_PWM_MODE_LTC3888-1[3] = 0
ns
ns
ON(MIN)
21
Rev. 0
6
For more information www.analog.com
LTC3888-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
+
–
junction temperature range, otherwise specifications are at TA = 25°C (Notes 2, 8). VIN = 12V, VSENSEn = 1V, VSENSEn = GND = 0V,
fSYNC = 500kHz (externally driven) unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Difference Amplifiers
+
l
l
DA_V
Input Offset Voltage
Referred to V
–16
–4
16
4
mV
%
OS
SENSE
DA_GE
Gain Error
Nominal Gain at DAOUT: 1.00 (Note 10)
DA_BW
Unity-Gain Crossover Frequency
Maximum Output Current
Maximum Output Voltage
R = 40kΩ (Note 16)
25
MHz
µA
L
l
DA_I
Sourced, DAOUT = 3.45V
325
OUT
DA_V
3.45
V
MAX
Input Voltage Supervisor
N
Input ON/OFF Resolution LSB Step
Size
9
54.7
Bits
mV
VON
V
V
Full-Scale ON Threshold
28
V
ON_FS
l
Input ON/OFF Threshold Accuracy
VIN_ON ≥ 6.5V
–2
2
%
ON_TOL
Output Voltage Supervisors
Accuracy (Note 10)
l
l
V
0.5V ≤ V
1.0V ≤ V
< 1.0V (UV and OV)
≤ 3.6V (UV and OV)
–3
–2
3
2
%
%
UVOV_TOL
OUT
OUT
Output Current Supervisors
N
I
Overcurrent Limit Resolution
SENSE
7
Bits
mV
%
ILIMIT
OC_FS
OC_TOL
V
V
Full-Scale Threshold
Accuracy
I
I
– IREF
500
SENSEn
SENSEn
l
– IREF ≥ 100mV
–6.5
6.5
Gate Drive Voltage Supervisors
l
l
I
VDR_MON Input Current
UV Threshold
VDR_MON = 1.22V
–1
1
µA
V
VDR_MON
V
1.194
1.243
DR_UV
ADC Readback Telemetry (Note 11)
N
V
Readback Resolution
(Note 12)
10
Bits
%
VIN
IN
V
V
Total Unadjusted
V ≥ 4.5V
IN
IN_TUE
IN
l
Readback Error
Resolution
1
N
V
16
130
Bits
µV
VOUT
OUT
LSB Step Size
V
V
Total Unadjusted
Constant Load
(Note 12)
0.2
%
%
OUT_TUE
OUT
l
l
l
Readback Error
–0.5
–1
0.5
1
V
V
Readback Offset Voltage
Readback Resolution
300
10
µV
Bits
%
OUT_OS
OUT
OUT
OUT
OUT
N
I
I
I
ISENSE
I
I
Total Unadjusted Readback Error
Readback Offset Voltage
I
– IREF ≥ 40mV
SENSE_TUE
SENSE_OS
SENSEn
125
10
µV
N
Temperature Resolution
(Note 12)
Bits
°C
TEMP
TUE
T
Temperature Total Unadjusted
Readback Error
0.24V ≤ TSNSn ≤ 1.8V (Note 13)
–1.5
1.5
t
Update Rate (Note 14)
MFR_PWM_CONFIG_LTC3888-1[6] = 0
MFR_PWM_CONFIG_LTC3888-1[6] = 1
90
45
ms
ms
CONVERT
Internal EEPROM (Note 15)
l
l
l
Endurance
Retention
Number of Write Operations
Stored Data Retention
0°C ≤ T ≤ 85°C During All Write Operations
10,000
10
Cycles
Years
s
J
T ≤ 125°C
J
Mass Write Time STORE_USER_ALL Execution
Duration
0°C ≤ T ≤ 85°C During All Write Operations
0.2
2
J
Rev. 0
7
For more information www.analog.com
LTC3888-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
+
–
junction temperature range, otherwise specifications are at TA = 25°C (Notes 2, 8). VIN = 12V, VSENSEn = 1V, VSENSEn = GND = 0V,
fSYNC = 500kHz (externally driven) unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Inputs (SCL, SDA, RUNn, FAULTn, SYNC, SHARE_CLOCK)
l
l
V
V
V
Input High Voltage
Input Low Voltage
SCL, SDA, RUNn, FAULTn
1.25
1.8
V
V
IH
SYNC, SHARE_CLK
l
l
SCL, SDA, RUNn, FAULTn
SYNC, SHARE_CLK
0.8
0.6
V
V
IL
Input Hysteresis
SCL, SDA (Note 10)
65
mV
µA
pF
HYST
l
I
Input Leakage Current
Input Capacitance
0V ≤ SCL, SDA, RUN0, RUN1 ≤ 5.5V
(Note 16)
–5
5
IN
C
10
IN
t
Input Digital Filter Delay
FAULTn
RUNn
3
10
µs
µs
FILT
Digital Outputs (SCL, SDA, RUNn, FAULTn, SYNC, SHARE_CLOCK, ALERT, PWMn, PGOODn, CLKOUT)
l
V
Output Low Voltage
I
= 3mA: SDA, SCL,
SINK
400
300
mV
OL
FAULTn, ALERT, SYNC,
RUNn, SHARE_CLK
l
l
I
= 2mA: PWMn, PGOODn,
mV
V
SINK
CLKOUT
V
Output High Voltage
PWMn, I
= 2mA
SOURCE
2.7
OH
l
l
l
l
l
I
Output Leakage Current
0V ≤ PWMn, PGOODn ≤ V
,
DD33
–2
–2
–2
–5
–5
2
2
2
5
5
µA
µA
µA
µA
µA
LKG
0V ≤ CLKOUT ≤ V
DD33
0V ≤ FAULTn, SYNC ≤ 3.6V,
0V ≤ SHARE_CLOCK ≤ 3.6V
0V ≤ RUNn, SCL, SDA, ALERT ≤ 5.5V
t
t
PWMn Output Rise Time
PWMn Output Fall Time
C
C
= 30pF, 10% to 90%
= 30pF, 90% to 10%
5
4
ns
ns
RO
FO
LOAD
LOAD
Serial Bus Timing
l
l
f
t
Serial Bus Operating Frequency
10
400
kHz
µs
SMB
BUF
Bus Free Time Between Stop and
Start
1.3
l
t
Hold Time After (Repeated)
Start Condition. After this
Period, the First Clock is
Generated.
0.6
µs
HD,STA
l
l
t
t
t
Repeated Start Condition Setup Time
Stop Condition Setup Time
0.6
0.6
µs
µs
SU,STA
SU,STO
HD,DAT
Data Hold Time:
Receiving Data
Transmitting Data
l
l
0
0.3
ns
µs
0.9
l
l
l
l
l
l
t
t
t
t
t
t
Input Data Setup Time
Clock Low Time-Out
100
25
ns
ms
µs
µs
ns
ns
SU,DAT
TIMEOUT
LOW
HIGH
F
35
Serial Clock Low Period
Serial Clock High Period
Clock or Data Fall Time
Clock or Data Rise Time
1.3
0.6
20
10,000
90% to 10%
10% to 90%
300
300
20
R
Rev. 0
8
For more information www.analog.com
LTC3888-1
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are given relative to GND, unless
otherwise specified. Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the device. Exposure
to any Absolute Maximum Rating condition for extended periods may
affect device reliability and lifetime.
Note 8: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to GND unless otherwise
specified.
Note 9: Specified accuracy requires Servo Mode to be set with MFR_
PWM_MODE_LTC3888-1 command bit 6. VOUT_COMMAND must be
Note 2: The LTC3888-1 is tested under pulsed load conditions such that
within 5.5% of unadjusted V
Note 10: LTC3888-1 output voltage control is trimmed and measured in
.
OUT
T ≈ T . Junction temperature T is calculated in °C from the ambient
J
A
J
temperature T and power dissipation P according to the formula: T =
A
D
J
a feedback loop that servos I to a specified value using a fixed external
TH
T + (P • θ ) where θ is the package thermal impedance. Note that
A
D
JA
JA
gain of 3.5. Output accuracy may be better than that of other loop-
regulated voltages (DAOUT, VFB). Output accuracy without Servo Mode
may degrade when external gain deviates from 3.5 in the application.
Note 11: ADC tested with PWMs disabled. Comparable capability
demonstrated by in-circuit evaluations. Total unadjusted error includes all
gain and linearity errors, as well as offsets.
Note 12: Internal 32-bit calculations using 16-bit ADC results are limited to
10-bit mantissa resolution by PMBus linear 11-bit data format.
Note 13: Limits guaranteed by TSNS voltage and current measurements
during test, including ADC read backs.
Note 14: Data conversion is done in round robin fashion. If all inputs
signals are scanned, continuous in-sequence conversions result in a
typical latency of 90ms.
Note 15: The EEPROM endurance, retention and mass write times are
guaranteed by design, characterization and correlation with statistical
process controls. Minimum retention applies only for devices cycled less
than the minimum endurance specification. EEPROM read commands
(e.g. RESTORE_USER_ALL) are valid over the entire specified operating
junction temperature range.
the maximum ambient temperature consistent with these specifications
is determined by specific operating conditions in conjunction with board
layout, the rated package thermal impedance and other environmental
factors. Refer to the Applications Information section.
Note 3: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 4: Do not apply a voltage source to INTV unless shorted to V .
CC
IN
Otherwise, connect only external passive components for LTC3888-1
configuration. See Electrical Characteristics for applicable limits beyond
which permanent damage may occur.
Note 5: An external voltage source may be connected directly to V
DD33
only if the device is not powered from V or INTV . Otherwise, connect
IN
CC
only external passive components for LTC3888-1 configuration. See
Electrical Characteristics for applicable limits beyond which permanent
damage may occur.
Note 6: Do not apply a voltage source directly to these pins. See Electrical
Characteristics for applicable limits beyond which permanent damage may
occur.
Note 16: Guaranteed by design.
Note 7: Do not apply a voltage or current source directly to these pins.
Connect only external passive components for LTC3888-1 configuration
and application, otherwise permanent damage may occur.
Rev. 0
9
For more information www.analog.com
LTC3888-1
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency and Power Loss vs
Input Voltage
(4-Phase Using TDA21470)
Efficiency vs Load Current
(8-Phase Using LTC7051)
Efficiency vs Load Current
(1-Phase Using TDA21470)
ꢀ00
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢀ
ꢀ0
ꢀ
ꢀ00
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ00
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁꢂ ꢃ ꢄꢅꢀ
ꢀꢁꢂ ꢃ ꢄꢅꢀ
ꢀꢁꢂꢃ ꢄ ꢅ.0ꢀ
ꢀꢁꢂꢃ ꢄ ꢅ0ꢆ
ꢀꢁ ꢂ00ꢃꢄꢅ
Efficiency
ꢀꢁ ꢂ00ꢃꢄꢅ
ꢀꢁ ꢂ00ꢃꢄꢅ
ꢀꢁꢂeꢃ ꢄꢁꢅꢅ
ꢀ
0.ꢀꢁ
0.ꢀꢁ
ꢀ.0ꢁ
ꢀ.ꢁꢂ
ꢀ
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ
ꢀ
ꢀ
ꢀ0
ꢀꢁ
ꢀꢁ
ꢀꢁ
0
ꢀ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀ00
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀꢁꢂ ꢃꢀꢄ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢁꢁꢂꢃ ꢄ0ꢀ
ꢀꢁꢁꢁꢂꢃ ꢄ0ꢃ
ꢀꢁꢁꢁꢂꢃ ꢄ0ꢅ
Typical Output Voltage
Typical Output Voltage Distrubtion
at 25°C with Servo
Regulated Output vs Temperature
Distribution at 25°C Without Servo
ꢀꢁ00
ꢀ000
ꢀꢁ00
ꢀ000
ꢀ00
ꢀꢁ00
ꢀ.00ꢁ0
ꢀ.00ꢁꢂ
ꢀ.0000
0.ꢀꢀꢁꢂ
0.ꢀꢀꢁ0
ꢀ0ꢁꢂ ꢃꢄꢅꢆꢇ
ꢀꢁꢂꢃꢄꢅꢁꢆꢆꢇꢈꢉ ꢊ ꢋ.0ꢀ
ꢀꢁRꢂꢃ ꢄꢃꢅꢁ ꢅꢆꢀꢇꢈꢉꢁꢅ
ꢀ0ꢁꢂ ꢃꢄꢅꢆꢇ
ꢀꢁꢂꢃꢄꢅꢁꢆꢆꢇꢈꢉ ꢊ ꢋ.0ꢀ
ꢀꢁRꢂꢃ ꢄꢃꢅꢁ ꢁꢆꢇꢈꢇꢁꢅ
ꢀꢁꢂꢃꢄꢅꢁꢆꢆꢇꢈꢉ ꢊ ꢋ.0ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢄꢈꢁꢁꢊ ꢋ ꢌ.ꢍ
ꢀꢁRꢂꢃ ꢄꢃꢅꢁ ꢅꢆꢀꢇꢈꢉꢁꢅ
ꢀ000
ꢀꢁ00
ꢀ000
ꢀ00
0
0
ꢀꢁ0 ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ0
ꢀꢁ ꢀꢁ.ꢂꢀꢁ.ꢂꢀ0.ꢁꢀ0.ꢁ 0.0 0.ꢀ 0.ꢀ ꢀ.ꢁ ꢀ.ꢁ
ꢀ
ꢀꢁ0 ꢀꢁ0
0
ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ00 ꢀꢁ0
ꢀ
ꢀRRꢁR ꢂꢃꢄꢅ
ꢀ
ꢀRRꢁR ꢂꢃꢄꢅ
ꢀꢁꢂ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂ
ꢀꢁꢁꢁꢂꢃ ꢄ0ꢅ
ꢀꢁꢁꢁꢂꢃ ꢄ0ꢅ
ꢀꢁꢁꢁꢂꢃ ꢄ0ꢅ
4-Phase Load Step Response
(Using TDA21470)
Emulated 4-Phase Load Step
Response (Using TDA21470)
4-Phase Single Cycle Response
(Using TDA21470 with COUT = 4mF)
ꢀ
ꢁꢂꢃ
ꢀ
ꢀ
ꢁꢂꢃ
ꢁꢂꢃ
ꢀ0ꢁꢂꢃꢄꢅꢂ
ꢀ0ꢁꢂꢃꢄꢅꢂ
ꢀ0ꢁꢂꢃꢄꢅꢂ
ꢀꢁꢂ
ꢀ00ꢁꢂꢃꢄꢅꢂ
ꢀꢁꢂ
ꢀ00ꢁꢂꢃꢄꢅꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢁ
ꢀꢁꢂꢃꢄ
ꢀ0ꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃꢄ
ꢀ0ꢁꢂꢃꢄꢅꢂ
ꢀ
ꢀ
ꢀ
ꢁꢂꢃ
ꢁꢂꢃ
ꢁꢂꢃ
ꢀ0ꢁꢂꢃꢄꢅ
ꢀ0ꢁꢂꢃꢄꢅ
ꢀ0ꢁꢂꢃꢄꢅ
ꢀꢁꢁꢁꢂꢃ ꢄ0ꢁ
ꢀꢁꢁꢁꢂꢃ ꢄ0ꢅ
ꢀꢁꢁꢁꢂꢃ ꢄ0ꢅ
50μs/DIV
2μs/DIV
50μs/DIV
ꢀ
ꢀ
ꢃ ꢄꢅꢀ
ꢃ ꢄ.0ꢀ
ꢀ
ꢀ
ꢃ ꢄꢅꢀ
ꢃ ꢄ.0ꢀ
ꢀ
ꢀ
ꢃ ꢄꢅꢀ
ꢃ ꢄ.0ꢀ
ꢁꢂ
ꢆꢇꢈ
ꢁꢂ
ꢆꢇꢈ
ꢁꢂ
ꢆꢇꢈ
ꢉꢊRꢋꢌꢆꢍꢎꢋꢏꢉꢇꢌꢍꢈꢁꢆꢂ ꢃ ꢄ0ꢍꢐꢑꢒꢍꢓꢏ
ꢉꢊꢂꢋ ꢃ ꢌ00ꢍꢎꢏ
ꢐ ꢃ ꢅꢄꢌꢑꢎ
ꢄ0ꢉ ꢈꢆ ꢊ0ꢉ ꢋꢈꢌꢍ
Rev. 0
10
For more information www.analog.com
LTC3888-1
TYPICAL PERFORMANCE CHARACTERISTICS
8-Phase DC Output Current
Sharing (Using TDA21470)
4-Phase Dynamic Load Sharing
4-Phase Dynamic Load Sharing
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀꢁꢂꢃꢄ 0
ꢀꢁꢂꢃꢄ ꢅ
ꢀꢁꢂꢃꢄ ꢅ
ꢀꢁꢂꢃꢄ ꢅ
ꢀꢁꢂꢃꢄ ꢅ
ꢀꢁꢂꢃꢄ ꢅ
ꢀꢁꢂꢃꢄ ꢅ
ꢀꢁꢂꢃꢄ ꢅ
ꢀꢁꢂꢃꢄꢅꢆR
ꢄꢃRRꢇꢁꢅ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃꢄꢅꢆR
ꢄꢃRRꢇꢁꢅ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢁꢁꢂꢃ ꢄꢃꢃ
ꢀꢁꢁꢁꢂꢃ ꢄꢃꢅ
2μs/DIV
2μs/DIV
ꢀ
ꢀ
ꢃ ꢄꢅꢀ
ꢃ ꢄ.0ꢀ
ꢀ
ꢀ
ꢃ ꢄꢅꢀ
ꢃ ꢄ.0ꢀ
ꢁꢂ
ꢆꢇꢈ
ꢁꢂ
ꢆꢇꢈ
0
0
ꢀ0
ꢀ0
ꢀꢁ0
ꢀꢁ0
ꢀ00
ꢀꢁ0
ꢉꢊꢂꢋ ꢃ ꢌ00ꢍꢎꢏ
ꢐ ꢃ ꢅꢄꢌꢑꢎ
ꢉꢊꢂꢋ ꢃ ꢌ00ꢍꢎꢏ
ꢐ ꢃ ꢅꢄꢌꢑꢎ
ꢀꢁꢀꢂꢃ Rꢂꢄꢃ ꢅꢆRRꢇꢈꢀ ꢉꢂꢊ
ꢀꢁꢁꢁꢂꢃ ꢄꢃ0
Typical Distribution of Slave IOUT
Offset (Not Including DrMOS
Mismatch) Room
Typical Distribution of Slave IOUT
Offset (Not Including DrMOS
Mismatch) Hot
Typical Distribution of Slave IOUT
Offset (Not Including DrMOS
Mismatch) Cold
ꢀ000
ꢀ000
ꢀ000
ꢀ000
ꢀ000
ꢀ000
ꢀ000
ꢀ000
0
ꢀ000
ꢀ000
ꢀ000
ꢀ000
ꢀ000
ꢀ000
ꢀ000
ꢀ000
0
ꢀ000
ꢀ000
ꢀ000
ꢀ000
ꢀ000
ꢀ000
ꢀ000
ꢀ000
0
ꢀꢁꢁ ꢂ ꢃꢄꢀꢅꢆꢅ
ꢀ0ꢁꢂ ꢃꢄꢅꢆꢇ
ꢀꢁꢁ ꢂ ꢃꢄꢀꢅꢆꢅ
ꢀꢁꢀ ꢂꢃꢄꢅꢆ
ꢀꢁꢁ ꢂ ꢃꢄꢀꢅꢆꢅ
ꢀ0ꢁꢂ ꢃꢄꢅꢆꢇ
ꢀRꢁꢂ ꢃ ꢄꢁꢅꢆ
ꢀRꢁꢂ ꢃ ꢄꢁꢅꢆ
ꢀRꢁꢂ ꢃ ꢄꢁꢅꢆ
ꢀ
ꢀ ꢁꢂꢃꢄꢅ
ꢀ ꢀ ꢁꢂ0ꢃꢄ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀ
ꢀ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁꢁꢂꢃꢄ ꢄꢀ ꢅꢆꢃꢇꢈ ꢉꢊꢋꢌ
ꢀ
ꢀꢁꢂꢀꢁ
ꢀꢁꢁꢂꢃꢄ ꢄꢀ ꢅꢆꢃꢇꢈ ꢉꢊꢋꢌ
ꢀ
ꢀꢁꢁꢂꢃꢄ ꢄꢀ ꢅꢆꢃꢇꢈ ꢉꢊꢋꢌ
ꢀꢁꢂꢀꢁ
ꢀꢁꢂꢀꢁ
ꢀꢁꢁꢁꢂꢃ ꢄꢃꢅ
ꢀꢁꢁꢁꢂꢃ ꢄꢃꢅ
ꢀꢁꢁꢁꢂꢃ ꢄꢃꢀ
4+4 Channel Crosstalk (Using
TDA21470)
Soft-Start Ramp
Start-Up Into a Prebiased Load
ꢀ
ꢁꢂꢃ
ꢀ
ꢁꢂꢃ0
0.ꢀꢁ ꢂRꢃꢄꢅꢆꢇ
ꢀ0ꢁꢂꢃꢄꢅꢂ
ꢀ
ꢁꢂꢃ
0.ꢄꢀꢅꢆꢇꢀ
ꢀ
ꢁꢂꢃꢄ
ꢀ0ꢁꢂꢃꢄꢅꢂ
ꢀ
ꢁꢂꢃꢄ
Rꢀꢁ
ꢂꢃꢄꢅꢆꢃ
ꢀꢁꢂꢃꢄꢁ
ꢀ
ꢁꢂꢃ0
ꢀ0ꢁꢂꢃꢄꢁ
ꢀꢁꢁꢁꢂꢃ ꢄꢃꢁ
ꢀꢁꢁꢁꢂꢃ ꢄꢃꢅ
ꢀꢁꢁꢁꢂꢃ ꢄꢃꢅ
100μs/DIV
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢁꢆꢆꢇꢈꢉ ꢊ ꢋ.0ꢀ
ꢀꢁꢂꢃꢄꢃRꢇꢈꢌꢍꢃꢍꢁꢈꢄRꢇꢃꢎ ꢊ 0.ꢋꢀꢏꢐꢑ
ꢀꢁꢂꢃꢄꢅꢁꢆꢆꢇꢈꢉ ꢊ ꢋ.0ꢀ
ꢀꢁꢂꢃꢄꢃRꢇꢈꢌꢍꢃꢍꢁꢈꢄRꢇꢃꢎ ꢊ 0.ꢋꢀꢏꢐꢑ
ꢃꢁꢈꢄꢉꢎꢒꢇꢓ ꢊ ꢔꢐꢑ
Rev. 0
11
For more information www.analog.com
LTC3888-1
TYPICAL PERFORMANCE CHARACTERISTICS
Output Overvoltage Threshold
V
OUT ADC TUE
Error vs Temperature
VIN ADC TUE
0.ꢍꢎ
0.ꢏꢐ
0.ꢏꢍ
0.0ꢑ
0
ꢀ
ꢀ
ꢀ00.0
ꢀꢁ.0
ꢀꢁꢂꢃꢄꢁꢀꢄꢅꢆꢂꢇꢃꢄꢇꢈꢉꢈꢃ ꢊ ꢋ.ꢋꢀ
ꢀ0.0
ꢀꢁ.0
0
0
ꢒ0.0ꢑ
ꢒ0.ꢏꢍ
ꢒ0.ꢏꢐ
ꢒ0.ꢍꢎ
ꢀꢁꢂ.0
ꢀꢁ0.0
ꢀꢁꢂ.0
ꢀꢁ00.0
ꢀꢁ
ꢀꢁꢂꢃe ꢄꢅe ꢆꢇ ꢈꢉꢊꢅꢋ ꢌꢍꢍ ꢎꢇꢏꢐꢂꢆ
ꢀꢁ
ꢀꢁ0 ꢀꢁ0
0
ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ00 ꢀꢁ0
0.ꢆ 0.ꢑ 0.ꢖ ꢏ.ꢍ ꢏ.ꢗ ꢏ.ꢐ ꢍ.ꢏ ꢍ.ꢎ ꢍ.ꢓ ꢆ.0 ꢆ.ꢆ
ꢄꢀꢅ
0
ꢀ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂ ꢃꢀꢄ
ꢀ
ꢁꢂꢃ
ꢀꢁꢁꢁꢂꢃ ꢄꢃꢅ
ꢀꢁꢁꢁꢂꢃ ꢄꢅ0
ꢆꢐꢐꢐꢔꢏ ꢕꢍꢏ
Temperature ADC TUE (Not
including DRMOS Error)
IOUT ADC TUE
ꢀ.ꢁ
ꢓ0
ꢎꢍ
ꢎ0
ꢀ.0
0.ꢀ
ꢍ
0
0
ꢔꢍ
ꢀ0.ꢁ
ꢀꢁ.0
ꢀꢁ.ꢂ
ꢔꢎ0
ꢔꢎꢍ
ꢔꢓ0
ꢀꢁꢂꢃe ꢄꢅe ꢆꢇ ꢈꢉꢊꢅꢋ ꢌꢍꢍ ꢎꢇꢏꢐꢂꢆ
ꢀꢁ0 ꢀꢁ0
0
ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ00 ꢀꢁ0
ꢓꢍ
0
ꢎꢓ.ꢍ
ꢏꢕ.ꢍ
ꢍ0
ꢀꢁꢂꢃꢀꢄ ꢂꢅꢆꢇꢅRꢀꢂꢃRꢅ ꢈꢉꢁꢊ
ꢀꢁꢂꢃꢁꢂ ꢄꢁRRꢅꢆꢂ ꢇꢈꢉ
ꢀꢁꢁꢁꢂꢃ ꢄꢅꢀ
ꢏꢐꢐꢐꢑꢎ ꢒꢓꢓ
4-Phase Line Step Transient
(Using TDA21470)
Programmable RITH
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀ
ꢁꢂ
ꢀꢁ ꢂꢃꢄꢅꢄꢆꢇꢇꢈ
ꢃꢀꢄꢅꢁꢀ
ꢀ
ꢁꢂꢃ
ꢄ0ꢅꢀꢆꢇꢈꢀ
ꢀꢁꢁꢁꢂꢃ ꢄꢅꢆ
200μs/DIV
0
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁꢁꢁꢂꢃ ꢄꢅꢆ
Rev. 0
12
For more information www.analog.com
LTC3888-1
PIN FUNCTIONS
PWMn (Pin 1, 2, 5, 42, 45, 46, 49, 50): PWM Control
Outputs. These eight pins provide 3.3V three-state PWM
switching control for each phase. Leave these pins open
if not used.
VFB0/VFB1 (Pin 12/Pin 35): Error Amplifier Inverting Input.
The PWM control loop regulates this voltage when the
output rail is on.
PGOOD0/PGOOD1 (Pin 13/Pin 34): Power Good Indicator
Open-Drain Outputs. These outputs are driven low through
an 80μs filter when the respective channel output is below
its programmed UV fault limit or above its programmed
OV fault limit. If used, a pull-up resistor is required in the
application.
I
(Pin 3, 4, 43, 44, 47, 48, 51, 52): Current Sense
SENSEn
Inputs. These eight inputs connect to the current moni-
tor outputs of DrMOS devices. Short these pins to IREF
if not used.
–
–
V
/V
(Pin 6/Pin 41): Differential Amplifier
SENSE0
SENSE1
and ADC Output Voltage Sense Negative Inputs. Short
these pins to GND if not used.
CLKOUT (Pin 13): Expansion Clock Output. This output
provides a phase expansion clock to a second LTC3888-1
if bit 3 of MFR_PWM_ CONFIG_LTC3888-1 is set. If used,
a pull-up resistor is required. Minimize the capacitance
on this line to ensure its time constant is fast enough for
the application.
+
+
V
/V
(Pin 7/Pin 40): Differential Amplifier
SENSE0
SENSE1
and ADC Output Voltage Sense Positive Inputs. Short
these pins to V
–
if not used.
SENSE
TSNS0/TSNS1 (Pin 8/Pin 39): External Temperature
Sense Inputs. Connect these pins to the shared tempera-
ture/fault bus of DrMOS devices, otherwise refer to the
Applications Information section for more detail.
SYNC (Pin 14): External Clock Synchronization Input and
Open-Drain Output. If desired, an external clock can be
applied to this pin to synchronize the internal PWM chan-
nels. Otherwise this pin can pull to ground at the selected
PWM switching frequency with a 500ns pulse width. A
pull-up resistor to 3.3V is required if SYNC is provided by
the LTC3888-1. Minimize the capacitance on this line to
ensure its time constant is fast enough for the application.
VDR_MON (Pin 8): External Gate Drive Voltage Sense
Input. This pin can be programmed to monitor the gate
drive voltage the system is providing to external DrMOS
power stages. Refer to MFR_CHAN_CONFIG command
details.
SCL (Pin 15): Serial Bus Clock Input and Open-Drain
Output. SCL functions as an output only if clock stretch-
ing is enabled. A pull-up resistor to the bus supply is
required in the application.
I /I (Pin 9/Pin 38): PWM Current Control Threshold
TH0 TH1
and Loop Compensation Nodes. Peak current increases
with ITH voltage. Attach a low ESR capacitor between
these pins and GND for adequate loop compensation.
Refer to the Applications Information section for more
details.
SDA (Pin 16): Serial Bus Data Input and Open-Drain
Output. A pull-up resistor to the bus supply is required
in the application.
I
/I
(Pin 10/Pin 37): Loop Compensation Nodes.
THR0 THR1
ALERT (Pin 17): Open-Drain Status Output. This pin may
be connected to the system SMBALERT# wire-AND inter-
rupt signal. A pull-up resistor to the bus supply is required
in the application. This pin should be left open if not used.
Attach a low ESR capacitor between these pins and GND
for adequate loop compensation. Refer to the Applications
Information section for more details.
DAOUT0/DAOUT1 (Pin 11/Pin 36): Differential Amplifier
FAULT0/FAULT1 (Pin 18/Pin 19): Programmable Digital
Inputs and Open-Drain Outputs for Fault Sharing. These
pins are used for channel-to-channel fault communication
and propagation. A pull-up resistor to 3.3V is required in
the application.
Outputs. DAOUT0/1 provide a voltage equal to the dif-
ference between V + and V
SENSE
– for that channel,
SENSE
referenced to GND (paddle). Leave these pins open if not
used.
Rev. 0
13
For more information www.analog.com
LTC3888-1
PIN FUNCTIONS
RUN0/RUN1 (Pin 20/Pin 21): Run Control Inputs and
Open-Drain Outputs. A voltage above 2V is required on
these pins to enable the respective PWM master chan-
nel. The LTC3888-1 may drive these pins low under cer-
tain reset/restart conditions regardless of any PMBus
command settings. A pullup resistor is required in the
application.
SHARE_CLK (Pin 29): Share Clock Input and Open-
Drain Output. Share clock, nominally 100kHz, is used to
sequence multiple rails in a power system utilizing more
than one ADI PMBus controller. A pull-up resistor to 3.3V
is required in the application. Minimize the capacitance
on this line to ensure the time constant is fast enough for
the application.
R
(Pin 22): Resistor Configuration Set Input. Connect
V
(Pin 30): Internal 3.3V Regulator Output. Bypass
DD33
SET
a 1% 18.7kΩ resistor between this pin and GND to set
the selection values for the configuration resistors for
programming bus address, output current limit and other
this pin to GND with a low ESR capacitor (1µF to 2.2µF).
The LTC3888-1 may also be powered from an external
3.3V source attached to this pin for programming pur-
poses only, if the device is otherwise unpowered. Connect
only external passive components for LTC3888-1 configu-
ration and application.
PWM settings. Refer to the Applications Information sec
tion for more details.
-
ASEL0/ASEL1 (Pin 23, Pin 24): Serial Bus Address Select
Inputs. Connect optional 1% resistors between these pins
and GND to select the serial bus interface address. Refer
to the Applications Information section for more detail.
INTV (Pin 31): 5.2V Regulator Output. Bypass this pin
CC
to GND with a low ESR 4.7μF capacitor. Connect only
external passive components for LTC3888-1 configura-
tion and application.
ILIM0_CFG/ILIM1_CFG (Pin 25/Pin 26): Output Current
Limit Configuration Inputs. Connect optional 1% resis-
tors between these pins and GND to select the output
current limit for each channel. Refer to the Applications
Information section for more detail.
V (Pin 32): Main Input Supply. Decouple this pin to GND
IN
with a low ESR capacitor (0.1µF to 2.2µF). In applications
where VIN will always operate below 6V, short this pin and
INTV together.
CC
PWM_CFG (Pin 27): PWM Configuration Input. Connect
an optional 1% resistor between this pin and GND to con-
figure PWM switching frequency and master/slave con-
figuration. Refer to the Applications Information section
for more detail.
IREF (Pin 33): DrMOS Current Sense Reference. This
voltage output provides reference bias for floating current
monitors from DrMOS devices. Decouple this pin to GND
(exposed pad) at the LTC3888-1 and each power stage
with 100nF to 1μF using low ESR capacitors.
V
(Pin 28): Internal 2.5V Regulator Output. Bypass
GND (Exposed Pad Pin 53): Ground. All small-signal and
compensation components should connect to this pad.
The exposed pad must be soldered to a suitable PCB cop-
per ground plane for proper electrical operation and to
obtain the specified package thermal resistance.
DD25
this pin to GND with a low ESR 1μF capacitor. Do not load
this pin with external current.
Rev. 0
14
For more information www.analog.com
LTC3888-1
BLOCK DIAGRAM
Rꢎꢐ
ꢖ
ꢄꢋ
Rꢆꢐ
ꢌꢌꢕRꢎꢐ
Rꢜꢈꢎꢋꢛꢄꢏ
ꢄꢋꢅꢌRꢋꢆꢍ ꢇꢆꢅꢆ ꢃꢑꢘ
ꢘꢊꢆRꢌꢜꢈꢍꢝ
ꢐꢈꢑ ꢆꢋꢇ
ꢈꢑꢘꢅꢎꢐ
ꢍꢎꢏꢄꢈ
ꢖ
ꢛꢃ0ꢚꢀ
ꢕꢐꢃꢡꢢ
ꢔ.ꢗꢖ
RꢌꢏꢑꢍꢆꢅꢎR
Rꢑꢋ0ꢚꢀ
ꢄ
ꢘꢌꢋꢘꢌ0ꢚꢀ
FAULT0ꢀ1
ꢐꢆꢘꢅꢌRꢘ
ꢕꢣꢐ0
ꢕꢣꢐꢀ
ꢄ
ꢅꢊR0ꢚꢀ
ꢘꢞꢋꢈ
ꢕꢍꢍ
ꢄ
ꢅꢊ0ꢚꢀ
ꢈꢍꢝꢎꢑꢅ
ꢕꢣꢐ0ꢚꢀ
ꢟ
ꢖ
ꢖ
ꢘꢌꢋꢘꢌ0ꢚꢀ
ꢘꢌꢋꢘꢌ0ꢚꢀ
ꢀꢒ
ꢕꢏꢎꢎꢇ0ꢚꢀ
ꢠ
ꢐꢆꢘꢅꢌRꢚꢘꢍꢆꢖꢌ
ꢈꢎꢋꢛꢄꢏꢑRꢆꢅꢄꢎꢋ
ꢖꢇRꢜꢐꢎꢋ
ꢥꢦꢧꢨꢩꢦꢪꢫꢬꢭ
ꢇꢆꢎꢑꢅ0ꢚꢀ
ꢖ
ꢇꢇꢉꢉ
ꢘꢍꢆꢖꢌꢘ
ꢕꢣꢐꢔ
ꢕꢣꢐꢉ
ꢕꢣꢐꢤ
ꢕꢣꢐꢗ
ꢕꢣꢐꢁ
ꢕꢣꢐꢙ
ꢖ
Rꢌꢛ
ꢖꢎꢍꢅꢆꢏꢌ
ꢉ.ꢉꢖ
RꢌꢏꢑꢍꢆꢅꢎR
ꢄ
ꢄꢋꢅꢖ
ꢈꢈ
ꢘꢌꢋꢘꢌꢔꢂꢙ
RꢌꢛꢌRꢌꢋꢈꢌ
ꢗ.ꢔꢖ
RꢌꢏꢑꢍꢆꢅꢎR
ꢕꢣꢐꢔꢂꢙ
ꢃꢄꢆꢘ ꢆꢋꢇ
ꢊꢎꢑꢘꢌꢝꢌꢌꢕꢄꢋꢏ
ꢖ
ꢄꢋ
ꢏꢆꢄꢋ
ꢄRꢌꢛ
ꢖ
ꢖ
ꢘꢌꢋꢘꢌ0
ꢘꢌꢋꢘꢌꢀ
ꢀꢁꢂꢃꢄꢅ
ꢆꢇꢈ
ꢀꢉ
ꢈꢊꢆꢋꢋꢌꢍ
ꢆꢋꢆꢍꢎꢏ
ꢐꢑꢒ
ꢄ
ꢘꢌꢋꢘꢌ0ꢂꢙꢚ
ꢄꢋꢅꢌRꢋꢆꢍ
ꢅꢌꢐꢕꢌRꢆꢅꢑRꢌ
ꢄ
Rꢌꢛ
ꢅꢘꢋꢘꢀ
ꢅꢘꢋꢘ0
ꢥꢦꢧꢨꢩꢦꢪꢫꢬꢭ
ꢉꢓꢓꢓꢀꢔ ꢃꢇꢀ
LTC3888-1 Block Diagram
Rev. 0
15
For more information www.analog.com
LTC3888-1
TEST CIRCUIT
ꢘꢆꢖꢛꢜꢜꢜꢙꢁ
ꢁ.ꢂꢂꢉ
ꢉ
R
ꢁꢂꢙꢋꢅꢆ
ꢎꢚꢑ
ꢎꢅꢌꢅꢆꢑꢘ
ꢄ
ꢃ
ꢐꢑ
ꢁꢟ
ꢃ
ꢄ
ꢌꢍꢎ
ꢓꢛ
ꢉ
ꢉ
ꢎꢑꢈꢒꢆ0
ꢁꢁ
ꢉ
ꢅ
ꢆꢇꢈ
ꢏꢐꢍꢏꢐ0
ꢏꢐꢍꢏꢐ0
ꢊꢋ0
ꢝ
ꢀ
ꢞ
ꢁꢂ
ꢂ.ꢓR
R
ꢄ
ꢃ
ꢘꢆꢖꢁ0ꢓꢓ
ꢂꢉ
ꢆꢑRꢌꢐꢆ ꢔ ꢉꢈꢒꢆꢕꢖꢈꢗꢗꢑꢍꢎ
ꢛꢜꢜꢜꢁꢂ ꢆꢖ
Rev. 0
16
For more information www.analog.com
LTC3888-1
TIMING DIAGRAM
ꢀꢁꢂ
ꢅ
ꢓ
ꢅ
ꢀꢊꢇꢁꢂꢈꢉ
ꢅ
ꢅ
ꢀꢍ
ꢅ
ꢓ
ꢆꢁꢇꢀꢁꢂꢉ
ꢅ
ꢅ
ꢅ
ꢅ
ꢔ
ꢎꢊꢏ
ꢔ
ꢄꢋꢌ
ꢀꢃꢄ
ꢅ
ꢅ
ꢅ
ꢀꢊꢇꢀꢈꢋꢉ
ꢆꢁꢇꢀꢈꢂꢉ
ꢀꢊꢇꢀꢈꢂꢉ
ꢅ
ꢅ
ꢆꢑꢕꢆ
ꢆꢁꢇꢁꢂꢈꢉ
ꢖꢗꢗꢗꢘꢙ ꢈꢁ
ꢀꢈꢂRꢈ
ꢃꢋꢐꢁꢑꢈꢑꢋꢐ
Rꢒꢍꢒꢂꢈꢒꢁ ꢀꢈꢂRꢈ
ꢃꢋꢐꢁꢑꢈꢑꢋꢐ
ꢀꢈꢋꢍ
ꢀꢈꢂRꢈ
ꢃꢋꢐꢁꢑꢈꢑꢋꢐ ꢃꢋꢐꢁꢑꢈꢑꢋꢐ
Rev. 0
17
For more information www.analog.com
LTC3888-1
OPERATION
OVERVIEW
group of slaves it controls to produce a single output
voltage, including multiple master channels with wire-OR
TH
The LTC3888-1 is a constant frequency analog current
mode controller for DC/DC step-down switch-mode appli-
cations. It provides up to two independent voltage loops
(masters) and also contains six additional slave modula-
tors, affording a wide range of predetermined PolyPhase
configurations.
I
control.
The phrase operating memory or simply RAM refers to
volatile onboard RAM holding PMBus commands during
operation.
PMBus commands in this document are given in all
capital letters with no white space, although hyphens or
underscores may be included. For brevity, the indentify-
ing phrase PMBus command is most often omitted when
this typeface appears. All PMBus commands from 0x00
through 0xFF not listed in Table 7 are implicitly not
supported by the LTC3888-1. Writing to any command
not listed in this table may result in a CML fault and/or
undesired operation of the part.
The device is designed to be used with external power
stages that provide an output current monitor, either as a
voltage or current. This includes higher level integrations
such as non-isolated power blocks. The LTC3888-1 pro-
vides a direct interface to the shared temperature and fault
indication bus commonly found on such power stages,
as well as an optional DrMOS gate drive supply voltage
supervisor.
The chip operates from a V power supply between 4.5V
IN
MAJOR PRODUCT FEATURES
and 28.5V. Without any other programming, output volt-
age may be set to any value between 0.4V and 3.45V
using an external resistor divider and the factory EEPROM
settings.
• Analog and/or Digitally Programmable Output Voltage
with UV/OV Supervisors
• Digitally Programmable Output Current Limit
• Digitally Programmable Input Voltage Supervisor
• Digitally Programmable Switching Frequency
• Digitally Programmable On and Off Delay Times
• Digitally Programmable Soft-Start/Stop
• Digitally Programmable Load Step Emulation
• Operating Condition Telemetry
The LTC3888-1 also features a PMBus compliant digital
interface for monitoring and setting of important power
system parameters, including direct output control using
the external resistor divider, if desired.
About This Document
PMBus command pages 0 and 1 control the two volt-
age regulation loops associated with PWM0 and PWM1,
respectively. In this document, these may also be referred
to as masters or master channels. There are often unique
IC pins associated with each of these master channels,
• Phase-Locked Loop for Synchronous PolyPhase
Operation
such as I
and I . In cases where discussion applies
TH0
TH1
• Non-Volatile Configuration Memory
to both or either of the master channels, these pin names
• Optional External Configuration Resistors for Key
Operating Parameters
may appear without index.
PWM2 to PWM7 are not directly controlled by PMBus
operation, but instead are managed by the master chan-
nel that is assigned to control them. In this document,
the modulators associated with PWM2 to PWM7 will be
referred to as slaves or slave channels. Occasionally the
term PWM or channel may apply to any of the eight PWM
modulators. Rail will designate a master channel and the
• Optional Time-Base Interconnect for Synchronization
Between Multiple Controllers
• Fault Event Data Logging
• Capable of Standalone Operation via EEPROM
Configuration
• PMBus Revision 1.2 Compliant Interface up to 400kHz
Rev. 0
18
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LTC3888-1
OPERATION
The PMBus interface provides access to important power
management data during system operation including:
the PWM duty cycle to match the V voltage to the EA
FB
positive terminal voltage.
• Average Input Voltage
The positive terminal of EA is connected to the output of a
12-bit DAC with values ranging from 0V to approximately
1.22V. The DAC value is determined by command values
retrieved from internal EEPROM or by a combination of
PMBus commands to synthesize the desired output volt-
age. The factory default EEPROM sets the value of this
DAC output to 400mV. The EA then regulates the output
voltage based on the ratio of external resistors R1 and R2.
• Average Output Voltages
• Average Output Currents
• PWM Operating Frequency
• Internal Device Temperature
• External Sensed Temperatures
+
• Warning and Fault Status, Including Input and Output
Undervoltage and Overvoltage
If load current increases, V
and thus V will droop
slightly, VFB with respect tSoENthSeE 12-bit DAC FoButput. This
causes the I voltage to increase until the average induc-
TH
The LTC3888-1 supports four PMBus bus addressing
schemes to access the individual PWM voltage loops
separately or jointly.
tor current matches the new load current and the desired
output voltage is restored. I is monitored to provide pro-
TH
grammable over-current protection with comparator ILIM.
Fault reporting and system response behavior are fully
configurable. The two status outputs (FAULT0, FAULT1)
can be controlled independently. A separate ALERT pin
also provides a maskable SMBALERT#. Fault responses
for each channel may be individually programmed,
depending on the fault type. PMBus status commands
allow fault reporting over the serial bus to identify a spe-
cific fault event.
When the top MOSFET is commanded off by the PWM
output, the bottom MOSFET is commanded on. The
LTC3888-1 operates in continuous conduction mode
(CCM), so the bottom MOSFET stays on until the PWM
clock next turns on the top MOSFET or the rail is com-
manded off.
POWER-UP AND INITIALIZATION
MAIN CONTROL LOOP
The LTC3888-1 is designed to provide standalone supply
sequencing with controlled turn-on and turn-off functions.
The LTC3888-1 utilizes constant frequency current mode
control with trailing-edge modulation. The main con-
trol loop used for each master channel is illustrated in
Figure 1. During normal operation the top MOSFET in
the external power stage (power switch) driving choke
L1 is commanded on when the clock phase for that mas-
ter sets the RS latch, unless the main PWM compara-
tor ICMP indicates there is already too much current in
L1. In that case no additional energy is delivered to the
choke during that cycle (PWM output remains low, cycle
skipped). Otherwise the latch is reset and power switch
commanded off later in the cycle by the PWM compara-
tor. Sensed output current is provided from the external
It operates from a V supply of 4.5V to 26.5V while three
IN
on-chip linear regulators generate internal 2.5V, 3.3V and
5.2V. If V is below 6V, the V and INTV pins must
IN
CC
be shorted together and limiteIdN to a maximum operat-
ing voltage of 5.5V. Controller configuration is reset by
the internal UVLO threshold, where INTVCC must be at
or above 4.45V, VDD33 must be at or above 3.1V and
the internal 2.5V supply must be within about 20% of its
regulated value. V must simply be high enough for the
IN
LDO outputs to reach these voltages. At that point the
internal microcontroller begins initialization. A RESTORE_
USER_ALL or MFR_RESET forces this same initialization.
power stage at the I
pin. The point in the PWM cycle
The LTC3888-1 features an internal RAM built-in self-test
(BIST) that runs during initialization. Should RAM BIST
fail, the following steps are taken.
SENSE
at which ICMP resets the RS latch is controlled by the
voltage provided by the output of error amplifier EA,
I
TH
including internal slope compensation for stable opera-
tion regardless of duty cycle. ln steady state, I adjusts
TH
Rev. 0
19
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LTC3888-1
OPERATION
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Figure 1. LTC3888-1 Master Channel Control Loop Diagram
Rev. 0
20
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LTC3888-1
OPERATION
• Device responds only at device address 0x7C and
ANALOG OUTPUT VOLTAGE CONTROL
global addresses 0x5A and 0x5B
The default factory EEPROM settings allow programming
of output voltage using only the external resistors R1 and
R2 shown in Figure 1. The control loop then produces the
desired output in a classical fashion as V is regulated
to 400mV. With other key parameters sFuBch as output
current limit programmable using external configuration
resistors, it is possible to create complex PolyPhase rail
solutions without needing to connect the device to any
digital bus. Refer to the Applications Information section
for more details on using analog output voltage control
with default factory EEPROM settings.
• A persistent Memory Fault Detected is indicated by
STATUS_CML
• Internal EEPROM is not accessed
• RUN pins and SHARE_CLK are driven low continuously
Normal operation can be restored if the RAM BIST sub-
sequently passes, for instance as the result of another
MFR_RESET issued to address 0x7C.
During initialization all PWM outputs are disabled. The
RUN pins and SHARE_CLK are held low and FAULT pins
are high impedance. External configuration resistors are
identified and the contents of the onboard EEPROM are
read into the controller command RAM. The LTC3888-1
can determine key operating parameters from external
configuration resistors according to application Table 10
through Table 12. See the following Resistor Configuration
Pins section for more detail. The resistor configuration
pins only determine some of the preset values of the
controller. The remaining values, retrieved from internal
EEPROM, are programmed at the factory or with PMBus
commands.
PMBUS OUTPUT VOLTAGE CONTROL
Once external programming resistors R1 and R2 (Figure
1) are chosen, it is possible to also use the full range
of digitally programmed output voltage control found
on most ADI PSM controllers. This is accomplished by
specifying the external divider gain with VOUT_SCALE_
LOOP. Again, refer to Applications Information for com-
plete details on controlling output voltage using built-in
LTC3888-1 PMBus commands and features.
SOFT-START
If the configuration resistor pins are all open, the
LTC3888-1 will use only EEPROM contents to determine
all operating parameters. If Ignore Resistor Configuration
Pins is set (bit 6 of MFR_CONFIG_ALL), the LTC3888-1
will use only its EEPROM contents to determine all operat-
ing parameters except device address. Unless both ASEL
pins are completely open, the LTC3888-1 will always
determine some portion of its device address from the
resistors on these pins. See Serial Bus Addressing later
in this section.
The internal microcontroller typically requires 35ms
to complete initialization once all onboard supplies are
above their UVLO threshold. After MCU initialization, an
internal comparator monitors V , which must exceed the
IN
VIN_ON threshold before output power sequencing can
begin. SHARE_CLK is released to run and the RUN pins
are released for external control after the part initializes
and V is greater than the VIN_ON threshold. Accurate
IN
readback telemetry can then require an additional 90ms
for initial round-robin A/D conversions.
Testing Integrity of Output Voltage Sense
During initialization, the LTC3888-1 also runs a connectiv-
ity check on the output voltage sense line (VSENSE+) of any
enabled master channel (see bit 4 of MFR_PWM_MODE_
LTC3888-1). If an open circuit is detected during this test,
the failure is indicated in the PMBus status registers, and
all PWMs on the IC are disabled until the test subsequently
passes after MFR_RESET or device power cycle.
Rev. 0
21
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LTC3888-1
OPERATION
If multiple LTC3888-1 ICs are used in an application,
shared RUN pins are held low until all units initialize and
VIN exceeds the VIN_ON threshold for all devices. A com-
mon SHARE_CLK signal can also ensure all connected
devices use the same time reference for initial start-up
even if RUN pins cannot be shared due to other design
requirements. SHARE_CLK is released by each IC once
the conditions for power sequencing have been fully satis-
fied, regardless of RUN pin state.
VOUT_TRANSITION_RATE. With LTC3888-1 digital con-
trol, ramping configurations can be reprogrammed as
needed without hardware modification.
Programmable fault responses and fault sharing can
ensure that any desired time-based output sequencing
and ramping control is properly accomplished each time
the system powers up or down. Refer to the Applications
Information section for various LTC3888-1 hardware and
PMBus command configurations needed to fully support
synchronization for time-based sequencing and output
ramping when using multiple ICs.
After a channel RUN pin rises above 2V and any specified
turn on delay (TON_DELAY) has expired, the LTC3888-1
performs an initial monotonic soft-start ramp on that
channel, allowing inrush current control. This is carried
out with a digitally controlled ramp of the internal EA
reference voltage from 0mV to the commanded value
(400mV factory default) at the VOUT_TRANSITION_RATE.
The soft-start feature is disabled by setting the value of
VOUT_TRANSITION_RATE to 4V/ms. The LTC3888-1 does
not initiate PWM operation until the commanded output
VOLTAGE-BASED OUTPUT SEQUENCING
It is also possible to sequence outputs on using cascaded
voltage events. To do this, the PGOOD status pin of one
PWM channel can be used to control the RUN pin of a
downstream channel. The controlling PGOOD pin holds
RUN low if V
is below the VOUT_UV_FAULT_LIMIT or
OUT
if power-good conditions are not being met. This keeps
the downstream channel off until acceptable output con-
ditions exist on the controlling channel. The LTC3888-1
does not readily support voltage-based off-sequencing.
Refer to the Applications Information section for more
details on voltage-based sequencing.
exceeds the actual rail voltage and I has risen to a level
TH
that will avoid negative average choke current. This allows
the regulator to start up into a prebiased load.
TIME-BASED OUTPUT SEQUENCING
The LTC3888-1 supports time-based output on and off
sequencing using a shared time reference (SHARE_CLK).
Following a qualified command to turn on, each output is
enabled after waiting its programmed TON_DELAY. This
can be used to sequence outputs in a prescribed order
that can be reprogrammed as needed without hardware
modification. Channel off-sequencing is accomplished in
a similar way with the TOFF_DELAY command.
OUTPUT DISABLE
All PWMs on the IC are disabled any time V is below
IN
the VIN_OFF threshold. The power stages are immediately
shut off to stop the transfer of energy to the load(s) as
quickly as possible.
PWM channels may also be disabled in response to cer-
tain internal fault conditions, an external fault propagated
through a FAULT pin, or loss of SHARE_CLK. In these
cases the power stages are immediately commanded off
to stop the transfer of energy to the load as quickly as pos-
sible. Refer to the following Fault Detection and Handling
section for additional details related to fault recovery.
OUTPUT RAMPING CONTROL
The LTC3888-1 supports synchronized output on and
off ramping control using a shared time reference
(SHARE_CLK). Power rail on and off relationships
similar to those of conventional analog tracking func-
tions can be achieved by using programmed delays and
Each rail can be disabled with an OPERATION command
at any time if enabled by ON_OFF_CONFIG. This will force
Rev. 0
22
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LTC3888-1
OPERATION
a controlled turn-off response with defined delay (TOFF_
DELAY) and ramp down rate (VOUT_TRANSITION_RATE).
SWITCHING FREQUENCY AND PHASE
There is a high degree of flexibility for setting the PWM
operating frequency of the LTC3888-1. The switching fre-
quency of the PWM can be established with an internal
oscillator or an external time base. The internal phase-
locked loop (PLL) synchronizes PWM control to this tim-
ing reference with proper phase relation. The device can
also be configured to provide the master clock (SYNC)
to other ICs through PMBus command or EEPROM set-
ting. The LTC3888-1 is designated as a clock master by
clearing bit 4 of MFR_CONFIG_ALL. As clock master,
the LTC3888-1 will drive its open-drain SYNC pin at the
selected rate with a pulse width of 500ns. An external
Finally, each rail can be commanded off by pulling the
associated RUN pin low. Pulling the RUN pin low can force
the master to perform a controlled turn off or immediately
disable all rail power stages, depending on the program-
ming of ON_OFF_CONFIG.
Minimum Output Disable Times
When OPERATION is used to turn off an LTC3888-1 rail,
a minimum output disable time of 120ms is imposed
regardless of how quickly the rail is commanded back
on. If bit 4 of MFR_CHAN_CONFIG is clear, a PMBus com-
mand to turn the channel off also pulses the RUN pin low.
Once the RUN pin is pulled low internally or externally,
a minimum output disable time (RUN forced low by the
LTC3888-1) of TOFF_DELAY + VOUT/VOUT_TRANSITION_
RATE + 136ms is enforced. If MFR_RESTART_DELAY is
greater than this mandatory minimum, the larger value
of MFR_RESTART_DELAY is used. These minimum off
times allow a consistent rail restart with coherent monitor
ADC values and make the LTC3888-1 highly compatible
with other ADI PMBus digital power system management
products.
pull-up resistor between SYNC and V
is required in
DD33
this case. Only one device connected to SYNC should be
designated to drive the pin. If more than one LTC3888-1
sharing SYNC is programmed as clock master, just one of
the devices is automatically elected to provide the clock.
The others disable their SYNC outputs and indicate this
with bit 10 of MFR_PADS_LTC3888-1.
The LTC3888-1 will automatically accept an external
SYNC input, disabling is own SYNC drive if necessary, as
long as the external clock frequency is greater than one-
half of the programmed internal oscillator. Whether con-
figured to drive SYNC or not, the LTC3888-1 will continue
PWM operation at the selected frequency (FREQUENCY_
SWITCH) using its own internal oscillator if an external
clock signal is subsequently lost.
OUTPUT SHORT CYCLE
An output short cycle condition is created when a master
channel is commanded back on while waiting for con-
trolled turn off to complete based on TOFF_DELAY and
VOUT_TRANSITION_RATE. Any time this occurs, the
LTC3888-1 asserts the short cycle bit in STATUS_MFR_
SPECIFIC. Device response at that point is governed by
bits in MFR_CHAN_CONFIG and SMBALERT_MASK.
Refer to the detailed descriptions of those commands
for additional details. Generally, the LTC3888-1 should be
controlled so that short cycle conditions are not created
during normal operation.
The MFR_PWM_CONFIG_LTC3888-1 command can be
used to create a specific master/slave configuration and
assign the phase of each channel. Desired master/slave
arrangement can also be set from EEPROM or external
configuration resistors as outlined in Table 11. Phase des-
ignates the relationship between the falling edge of SYNC
and the internal clock edge that sets the PWM latch for
that channel. Additional small propagation delays to the
PWM control pins will apply.
Rev. 0
23
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LTC3888-1
OPERATION
PWM phase relationships and frequency are independent
of each other, providing numerous application options.
Multiple LTC3888-1 ICs can be synchronized to real-
ize a PolyPhase array. Two LTC3888-1 devices can be
combined to expand phase count while maintaining ideal
phase separation of 360/n degrees, where n is the num-
ber of phases driving the output voltage rail. Refer to the
Applications Information section for additional details.
Bits[4:0] of MFR_PWM_COMP adjust an internal resis-
tor which can be used to set the dominant zero against
the primary compensation capacitance. This resistance
appears between the I and I
pins.
TH
THR
The transconductance of the error amplifier itself can also
be adjusted using bits[7:5] of MFR_PWM_COMP.
Both of these parameters can be modified when the device
is in operation, affording real-time evaluation of compen-
sation settings. Refer to the Applications Information sec-
ton for additional details related to loop compensation.
POLYPHASE LOAD SHARING
Multiple LTC3888-1 devices can be combined to provide
a balanced load-share solution by configuring the neces-
sary pins. The SHARE_CLK and SYNC pins of all load-
sharing ICs should be bussed together. Connecting the
SYNC pins synchronizes the PWM controllers with each
other. Bussing the SHARE_CLK pins together allows the
phases to start synchronously. Refer to the discussion in
the previous Power-Up and Initialization section. The last
device to see all start-up conditions satisfied controls the
initiation of power sequencing for all phases.
LOAD STEP EMULATION
Basic assembly integrity, PWM regulator loop response,
and passive component aging or thermal degredation
are best evaluated by analyzing load current transient
response. The LTC3888-1 features a flexible load step
emulation capability that allows in-situ transient response
evaluation without the need to actually generate and apply
large, regulated load current pulses at the regulator out-
put. These features can find use in the design, debug,
prototyping and preventative maintenence phases of a
product life cycle.
The outputs of multiple LTC3888-1 error amplifiers (I
TH
pins) may be wired together in large PolyPhase applica-
tions if V sensing for those channels is also shared.
OUT
Load step emulation is controlled by MFR_LOAD_
EMULATION. All phases associated with each master
channel can be programmed to emulate a load step of
known amplitude (bits[1:0]). Bit 2 of the command deter-
mines whether the emulated load is applied as a con-
tinuous increase or as a 100μs pulse. Because internal
application of data from a PMBus command is an asyn-
chronous event, bit 3 of the command allows the PGOOD
output to be repurposed to provide a trigger at the actual
start of the emulated load step, if necessary.
The error amplifier of only one master phase can also be
designated for voltage control by redefining any remain-
ing master phases as slaves using bit 4 of MFR_PWM_
MODE_LTC3888-1. Additional details for properly con-
structing various PolyPhase designs are covered in the
Applications Information section.
VOLTAGE CONTROL LOOP COMPENSATION
Because the LTC3888-1 uses an operational transcon-
ductance amplifier (OTA) architecture for its error ampli-
fier, Type II compensation is most commonly applied for
stabilizing the voltage control loop. The LTC3888-1 offers
several programmable features for flexability in designing
and operating the PWM with optimum transient behavior
over a wide range of output capacitance without additional
hardware changes.
INPUT SUPPLY MONITORING
The input supply voltage is sensed by the LTC3888-1 at
the V pin. Undervoltage, overvoltage, and valid on/off
IN
levels can be programmed for V . Refer to the following
IN
PMBus Command Details section for more information
on programming input supply thresholds. In addition, the
telemetry ADC monitors V relative to GND. Conversion
IN
results are returned by READ_VIN.
Rev. 0
24
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LTC3888-1
OPERATION
OUTPUT VOLTAGE SENSING AND MONITORING
TEMPERATURE SENSE
External temperature can be monitored by most modern
power stages. This is normally presented on a highest-
indicated wire-OR analog bus for each rail, where the
device with highest internal temperature sets the bus volt-
age. The internal ADC converts these temperature inputs
at one-third the rate of voltage or current channels, and
those results are returned by READ_TEMPERATURE_1.
READ_TEMPERATURE_2 returns the internal junction
temperature of the LTC3888-1 using an on-chip diode
Both on-chip voltage control loops allow remote, differ-
ential sensing of the load voltage with V
pins. The
SENSE
DAOUT0/1 outputs provide a 1X buffered version of this
sensed differential referenced to package GND. These
outputs are suitable for driving a resistor divider to GND
supplying V to set the desired output voltage.
FB
VOUT supervisor UV and OV fault limits are set from
EEPROM or PMBus command. Factory EEPROM sets
the supervisor limits and margin values as a percentage
with accurate ΔV measurement and calculation.
BE
of V and hence V . If these are modified by PMBus
FB
OUT
command, they are specified in absolute volts.
RESISTOR CONFIGURATION PINS
The telemetry ADC is also fully differential and makes
Six input pins can be used to configure key operating
parameters with selected 1% resistors between each pin
measurements of regulated output voltages at V
Conversion results are returned by READ_VOUT.
.
SENSE
and GND. R
establishes the proper bias levels for the
SET
remaining five pins and requires an 18.7kΩ resistor to
GND. The remaining RCONFIG pins are ASEL0, ASEL1,
ILIM0_CFG, ILIM1_CFG, and PWM_CFG. If any of these
five pins are left open, the value stored in the correspond-
ing EEPROM command(s) is used. The resistor configura-
tion pins are only measured during power-up and execu-
tion of RESTORE_USER_ALL or MFR_RESET. If bit 6 of
MFR_CONFIG_ALL is set in EEPROM, all resistor configu-
ration pins except ASEL0 and ASEL1 are ignored. Per the
PMBus specification, all pin-programmed parameters can
be overridden at any time by commands from the digital
interface.
OUTPUT CURRENT SENSING AND MONITORING
Every PWM channel on the LTC3888-1 accepts an output
current monitor signal from the power stage it controls. A
proprietary input interface uses this information to control
output pulse width on that phase. When the I
pins for
a channel are multiplexed to the differentialSiEnNpSuEts of the
LTC3888-1 monitor ADC, they use IREF as the negative
input. These ADC channels have a differential input range
of approximately 400mVdc. The internal ADC anti-alias-
ing filter and conversion rate produce an average reading
of the I
input voltage relative to IREF. The resulting
SENSE
value is returned by the READ_IOUT PMBus command.
To allow reduction in round-robin latency, bit 6 of MFR_
PWM_CONFIG_LTC3888-1 determines if the ADC con-
The ASEL0/1 pin settings are described in application
Table 12. These pins can be used to select the entire
LTC3888-1 device address. ASEL0 always programs the
bottom four bits of the device address for the LTC3888-1
unless left open. ASEL1 can be used to program the
three most-significant bits. Either portion of the address
can also be retrieved from the MFR_ADDRESS value in
EEPROM. If both pins are left open, the full 7-bit MFR_
ADDRESS value stored in EEPROM is used to determine
the device address. The LTC3888-1 always responds to
7-bit global addresses 0x5A and 0x5B. MFR_ADDRESS
should not be set to either of these values or 0x7C.
verts I
for all eight phases, or only the two master
SENSE
channels. If only I
and I
are monitored, the
SENSE0
SENSE1
IOUT results for the remaining six channels are set to 0A.
READ_IOUT returns readings for the two master channels,
MFR_TOTAL_IOUT returns the sum of all output currents
for on-chip phases assigned to each master channel, and
MFR_READ_ALL_IOUT returns output current for each
individual phase using block read format.
Rev. 0
25
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LTC3888-1
OPERATION
The ILIM0_CFG and ILIM1_CFG pin settings are described
in application Table 10. These pins select the per-phase
output current limit for each related rail.
FAULT DETECTION
A variety of fault and warning detection, reporting and
handling mechanisms are provided by the LTC3888-1.
Fault or warning detection capabilities include:
PWM_CFG pin settings are described in application
Table 11. This pin selects the master/slave configurnation
and switching frequency of the internal oscillator.
• Input Under/Overvoltage
• Power Stage UV or Fault
INTERNAL EEPROM WITH CRC
• Output Under/Overvoltage
The LTC3888-1 contains internal EEPROM with error cor-
rection code (ECC) to store user configuration settings
and fault log information. EEPROM endurance and reten-
tion for user space and fault log pages are specified in the
Absolute Maximum Ratings and Electrical Characteristics
table.
• Output Overcurrent
• External Overtemperature
• Internal Overtemperature
• CML Fault (Communication, Memory, or Logic)
• External Fault Detection via Bidirectional FAULT Pins
The integrity of the entire onboard EEPROM is checked
with a CRC calculation each time its data is to be
read, such as after a power-on reset or execution of
RESTORE_USER_ALL. If a CRC error occurs, the CML
bit is set in STATUS_BYTE and STATUS_WORD, the
EEPROM CRC Error bit in STATUS_MFR_SPECIFIC is set,
and the ALERT, SHARE_CLK and RUN pins are pulled low
(PWM channels off). At that point the device will respond
at special address 0x7C, which is activated after an invalid
CRC has been detected. The chip no longer responds at
its specifically assigned address, but will still respond at
global addresses 0x5A and 0x5B. However, use of these
global addresses when attempting to recover from a CRC
issue is not recommended. All power supply rails associ-
ated with a device reporting an invalid CRC should remain
disabled until the issue is resolved.
Reporting is covered in following sections on status com-
mands (registers) and ALERT pin function. Fault handling
mechanisms include hardwired low level PWM safety
responses that always occur and higher-level program-
mable event management. Both types are covered in the
following sections.
Input Supply Faults
Input undervoltage and overvoltage limits are determined
from multiplexed monitor ADC conversions. Therefore
the input UV/OV response is naturally deglitched by the
typical conversion cycle of the ADC (tens of milliseconds).
There is no hardwired low level PWM response for any
input supply fault.
Hardwired PWM Response to Power Stage Faults
ADI recommends that the EEPROM not be written when
die temperature is greater than 85°C. If internal die tem-
perature exceeds 130°C, all EEPROM operations except
RESTORE_USER_ALL and MFR_RESET are disabled. Full
EEPROM operation is not re-enabled until die temperature
falls below 125°C. Refer to the Applications Information
section for equations to predict retention degradation due
to elevated operating temperatures.
Power stage faults are monitored on the shared TEMP/
FAULT bus attached to an LTC3888-1 TSNS pin. A power
stage fault condition is detected if this bus is pulled above
any voltage expected for normal operating temperature
range. The specific faults that are reported are determined
by the power stage manufacturer. When a power stage
fault is detected, the master and its associated slave chan-
nels are all commanded off. This state is indicated in the
LTC3888-1 status registers and optionally on the ALERT
pin. The off condition is latched until the rail is turned off
See the Applications Information section or contact the
factory for details on efficient in-system EEPROM pro
-
gramming, including bulk EEPROM programming, which
the LTC3888-1 also supports.
Rev. 0
26
For more information www.analog.com
LTC3888-1
OPERATION
and then back on by the RUN pin or OPERATION com-
mand, including IC reset or power supply cycling.
overvoltage comparator guards against transient over-
shoots as well as long term overvoltages at the output.
When an output OV fault is detected, the state is indicated
in the LTC3888-1 status registers and optionally on the
ALERT pin. The master and its associated slave chan-
nels are all commanded off, unless bit 4 of MFR_PWM_
CONFIG_LTC3888-1 is set and bit 4 in the associated
MFR_PWM_MODE_LTC3888-1 command is clear. In that
special case the master phase of the OV rail commands
its power stage to drive low as long as the OV condition
is detected. Regardless, the off condition is latched until
the rail is cycled off and then back on after the fault has
cleared.
Hardwired PWM Response to Power Stage UV
Some power stages can also report a undervoltage condi-
tion for their input supplies on the shared TEMP/FAULT bus.
When supported, this condition is indicated by pulling the
bus below any voltage expected for normal operating tem-
perature range. The LTC3888-1 recognizes this UV indica-
tion if enabled by bit 0 of MFR_PWM_MODE_LTC3888-1.
If the power stage does not provide inherent UV indica-
tion on a shared TEMP/FAULT bus, the LTC3888-1 can be
programmed to provide additional power stage undervolt-
age detection by setting bit 5 of MFR_CHAN_CONFIG on
Page 0. Pin 8 is then converted to a VDR_MON input to
monitor the FET gate drive supply voltage (VDR) of the
external power stages for both master channels. Normally
an external resistor divider to set the desired UV threshold
is required. In this case TSNS1 serves as connection for
the shared TEMP/FAULT bus for both master channels
with UV detection disabled, regardless of the state of bit
0 of MFR_PWM_MODE_LTC3888-1 on either page.
UV faults are masked if the channel has been commanded
off or until all of the following criteria are achieved.
• TON_DELAY Has Expired
• The Soft-Start Ramp Has Completed
• TON_MAX_FAULT_LIMIT Has Been Reached
• IOUT_OC_FAULT_LIMIT Has Not Been Reached
• Soft-Off Is Not in Progress
The LTC3888-1 has no hardwired PWM response for out-
put UV faults.
When TSNS-based UV detection or VDR_MON are
enabled, power stage UV condition is continuously indi-
cated in bits[15:14] of MFR_PADS_LTC3888-1. If a power
stage UV condition then occurs during PWM operation
or is present when the PWM master is commanded to
start, the master and its associated slave channels are all
latched off. This state is indicated in the LTC3888-1 status
registers and optionally on the ALERT pin. The off condi-
tion is latched until the rail is turned off and then back on
by the RUN pin or OPERATION command, including IC
reset or power supply cycling.
The LTC3888-1 supports optional output UV and OV
warnings that are determined from multiplexed monitor
ADC conversions. The LTC3888-1 has no hardwired PWM
response for output UV or OV warnings.
Power Good Indication
An LTC3888-1 master phase indicates Power Good on its
PGOOD pin and in STATUS_WORD based on selected UV
and OV fault limits. Power Good is indicated as long as
Note that if an enabled power stage UV indication exists
on both master channels that are sequentially turned
on by RUN pin or OPERATION command, the indicated
fault on the first channel on will be cleared if bit 0 of
MFR_CONFIG_ALL is set. However, both channels will be
latched off as described above.
the phase is enabled to run and V
and OV fault limits.
is between the UV
OUT
Hardwired PWM Response to I
Faults
OUT
The LTC3888-1 monitors output current as commanded
by the I pins, taking into account power stage current
TH
monitor gain, which is provided by PMBus command or
Hardwired PWM Response to V
Faults
OUT
EEPROM values.
VOUT undervoltage (UV) and overvoltage (OV) faults
are detected by supervisor comparators. The output
Rev. 0
27
For more information www.analog.com
LTC3888-1
OPERATION
An output overcurrent (OC) fault condition is detected by a
supervisor comparator for each master channel when the
An internal watchdog detects if SHARE_CLK remains low
for more than 64µs. The part then actively holds SHARE_
CLK low for 120ms, ensuring all devices connected to
this shared control observe a minimum RETRY_DELAY
event. The LTC3888-1 sets the SHARE_CLK_LOW bit in
MFR_COMMON to indicate this fault condition.
I
voltage for that channel reaches its maximum allowed
TH
value. Refer to IOUT_OC_FAULT_LIMIT for details. When
an OC fault is detected the controller clamps I at the
OC value.
TH
Output OC warnings are determined from multiplexed
monitor ADC conversions. The LTC3888-1 has no hard-
wired PWM response if an output OC warning occurs.
External Faults
There are no hardware-level responses to any external
faults propagated into the IC through the FAULT pins.
Hardwired PWM Response to Internal Temperature
Faults
HIGHER-LEVEL FAULT HANDLING
An internal temperature sensor measured by the monitor
ADC protects against EEPROM and other IC damage. When
die temperature rises above 130°C, the LTC3888-1 will
NACK any EEPROM-related command except RESTORE_
USER_ALL and MFR_RESET and issue a CML fault for
Invalid/Unsupported Command. Normal EEPROM access
is re-enabled when die temperature drops below 125°C.
Above 160°C, the part shuts down all PWM outputs until
die temperature is below 150°C. Internal temperature fault
limits cannot be adjusted. Writing to the EEPROM above
a die temperature of 85°C is strongly discouraged. Refer
to the Absolute Maximum Ratings for other important
temperature limitations on internal EEPROM use.
Higher-level input and output fault event handling
(response) can be programmed as described in the fol-
lowing PMBus Command Details section. Once a fault is
detected, several tens of microseconds may be required
for these higher level responses to occur, including related
assertion of a FAULT output. Time filtering programmed in
any specific fault response will be in addition to these nor-
mal processing delays. For many faults, the LTC3888-1
can manage response in one of three ways: ignore, auton-
omous recovery (hiccup), or latch off. The device takes no
additional action beyond previously discussed hardware-
level responses when programmed to ignore a fault.
For autonomous recovery a new soft-start is attempted if
the fault condition is not present after the MFR_RETRY_
DELAY interval has elapsed. MFR_RETRY_DELAY can
be set from 120ms to 83 seconds in 1ms increments.
If the fault persists, the controller will continue to retry
with an interval specified by MFR_RETRY_DELAY. This
avoids damage to external regulator components caused
by repetitive, rapid power cycling.
External Temperature Faults
The external shared (wire-OR) power stage temperature
bus may also be monitored by the onboard ADC. There
is no hardwired PWM response for sensed external tem-
perature faults or warnings.
Timing Faults
No retry is attempted for a latch off fault response. In the
latch off state the applicable external power stages are
immediately disabled to stop the transfer of energy to
the load as quickly as possible. The output remains dis-
abled until the master channel is commanded off and then
on, or IC supply power is cycled. Commanding a PWM
channel off and on may require software and/or hardware
intervention depending on its programmed configuration.
There is no hardwired PWM response to any timing faults.
TON_MAX_FAULT_LIMIT is the time allowed for VOUT
to rise and settle at start-up. The TON_MAX_FAULT_
LIMIT timer, which has a resolution of 10µs, is started
after TON_DELAY has been reached and a soft-start
sequence is started. If the VOUT_UV_FAULT_LIMIT
is not reached or an OC fault remains after the speci-
fied time, fault response is determined by the value of
TON_MAX_FAULT_RESPONSE.
Rev. 0
28
For more information www.analog.com
LTC3888-1
OPERATION
The RUN pin must be released by any controlling exter-
nal application circuits for that channel to restart from the
latch off state. As the RUN pin for a given rail rises, asso-
ciated internal fault indications are cleared automatically.
The LTC3888-1 can also be programmed to clear faults
for both master channels based solely on the run state of
just one channel. See the MFR_CONFIG_ALL command.
CLEAR_FAULTS can also be used to clear all fault bits at
any time, independent of PWM channel state.
in the same fashion as the status bits themselves. For
example, if ALERT is masked for all bits in Channel 0
STATUS_VOUT, then ALERT is effectively masked for the
VOUT bit in STATUS_WORD for PAGE 0.
The BUSY bit in STATUS_BYTE also asserts ALERT and
cannot be masked. This bit can be set as a result of inter-
action between internal operations and PMBus communi-
cation. This fault occurs when a command is received that
cannot be safely executed with one or both master chan-
nels enabled. As discussed in Application Information,
BUSY faults can be avoided by polling MFR_COMMON
before executing some commands.
Higher-level handling of some internally generated faults
can be digitally deglitched. External faults propagated into
the chip using FAULT pins are not deglitched. Refer to the
following section on FAULT Pin I/O.
Status information contained in MFR_COMMON and
MFR_PADS_LTC3888-1 can be used to clarify the con-
tents of STATUS_BYTE or STATUS_WORD as shown,
but the contents of these registers do not affect the state
of the ALERT pin and may not directly influence bits in
STATUS_BYTE or STATUS_WORD.
STATUS REGISTERS AND ALERT MASKING
Figure 2 summarizes the internal LTC3888-1 status reg-
isters accessible by PMBus command. These contain
indication of various faults, warnings and other impor-
tant operating conditions. As shown, STATUS_BYTE and
STATUS_WORD also summarize contents of other status
registers. Refer to PMBus Command Details for specific
information.
FAULT PIN I/O
The LTC3888-1 can map various fault indicators to their
respective FAULT pin using the MFR_FAULT_PROPAGATE
command.
NONE OF THE ABOVE in STATUS_BYTE indicates that
one or more of the bits in the most-significant nibble of
STATUS_WORD are also set.
Channel-to-channel fault dependencies and communica-
tion can be created by connecting FAULT pins together. In
the event of an internal fault, one or more of the channels
is configured to pull the bussed FAULT pins low. All chan-
nels are then configured to shut down when the bussed
FAULT pins are pulled low (MFR_FAULT_RESPONSE set
to 0xC0). If latch off is the programmed response on the
faulted channel, the FAULT pin remains low until one of
the following occurs:
Figure 2 also shows which of the status bits will assert
ALERT if set and not masked. Once set, ALERT will remain
low until one of the following occurs.
• A CLEAR_FAULTS, RESTORE_USER_ALL or MFR_
RESET Command Is Issued
• The Related Status Bit Is Written to a One
• The Faulted Channel Is Properly Commanded Off and
Back On
• A CLEAR_FAULTS, RESTORE_USER_ALL or MFR_
RESET Command Is Issued
• The LTC3888-1 Successfully Transmits Its Address
During a PMBus Alert Response Address (ARA)
• The Related Status Bit Is Written to a One
• The Faulted Channel Is Properly Commanded Off and
Back On
• IC Supply Power Is Cycled
With some exceptions, the SMBALERT_MASK command
can be used to prevent the LTC3888-1 from asserting
ALERT on a bit-by-bit basis by register. These mask set-
tings are promoted to STATUS_WORD and STATUS_BYTE
• IC Supply Power Is Cycled
For autonomous group retry, the faulted channel is con-
figured to release the FAULT pin(s) after a retry interval,
Rev. 0
29
For more information www.analog.com
LTC3888-1
OPERATION
STATUS_WORD
STATUS_VOUT
ꢇꢈ ꢴꢗꢠꢟ
ꢇꢉ ꢜꢗꢠꢟ
ꢇꢊ ꢜꢢꢁꢠꢟ
ꢇꢋ ꢖꢫRꢞꢘꢁꢄꢐꢜꢫꢜꢐ
ꢇꢇ ꢁꢗꢨꢄRꢞꢃꢗꢗꢅꢻ
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ꢇ
ꢎ
ꢏ
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ꢉ
ꢊ
ꢋ
ꢇ
0
ꢴꢗꢠꢟꢞꢗꢴ ꢫꢒꢣꢔꢤ
ꢴꢗꢠꢟꢞꢗꢴ ꢨꢒꢕꢓꢝꢓꢮ
ꢴꢗꢠꢟꢞꢠꢴ ꢨꢒꢕꢓꢝꢓꢮ
ꢴꢗꢠꢟꢞꢠꢴ ꢫꢒꢣꢔꢤ
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ꢀꢕeꢒꢙꢛ 0ꢆ
STATUS_INPUT
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ꢀꢕeꢒꢙꢛ 0ꢆ
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ꢀꢕeꢒꢙꢛ 0ꢆ
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ꢎ
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0
ꢌ
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ꢀꢕeꢒꢙꢛ 0ꢆ
ꢀꢕeꢒꢙꢛ 0ꢆ
STATUS_BYTE
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢕeꢒꢙꢛ 0ꢆ
ꢀꢕeꢒꢙꢛ 0ꢆ
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
ꢰꢠꢘꢡ
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ꢴꢗꢠꢟꢞꢗꢴ
ꢜꢗꢠꢟꢞꢗꢐ
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ꢟꢄꢖꢁꢄRꢂꢟꢠRꢄ
ꢐꢖꢩ
ꢢꢗꢢꢄ ꢗꢫ ꢟꢲꢄ ꢂꢰꢗꢴꢄ
STATUS_IOUT
STATUS_MFR_SPECIFIC
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
ꢜꢗꢠꢟꢞꢗꢐ ꢫꢒꢣꢔꢤ
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ꢎ
ꢏ
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ꢉ
ꢊ
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0
ꢜꢓꢤeꢕꢓꢒꢔ ꢟeꢸꢥeꢕꢒꢤꢣꢕe ꢫꢒꢣꢔꢤ
ꢜꢓꢤeꢕꢓꢒꢔ ꢟeꢸꢥeꢕꢒꢤꢣꢕe ꢨꢒꢕꢓꢝꢓꢮ
ꢄꢄꢁRꢗꢖ ꢐRꢐ ꢄꢕꢕꢬꢕ
ꢜꢓꢤeꢕꢓꢒꢔ ꢁꢩꢩ ꢠꢓꢔꢬꢭꢷeꢙ
ꢫꢒꢣꢔꢤ ꢩꢬꢮ ꢁꢕeꢛeꢓꢤ
ꢀꢕeꢒꢙꢛ 0ꢆ
ꢴꢗꢠꢟ ꢘꢑꢬꢕꢤ ꢐꢚꢭꢔeꢙ
FAULT ꢩꢬꢯ
ꢜꢗꢠꢟꢞꢗꢐ ꢨꢒꢕꢓꢝꢓꢮ
ꢀꢕeꢒꢙꢛ 0ꢆ
ꢐꢣꢕꢕeꢓꢤ ꢘꢑꢒꢕe ꢫꢒꢣꢔꢤ
ꢋ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢕeꢒꢙꢛ 0ꢆ
ꢀꢕeꢒꢙꢛ 0ꢆ
MFR_COMMON
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
ꢐꢑꢝꢥ ꢢꢬꢤ ꢅꢕꢝvꢝꢓꢮ ALERT ꢩꢬꢯ
ꢐꢑꢝꢥ ꢢꢬꢤ ꢰꢣꢛꢚ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆ
ꢜꢓꢤeꢕꢓꢒꢔ ꢐꢒꢔꢭꢣꢔꢒꢤꢝꢬꢓꢛ ꢢꢬꢤ ꢁeꢓꢙꢝꢓꢮ
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ꢀꢕeꢒꢙꢛ 0ꢆ
ꢘꢲꢂRꢄꢞꢐꢩꢳꢞꢩꢗꢨ
ꢀꢕeꢒꢙꢛ 0ꢆ
STATUS_TEMPERATURE
MFR_PADS_LTC3888-1
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
ꢗꢟ ꢫꢒꢣꢔꢤ
ꢇꢈ ꢐꢑꢒꢓꢓeꢔ ꢇ ꢅꢕꢖꢗꢘ Reꢒꢙꢚ
ꢇꢉ ꢐꢑꢒꢓꢓeꢔ 0 ꢅꢕꢖꢗꢘ Reꢒꢙꢚ
ꢇꢊ ꢀꢕeꢒꢙꢛ 0ꢆ
ꢇꢋ ꢀꢕeꢒꢙꢛ 0ꢆ
ꢇꢇ ꢜꢓvꢒꢔꢝꢙ RꢄꢂꢅꢞꢟꢄꢖꢁꢄRꢂꢟꢠRꢄꢞꢇ
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ꢗꢟ ꢨꢒꢕꢓꢝꢓꢮ
ꢀꢕeꢒꢙꢛ 0ꢆ
ꢀꢕeꢒꢙꢛ 0ꢆ
ꢀꢕeꢒꢙꢛ 0ꢆ
ꢀꢕeꢒꢙꢛ 0ꢆ
ꢀꢕeꢒꢙꢛ 0ꢆ
ꢀꢕeꢒꢙꢛ 0ꢆ
MFR_INFO
ꢌ
ꢍ
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
ꢐꢑꢒꢓꢓeꢔ ꢇ ꢝꢛ ꢁꢗꢨꢄRꢞꢃꢗꢗꢅ
ꢐꢑꢒꢓꢓeꢔ 0 ꢝꢛ ꢁꢗꢨꢄRꢞꢃꢗꢗꢅ
ꢩꢟꢐꢊꢍꢍꢍꢪꢇ ꢫꢬꢕꢭꢝꢓꢮ Rꢠꢢꢇ ꢩꢬꢯ
ꢩꢟꢐꢊꢍꢍꢍꢪꢇ ꢫꢬꢕꢭꢝꢓꢮ Rꢠꢢ0 ꢩꢬꢯ
Rꢠꢢꢇ ꢁꢝꢓ ꢘꢤꢒꢤe
ꢇꢈ Reꢛeꢕveꢙ
ꢇꢉ Reꢛeꢕveꢙ
ꢇꢊ Reꢛeꢕveꢙ
ꢇꢋ Reꢛeꢕveꢙ
ꢇꢇ Reꢛeꢕveꢙ
ꢇ0 Reꢛeꢕveꢙ
ꢌ
ꢍ
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
ꢀꢁꢂꢃꢄꢅꢆ
STATUS_CML
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
ꢜꢓvꢒꢔꢝꢙꢺꢠꢓꢛꢣꢥꢥꢬꢕꢤeꢙ ꢐꢬꢸꢸꢒꢓꢙ
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ꢁꢒꢭꢷeꢤ ꢄꢕꢕꢬꢕ ꢐꢑeꢭꢷ ꢫꢒꢝꢔeꢙ
ꢖeꢸꢬꢕꢚ ꢫꢒꢣꢔꢤ ꢅeꢤeꢭꢤeꢙ
ꢁꢕꢬꢭeꢛꢛꢬꢕ ꢫꢒꢣꢔꢤ ꢅeꢤeꢭꢤeꢙ
ꢀꢕeꢒꢙꢛ 0ꢆ
Rꢠꢢ0 ꢁꢝꢓ ꢘꢤꢒꢤe
ꢩꢟꢐꢊꢍꢍꢍꢪꢇ ꢫꢬꢕꢭꢝꢓꢮ FAULT1 ꢩꢬꢯ
ꢩꢟꢐꢊꢍꢍꢍꢪꢇ ꢫꢬꢕꢭꢝꢓꢮ FAULT0 ꢩꢬꢯ
FAULT1 ꢁꢝꢓ ꢘꢤꢒꢤe
Reꢛeꢕveꢙ
Reꢛeꢕveꢙ
Reꢛeꢕveꢙ
Reꢛeꢕveꢙ
ꢄꢄꢁRꢗꢖ ꢄꢐꢐ ꢘꢤꢒꢤꢣꢛ
Reꢛeꢕveꢙ
Reꢛeꢕveꢙ
Reꢛeꢕveꢙ
Reꢛeꢕveꢙ
FAULT0 ꢁꢝꢓ ꢘꢤꢒꢤe
ꢗꢤꢑeꢕ ꢐꢬꢸꢸꢣꢓꢝꢭꢒꢤꢝꢬꢓ ꢫꢒꢣꢔꢤ
ꢗꢤꢑeꢕ ꢖeꢸꢬꢕꢚ ꢬꢕ ꢩꢬꢮꢝꢭ ꢫꢒꢣꢔꢤ
Reꢛeꢕveꢙ
DESCRIPTION
MASKABLE GENERATES ALERT BIT CLEARABLE
ꢃeꢓeꢕꢒꢔ ꢫꢒꢣꢔꢤ ꢬꢕ ꢨꢒꢕꢓꢝꢓꢮ ꢄveꢓꢤ
ꢃeꢓeꢕꢒꢔ ꢢꢬꢓꢪꢖꢒꢛꢷꢒꢦꢔe ꢄveꢓꢤ
ꢅꢚꢓꢒꢸꢝꢭ
ꢡeꢛ
ꢢꢬ
ꢢꢬ
ꢢꢬ
ꢡeꢛ
ꢡeꢛ
ꢢꢬ
ꢡeꢛ
ꢡeꢛ
ꢢꢬ
ꢘꢤꢒꢤꢣꢛ ꢅeꢕꢝveꢙ ꢶꢕꢬꢸ ꢗꢤꢑeꢕ ꢰꢝꢤꢛ
ꢢꢬꢤ ꢅꢝꢕeꢭꢤꢔꢚ
ꢢꢬ
ꢇ
ꢋ
ꢘeꢤ ꢦꢚ ꢴꢗꢠꢟꢞꢗ ꢵ ꢅꢕꢖꢗꢘ ꢀꢥꢬꢯeꢕ ꢛꢤꢒꢮeꢆ ꢶꢒꢣꢔꢤ ꢬꢕ ꢅꢕꢖꢗꢘ ꢠꢴꢩꢗ ꢙꢣꢕꢝꢓꢮ Rꢠꢢ
ꢘeꢤ ꢬꢓꢔꢚ ꢦꢚ ꢙeꢤeꢭꢤeꢙ ꢥꢬꢯeꢕ ꢛꢤꢒꢮe ꢶꢒꢣꢔꢤ
ꢊꢍꢍꢍꢇꢋ ꢫ0ꢋ
Figure 2. LTC3888-1 Status Register Summary
Rev. 0
30
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LTC3888-1
OPERATION
assuming the original fault has cleared. All the channels
in the group then begin a soft-start sequence.
fault log is partial. Data in one or more event records may
be incomplete or incorrect.
As noted above, FAULT pins can also find use as inputs
to detect faults external to the controller that require an
immediate response. External faults propagated into the
chip using FAULT pins are not deglitched.
Fault Log Details
The MFR_FAULT_LOG command uses a block read pro-
tocol with a fixed length of 147 bytes. The LTC3888-1
returns a block byte count of zero if a fault log is not
present.
Refer to MFR_FAULT_PROPAGATE for additional details.
Contents of a fault log are shown in Table 1 through
Table 4. Refer to Table 6 for an explanation of data for-
mats. Each event record represents one complete conver-
sion cycle through all multiplexed monitor ADC inputs
and related status. When a fault log is created the present
ADC input cycle is completed and the ADC input being
FAULT LOG OPERATION
The LTC3888-1 supports fault logging to provide telem-
etry recording capability. A conceptual diagram of the fault
log is shown in Figure 3. During normal operation the
contents of primary status registers and all ADC readings,
including peak voltage and current results, are stored in
a continuously updated RAM buffer if enabled by bit 7
of MFR_CONFIG_ALL. The operation is similar to a strip
recorder. When a fault occurs that disables either master
channel, recording to internal memory is halted (locked)
and the fault log information is made available from RAM
via the MFR_FAULT_LOG command. Some contents of
the locked RAM fault log are also copied into EEPROM for
nonvolatile storage. See Fault Log Details below.
ꢉꢌꢇ Rꢏꢉꢌꢑꢋꢓꢎ
ꢇꢆꢋꢍꢑꢋꢒꢆꢒꢎꢅꢔ
ꢄꢑꢅꢅ ꢕꢒꢄꢄꢏR
ꢒꢋꢍꢑꢅ ꢄꢉꢒꢅꢍ
ꢁ
ꢅꢆꢇꢈ Rꢉꢊ
ꢅꢉꢍꢏꢎꢍ ꢙ
RꢏꢇꢆRꢌꢎ
ꢅꢉꢍꢏꢎꢍ ꢚ
RꢏꢇꢆRꢌꢎ
ꢉꢋꢌ ꢍRꢉꢋꢎꢄꢏR
ꢍꢆ ꢏꢏꢐRꢆꢊ
ꢉꢍ ꢍꢑꢊꢏ ꢆꢄ ꢄꢉꢒꢅꢍ
ꢖ
ꢖ
ꢖ
ꢖ
ꢖ
ꢖ
A fault log write to EEPROM is allowed above a die tem-
perature of 85°C, but 10 years of retention is not guaran-
teed. When die temperature exceeds 130°C, any EEPROM
fault log storage is delayed until the temperature drops
below 125°C.
ꢐꢊꢕꢗꢘ Rꢏꢉꢌ
ꢆꢄ ꢄꢉꢒꢅꢍ
ꢅꢆꢓ
ꢍRꢉꢋꢎꢄꢏR ꢄRꢆꢊ
ꢏꢏꢐRꢆꢊ ꢉꢄꢍꢏR
Rꢏꢎꢏꢍ
RAM BYTES
EEPROM BYTES
ꢀꢁꢁꢁꢂꢃ ꢄ0ꢀ
Once created, a fault log cannot be overwritten by sub-
sequent fault events, even if the log is only partial. An
MFR_FAULT_LOG_CLEAR command must be executed
to erase an existing log, leaving the IC free to generate a
new one.
Figure 3. Fault Log Conceptual Diagram
converted at the time of the fault is noted in the log header.
Referring to Figure 3, the six most recent event records
are maintained in internal RAM in reverse chronological
order. If input power is cycled or the part is reset after
a fault log is creatred, the RAM record is restored from
EEPROM where only the four most recent events are
retained due to available storage.
Faults propagated into the IC through FAULT pins do not
trigger a fault logging event, regardless of their impact on
PWM operation. Faults that generate a fault log should be
fully cleared before the log is erased to prevent creation
of spurious fault logs.
When the LTC3888-1 powers up it checks the EEPROM
for a valid fault log. If one is found the Fault Log Present
bit in STATUS_MFR_SPECIFIC is set. If the Memory Fault
Detected bit is also set in STATUS_CML, then the stored
Rev. 0
31
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LTC3888-1
OPERATION
Table 1. LTC3888-1 Fault Log Contents
STARTING
ENDING
BYTE
RECORD TYPE
BYTE
COMMENTS
Header Information
Fault Event Record
0
26
46
See Table 2.
27
Fault may have occurred anywhere during this event record. See byte 4 of Table 2 and all of
Table 3 and Table 4.
Event Record N-1
Event Record N-2
Event Record N-3
Event Record N-4
Event Record N-5
47
67
66
86
Last complete cyclical data read before the fault was detected.
Older data records…
87
106
126
146
107
127
Oldest recorded data.
Table 2. Fault Log Header Information
BLOCK
BYTE
RECORD
BITS
[7:0]
FORMAT COUNT DETAILS
Fault Log Preface
ASC
0
1
Returns LTxx beginning at byte 0 if a partial or complete fault log exists. Word xx is
a factory identifier that may vary part to part.
[7:0]
[15:8]
[7:0]
Reg
2
3
Fault Source
[7:0]
Reg
Reg
4
Refer to Table 3.
MFR_REAL_TIME
[7:0]
5
48 bit share-clock counter value when fault occurred (200µs resolution).
[15:8]
[23:16]
[31:24]
[39:32]
[47:40]
[15:8]
[7:0]
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
MFR_VOUT_PEAK (PAGE 0)
MFR_VOUT_PEAK (PAGE 1)
MFR_IOUT_PEAK (PAGE 0)
MFR_IOUT_PEAK (PAGE 1)
MFR_VIN_PEAK
L16
L16
L11
L11
L11
L11
L11
L11
Peak READ_VOUT on Channel 0 since last power-on or CLEAR_PEAKS command.
Peak READ_VOUT on Channel 1 since last power-on or CLEAR_PEAKS command.
Peak READ_IOUT on Channel 0 since last power-on or CLEAR_PEAKS command.
Peak READ_IOUT on Channel 1 since last power-on or CLEAR_PEAKS command.
Peak READ_VIN since last power-on or CLEAR_PEAKS command.
External temperature sensor 0 during last event.
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
READ_TEMPERATURE1 (PAGE 0)
READ_TEMPERATURE1 (PAGE 1)
READ_TEMPERATURE2
[15:8]
[7:0]
[15:8]
[7:0]
External temperature sensor 1 during last event.
[15:8]
[7:0]
Internal temperature sensor during last event.
Rev. 0
32
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LTC3888-1
OPERATION
Table 3. Fault Source Values
FAULT SOURCE VALUE
CAUSE OF FAULT LOG
TON_MAX
CHANNEL
0x00
0x01
0x02
0x03
0x05
0x07
0x0A
0x10
0x11
0x12
0x13
0x15
0x17
0x1A
0xFF
0
VOUT_OV
VOUT_UV
IOUT_OC
Over Temperature
VIN_OV
Internal Temperature
TON_MAX
1
VOUT_OV
VOUT_UV
IOUT_OC
Over Temperature
VIN_OV
Internal Temperature
MFR_FAULT_LOG_STORE
Table 4. Fault Log Event Record
DATA
BITS
[15:8]
[7:0]
FORMAT
RECORD BYTE INDEX
READ_VOUT (PAGE 0)
L16
0
1
READ_VOUT (PAGE 1)
MFR_TOTAL_IOUT (PAGE 0)
MFR_TOTAL_IOUT (PAGE 1)
READ_VIN
[15:8]
[7:0]
L16
L11
L11
L11
L11
2
3
[15:8]
[7:0]
4
5
[15:8]
[7:0]
6
7
[15:8]
[7:0]
8
9
(Not used)
[15:8]
[7:0]
10
11
12
13
14
15
16
17
18
19
STATUS_VOUT (PAGE 0)
STATUS_VOUT (PAGE 1)
STATUS_WORD (PAGE 0)
[7:0]
Reg
Reg
Reg
[7:0]
[15:8]
[7:0]
STATUS_WORD (PAGE 1)
[15:8]
[7:0]
Reg
STATUS_MFR_SPECIFIC (PAGE 0)
STATUS_MFR_SPECIFIC (PAGE 1)
[7:0]
Reg
Reg
[7:0]
Rev. 0
33
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LTC3888-1
OPERATION
FACTORY DEFAULT OPERATION
internal RAM, and that will permanently overwrite the fac-
tory defaults. Table 5 summarizes the default factory opera-
tion settings of the LTC3888-1 if all resistor configuration
pins are left open. These defaults allow parameters listed
in bold text in the table to be overridden with configuration
resistor programming. Warning limits are given in Table 5
because exceeding them will cause the ALERT pin to be
asserted even if the PMBus interface is not being utilized.
The LTC3888-1 ships from the factory with a default con-
figuration stored in its non-volatile memory unless custom
programming has been requested. These command values
are loaded into volatile RAM when the chip is initialized. Prior
to receiving any PMBus commands, a stock LTC3888-1 will
operate in the factory default mode. If a STORE_USER_
ALL command is executed, the contents of the non-volatile
memory are replaced with active command values from
Table 5. Factory Default Operation Summary
PARAMETER*
DEFAULT SETTING
UNITS
PMBus Address
All writes enabled to Channel 0 at address 0x4F (no PEC).
–
–
Operation
OPERATION enabled with RUN pin control and soft-off.
Input Voltage OFF Threshold
Input Voltage UV Warning Limit
Input Voltage ON Threshold
Input Voltage OV Fault Limit
Input Voltage OV Fault Response
Soft-Start Time
6.0
V
6.3
V
6.5
V
15.5
V
Latch off
–
1.6 (with no delay)
10
ms
ms
–
Maximum Start-Up Time (TMAX)
TMAX Fault Response
Retry every 350ms
Output Voltage UV Fault Limit
Output Voltage UV Fault Response
Output Voltage
–10% of nominal V
Retry every 350ms
–
OUT
–
Set by external R-divider (V = 400mV, V
servo disabled)
OUT
–
FB
Output Voltage OV Fault Limit
Output Voltage OV Fault Response
Shut Down
10% of nominal V
Latch off
–
OUT
–
1.6ms soft-off
5.0
–
Output Current Monitor Gain
Output Current OC Warning/Fault Limits
Output Current OC Fault Response
PWM Switching Frequency
Master/Slave Configuration
Internal Overtemperature Warning/Fault Limits
Internal Overtemperature Responses
External Overtemperature Warning/Fault Limits
External Overtemperature Fault Response
FAULT
mΩ
A
20/29.75
Ignore
–
500
kHz
–
4+4 (or 8-phase)
130/160
°C
–
Warning: EEPROM disabled; Fault: PWM disabled
85/100
°C
–
Retry every 350ms
Asserts low for the following faults: V
TON_MAX, or output short cycle
UV or OV, V OV, external or internal OT,
–
OUT
IN
ALERT Masking
Masked for loss of PLL lock and external fault inputs
–
*Bold entries can be changed with external configuration resistors
Rev. 0
34
For more information www.analog.com
LTC3888-1
OPERATION
SERIAL INTERFACE
The LTC3888-1 uses the following standard serial
interface protocols defined in the SMBus and PMBus
specifications:
The LTC3888-1 has a PMBus compliant serial interface
that can operate at any frequency between 10kHz and
400kHz. The LTC3888-1 is a bus slave device that commu-
nicates bidirectionally with a host (master) using standard
PMBus protocols. The Timing Diagram found earlier in
this document, along with related Electrical Characteristics
table entries, define the timing relationships of the SDA
and SCL bus signals. SDA and SCL must be high when
the bus is not in use. External pull-up resistors or current
sources are required on these lines.
• Quick Command
• Send Byte
• Write Byte
• Write Word
• Read Byte
• Read Word
• Block Read
PMBus, an incremental extension of the SMBus standard,
offers more robust operation than a 2-wire I C interface.
• Block Write – Block Read Process Call
2
• Alert Response Address
In addition to adding a protocol layer to improve interop-
erability and facilitate reuse, PMBus supports bus time-
out recovery for system reliability, optional packet error
checking (PEC) to ensure data integrity, and peripheral
hardware alerts for system fault management. In general,
The LTC3888-1 does not require PEC for Quick Command
under any circumstances. The LTC3888-1 also supports
group command protocol (GCP) as required by PMBus
specification Part I, section 5.2.3. GCP is used to send
commands to more than one PMBus device in one contin-
uous transmission. It should not be used with commands
that require the receiving device to respond with data,
such as a STATUS_BYTE command. Refer to Part I of the
PMBus specification for additional details on using GCP.
2
a programmable device capable of functioning as an I C
bus master can be configured for PMBus management
with little or no change to hardware. However, not all
2
I C controllers support repeat start (restart) required for
PMBus reads.
For a description of the minor extensions and exceptions
PMBus makes to the SMBus standard, refer to PMBus
Specification Part I Revision 1.2 Paragraph 5 on Transport.
All LTC3888-1 message transmission types allow
for packet error checking. The later section on Serial
Communication Errors provides more detail on packet
error checking.
For a description of the differences between SMBus
and I2C, refer to System Management Bus (SMBus)
Specification Version 2.0 Appendix B on Differences
Figure 5 to Figure 21 illustrate these protocols. Figure 4
provides a key to the protocol diagrams. Not all proto-
col elements will be present in every data packet. For
instance, not all packets are required to include the packet
error code. A number shown above a field in these dia-
grams indicates the number of bits in that field. All data
transfers are initiated by the present bus master regard-
less of how many times data direction flow may change
during the subsequent transmission. The LTC3888-1
never functions as a bus master.
2
Between SMBus and I C.
The user is encouraged to reference Part I of the latest
PMBus Power System Management Protocol Specification
to understand how to interface the LTC3888-1 to a PMBus
system. This specification can be found at http://www.
pmbus.org/specs.html.
This device includes handshaking features to ensure
robust system communication. Please refer to the PMBus
Communication and Command Processing section in
Applications Information for more details.
Rev. 0
35
For more information www.analog.com
LTC3888-1
OPERATION
ꢆ
ꢆꢇꢈRꢇ ꢉꢊꢋꢌꢍꢇꢍꢊꢋ
ꢆꢎ
Rꢏꢐꢏꢈꢇꢏꢌ ꢆꢇꢈRꢇ ꢉꢊꢋꢌꢍꢇꢍꢊꢋ
Rꢑ Rꢏꢈꢌ ꢒꢓꢍꢇ ꢔꢈꢕꢖꢏ ꢊꢄ ꢂꢗ
ꢘꢎ ꢘRꢍꢇꢏ ꢒꢓꢍꢇ ꢔꢈꢕꢖꢏ ꢊꢄ 0ꢗ
ꢈ
ꢈꢉꢙꢋꢊꢘꢕꢏꢌꢚꢏ ꢒꢓꢍꢇ ꢆꢛꢊꢖꢕꢌ ꢓꢏ 0ꢗꢜ ꢊR
ꢋꢈ ꢋꢊꢇ ꢈꢉꢙꢋꢊꢘꢕꢏꢌꢚꢏ ꢒꢓꢍꢇ ꢆꢛꢊꢖꢕꢌ ꢓꢏ ꢂꢗ
ꢐ
ꢆꢇꢊꢐ ꢉꢊꢋꢌꢍꢇꢍꢊꢋ
ꢐꢏꢉ ꢐꢈꢉꢙꢏꢇ ꢏRRꢊR ꢉꢊꢌꢏ
ꢝꢈꢆꢇꢏR ꢇꢊ ꢆꢕꢈꢔꢏ
ꢆꢕꢈꢔꢏ ꢇꢊ ꢝꢈꢆꢇꢏR
...
ꢉꢊꢋꢇꢍꢋꢖꢈꢇꢍꢊꢋ ꢊꢄ ꢐRꢊꢇꢊꢉꢊꢕ
ꢀꢁꢁꢁꢂꢃ ꢄ0ꢅ
Figure 4. PMBus Packet Protocol Diagram Element Key
ꢍ
ꢑ
ꢍ
ꢍ
ꢍ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢆꢇꢈꢉ
ꢂ
ꢊ
ꢋꢌꢌꢌꢍꢎ ꢏ0ꢐ
Figure 5. Quick Command Protocol
ꢏ
ꢓ
ꢏ
ꢏ
ꢎ
ꢏ
ꢏ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢊꢋ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢌ
ꢍꢎꢎꢎꢏꢐ ꢑ0ꢒ
Figure 6. Send Byte Protocol
ꢏ
ꢒ
ꢏ
ꢏ
ꢎ
ꢏ
ꢎ
ꢏ
ꢏ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢋꢌ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢊꢄꢆ
ꢂ
ꢊ
ꢍꢎꢎꢎꢏꢐ ꢑ0ꢒ
Figure 7. Send Byte Protocol with PEC
ꢒ
ꢕ
ꢒ
ꢒ
ꢑ
ꢒ
ꢑ
ꢒ
ꢒ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢍꢎ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢅꢂꢊꢂ ꢋꢌꢊꢄ
ꢂ
ꢏ
ꢐꢑꢑꢑꢒꢓ ꢔ0ꢑ
Figure 8. Write Byte Protocol
ꢒ
ꢖ
ꢒ
ꢒ
ꢑ
ꢒ
ꢑ
ꢒ
ꢑ
ꢒ
ꢒ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢍꢎ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢅꢂꢊꢂ ꢋꢌꢊꢄ
ꢂ
ꢏꢄꢆ
ꢂ
ꢏ
ꢐꢑꢑꢑꢒꢓ ꢔ0ꢕ
Figure 9. Write Byte Protocol with PEC
ꢒ
ꢕ
ꢒ
ꢒ
ꢑ
ꢒ
ꢑ
ꢒ
ꢑ
ꢒ
ꢒ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢍꢎ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢅꢂꢊꢂ ꢋꢌꢊꢄ ꢁꢇꢍ
ꢂ
ꢅꢂꢊꢂ ꢋꢌꢊꢄ ꢖꢗꢘꢖ
ꢂ
ꢏ
ꢐꢑꢑꢑꢒꢓ ꢔꢒ0
Figure 10. Write Word Protocol
Rev. 0
36
For more information www.analog.com
LTC3888-1
OPERATION
ꢒ
ꢕ
ꢒ
ꢒ
ꢑ
ꢒ
ꢑ
ꢒ
ꢑ
ꢒ
ꢑ
ꢒ
ꢒ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢍꢎ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢅꢂꢊꢂ ꢋꢌꢊꢄ ꢁꢇꢍ
ꢂ
ꢅꢂꢊꢂ ꢋꢌꢊꢄ ꢖꢗꢘꢖ
ꢂ
ꢏꢄꢆ
ꢂ
ꢏ
ꢐꢑꢑꢑꢒꢓ ꢔꢒꢒ
Figure 11. Write Word Protocol with PEC
ꢏ
ꢒ
ꢏ
ꢏ
ꢎ
ꢏ
ꢏ
ꢒ
ꢏ
ꢏ
ꢎ
ꢏ
ꢏ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢊꢋ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢀꢋ ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢖ
ꢂ
ꢅꢂꢓꢂ ꢔꢕꢓꢄ
ꢉꢂ
ꢌ
ꢍꢎꢎꢎꢏꢐ ꢑꢏꢐ
Figure 12. Read Byte Protocol
ꢏ
ꢒ
ꢏ
ꢏ
ꢎ
ꢏ
ꢏ
ꢒ
ꢏ
ꢏ
ꢎ
ꢏ
ꢎ
ꢏ
ꢏ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢊꢋ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢀꢋ ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢖ
ꢂ
ꢅꢂꢓꢂ ꢔꢕꢓꢄ
ꢂ
ꢌꢄꢆ
ꢂ
ꢌ
ꢍꢎꢎꢎꢏꢐ ꢑꢏꢍ
Figure 13. Read Byte Protocol with PEC
ꢏ
ꢓ
ꢏ
ꢏ
ꢎ
ꢏ
ꢏ
ꢓ
ꢏ
ꢏ
ꢎ
ꢏ
ꢎ
ꢏ
ꢏ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢊꢋ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢀꢋ ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢚ
ꢂ
ꢅꢂꢔꢂ ꢕꢖꢔꢄ ꢁꢇꢊ
ꢂ
ꢅꢂꢔꢂ ꢕꢖꢔꢄ ꢗꢘꢙꢗ ꢉꢂ
ꢌ
ꢍꢎꢎꢎꢏꢐ ꢑꢏꢒ
Figure 14. Read Word Protocol
ꢏ
ꢓ
ꢏ
ꢏ
ꢎ
ꢏ
ꢏ
ꢓ
ꢏ
ꢏ
ꢎ
ꢏ
ꢎ
ꢏ
ꢎ
ꢏ
ꢏ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢊꢋ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢀꢋ ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢚ
ꢂ
ꢅꢂꢔꢂ ꢕꢖꢔꢄ ꢁꢇꢊ
ꢂ
ꢅꢂꢔꢂ ꢕꢖꢔꢄ ꢗꢘꢙꢗ
ꢂ
ꢌꢄꢆ
ꢂ
ꢌ
ꢍꢎꢎꢎꢏꢐ ꢑꢏꢒ
Figure 15. Read Word Protocol with PEC
ꢎ
ꢌ
ꢎ
ꢎ
ꢍ
ꢎ
ꢎ
ꢌ
ꢎ
ꢎ
ꢍ
ꢎ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢊꢋ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢀꢋ ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢔ
ꢂ
ꢏꢐꢑꢄ ꢆꢇꢒꢉꢑ ꢓ ꢉ
ꢂ
ꢕ
ꢍ
ꢎ
ꢍ
ꢎ
ꢍ
ꢎ
ꢎ
ꢕ
ꢅꢂꢑꢂ ꢏꢐꢑꢄ ꢎ
ꢂ
ꢅꢂꢑꢂ ꢏꢐꢑꢄ ꢘ
ꢂ
ꢕ
ꢅꢂꢑꢂ ꢏꢐꢑꢄ ꢉ ꢉꢂ
ꢖ
ꢗꢍꢍꢍꢎꢘ ꢙꢎꢚ
Figure 16. Block Read Protocol
ꢎ
ꢌ
ꢎ
ꢎ
ꢍ
ꢎ
ꢎ
ꢌ
ꢎ
ꢎ
ꢍ
ꢎ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢊꢋ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢀꢋ ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢔ
ꢂ
ꢏꢐꢑꢄ ꢆꢇꢒꢉꢑ ꢓ ꢉ
ꢂ
ꢕ
ꢍ
ꢎ
ꢍ
ꢎ
ꢍ
ꢎ
ꢍ
ꢎ
ꢎ
ꢕ
ꢕ
ꢅꢂꢑꢂ ꢏꢐꢑꢄ ꢎ
ꢂ
ꢅꢂꢑꢂ ꢏꢐꢑꢄ ꢖ
ꢂ
ꢅꢂꢑꢂ ꢏꢐꢑꢄ ꢉ
ꢂ
ꢗꢄꢆ
ꢉꢂ
ꢗ
ꢘꢍꢍꢍꢎꢖ ꢙꢎꢌ
Figure 17. Block Read Protocol with PEC
Rev. 0
37
For more information www.analog.com
LTC3888-1
OPERATION
ꢓ
ꢑ
ꢓ
ꢓ
ꢒ
ꢓ
ꢒ
ꢓ
ꢒ
ꢓ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢏꢐ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢊꢋꢌꢄ ꢆꢇꢍꢉꢌ ꢎ ꢈ
ꢂ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢓ
ꢂ
ꢔ
ꢒ
ꢓ
ꢒ
ꢓ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢕ
ꢂ
ꢔ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢈ
ꢂ
ꢔ
ꢓ
ꢑ
ꢓ
ꢓ
ꢒ
ꢓ
ꢒ
ꢓ
ꢀꢐ ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢖ
ꢂ
ꢊꢋꢌꢄ ꢆꢇꢍꢉꢌ ꢎ ꢉ
ꢂ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢓ
ꢂ
ꢔ
ꢒ
ꢒ
ꢓ
ꢓ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢕ
ꢂ
ꢔ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢉ ꢉꢂ
ꢗ
ꢘꢒꢒꢒꢓꢕ ꢙꢓꢒ
Figure 18. Block Write – Block Read Process Call
ꢓ
ꢑ
ꢓ
ꢓ
ꢒ
ꢓ
ꢒ
ꢓ
ꢒ
ꢓ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢏꢐ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢊꢋꢌꢄ ꢆꢇꢍꢉꢌ ꢎ ꢈ
ꢂ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢓ
ꢂ
ꢔ
ꢒ
ꢓ
ꢒ
ꢓ
ꢔ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢕ
ꢂ
ꢔ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢈ
ꢂ
ꢔ
ꢓ
ꢑ
ꢓ
ꢓ
ꢒ
ꢓ
ꢒ
ꢀꢐ ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢖ
ꢂ
ꢊꢋꢌꢄ ꢆꢇꢍꢉꢌ ꢎ ꢉ
ꢂ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢓ
ꢂ
ꢔ
ꢒ
ꢓ
ꢒ
ꢓ
ꢒ
ꢓ
ꢓ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢕ
ꢂ
ꢔ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢉ
ꢂ
ꢗꢄꢆ
ꢉꢂ
ꢗ
ꢘꢒꢒꢒꢓꢕ ꢙꢓꢚ
Figure 19. Block Write – Block Read Process Call with PEC
ꢌ
ꢏ
ꢌ
ꢌ
ꢋ
ꢌ
ꢌ
ꢀꢁꢂRꢃ Rꢂꢄꢅꢆꢇꢄꢂ
ꢀꢈꢈRꢂꢄꢄ
ꢄ
Rꢉ
ꢀ
ꢈꢂꢐꢑꢒꢂ ꢀꢈꢈRꢂꢄꢄ ꢇꢀ
ꢅ
ꢊꢋꢋꢋꢌꢍ ꢎꢍ0
Figure 20. Alert Response Address Protocol
ꢌ
ꢊ
ꢌ
ꢌ
ꢋ
ꢌ
ꢋ
ꢌ
ꢌ
ꢀꢁꢂRꢃ Rꢂꢄꢅꢆꢇꢄꢂ
ꢀꢈꢈRꢂꢄꢄ
ꢄ
Rꢉ
ꢀ
ꢈꢂꢍꢎꢏꢂ ꢀꢈꢈRꢂꢄꢄ
ꢀ
ꢅꢂꢏ
ꢇꢀ
ꢅ
ꢐꢋꢋꢋꢌꢑ ꢒꢑꢌ
Figure 21. Alert Response Address Protocol with PEC
Rev. 0
38
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LTC3888-1
OPERATION
Serial Bus Addressing
Communication to LTC3888-1 devices at global and rail
addresses should be limited to command write operations.
The LTC3888-1 supports four types of serial bus
addressing:
Serial Bus Timeout
• Global Bus Addressing
The LTC3888-1 implements a timeout feature to avoid
hanging the serial interface. The data packet timer
begins running at the first START event before the SLAVE
ADDRESS write byte and ends with the STOP bit. Packet
transmission must be completed before the timer expires,
or the LTC3888-1 will tri-state the bus and ignore all mes-
sage data. The data packet includes the SLAVE ADDRESS
byte, COMMAND CODE byte, repeated START and SLAVE
ADDRESS byte (if a read operation), all ACKNOWLEDGE
and flow control bits (R/W) and all data bytes.
• Power Rail Addressing
• Individual Device Addressing
• Page+ Master Channel Addressing
Global addressing provides a means for the bus master
to communicate with all LTC3888-1 devices on the bus
simultaneously. The LTC3888-1 global addresses of 0x5A
and 0x5B cannot be changed or disabled. Commands sent
to address 0x5A are applied to both master channels as
if the PAGE command were set to 0xFF. Global address
0x5B is paged, allowing channel-specific control of all
LTC3888-1 devices on the bus. Other ADI device types
may respond at one or both of these global addresses.
Reading from global addresses is strongly discouraged.
The packet timer is typically set to 30ms. If bit 3 of MFR_
CONFIG_ALL is set, this period is extended to 255ms. The
LTC3888-1 automatically allows a packet transmission
time of 255ms for MFR_FAULT_LOG block reads regard-
less of the setting of this bit. In no circumstances will
the timeout period be less than the t
(25ms minimum).
specification
TIMEOUT
Rail addressing provides a means for the bus master to
simultaneously communicate with all master channels
connected together to produce a single output voltage
(PolyPhase). While similar to global addressing, the rail
address can be dynamically assigned with the paged
MFR_RAIL_ADDRESS command, allowing for any logi-
cal grouping of channels that might be required for reli-
able system control. Reading from rail addresses is also
strongly discouraged.
The LTC3888-1 supports a PMBus frequency range of
10kHz to 400kHz.
Serial Communication Errors
The LTC3888-1 supports the optional PMBus packet
error checking protocol. This protocol appends a packet
error code (PEC) to the end of applicable message trans-
fers to improve communication reliability. The PEC is a
CRC-8 error-checking byte calculated by the bus device
Device addressing is the most common means used by
a bus master to communicate with an LTC3888-1. The
value of the device address is set by the combination of sending the last data byte. Refer to SMBus specification
1.2 or higher for additional implementation details. All
LTC3888-1 read operations will return a valid PEC if the
bus master requests it. If bit 2 in the MFR_CONFIG_ALL
command is set, the IC will not act in response to a bus
write operation unless a valid PEC is also received from
the host.
ASEL0/ASEL1 pin programming and the MFR_ADDRESS
command. Refer to the previous section on Resistor
Configuration Pins for details.
Direct, individual channel addressing (Page+) allows
the bus master to communicate directly with a specific
LTC3888-1 PWM master channel without first using a
PAGE command. Refer to the PAGE_PLUS commands
for additional details.
PEC errors on command writes, attempts to access
unsupported commands, or writing invalid data to sup-
ported commands all cause the LTC3888-1 to generate a
CML fault. The CML bit is then set in the STATUS_BYTE
and STATUS_WORD commands, and the appropriate bit
Use of any of the four types of addressing requires
careful planning to avoid address-related bus conflicts.
is set in the STATUS_CML command.
Rev. 0
39
For more information www.analog.com
LTC3888-1
PMBUS COMMAND SUMMARY
PMBus Commands
II, Section 10.8.7, to communicate that it is busy. This
device includes handshaking features to eliminate busy
responses, simplify error handling software and ensure
robust communication and system behavior. Please refer
to PMBus Communication and Command Processing in
the Applications Information section for further details.
Table 7 lists supported PMBus commands and manufac-
turer specific commands. Additional information about
these commands can be found in Revision 1.2 of Part
II of the PMBus Power System Management Protocol
Specification. Users are encouraged to reference that
manual. Exceptions or manufacturer-specific implementa-
tions are detailed in the tables below. All standard PMBus
commands from 0x00 through 0xCF not listed in this table
are implicitly not supported by the LTC3888-1. All com-
mands from 0xD0 through 0xFF not listed in Table 7 are
implicitly reserved by the manufacturer. The LTC3888-1
may execute additional commands not listed in this table,
and these can change without notice. Reading these
unlisted commands is harmless to the operation of the
IC. Writes to any unsupported or reserved command
should be avoided, as that may result in a CML fault and/
or undesired operation of the part.
ADI has made an effort to establish PMBus command
compatibility and functional uniformity among its family
of parts. However, differences may occur due to specific
product requirements. Compatibility of PMBus commands
among any ICs should not be assumed based simply on
command name. Always refer to the manufacturer’s data
sheet of each device for a complete definition of a com-
mand function.
Data Formats
PMBus supports specific floating point number formats
and allows for a wide range of other data formats.
If PMBus commands are received faster than they are
being processed, the part may become too busy to handle
new commands. In these cases the LTC3888-1 follows the
protocols defined in the PMBus Specification V1.2, Part
Table 6 describes the data formats used by the LTC3888-1.
Abbreviations of these formats appear throughout this
document.
Table 6. Abbreviations of Supported Data Formats
PMBus
SPECIFICATION
ADI
TERMINOLOGY
L11 Linear
REFERENCE TERMINOLOGY DEFINITION
EXAMPLE
N
Part II ¶7.1
Linear_5s_11s Floating point 16-bit data: value = Y • 2 , b[15:0] = 0x9807 = 10011_000_0000_0111
–13
where N = b[15:11] and Y = b[10:0], both value = 7 • 2 = 854E-6
two’s compliment binary integers.
–12
L16 Linear VOUT_MODE
CF DIRECT
Part II ¶8.2
Part II ¶7.2
Linear_16u
Varies
Reg
Floating point 16-bit data: value = Y • 2
where Y = b[15:0], an unsigned integer.
,
b[15:0] = 0x4C00 = 0100_1100_0000_0000
–12
value = 19456 • 2 = 4.75
Data with a custom format defined in the
detailed PMBus command description.
Often an unsigned or two’s compliment
integer.
Reg Register Bits
Part II ¶10.3
Part II ¶22.2.1
Per-bit meaning defined in detailed PMBus PMBus STATUS_BYTE command.
command description.
ASC Text Characters
ASCII
ISO/IEC 8859-1 [A05]
LTC (0x4C5443)
Rev. 0
40
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LTC3888-1
PMBUS COMMAND SUMMARY
Table 7. PMBus Command Summary
CMD
DATA
DEFAULT
VALUE
SEE
PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
PAGE
0x00 Channel (page) presently selected for
any paged command.
R/W Byte
N
Reg
0x00
67
l
l
OPERATION
0x01 On, off and margin control.
R/W Byte
R/W Byte
Y
Y
Reg
Reg
0x80
0x1E
71
70
ON_OFF_CONFIG
0x02 RUN pin and PMBus on/off command
configuration.
CLEAR_FAULTS
0x03 Clear all set fault bits.
Send Byte
W Block
N
N
91
67
PAGE_PLUS_WRITE
0x05 Write a command directly to a specified
page.
PAGE_PLUS_READ
WRITE_PROTECT
STORE_USER_ALL
RESTORE_USER_ALL
CAPABILITY
0x06 Read a command directly from a
specified page.
Block R/W
Process
N
N
N
N
N
Y
Y
68
68
l
0x10 Protect the device against unintended
PMBus modifications.
R/W Byte
Send Byte
Send Byte
R Byte
Reg
0x00
0xB0
0x15 Store entire operating memory in
EEPROM.
102
102
69
0x16 Restore entire operating memory from
EEPROM.
0x19 Summary of supported optional PMBus
features.
Reg
Reg
L11
l
l
SMBALERT_MASK
VOUT_TRANSITION_RATE
0x1B Mask ALERT activity.
Block R/W
see CMD
details
99
0x27 Slew rate for V (default) or V
soft-on/ R/W Word
V/ms
0.25
AA00
88
FB
OUT
off and margining, including changes to
VOUT_COMMAND.
l
l
l
l
FREQUENCY_SWITCH
VIN_ON
0x33 PWM frequency control.
R/W Word
R/W Word
N
N
N
Y
Y
L11
L11
L11
L11
Reg
kHz
V
500kHz
0xFBE8
72
78
78
81
95
0x35 Minimum input voltage to begin power
conversion.
6.5V
0xCB40
VIN_OFF
0x36 Decreasing input voltage at which power R/W Word
conversion stops.
V
6.0V
0xCB00
IOUT_CAL_GAIN
0x38 Ratio of I
voltage to sensed current. R/W Word
mΩ
5mΩ
0xCA80
SENSE
VOUT_OV_FAULT_RESPONSE 0x41 Fault response for V
power stage fault.
overvoltage and
R Byte
0x80
0xB8
OUT
l
l
VOUT_UV_FAULT_RESPONSE 0x45
V
OUT
undervoltage fault response.
R/W Byte
Y
Y
Reg
L11
96
82
IOUT_OC_FAULT_LIMIT
0x46 Output overcurrent fault limit.
R/W Word
A
29.75A
0xDBB8
l
l
IOUT_OC_FAULT_RESPONSE
IOUT_OC_WARN_LIMIT
0x47 Output overcurrent fault response.
0x4A Output overcurrent warning limit.
R/W Byte
Y
Y
Reg
L11
0x00
97
82
R/W Word
A
20.0A
0xDA80
l
OT_FAULT_LIMIT
0x4F External overtemperature fault limit.
R/W Word
Y
L11
°C
100.0°C
0xEB20
85
l
l
OT_FAULT_RESPONSE
OT_WARN_LIMIT
0x50 External overtemperature fault response. R/W Byte
0x51 External overtemperature warning limit. R/W Word
Y
Y
Reg
L11
0xB8
98
85
°C
85.0°C
0xEAA8
Rev. 0
41
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LTC3888-1
PMBUS COMMAND SUMMARY
Table 7. PMBus Command Summary
CMD
DATA
DEFAULT
VALUE
SEE
PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
l
VIN_OV_FAULT_LIMIT
0x55
V
IN
overvoltage fault limit.
R/W Word
N
L11
V
15.5V
0xD3E0
78
l
l
VIN_OV_FAULT_RESPONSE
VIN_UV_WARN_LIMIT
0x56
0x58
V
V
overvoltage fault response.
undervoltage warning limit.
R/W Byte
Y
N
Reg
L11
0x80
96
78
IN
R/W Word
V
6.3V
0xCB26
IN
l
l
TON_DELAY
0x60 Delay from RUN pin or OPERATION on
command to V ramp start.
R/W Word
R/W Word
Y
Y
L11
L11
ms
ms
0.0ms
83
84
0x8000
OUT
TON_MAX_FAULT_LIMIT
0x62 Maximum time allowed for V
to rise
10.0ms
0xD280
OUT
above VOUT_UV_FAULT_LIMIT after
TON_DELAY.
l
l
TON_MAX_FAULT_RESPONSE 0x63 Fault response when TON_MAX_FAULT_ R/W Byte
LIMIT is exceeded.
Y
Y
Reg
L11
0xB8
98
84
TOFF_DELAY
0x64 Delay from RUN pin or OPERATION off
command to TOFF_FALL ramp start.
R/W Word
ms
0.0ms
0x8000
STATUS_BYTE
0x78 One-byte channel status summary.
0x79 Two-byte channel status summary.
R/W Byte
R/W Word
R/W Byte
R/W Byte
R/W Byte
R/W Byte
Y
Y
Y
Y
N
Y
Reg
Reg
Reg
Reg
Reg
Reg
86
87
87
88
88
88
STATUS_WORD
STATUS_VOUT
0x7A
0x7B
V
fault and warning status.
fault and warning status.
OUT
STATUS_IOUT
I
OUT
STATUS_INPUT
STATUS_ TEMPERATURE
0x7C Input supply fault and warning status.
0x7D External temperature fault and warning
status.
STATUS_CML
0x7E Communication, memory and logic fault R/W Byte
and warning status.
N
Reg
89
STATUS_MFR_ SPECIFIC
READ_VIN
0x80 IC-specific status.
0x88 Measured V .
R/W Byte
R Word
R Word
R Word
R Word
R Word
R Word
R Byte
Y
N
Y
Y
Y
N
Y
N
Reg
L11
L16
L11
L11
L11
L11
Reg
89
92
93
93
94
94
94
69
V
V
IN
READ_VOUT
0x8B Measured V
.
OUT
READ_IOUT
0x8C Measured I
.
A
OUT
READ_TEMPERATURE_1
READ_TEMPERATURE_2
READ_FREQUENCY
PMBUS_REVISION
0x8D Measured external temperature.
0x8E Measured internal temperature.
0x95 Measured PWM input clock frequency.
0x98 Supported PMBus version.
°C
°C
kHz
0x22
V1.2
MFR_ID
0x99 Manufacturer identification.
0xAD LTC3888-1 model number.
R String
R String
N
N
ASC
ASC
LTC
104
IC_DEVICE_ID
LTC3888-1 104
Commands for Digital Output Voltage Control (See Applications Information or PMBus Command for Details)
VOUT_MODE
0x20 Voltage-related format (Linear) and
exponent.
R Byte
Y
Reg
0x14
82
82
–12
2
l
VOUT_COMMAND
0x21 Default Nominal V regulation. Nominal R/W Word
Y
L16
V
V
400mV
0x0666
FB
V
value when VOUT_SCALE_LOOP
OUT
is defined.
VOUT_MAX
0x24 Maximum V
capability.
R Word
Y
L16
1.1V
0x119A
82
OUT
Rev. 0
42
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LTC3888-1
PMBUS COMMAND SUMMARY
Table 7. PMBus Command Summary
CMD
DATA
DEFAULT
VALUE
SEE
PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
Commands for Digital Output Voltage Control (Continued)
l
VOUT_MARGIN_HIGH
VOUT_MARGIN_LOW
VOUT_SCALE_LOOP
0x25
0x26
V
(default) or V
at high margin,
R/W Word
R/W Word
R/W Word
R/W Word
R/W Word
Y
Y
Y
Y
Y
Y
Y
Y
L16
L16
L11
L16
L16
L16
L16
L11
V
V
420mV
0x06B8
83
83
83
83
83
84
84
88
FB
OUT
must be greater than VOUT_COMMAND.
l
l
l
l
l
l
l
V
(default) or V at low margin,
380mV
0x0614
FB
OUT
must be less than VOUT_COMMAND.
0x29 Nominal V / V gain provided by
V/V
V
N/A
OUT FB
external feedback network.
VOUT_OV_FAULT_LIMIT
VOUT_OV_WARN_LIMIT
VOUT_UV_WARN_LIMIT
VOUT_UV_FAULT_LIMIT
TOFF_MAX_WARN_LIMIT
0x40 Default V overvoltage fault limit. V
440mV
0x070A
FB
OUT
OV limit if VOUT_SCALE_LOOP is defined.
0x42
0x43
V
overvoltage warning limit, sensed
V
3.6V
0x3981
OUT
at V
.
SENSE
V
undervoltage warning limit, sensed R/W Word
V
0.0V
0x0000
OUT
at V
.
SENSE
0x44 Default V undervoltage fault limit. V
R/W Word
R/W Word
V
360mV
0x05C3
FB
OUT
UV limit if VOUT_SCALE_LOOP is defined.
0x66 Maximum time for V
to reach
ms
0ms
0x8000
OUT
0.125xVOUT_COMMAND after being
commanded to 0.0V.
LTC3888-1 Custom Commands
MFR_VOUT_MAX
0xA5 Maximum VOUT_MAX.
R Word
Y
L16
V
3.75V
0x3C00
79
l
l
l
l
USER_DATA_00
USER_DATA_01
USER_DATA_02
USER_DATA_03
0xB0 EEPROM word reserved for LTpowerPlay. R/W Word
0xB1 EEPROM word reserved for LTpowerPlay. R/W Word
N
Y
N
Y
Reg
Reg
Reg
Reg
103
103
103
103
0xB2 EEPROM word reserved for OEM use.
R/W Word
0xB3 EEPROM word available for general data R/W Word
storage.
0x0000
0x0000
l
USER_DATA_04
0xB4 EEPROM word available for general data R/W Word
storage.
N
N
Reg
Reg
103
MFR_INFO
0xB6 Manufacturer-specific information
0xBD (contact the factory)
R Word
91
103
103
103
73
MFR_EE_UNLOCK
MFR_EE_ERASE
MFR_EE_DATA
0xBE (contact the factory)
0xBF (contact the factory)
l
l
l
MFR_CHAN_CONFIG
MFR_CONFIG_ALL
MFR_FAULT_PROPAGATE
0xD0 General channel-specific configuration.
0xD1 General device-level configuration.
R/W Byte
R/W Byte
R/W Word
Y
N
Y
Reg
Reg
Reg
0x1D
0x21
70
0xD2 Configure fault propagation via FAULT
0x6993
100
pins.
l
l
l
MFR_PWM_COMP
0xD3 Channel-specific PWM loop
compensation.
R/W Byte
Y
Y
Y
N
Reg
Reg
Reg
Reg
0xAE
0x02
0xC0
0xC0
77
76
MFR_PWM_MODE_LTC3888-1 0xD4 LTC3888-1 channel-specific PWM mode R/W Byte
control.
MFR_FAULT_RESPONSE
0xD5 PWM response when FAULT pin is low
R/W Byte
101
98
due to external fault.
MFR_OT_FAULT_RESPONSE
0xD6 Internal overtemperature fault response.
R Byte
Rev. 0
43
For more information www.analog.com
LTC3888-1
PMBUS COMMAND SUMMARY
Table 7. PMBus Command Summary
CMD
DATA
DEFAULT
VALUE
SEE
PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
MFR_IOUT_PEAK
0xD7 Maximum master channel
R Word
Y
L11
A
93
I
measurement since last
OUT
MFR_CLEAR_PEAKS.
l
l
MFR_RETRY_DELAY
MFR_RESTART_DELAY
MFR_VOUT_PEAK
MFR_VIN_PEAK
0xDB Minimum time before retry after a fault. R/W Word
Y
Y
Y
N
Y
L11
L11
L16
L11
L11
ms
ms
V
350ms
99
83
93
93
94
0xFABC
0xDC Minimum time RUN pin is held low by
the LTC3888-1.
R/W Word
R Word
R Word
R Word
500ms
0xFBE8
0xDD Maximum V
measurement since last
OUT
MFR_CLEAR_PEAKS.
0xDE Maximum V measurement since last
V
IN
MFR_CLEAR_PEAKS.
MFR_TEMPERATURE_1_PEAK 0xDF Maximum external temperature
measurement since last MFR_CLEAR_
°C
PEAKS (LTC3888-1 only).
MFR_TOTAL_IOUT
0xE1 Read total IOUT for each
page/rail defined by
R Word
Y
L11
A
93
MFR_PWM_CONFIG_LTC3888-1[2:0]
MFR_CLEAR_PEAKS
MFR_PADS_LTC3888-1
MFR_ADDRESS
0xE3 Clear all peak values.
Send Byte
R Word
N
N
N
94
90
69
0xE5 State of selected LTC3888-1 pads.
Reg
Reg
l
0xE6 Specify right-justified 7-bit device
address.
R/W Byte
0x4F
MFR_SPECIAL_ID
0xE7 Unique manufacturer product ID
R Word
N
N
Reg
0x488X
103
103
MFR_FAULT_LOG_STORE
0xEA Force capture of fault log in RAM and
transfer to EEPROM.
Send Byte
MFR_FAULT_LOG_CLEAR
MFR_FAULT_LOG
0xEC Clear existing EEPROM fault log.
0xEE Read fault log data.
Send Byte
R Block
N
N
N
N
101
101
90
Reg
Reg
MFR_COMMON
0xEF ADI-generic device status reporting.
R Byte
MFR_COMPARE_USER_ALL
0xF0 Compare contents of command RAM
with EEPROM.
Send Byte
93
MFR_TEMPERATURE_2_PEAK 0xF4 Maximum internal temperature
measurement since last
R Word
N
N
L11
Reg
°C
94
73
MFR_CLEAR_PEAKS.
l
MFR_PWM_CONFIG_
LTC3888-1
0xF5 LTC3888-1 PWM configuration common R/W Byte
to both master channels.
0x03
0x00
MFR_LOAD_EMULATION
MFR_TEMP_1_GAIN
0xF7 Load step emulation control.
R/W Byte
Y
Y
Reg
L11
81
85
l
l
l
0xF8 Slope for external temperature
calculations (LTC3888-1 only).
R/W Word
mV/ °C
mV
8 mV/ °C
0xD200
MFR_TEMP_1_OFFSET
MFR_RAIL_ADDRESS
0xF9 0 °C offset for external temperature
calculations (LTC3888-1 only).
R/W Word
R/W Byte
Y
Y
L11
Reg
600mV
0x0258
85
69
0xFA Specify unique right-justified 7-bit
address for channels comprising a
PolyPhase output.
0x80
MFR_RESET
0xFD Force full reset without removing power. Send Byte
N
71
NVM
l
Indicates a command value stored to and restored from internal EEPROM using the STORE_USER_ALL and RESTORE_USER_ALL commands,
respectively.
Rev. 0
44
For more information www.analog.com
LTC3888-1
APPLICATIONS INFORMATION
EFFICIENCY CONSIDERATIONS
Other sources of loss include internal body or external
Schottky diode conduction during the power stage FET
driver non-overlap time, as well as inductor core losses.
These latter categories generally account for less than 2%
total additional loss.
Normally, one of the primary goals of any LTC3888-1
application will be to obtain the highest practical conver-
sion efficiency. The efficiency of a switching regulator is
equal to the output power divided by the input power. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and to ascertain which change
would produce the most improvement. Balancing or limit-
ing these individual losses plays a dominant role in the
component selection process outlined over the next few
sections.
POWER STAGE SELECTION AND INTERFACE
The LTC3888-1 operates with power stages that provide
a voltage or current monitor of the output current they
sense. As a minimum, these stages must also accept
3.3V-compatible three-state PWM input control. Other
features such as PWM input off-state biasing, power
stage temperature monitoring, fault detection and indi-
cation, and UVLO protection are optional. Examples of
these kinds of devices include the TDA21470, IR35411
and FDM3170.
Percent efficiency can be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + …)
where L1, L2, et al, are the individual losses as a percent-
age of input power: 100 • P /P .
Ln IN
Although all dissipative elements in the system produce
losses, four main sources usually account for most of
the losses in LTC3888-1 applications: IC supply current,
The LTC3888-1 I
pins are high impedance inputs to
SENSE
internal interface circuits and the monitor ADC, both using
a common mode of IREF (1.6V). Maximum instantaneous
differential current sense input relative to IREF is 525mV,
and maximum DC input differential is 400mV. These
inputs must be properly connected in the application at
all times. While not strictly required, it is recommended
to short ISENSE to IREF on PWM channels disabled by
MFR_PWM_CONFIG_LTC3888-1 master/slave setting.
2
I R losses, topside power MOSFET transition losses and
total gate drive current.
1. The LTC3888-1 IC supply current is a DC value given
in the Electrical Characteristics table. The absolute
loss created by the IC itself is approximately this cur-
rent times the V supply voltage. IC supply current
IN
typically results in a small loss (<0.1%).
As shown in Figure 22 and Figure 23, the LTC3888-1 is
designed to interface to power stages that provide either
a current or voltage analog of sensed output current.
The LTC3888-1 IREF output should be used to provide
the common mode voltage for this output current moni-
tor, with some bypass located adjacent to each power
stage and returned to GND (IC paddle). The LTC3888-1
is designed to work best when the power stage output
current monitor is scaled to provide between 3mV/A and
2
2. I R losses occur mainly in the DC resistances of the
selected power stage, inductor, PCB routing, and
input and output capacitor ESR. It is crucial that care-
ful attention is paid to the layout of the power path on
the PCB to minimize that resistance. In a 2-phase 1.2V
system, 1mΩ of PCB resistance at the output costs
5% in efficiency with the output running at 60A.
3. Transition losses apply only to the selected power
stage and normally do not become significant until
operating above 12V.
10mV/A to its I
input. This scaling must be identical
SENSE
for all phases on a rail. For most power stages providing
a voltage-mode monitor, no additional external scaling
components are required.
4. Gate drive current is equal to the sum of the top and
bottom MOSFET gate charges multiplied by the fre-
quency of operation. These charges are based on
internal power stage design and are normally included
in overall efficiency (or power loss) numbers provded
by the manufacturer at a given operating condtion.
Some of these power stages require the controller to pro-
vide a PWM pulse with a minimum width. The LTC3888-1
can be configured to accommodate this requirement by
setting bit 1 of MFR_PWM_MODE_LTC3888-1.
Rev. 0
45
For more information www.analog.com
LTC3888-1
APPLICATIONS INFORMATION
The LTC3888-1 TSNS pins interface directly to the wire-
OR shared TEMP/FAULT bus found on most power stages
offering output current monitor. When all phases are fault-
free, the voltage on this bus indicates the highest power
stage temperature on the rail. The internal monitor ADC
converts this voltage, and the computed temperature
value is returned by the paged READ_TEMPERATURE_1
telemetry command. The slope of the external tempera-
ture sensor can be modified to fit the selected power stage
using the coefficient stored in MFR_TEMP_1_GAIN. The
offset of the external temperature sense can be adjusted
by MFR_TEMP_1_OFFSET, which designates the bus volt-
age indicating 0°C.
ꢈꢑꢆꢒ
ꢈ
ꢀꢄꢒꢀꢄ
ꢄꢔꢅꢄRꢒꢂꢃ ꢎꢆꢏꢄR
ꢀꢅꢂꢐꢄ
ꢃꢅꢁꢕꢖꢖꢖꢚꢗ
ꢈRꢄꢓ
Rꢄꢓꢈꢒ
ꢐꢒꢙ
0.ꢛꢜꢝꢓ
ꢕꢖꢖꢖꢗꢘ ꢓꢘꢘ
ꢅꢆ ꢆꢅꢇꢄR
ꢎꢆꢏꢄR
ꢀꢅꢂꢐꢄꢀ
ꢀꢁꢂꢃꢄ ꢅꢆ
ꢂꢁꢇꢈꢄꢉꢄ
ꢊꢋꢌꢉꢍꢂ
Figure 22. Interface to Current-Mode Output Current Sense
ꢉ
ꢉ
ꢆꢃꢌꢆꢃ
ꢁꢊꢀ
The LTC3888-1 also recognizes indicated power stage
fault conditions on the shared TEMP/FAULT bus. This
includes support for optional power stage UV indication
when enabled with bit 0 of MFR_PWM_MODE_LTC3888-
1. These events are reported through standard PMBus
status registers for improved system state observation
by the bus host as shown in Table 8. Refer to previ-
ous Operation section discussions on Hardwired PWM
Response to Power Stage Faults and Status Registers
and ALERT Masking for additional details.
ꢃꢍꢀꢃRꢌꢇꢎ ꢄꢁꢅꢃR
ꢆꢀꢇꢈꢃ
ꢎꢀꢔꢏꢐꢐꢐꢕꢑ
ꢉRꢃꢋ
Rꢃꢋꢉꢌ
ꢈꢌꢓ
0.ꢖꢗꢘꢋ
ꢏꢐꢐꢐꢑꢒ ꢋꢒꢏ
ꢀꢁ ꢁꢀꢂꢃR
ꢄꢁꢅꢃR
ꢆꢀꢇꢈꢃꢆ
Figure 23. Interface to Voltage-Mode Output Current Sense
Table 8. Special LTC3888-1 Status Indications1
5
PAGED
MFR_PADS_LTC3888-1
STATUS_VOUT
BIT 7
(VOUT_OV FAULT)
STATUS_VOUT
BIT 4
(VOUT_UV FAULT)
CH0/1 DrMOS
CONDITION
INDICATED
STATUS_IOUT
BIT 3
READY
BIT 14/15
V
V
V
OV
•
•
•
•
OUT
OUT
UV
•
•
2,3
+
OPEN
•
SENSE
Power Stage UV
•
4
(TSNS) or VDR
(IFF CH Set to Run)
Monitor UV
6
Power Stage Fault
•
•
•
1
+
With the exception of V
Open, all VOUT_OV Fault conditions are handled by VOUT_OV_FAULT_RESPONSE, which is immediate off with no retry,
SENSE
and a VOUT_UV fault condition is handled by VOUT_UV_FAULT_RESPONSE.
2
+
+
line is to disable all
Both V
lines are tested each time the LTC3888-1 powers up or resets. The response of the LTC3888-1 for any open V
SENSE
SENSE
outputs. A detected open line condition can only be cleared with successful retesting by power cycle or MFR_RESET.
3
Both bit 7 and bit 4 of STATUS_VOUT may also be set if a power stage UV or fault occurs during a true V
UV with the PWM still running. In this case
OUT
STATUS_IOUT and MFR_PADS will continue to accurately indicate power stage state, which does not require a full reset to clear.
4
Detection of this condition must be enabled by setting bit 0 of MFR_PWM_MODE_LTC3888-1 (paged). No UV indication is given or response taken if bit
0 of MFR_PWM_MODE_LTC3888-1 is clear.
5
MFR_PADS_LTC3888-1[15:14] respond to enabled power stage UV detection by indicating NOT READY (1’b0) for their respective channels, regardless
of PWM run state. Otherwise these bits indicate READY (1’b1).
6
The exact nature of fault indicated in this case varies by manufacturer and can include such issues as gross output overcurrent or power stage
overtemperature.
Rev. 0
46
For more information www.analog.com
LTC3888-1
APPLICATIONS INFORMATION
If power stage UV detection is enabled, a check of the
MFR_PADS_LTC3888-1 status bits shown in Table 8 is
strongly recommended before turning on a rail. Otherwise,
if the power stage UV is in the process of clearing during
system power-up, the resulting LTC3888-1 fault condition
cannot be distinquished from overvoltage on the output.
required, unused TSNS inputs may be left open or wired
to GND as long as bit 0 of MFR_PWM_MODE_LTC3888-1
(paged) is left clear. The LTC3888-1 will then continue to
respond to READ_TEMPERATURE_1 requests, but the
data returned will be meaningless.
PWM FREQUENCY AND INDUCTOR SELECTION
USING THE VDR MONITOR
The selection of the PWM switching frequency is a trade-
off between efficiency, transient response and compo-
nent size. High frequency operation reduces the size of
the inductor and output capacitor as well as increasing
the maximum practical control loop bandwidth. However,
efficiency is generally lower due to increased transition
and switching losses. The inductor value is related to the
When a shared TEMP/FAULT bus is not provided from the
power stages in an application, or if a necessary UV indica-
tion is not provided by the particular power stage selected,
pin 8 of the LTC3888-1 can be programmed to function
as a VDR_MON input by bit 5 of MFR_CHAN_CONFIG on
Page 0 to observe UV conditions on the power stage gate
drive supply. As shown in Figure 24 this simply requires
sensing the supply to be monitored with a resistor divider
that produces 1.22V at the desired UV threshold.
switching frequency f
and step-down ratio. It should
PWM
be selected to meet choke ripple current requirements.
The inductor value can be calculated using the following
equation:
V
UV
= 1.22V • (R1+R2)/R2
⎛
⎞
⎛
⎞
⎟
⎠
ꢁ
ꢁ
ꢂꢃꢄ
ꢁ
ꢊꢍ
A single VDR_MON input is provided for both master
channels. The state of bit 0 of MFR_PWM_CONFIG_
LTC3888-1 is ignored and UV detection on TSNS1 fully
disabled when VDR_MON is active.
ꢂꢃꢄ
ꢉ Δꢊ
ꢀ =
ꢉ ꢋꢌ
⎜
⎜
⎟
ꢅ
⎝
⎝
⎠
ꢆꢇꢈ
ꢀ
Allowing a larger value of choke ripple current (ΔI ) leads
L
to smaller L, but results in greater core loss and higher
output voltage ripple for a given output capacitance and/
or ESR. A reasonable starting point for setting the ripple
current is 30% of the maximum output current.
UNUSED TSNS INPUTS
In cases where a shared TEMP/FAULT bus is not avail-
able or monitoring of external temperature is simply not
ꢆꢇ ꢇꢆꢚꢖR
ꢔꢇꢕꢖR
ꢗꢆꢈꢍꢖꢗ
ꢘꢏ ꢈꢉꢙ
Rꢂ
ꢊꢆꢋꢀꢁꢁꢁꢓꢂ
ꢏꢐRꢑꢒꢇꢌ
ꢆꢇ ꢄꢈꢉꢊꢆ
ꢏꢐR ꢉꢏ
ꢋꢇꢌꢆRꢇꢊ
ꢊꢇꢍꢎꢋ
Rꢃ
ꢏ
ꢎꢌ
ꢏꢐRꢏ
ꢔꢇꢕꢖR ꢗꢆꢈꢍꢖ
ꢂ.ꢃꢃꢏ
ꢊꢂ
ꢍꢈꢆꢖ
ꢐRꢎꢏꢖR
ꢔꢕꢒ0
ꢏ
ꢇꢉꢆ
ꢋ
ꢇꢉꢆ
ꢀꢁꢁꢁꢂꢃ ꢄꢃꢅ
Figure 24. LTC3888-1 Power Stage VDR Monitor
Rev. 0
47
For more information www.analog.com
LTC3888-1
APPLICATIONS INFORMATION
The inductor saturation current rating needs to be higher
than the peak inductor current during transient condi-
far more capacitance than is required to keep capacitance-
based droop under control.
tions. If I
is the maximum rated load current, then the
OUT
The input capacitance voltage rating should be at least 1.4
times the maximum input voltage. Power loss due to ESR
maximum transient current I
would normally be cho-
MAX
sen to be some factor greater than I
(e.g., 1.6 • I ).
2
OUT
OUT
occurs as I R dissipation in the capacitor itself. The input
capacitor RMS current and its impact on any preceding
input network is reduced by PolyPhase architecture. It can
be shown that the worst case RMS current occurs when
only one phase is operating. The phase with the highest
(VOUT)(IOUT) product should be used to determine the
The minimum saturation current rating should be chosen
to allow margin due to manufacturing and temperature
variation in the power stage output current monitor. A
reasonable I value would be 2.2 • I
.
SAT
OUT
The programmed current limit IOUT_OC_FAULT_LIMIT
must be low enough to ensure that the inductor never
saturates and high enough to allow increased current dur-
ing transient conditions. For example, if:
maximum RMS current requirement. Increasing the num
-
ber of phases will decrease the input RMS ripple current
from this maximum value. 2-phase operation typically
reduces the input capacitor RMS ripple current by a factor
of 30% to 70%.
I
I
= 2.2 • I , and
OUT
SAT
In continuous inductor conduction mode, the source cur-
rent of the top power MOSFET is approximately a square
= 1.6 • I
MAX
OUT
a reasonable output current limit would be
wave of duty cycle V /V . The maximum RMS capaci-
OUT IN
IOUT_OC_FAULT_LIMIT = 1.8 • I
tor current in this case is given by:
OUT
Once the value of L is known, the type of inductor must
be selected. High efficiency converters generally can-
not afford the core losses found in low-cost powdered
iron cores, forcing the use of more expensive ferrite
or molypermalloy cores. Also, core losses decrease as
inductance increases. Unfortunately, increased induc-
tance requires more turns of wire, larger inductance and
larger copper losses.
V
V – V
IN
OUT
(
)
OUT
I
� I
RMS OUT(MAX)
V
IN
This formula has a maximum at V = 2V , where
IN
OUT
I
= I /2
OUT
RMS
This simple worst-case condition is commonly used for
design because even significant deviations do not offer
much relief.
Ferrite designs have very low core loss and are preferred
at high switching frequencies. However, these core mate-
rials exhibit hard saturation, causing an abrupt reduc-
tion in the inductance when the peak current capability is
exceeded. Do not allow the core to saturate.
Note that manufacturer ripple current ratings for capaci-
tors are often based on only 2000 hours of life. This makes
it advisable to further derate the capacitor or to choose
a capacitor rated at a higher temperature than required.
Several capacitors may also be paralleled to meet size or
height requirements in the design. Always consult the
manufacturer if there is any question.
C SELECTION
IN
The input bypass capacitance for an LTC3888-1 power
circuit needs to have ESR low enough to keep the sup-
ply drop low as the top MOSFETs turn on, RMS current
capability adequate to withstand the ripple current at the
input, and a capacitance value large enough to maintain
the input voltage until the input supply can make up the
difference. Generally, a capacitor that meets the first two
requirements (particularly a non-ceramic type) will have
Ceramic, tantalum, semiconductor electrolyte (OS-CON),
hybrid conductive polymer (SUNCON) and switcher-rated
electrolytic capacitors can be used as input capacitors, but
each has drawbacks. Ceramics have high voltage coeffi-
cients of capacitance and may have audible piezoelectric
effects; tantalums need to be surge-rated; OS-CONs suf-
fer from higher inductance, larger case size and limited
Rev. 0
48
For more information www.analog.com
LTC3888-1
APPLICATIONS INFORMATION
surface mount applicability; and electrolytic capacitors
have higher ESR and can dry out. Sanyo OS-CON SVP(D)
series, Sanyo POSCAP TQC series, or Panasonic EE-FT
series aluminum electrolytic capacitors can be used in
parallel with high performance ceramic capacitors as
an effective means of achieving low ESR and high bulk
capacitance.
handling requirements of the application. Aluminum
electrolytic and dry tantalum capacitors are both avail-
able in surface mount configurations. New polymer sur-
face mount capacitors also offer very low ESR but have
much lower capacitive density. In the case of tantalum,
it is critical that the capacitors are surge tested for use
in switching power supplies. Several excellent output
capacitor choices include the Sanyo POSCAP TPD/E/F
series, the Kemet T520, T530 and A700 series, NEC/Tokin
NeoCapacitors and Panasonic SP series. Other suitable
capacitor types include Nichicon PL series and Sprague
595D series. Consult the manufacturer for other specific
recommendations.
In addition to PWM bulk input capacitance, a small
(0.01μF to 1μF) bypass capacitor between the chip V
IN
pin and ground, placed close to the LTC3888-1, is also
suggested. A small resistor placed between the bulk C
IN
and the V pin/bypass provides further isolation between
IN
rails. However, if the time constant of any such R-C net-
work on the V pin exceeds 30ns, dynamic line transient
IN
PROGRAMMABLE LOOP COMPENSATION
response can be adversely affected.
Because the LTC3888-1 uses an OTA error amplifier
architecture, Type II compensation is most commonly
applied for stabilizing the voltage control loop as shown
in Figure 25. The LTC3888-1 offers programmable loop
compensation to optimize the transient response without
C
SELECTION
OUT
The selection of C
required to minimize voltage ripple and load step tran-
sients. The output ripple ΔV
by:
is primarily determined by the ESR
OUT
is approximately bounded
OUT
requiring a hardware change. Internal error amplifier g
m
can be varied from 1mmho to 5.73 mmho, and internal
⎛
⎞
ꢈ
compensation resistor R can be varied from 1kΩ to
Δꢀ
≤ Δꢄ ꢆꢇR +
ITH
⎜
⎟
ꢅ
ꢁꢂꢃ
ꢉ ꢊ ꢋ
ꢊꢏ
ꢁꢂꢃ
⎝
⎠
62kΩ with the MFR_PWM_COMP command. A maximum
of two external capacitors are then required to stabilize
each voltage control loop.
ꢌꢍꢎ
where ΔI is the inductor ripple current.
L
⎛
⎜
⎝
⎞
⎟
⎠
ꢂ
ꢂ
ꢃꢄꢅ
ꢃꢄꢅ
Δꢀ =
ꢋꢌ
ꢁ
ꢁ ꢆ ꢇ
ꢂ
ꢀꢍ
ꢈꢉꢊ
ꢂ
Rꢃꢄ
ꢁ
ꢐ
ꢑ
Since ΔI increases with input voltage, the output ripple
L
voltage is highest at maximum input voltage. Typically
once the ESR requirement is satisfied, the capacitance is
adequate for filtering and has the necessary RMS current
rating.
ꢄꢅ
ꢀ
R
ꢏꢌꢍ
ꢏ
ꢏ
ꢌꢍ
ꢌꢍR
ꢆꢇꢇꢇꢈꢉ ꢄꢉꢊ
ꢋ
ꢋ
ꢌꢍꢎ
ꢌꢍ
Manufacturers such as Sanyo, Panasonic and Cornell
Dubilier should be considered for high performance
through-hole capacitors. The OS-CON semiconductor
electrolyte capacitor available from Sanyo has a good
(ESR)(size) product. Additional ceramic capacitors in par-
allel with polarized capacitors is recommended to offset
the effect of lead inductance.
Figure 25. Programmable Loop Compensation
By adjusting EA gm and RITH the LTC3888-1 can pro-
vide flexible Type II compensation for loop optimization
over a wide range of output capacitance. Adjusting gm
will change compensation gain over the entire frequency
range without adjusting any pole-zero locations as shown
in Figure 26.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the ESR or transient current
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APPLICATIONS INFORMATION
Adjusting RITH will change the pole-zero locations as
shown in Figure 27. LTpowerCAD is a freeware tool avail-
able from ADI suitable for determining optimum values
ꢔꢄꢅꢆꢉꢉꢉꢕꢇ
ꢀꢁꢂꢃꢄ
ꢋ
ꢂꢃꢄ
ꢐ
ꢏ
ꢋ
ꢋ
ꢌꢍꢎꢌꢍ
ꢐ
ꢏ
for g and R for the LTC3888-1.
m
ITH
ꢇꢓ
ꢌꢍꢎꢌꢍ
ꢅ
ꢆ
Internal R and external C combine to set the domi-
ꢆ
ITH
TH
nant pole-zero loop compensation. Adjust the value of
R
ꢇ
R
R
to optimize transient response after final PCB layout
ITH
ꢋ
ꢑꢒ
is complete and a particular CTH and output filter capacitor
have been selected. The types and values used for these
capacitors will strongly influence loop gain and phase.
R
ꢈ
ꢆꢉꢉꢉꢇ ꢊꢈꢉ
ꢒꢋꢓꢃ ꢀꢀ ꢂꢔꢕꢓꢃꢁꢅꢄꢒꢀꢔꢁ
ꢑꢄꢀꢁ
Figure 28. Remote Sense and Setting Output Voltage
Regulator loop stability can be checked by observing a
load transient response. Post-transient output voltage
settling is related to closed-loop stability and will dem-
onstrate actual overall supply performance. Switching
regulators can require several clock cyles to respond to
a direct step in DC load current due to the time required
for a voltage feedback error signal to develop. As the loop
responds and adjusts to remove the developing error sig-
ꢀꢁꢂRꢃꢄꢅꢃ ꢆ
ꢇ
ꢈRꢃꢉꢊꢃꢁꢂꢋ
ꢌꢍꢍꢍꢎꢏ ꢈꢏꢐ
nal, V
can be monitored for an over-damped, sluggish
OUT
Figure 26. Error AMP gm Adjust
response or excessive overshoot or ringing, which would
then indicate a stability problem.
ꢆꢋꢒꢃ ꢀꢀ ꢂꢓꢔꢒꢃꢁꢅꢄꢆꢀꢓꢁ
ꢑꢄꢀꢁ
The LTC3888-1 features flexible load step emulation
(PMBus MFR_LOAD_EMULATION command) to simu-
late calibrated output loads placed simultaneously on
all phases of the rail. It is not necessary to generate an
actual, high powered and regulated load step on the rail
output. This creates a V
response that is identical to
OUT
ꢀꢁꢂRꢃꢄꢅꢃ R
ꢀꢆꢇ
that of a physical output load step with C
ESR effects
OUT
removed from the initial step edge. This makes observa-
tion of V useful for loop evalution. In a predominantly
ꢈRꢃꢉꢊꢃꢁꢂꢋ
ꢌꢍꢍꢍꢎꢏ ꢈꢏꢐ
OUT
Figure 27. RITH Adjust
second-order system, phase margin and/or damping fac-
tor can be estimated using the percentage of overshoot
seen at the output. Bandwidth can also be estimated by
Occassionally, fine tuning of AC compensation to optimize
transient response may benefit from additional mid-band
phase recovery. In this case, another pole-zero pair can
be added to the feedback loop with a small capacitor or
R-C across the top resistor of the VOUT feedback network,
as shown in Figure 28. Often R3 is replaced with a short
when the error amplifer is an OTA, as is the case with
the LTC3888-1. Adding R3 provides additional AC gain
control, if needed. This allows total loop compensation
approaches similar to a Type III network.
the rise time of the V
waveform in this case.
OUT
A more severe load step case is created if unpowered
loads with large supply bypass capacitors (>1μF) are
cold-switched to the rail output for power. The discharged
bypass capacitors are effectively put in parallel wth C
,
OUT
causing a rapid drop in VOUT. No regulator can alter power
delvery quickly enough to prevent this sudden step change
in output voltage if the load switch resistance is low and
Rev. 0
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APPLICATIONS INFORMATION
driven on quickly. If the ratio of such a switched C
4. PCB traces for remote voltage sense should be run
together back to the LTC3888-1 in pairs with the small-
est spacing possible on any given layer on which they
are routed. Avoid high frequency switching signals
and ideally shield with ground planes. Locate any filter
component on these traces next to the LTC3888-1,
and not at the Kelvin sense location.
LOAD
to C
is greater than 1:50, the switch rise time should
OUT
be limited to approximately 25 • C
. As an example, a
LOAD
10μF switched load would require a 250μs rise time with
charging current limited to about 200mA.
PCB LAYOUT CONSIDERATIONS
5. PCB traces for output current sense (I
, IREF)
SENSE
To prevent magnetic and electrical field radiation, or high
frequency resonant problems, and to ensure correct IC
operation, proper layout of the components connected to
the LTC3888-1 is essential. Refer to Figure 29, which also
illustrates current waveforms typically present in the cir-
cuit branches. In this drawing SW0/1 and D0/1 respresent
salient features of the selected power stage. For maximum
efficiency, the switch node (input to L0/1) rise and fall
times should be minimized. The following PCB design
priority list will help ensure proper topology.
should avoid high frequency switching signals and
ideally be shielded with ground planes. Filter com-
ponents on these traces should return to GND (IC
paddle) and not to a local PGND.
6. Place low ESR output capacitors adjacent to the induc-
tor output and ground. Output capacitor ground con-
nections must feed into the same copper that con-
nects to the input capacitor ground before connecting
back to system ground.
1. Place a ground or DC voltage layer between a power
layer and a small-signal layer. Generally, power planes
should be placed on the top layer (4-layer PCB), or top
and bottom layer if more than 4 layers are used. Use
wide/short copper traces for power components and
avoid improper use of thermal relief around power
plane vias to minimize resistance and inductance.
7. Connection of switching ground to system ground,
small-signal analog ground or any internal ground
plane should be single-point. If the system has an
internal system ground plane, a good way to do this
is to cluster vias into a single star point to make the
connection. This cluster should be located directly
beneath the IC GND paddle, which serves as analog
signal ground. A useful CAD technique is to make
separate ground nets and use a 0Ω resistor to con-
nect them to system ground.
2. Low ESR input capacitors should be placed as close
as possible to the power stage FET supply and ground
connections with the shortest copper traces possible.
The power stage must be on the same layer of cop-
per as the input capacitors with a common topside
8. Place all small-signal components away from high
frequency switching nodes. Place decoupling capaci-
tors for the LTC3888-1 immediately adjacent to the IC.
power connection at C . Do not attempt to split the
IN
input decoupling for multiple phases, as a large reso-
nant loop can result. Vias should not be used to make
these connections. Avoid blocking forced air flow to
the power stages with large size passive components.
9. A good rule of thumb for via count in a given high cur-
rent path is to use 0.5A per via. Be consistent when
applying this rule.
10. Copper fills or pours are good for all power connec-
tions except as noted above in rule 3. Copper planes
on multiple layers can also be used in parallel. This
helps with thermal management and lowers trace
inductance, which further improves EMI performance.
3. Place the inductor input as close as possible to the
power stage. Minimize the surface area of the switch
node. Make the trace width the minimum needed to
support the maximum output current. Avoid copper
fills or pours. Avoid running the connection on mul-
tiple copper layers in parallel. Minimize capacitance
from the switch node to any other trace or plane.
Rev. 0
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LTC3888-1
APPLICATIONS INFORMATION
OUTPUT VOLTAGE SENSING
CLASSICAL ANALOG OUTPUT VOLTAGE CONTROL
The LTC3888-1 employs a classical analog approach for
setting output voltage when using default factory EEPROM
values. This control uses the circuit of Figure 28, where
external resistors R1 and R2 are used to set VOUT accord-
ing to the following equation.
Accurate Kelvin sensing techniques should be used
to connect the output voltage differentially back to the
LTC3888-1 V
pins of the master channel for best
SENSE
output voltage regulation at the point of load. These pins
also provide the ADC inputs for output voltage telemetry.
These connections are not strictly required for disabled
master channels (i.e. forced to be slave phases using bit
4 of MFR_PWM_MODE_LTC3888-1, with an external
V
=(R1+R2)/R2x400mV
OUT
In this mode, output margining is still possible using the
OPERATION command. The margining levels, along with
undervoltage and overvoltage supervisor fault thresholds,
are preset according to the following table. These values
are relative to the nominal output voltage created by R1
and R2.
I
connection). However, because the LTC3888-1 error
TH
amplifier is an OTA, it is sometimes advantageous to
wire-OR I pins and use multiple V sense points to
TH
OUT
provide improved power plane voltage averaging. Post-
manufacture selection of the most ideal load sense point
via final EEPROM programming is also possible. So in
general, sound Kelvin VOUT sensing techniques for all
LTC3888-1 master channels is recommended. Refer to
Figure 28.
ꢃꢄꢁ
ꢂꢁ
ꢀꢁ
ꢅ
ꢆꢇꢈꢁ
ꢉ
ꢆꢇꢈꢁ
R
ꢀꢁ
ꢅ
ꢊꢋ
R
ꢊꢋ
ꢉ
ꢊꢋ
ꢃꢄ0
ꢀ0
ꢅ
ꢆꢇꢈ0
ꢂ0
ꢉ
ꢆꢇꢈ0
R
ꢀ0
ꢌꢆꢀꢂ ꢀꢊꢋꢍꢃ ꢊꢋꢂꢊꢉꢎꢈꢍ
ꢏꢊꢐꢏ ꢃꢄꢊꢈꢉꢏꢊꢋꢐ
ꢉꢇRRꢍꢋꢈ. ꢑꢍꢍꢒ ꢀꢊꢋꢍꢃ
ꢈꢆ ꢎ ꢓꢊꢋꢊꢓꢇꢓ ꢀꢍꢋꢐꢈꢏ.
ꢔꢕꢕꢕꢁꢖ ꢗꢖꢘ
Figure 29. High Frequency Paths and Branch Current Waveforms
Rev. 0
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LTC3888-1
APPLICATIONS INFORMATION
Table 9. Factory EEPROM Output-Related Settings
4. Program VOUT_COMMAND to the value desired
(range of 300mV to 3.45V). See VOUT_MAX details
below for limitations on this value.
Quantity
UV Threshold
Margin Low
Margin High
OV Threshold
PMBus Command
VOUT_UV_FAULT_LIMIT −10%
VOUT_MARGIN_LOW
VOUT_MARGIN_HIGH
VOUT_OV_FAULT_LIMIT +10%
Value
5. Program related values for V
margins, warning
OUT
−5%
+5%
levels and hard supervisor thresholds (UV/OV) using
good practices for the bracketing of nominal VOUT with
these quantities.
Under and overvoltage warning limits are effectively dis-
abled by the default factory EEPROM settings. Several
other points should also be carefully noted when using
the LTC3888-1 default factory configuration.
6. Re-enabletheoutputusingRUNpinand/orOPERATION
command. V
servo can also be enabled before the
OUT
rail is turned on, or at any time afterward. See Using
Output Voltage Servo below for details.
1. In this mode VOUT_TRANSITION_RATE (in V/ms)
Once direct PMBus control of VOUT is established in this
way, VOUT_TRANSITION_RATE then applies to the output
applies to the V point, not V
Absolute slew rates
FB
OUT.
at V
will then be scaled by a factor of (R1+R2)/R2.
OUT
voltage proper, not V . Also, when using VOUT_SCALE_
FB
LOOP on the LTC3888-1, some restrictions apply.
2. In this mode, bit 6 of MFR_PWM_MODE_LTC3888-1
must be left clear, which is the factory default. V
OUT
1. VOUT_SCALE_LOOP cannot be changed on the fly.
The rail must be commanded off by RUN pin or
OPERATION command. Bits[6:5] of MFR_COMMON
should be polled whenever this command value is
written. A rail-off update time of up to 500ms may be
required. During this period, processing of any other
servo should not be used with these EEPROM set-
tings. Refer to PWM Control Loops in Electrical
Characteristics for device tolerances that apply to
VOUT accuracy in this case. Also refer to command
details for MFR_PWM_MODE_LTC3888-1. Proper use
of VOUT servo in full PMBus control context is covered
in the next few paragraphs.
V
-related commands sent to the LTC3888-1 will
OUT
be delayed until new VOUT_SCALE_LOOP calcuations
have completed. It is strongly recommended to set
this value just once after the desired value of (R1+R2)/
R2 is determined.
PMBUS OUTPUT VOLTAGE CONTROL
It is also possible to utilize the full range of digitally
programmable output voltage controls afforded by the
PMBUs interface once external components R1 and R2
have been chosen. The following steps should be taken
to properly enable this control mode on the LTC3888-1.
2. Sending VOUT-related commands to the LTC3888-1
or re-enabling the output before the device indicates
it has completed processing of VOUT_SCALE_LOOP
for that channel may result in erroroneous faults or
undesirable controller operation.
1. Disable the master (page) that will utilize full PMBus
control by using the RUN pin or OPERATION command.
3. VOUT_MAX is a read-only command that returns a
value based on VOUT_SCALE_LOOP, with a maximum
given by the read-only value of MFR_VOUT_MAX. This
calculated value sets the maximum output that can be
programmed with a particular R1/R2 combination for
2. Program VOUT_SCALE_LOOP to a value equal to
(R1+R2)/R2.
3. While internal calculations are performed to imple-
ment this change in output control mode, wait for
bits[6:5] of MFR_COMMON to both be clear. This may
take as much as 500ms.
nominal V
margin or fault. See command details
OUT,
for VOUT_MAX.
Rev. 0
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APPLICATIONS INFORMATION
USING OUTPUT VOLTAGE SERVO
VOUT_TRANSITION_RATE to minimize inrush currents
associated with the start-up voltage ramp. The maximum
rate at which the LTC3888-1 can move the output in this
fashion is 100µs/step. Soft-start is disabled by setting
VOUT_TRANSITION_RATE to 4V/ms. The LTC3888-1
will internally perform the math necessary to assure the
voltage ramp is controlled to the desired slope. However,
the voltage slope cannot be any faster than fundamental
limits imposed by the power stage. The larger VOUT_
TRANSITION_RATE becomes, the more noticeable an
output voltage stair-step may become.
For best output voltage accuracy, enable VOUT
servo mode on the master phase by setting bit 6 of
MFR_PWM_MODE_LTC3888-1 once PMBus output
control is fully programmed. In V
servo mode, the
OUT
LTC3888-1 will adjust the regulated output voltage based
on its related monitor ADC reading. Every time that output
voltage ADC channel is converted, the V
servo will
OUT
step the internal EA reference by 297.5μV until the output
produces the correct ADC reading.
In order for the LTC3888-1 to servo V , VOUT_SCALE_
LOOP must be used. This will allowOtUhTe final V
cre-
The LTC3888-1 also supports soft turn off in the same
manner it controls turn on. Soft-off is performed when
the RUN pin goes low or if the part is commanded off.
The LTC3888-1 can produce a controlled ramp off as long
as VOUT_TRANSITION_RATE is sufficiently slow to allow
the control loop and power stage to achieve the desired
slope. If VOUT_TRANSITION_RATE is too high to dis-
charge the load capacitance, the output will not reach 0V.
In this case, the power stage will still be commanded off
OUT
ated by the servo at any condition to have 0.2% typical
accuracy ( 0.5% absolute maximum). The raw output
created by the application must be within 5.5% of
VOUT_COMMAND for the V
servo to function to full
OUT
effectiveness, so external feedback resistors with 0.5%
tolerance are recommended.
When the master channel is turned on, VOUT servo is
enabled after all of the following conditions are satisfied.
at the end of soft-off and V
will decay at a rate deter-
OUT
mined by the load. The larger VOUT_TRANSITION_RATE
becomes, the more noticeable an output voltage stair-step
may become. If a rail faults off for any reason, all related
PWM phases are instantly commanded off. The output
will then decay as a function of load current.
• Bit 6 of MFR_PWM_MODE_LTC3888-1 Is Set
• The Soft-Start Sequence Is Complete
• A VOUT_UV_FAULT Is Not Present
• An IOUT_OC_FAULT Is Not Present
V
servo mode then engages after TON_MAX_ FAULT_
OUT
TIME-BASED OUTPUT SEQUENCING AND RAMPING
LIMIT has expired as shown in Figure 30, unless that limit
is set to 0s (infinite). In that case, the mode is engaged as
soon as the above conditions are satisfied.
The LTC3888-1 TON_DELAY and TOFF_DELAY commands
can be used in combination with VOUT_TRANSITION_
RATE to implement a wide range of versatile sequencing
and ramping schemes. The key to time-based sequencing
and ramping is the ability of LTC3888-1 master phases
to move their outputs up and down according to PMBus
command values as shown in Figure 30 and Figure 31.
SOFT-START AND STOP
The LTC3888-1 uses digital ramp control to create both
soft-start and soft-stop.
The LTC3888-1 must enter the run state prior to soft-start.
The RUN pins are released after the part initializes and V
is determined to be greater than the VIN_ON thresholdI.N
There is a fixed delay and other timing uncertainty associ-
ated with all changes in output voltage controlled by the
LTC3888-1. A nominal fixed timing delay of 270µs exists to
process any change in output voltage including soft-start/
stop and margining. The start of all time-based output
operations occur with an uncertainty of 50µs and have
a nominal step resolution of 100µs. This means the mini-
mum controlled time delay the LTC3888-1 can produce
Once in the run state, soft-start is performed after any
additional prescribed delay (see next section) by actively
regulating the load voltage while digitally ramping the
target voltage from 0V to the final expected value. Rise
time of the voltage ramp can be programmed using
Rev. 0
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APPLICATIONS INFORMATION
Rꢖꢊ
ꢔꢇꢄꢄꢀ
ꢋꢈRꢃꢄ ꢎꢄꢀꢈ
ꢈꢊꢁꢕꢅꢈꢀ
ꢐꢍꢊꢁꢅ ꢄꢖꢆꢔꢖꢆ
ꢃꢄꢅꢆꢁꢇꢈ Rꢈꢁꢂꢗꢈꢀ
ꢆꢄꢊꢘꢎꢁꢙꢘꢐꢁꢖꢅꢆꢘꢅꢍꢎꢍꢆ
ꢃꢄꢖꢆꢘꢖꢃꢘꢐꢁꢖꢅꢆꢘꢅꢍꢎꢍꢆ
ꢅ
ꢆꢇꢈ
ꢉ0.ꢊꢅꢋꢌꢍꢅꢎ
ꢀꢁꢂ ꢃꢄꢅꢆꢁꢇꢈ
ꢈRRꢄR ꢉꢊꢄꢆ
ꢆꢄ ꢋꢂꢁꢅꢈꢌ
ꢆꢍꢎꢈ ꢀꢈꢅꢁꢏ ꢄꢐ
ꢑꢒꢋꢓ ꢆꢏꢔꢍꢂꢁꢅ
Rꢇꢏ
ꢉꢊꢅꢋꢌꢍꢅꢎ
ꢃ
ꢄꢖꢆ
ꢀꢁꢁꢁꢂꢃ ꢄꢀꢃ
ꢃ00ꢐꢑꢋꢌꢍꢅ
ꢗꢏꢋꢆꢈRꢈꢋꢍꢋ
ꢉꢊꢄꢆ ꢆꢄ ꢋꢂꢁꢅꢈꢌ
Figure 32. Example of Fixed LTC3888-1 Processing Delay
and Soft-Start
ꢜꢝꢝꢝꢒꢞ ꢐꢜ0
ꢆꢍꢎꢈ
ꢋꢄꢐꢆꢚꢋꢆꢁRꢆ
ꢆꢄꢊꢘꢀꢈꢅꢁꢏ
ꢛ ꢃꢄꢖꢆꢘꢆRꢁꢊꢋꢍꢆꢍꢄꢊꢘRꢁꢆꢈ
Figure 30. Time-Based VOUT Turn-On with Servo
0.ꢏꢅꢌꢍꢎꢅ
ꢅꢆꢇꢈꢉ
ꢅꢆꢇꢈꢀ
ꢅꢆꢇꢈꢃ
ꢅꢆꢇꢈꢂ
Rꢇꢊ
ꢆ
ꢁꢇꢃ
ꢀꢁꢁꢁꢂꢃ ꢄꢀꢀ
ꢂ00ꢊꢋꢌꢍꢎꢅ
Figure 33. LTC3888-1 Time-Based Supply Sequencing
ꢑꢒꢒꢒꢓꢔ ꢂꢑꢓ
ꢃꢋꢐꢌ
ꢅ ꢆꢁꢇꢃꢈꢃRꢉꢊꢀꢋꢃꢋꢁꢊꢈRꢉꢃꢌ
ꢃꢁꢂꢂꢈꢍꢌꢎꢉꢏ
ꢀꢁꢂꢃꢄꢁꢂꢂ
Figure 31. Time-Based VOUT Turn-Off
will range from 220µs to 320µs, not including basic oscil-
lator tolerances. For software-based output changes (e.g.,
margining), this algorithmic delay begins when the STOP
bit is received on the serial bus. An example of this mini-
mum turn on/off delay and step-wise output control can
be seen in Figure 33, where TON_DELAY = 0s.
0.ꢏꢋꢈꢉꢊꢋ
ꢋꢌꢍꢎꢅ
ꢋꢌꢍꢎꢀ
ꢋꢌꢍꢎꢃ
ꢋꢌꢍꢎꢂ
ꢀꢁꢁꢁꢂꢃ ꢄꢀꢅ
To effectively implement tracking and sequencing between
rails controlled by ADI digital power products, two signals
should be shared between all controlling ICs: SHARE_CLK
and RUN (CONTROL pin on LTC297x products). This
facilitates synchronized rail sequencing on or off based
on shared input supply state (VIN_ON threshold), external
hardware control (RUN pin), or PMBus commands (pos-
sibly using global addressing).
ꢂ00ꢆꢇꢈꢉꢊꢋ
Figure 34. LTC3888-1 Time-Based Coincident Supply Ramping
0.ꢅꢋꢈꢉꢊꢋ
ꢋꢌꢍꢎꢏ
ꢋꢌꢍꢎꢀ
ꢋꢌꢍꢎꢃ
ꢋꢌꢍꢎꢂ
Figure 33 shows an example of output supply sequencing
using TON_DELAY.
Conventional coincident and ratiometric tracking can also
be emulated by setting equivalent turn-on/off delays and
appropriate rates as shown in Figure 34 and Figure 35.
ꢀꢁꢁꢁꢂꢃ ꢄꢀꢅ
ꢂ00ꢆꢇꢈꢉꢊꢋ
Figure 35. LTC3888-1 Time-Based Ratiometric Supply Ramping
Rev. 0
55
For more information www.analog.com
LTC3888-1
APPLICATIONS INFORMATION
In addition, these schemes can easily be mixed and
matched to create any necessary ramping controls, some
of which might prove difficult to implement with conven-
tional analog-only controllers. These programmable fea-
tures greatly simplify system development because rails
can be resequenced without a hardware change as final
product requirements evolve. The LTpowerPlay GUI and
LTC3888-1 onboard EEPROM can be used for this task,
avoiding the need for firmware development to modify
turn on/off relationships between rails. Entire power sys-
tems can easily be scaled up or down, facilitating reuse
of proven hardware macro designs.
Rꢋꢌ 0
Rꢋꢌ ꢊ
ꢆꢇꢈꢉ0
ꢆꢇꢈꢉꢊ
ꢍꢁꢎRꢁ
ꢀꢁꢂꢃꢄꢄꢅ
ꢓꢇꢋꢀꢀꢏꢋꢇ RꢔꢍꢈꢍꢁꢉRꢍ
ꢁꢉ ꢃ.ꢃꢕ ꢌꢉꢁ ꢍꢖꢉꢗꢌꢘ
Rꢋꢌ 0
Rꢋꢌ ꢊ
ꢇꢆꢉꢉꢒ0
ꢀꢁꢂꢃꢄꢄꢄꢏꢊ
ꢇꢆꢉꢉꢒꢊ
ꢁꢉ ꢌꢔꢙꢁ ꢂꢖꢎꢌꢌꢔꢀ
ꢈꢌ ꢁꢖꢔ ꢍꢔꢚꢋꢔꢌꢂꢔ
ꢃꢄꢄꢄꢊꢅ ꢐꢃꢑ
Figure 36. Cascade Sequencing Configuration Example
same order as they turn on, as shown in Figure 37. If a
different sequence is required, the circuit must be rewired
or delays must be added by programming TON_DELAY
or TOFF_DELAY. A fundamental limitation of this applica-
tion is the inability of upstream rails to detect a start-up
failure of downstream rails. Due to this, cascade sequenc-
ing should not be implemented without an external fast
supervisor to monitor downstream rails and assert a sys-
tem fault if problems occur.
VOLTAGE-BASED OUTPUT SEQUENCING
The LTC3888-1 is capable of voltage-based output
sequencing. For concatenated events between members
of the ADI PSM family, it is possible to control one RUN
pin from a GPIO, FAULT or PGOOD pin of a different con-
troller. A hardware configuration of the type shown in
Figure 36 disables the next downstream controller any-
time the upstream output is below the specific UV thresh-
old. If GPIO or FAULT is used, the controlling output must
be configured to only propagate VOUT_UV_UF, and that
IC must have its MFR_GPIO/FAULT_RESPONSE set to
0.ꢐꢋꢈꢉꢊꢋ
ꢋꢌꢍꢎꢏ
ꢋꢌꢍꢎꢀ
ꢋꢌꢍꢎꢃ
ꢋꢌꢍꢎꢂ
ignore (0x00). Use of the unfiltered V
UV fault limit is
OUT
recommended because there is less delay between cross-
ing the UV threshold and the GPIO/FAULT pin releasing.
When GPIO/FAULT UV propagation is utilized, an output
deglitching filter can ensure the control does not toggle
repeatedly at lower values of output transition due to
noise on VOUT. If unwanted transitions still occur with
only the internal filter found on most ADI PSM deviced
(typically 250μs), place a capacitor to ground on the out-
put pin. The RC time-constant of the filter should be low
enough to assure no appreciable delay is incurred. A value
of 300μs to 500μs will provide some additional filtering
without significant delay of the trigger event.
ꢀꢁꢁꢁꢂꢃ ꢄꢀꢅ
ꢂ00ꢆꢇꢈꢉꢊꢋ
Figure 37. Cascade Sequencing Waveforms
PWM FREQUENCY SYNCHRONIZATION
The LTC3888-1 incorporates an internal phase-locked
loop (PLL) which enables synchronization of all PWM
channels to an external CMOS clock from 250kHz to
1MHz. The PLL is locked to the falling edge of the SYNC
pin clock signal. For synchronization required by the
application, SYNC may be driven from a separate source,
including another LTC3888-1 or other ADI PSM device.
If SYNC is not externally clocked, the PWMs will operate
at the frequency specified by the FREQUENCY_SWITCH
command.
When the system is turned off, rails will shut down in the
same order as they turn on, as shown in Figure 37. If a
different sequence is required, the circuit must be rewired
or delays must be added by programming TON_DELAY or
TOFF_DELAY. A fundamental limitation of this application
When the system is turned off, rails will shut down in the
Rev. 0
56
For more information www.analog.com
LTC3888-1
APPLICATIONS INFORMATION
All ICs of a PolyPhase rail may be required to share SYNC
pins. If phase expansion for a single rail is all that is
required, the IC providing the master clock simply drives
the clock slave IC SYNC input with its CLKOUT. If SYNC is
shared between ADI PSM devices, only one device should
be programmed to control the SYNC output. Refer to the
following section for additional PolyPhase details.
As shown in Figure 38 master channel 0 and its assigned
slaves from the two ICs combine to form a single high
phase count rail with ideal phase separation, in this case
360/12 = 30 degrees. While a great deal of flexibility exists
in utilizing the remaining voltage control loops and slaves,
some phasing limitations do exist. For example, in a
10-phase case, the remaining three phases on each IC are
separated by 120 degrees, so a 2-phase rail built from one
of those loops would not be capable of 180° phasing. The
two remaining loops would also not produce uniform 60°
separation if combined into a single 6-phase rail. While
none of the phases on these remaining two 3-phase loops
overlap each other, one or more may overlap those of the
primary high count rail.
The PLL generates very accurate channel phase relation-
ships which can be selected with MFR_PWM_CONFIG_
LTC3888-1. For PolyPhase applications, all phases should
be spaced evenly around the unit circle for best results.
For instance, a 4-phase system should use a separation
of 90° between channels.
The PLL has a lock detection circuit. If the PLL should
lose lock during operation, bit 4 of the STATUS_MFR_
SPECIFIC command is asserted and the ALERT pin is
pulled low, if not masked. The fault can be cleared by
writing a 1 to STATUS_MFR_SPECIFIC bit 4.
Whether using the phase expansion feature of the
LTC3888-1 or not, the following pins should be shared
between two or more devices devices on a large PolyPhase
rail:
• V (if separatre ICs)
IN
• VSENSE (see previous Output Voltage Sensing
discussion)
POLYPHASE OPERATION AND LOAD SHARING
Single IC PolyPhase LTC3888-1 configuration are con-
trolled by bits [2:0] of MFR_PWM_CONFIG_LTC3888-1.
All necessary slave phase control is managed internal to
the device in this case. When operating a high power rail
requires between ten and sixteen phases, the LTC3888-1
affords dual-IC phase expansion to keep those phases ide-
ally spaced around the unit circle as shown in Figure 38.
To do this, bit 3 of MFR_PWM_CONFIG_LTC3888-1 is
set, making that device the clock master. The PGOOD0
pin is redefined to provide CLKOUT to drive the SYNC
input of the second LTC3888-1. A pull-up resistor to 3.3V
is still required on CLKOUT. Bits[2:0] of MFR_PWM_
CONFIG_LTC3888-1 are then set to the same value on
both ICs, yielding the following additional dual-IC rail
configurations:
• I / I
TH THR
• TSNS/VDR_MON
• SYNC (if not using phase expansion)
2
• I C bus pins (SCL, SDA)
• ALERT
• FAULT pins
• RUN
• SHARE_CLK (if separate ICs)
When ITH pins are shorted, one ITHR pin can be selected to
apply primary loop compensation, with all other ITHR pins
shorted to the common I . Alternatively, all I
pins can
be shorted, making theTeHffective resistanceTtHhRe parallel
combination of all these R . This will reduce dynamic
ITH
• 10+(1 or 3)+(1 or 3)
• 12+(1 or 2)+(1 or 2)
• 14+1+1
range of R but will increase programming resolution.
ITH
Linear regulator outputs such as V
and resistor config-
uration pins, including R , shoulDdDn3o3t be shared between
SET
devices. PGOOD may be shared between all master chan-
nels on a single rail, or a single PGOOD output can be
selected to indicate the rail output voltage is in regulation.
• 16-phase
Rev. 0
57
For more information www.analog.com
LTC3888-1
APPLICATIONS INFORMATION
ꢇꢛꢗꢂꢜꢝ
ꢃꢔꢇꢓꢕꢊꢖ ꢅ
ꢙꢄꢉR ꢅ
ꢅ
ꢆꢆꢀꢀ
ꢉꢐꢑꢂ
ꢃꢠ
ꢃ0ꢠ
ꢅ
ꢚ
ꢊꢖꢌꢊꢖꢂ
ꢉꢐꢑꢂ
ꢎꢑꢍꢀꢁꢁꢁꢔꢂ
ꢙꢄꢉR ꢅ
ꢚ
ꢇꢈꢉꢉꢆꢂ
ꢊꢋꢌꢍ
ꢉꢐꢑꢂ
ꢅ
ꢙꢄꢉR ꢅ
ꢚ
ꢊꢖꢌꢊꢖ0
ꢉꢐꢑꢃ
ꢍꢎꢏꢉꢐꢑ
ꢇꢛꢗ0ꢜꢃꢔꢞ
ꢂꢃꢔꢇꢓꢕꢊꢖ ꢅ
ꢉꢐꢑꢃ
ꢒ
ꢑꢓ0
ꢂꢃꢔꢇꢓꢕꢊꢖ ꢍꢎꢉꢍꢏ ꢗꢕꢊꢑꢖR
ꢒ
ꢑꢓ0
ꢟꢇꢛꢗ0ꢜꢃꢔꢞ
ꢊꢋꢌꢍ
ꢅ
ꢙꢄꢉR ꢅ
ꢙꢄꢉR ꢅ
ꢚ
ꢊꢖꢌꢊꢖ0
ꢉꢐꢑꢃ
ꢙꢄꢉR ꢅ
ꢙꢄꢉR ꢅ
ꢚ
ꢚ
ꢇꢈꢉꢉꢆ0
ꢇꢈꢉꢉꢆꢂ
ꢉꢐꢑꢃ
ꢎꢑꢍꢀꢁꢁꢁꢔꢂ
ꢉꢐꢑꢀ
ꢅ
ꢚ
ꢊꢖꢌꢊꢖꢂ
ꢉꢐꢑꢀ
ꢃꢠ
ꢃ0ꢠ
ꢃ0ꢠ
ꢇꢛꢗꢂꢜꢝ
ꢃꢔꢇꢓꢕꢊꢖ ꢅ
ꢉꢐꢑꢀ
ꢅ
ꢆꢆꢀꢀ
ꢂꢃꢔꢇꢓꢕꢊꢖ ꢍꢎꢉꢍꢏ ꢊꢎꢕꢅꢖ
ꢌꢉꢑꢖꢘ ꢊꢉꢗꢖ ꢆꢖꢑꢕꢒꢎꢊ ꢉꢗꢒꢑꢑꢖꢆ ꢄꢉR ꢍꢎꢕRꢒꢑꢋ
ꢀꢁꢁꢁꢂꢃ ꢄꢀꢁ
Figure 38. Simplified Schematic Showing 12 + 2 + 2 Phase Expansion
At any point that additional output current is required
without the need for additional phase separation, it is
always possible to simply add overlapping phases on
an LTC3888-1 rail. For example, two LTC3888-1s can
be combined to provide two 5-phase rails with a third
6-phase rail with two PWMs driving each phase. In this
case, SYNC would be shared between the ICs (one con-
figured as clock master) and all rails would have phases
with the desired uniform spacing around the unit circle.
Refer to Figure 39.
ꢈꢝꢕ0ꢞꢃꢓꢘ
ꢘꢓꢈꢑꢖꢋꢗ ꢆ
ꢚꢄꢊR ꢆ
ꢆ
ꢇꢇꢀꢀ
ꢊꢙꢐꢂ
ꢃꢡ
ꢃ0ꢡ
ꢆ
ꢛ
ꢋꢗꢍꢋꢗ0
ꢊꢙꢐꢂ
ꢒꢐꢎꢀꢁꢁꢁꢓꢂ
ꢚꢄꢊR ꢆ
ꢊꢙꢐꢂ
ꢛ
ꢈꢉꢊꢊꢇ0
ꢋꢌꢍꢎ
ꢆ
ꢚꢄꢊR ꢆ
ꢛ
ꢋꢗꢍꢋꢗꢂ
ꢊꢙꢐꢃ
ꢈꢉꢊꢊꢇꢂ
ꢈꢝꢕꢂꢞꢜꢞꢟ
ꢜꢓꢈꢑꢖꢋꢗ ꢆ
ꢊꢙꢐꢃ
ꢚꢑꢏꢉꢑ ꢊꢙꢐꢈꢙꢐꢛ
ꢏ
ꢐꢑꢂ
ꢎꢒꢊꢎꢔ ꢕꢖꢋꢐꢗR
ꢏ
ꢐꢑꢂ
ꢠꢈꢝꢕꢂꢞꢜꢞꢟ
ꢋꢌꢍꢎ
ꢆ
ꢚꢄꢊR ꢆ
ꢚꢄꢊR ꢆ
ꢛ
ꢋꢗꢍꢋꢗꢂ
ꢊꢙꢐꢃ
ꢚꢄꢊR ꢆ
ꢚꢄꢊR ꢆ
ꢛ
ꢛ
ꢈꢉꢊꢊꢇꢂ
ꢈꢉꢊꢊꢇ0
ꢊꢙꢐꢃ
ꢒꢐꢎꢀꢁꢁꢁꢓꢂ
ꢊꢙꢐꢀ
ꢆ
ꢛ
ꢋꢗꢍꢋꢗ0
ꢊꢙꢐꢀ
ꢃ0ꢡ
ꢃ0ꢡ
ꢈꢝꢕ0ꢞꢃꢓꢘ
ꢘꢓꢈꢑꢖꢋꢗ ꢆ
ꢊꢙꢐꢀ
ꢆ
ꢇꢇꢀꢀ
ꢀꢁꢁꢁꢂꢃ ꢄꢀꢅ
ꢍꢊꢐꢗꢢ ꢋꢊꢕꢗ ꢇꢗꢐꢖꢏꢒꢋ ꢊꢕꢏꢐꢐꢗꢇ ꢄꢊR ꢎꢒꢖRꢏꢐꢌ
Figure 39. Simplified Schematic Showing 5+5+6 Application
Rev. 0
58
For more information www.analog.com
LTC3888-1
APPLICATIONS INFORMATION
Load sharing accuracy is based on the power stage out-
put current monitor interface of each slave phase. The
gain matching errors of these channels tend to be small
and negligible. The input-referred offset of the LTC3888-1
current interface is trimmed at the factory but will still
dominate the sharing error budget, especially at lower
phase current levels. Specifications for on-chip and off-
chip output current matching are given in the Electrical
Characteristics table. These specifications do not include
the current error created by mismatch of the output cur-
rent monitors of the individual power stages.
The worst-case RMS ripple current for a single stage
design peaks at an input voltage of twice the output volt-
age. The worst case RMS ripple current for a 2-phase
design peaks at output voltages of one-quarter and three-
quarters of the input voltage. When the RMS current is
calculated, higher effective duty factor results and the
peak current levels are divided as long as the current in
each stage is balanced. Refer to Application Note 19 for a
detailed description of how to calculate RMS current for a
single stage switching regulator. Figure 41 and Figure 42
illustrate how the input and output currents are reduced
by using an additional phase. For a 2-phase converter,
the input current peaks drop in half and the frequency is
doubled. The input capacitor requirement is then theoreti-
cally reduced by a factor of four.
Every master channel on a rail should use identical values
for all PMBus commands related to output voltage control
(including margin and start/stop timing), input and output
warning limits (both voltage and current), all fault limits
and associated responses, and all PWM configuration
controls. The correct current sense gain should also be
set for each master (IOUT_CAL_GAIN) to achieve accu-
0.ꢇ
ꢀꢜꢗꢝꢌꢖꢙ
0.ꢆ
rate I
telemetry and consistent fault handling across
OUT
phases.
0.ꢃ
0.ꢂ
A PolyPhase power supply significantly reduces the
amount of ripple current in both the input and output
capacitors. The RMS input ripple current is divided by,
and the effective ripple frequency is multiplied by, the
number of phases used as long as the input voltage is
greater than the number of phases times the output volt-
age. Output voltage ripple amplitude is also reduced by
the number of phases used. Figure 40 graphically illus-
trates the principle.
ꢁꢜꢗꢝꢌꢖꢙ
0.ꢁ
0.ꢀ
0
0.ꢀ
0.ꢆ
0.ꢚ 0.ꢄ
0.ꢁ 0.ꢂ 0.ꢃ
0.ꢇ
0.ꢛ
ꢈꢉꢊꢋ ꢅꢌꢍꢊꢎR ꢏꢐ ꢑꢐ
ꢔ
ꢎꢉꢊ ꢒꢓ
ꢂꢄꢄꢄꢀꢁ ꢅꢃꢀ
Figure 41. Normalized RMS Input Ripple Current
ꢎ.0
0.ꢒ
ꢆꢉꢋꢏꢐꢑ ꢒꢓꢔꢆꢑ
ꢕꢍꢔꢐ ꢒꢓꢔꢆꢑ
0.ꢓ
ꢎꢐꢏꢚꢅꢛꢜ
0.ꢔ
ꢆꢇꢂ ꢈ
ꢆꢇꢂ ꢈ
ꢆꢇꢃ ꢈ
0.ꢕ
0.ꢖ
0.ꢗ
0.ꢘ
ꢉ
ꢊꢉꢋ
ꢉ
ꢉ
ꢐꢂ
ꢐꢃ
ꢉ
ꢊꢌꢍꢎ
ꢙꢐꢏꢚꢅꢛꢜ
0.ꢙ
ꢉ
ꢊꢉꢋ
0.ꢎ
0
ꢉ
ꢊꢌꢍꢎ
ꢀꢁꢁꢁꢂꢃ ꢄꢅ0
0.ꢎ
0.ꢖ
0.ꢔ 0.ꢓ
0.ꢙ 0.ꢘ 0.ꢗ
0.ꢕ
0.ꢒ
Rꢉꢒꢒꢐꢑ
ꢀꢁꢂꢃ ꢄꢅꢆꢂꢇR ꢈꢉ ꢊꢉ
ꢍ
ꢇꢁꢂ ꢋꢌ
ꢘꢓꢓꢓꢎꢙ ꢄꢗꢙ
Figure 40. Single and 2-Phase Current Waveforms
Figure 42. Normalized Output Ripple Current
Rev. 0
59
For more information www.analog.com
LTC3888-1
APPLICATIONS INFORMATION
RESISTOR CONFIGURATION PINS
Any of the single-IC master/slave configurations that the
LTC3888-1 supports can be programmed with PWM_CFG
using one of two frequencies as shown in Table 11. Phase
expansion is not supported when using an external resis-
tor to set master/slave configuration.
As a factory default, the LTC3888-1 is programmed to
use external resistor configuration, allowing output cur-
rent limit, PWM frequency and phasing, and the PMBus
address to be set without programming the part through
its serial interface or purchasing devices with custom
EEPROM contents. An 18.7kΩ resistor with a tolerance
Table 11. PWM_CFG Resistor Programming
MFR_PWM_CONFIG_LTC3888-1[3:0] SWITCHING
FREQUENCY
of 1% or better must be wired between the R pin and
SET
BINARY
MASTER/SLAVE
R
(kΩ)
(kHz)
GND. This component establishes the correct bias level
for the remaining RCONFIG pins, which are programmed
with a resistor to GND. The RCONFIG pins are only inter-
rogated at initial power up and during a reset, so modify-
ing their values on the fly is not recommended. RCONFIG
pins on the same IC can share a single resistor if they
require identical programming. Resistors with a tolerance
of 1% or better must be used to assure proper operation.
Noisy clock signals should not be routed near these pins.
CONFIG
OPEN
from EEPROM
7 + 1
11.8
10.2
9.31
8.66
7.87
7.15
6.49
5.9
0111
0110
0101
0100
0011
0010
0001
0000
0111
0110
0101
0100
0011
0010
0001
0000
6 + 2
6 + 1
5 + 3
550
4 + 4 (or 8-phase)
4 + 3
4 + 2
3 + 3
Output current limit can be set as shown in Table 10. For
example, setting this resistor to 4.42kΩ is equivalent to
programming a IOUT_OC_WARN_LIMIT value of 32A
with IOUT_OC_FAULT_LIMIT set to 40A.
5.11
4.42
3.74
3.09
2.43
1.74
1.02
GND
7 + 1
6 + 2
6 + 1
5 + 3
450
Table 10. Resistor Programming of OC Warning and Fault Limits
4 + 4 (or 8-phase)
4 + 3
R
(kΩ) IOUT_OC_WARN_LIMIT (A) IOUT_OC_FAULT_LIMIT (A)
CONFIG
OPEN
from EEPROM
from EEPROM
4 + 2
11.8
10.2
9.31
8.66
7.87
7.15
6.49
5.9
68
64
60
56
52
48
44
40
36
32
28
24
20
16
12
8
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
3 + 3
The LTC3888-1 address is selected based on the pro-
gramming of the two configuration pins ASEL0 and
ASEL1 according to Table 12. ASEL0 programs the bot-
tom four bits of the device address for the LTC3888-1,
and ASEL1 programs the three most-significant bits.
Either portion of the address can also be retrieved from
the MFR_ADDRESS value in EEPROM. If both pins are
left open, the full 7-bit MFR_ADDRESS value stored in
EEPROM is used to determine the device address. It is
recommended that each LTC3888-1 in a system have a
unique address, and the ASEL pins provide an efficient
way to accomplish this without a plethora of custom
EEPPOM programming. The LTC3888-1 also responds
to 7-bit global addresses 0x5A and 0x5B. MFR_ADDRESS
and MFR_RAIL_ADDRESS should not be set to either of
these values.
5.11
4.42
3.74
3.09
2.43
1.74
1.02
GND
Rev. 0
60
For more information www.analog.com
LTC3888-1
APPLICATIONS INFORMATION
Table 12. Resistor Programming of MFR_ADDRESS
ASEL1
ASEL0
DEVICE ADDRESS BITS[3:0]
R
(kΩ)
DEVICE ADDRESS BITS[6:4]
HEX
CONFIG
BINARY
BINARY
from EEPROM
HEX
OPEN
from EEPROM
11.8
10.2
9.31
8.66
7.87
7.15
6.49
5.9
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
5.11
4.42
3.74
3.09
2.43
1.74
1.02
GND
0111
0110
0101
0100
0011
0010
0001
0000
7
6
5
4
3
2
1
0
GND with a low ESR X5R or X7R ceramic capacitor with
a value of 1μF or greater.
INTERNAL REGULATOR OUTPUTS
The INTV pin provides supply current for much of the
CC
Do not draw any external system current from these LDO
supplies beyond that required for specific LTC3888-1
configuration or load/pull-up resistors.
internal LTC3888-1 analog circuitry at a nominal value of
5.2V. The LTC3888-1 features an internal linear regulator
that can be used to supply 5.2V to INTV from the pri-
CC
mary V supply. At lower supply voltages, the LTC3888-1
IN
will also accept an external 5V supply attached to this pin
IC JUNCTION TEMPERATURE
if V and INTV are shorted. If the internal 5.2V LDO
IN
CC
The user must ensure that the maximum rated junction
temperature is not exceeded under all operating condi-
tions. The thermal resistance of the LTC3888-1 package
is used, INTVCC must be bypassed to GND with a low
ESR X5R or X7R ceramic capacitor with a value between
1µF and 4.7μF. If an external 5V source supplies V and
INTVCC, a local low ESR bypass capacitor with aINvalue
between 0.01μF and 0.1μF should be placed directly
between the shorted power pins and GND.
(θ ) is 36°C/W, provided the exposed pad is in good ther-
JA
mal contact with the PCB. The actual thermal resistance
in the application will depend on forced air cooling and
other heat sinking means, especially the amount of cop-
per on the PCB to which the LTC3888-1 is attached. The
following formula may be used to estimate the maximum
INTV powers secondary internal 3.3V and 2.5V LDOs
CC
whose outputs are present on V
and V
, respec-
DD25
DD33
tively. The 3.3V supply provides power for internal aux-
illary circuits, and the 2.5V supply provides power for
much of the internal processor logic on the LTC3888-1.
Both of these LDO outputs should be bypassed directly to
average power dissipation P (in watts) of the LTC3888-1.
D
P = V (.03 + I + I )
RC25
D
IN
EXT
Rev. 0
61
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LTC3888-1
APPLICATIONS INFORMATION
where:
⎡
⎢
⎣
⎤
⎥
⎦
⎛
⎜
⎝
ꢂ.ꢃ
⎞
⎟
⎠
ꢂ
ꢂ
⎛
ꢇ⎜
⎝
⎞
⎟
⎠
−
ꢈꢉ
ꢊꢋꢄ ꢃ0ꢊ
ꢄ.ꢅꢂꢆꢇꢂ0
I
= total external load drawn from V
, including
DD33
EXT
ꢀꢁ = e
= ꢂ.ꢅꢅ
local pull-up resistors, in amps
indicating the effect is the same as operating the device at
125°C for 10 • 1.66 = 16.6 hours, resulting in a retention
derating of 6.6 hours.
IRC25 = total current drawn from VDD25 by LTC3888-1
configuration resistors, in amps
and f
is the PWM switching frequency in kHz
PWM
The maximum junction temperature of the LTC3888-1 in
°C may then be found from the following equation
CONFIGURING OPEN-DRAIN PINS
The LTC3888-1 has the following open-drain pins:
T = T + 36 • P
D
J
A
• 3.3V Pins
with ambient temperature T expressed in °C
A
1. PGOOD0/CLKOUT
2. PGOOD1
DERATING EEPROM RETENTION AT TEMPERATURE
3. FAULT0, FAULT1
EEPROM read operations between 85°C and 125°C will
not affect data storage. But retention will be degraded if
the EEPROM is written above 85°C or stored or oper-
ated above 125°C. If an occasional fault log is generated
above 85°C, the slight reduction in data retention in the
EEPROM fault log area will not affect the use of the func-
tion or other EEPROM storage. See the Operation section
for other high temperature EEPROM functional details.
Degradation in data retention can be approximated by
calculating the dimensionless acceleration factor using
the following equation.
4. SYNC
5. SHARE_CLK
• 5V Capable Pins
(These pins operate correctly when pulled to 3.3V.)
1. RUN0, RUN1
2. ALERT
3. SCL
4. SDA
⎡
⎤
⎛
⎞ ⎛
⎞
ꢂꢃ
ꢄ
ꢆ
ꢆ
ꢅ
−
⎢⎜ ⎟ ⎜
⎟ ⎥
ꢇ
+ꢊꢋꢌ
ꢇ
+ꢊꢋꢌ
⎝
⎠ ⎝
⎠
⎥
⎦
Most of the above pins have on-chip pull-down transis-
tors that can sink 3mA at 0.4V. The low state threshold
on these pins provides ample noise margin with 3mA of
current. For 3.3V pins, 3mA of current is produced by
a 1.1k pull-up resistor. Unless there are transient speed
issues associated with the RC time constant of the net, a
10k resistor or larger is generally recommended.
⎢
⎣
ꢈꢉꢂ
ꢉꢇRꢂꢉꢉ
ꢀꢁ = e
Where:
AF = acceleration factor
Ea = activation energy = 1.4eV
–5
k = 8.617 • 10 eV/°K
The pull-up resistor for PGOOD should be terminated
to the LTC3888-1 VDD33 pin or a separate bias supply
under 3.6V that is up before the LTC3888-1 is enabled.
Otherwise, power-not-good may be falsely indicated after
the PWM outputs are running.
T
T
= is the specified junction temperature
USE
= actual junction temperature in °C
STRESS
As an example, if the device is stored at 130°C for 10
hours,
For high speed signals such as SDA and SCL, a lower
value resistor may be required. The RC time constant
should be set to one-third to one-fifth the required rise
T
= 130°C, and
STRESS
time to avoid timing issues. For a 100pF load and a 400kHz
Rev. 0
62
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LTC3888-1
APPLICATIONS INFORMATION
PMBus communication rate, the resistor pull-up on the
SDA and SCL pins with the time constant set to one-third
the required rise time equals
PMBUS COMMUNICATION AND COMMAND
PROCESSING
The LTC3888-1 has a one deep buffer to hold the last data
written for each supported command prior to processing,
as shown in Figure 43. Two distinct parallel sections of the
LTC3888-1 manage command buffering and command
processing to ensure the last data written to any com-
mand is never lost. When the part receives a new com-
mand from the bus, command data buffering copies the
data into the write command data buffer and indicates to
the internal processor that data for that command should
be handled. The internal processor runs in parallel and
performs the sometimes slower task of fetching, convert-
ing (to internal format) and executing commands marked
for processing.
t
RISE
R
=
= 1kΩ
PULLUP
3 •100pF
The closest 1% resistor value is 1kΩ. Limit to 1.1kΩ for
best noise margin.
Be careful to minimize parasitic capacitance on the SDA
and SCL lines to avoid communication problems. To esti-
mate the loading capacitance, monitor the signal in ques-
tion and measure how long it takes for the desired signal
to reach approximately 63% of the output value. This is
one time constant.
Some computationally intensive commands (e.g., timing
parameters, temperatures, voltages and currents) have
internal processor execution times that may be long rela-
tive to PMBus timing. If the part is busy processing a
command, and a new command(s) arrives, execution may
be delayed or processed in a different order than received.
The part indicates when internal calculations are in pro-
cess with bit 5 of MFR_COMMON (Internal Calculations
Not Pending). When the internal processor is busy cal-
culating, bit 5 is cleared. When this bit is set, the part is
ready for another command. An example polling loop is
provided in Figure 44, which ensures that commands are
processed in order while simplifying error handling rou-
tines. MFR_COMMON always returns valid data at PMBus
speeds between 10kHz and 400kHz.
The SYNC pin has an on-chip pull-down transistor with
the output held low for nominally 500ns when driven by
the LTC3888-1. If the internal oscillator is set for 500kHz
and the load is 100pF with a one-third rise time required,
the resistor calculation is as follows:
2µs – 500ns
R
=
= 5.0kΩ
PULLUP
3 •100pF
The closest 1% resistor is 4.99kΩ .
If timing errors are occurring or if the SYNC amplitude is not
as large as required, monitor the waveform and determine
if the RC time constant is too long for the application. If
possible reduce the parasitic capacitance. Otherwise reduce
the pull-up resistor sufficiently to assure proper operation.
When the part receives a new command while it is busy,
it will communicate this condition using standard PMBus
protocol. Depending on device configuration and state it
may either NACK the command or return all ones (0xFF)
for reads. It may also generate a BUSY fault and ALERT
notification, or stretch the SCL clock low. For more infor-
mation refer to PMBus Specification V1.2, Part II, Section
10.8.7 and SMBus V2.0 section 4.3.3. Clock stretching
can be enabled by asserting bit 1 of MFR_CONFIG_ALL.
Clock stretching will only occur if enabled and the bus
communication speed exceeds 100kHz.
Similar results (R < 5kΩ) should be applied to the
PGOOD0 output when configured as CLKOUT to ensure
proper clocking of the slave IC.
The SHARE_CLK output has a nominal period of 10μs
and is pulled low for about 1μs. If the system load on this
shared line is 100pF, the resistor calculation for this line
with a one-third rise time is:
9µs
R
=
= 30kΩ
PULLUP
3 •100pF
PMBus protocols for busy devices are well accepted
standards but can make writing system level software
The closest 1% resistor is 30.1kΩ .
Rev. 0
63
For more information www.analog.com
LTC3888-1
APPLICATIONS INFORMATION
somewhat complex. The part provides three handshaking
status bits which reduce this complexity while enabling
robust system level communication. The three hand
shaking status bits are in the MFR_COMMON register.
When the part is busy executing an internal operation,
it will clear bit 6 of MFR_COMMON (Chip Not BUSY).
When internal calculations are in process, the part will
clear bit 5 of MFR_COMMON (Internal Calculations Not
Pending). When the part is busy specifically because it
of 100kHz, it is strongly recommended that the part be
enabled to use clock stretching, requiring a PMBus mas-
ter that supports that function. Clock stretching does not
allow the LTC3888-1 to communicate reliably on busses
operating above 400kHz. Operating the LTC3888-1 with
PMBus SCL rates above 400kHz is not recommended.
System software that detects and properly recovers from
the standard PMBus NACK responses or BUSY faults
described in PMBus Specification V1.2, Part II, Section
10.8.7 is required to communicate above 100kHz without
clock stretching.
is transitioning V
(margining or on/off) it will clear bit
OUT
4 of MFR_COMMON (Output Not In Transition). These
three status bits can be polled with a PMBus read byte
of the MFR_COMMON register until all three bits are set.
A command immediately following all these status bits
being set will be accepted without a NACK, BUSY fault
or ALERT notification. The part can NACK commands for
Refer to Application Note 135 for techniques that may also
apply to implement a robust PMBus interface to the LTC3888-1.
STATUS AND FAULT LOG MANAGEMENT
Due to internal operation, very infrequently the LS byte
of STATUS_WORD may be inconsistent with the state
of bits in the MS byte. This condition is quite transient
and can normally be resolved by simply re-reading
STATUS_WORD.
ꢂꢄꢀ
ꢌRꢅꢇꢁ ꢂꢃꢄꢄꢈꢆꢀ
ꢀꢈꢇꢈ ꢍꢎꢏꢏꢁR
ꢊꢄꢍꢚꢛ
ꢌRꢅꢇꢁ
ꢀꢁꢂꢃꢀꢁR
ꢅꢆꢇꢁRꢆꢈꢉ
ꢊꢈꢐꢁ
0ꢑ00
ꢊRꢃꢂꢁꢋꢋꢃR
ꢗ
ꢗ
ꢗ
ꢂꢄꢀꢋ
ꢏꢁꢇꢂꢜꢝ
ꢂꢃꢆꢙꢁRꢇ
ꢀꢈꢇꢈ
ꢈꢆꢀ
ꢁꢞꢁꢂꢎꢇꢁ
ꢀꢈꢇꢈ
ꢄꢎꢞ
ꢙꢃꢎꢇꢘꢂꢃꢄꢄꢈꢆꢀ 0ꢑꢒꢓ
If power is lost during an internal store of a fault log to
EEPROM, a partial write of the log can result. In this situ-
ation, the LTC3888-1 will indicate that a partial fault log is
present the next time adequate supply voltage is applied
by setting bit 3 of STATUS_MFR_SPECIFIC and bit 4 of
STATUS_CML. Additional logging remains disabled. The
only way to then determine how much of the log is actu-
ally valid is by subjective evaluation of the contents of
ꢗ
ꢗ
ꢗ
0ꢑꢏꢀ
ꢄꢏRꢘRꢁꢋꢁꢇ
ꢑꢓ
ꢋ
R
ꢂꢈꢉꢂꢎꢉꢈꢇꢅꢃꢆꢋ
ꢊꢁꢆꢀꢅꢆꢐ
ꢔꢕꢕꢕꢓꢒ ꢏꢖꢔ
Figure 43. Write Command Data Processing
other reasons, however, as required by the PMBus speci-
fication (e.g., an invalid command or data).
each log event record. MFR_FAULT_LOG_CLEAR will per
-
manently erase a partial fault log, allowing a subsequent
log to be written. It is a good practice to always check for
a partial fault log at power-up if fault logging is enabled
(bit 7 of MFR_CONFIG_ALL).
An example of a robust command write algorithm for the
VOUT_COMMAND register is provided in Figure 44. It is
recommended that all command writes be preceded with
such a polling loop to avoid the extra complexity of deal-
ing with busy behavior or unwanted ALERT notifications.
A simple way to achieve this is to embed the polling in
subroutines to write command bytes and words. This poll-
ing mechanism will allow system software to remain clean
and simple while robustly communicating with the part.
Refer to Fault Log Details in the Operation section for
more details.
LTPOWERPLAY – AN INTERACTIVE DIGITAL POWER GUI
LTpowerPlay is a powerful Windows-based development
environment that supports Analog Devices Power System
Management ICs, including the LTC3888-1. LTpowerPlay
can be used to evaluate ADI products by connecting to
When communicating using bus speeds at or below
100kHz, the polling mechanism previously shown pro-
vides a simple solution that ensures robust communica-
tion without clock stretching. At bus speeds in excess
Rev. 0
64
For more information www.analog.com
LTC3888-1
APPLICATIONS INFORMATION
an Analog Devices demo circuit or user application.
LTpowerPlay can also be used offline (no hardware pres-
ent) to build multiple IC configuration files that can be
saved and later reloaded. LTpowerPlay uses the DC1613
USB-to-I2C/SMBus/PMBus controller to communicate
with a system for evaluation, development or debug. The
software also features automatic update to remain up-to-
date with the latest application code and documentation
available from Analog Devices. A great deal of context
INTERFACING TO THE DC1613
The ADI DC1613 USB-to-I2C/SMBus/PMBus control-
ler can be interfaced to the LTC3888-1 on any board for
programming, telemetry and system debug. This includes
the DC2652 from Analog Devices, or any customer tar-
get system. The controller, when used in conjunction
with LTpowerPlay, provides a powerful way to debug an
entire power system. Faults are quickly diagnosed using
telemetry, status registers and the fault log. A final design
configuration can be quickly developed and stored to the
LTC3888-1 EEPROM and/or LTpowerPlay configuration file.
// wait until bits 6, 5, and 4 of MFR_COMMON are all set
do
{
The DC1613 can communicate with, program and even
power one or more LTC3888-1devices, regardless of
whether system power is present. The DC2086 Powered
Programming Adapter can be used to extend the power
sourcing capability of the DC1613. Figure 45 illustrates
an application schematic for in-system programming
of multiple LTC3888-1 devices normally powered from
mfrCommonValue = PMBUS_READ_BYTE(0xEF);
partReady = (mfrCommonValue & 0x68) == 0x68;
}while(!partReady)
// now the part is ready to receive the next command
PMBUS_WRITE_WORD(0x21, 0x2000); //write VOUT_COMMAND to 2V
Figure 44. Example of a Polling Loop to Write VOUT_COMMAND
VIN. If the DC2086 is used, PFETs with lower RDS(ON)
,
sensitive help is available within LTpowerPlay, along with
several tutorials.
such as the SiA907EDJT, should be used in place of the
Si2305CDS devices. If system power is not present, the
ꢀ
ꢁꢂ
ꢈꢃꢁ
ꢓꢎꢂꢏRꢎꢛꢛꢑR
ꢐꢑꢈꢃꢑR
ꢔ00ꢚ
ꢔ00ꢚ
ꢀ
ꢀ
ꢁꢂ
ꢁꢇꢎꢛꢈꢏꢑꢃ
ꢄ.ꢄꢀ
ꢇꢃꢈ
ꢇꢓꢛ
ꢀ
ꢃꢃꢄꢄ
ꢃꢃꢅꢆ
ꢇꢒꢅꢄ0ꢆꢓꢃꢇ
ꢅ.ꢅꢉꢊ
ꢔꢉꢊ
ꢛꢏꢓꢄꢘꢘꢘꢢꢔ
ꢔ0ꢚ
ꢔ0ꢚ
ꢇꢃꢈ
ꢇꢓꢛ
ꢋꢂꢃ
ꢏꢎ ꢃꢓꢔꢜꢔꢄ
ꢅ
ꢝꢇꢞ ꢏꢎ ꢁ ꢓꢟꢇꢌꢞꢠꢡꢟꢗꢌꢞꢠꢡ
ꢓꢎꢂꢏRꢎꢛꢛꢑR
ꢀ
ꢀ
ꢁꢂ
ꢀ
ꢃꢃꢄꢄ
ꢃꢃꢅꢆ
ꢇꢒꢅꢄ0ꢆꢓꢃꢇ
ꢔꢉꢊ
ꢅ.ꢅꢉꢊ
ꢛꢏꢓꢄꢘꢘꢘꢢꢔ
ꢇꢃꢈ
ꢇꢓꢛ
ꢀꢋꢇ ꢌꢈꢍ ꢎꢂ ꢏꢐꢑ ꢇꢒꢅꢄ0ꢆꢓꢃꢇ ꢁꢇ ꢔꢅ ꢕ ꢁꢊ ꢀ ꢖ ꢅ0ꢀ
ꢁꢂ
ꢋꢂꢃ
ꢓꢐꢈꢂꢋꢑ ꢏꢐꢑ RꢑꢇꢁꢇꢏꢎR ꢃꢁꢀꢁꢃꢑR ꢎꢂ ꢏꢐꢑ ꢗꢊꢑꢏ ꢋꢈꢏꢑ
ꢄꢘꢘꢘꢔꢅ ꢊꢙꢆ
Figure 45. DC1613 Connections
Rev. 0
65
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LTC3888-1
APPLICATIONS INFORMATION
DC1613 or DC2086 will power the LTC3888-1 VDD33
supply, allowing in-circuit configuration or manufactur-
ing customization. With VDD33 applied in this fashion,
the device(s) can be initialized when the system is not
powered by using PMBus address 0x5B to send a value
of 0x2B to command 0xBD. If this is followed with a value
of 0xC4 to 0xBD at address 0x5B, the LTC3888-1 will
begin to communicate and allow PMBus command values
to be updated at its normal PMBus device address. Any
changes will become permanent (stored to EEPROM) by
system for TDA21470 power requirements. Details are
shown in Figure 46 for biasing and bypassing one of the
power stages. This detail is not shown for the remaining
seven TDA21470 devices but should be repeated for each
(including V bypass and output filter capacitance), with
IN
components located close to each device using the PCB
layout guidelines given in previous discussion.
The necessary local bypassing is then provided for the
LTC3888-1 INTVCC (4.7µF), VDD33 (2.2µF) and VDD25
(1µF) LDO outputs. These LDO outputs should not be
shared with outputs of other ICs that might have the same
name, because they have independent internal control
loops.
a subsequent STORE_USER_ALL command. When V
IN
is reapplied, MFR_RESET must be excuted to establish
normal operation if command 0xBD has been used for
communication in the absence of system power.
Next, the regulated output for each rail is established by
The DC1613 I2C connections are opto-isolated from
the host PC USB. The DC1613 3.3V current limit is only
100mA, so it should be used to power only one or two
LTC3888-1 devices in-system. Because of this limited
current sourcing capability, only the LTC3888-1 devices,
their associated pull-up resistors and the I2C pull-up
resistors should be powered from the isolated 3.3V sup-
ply provided by the DC1613. Using the DC2086 will enable
in-system programming of several tens of LTC3888-1
devices without normal system power applied. Some
small current, normally less than 1mA, may be driven
back into the internal INTV LDO output or V supply
selecting suitable values for R284, R285 (V
), R277
OUT1
and R278 (V
). Maintaining a total load on DAOUT of
OUT0
50kΩ to 100kΩ is recommended.
The PWM_CONFIG pin is left open to select the factory
default master/slave configuration (4+4) and a PWM oper-
ating frequency (FREQUENCY_SWITCH) of 500kHz, both
of which are desired targets for this appliation. In this
configuration the four phases of each rail are separateed
by 90°, and none of the eight phases overlap, producing
the lowest input and output ripple possible.
The design will plan on a nominal output ripple of about
CC
IN
by each LTC3888-1 when power is applied only to V
.
55% of I
to minimize the magnetics volume, and the
DD33
inductanOceUTvalue is chosen based on this assumption.
Each phase supplies an average of 25A to the output at
2
Any other device sharing the I C bus with the LTC3888-1
should not have internal body diodes between SDA/SCL
pins and their respective logic supply, because this will
interfere with bus communication in the absence of sys-
tem power. Configure both masters to be off, for example
by driving both RUN pins low, to avoid providing power
to the load until the part is fully configured.
full load, resulting in a ripple of 14A in each choke. A
P-P
215nH inductor would create this peak-to-peak ripple at
500kHz on the 1.8V rail. (Ripple on the 1V rail will be less.)
A Cooper FP1007R3-R22-R 220nH inductor is selected
with a 50A saturation current limit at room temperature.
For input filtering, a bank of six 270μF Panasonic OS_CON
capacitors are selected to provide acceptable AC imped-
ance against the designed converter ripple current. High
frequency bypassing (1Ω into 2.2μF) is provided for the
LTC3888-1 itself, and additional ceramic bulk bypass local
to each power stage will also lower ESR on this input at
higher frequencies.
DESIGN EXAMPLE
As a design example, consider a 280W dual output appli-
cation such as the one shown in Figure 46, where V =
IN
12V, V
= 1V, and V
= 1.8V. Both rails support
a ratedOlUoTa0d of 100A. The TDA21470 is chosen as the
power stage for both rails based on its output current
capability, feature set, and small package size. Assume
that an auxillary 5V supply VDR will be available in the
OUT1
Rev. 0
66
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LTC3888-1
APPLICATIONS INFORMATION
V
IN
C
22µF
1210
C
22µF
1210
C
22µF
1210
C
IN4
22µF
1210
IN1
IN2
IN3
PGND PGND
PHASE
V
V
V
V
V
V
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
IN IN IN IN IN IN
C7
0.47µF
VDR
BOOST
EN
V
IN
TDA21470
J1
J2
V
C12
IN
V
7V TO
14V
DRV
4.7µF
C1
270µF
16V
C2
270µF
16V
C3
270µF
16V
C4
270µF
16V
C5
270µF
16V
C6
270µF
16V
+
+
+
+
+
+
V
CC
C14
4.7µF
GND
R3
1Ω
1%
V
DD33
C10
2.2µF
C11
2.2µF
C8
C9
V
DD33
4.7µF 1.0µF
PWM
I
OUT
R10
1k
REFIN VOS TOUT NC GL GL OCSET LGND
V
IN
INTV
V
V
PWM0
DD33
SYNC
SCL
SYNC
SCL
CC DD25
R23
10k
I
R18
1k
SENSE0
C16
0.47µF
330pF
V
IN
R9
1k
PWM2
SENSE2
PWM
OUT
REFIN
TOUT
V
IN
SDA
SDA
I
I
SW
TDA21470
R17
10k
GND
V
OUT0
LTC3888-1
R234
0Ω
J3
J4
ALERT
SHARE_CLK
RUN0
ALERT
V
V
+
SENSE0
SENSE0
R16
4.99k
V
OUT0
V
V
+
–
SENSE0
1V, 100A
R235
0Ω
SHARE_CLK
RUN0
–
R15
10k
GND
SENSE0
PWM3
SENSE3
PWM
V
IN
R244
10k
I
I
SW
OUT
TDA21470
TDA21470
REFIN
TOUT
GND
RUN1
RUN1
I
I
THR0
THR1
C18
6.8nF
PWM4
SENSE4
PWM
V
IN
C19
I
I
SW
OUT
6.8nF
REFIN
TOUT
GND
TSNS0
I
I
TH0
TH1
IREF
TSNS1
PWM1
C21
330pF
C22
330pF
PWM
V
IN
I
I
I
SW
SENSE1
OUT
TDA21470
TDA21470
ASEL0
ASEL1
ILIM0_CFG
ILIM1_CFG
REFIN
TOUT
GND
PWM5
SENSE5
V
PWM
V
OUT1
IN
1.8V
I
SW
OUT
R
SET
100A
REFIN
TOUT
GND
PWM_CFG
R37
5.9k
R39
R40
R41
R38
1.74k
4.42k 4.42k 18.2k
+
V
V
+
–
SENSE0
SENSE0
PWM6
SENSE6
PWM
OUT
REFIN
TOUT
V
IN
I
PGOOD0
PGOOD1
PGOOD0
PGOOD1
VFB0
I
SW
TDA21470
TDA21470
GND
R53
10k
R54
10k
VFB1
PWM7
SENSE7
PWM
V
IN
I
I
SW
OUT
V
DD33
REFIN
TOUT
GND
V
DD33
R49
10k
R48
10k
FAULT0
FAULT1
FAULT0
FAULT1
GND
DAOUT1 DAOUT0
388812 F46
NOTE: SOME POWER STAGE DETAILS OMITTED FOR CLARITY
C122
OPT
R284
52.3k
C121
OPT
R277
42.2k
R278
28k
R285
15k
Figure 46. 1V/100A and 1.8V/100A 500kHz Converter using the TDA21470 DrMOS
Rev. 0
67
For more information www.analog.com
LTC3888-1
APPLICATIONS INFORMATION
V
IN
C
22µF
1210
C
22µF
1210
C
22µF
1210
C
IN4
22µF
1210
IN1
IN2
IN3
PGND PGND
RUN
V
V
V
V
V
V
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
IN IN IN IN IN IN
VDR
V
IN
LTC7051
J1
J2
V
C12
IN
PV
CC
7V TO
14V
4.7µF
C1
270µF
16V
C2
270µF
16V
C3
270µF
16V
C4
270µF
16V
C5
270µF
16V
C6
270µF
16V
+
+
+
+
+
+
1Ω
V
CC
GND
C14
4.7µF
R3
V
DD33
C10
2.2µF
1Ω
1%
TDIO
C11
2.2µF
C8
C9
V
DD33
4.7µF 1.0µF
FLTB
PWM
I
SNS
R10
1k
TMON NC NC NC NC SGND
V
INTV
V
V
DD33
PWM0
SENSE0
SYNC
SCL
SYNC
SCL
IN
CC DD25
I
I
R18
1k
500Ω
C16
330pF
V
IN
0.47µF
R9
1k
PWM2
SENSE2
PWM
SNS
V
IN
SDA
SDA
I
SW
FLTB
GND
LTC7051
R17
10k
V
500Ω
OUT0
TMON
LTC3888-1
R234
0Ω
J3
J4
ALERT
SHARE_CLK
RUN0
ALERT
V
V
+
SENSE0
SENSE0
R16
4.99k
V
OUT0
V
V
+
–
SENSE0
1V, 200A
R235
0Ω
SHARE_CLK
RUN0
–
R15
10k
GND
SENSE0
PWM3
SENSE3
PWM
SNS
V
IN
R244
10k
I
I
I
SW
FLTB
GND
LTC7051
LTC7051
RUN1
RUN1
500Ω
500Ω
TMON
I
I
THR0
THR1
C18
PWM4
SENSE4
PWM
SNS
V
IN
C19
6.8nF
6.8nF
I
SW
FLTB
GND
TSNS0
TMON
I
I
TH0
TH1
IREF
TSNS1
PWM1
C21
C22
330pF
330pF
PWM
SNS
REFIN
TMON
V
IN
I
I
I
SW
FLTB
GND
SENSE1
LTC7051
LTC7051
ASEL0
ASEL1
500Ω
500Ω
ILIM0_CFG
ILIM1_CFG
PWM5
SENSE5
V
PWM
SNS
V
OUT1
IN
1.8V
I
SW
FLTB
GND
R
SET
200A
PWM_CFG
TMON
R37
5.9k
R39
R40
R41
R38
1.74k
4.42k 4.42k 18.2k
+
V
V
+
–
SENSE0
SENSE0
PWM6
SENSE6
PWM
SNS
V
IN
I
PGOOD0
PGOOD1
PGOOD0
PGOOD1
VFB0
I
SW
FLTB
GND
LTC7051
LTC7051
500Ω
500Ω
TMON
R53
10k
R54
10k
VFB1
PWM7
SENSE7
PWM
V
IN
I
I
SW
FLTB
GND
SNS
V
V
DD33
DD33
TMON
R49
10k
R48
10k
FAULT0
FAULT1
FAULT0
FAULT1
GND
DAOUT1 DAOUT0
388812 F47
NOTE: SOME POWER STAGE DETAILS OMITTED FOR CLARITY
C122
OPT
R284
52.3k
C121
OPT
R277
42.2k
R278
28k
R285
15k
Figure 47. 1V/200A and 1.8V/200A 500kHz Converter using the LTC7051 DrMOS
Rev. 0
68
For more information www.analog.com
LTC3888-1
APPLICATIONS INFORMATION
The required RSET resistor (18.7kΩ) is connected to GND.
Resistor configuration is then used on the ASEL0 and
ASEL1 pins to program PMBus address (MFR_ADDRESS)
to 0x28. Each LTC3888-1 must be configured for a
unique address. Using both ASEL pins to accomplish
this is recommended for simpliest in-system program-
ming. Check the selected address to avoid collision with
global addresses or other any other specific devices. The
LTC3888-1 also responds to 7-bit global addresses 0x5A
and 0x5B. MFR_ADDRESS and MFR_RAIL_ADDRESS
should not be set to either of these values. Resistors are
used to program ILIM0_CFG and ILIM1_CFG to set IOUT_
OC_WARN_LIMIT to 32A and IOUT_OC_FAULT_LIMIT
to 40A, based on the design value of 25A rated load
per phase (100A total) with a room temperature choke
saturation of 50A.
Two 470μF Panasonic 5mΩ POSCAPs and three 100μF
ceramic capacitors are chosen for each phase output to
maintain supply regulation during severe transient condi-
tions and to minimize output voltage ripple.
The loop compensation components C18, C21 (V
)
OUT0
and C19,C22 (VOUT1) provide a good starting point to
tune the crossover frequency by programming error
amplifer transconductance and internal R with the help
ITH
of LTpowerCAD, LTpowerPlay and built-in LTC3888-1 load
step emulation. With a 500kHz switching frequency, an
initial crossover target of 100kHz should provide good
transient performance. System phase margin of around
65° is recommended at that bandwidth.
For output current sensing, the TDA21470 provides a
voltage-mode monitor scaled to 5mV/A, ideal for the
LTC3888-1and allowing direct connection from IOUT to the
LTC3888-1 ISENSE pin. The IREF output of the LTC3888-1
is used to provide the necessary common mode refer-
ence to all power stages. Each DrMOS device then has
470nF of local bypassing on this DC reference (REFIN) to
limit introduction of switching noise and crosstalk. These
capacitors should be returned to GND (the LTC3888-1
package paddle) for best noise performance.
PMBus connection (three signals), as well as shared RUN
control and fault propagation (FAULT) for each rail are
provided. SYNC can be used to synchronize other PWMs
to this device if required.
Pull-ups are provided on all open-drain signals assuming
a maximum 100pF line load and PMBus rate of 100kHz.
These pins should not be left floating. Termination to
3.3V ensures the absolute maximum ratings for the pins
are not exceeded. All other operating parameters such
as soft-start/stop and desired fault responses are pro-
grammed via PMBus command values stored in internal
LTC3888-1 EEPROM.
External temperatures of interest are also sensed by the
individual power stages. The highest temperature for each
rail is indicated on the shared TOUT/FLT bus, which is con-
nected directly to the respective LTC3888-1 TSNS input.
Rev. 0
69
For more information www.analog.com
LTC3888-1
PMBus COMMAND DETAILS
(by Functional Groups)
ADDRESSING AND WRITE PROTECT
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
PAGE
0x00 Channel (page) presently selected for any
paged command.
R/W Byte
N
Reg
0x00
PAGE_PLUS_WRITE
PAGE_PLUS_READ
0x05 Write a command directly to a specified page. W Block
N
N
0x06 Read a command directly from a specified
page.
Block R/W
Process
l
WRITE_PROTECT
0x10 Protect the device against unintended PMBus R/W Byte
modifications.
N
Reg
0x00
l
l
MFR_ADDRESS
0xE6 Specify right-justified 7-bit device address.
R/W Byte
R/W Byte
N
Y
Reg
Reg
0x4F
0x80
MFR_RAIL_ADDRESS
0xFA Specify unique right-justified 7-bit address
for channels comprising a PolyPhase output.
PAGE
The PAGE command provides the ability to configure, control and monitor both master channels through only one
physical address, either the MFR_ADDRESS or global device address. Each PAGE contains the operating memory for
one master channel.
Pages 0x00 and 0x01 correspond to Channel 0 (or PWM0) and Channel 1 (or PWM1), respectively.
Setting PAGE to 0xFF applies any following paged commands to both master channels. With PAGE set to 0xFF the
LTC3888-1 will respond to read commands as if PAGE were set to 0x00 (Channel 0 results only).
This command has one data byte.
PAGE_PLUS_WRITE
The PAGE_PLUS_WRITE command provides a way to set the page within a device, send a command and then send the
data for the command, all in one communication packet. Commands allowed by the present write protection level may
be sent with PAGE_PLUS_WRITE.
The value stored in the PAGE command is not affected by PAGE_PLUS_WRITE. If PAGE_PLUS_WRITE is used to send a
non-paged command, the Page Number byte is ignored.
This command uses Write Block protocol. An example of the PAGE_PLUS_WRITE command with PEC sending a command
that has two data bytes is shown in Figure 48.
ꢘ
ꢖ
ꢘ
ꢘ
ꢗ
ꢘ
ꢗ
ꢘ
ꢗ
ꢘ
ꢗ
ꢘ
ꢀꢁꢂꢃꢄ
ꢂꢅꢅRꢄꢀꢀ
ꢆꢂꢇꢄꢈꢆꢁꢉꢀ
ꢊꢋꢌꢌꢂꢍꢅ ꢊꢋꢅꢄ
ꢎꢁꢋꢊꢏ ꢊꢋꢉꢍꢐ
ꢑꢒ ꢓꢔ
ꢆꢂꢇꢄ
ꢍꢉꢌꢎꢄR
ꢊꢋꢌꢌꢂꢍꢅ
ꢊꢋꢅꢄ
ꢀ
ꢕ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢙ
ꢗ
ꢘ
ꢗ
ꢘ
ꢗ
ꢘ
ꢘ
ꢁꢋꢕꢄR ꢅꢂꢐꢂ
ꢎꢚꢐꢄ
ꢉꢆꢆꢄR ꢅꢂꢐꢂ
ꢎꢚꢐꢄ
ꢂ
ꢂ
ꢆꢄꢊ ꢎꢚꢐꢄ
ꢂ
ꢆ
ꢛꢗꢗꢗꢘꢜ ꢝꢓꢗ
Figure 48. Example of PAGE_PLUS_WRITE
Rev. 0
70
For more information www.analog.com
LTC3888-1
PMBus COMMAND DETAILS (Addressing and Write Protect)
PAGE_PLUS_READ
The PAGE_PLUS_READ command provides the ability to set the page within a device, send a command and then read
the data returned by the command, all in one communication packet .
The value stored in the PAGE command is not affected by PAGE_PLUS_READ. If PAGE_PLUS_READ is used to access
data from a non-paged command, the Page Number byte is ignored.
This command uses Block Write – Block Read Process Call protocol. An example of the PAGE_PLUS_READ command
with PEC is shown in Figure 49.
NOTE: PAGE_PLUS commands cannot be nested. A PAGE_PLUS command cannot be used to read or write another
PAGE_PLUS command. If this is attempted, the LTC3888-1 will NACK the entire PAGE_PLUS packet and issue a CML
fault for Invalid/Unsupported Data.
ꢁ
ꢗ
ꢁ
ꢁ
ꢘ
ꢁ
ꢘ
ꢁ
ꢘ
ꢁ
ꢘ
ꢁ
ꢂꢃꢄꢅꢆ
ꢄꢇꢇRꢆꢂꢂ
ꢀꢄꢈꢆꢉꢀꢃꢊꢂ
ꢋꢌꢍꢍꢄꢎꢇ ꢋꢌꢇꢆ
ꢏꢃꢌꢋꢐ ꢋꢌꢊꢎꢑ
ꢒꢓ ꢔꢕ
ꢀꢄꢈꢆ
ꢎꢊꢍꢏꢆR
ꢋꢌꢍꢍꢄꢎꢇ
ꢋꢌꢇꢆ
ꢂ
ꢖ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢙ
ꢁ
ꢗ
ꢁ
ꢁ
ꢘ
ꢁ
ꢘ
ꢁ
ꢘ
ꢁ
ꢘ
ꢁ
ꢁ
ꢂꢃꢄꢅꢆ
ꢄꢇꢇRꢆꢂꢂ
ꢏꢃꢌꢋꢐ ꢋꢌꢊꢎꢑ
ꢃꢌꢖꢆR ꢇꢄꢑꢄ
ꢏꢚꢑꢆ
ꢊꢀꢀꢆR ꢇꢄꢑꢄ
ꢏꢚꢑꢆ
ꢂꢛ
R
ꢄ
ꢄ
ꢄ
ꢄ
ꢀꢆꢋ ꢏꢚꢑꢆ
ꢎꢄ
ꢀ
ꢒꢓ ꢔꢕ
ꢜꢘꢘꢘꢁꢔ ꢝꢞꢟ
Figure 49. Example of PAGE_PLUS_READ
WRITE_PROTECT
The WRITE_PROTECT command is used to control PMBus write access to the LTC3888-1.
Supported Values:
VALUE
0x80
MEANING
Disable all writes except WRITE_PROTECT, PAGE, STORE_USER_ALL and MFR_EE_UNLOCK commands.
0x40
Disable all writes except WRITE_PROTECT, PAGE, STORE_USER_ALL, MFR_EE_UNLOCK, OPERATION, CLEAR_PEAKS and CLEAR_
FAULTS commands. Individual faults can also be cleared by writing a 1 to the respective status bit.
0x20
0x00
Disable all writes except WRITE_PROTECT, PAGE, STORE_USER_ ALL, MFR_EE_UNLOCK, OPERATION, CLEAR_PEAKS, CLEAR_FAULTS,
ON_OFF_CONFIG and VOUT_COMMAND commands. Individual faults can be cleared by writing a 1 to the respective status bit.
Enables writes to all commands.
This command has one data byte.
Rev. 0
71
For more information www.analog.com
LTC3888-1
PMBus COMMAND DETAILS (Addressing and Write Protect/General Device Configuration)
MFR_ADDRESS
The MFR_ADDRESS command sets the seven bits of the PMBus device address for this unit.
Setting this command to a value of 0x80 disables device-level addressing. The global device addresses 0x5A and
0x5B cannot be disabled. The LTC3888-1 always responds at these addresses. The device address, or any portion of
an address, specified with external resistors on ASEL0 or ASEL1 is applied. If both of these pins are open, the device
address is determined strictly by the MFR_ADDRESS value stored in EEPROM. Refer to the Operation section on
Resistor Configuration Pins for additional details.
This command has one data byte.
MFR_RAIL_ADDRESS
The MFR_RAIL_ADDRESS command sets a direct PMBus address for the active channel(s) as determined by the PAGE
command. This address should be common to all master channels attached to a single power supply rail. Setting this
command to a value of 0x80 disables rail addressing for the selected channel. Only command writes should be made
to the rail address. If a read is performed from this address, a CML fault may result.
This command has one data byte.
GENERAL DEVICE CONFIGURATION
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
PMBUS_REVISION
0x98 Supported PMBus version.
R Byte
Y
N
N
Reg
Reg
Reg
0x22
V1.2
CAPABILITY
0x19 Summary of supported optional PMBus
features.
R Byte
0xB0
l
MFR_CONFIG_ALL
0xD1 General device-level configuration.
R/W Byte
0x21
PMBUS_REVISION
The PMBUS_REVISION command returns the revision of the PMBus Specification that the device supports. The
LTC3888-1 is compliant with PMBus Version 1.2, both Part I and Part II.
This read-only command has one data byte.
CAPABILITY
The CAPABILITY command reports some key LTC3888-1 features to the PMBus host device.
The LTC3888-1 supports packet error checking, 400kHz bus speeds and has an ALERT output.
This read-only command has one data byte.
Rev. 0
72
For more information www.analog.com
LTC3888-1
PMBus COMMAND DETAILS (General Device Configuration/On, Off and Margin Control)
MFR_CONFIG_ALL
The MFR_CONFIG_ALL command provides device-level configuration common to multiple ADI PMBus products.
Bit Definitions:
BIT
7
MEANING
Enable fault logging.
6
Ignore ILIM and PWM resistor configuration pins.
Disable CML fault for quick command message.
Disable SYNC output.
5
4
3
Enable 255ms PMBus timeout.
2
Require valid PEC for PMBus write.
Enable PMBus clock stretching.
1
0
Execute CLEAR_FAULTS when either channel is turned on by RUN pin or OPERATION command.
If a legal command is received with an invalid PEC, the LTC3888-1 will not execute the command, regardless of the state
of bit 2. If clock stretching is enabled, the LTC3888-1 only uses it as required, generally above SCL rates of 100kHz.
This command has one data byte.
ON, OFF AND MARGIN CONTROL
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
l
ON_OFF_CONFIG
0x02 RUN pin and PMBus on/off command
configuration.
R/W Byte
Y
Reg
Reg
0x1E
l
OPERATION
MFR_RESET
0x01 On, off and margin control.
R/W Byte
Send Byte
Y
N
0x80
0xFD Force full reset without removing power.
ON_OFF_CONFIG
The ON_OFF_CONFIG command specifies the combination of RUN pin input state and PMBus commands needed to
turn the addressed output rail on and off.
Supported Values:
VALUE
0x1F
MEANING
OPERATION value and RUN pin must both command the device to start/run. Device executes immediate off when commanded off.
OPERATION value and RUN pin must both command the device to start/run. Device uses TOFF_ command values when commanded off.
RUN pin control with immediate off when commanded off. OPERATION on/off control ignored.
RUN pin control using TOFF_ command values when commanded off. OPERATION on/off control ignored.
0x1E
0x17
0x16
Programming an unsupported ON_OFF_CONFIG value will generate a CML fault and the command will be ignored.
This command has one data byte.
Rev. 0
73
For more information www.analog.com
LTC3888-1
PMBus COMMAND DETAILS (On, Off and Margin Control)
OPERATION
The OPERATION command is used to turn the related output rail on and off in conjunction with RUN pin hardware
control. This command may also be used to move the output voltage to margin levels. V
changes commanded by
OUT
OPERATION margin commands occur at the programmed VOUT_TRANSITION_RATE. The unit stays in the commanded
operating state until an OPERATION command or RUN pin voltage instructs the device to change to another state.
Execution of margin commands is delayed until any on-going output transition sequencing is completed. Margin
operations that ignore faults are not supported by the LTC3888-1.
Supported Values:
VALUE
0xA8
MEANING
Margin high.
Margin low.
0x98
0x80
On (i.e. nominal V , even if bit 3 of ON_OFF_CONFIG is not set).
OUT
0x40*
0x00*
Soft off (with sequencing).
Immediate off (no sequencing).
*Device does not respond to these commands if bit 3 of ON_OFF_CONFIG is not set.
Programming an unsupported OPERATION value will generate a CML fault and the command will be ignored.
This command has one data byte.
MFR_RESET
This command provides a means to fully reset the LTC3888-1 from the serial bus. This forces the LTC3888-1 to turn
off all PWM channels, load the operating memory from internal EEPROM, clear all faults and then perform a soft-start
of all PWM channels that are enabled.
This write-only command has no data bytes.
Rev. 0
74
For more information www.analog.com
LTC3888-1
PMBus COMMAND DETAILS (PWM Configuration)
PWM CONFIGURATION
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
l
FREQUENCY_SWITCH
0x33 PWM frequency control.
R/W Word
N
L11
kHz
500kHz
0xFBE8
l
l
MFR_CHAN_CONFIG
0xD0 General channel-specific configuration.
R/W Byte
R/W Byte
Y
N
Reg
Reg
0x1D
0x03
MFR_PWM_CONFIG_LTC3888-1
0xF5 LTC3888-1 PWM configuration common to
both master channels.
l
l
MFR_PWM_MODE_LTC3888-1
MFR_PWM_COMP
0xD4 Channel-specific LTC3888-1 PWM mode
control.
R/W Byte
R/W Byte
Y
Y
Reg
Reg
0x02
0xAE
0xD3 Channel-specific PWM loop compensation
FREQUENCY_SWITCH
The FREQUENCY_SWITCH command sets the switching frequency of all LTC3888-1 PWM channels in kilohertz. The
valid range for this command value is 250 to 1000, inclusive. At most only one IC sharing SYNC should be programmed
as clock master. See bit 4 in MFR_CONFIG_ALL. FREQUENCY_SWITCH value will determine the free-running frequency
of PWM operation if an expected external clock source is not present or the bussed SYNC line becomes stuck due an
external fault or conflict. Both master channels must be turned off by the RUN pins, OPERATION command, or their
combination to process this command. If this command is sent while either master channel is operating, the LTC3888-1
will NACK the command byte, ignore the command and its data, and assert a BUSY fault. A PLL Unlocked status may
be reported after changing the value of this command until the new frequency is established.
This command has two data bytes in Linear_5s_11s format.
Rev. 0
75
For more information www.analog.com
LTC3888-1
PMBus COMMAND DETAILS (PWM Configuration)
MFR_CHAN_CONFIG
The MFR_CHAN_CONFIG command provides per-channel configuration common to multiple ADI PMBus products.
Bit Definitions:
BIT
7:6
5
MEANING
(Reserved, must write as 0).
Pin 8 function control: (Page 0 only)
0: Pin 8 functions as TSNS0.
1: Pin 8 functions as VDR_MON.
RUN pin control:
4
3
2
0: When the channel is commanded off, the associated RUN pin is pulsed low for TOFF_DELAY + V /VOUT_TRANSITION_RATE + 136ms
OUT
(or MFR_RESTART_DELAY, if longer) regardless of the state of bit 3.
1: RUN pin is not pulsed low if channel is commanded off.
Short cycle control:
0: No special control. Device attempts to follow on/off commands exactly as issued.
1: Output is immediately disabled if commanded back on while waiting for TOFF_DELAY or V /VOUT_TRANSITION_RATE to expire.
A minimum off time of 120ms is then enforced before the channel is turned back on. Additional delay will apply if bit 4 is clear.
OUT
SHARE_CLK output control:
0: No special control.
1: Output disabled if SHARE_CLK is held low.
(Reserved, must write as 0).
MFR_RETRY_DELAY control:
1
0
0: No retry allowed after output off for any reason until V
≤ 0.125xVOUT_COMMAND.
OUT
1: No special control (TOFF_MAX_WARN_LIMIT also disabled).
This command has one data byte.
MFR_PWM_CONFIG_LTC3888-1
The MFR_PWM_CONFIG_LTC3888-1 command controls primary master/slave configuration and monitor ADC sam-
pling control for the LTC3888-1. Both master channels must be turned off by the RUN pins, OPERATION command,
or their combination to process this command. If this command is sent while either master channel is operating, the
LTC3888-1 will NACK the command byte, ignore the command and its data, and assert a BUSY fault.
Rev. 0
76
For more information www.analog.com
LTC3888-1
PMBus COMMAND DETAILS (PWM Configuration)
Bit Definitions
BIT
7
MEANING
(Reserved, must write as 0)
6
Slave I
Telemetry:
OUT
0: The LTC3888-1 provides continuous IOUT telemetry for all enabled phases.
1: The LTC3888-1 only provides IOUT telemetry for master channels PWM0 and PWM1.
5
4
(Reserved)
VOUT_OV_FAULT HW Response:
0: No special low level response, master phase obeys VOUT_OV_FAULT_RESPONSE of immediate off (PWM Hi-Z).
1: PWM of master phase driven low during VOUT_OV_FAULT, synchronous bottom power FET attempts to discharge V
with rail off.
OUT
3
Phase Expansion:
0: The power-good state for Channel 0 is output on PGOOD0.
1: A phase expansion clock (CLKOUT) is output on PGOOD0 to drive SYNC on a second LTC3888-1.
Master/Slave Configuration
Value
Master
PWM0
PWM0
PWM0
PWM0
PWM0
PWM0
PWM0
PWM1
PWM0
PWM0
PWM0
PWM0
PWM0
PWM0
PWM1
PWM1
PWM0
PWM0
PWM0
PWM0
PWM0
PWM0
PWM1
Configuration / Slave
7-Phase
PWM2
Phase (*)
0
51.4
154.3
205.7
102.9
257.1
308.6
25.7
0
PWM3
PWM4
111
110
101
PWM5
PWM6
PWM7
1-Phase
(6-Phase)
PWM2
60
PWM3
180
240
120
300
30
[2:0]
PWM4
PWM5
PWM6
(2-Phase)
PWM7
210
0
(6-Phase)
PWM2
60
PWM3
180
240
120
300
30
PWM4
PWM5
PWM6
(1-Phase)
PWM7
Off
Rev. 0
77
For more information www.analog.com
LTC3888-1
PMBus COMMAND DETAILS (PWM Configuration)
MFR_PWM_CONFIG_LTC3888-1 Bit Definitions (continued)
Master/Slave Configuration
Value
Master
PWM0
PWM0
PWM0
PWM0
PWM0
PWM1
PWM1
PWM1
PWM0
PWM0
PWM0
PWM0
PWM1
PWM1
PWM1
PWM1
PWM0
PWM0
PWM0
PWM0
PWM1
PWM1
PWM1
Configuration / Slave
Phase (*)
0
(5-Phase)
PWM2
72
PWM3
144
216
288
34.3
274.4
154.3
0
PWM4
100
011
010
001
000
PWM5
(3-Phase)
PWM6
PWM7
(4-Phase, optional 8-phase with PWM1)
PWM2
90
PWM3
180
270
45
PWM4
(4-Phase, Optional 8-Phase with PWM0)
PWM5
135
225
315
0
PWM6
PWM7
(4-Phase)
PWM2
90
PWM3
180
270
42.9
162.9
282.9
Off
PWM4
[2:0]
(3-Phase)
PWM5
PWM6
PWM7
PWM0
PWM0
PWM0
PWM0
PWM1
(4-Phase)
0
PWM2
90
PWM3
180
270
45
PWM4
(2-Phase)
PWM5
Off
PWM1
PWM6
225
Off
PWM7
PWM0
(3-Phase)
0
PWM0
PWM2
120
Off
PWM3
PWM0
PWM1
PWM1
PWM1
PWM4
240
60
(3-Phase, Optional 6-Phase with PWM0)
PWM5
PWM6
PWM7
180
300
Off
Phase is expressed from the falling edge of SYNC to the rising edge of PWM.
This command has one data byte.
Rev. 0
78
For more information www.analog.com
LTC3888-1
PMBus COMMAND DETAILS (PWM Configuration)
MFR_PWM_MODE_LTC3888-1
The MFR_PWM_MODE_LTC3888-1 command sets important PWM controls for each master channel. The addressed
channel(s) must be turned off by its RUN pin, OPERATION command, or their combination when this command is
issued. Otherwise the LTC3888-1 will NACK the command byte, ignore the command and its data, and assert a BUSY
fault.
Bit Definitions
BIT
7
MEANING
(Reserved)
6
Enable V
servo. (VOUT_LOOP_SCALE should be programmed first.)
OUT
5
(Reserved, must write as 0)
Error Amplifier Disable:
4
0: Error Amplifier output (I ) enabled. Channel operates as voltage loop master.
TH
1: Error Amplifier output disabled (I high-Z input). Channel operates as slave phase to another master.
TH
3
2
(Reserved)
(Reserved)
t
Control:
ON_MIN
1
0: Minimum PWM On Time Set by Controller (can be < 30ns).
1: Minimum PWM On Time Limited to ≥ 30ns.
Power Stage UV HW Response: (see Applications Information for exceptions)
0: Rail ignores any UV indication on shared TEMP/FAULT bus.
1: Rail is latched off if UV is indicated on the shared TEMP/FAULT bus while operating.
0
(WARNING: Not all power stages support this feature.)
This command has one data byte.
Rev. 0
79
For more information www.analog.com
LTC3888-1
PMBus COMMAND DETAILS (PWM Configuration)
MFR_PWM_COMP
The MFR_PWM_COMP command sets the transconductance of the voltage loop error amplifier and the value of the
internal compensation resistor R for each master channel.
ITH
Bit Definitions
BIT
MEANING
Value
Error Amplifier gm (mS)
000b
1.00
001b
010b
011b
100b
101b
110b
111b
1.68
2.35
3.02
3.69
4.36
5.04
5.73
[7.5]
Value
R
ITH
(kΩ)
00000b
00001b
00010b
00011b
00100b
00101b
00110b
00111b
01000b
01001b
01010b
01011b
01100b
01101b
01110b
01111b
10000b
10001b
10010b
10011b
10100b
10101b
10110b
10111b
11000b
11001b
11010b
11011b
11100b
11101b
11110b
11111b
1
1
1
1
1
1.25
1.5
1.75
2
2.5
3
3.5
4
4.5
5
5.5
6
7
8
9
11
13
15
17
20
24
28
32
38
46
54
62
[4:0]
This command has one data byte.
Rev. 0
80
For more information www.analog.com
LTC3888-1
(Input Voltage and Limits)
PMBus COMMAND DETAILS
INPUT VOLTAGE AND LIMITS
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
l
VIN_ON
0x35 Minimum input voltage to begin power
conversion.
R/W Word
N
N
N
N
L11
L11
L11
L11
V
V
V
V
6.5V
0xCB40
l
l
l
VIN_OFF
0x36 Decreasing input voltage at which power
conversion stops.
R/W Word
R/W Word
R/W Word
6.0V
0xCB00
VIN_OV_FAULT_LIMIT
VIN_UV_WARN_LIMIT
0x55
V
IN
overvoltage fault limit.
15.5V
0xD3E0
0x58
V
IN
undervoltage warning limit.
6.3V
0xCB26
Related commands: STATUS_INPUT, SMBALERT_MASK, READ_VIN, VIN_OV_FAULT_RESPONSE
VIN_ON
The VIN_ON command sets the input voltage, in volts, required to start power conversion.
This command has two data bytes in Linear_5s_11s format.
VIN_OFF
The VIN_OFF command sets the minimum input voltage, in volts, at which power conversion stops.
This command has two data bytes in Linear_5s_11s format.
VIN_OV_FAULT_LIMIT
The VIN_OV_FAULT_LIMIT command sets the value of the input voltage measured by the ADC, in volts, that causes
an input overvoltage fault.
This command has two data bytes in Linear_5s_11s format.
VIN_UV_WARN_LIMIT
The VIN_UV_WARN_LIMIT command sets the value of input voltage measured by the ADC, in volts, that causes an
input undervoltage warning. This warning is disabled until the input exceeds the VIN_ON command value and the unit
has been enabled. If the VIN_UV_WARN_LIMIT is then exceeded, the device:
•
•
•
Sets the INPUT Bit in the STATUS_WORD
Sets the V Undervoltage Warning Bit in the STATUS_INPUT Command
IN
Notifies the Host by Asserting ALERT, Unless Masked
Rev. 0
81
For more information www.analog.com
LTC3888-1
(Output Voltage and Limits)
PMBus COMMAND DETAILS
(for PMBus Control, DEFAULT VALUE Applies to Analog Control)
OUTPUT VOLTAGE AND LIMITS
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
l
VOUT_COMMAND
0x21 Default V regulation. Nominal V
value
R/W Word
Y
Y
Y
L16
L16
L16
V
V
V
400mV
0x0666
FB
OUT
when VOUT_SCALE_LOOP is defined.
VOUT_MAX
0x24 Maximum V capability.
R Word
R Word
1.1V
0x119A
OUT
MFR_VOUT_MAX
0xA5 Maximum value allowed for VOUT_MAX.
3.75V
0x3C00
l
l
VOUT_MARGIN_HIGH
VOUT_MARGIN_LOW
0x25
0x26
V
(default) or V
at high margin, must be R/W Word
Y
Y
L16
L16
V
V
420mV
0x06B8
FB
OUT
greater than VOUT_COMMAND.
V
FB
(default) or V at low margin, must be R/W Word
380mV
0x0614
N/A
OUT
greater than VOUT_COMMAND.
l
l
l
l
l
VOUT_SCALE_LOOP
0x29 Nominal V /V gain provided by external R/W Word
Y
Y
Y
Y
Y
L11
L16
L16
L16
L16
V
V
V
V
V
OUT FB
feedback network.
VOUT_OV_FAULT_LIMIT
VOUT_OV_WARN_LIMIT
VOUT_UV_WARN_LIMIT
VOUT_UV_FAULT_LIIMIT
0x40 Default V overvoltage fault limit. V
OV
OUT
R/W Word
R/W Word
440mV
0x070A
FB
limit if VOUT_SCALE_LOOP is defined.
0x42
0x43
V
V
overvoltage warning limit sensed at
.
3.6V
0x3981
OUT
SENSE
V
V
undervoltage warning limit sensed at
.
R/W Word
0.0V
0x0000
OUT
SENSE
0x44 Default V undervoltage fault limit. V
UV R/W Word
OUT
360mV
0x05C3
FB
limit if VOUT_SCALE_LOOP is defined.
Related commands: STATUS_VOUT, SMBALERT_MASK, READ_VOUT, MFR_VOUT_PEAK, VOUT_OV_FAULT_RESPONSE, VOUT_UV_FAULT_RESPONSE
VOUT_MODE
The VOUT_MODE command gives the format used by the device for output voltage related commands. Only Linear
Mode is supported, with a resolution of 244µV. Sending the VOUT_MODE command to the LTC3888-1 using a write
protocol will result in a CML fault.
This read-only command has one data byte.
VOUT_COMMAND
VOUT_COMMAND is used to set the output voltage in volts if VOUT_SCALE_LOOP has been defined. Execution of this
command is delayed if VOUT_SCALE_LOOP is being processed or until any ongoing soft-on/off output sequence is
ccomplete. Otherwise, the output voltage moves to a new value at VOUT_TRANSITION_RATE.
This command has two data bytes in Linear_16u format.
VOUT_MAX
The VOUT_MAX command returns the maximum value, in volts, allowed for any V -related command, including
OUT
VOUT_OV_FAULT_LIMIT. This value represents the maximum regulated voltage the selected rail is capable of produc-
ing based on internal design and the value of VOUT_SCALE_LOOP.
This read-only command has two data bytes in Linear_16u format.
Rev. 0
82
For more information www.analog.com
LTC3888-1
(Output Voltage and Limits)
PMBus COMMAND DETAILS
MFR_VOUT_MAX
The MFR_VOUT_MAX command returns the maximum value, in volts, allowed for VOUT_MAX based on internal device
capability.
This read-only command has two data bytes in Linear_16u format.
VOUT_MARGIN_HIGH
The VOUT_MARGIN_HIGH command programs the value of V (or V
if VOUT_SCALE_LOOP has been defined),
OUT
FB
in volts, to be produced when Margin High is set with the OPERATION command. The value must be greater than
VOUT_COMMAND. Execution of this command is delayed if VOUT_SCALE_LOOP is being processed.
This command has two data bytes in Linear_16u format.
VOUT_MARGIN_LOW
The VOUT_MARGIN_LOW command programs the value of V (or V
if VOUT_SCALE_LOOP has been defined),
OUT
FB
in volts, to be produced when Margin Low is set with the OPERATION command. The value must be less than VOUT_
COMMAND. Execution of this command is delayed if VOUT_SCALE_LOOP is being processed.
This command has two data bytes in Linear_16u format.
VOUT_SCALE_LOOP
The VOUT_SCALE_LOOP command programs the gain, in volts per volt, produced from V to V
by the external
FB
OUT
voltage feedback network. Values from 1 to 9 are considered valid. The LTC3888-1 will assert a CML fault and ignore
the value if an attempt is made to write VOUT_SCALE_LOOP to a value outside of this range.
This command has two data bytes in Linear_5s_11s format.
VOUT_OV_FAULT_LIMIT
The VOUT_OV_FAULT_LIMIT command sets the value value of VFB (or VOUT if VOUT_SCALE_LOOP has been defined),
in volts, that causes an output overvoltage fault. If VOUT_OV_FAULT_LIMIT is modified while the channel is on, 2ms
should be allowed for the new value to take effect. Modifying VOUT during that time can result in an erroneous OV fault.
The LTC3888-1 sets MFR_COMMON bits[6:5] low while a new VOUT_OV_FAULT_LIMIT is established. Execution of
this command is delayed if VOUT_SCALE_LOOP is being processed.
This command has two data bytes in Linear_16u format.
VOUT_OV_WARN_LIMIT
The VOUT_OV_WARN_LIMIT command sets the value, in volts, of the V
differential voltage measured by the
SENSE
ADC that causes an output overvoltage warning. If the VOUT_OV_WARN_LIMIT is exceeded, the device:
• Sets the VOUT Bit in the STATUS_WORD
• Sets the V
Overvoltage Warning Bit in the STATUS_VOUT Command
OUT
• Notifies the Host by Asserting ALERT, Unless Masked
This command has two data bytes in Linear_16u format.
Rev. 0
83
For more information www.analog.com
LTC3888-1
(Output Voltage and Limits)
PMBus COMMAND DETAILS
VOUT_UV_WARN_LIMIT
The VOUT_UV_WARN_LIMIT command sets the value, in volts, of the V
differnetial voltage measured by the
SENSE
ADC that causes an output undervoltage warning. If the VOUT_UV_WARN_LIMIT is exceeded, the device:
• Sets the VOUT Bit in the STATUS_WORD
• Sets the V
Undervoltage Warning Bit in the STATUS_VOUT Command
OUT
• Notifies the Host by Asserting ALERT, Unless Masked
This command has two data bytes in Linear_16u format.
VOUT_UV_FAULT_LIMIT
The VOUT_UV_FAULT_LIMIT command sets the value of V (or V
if VOUT_SCALE_LOOP has been defined), in
FB
OUT
volts, that causes an output undervoltage fault. If VOUT_UV_FAULT_LIMIT is modified while the channel is on, 2ms
should be allowed for the new value to take effect. Modifying VOUT during that time can result in an erroneous UV fault.
The LTC3888-1 sets MFR_COMMON bits[6:5] low while a new VOUT_UV_FAULT_LIMIT is established. Execution of
this command is delayed if VOUT_SCALE_LOOP is being processed.
This command has two data bytes in Linear_16u format.
Rev. 0
84
For more information www.analog.com
LTC3888-1
(Output Current and Limits)
PMBus COMMAND DETAILS
OUTPUT CURRENT AND LIMITS
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
l
IOUT_CAL_GAIN
0x38 Ratio of I
voltage to sensed current.
R/W Word
Y
L11
mΩ
5mΩ
0xCA80
SENSE
MFR_LOAD_EMULATION
IOUT_OC_FAULT_LIMIT
0xF7 Load step emulation control.
R/W Byte
Y
Y
Reg
L11
0x00
l
l
0x46 Per phase output overcurrent fault limit.
R/W Word
A
A
29.75A
0xDBB8
IOUT_OC_WARN_LIMIT
0x4A Per phase output overcurrent warning limit.
R/W Word
Y
L11
20.0A
0xDA80
Related commands: STATUS_IOUT, SMBALERT_MASK, READ_IOUT, MFR_IOUT_PEAK, MFR_TOTAL_IOUT,
MFR_READ_ALL_IOUT,IOUT_OC_FAULT_RESPONSE
IOUT_CAL_GAIN
The IOUT_CAL_GAIN command is used to set the power stage output current monitor gain at I
in milliohms. If
SENSE
both master channels are not commanded off by their RUN pin or OPERATION command when IOUT_CAL_GAIN is
sent to either page, the LTC3888-1 will assert a CML fault.
This command has two data bytes in Linear_5s_11s format.
MFR_LOAD_EMULATION
The MFR_LOAD_EMULATION command is used to control load step emulation for all phases on each master channel.
MFR_LOAD_EMULATION
BIT
7
MEANING
(Reserved)
6
(Reserved)
5
(Reserved)
4
(Reserved)
3
Enable Load Step Emulation (LSE) Event Scope Trigger on PGOOD (negative edge)
LSE Mode Control:
2
0: Non-pulsed: LSE state statically follows data written to bits[1:0}.
1: Pulsed: Writing any non-zero state to bits [1:0] produces an LSE pulse of the specified magnitude with a width of ~ 100µs.
Value
11b
Load Step Emulated at IOUT_CAL_GAIN = 5mΩ
30A/Phase
20A/Phase
10A/Phase
Off
[1:0]
10b
01b
00b
This command has one data byte.
Rev. 0
85
For more information www.analog.com
LTC3888-1
(Output Current and Limits)
PMBus COMMAND DETAILS
IOUT_OC_FAULT_LIMIT
The IOUT_OC_FAULT_LIMIT command sets the value of the per phase output current, in amperes, which will cause the
OC supervisor to detect an output overcurrent fault. The LTC3888-1 uses IOUT_CAL_GAIN and the voltage between the
I
inputs and IREF to determine output current. Output overcurrent faults are ignored during turn-on and turn-off
SENSE
output transitions.
This command has two data bytes in Linear_5s_11s format.
IOUT_OC_WARN_LIMIT
The IOUT_OC_WARN_LIMIT command sets the value of the average per phase output current measured by the ADC,
in amperes, that causes an output overcurrent warning. To provide meaningful responses, this value should be set
below IOUT_OC_FAULT_LIMIT. If the IOUT_OC_WARN_LIMIT is exceeded, the device:
• Sets the IOUT Bit in the STATUS_WORD
• Sets the I
Overcurrent Warning Bit in the STATUS_IOUT Command
OUT
• Notifies the Host by Asserting ALERT, Unless Masked
Output overcurrent warnings are ignored during turn-on and turn-off output transitions.
This command has twºo data bytes in Linear_5s_11s format.
Rev. 0
86
For more information www.analog.com
LTC3888-1
(Output Timing, Delays, and Ramping)
PMBus COMMAND DETAILS
OUTPUT TIMING, DELAYS, AND RAMPING
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
l
MFR_RESTART_DELAY
0xDC Minimum time RUN pin is held low by the
LTC3888-1.
R/W Word
Y
Y
Y
L11
L11
L11
ms
ms
ms
500ms
0xFBE8
l
l
TON_DELAY
0x60 Delay from RUN pin or OPERATION on
command to beginning of soft-start ramp.
R/W Word
R/W Word
0.0ms
0x8000
TON_MAX_FAULT_LIMIT
0x62 Maximum time for V (default) or V
to
10.0ms
0xD280
FB
OUT
rise above VOUT_UV_FAULT_LIMIT after
TON_DELAY.
–1
l
VOUT_TRANSITION_RATE
0x27 Slew rate for V (default) or V
soft-on/
R/W Word
Y
L11
ms
0.01
0x82BF
FB
OUT
off and margining, including changes to
VOUT_COMMAND.
l
l
TOFF_DELAY
0x64 Delay from RUN pin or OPERATION off
command to beginning of soft-off ramp.
R/W Word
R/W Word
Y
Y
L11
L11
ms
ms
0.0ms
0x8000
TOFF_MAX_WARN_LIMIT
0x66 Maximum time for V
to reach
0.0ms
0x8000
OUT
0.125xVOUT_COMMAND after being
commanded to 0.0V.
Related commands: MFR_RETRY_DELAY, STATUS_VOUT, SMBALERT_MASK, TON_MAX_FAULT_RESPONSE
These commands can be used to establish required sequencing and tracking for any number of system power supply rails.
MFR_RESTART_DELAY
The MFR_RESTART_DELAY command specifies the minimum rail off time (RUN low) in milliseconds. The LTC3888-1
will actively hold its RUN pin low for this length of time if a falling RUN edge is detected. After this delay, a standard
start-up sequence can be initiated. A minimum of TOFF_DELAY + TOFF_FALL + 136ms is recommended for this com-
mand value. Valid value range is 136ms to 65.52 seconds. The LTC3888-1 will not produce delays outside of this range
and uses a resolution of 16ms for this command.
This command has two data bytes in Linear_5s_11s format.
TON_DELAY
The TON_DELAY command sets the delay, in milliseconds, between a PWM start condition and the beginning of the
output voltage rise. Values from 0ms to 83 seconds are considered valid, and the LTC3888-1 will not produce delays
outside of this range.
This command has two data bytes in Linear_5s_11s format.
TON_MAX_FAULT_LIMIT
The TON_MAX_FAULT_LIMIT command sets the maximum time, in milliseconds, the unit is allowed from the begin-
ning of the soft-start ramp to power up the output without passing VOUT_UV_FAULT_LIMIT. A value of 0ms means
there is no limit and the unit can attempt to bring up the output voltage indefinitely. The maximum allowed TON_MAX
is 8 seconds. To avoid generation of spurious faults, the value of this command should be set to meet the following
guideline.
TON_MAX_FAULT_LIMIT ≥ 1.25xVOUT_COMMAND/VOUT_TRANSITION_RATE
This command has two data bytes in Linear_5s_11s format.
Rev. 0
87
For more information www.analog.com
LTC3888-1
(Output Timing, Delays, and Ramping)
PMBus COMMAND DETAILS
VOUT_TRANSITION_RATE
When using factory defaults, the VOUT_TRANSITION_RATE command sets the rate at which VFB changes during
soft-on/off and when margin commands are executed. If VOUT_SCALE_LOOP is definded this command specifies the
rate at which the output voltage changes whenever commanded to moved. In either case this rate of change does not
apply to operations that immediately turn the PWM channel on or off.
This command has two data bytes in Linear_5s_11s format.
TOFF_DELAY
The TOFF_DELAY command sets the delay, in milliseconds, between a stop condition and the beginning of the output
voltage fall. Values from 0s to 16s are considered valid.
This command has two data bytes in Linear_5s_11s format.
TOFF_MAX_WARN_LIMIT
The TOFF_MAX_WARN_LIMIT command sets the time, in milliseconds, V
is allowed to drop to 0.125xVOUT_
OUT
COMMAND after being commanded to 0V. This time begins after TOFF_DELAY+VOUT_COMMAND/VOUT_TRANSITION
expires if the output is not commanded to immediate off. If this limit is exceeded a warning is issued in VOUT_STATUS
and ALERT asserted if not masked. No warning limit is enforced if bit 0 of MFR_CHAN_CONFIG is set or the value of
this command is programmed to zero. Otherwise, values from 120ms to 524s are considered valid. In order to avoid
erroneous ALERT indication, VOUT_SCALE_LOOP and all other related V
commands must be defined before this
OUT
command is set to a non-zero value.
This command has two data bytes in Linear_5s_11s format.
Rev. 0
88
For more information www.analog.com
LTC3888-1
(External Temperature and Limits)
TYPE
PMBus COMMAND DETAILS
EXTERNAL TEMPERATURE AND LIMITS
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
PAGED FORMAT UNITS NVM
l
MFR_TEMP_1_GAIN
0xF8 Slope for external temperature calculations.
R/W Word
R/W Word
R/W Word
R/W Word
Y
Y
Y
Y
L11
L11
L11
L11
mV/°C
mV
°C
8mV/°C
0xD200
l
l
l
MFR_TEMP_1_OFFSET
OT_FAULT_LIMIT
0xF9 0°C offset for external temperature
calculations.
600mV
0x0258
0x4F External overtemperature fault limit.
100.0°C
0xEB20
OT_WARN_LIMIT
0x51 External overtemperature warning limit.
°C
85.0°C
0xEAA8
Related commands: STATUS_TEMPERATURE, SMBALERT_MASK, READ_TEMPERATURE_1,MFR_TEMPERATURE1_PEAK, OT_FAULT_RESPONSE
MFR_TEMP_1_GAIN
The MFR_TEMP_1_GAIN command sets the slope, in mV/°C, used in the calculation of external temperature based on
monitor ADC conversions of the shared TEMP/FAULT bus (TSNS pins).
This command has two data bytes in Linear_5s_11s format.
MFR_TEMP_1_OFFSET
The MFR_TEMP_1_OFFSET command sets the 0°C offset, in mV, used in the calculation of external temperature based
on monitor ADC conversions of the shared TEMP/FAULT bus (TSNS pins).
This command has two data bytes in Linear_5s_11s format.
OT_FAULT_LIMIT
The OT_FAULT_LIMIT command sets the value of sensed external temperature, in degrees Celsius, which causes an
overtemperature fault.
This command has two data bytes in Linear_5s_11s format.
OT_WARN_LIMIT
The OT_WARN_LIMIT command sets the value of sensed external temperature, in degrees Celsius, which causes an
overtemperature warning. If the OT_WARN_LIMIT is exceeded, the device:
• Sets the TEMPERATURE Bit in the STATUS_BYTE
• Sets the Overtemperature Warning Bit in the STATUS_TEMPERATURE Command
• Notifies the Host by Asserting ALERT, Unless Masked
This command has two data bytes in Linear_5s_11s format.
Rev. 0
89
For more information www.analog.com
LTC3888-1
(Status Reporting)
PMBus COMMAND DETAILS
STATUS REPORTING
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
STATUS_BYTE
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
0x78 One-byte channel status summary.
0x79 Two-byte channel status summary.
R/W Byte
R/W Word
R/W Byte
R/W Byte
R/W Byte
R/W Byte
Y
Y
Y
Y
N
Y
Reg
Reg
Reg
Reg
Reg
Reg
STATUS_WORD
STATUS_VOUT
0x7A
0x7B
V fault and warning status.
OUT
fault and warning status.
STATUS_IOUT
I
OUT
STATUS_INPUT
STATUS_TEMPERATURE
0x7C Input supply fault and warning status.
0x7D External temperature fault and warning
status.
STATUS_CML
0x7E Communication, memory and logic fault and R/W Byte
warning status.
N
Reg
STATUS_MFR_SPECIFIC
MFR_PADS_LTC3888-1
MFR_COMMON
0x80 IC-specific status.
R/W Byte
R Word
R Byte
Y
N
N
N
N
Reg
Reg
Reg
Reg
0xE5 State of selected LTC3888-1 pads.
0xEF ADI-generic device status reporting.
0xB6 Manufacturer-specific information
0x03 Clear all set fault bits.
MFR_INFO
R Word
Send Byte
CLEAR_FAULTS
Refer to Figure 2 for a graphical depiction of these register contents and their relationships. Refer to Power Stage Selection and Interface in the
Applications Information section for details of special status reporting related to external power stages that is supported by the LTC3888-1.
STATUS_BYTE
The STATUS_BYTE command returns a one-byte summary of the most critical faults.
STATUS_BYTE Message Contents:
BIT
7*
6
STATUS BIT NAME
MEANING
BUSY
OFF
A fault was declared because the device was unable to respond.
This bit is set if the channel is not providing power to its output, regardless of the reason, including simply not
being enabled.
5
4
3
2
1
0
VOUT_OV
IOUT_OC
VIN_UV
An output overvoltage or power stage fault has occurred. Also set if open V
An output overcurrent fault has occurred.
+ is detected.
SENSE
Not supported (device returns 0).
TEMPERATURE
CML
A temperature fault or warning has occurred. (LTC3888-1 only)
A communications, memory or logic fault has occurred.
NONE OF THE ABOVE A fault Not listed in bits[7:1] has occurred.
*ALERT can be asserted if this bit is set. It may be cleared by writing a 1 to that bit position in the STATUS_BYTE, in lieu of a CLEAR_FAULTS command.
This command has one data byte.
Rev. 0
90
For more information www.analog.com
LTC3888-1
(Status Reporting)
PMBus COMMAND DETAILS
STATUS_WORD
The STATUS_WORD command returns a two-byte summary of the channel's fault condition. The low byte of the
STATUS_WORD is the same as the STATUS_BYTE command.
STATUS_WORD High Byte Message Contents:
BIT
15
14
13
12
11
10
9
STATUS BIT NAME
VOUT
MEANING
An output voltage fault or warning has occurred. Also set if a power stage fault or open V
+ is detected.
SENSE
IOUT
An output current fault or warning has occurred. Also set if a power stage fault is detected.
An input voltage fault or warning has occurred.
A fault or warning specific to the LTC3888-1 has occurred.
The POWER_GOOD state is false if this bit is set.
Not supported (LTC3888-1 returns 0).
INPUT
MFR_SPECIFIC
POWER_GOOD#
FANS
OTHER
Not supported (LTC3888-1 returns 0).
8
UNKNOWN
Not supported (LTC3888-1 returns 0).
This command has two data bytes.
STATUS_VOUT
The STATUS_VOUT command returns one byte of V
status information. Refer to Table 8 for additional details.
OUT
STATUS_VOUT Message Contents:
BIT
7
MEANING
V
OUT
V
OUT
V
OUT
V
OUT
overvoltage fault, power stage fault, or open V
overvoltage warning.
+ input.
SENSE
6
5
undervoltage warning.
4
undervoltage fault or open V
+ input.
SENSE
3
VOUT_MAX warning.
TON_MAX fault.
2
1
Not supported by the LTC3888-1 (returns 0).
Not supported by the LTC3888-1 (returns 0).
0
ALERT can be asserted if any of bits[7:2] are set. These may be cleared by writing a 1 to their bit position in STATUS_VOUT, in lieu of a CLEAR_FAULTS
command.
This command has one data byte.
Rev. 0
91
For more information www.analog.com
LTC3888-1
(Status Reporting)
PMBus COMMAND DETAILS
STATUS_IOUT
The STATUS_IOUT command returns one byte of I
status information. Refer to Table 8 for additional details.
OUT
STATUS_IOUT Message Contents:
BIT
7
MEANING
overcurrent fault.
I
OUT
6
Not supported (LTC3888-1 returns 0).
I overcurrent warning.
OUT
5
4
Not supported (LTC3888-1 returns 0).
3
Power stage fault detected (differs from standard PMBus meaning).
Not supported (LTC3888-1 returns 0).
2:0
ALERT can be asserted if any supported bits are set. Any supported bit may be cleared by writing a 1 to that bit position in STATUS_IOUT, in lieu of a
CLEAR_FAULTS command.
This command has one data byte.
STATUS_INPUT
The STATUS_INPUT command returns one byte of V status information.
IN
STATUS_INPUT Message Contents:
BIT
7
MEANING
overvoltage fault.
V
IN
6
Not supported (LTC3888-1returns 0).
V undervoltage warning.
IN
5
4
Not supported (LTC3888-1 returns 0).
3
Unit off for insufficient V .
IN
2:0
Not supported (LTC3888-1 returns 0).
ALERT can be asserted if bit 7 is set. Bit 7 may be cleared by writing it to a 1, in lieu of a CLEAR_FAULTS command.
This command has one data byte.
STATUS_TEMPERATURE
The STATUS_TEMPERATURE command returns one byte of sensed external temperature status information.
STATUS_TEMPERATURE Message Contents:
BIT
7
MEANING
External overtemperature fault.
External overtemperature warning.
Not supported (LTC3888-1 returns 0).
Not supported (LTC3888-1 returns 0).
Not supported (LTC3888-1 returns 0).
6
5
4
3:0
ALERT can be asserted if any supported bits are set. Any supported bit may be cleared by writing a 1 to that bit position in STATUS_TEMPERATURE, in
lieu of a CLEAR_FAULTS command.
This command has one data byte.
Rev. 0
92
For more information www.analog.com
LTC3888-1
(Status Reporting)
PMBus COMMAND DETAILS
STATUS_CML
The STATUS_CML command returns one byte of status information on received commands, internal memory and logic.
STATUS_CML Message Contents:
BIT
7
MEANING
Invalid or unsupported command received.
Invalid or unsupported data received.
Packet error check failed.
6
5
4
Memory fault detected.
3
Processor fault detected.
2
Reserved (LTC3888-1 returns 0).
Other communication fault.
Other memory or logic fault.
1
0
ALERT can be asserted if any supported bits are set. Any supported bit may be cleared by writing a 1 to that bit position in STATUS_CML, in lieu of a
CLEAR_FAULTS command.
This command has one data byte.
STATUS_MFR_SPECIFIC
The STATUS_MFR_SPECIFIC command returns one byte with device-specific status information.
STATUS_MFR_SPECIFIC Message Contents:
BIT
7
MEANING
Internal temperature fault (>160°C).
Internal temperature warning (>130°C).
EEPROM CRC error.
6
5
4
Internal PLL unlocked.
Fault log present.
3
2
Not supported (LTC3888-1 returns 0).
Output short cycled.
1
0
FAULT low.
If any supported bits are set, the MFR bit in the STATUS_WORD will be set and ALERT may be asserted. Any supported bit may be cleared by writing a 1 to
that bit position in STATUS_MFR_SPECIFIC, in lieu of a CLEAR_FAULTS command.
This command has one data byte.
Rev. 0
93
For more information www.analog.com
LTC3888-1
(Status Reporting)
PMBus COMMAND DETAILS
MFR_PADS_LTC3888-1
The MFR_PADS_LTC3888-1 command provides status of the LTC3888-1 digital I/O and control pins, in addition to
general output voltage conditions.
MFR_PADS_LTC3882 Message Contents:
BIT
15
14
13:12
11
10
9
MEANING
Channel 1 power stages all report ready.
Channel 0 power stages all report ready.
Not supported (LTC3888-1 returns 0).
ADC results for READ_TEMPERATURE_1 may be invalid.
SYNC output disabled externally.
Channel 1 POWER_GOOD.
Channel 0 POWER_GOOD.
LTC3888-1 forcing RUN1 low.
LTC3888-1 forcing RUN0 low.
RUN1 pin state.
8
7
6
5
4
RUN0 pin state.
3
LTC3888-1 forcing FAULT1 low.
LTC3888-1 forcing FAULT0 low.
FAULT1 pin state.
2
1
0
FAULT0 pin state.
This read-only command has two data bytes.
MFR_COMMON
The MFR_COMMON command contains status bits that are common to multiple ADI PMBus products.
MFR_COMMON Message Contents:
BIT
7
MEANING
LTC3888-1 not forcing ALERT low.
LTC3888-1 not BUSY.
6
5
LTC3888-1 calculations not pending.
LTC3888-1 output not in transition.
LTC3888-1 EEPROM initialized.
Not supported (LTC3888-1 returns 0).
SHARE_CLK timeout.
4
3
2
1
0
Not supported (LTC3888-1 returns 0).
This read-only command has one data byte.
Rev. 0
94
For more information www.analog.com
LTC3888-1
(Status Reporting)
PMBus COMMAND DETAILS
MFR_INFO
The MFR_INFO command contains status bits providing manufacturer-specific information.
MFR_INFO Message Contents:
BIT
15:6
5
MEANING
Reserved.
EEPROM ECC Status:
0: Corrections have been made in the EEPROM user space.
1: No corrections have been made in the EEPROM user space.
4:0
Reserved.
This read-only command has two data bytes.
CLEAR_FAULTS
The CLEAR_FAULTS command clears any fault bits that have been set and deasserts (releases) the ALERT pin. This
command clears all fault bits in all status commands simultaneously.
CLEAR_FAULTS does not cause a channel that has latched off for a fault condition to restart. Channels that are latched
off for a fault condition are restarted when the output is commanded to turn off and then on through the OPERATION
command or RUN pins, or IC supply power is cycled.
If a fault is still present when CLEAR_FAULTS is commanded, that fault bit will immediately be set again and ALERT
asserted low if not masked.
This write-only command has no data bytes.
Rev. 0
95
For more information www.analog.com
LTC3888-1
(Telemetry)
PMBus COMMAND DETAILS
TELEMETRY
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
READ_VIN
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
0x88 Measured V .
R Word
R Word
N
N
L11
L11
V
V
IN
MFR_VIN_PEAK
0xDE Maximum V measurement since last
IN
MFR_CLEAR_PEAKS.
READ_VOUT
0x8B Measured V
0xDD Maximum V
.
R Word
R Word
Y
Y
L16
L16
V
V
OUT
MFR_VOUT_PEAK
measurement since last
OUT
MFR_CLEAR_PEAKS.
READ_IOUT
0x8C Measured master channel I
0xD7 Maximum master channel I
.
R Word
R Word
Y
Y
L11
L11
A
A
OUT
MFR_IOUT_PEAK
measurement
OUT
since last MFR_CLEAR_PEAKS.
MFR_TOTAL_IOUT
0xE1 Measured total I for each rail defined by
R Word
R Block
R Word
Y
N
L11
L11
A
A
OUT
MFR_PWM_CONFIG_LTC3888-1.
MFR_READ_ALL_IOUT
0xE4 Measured I
for each individual PWM
OUT
phase.
READ_TEMPERATURE_1
0x8D Measured external temperature.
Y
Y
L11
L11
°C
°C
MFR_TEMPERATURE_1_PEAK
0xDF Maximum external temperature measurement R Word
since last MFR_CLEAR_PEAKS.
READ_TEMPERATURE_2
0x8E Measured internal temperature.
R Word
N
N
L11
L11
°C
°C
MFR_TEMPERATURE_2_PEAK
0xF4 Maximum internal temperature measurement R Word
since last MFR_CLEAR_PEAKS.
READ_FREQUENCY
0x95 Measured PWM input clock frequency.
0xE3 Clear all peak values.
R Word
Y
N
L11
kHz
MFR_CLEAR_PEAKS
Send Byte
Related commands: IOUT_CAL_GAIN
READ_VIN
The READ_VIN command returns the input voltage measured between V and GND in volts.
IN
This read-only command has two data bytes in Linear_5s_11s format.
Rev. 0
96
For more information www.analog.com
LTC3888-1
(Telemetry)
PMBus COMMAND DETAILS
MFR_VIN_PEAK
The MFR_VIN_PEAK command reports the highest voltage, in volts, measured for READ_VIN. This peak value can be
reset by a MFR_CLEAR_PEAKS command.
This read-only command has two data bytes in Linear_5s_11s format.
READ_VOUT
The READ_VOUT command returns the output voltage measured at the V
This read-only command has two data bytes in Linear_16u format.
pins in volts.
SENSE
MFR_VOUT_PEAK
The MFR_VOUT_PEAK command reports the highest voltage, in volts, measured for READ_VOUT. This peak value can
be reset by a MFR_CLEAR_PEAKS command.
This read-only command has two data bytes in Linear_16u format.
READ_IOUT
The READ_IOUT command returns the master channel output current in amperes. This value is computed by applying
IOUT_CAL_GAIN to the voltage measured between I
and IREF.
SENSE
This read-only command has two data bytes in Linear_5s_11s format.
MFR_IOUT_PEAK
The MFR_IOUT_PEAK command reports the highest current, in amperes, calculated for READ_IOUT. This peak value
can be reset by a MFR_CLEAR_PEAKS command.
This read-only command has two data bytes in Linear_5s_11s format.
MFR_TOTAL_IOUT
The MFR_TOTAL_IOUT command reports the total output current for all on-chip phases of the entire rail as defined by
MFR_PWM_CONFIG_LTC3888-1. The value is calculated from the sum of the individual phase I
ADC conversions.
OUT
If bit 6 of MFR_PWM_CONFIG_LTC3888-1 is set, PWM2-PWM7 report 0A regardless of the actual output load. Sums
are always reported by page, even if the master channel has been defined as a slave (see bit 4 of MFR_PWM_MODE_
LTC3888-1). Sums across IC boundaries are not supported.
This read-only command has two data bytes in Linear_5s_11s format.
MFR_READ_ALL_IOUT
The MFR_READ_ALL_IOUT command reports the output current for each of the eight phases on the LTC3888-1 using
block read protocol. Monitor ADC results are presented in order from PWM0 to PWM7. If bit 6 of MFR_PWM_CONFIG_
LTC3888-1 is set, PWM2-PWM7 report 0A.
This read-only command uses block protocol with 17 bytes of data delivering I
results in Linear_5s_11s format.
OUT
Rev. 0
97
For more information www.analog.com
LTC3888-1
(Telemetry)
PMBus COMMAND DETAILS
READ_TEMPERATURE_1
The READ_TEMPERATURE_1 command returns the temperature, in degrees Celsius, of external power stages con-
nected to the device TSNS pin(s).
This read-only command has two data bytes in Linear_5s_11s format.
MFR_TEMPERATURE_1_PEAK
The MFR_TEMPERATURE_1_PEAK command reports the highest temperature, in degrees Celsius, calculated for
READ_TEMPERATURE_1. This peak value can be reset by a MFR_CLEAR_PEAKS command.
This read-only command has two data bytes in Linear_5s_11s format.
READ_TEMPERATURE_2
The READ_TEMPERATURE_2 command returns the LTC3888-1 internal temperature in degrees Celsius.
This read-only command has two data bytes in Linear_5s_11s format.
MFR_TEMPERATURE_2_PEAK
The MFR_TEMPERATURE_2_PEAK command reports the highest temperature, in degrees Celsius, calculated for
READ_TEMPERATURE_2. This peak value can be reset by a MFR_CLEAR_PEAKS command.
This read-only command has two data bytes in Linear_5s_11s format.
READ_FREQUENCY
The READ_FREQUENCY command returns the switching frequency supplied to the internal PLL in kilohertz, whether
generated internally or provided by external clock on the SYNC pin.
This read-only command has two data bytes in Linear_5s_11s format.
MFR_CLEAR_PEAKS
The MFR_CLEAR_PEAKS command resets all stored _PEAK values. The LTC3888-1 determines new peak values after
this command is received.
This write-only command has no data bytes.
Rev. 0
98
For more information www.analog.com
LTC3888-1
(Fault Response and Communication)
PMBus COMMAND DETAILS
FAULT RESPONSE AND COMMUNICATION
CMD
DATA
DEFAULT
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
VALUE
0x80
0x80
0xB8
0x00
0xB8
0xC0
0xB8
l
VIN_OV_FAULT_RESPONSE
VOUT_OV_FAULT_RESPONSE
VOUT_UV_FAULT_RESPONSE
IOUT_OC_FAULT_RESPONSE
OT_FAULT_RESPONSE
0x56
0x41
0x45
V
V
V
overvoltage fault response.
R/W Byte
R Byte
Y
Y
Y
Y
Y
N
Y
Reg
Reg
Reg
Reg
Reg
Reg
Reg
IN
l
l
l
l
l
l
overvoltage fault response.
undervoltage fault response.
OUT
OUT
R/W Byte
R/W Byte
R/W Byte
R/W Byte
R/W Byte
0x47 Output overcurrent fault response.
0x50 External overtemperature fault response.
0xD6 Internal overtemperature fault response.
MFR_OT_FAULT_RESPONSE
TON_MAX_FAULT_RESPONSE
0x63 Fault response when
TON_MAX_FAULT_LIMIT is exceeded.
l
l
MFR_RETRY_DELAY
SMBALERT_MASK
0xDB Minimum time before retry after a fault.
R/W Word
Block R/W
N
Y
L11
Reg
ms
350ms
0xFABC
0x1B Mask ALERT Activity.
See
Following
Details
l
l
MFR_FAULT_PROPAGATE
MFR_FAULT_RESPONSE
0xD2 Configure fault propagation via FAULT pins.
R/W Word
Y
Y
Reg
Reg
0x6993
0xC0
0xD5 PWM response when FAULT pin is low due to R/W Byte
external fault.
MFR_FAULT_LOG
0xEE Read fault log data.
R Block
N
N
Reg
MFR_FAULT_LOG_CLEAR
0xEC Clear existing EEPROM fault log.
Send Byte
Related commands: STATUS_BYTE, STATUS_WORD, MFR_PADS_LTC3888-1, MFR_RESTART_DELAY, MFR_FAULT_LOG_STORE, CLEAR_FAULTS
These commands detail programmable device responses for detected faults beyond the hardware-level actions
described in the Operation section. LTC3888-1 hardware-level fault responses cannot be modified. PMBus warning
event responses are listed under _WARN_LIMIT command details.
VIN_OV_FAULT_RESPONSE
The VIN_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an input over-
voltage fault. The format for this command is given in Table 14. The device also:
• Sets the INPUT Bit in the STATUS_WORD
• Sets the V Overvoltage Fault Bit in the STATUS_INPUT Command
IN
• Notifies the Host by Asserting ALERT, Unless Masked
This command has one data byte.
Rev. 0
99
For more information www.analog.com
LTC3888-1
(Fault Response and Communication)
PMBus COMMAND DETAILS
VOUT_OV_FAULT_RESPONSE
The VOUT_OV_FAULT_RESPONSE command reports the actions the device will take in response to an output over-
voltage fault, power stage fault or qualified UVLO (LTC3888-1 only) or qualified VDR supply UV during operation. The
format for this command is given in Table 13. The device also:
• Sets the VOUT_OV Bit in the STATUS_BYTE
• Sets the VOUT Bit in the STATUS_WORD
• Sets the V
Overvoltage Fault Bit in the STATUS_VOUT Command
OUT
• Notifies the Host by Asserting ALERT, Unless Masked
This read-only command has one data byte.
VOUT_UV_FAULT_RESPONSE
The VOUT_UV_FAULT_RESPONSE command instructs the device on what action to take in response to an output
undervoltage fault. The format for this command is given in Table 13. The device also:
• Sets the VOUT Bit in the STATUS_WORD
• Sets the V
Undervoltage Fault Bit in the STATUS_VOUT Command,
OUT
• Notifies the Host by Asserting ALERT, Unless Masked
This command has one data byte.
Table 13. Data Byte Contents for VOUT_OV_FAULT_RESPONSE and VOUT_UV_FAULT_RESPONSE
BITS
DESCRIPTION
VALUE
MEANING
[7:6]
For all values of bits [7:6], the LTC3888-1:
00
The LTC3888-1 continues to operate indefinitely with the
normal hardware response described in the Operation
section.
• Sets the corresponding fault bits in the status commands.
• Notifies the host by asserting ALERT, unless masked.
01
The LTC3888-1 continues operating with the normal
hardware response for the delay time specified by bits
[2:0]. If the fault is continuously present for the entire delay,
the unit then disables the output and responds according to
the retry setting in bits [5:3].
The fault, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command.
• The corresponding STATUS_VOUT bit is written to a one.
• The output is commanded off, then on, by the RUN pin or
OPERATION command.
• The device receives a RESTORE_USER_ALL command.
• The device receives an MFR_RESET command.
• IC supply power is cycled.
10
11
The LTC3888-1 immediately disables the output and
responds according to the retry setting in bits [5:3].
Not supported. Writing this value will generate a CML fault.
[5:3]
[2:0]
Retry setting.
000-110 The LTC3888-1 does not attempt to restart. The output
remains disabled until the fault is cleared, the device is
commanded off and then on, or IC supply power is cycled.
111
The LTC3888-1 attempts to restart continuously without
limitation with an interval set by MFR_RETRY_DELAY. This
response persists until the unit is commanded off, or IC
supply power is removed, or another fault response forces
shutdown without retry.
Delay time.
xxx
Response delay time in 10µs increments. This delay
time determines how long the fault may have to persist
before the controller is disabled, depending on bits [7:6].
Hardware-level response, if any, will occur during this delay.
Rev. 0
100
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LTC3888-1
(Fault Response and Communication)
PMBus COMMAND DETAILS
IOUT_OC_FAULT_RESPONSE
The IOUT_OC_FAULT_RESPONSE command instructs the device on what action to take in response to an output
overcurrent fault. The device also:
• Sets the IOUT_OC Bit in the STATUS_BYTE
• Sets the IOUT Bit in the STATUS_WORD
• Sets the I
Overcurrent Fault Bit in the STATUS_IOUT Command
OUT
• Notifies the Host by Asserting ALERT, Unless Masked
Output overcurrent faults are ignored during turn-on and turn-off output transitions.
Data Byte Contents for IOUT_OC_FAULT_RESPONSE:
BITS
DESCRIPTION
VALUE
MEANING
[7:6]
For all values of bits [7:6], the LTC3888-1:
00
The LTC3888-1 continues to operate indefinitely with the
normal hardware response described in the Operation
section.
• Sets the corresponding fault bits in the status commands.
• Notifies the host by asserting ALERT, unless masked.
01
10
Not supported. Writing this value will generate a CML fault.
The fault, once set, is cleared only when one or more of the
following events occurs:
The LTC3888-1 continues operating with the normal
hardware response for the delay time specified by bits
[2:0]. If the fault is continuously present for the entire delay,
the unit then disables the output and responds according to
the retry setting in bits [5:3].
• The device receives a CLEAR_FAULTS command.
• The corresponding STATUS_IOUT bit is written to a one.
• The output is commanded off, then on, by the RUN pin or
OPERATION command.
• The device receives a RESTORE_USER_ALL command.
• The device receives an MFR_RESET command.
• IC supply power is cycled.
11
The LTC3888-1 immediately disables the output and
responds according to the retry setting in bits [5:3].
[5:3]
[2:0]
Retry setting.
000-110 The LTC3888-1 does not attempt to restart. The output
remains disabled until the fault is cleared, the device is
commanded off and then on, or IC supply power is cycled.
111
The LTC3888-1 attempts to restart continuously without
limitation with an interval set by MFR_RETRY_DELAY.
This response persists until the unit is commanded off, IC
supply power is removed, or another fault response forces
shutdown without retry.
Delay time.
xxx
Response delay time in 16ms increments. This delay time
determines how long the fault may have to persist before
the controller is disabled, depending on bits [7:6]. These
bits always return zero if bits [7:6].
This command has one data byte.
Rev. 0
101
For more information www.analog.com
LTC3888-1
(Fault Response and Communication)
PMBus COMMAND DETAILS
OT_FAULT_RESPONSE
The OT_FAULT_RESPONSE command instructs the device on what action to take in response to an external overtem-
perature fault. The format for this command is given in Table 14. The device also:
• Sets the TEMPERATURE Bit in the STATUS_BYTE
• Sets the Overtemperature Fault Bit in the STATUS_TEMPERATURE Command
• Notifies the Host by Asserting ALERT, Unless Masked
This command has one data byte.
MFR_OT_FAULT_RESPONSE
The MFR_OT_FAULT_RESPONSE command instructs the device on what action to take in response to an internal
overtemperature fault (150°C to 160°C). The device also:
• Sets the MFR Bit in the STATUS_WORD
• Sets the Overtemperature Fault Bit in the STATUS_MFR_SPECIFIC Command
• Notifies the Host by Asserting ALERT, Unless Masked
Supported Values:
VALUE
0xC0
MEANING
The LTC3888-1 continues to operate indefinitely with the normal hardware response described in the Operation section.
0x80
The LTC3888-1 shuts down immediately and does not attempt to restart. The output remains disabled until the fault is cleared and the unit
is commanded off and then on, or IC supply power is cycled.
Programming an unsupported MFR_OT_FAULT_RESPONSE value will generate a CML fault and the command will be
ignored.
This command has one data byte.
TON_MAX_FAULT_RESPONSE
The TON_MAX_FAULT_RESPONSE command instructs the device on what action to take in response to a TON_MAX
fault. The format for this command is given in Table 14. The device also:
• Sets the VOUT Bit in the STATUS_WORD
• Sets the TON_MAX Fault Bit in the STATUS_VOUT Command
• Notifies the Host by Asserting ALERT, Unless Masked
This command has one data byte.
Rev. 0
102
For more information www.analog.com
LTC3888-1
(Fault Response and Communication)
Table 14. Data Byte Contents for the Following _FAULT_RESPONSE Commands: VIN_OV, OT and TON_MAX
PMBus COMMAND DETAILS
BITS
DESCRIPTION
VALUE
00
MEANING
[7:6]
For all values of bits [7:6], the LTC3888-1:
The LTC3888-1 continues operating without interruption.
Not supported. Writing this value will generate a CML fault.
• Sets the corresponding fault bits in the status commands.
• Notifies the host by asserting ALERT, unless masked.
01
10
The LTC3888-1 shuts down immediately (disables the
output) and responds according to the retry setting in bits
[5:3].
The fault, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command.
• The corresponding fault bit is written to a one.
• The output is commanded off, then on, by the RUN pin or
OPERATION command.
11
Not supported. Writing this value will generate a CML fault.
• The device receives a RESTORE_USER_ALL command.
• The device receives an MFR_RESET command.
• IC supply power is cycled.
[5:3]
[2:0]
Retry setting.
000-110 The LTC3888-1 does not attempt to restart. The output
remains disabled until the fault is cleared, the device is
commanded off and then on, or IC supply power is cycled.
111
The LTC3888-1 attempts to restart continuously without
limitation with an interval set by MFR_RETRY_DELAY.
This response persists until the unit is commanded off, IC
supply power is removed, or another fault response forces
shutdown without retry.
Delay time.
xxx
Not supported. Values ignored.
MFR_RETRY_DELAY
The MFR_RETRY_DELAY command sets the time, in milliseconds, between restart attempts for all retry fault responses.
Retry delay starts once the fault is no longer detected by the LTC3888-1 or its FAULT pin is externally released. Legal
values run from 120ms to 32.7 seconds.
This command has two data bytes in Linear_5s_11s format.
SMBALERT_MASK
The SMBALERT_MASK command can be used to prevent a particular status bit or bits from pulling ALERT low as
they are asserted.
Figure 50 shows an example of the Write Word format used to set an ALERT mask, in this case without PEC. The bits in
the mask byte align with bits in the specified status register. For example, if the STATUS_TEMPERATURE command code
is sent in the first data byte, and the mask byte contains 0x40, then a subsequent External Overtemperature Warning
would still set bit 6 of STATUS_TEMPERATURE but not assert ALERT. All other supported STATUS_TEMPERATURE
bits would continue to assert ALERT if set.
Figure 51 shows an example of the Block Write – Block Read Process Call protocol used to read back the present state
of the ALERT mask for any supported status register, again without PEC.
SMBALERT_MASK cannot be applied to STATUS_BYTE, STATUS_WORD, MFR_COMMON or MFR_PADS_LTC3888-1.
Factory default masking for applicable status registers is shown below. Providing an unsupported command code to
SMBALERT_MASK will generate a CML for Invalid/Unsupported Data.
Rev. 0
103
For more information www.analog.com
LTC3888-1
(Fault Response and Communication)
PMBus COMMAND DETAILS
SMBALERT_MASK Default Setting: (Refer Also to Figure 2)
STATUS RESISTER
STATUS_VOUT
ALERT Mask Value MASKED BITS
0x00
0x00
0x00
0x00
0x00
0x11
None
None
None
None
None
STATUS_IOUT
STATUS_TEMPERATURE
STATUS_CML
STATUS_INPUT
STATUS_MFR_SPECIFIC
Bit 4 (internal PLL unlocked), bit 0 (FAULT low)
ꢁ
ꢓ
ꢁ
ꢁ
ꢔ
ꢁ
ꢔ
ꢁ
ꢔ
ꢁ
ꢁ
ꢂꢃꢄꢅꢆ
ꢄꢇꢇRꢆꢂꢂ
ꢂꢈꢉꢄꢃꢆRꢊꢋꢈꢄꢂꢌ
ꢍꢎꢈꢈꢄꢏꢇ ꢍꢎꢇꢆ
ꢂꢊꢄꢊꢐꢂꢋꢑ
ꢍꢎꢈꢈꢄꢏꢇ ꢍꢎꢇꢆ
ꢂ
ꢒ
ꢄ
ꢄ
ꢄ
ꢈꢄꢂꢌ ꢉꢕꢊꢆ
ꢄ
ꢀ
ꢖꢔꢔꢔꢁꢗ ꢘꢙ0
Figure 50. Example of Setting SMBALERT_MASK
ꢑ
ꢔ
ꢑ
ꢑ
ꢕ
ꢑ
ꢕ
ꢑ
ꢕ
ꢑ
ꢀꢁꢂꢃꢄ
ꢂꢅꢅRꢄꢀꢀ
ꢀꢆꢇꢂꢁꢄRꢈꢉꢆꢂꢀꢊ
ꢋꢌꢆꢆꢂꢍꢅ ꢋꢌꢅꢄ
ꢇꢁꢌꢋꢊ ꢋꢌꢎꢍꢈ
ꢏꢐ ꢑꢒ
ꢀꢈꢂꢈꢎꢀꢉꢖ
ꢋꢌꢆꢆꢂꢍꢅ ꢋꢌꢅꢄ
ꢀ
ꢓ
ꢂ
ꢂ
ꢂ
ꢂ
ꢗ
ꢑ
ꢔ
ꢑ
ꢑ
ꢕ
ꢑ
ꢕ
ꢑ
ꢑ
ꢀꢁꢂꢃꢄ
ꢂꢅꢅRꢄꢀꢀ
ꢇꢁꢌꢋꢊ ꢋꢌꢎꢍꢈ
ꢏꢐ ꢑꢒ
ꢀꢘ
R
ꢂ
ꢂ
ꢆꢂꢀꢊ ꢇꢞꢈꢄ
ꢍꢂ
ꢙ
ꢚꢕꢕꢕꢑꢛ ꢜꢝꢑ
Figure 51. Example of Reading SMBALERT_MASK
MFR_FAULT_PROPAGATE
The MFR_FAULT_PROPAGATE command determines internal events that cause FAULT to be asserted. Setting a bit in
this register allows the specified condition to also assert the FAULT output for that channel. FAULT is not asserted by
a fault, even if set to propagate, if that FAULT_RESPONSE is set to Ignore. The state of SMBLALERT_MASK does not
affect fault propagation.
Supported Values:
BIT
15
14
13
12
11
10*
9*
8
PROPAGATED CONDITION
(Reserved).
V
OUT
short cycled (automatically deasserted 120ms after V
is fully OFF).
OUT
TON_MAX_FAULT_LIMIT exceeded.
VOUT_UV_FAULT_LIMIT exceeded (unfiltered, aka VOUT_UV_UF).
MFR_OT_FAULT_LIMIT exceeded.
Channel 1 POWER_GOOD false.
Channel 0 POWER_GOOD false.
(Reserved).
Rev. 0
104
For more information www.analog.com
LTC3888-1
(Fault Response and Communication)
PMBus COMMAND DETAILS
BIT
PROPAGATED CONDITION
OT_FAULT_LIMIT exceeded.
(Reserved).
7
6
5
(Reserved).
4
VIN_OV_FAULT_LIMIT exceeded.
(Reserved).
3
2
IOUT_OC_FAULT_LIMIT exceeded.
VOUT_UV_FAULT_LIMIT exceeded
1
0
VOUT_OV_FAULT_LIMIT exceeded, power stage fault or UV, or VDR monitor UV
*If this bit is set, MFR_FAULT_RESPONSE should be set to ignore (0x00), otherwise the rail might not start.
This command has two data bytes.
MFR_FAULT_RESPONSE
The MFR_FAULT_RESPONSE command instructs the device on what action to take in response to a FAULT pin being
pulled low externally.
Supported Values:
VALUE
0xC0
MEANING
Related rail is immediately disabled.
Input ignored, PWM operation continues without interruption.
0x00
When a FAULT pin is pulled low externally, the device also:
• Sets the MFR_SPECIFIC Bit in the STATUS_WORD
• Sets Bit 0 in the STATUS_MFR_SPECIFIC Command to Indicate FAULT Is or Has Been Pulled Low
• Notifies the Host by Asserting ALERT, Unless Masked
This command has one data byte.
MFR_FAULT_LOG
The MFR_FAULT_LOG command allows the contents of the fault log to be read. This log is created with MFR_FAULT_
LOG_STORE or at the first fault occurrence after an MFR_FAULT_LOG_CLEAR. If a fault occurs within the first second
after applying power, some earlier pages in the log may not contain valid data.
This read-only command uses block protocol with 147 bytes of data requiring an estimated data transfer time of3.4ms
at 400kHz. The t
parameter is extended when this command is executed and a fault log is present.
TIMEOUT
Refer to Fault Log Details in the Operation section for complete information on using the LTC3888-1 fault log.
MFR_FAULT_LOG_CLEAR
The MFR_FAULT_LOG_CLEAR command erases all stored fault log values. After a clear is issued, up to 8ms may be
required to clear related bit 3 in STATUS_MFR_SPECIFIC.
This write-only command has no data bytes.
Rev. 0
105
For more information www.analog.com
LTC3888-1
(EEPROM User Access)
PMBus COMMAND DETAILS
EEPROM USER ACCESS
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
STORE_USER_ALL
RESTORE_USER_ALL
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
0x15 Store entire operating memory in EEPROM.
Send Byte
Send Byte
N
N
0x16 Restore entire operating memory from
EEPROM.
MFR_COMPARE_USER_ALL
MFR_FAULT_LOG_STORE
0xF0 Compare operating memory with EEPROM
contents.
Send Byte
N
N
0xEA Force capture of fault log in RAM and transfer Send Byte
to EEPROM.
MFR_EE_UNLOCK
MFR_EE_ERASE
MFR_EE_DATA
USER_DATA_00
USER_DATA_01
USER_DATA_02
USER_DATA_03
0xBD (contact the factory)
0xBE (contact the factory)
0xBF (contact the factory)
l
0xB0 EEPROM word reserved for LTpowerPlay.
0xB1 EEPROM word reserved for LTpowerPlay.
0xB2 EEPROM word reserved for OEM use.
R/W Word
R/W Word
R/W Word
R/W Word
N
Y
N
Y
Reg
Reg
Reg
Reg
l
l
l
0xB3 EEPROM word available for general data
storage.
0x0000
0x0000
l
USER_DATA_04
0xB4 EEPROM word available for general data
storage.
R/W Word
N
Reg
Related commands: MFR_CONFIG_ALL
Note that if the LTC3888-1 die temperature exceeds 130°C, execution of any command in the above table except
RESTORE_USER_ALL and MFR_FAULT_LOG_STORE will be disabled until the IC temperature drops below 125°C.
RESTORE_USER_ALL is executed immediately, and MFR_FAULT_LOG_STORE to EEPROM is executed after the IC
temperature drops below 125°C. Using any command that writes data to the EEPROM is strongly discouraged if bit 6
of STATUS_MFR_ SPECIFIC is set, indicating the internal die temperature is above 85°C. Data retention of 10 years is
not guaranteed if the EEPROM is written above a junction temperature of 85°C.
STORE_USER_ALL
The STORE_USER_ALL command instructs the PMBus device to copy the entire contents of the operating memory to
internal EEPROM PMBus configuration space.
This write-only command has no data bytes.
RESTORE_USER_ALL
The RESTORE_USER_ALL command instructs the PMBus device to copy the entire contents of the internal EEPROM to
matching locations in operating memory. The values in operating memory are overwritten by the values retrieved from
EEPROM. Both master channels should be turned off prior to issuing this command. The LTC3888-1 ensures all PWM
channels are off, loads the operating memory from internal EEPROM, clears all faults, reads the resistor configuration
pins, and then performs a soft-start of any enabled master channels.
This write-only command has no data bytes.
Rev. 0
106
For more information www.analog.com
LTC3888-1
(EEPROM User Access/Unit Identification)
PMBus COMMAND DETAILS
MFR_COMPARE_USER_ALL
The MFR_COMPARE_USER_ALL command instructs the LTC3888-1 to compare current operating memory with the
contents of the internal EEPROM. If the compared memories differ, a CML fault is generated.
This write-only command has no data bytes.
MFR_FAULT_LOG_STORE
The MFR_FAULT_LOG_STORE command forces a data log to be written to RAM (at any temperature) and transferred to
internal EEPROM as if a fault event had occurrred. Execution of this command will lock the fault log until a subsequent
MFR_FAULT_LOG_CLEAR is received. Die temperature limitations apply to the EEPROM write, as noted above. This
command will generate a CML fault if the Enable Fault Logging bit is clear in MFR_CONFIG_ALL.
This write-only command has no data bytes.
MFR_EE_xxxx
The MFR_EE_xxxx commands facilitate bulk programming of the LTC3888-1 internal EEPROM. Contact the factory for details.
USER_DATA_0x
The USER_DATA_0x commands provide uncommitted EEPROM locations that may be applied as system scratchpad
space. USER_DATA_00 and USER_DATA_01 should not be modified when using the LTpowerPlay GUI. Some contract
manufacturers also reserve use of USER_DATA_02 for their own inventory control.
UNIT IDENTIFICATION
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
MFR_ID
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
0x99 Manufacturer identification.
0xAD LTC3888-1 model number.
0xE7 Unique manufacturer product ID
R String
R String
R Word
N
N
N
ASC
ASC
REG
LTC
IC_DEVICE_ID
MFR_SPECIAL_ID
LTC3888-1
0x488x
The following three read-only commands use block format.
MFR_ID
The MFR_ID command returns the manufacturer ID of the LTC3888-1 using 8-bit ASCII characters.
IC_DEVICE_ID
The IC_DEVICE_ID command returns the ADI IC part number using 8-bit ASCII characters.
MFR_SPECIAL_ID
The MFR_SPECIAL_ID command returns a unique binary product code for the device. X is adjustable by the maufacturer.
This read-only command has two data bytes.
Rev. 0
107
For more information www.analog.com
LTC3888-1
PACKAGE DESCRIPTION
UHG Package
52-Lead Plastic QFN (5mm × 8mm)
ꢘReꢪeꢫeꢬꢭe ꢔꢄꢌ ꢇꢉꢋ ꢮ 0ꢀꢕ0ꢝꢕꢁꢀꢀ0 Rev ꢦꢚ
ꢙ.ꢛ0 Rꢅꢍ
ꢛꢗ
ꢖꢜ
0.ꢜ0 ±0.0ꢀ
ꢛꢛ
ꢖꢙ
ꢀ.ꢀ0 ±0.0ꢀ
ꢛ.ꢁ0 ±0.0ꢀ
ꢗ.ꢖ0 Rꢅꢍ
ꢗ.ꢙꢀ ±0.ꢁ0
ꢙ.ꢙꢀ ±0.ꢁ0
ꢁꢝ
ꢀꢖ
ꢑꢈꢌꢒꢈꢋꢅ
ꢃꢓꢄꢔꢊꢂꢅ
ꢁ
ꢁꢜ
0.ꢝ0 ꢞꢏꢌ
0.ꢛ0 ꢞꢏꢌ
0.ꢖ0 ±0.0ꢀ
ꢜ.ꢁ0 ±0.0ꢀ
ꢝ.ꢀ0 ±0.0ꢀ
Rꢅꢌꢃꢎꢎꢅꢂꢇꢅꢇ ꢏꢃꢔꢇꢅR ꢑꢈꢇ ꢑꢊꢄꢌꢤ ꢈꢂꢇ ꢇꢊꢎꢅꢂꢏꢊꢃꢂꢏ
ꢈꢑꢑꢔꢣ ꢏꢃꢔꢇꢅR ꢎꢈꢏꢒ ꢄꢃ ꢈRꢅꢈꢏ ꢄꢤꢈꢄ ꢈRꢅ ꢂꢃꢄ ꢏꢃꢔꢇꢅRꢅꢇ
ꢑꢊꢂ ꢁ ꢂꢃꢄꢌꢤ
R ꢢ 0.ꢁ0
ꢄꢣꢑ
R ꢢ 0.ꢗ0 ꢄꢣꢑ ꢃR
0.ꢜꢀ ± 0.0ꢀ
0.ꢗꢀ × ꢛꢀ° ꢌꢤꢈꢎꢍꢅR
ꢀ.00 ±0.ꢁ0
ꢛꢛ
ꢀꢖ
0.00 ꢧ 0.0ꢀ
ꢛꢗ
0.ꢛ0 ±0.ꢁ0
ꢑꢊꢂ ꢁ
ꢄꢃꢑ ꢎꢈRꢒ
ꢘꢏꢅꢅ ꢂꢃꢄꢅ ꢙꢚ
ꢁ
ꢛꢗ
0.ꢖ0 ±0.0ꢀ
ꢙ.ꢛ0 Rꢅꢍ
ꢝ.00 ±0.ꢁ0
0.ꢛ0 ꢞꢏꢌ
ꢙ.ꢙꢀ ±0.ꢁ0
ꢗ.ꢙꢀ ±0.ꢁ0
ꢖꢜ
ꢁꢜ
ꢖꢜ
0.ꢖꢜ Rꢅꢍ
ꢘꢓꢤꢋꢀꢖꢚ ꢥꢍꢂ 0ꢜꢁꢙ Rꢅꢟ ꢦ
ꢖꢙ
ꢁꢝ
0.ꢖ00 Rꢅꢍ
ꢗ.ꢖ0 Rꢅꢍ
ꢞꢃꢄꢄꢃꢎ ꢟꢊꢅꢉꢠꢅꢡꢑꢃꢏꢅꢇ ꢑꢈꢇ
0.ꢜꢀ ±0.0ꢀ
ꢁꢝ
ꢖꢙ
0.00 ꢧ 0.0ꢀ
ꢂꢃꢄꢅꢆ
ꢁ. ꢇRꢈꢉꢊꢂꢋ ꢌꢃꢂꢍꢃRꢎꢏ ꢄꢃ ꢐꢅꢇꢅꢌ ꢑꢈꢌꢒꢈꢋꢅ
ꢃꢓꢄꢔꢊꢂꢅ ꢎꢃꢕꢖꢖ0
ꢛ. ꢇꢊꢎꢅꢂꢏꢊꢃꢂꢏ ꢃꢍ ꢅꢡꢑꢃꢏꢅꢇ ꢑꢈꢇ ꢃꢂ ꢞꢃꢄꢄꢃꢎ ꢃꢍ ꢑꢈꢌꢒꢈꢋꢅ ꢇꢃ ꢂꢃꢄ ꢊꢂꢌꢔꢓꢇꢅ
ꢎꢃꢔꢇ ꢍꢔꢈꢏꢤ. ꢎꢃꢔꢇ ꢍꢔꢈꢏꢤꢨ ꢊꢍ ꢑRꢅꢏꢅꢂꢄꢨ ꢏꢤꢈꢔꢔ ꢂꢃꢄ ꢅꢡꢌꢅꢅꢇ 0.ꢖ0ꢩꢩ ꢃꢂ ꢈꢂꢣ ꢏꢊꢇꢅ
ꢀ. ꢅꢡꢑꢃꢏꢅꢇ ꢑꢈꢇ ꢏꢤꢈꢔꢔ ꢞꢅ ꢏꢃꢔꢇꢅR ꢑꢔꢈꢄꢅꢇ
ꢙ. ꢏꢤꢈꢇꢅꢇ ꢈRꢅꢈ ꢊꢏ ꢃꢂꢔꢣ ꢈ RꢅꢍꢅRꢅꢂꢌꢅ ꢍꢃR ꢑꢊꢂ ꢁ ꢔꢃꢌꢈꢄꢊꢃꢂ
ꢃꢂ ꢄꢤꢅ ꢄꢃꢑ ꢈꢂꢇ ꢞꢃꢄꢄꢃꢎ ꢃꢍ ꢑꢈꢌꢒꢈꢋꢅ
ꢖ. ꢇRꢈꢉꢊꢂꢋ ꢂꢃꢄ ꢄꢃ ꢏꢌꢈꢔꢅ
ꢗ. ꢈꢔꢔ ꢇꢊꢎꢅꢂꢏꢊꢃꢂꢏ ꢈRꢅ ꢊꢂ ꢎꢊꢔꢔꢊꢎꢅꢄꢅRꢏ
Rev. 0
108
For more information www.analog.com
LTC3888-1
TYPICAL APPLICATIONS
(Advanced implementation with some error amplifiers disabled)
6V TO 14V
V
IN
2.2μF
V
IN
V
IN
SW
GND
PWM
IMON
IREF
V
V
SW
GND
PWM
IMON
IREF
PWM5
SENSE5
PWM0
SENSE0
OUT0
IN
I
0.4V TO 3.45V
AT 800A
I
TEMP
TEMP
TSNS1
TSNS0
+
V
SW
GND
PWM
IMON
IREF
V
SW
GND
PWM
IMON
IREF
PWM5
SENSE5
PWM2
SENSE2
IN
IN
I
I
I
TEMP
TEMP
LTC3888-1
V
SW
GND
PWM3
SENSE3
PWM6
PWM
IMON
IREF
V
SW
GND
PWM
IMON
IREF
IN
IN
I
SENSE6
TEMP
TEMP
PWM4
SENSE4
IREF
PWM7
SENSE7
V
SW
GND
PWM
IMON
IREF
V
SW
GND
PWM
IMON
IREF
IN
IN
I
I
TEMP
TEMP
INTV
V
+
–
CC
V
V
SENSE0
SENSE0
V
DD33
4.7μF
DAOUT0
VFB0
+
–
SENSE1
SENSE1
V
DD33
V
V
DD33
DAOUT1
VFB1
PGOOD1
PGOOD0
SYNC
FAULT0
FAULT1
RUN0
RUN1
SCL
SDA
ALERT
PMBus
SHARE_CLK
I
I
TH1
TH0
100pF
I
I
THR1
V
THR0
DD25
V
2200pF
DD33
GND
GND
2μF
1μF
I
I
I
THR1
TH1
THR0
I
TH0
PGOOD0
PGOOD1
SHARE_CLK
V
DD33
RUN0
RUN1
FAULT0
FAULT1
SYNC
INTV
CC
V
DD25
LTC3888-1
1μF
V
4.7μF
DD33
+
–
V
V
SENSE0
SENSE0
DAOUT0
VFB0
2μF
+
–
V
V
SENSE1
SENSE1
DAOUT1
VFB1
SCL
SDA
PMBus
ALERT
V
SW
GND
V
SW
GND
PWM
IMON
IREF
PWM1
SENSE1
PWM
PWM0
SENSE0
IN
IN
I
IMON
IREF
I
I
TEMP
TSNS1
TSNS0
TEMP
V
PWM
IMON
IREF
PWM5
V
PWM2
SENSE2
PWM
IMON
IREF
IN
IN
I
SW
GND
SW
GND
SENSE5
TEMP
TEMP
V
SW
GND
PWM
IMON
IREF
V
SW
GND
PWM6
SENSE6
PWM3
SENSE3
PWM
IMON
IREF
IN
IN
I
I
I
TEMP
TEMP
PWM4
SENSE4
IREF
V
SW
GND
PWM
IMON
IREF
V
SW
GND
PWM7
PWM
IMON
IREF
IN
IN
I
SENSE7
NOTE: RSET and optional
resistor configuration not
shown, see page 59.
V
IN
TEMP
TEMP
V
38881 F52
IN
Figure 52. 16-Phase 800A Output
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
109
LTC3888-1
TYPICAL APPLICATIONS
ꢘ
ꢖꢘ ꢆꢜ ꢀꢕꢘ
ꢎR
ꢒꢍ
ꢀ.ꢀꢁꢂ
ꢘ
ꢋꢘ ꢆꢜ ꢗꢘ
ꢘ
ꢒꢍ
ꢘ
ꢘ
ꢜꢝꢆ0
0.ꢕꢘ ꢆꢜ ꢈ.ꢕꢋꢘ
ꢛꢆ ꢃꢀ0ꢛ
ꢘꢎRꢡꢑꢜꢍ
ꢏꢐꢑꢃ
ꢓꢔꢍꢓꢔꢃ
ꢆꢓꢍꢓꢃ
ꢏꢐꢑ0
ꢓꢔꢍꢓꢔ0
ꢜꢝꢆꢃ
0.ꢕꢘ ꢆꢜ ꢈ.ꢕꢋꢘ
ꢛꢆ ꢃꢀ0ꢛ
ꢙꢇꢓꢃ
ꢚꢇꢓꢃ
ꢙꢇꢓꢃ
ꢚꢇꢓꢃ
ꢒ
ꢒ
ꢏꢜꢐꢔR
ꢞꢅꢜꢇꢢ
ꢏꢜꢐꢔR
ꢞꢅꢜꢇꢢ
ꢏꢐꢑꢋ
ꢓꢔꢍꢓꢔꢋ
ꢏꢐꢑꢀ
ꢓꢔꢍꢓꢔꢀ
ꢙꢇꢓꢀ
ꢚꢇꢓꢀ
ꢒ
ꢒ
ꢒ
ꢒ
ꢙꢇꢓꢀ
ꢚꢇꢓꢀ
ꢅꢆꢇꢈꢉꢉꢉꢊꢃ
ꢏꢐꢑꢈ
ꢓꢔꢍꢓꢔꢈ
ꢆꢠRꢔꢔ ꢛꢎꢎꢒꢆꢒꢜꢍꢛꢅ
ꢏꢐꢑꢖ
ꢆꢠRꢔꢔ ꢛꢎꢎꢒꢆꢒꢜꢍꢛꢅ
ꢒꢎꢔꢍꢆꢒꢇꢛꢅ ꢏꢜꢐꢔR ꢙꢇꢓꢈ
ꢒ
ꢙꢇꢓꢈ ꢒꢎꢔꢍꢆꢒꢇꢛꢅ ꢏꢜꢐꢔR
ꢚꢇꢓꢈ
ꢓꢔꢍꢓꢔꢖ
ꢓꢆꢛꢌꢔꢓ
ꢚꢇꢓꢈ
ꢓꢆꢛꢌꢔꢓ
ꢏꢐꢑꢕ
ꢓꢔꢍꢓꢔꢕ
ꢒRꢔꢂ
ꢏꢐꢑꢗ
ꢙꢇꢓꢕ
ꢚꢇꢓꢕ
ꢙꢇꢓꢕ
ꢚꢇꢓꢕ
ꢒ
ꢓꢔꢍꢓꢔꢗ
ꢒꢍꢆꢘ
ꢇꢇ
ꢈꢁꢂ
ꢕ.ꢗꢁꢂ
ꢙ
ꢚ
ꢙ
ꢚ
ꢘ
ꢘ
ꢘ
ꢘ
ꢓꢔꢍꢓꢔꢃ
ꢓꢔꢍꢓꢔꢃ
ꢓꢔꢍꢓꢔ0
ꢓꢔꢍꢓꢔ0
ꢎꢛꢜꢝꢆꢃ
ꢎꢛꢜꢝꢆ0
ꢘꢂꢞ0
ꢏꢌꢜꢜꢎ0
ꢏꢌꢜꢜꢎꢃ
ꢘꢂꢞꢃ
ꢓꢟꢍꢇ
FAULT0
FAULT1
Rꢝꢍ0
Rꢝꢍꢃ
ꢏꢓꢑ
ꢓꢠꢛRꢔꢎ
ꢏꢒꢍꢓ
ꢓꢇꢅ
ꢓꢎꢛ
ꢛꢅꢔRꢆ
ꢏꢑꢞꢣꢤ
ꢓꢠꢛRꢔꢡꢇꢅꢢ
ꢒ
ꢒ
ꢒ
ꢆꢠRꢃ
ꢆꢠꢃ
ꢎꢎꢈꢈ
ꢆꢠR0
ꢆꢠ0
NOTE: RSET and optional
resistor configuration not
shown, see page 59.
ꢀꢀ00ꢄꢂ
ꢀꢀ00ꢄꢂ
ꢒ
ꢃ00ꢄꢂ
ꢘ
ꢘ
ꢃ00ꢄꢂ
ꢎꢎꢀꢋ
ꢌꢍꢎ
ꢀꢁꢂ
ꢃꢁꢂ
ꢈꢉꢉꢉꢃꢀ ꢂꢋꢈ
Figure 53. Dual 4-Phase 120A Power Block Rails
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COMMENTS
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LTM4677
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IN
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2
with Digital Power Management
Fault Logging, I C/PMBus Interface, 16mm × 16mm × 5mm BGA Package
2
Dual 18A or Single 36A Step-Down DC/DC µModule Regulator 4.5V ≤ V ≤ 16V, 0.5V ≤ V
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IN
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Dual 50A or Single 100A Step-Down DC/DC µModule
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4.5V ≤ V ≤ 16V, 0.5V ≤ V
≤ 1.8V, 0.5% V
Accuracy, Fault
IN
OUT
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Logging, I C/PMBus Interface, 15mm × 22mm × 7.87mm BGA Package
8-Channel PMBus Power System Manager
Fault Logging of 8 Output Voltages, V and Die Temperature
IN
LTC3882/
Dual Output Multiphase Step-Down DC/DC Voltage Mode
Controller Digital Power System Management
V
Up to 38V, 0.5V ≤ V
≤ 5.25V, 0.5% V
Accuracy, Fault
IN
OUT
OUT
2
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2
LTC3884/
LTC3884-1
Dual Output Multiphase Step-Down DC/DC Current Mode
Controller with Sub-mΩ DCR Sensing and Digital Power
System Management
4.5V ≤ V ≤ 38V, 0.5V ≤ V
Interface with EEPROM and 16-Bit ADC, Programmable Analog Loop
Compensation, Input Current Sense
( 0.5%) ≤ 5.5V, Fault Logging, I C/PMBus
IN
OUT
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Up to 5.5V, Accurate Current Sharing
IN
OUT
with Sub-mΩ DCR Sensing
LTC3887/
LTC3887-1
Dual Output Multiphase Step-Down DC/DC Current Mode
Controller Digital Power System Management
V
Up to 24V, 0.5V ≤ V
≤ 5.5V, 0.5% V
Accuracy, Fault Logging,
IN
OUT
OUT
2
I C/PMBus Interface with EEPROM and 16-Bit ADC
LTC3886
60V Dual Output Multiphase Step-Down DC/DC Current Mode 4.5V ≤ V ≤ 60V, 0.5V ≤ V
( 0.5%) ≤ 13.8V, Fault Logging,
IN
OUT
2
Controller Digital Power System Management
I C/PMBus Interface with EEPROM and 16-Bit ADC, Programmable
Analog Loop Compensation, Input Current Sense
LTC3889
60V Dual Output Multiphase Step-Down DC/DC Current Mode 5V ≤ V ≤ 60V, 1V ≤ V
≤ 40V, 0.5% V
Accuracy, Fault Logging,
IN
OUT
OUT
2
Controller Digital Power System Management
I C/PMBus Interface with EEPROM and 16-Bit ADC, Programmable
Analog Loop Compensation, Input Current Sense
LTC3870/
LTC3870-1
60V Multiphase Step-Down DC/DC Current Mode Slave
Controller
V
Up to 60V, 0.5V ≤ V
Up to 14V, Accurate Current Sharing
IN
OUT
LTC3888/
LTC3888-2
Dual Output 8-Phase Expandable Step-Down DC/DC Current
4.5V ≤ V ≤ 28.5V, 0.3V ≤ V
( 0.5%) ≤ 3.45V, Fault Logging,
IN
OUT
2
Mode Controller with Digital Power System Management and SPI I C/PMBus Interface with EEPROM and 16-Bit ADC, Programmable
Interface
Analog Loop Compensation with Load Step Emulation
Rev. 0
02/20
www.analog.com
ANALOG DEVICES, INC. 2020
110
相关型号：
LTC3890EGN-3#PBF
LTC3890-3 - 60V Low IQ, Dual, 2-Phase Synchronous Step-Down DC/DC Controller; Package: SSOP; Pins: 28; Temperature Range: -40°C to 85°C
Linear
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