LTC4242CG#PBF [ADI]
Dual Slot Hot Swap Controller for PCI Express;型号: | LTC4242CG#PBF |
厂家: | ADI |
描述: | Dual Slot Hot Swap Controller for PCI Express PC 光电二极管 |
文件: | 总24页 (文件大小:345K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC4242
Dual Slot Hot Swap
Controller for PCI Express
U
DESCRIPTIO
FEATURES
Allows Live Insertion into PCI Express® Backplane
The LTC®4242 Hot SwapTM controller allows safe board
insertion and removal for two independent slots on a PCI
Expressbackplane.ExternalN-channeltransistorscontrol
the12Vand3.3Vsupplieswhileintegratedswitchescontrol
the 3.3V auxiliary supplies. Both 12V and 3.3V supplies
can be ramped up at an adjustable rate. Dual level circuit
breakersandfastactivecurrentlimitingprotectallsupplies
against overcurrent faults.
■
■
Controls Two Independent PCI Express Slots
■
Independent Control of Main and Auxiliary Supplies
■
20V Rating for 12V Supply Input Pins
■
Integrated 0.25Ω AUX Switches
■
Limits Fault Current in ≤1µs
■
Force On Test Mode
■
Adjustable Supply Voltage Power-Up Rate
■
High Side Drivers for N-Channel MOSFETs
A supply filter at the V pin allows the LTC4242 to endure
CC
■
Thermal Shutdown Protection
supply transients. The EN input detects the presence of a
card in the PCI Express slot. The FAULT and AUXFAULT
outputs alert the system of overcurrent conditions on the
main and auxiliary supplies, respectively. PGOOD and
AUXPGOOD outputs indicate proper main and auxiliary
supply outputs.
■
Available in 38-Lead QFN and 36-Lead SSOP
Packages
U
APPLICATIO S
■
PCI Express-Based PC and Servers
Hot Swap Application for Triple Supply Systems
■
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
Hot Swap is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
U
TYPICAL APPLICATIO
PCI Express Application
12V
12V
OUT
3.3V
3.3V
OUT
Normal Power-Up Sequence
12V
12V
12V
12V
3V
3V
3V
SENSE1
IN1
SENSE1
GATE1
OUT1
IN1
GATE1
V
3V
CC
OUT1
ENn
5V/DIV
AUXOUT1
3.3V
OUT
AUXOUTn
5V/DIV
3.3V
AUXIN1
BD_PRST1
AUXON1
ON1
FON1
EN1
GND
EN2
FON2
FAULT1
AUXFAULT1
PGOOD1
PGOOD2
AUXFAULT2
FAULT2
ON2
PCIe
PLUG-IN
CONNECTOR CARD
12V
OUTn
LTC4242G
5V/DIV
PCI EXPRESS
HOT PLUG
CONTROLLER
3V
5V/DIV
OUTn
BD_PRST2
AUXON2
AUXOUT2
3.3V
OUT
PGOODn
5V/DIV
3V
OUT2
AUXIN2
3.3V
12V
12V
12V
12V
3V
3V
3V
SENSE2 GATE2
IN2
SENSE2
GATE2
OUT2
IN2
4242 F04
10ms/DIV
3.3V
3.3V
12V
OUT
12V
OUT
4242 TA01a
PCIe
PLUG-IN
CONNECTOR CARD
4242f
1
LTC4242
W W U W
ABSOLUTE AXI U RATI GS (Note 1)
12V
12V
................................................ –0.3V to 25V
Supply Voltages
GATEn
OUTn
(Note 3).. 12V
– 5V to 12V
+ 0.3V
V ........................................................... –0.3V to 7V
GATEn
GATEn
CC
AUXOUTn, 3V
.............................. –0.3V to 10V
12V .................................................... –0.3V to 20V
SENSEn
INn
3V
3V
.................................................. –0.3V to 14V
3V ...................................................... –0.3V to 10V
GATEn
OUTn
INn
(Note 3)....... 3V
– 5V to 3V
+ 0.3V
AUXINn.................................................. –0.3V to 10V
GATEn
GATEn
Operating Temperature Range
Input Voltages
LTC4242C ................................................ 0°C to 70°C
LTC4242I ............................................. –40°C to 85°C
Storage Temperature Range
ONn, AUXONn, FONn............................... –0.3V to 7V
ENn.......................................................... –0.3V to 7V
Output Voltages
SSOP ................................................. –65°C to 150°C
QFN.................................................... –65°C to 125°C
Lead Temperature (Soldering, 10 sec)
FAULTn, PGOODn, AUXFAULTn,
AUXPGOODn ........................................... –0.3V to 7V
Analog Voltages
SSOP ................................................................ 300°C
12V
.............................................. –0.3V to 20V
SENSEn
U
W
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
TOP VIEW
1
2
FAULT1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
EN1
FON1
AUXFAULT1
PGOOD1
3
ON1
38 37 36 35 34 33 32
4
12V
IN1
AUXON1
AUXON1
1
2
31 12V
IN1
5
12V
SENSE1
3V
30
29
28
12V
SENSE1
12V
GATE1
12V
OUT1
3V
OUT1
OUT1
3V
3
6
12V
GATE1
3V
GATE1
GATE1
3V
4
7
12V
OUT1
SENSE1
3V
3V
SENSE1
5
27 AUXOUT1
GND
IN1
AUXIN1
8
AUXOUT1
GND
3V
IN1
6
26
25 AUXOUT2
9
AUXIN1
39
V
7
CC
AUXIN2
3V
10
11
12
13
14
15
16
17
18
AUXOUT2
V
CC
8
24 12V
23 12V
22 12V
21 12V
OUT2
12V
OUT2
AUXIN2
9
IN2
GATE2
SENSE2
12V
GATE2
3V
IN2
3V
10
11
12
SENSE2
12V
SENSE2
3V
SENSE2
3V
GATE2
3V
IN2
12V
IN2
3V
GATE2
20
AUXPGOOD2
OUT2
PGOOD2
AUXFAULT2
FAULT2
EN2
3V
OUT2
13 14 15 16 17 18 19
AUXON2
ON2
FON2
UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
G PACKAGE
36-LEAD PLASTIC SSOP
T
JMAX
= 125°C, θ = 34°C/W
JA
T
= 125°C, θ = 95°C/W
JA
JMAX
EXPOSED PAD (PIN 39) IS GND, PCB ELECTRICAL CONNECTION OPTIONAL
ORDER PART NUMBER
ORDER PART NUMBER
UHF PART MARKING*
LTC4242CG
LTC4242IG
LTC4242CUHF
LTC4242IUHF
4242
4242
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
*The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges.
4242f
2
LTC4242
ELECTRICAL CHARACTERISTICS The
(Note 2)
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V = V
= V
= 3.3V, V
= 12V, unless otherwise noted.
A
CC
AUXINn
3VINn
12VINn
SYMBOL
Supplies
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
●
●
●
●
V
Operating Voltage
V
2.7
10.1
3.0
6.0
14.4
6.0
V
V
V
V
IN
CC
12V
INn
3V
AUXINn
INn
3.0
6.0
I
DD
Input Supply Current
V
= 2V, V
= 2V
AUXONn
ONn
●
●
●
V
1.6
0.5
0.35
4
1
1
mA
mA
mA
CC
12V
INn
INn
3V
●
●
●
●
V
Supply Undervoltage Lockout
V
Rising
INn
INn
2.3
2.45
9.78
2.67
2.67
2.6
10.08
2.77
2.77
V
V
V
V
UVL
CC
12V Rising
9.48
2.57
2.57
3V Rising
AUXINn Rising
●
●
●
●
ΔV
LKO(HYST)
Supply Undervoltage Lockout Hysteresis
V
30
90
20
20
100
130
35
200
170
50
mV
mV
mV
mV
CC
12V
INn
3V
AUXINn
INn
35
50
Current Limit
ΔV
SENSE(CB)
Circuit Breaker Trip Sense Voltage
●
●
12V – 12V
45
45
50
50
55
55
mV
mV
INn
SENSEn
SENSEn
3V – 3V
INn
ΔV
Active Current Limit Sense Voltage
12V – 12V
SENSE(ACL)
●
●
75
75
100
100
125
125
mV
mV
INn
SENSEn
SENSEn
3V – 3V
INn
●
●
I
t
Circuit Breaking Current for AUX Supply
Circuit Breaker Response Time
385
10
550
20
715
40
mA
µs
CBAUX
CB
Switch Resistance
R
Internal Switch Resistance
(Note 4)
I = 375mA
AUX
●
R
= (V – V )/I
AUXOUTn
0.25
0.4
Ω
AUX
AUXINn
External Gate Drive
I
I
I
External N-Channel Gate Pull-Up Current
External N-Channel Gate Pull-Down Current
Gate Drive On
GATE(UP)
GATE(DN)
GATE(FPD)
●
●
V
V
= 1V
–5
–5
–9
–9
–13
–13
µA
µA
12VGATEn
= 1V
3VGATEn
Gate Drive Off
●
●
V = 17V, V
12VGATEn
V = 8.3V, V
3VGATEn
= 12V
12VOUTn
3VOUTn
0.5
0.5
1
1
2
2
mA
mA
= 3.3V
External N-Channel Gate Fast Pull-Down
Current
Fast Turn Off
●
●
V
V
= 17V, V
= 12V
150
150
250
250
400
400
mA
mA
12VGATEn
3VGATEn
12VOUTn
3VOUTn
= 8.3V, V
= 3.3V
ΔV
External N-Channel Gate Drive
I
= 1µA (Note 3)
GATE
GATE
●
●
12V
– 12V
4.5
4.5
5.5
5.5
7.9
7.9
V
V
GATEn
OUTn
– 3V
OUTn
3V
GATEn
Input Pins
●
●
●
V
Power Good Threshold Voltage
Power Good Hysteresis
12V
OUTn
AUXOUTn Falling (Note 5)
Falling
10.08
2.772
2.772
10.38
2.855
2.855
10.68
2.937
2.937
V
V
V
PG(TH)
OUTn
3V
Falling
●
●
●
V
12V
OUTn
20
5
5
70
20
20
110
30
30
mV
mV
mV
PG(HYST)
OUTn
3V
AUXOUTn (Note 5)
4242f
3
LTC4242
ELECTRICAL CHARACTERISTICS The
(Note 2)
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V = V
= V
= 3.3V, V
= 12V, unless otherwise noted.
A
CC
AUXINn
3VINn
12VINn
SYMBOL
PARAMETER
CONDITIONS
MIN
1.173
30
TYP
1.235
70
MAX
1.297
120
0.7
UNITS
V
●
●
●
●
●
●
●
●
V
ONn, AUXONn Pin Threshold Voltage
ONn, AUXONn Pin Hysteresis
ONn, AUXONn Pin Reset Threshold Voltage
ONn, AUXONn Pin Input Current
ENn Pin Threshold Voltage
ENn Pin Hysteresis
Rising Edge
ON(TH)
ΔV
mV
V
ON(TH)
ON(RTH)
ON(IN)
V
Falling Edge
0.5
0.6
I
V
= V
= 1.2V
1
µA
V
ONn
AUXONn
V
ENn Rising
1.173
30
1.235
70
1.297
120
–13
2.6
EN(TH)
ΔV
EN(HYST)
mV
µA
V
I
ENn Pull-Up Current
V
ENn
= 1V
–5
–9
EN(UP)
V
FONn Pin Logic Threshold
0.7
FON
I
SENSE Pin Input Current
SENSE
●
●
12V
V
V
= 12V
12VSENSEn
3VSENSEn
40
40
100
100
µA
µA
SENSEn
SENSEn
3V
= 3.3V
I
OUT Pin Input Current
12V
Gate Drive On
OUT
●
●
V
V
= 12V
12VOUTn
45
27
90
60
µA
µA
OUTn
3V
= 3.3V
3VOUTn
OUTn
R
OUT Pin Discharge Resistance
12V
OUTn
AUXOUTn
Gate Drive Off
OUT(DIS)
●
●
●
V
V
= 6V
12VOUTn
350
165
375
700
330
750
1400
660
1500
Ω
Ω
Ω
OUTn
3V
= 2V
3VOUTn
V
= 2V
AUXOUTn
Output Pins
V
Output Low Voltage
I
= 3mA
= 1.5V
OL
PIN
●
●
FAULTn, AUXFAULTn, PGOODn,
AUXPGOODn (Note 5)
0.14
–9
0.4
V
I
PU
Pull-Up Current
FAULTn, AUXFAULTn, PGOODn,
AUXPGOODn (Note 5)
V
PIN
–5
–13
µA
Slew Rate
SR
●
AUXOUTn Slew Rate
1.25
1.7
V/ms
AUXOUT
Delays
●
●
t
Input High (ONn) to GATEs High Prop Delay
7
14
36
µs
µs
PLH(GATE)
PLH(UVL)
t
Input Supply Low (12V , 3V ) to GATEs
18
INn
INn
Low Prop Delay
●
●
t
t
Out Low (12V
Prop Delay
, 3V
) to PGOOD High
20
40
1
µs
µs
PLH(PG)
OUTn
OUTn
Sense Voltage High to GATE Low
ΔV
= 200mV, C = 10nF
GATE
0.4
PHL(SENSE)
SENSE
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: An internal clamp limits the GATE pins to a minimum of 5V above
. Driving this pin to voltages beyond the clamp may damage the
device.
V
OUT
Note 4: For the QFN package, the AUX FET on resistance is guaranteed by
Note 2: All current into device pins is positive, all current out of the device
pins is negative. All voltages are referenced to GND unless otherwise
specified.
correlation to wafer level measurements.
Note 5: Available on QFN package only.
4242f
4
LTC4242
U W
TYPICAL PERFOR A CE CHARACTERISTICS
T = 25°C. V = V
= V
= 3.3V, V = 12V, unless otherwise noted. (Note 2)
12VINn
A
CC
AUXINn
3VINn
V
, 12V and 3V Supply
12V UV Rising Threshold
INn
vs Temperature
CC
INn
INn
I
vs V
Current vs Temperature
DD
CC
3.0
2.5
1.0
1.5
1.0
1.8
1.5
1.2
0.9
10.2
10.0
9.8
V
CC
9.6
12V
INn
0.6
0.3
3V
INn
9.4
–50
–25
0
25
50
75
100
100
100
5
6
–50
0
25
50
75
100
3
7
4
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
V
(V)
CC
4242 G03
4242 G01
4242 G02
3V
, AUXOUTn Power Good
3V , AUXINn Rising Threshold
12V
Power Good Threshold
OUTn
INn
OUTn
Threshold vs Temperature
vs Temperature
vs Temperature
10.6
10.4
10.2
10.0
2.72
2.70
2.68
2.66
2.92
2.90
2.88
2.86
9.8
2.64
2.84
–50 –25
0
25
50
75
100
–50 –25
0
25
50
75
100
–50 –25
0
25
50
75
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4242 G05
4242 G04
4242 G06
OUT Discharge Resistance
vs Temperature
ONn, AUXONn, ENn Low-to-High
Threshold vs Temperature
ONn, AUXONn, ENn Hysteresis
vs Temperature
1.242
1.240
1.238
1.236
1000
800
600
400
90
80
70
60
AUXOUTn
12V
OUTn
1.234
1.232
3V
50
OUTn
200
50
–50
0
25
50
75
100
–25
–50 –25
0
25
75
100
–50 –25
0
25
50
75
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4242 G08
4242 G07
4242 G09
4242f
5
LTC4242
U W
TYPICAL PERFOR A CE CHARACTERISTICS
T = 25°C. V = V
= V
= 3.3V, V
12VINn
= 12V, unless otherwise noted. (Note 2)
A
CC
AUXINn
3VINn
FONn Low-to-High Threshold
FONn High-to- Low Threshold
vs V
R
vs Temperature
vs V
CC
ON
CC
3
5
4
3
2
1
0
0.35
0.30
0.25
0.20
2
1
0
0.15
2
3
4
5
6
7
–50 –25
0
25
50
75
100
2
3
4
5
6
7
V
(V)
TEMPERATURE (°C)
CC
V
(V)
CC
4242 G11
4242 G12
4242 G10
Current Limit Propagation Delay
vs Sense Voltage
Circuit Breaker Trip Sense
Voltage vs Temperature
R
ON
vs AUXINn
0.35
100
10
1
52
51
50
49
0.30
0.25
0.20
0.1
0.15
0.01
48
–50
3
3.5
4
4.5
5
5.5
6
6.5
0
50
100
150
200
250
300
–25
0
25
50
75
100
AUXINn (V)
SENSE VOLTAGE (mV)
TEMPERATURE (°C)
4242 G13
4242 G14
4242 G14
Circuit Breaker Trip Filter Time
vs Temperature
Aux Circuit Breaker Trip Current
vs Temperature
Gate Drive vs I
GATE
6
25.0
22.5
20.0
17.5
650
600
550
500
5
4
3
2
1
0
15.0
450
2
4
6
8
10
–50 –25
0
25
50
75
100
–50 –25
0
25
50
75
100
TEMPERATURE (°C)
I
(µA)
TEMPERATURE (°C)
GATE
4242 G18
4242 G17
4242 G14
4242f
6
LTC4242
U W
TYPICAL PERFOR A CE CHARACTERISTICS
= 12V, unless otherwise noted. (Note 2)
12VINn
T = 25°C. V = V
= V
= 3.3V, V
A
CC
AUXINn
3VINn
Gate Drive vs Temperature
I
Pull-Up vs Temperature
GATE
–15
–10
–5
6.0
5.8
5.6
5.4
5.2
5.0
0
–50
–25
0
25
50
75
100
–50
0
25
50
75
100
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
4242 G20
4242 G19
Gate Fast Pull-Down Current
vs Temperature
I
Off Current vs Temperature
GATE
1.2
1.1
1.0
0.9
300
275
250
225
0.8
0.7
200
–50
0
25
50
74
100
–25
–50 –25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
4242 G21
4242 G22
4242f
7
LTC4242
U
U
U
PI FU CTIO S
12V
/12V
: Gate Drive for 12V Supply External
3V
/3V
:3.3VSupplyCurrentLimitSenseInput.
GATE1
GATE2
SENSE1
SENSE2
N-Channel MOSFET. An internal charge pump provides
Asenseresistorisplacedinthesupplypathbetween3V
INn
a 9µA pull-up current to ramp up 12V . During turn
off, a 1mA pull-down current source discharges 12V
to ground. 12V
12V
currentsourcebetween12V
An external RC network is required at the pin for optimum
current limit response.
and 3V
to sense 3.3V channel’s load current. The
GATEn
SENSEn
voltage across the sense resistor is monitored for active
current limit and circuit breaker fault detection. To disable
the circuit breaker function for the 3.3V channel, connect
GATEn
is internally clamped to 5.5V above
GATEn
. During an overcurrent fault, a 250mA pull-down
OUTn
and12V
isactivated.
3V
to 3V
.
GATEn
OUTn
SENSEn
INn
3V /3V : 3.3V Supply Input. An undervoltage lockout
IN1
IN2
circuit disables the 3.3V and 12V supplies when 3V
INn
12V
/12V
SENSE1
: 12V Supply Current Limit Sense
voltage is less than 2.67V.
SENSE2
Input.Asenseresistorisplacedinthesupplypathbetween
3V
/3V
: 3.3V Output Connection. Connect this
OUT1
OUT2
12V and 12V to sense the 12V channel’s load
INn
SENSEn
pin to the source of the 3.3V supply external N-channel
MOSFET for gate drive return. PGOOD1/PGOOD2 cannot
pull low until this pin goes above 2.855V. A 375Ω active
current.Thevoltageacrossthesenseresistorismonitored
for active current limit and circuit breaker fault detection.
To disable the circuit breaker function for the 12V channel,
pull-downdischarges3V
MOSFET is turned off.
togroundwhentheexternal
OUTn
connect 12V
to 12V
.
SENSEn
INn
12V /12V :12VSupplyInput.Anundervoltagelockout
IN1
IN2
AUXFAULT1/AUXFAULT2: AUX Supply Fault Status Out-
put.AUXFAULTnisnormallypulledhighbyaninternal9µA
pull-up. It asserts low if the AUX channel shuts off due
to an overcurrent fault or due to the device temperature
rising above 150°C. Indicates switch ON status when
FONn and ENn are high.
circuit disables the 12V and 3.3V supplies when 12V
INn
voltage is less than 9.78V.
12V
/12V
: 12V Output Connection. Connect this
OUT1
OUT2
pin to the source of the 12V supply external N-channel
MOSFET for gate drive return. PGOOD1/PGOOD2 cannot
pull low until this pin goes above 10.38V. A 700Ω active
AUXON1/AUXON2: AUX Supply On Control Input. A rising
edge turns on the internal FET, while a falling edge turns it
off. Pulling this pin below 0.6V for more than 3.5µs clears
the fault on the AUX channel.
pull-downdischarges12V
MOSFET is turned off.
togroundwhentheexternal
OUTn
3V
/3V
: Gate Drive for 3.3V Supply External
GATE2
GATE1
N-Channel MOSFET. An internal charge pump provides
AUXIN1/AUXIN2: AUX Supply Input. An undervoltage
lockout circuit disables the AUX supply when the voltage
at AUXINn is less than 2.67V. AUXINn is the input to the
internal pass FET.
a 9µA pull-up current to ramp up 3V . During turn
GATEn
off, a 1mA pull-down current source discharges 3V
GATEn
to ground. 3V
is internally clamped to 5.5V above
GATEn
3V
. During an overcurrent fault, a 250mA pull-down
OUTn
AUXOUT1/AUXOUT2: AUX Supply Output. AUXOUTn
is the output from the internal pass FET. AUXPGOOD1/
AUXPGOOD2 cannot pull low until this pin goes above
2.855V. A 750Ω active pull-down discharges AUXOUTn
to ground when the internal FET is turned off.
current source between 3V
and 3V
is activated.
GATEn
OUTn
An external RC network is required at the pin for optimum
current limit response.
4242f
8
LTC4242
U
U
U
PI FU CTIO S
on the ONn and AUXONn pins. However, UVLO on V
AUXPGOOD1/AUXPGOOD2 (QFN): AUX Supply Power
Status Output. This open-drain pin is pulled high by an
internal 9µA pull-up when AUXOUTn is below power good
threshold, when ENn is high, during thermal shutdown,
CC
would shut off the switches. Caution! There is no current
limit mechanism in this mode. Connect FONn to ground
to disable the fault override feature.
AUXONn is low or when V or AUXINn are in UVLO.
CC
GND: Device Ground. Connect to a ground plane.
EN1/EN2: Card Presence/Slot Insert Detect Input. ENn
pin must be pulled below 1.235V to enable the system.
An internal 9µA pull-up current source is present on this
pin.
ON1/ON2: Main Supply On Control Input. A rising edge
turns on the external MOSFETs for the 12V and 3.3V sup-
plies,whileafallingedgeturnsthemoff.Pullthispinbelow
0.6V to clear the faults on 12V and 3.3V channels.
Exposed Pad (QFN): Power Ground. PCB electrical con-
PGOOD1/PGOOD2:MainSupplyPowerStatusOutput.This
nection is optional.
open-drain pin is pulled high by an internal 9µA pull-up
when 12V
or 3V
is below power good threshold,
FAULT1/FAULT2: Main Supplies Fault Status Output.
FAULTn is pulled high by an internal 9µA pull-up. When an
overcurrent fault occurs at either the 12V or 3.3V supply,
FAULTn is latched low.
OUTn
OUTn
when ENn is high, ONn is low or when V or any of the
CC
main supplies are in UVLO.
V : Device Supply Input. Operates from 2.7V to 6V. An
CC
internalundervoltagelockoutcircuitdisablesthepartuntil
FON1/FON2: Force On Digital Input. For diagnostic pur-
poses,ahighinputoverridesundervoltageandovercurrent
faultson12V,3.3VandAUXchannelsandinputcommands
the voltage at V exceeds 2.45V.
CC
4242f
9
LTC4242
U
U
W
FU CTIO AL DIAGRA
CP12V
CP3V
CPAUX
V
CC
CHARGE
PUMP
V
CC
OSCILLATOR
12V
3V
IN
GND
UVLO
4
V
CC
IN
V
CC
AUXIN
9µA
10µA
FAULTn
EN
ENn
ONn
+
–
BOARD PRSNT
MAIN ON
1.235V
ON1
FON
ON2
+
–
–
0.6V
V
CC
1.235V
SYSTEM
CONTROL
9µA
FORCE ON
AUX ON
FONn
PGOODn
AUXONn
+
–
–
0.6V
1.235V
3
3
SYSTEM CONTROL
CP12V
100mV
12V
12V
INn
ACL1
+
+
–
–
9µA
SENSEn
12V
GATEn
50mV
ECB1
+
+
–
–
12V SUPPLY
CONTROL
12V
OUTn
GATE
DRIVER
5.5V
PG1
1.235V
7.4R
R
+
–
12V PWR GOOD
12V
OUTn
1mA
12V SUPPLY
CP3V
100mV
3V
3V
INn
ACL2
+
+
–
–
9µA
SENSEn
3V
GATEn
50mV
ECB2
+
+
–
–
3.3V SUPPLY
CONTROL
3V
OUTn
GATE
DRIVER
5.5V
PG2
1.235V
1.31R
+
–
3.3V PWR GOOD
3V
OUTn
1mA
R
3.3V SUPPLY
V
CC
AUXINn
9µA
THERMAL
SHUTDOWN
AUXFAULTn
CPAUX
V
CC
AUX SUPPLY
CONTROL
AUX FET
9µA
AUXPGOODn
AUXOUTn
AUX SUPPLY
4242 FD
4242f
10
LTC4242
U
OPERATIO
The Functional Diagram displays the main functional ele-
ments of this device. The LTC4242 is designed to control
the power for two independent slots on a PCI Express
backplane, allowing two boards to be safely inserted and
removed. During normal operation, the charge pump
sources 9µA to turn on the gate of the external N-chan-
nel MOSFETs to pass power to the load. The gates of the
external MOSFETs are clamped about 5.5V above their
sources. The gates of the AUX FETs rise at a slew rate of
about 1.25V/ms to control the inrush current.
an overcurrent conditon on the internal FET or thermal
shutdown has occurred.
When the switches are off (both internal and external),
the OUT pins are discharged to ground through internal
N-channel transistors.
The output voltages are monitored using the OUT pins
and the PG comparators to determine if the voltage
is valid. The power good conditon is signaled by the
PGOOD/AUXPGOOD pins using open-drain pull-down
transistors.
The electronic circuit breaker (ECB) comparator and ana-
log current limit (ACL) amplifier monitor the load current
using the difference between the V and SENSE voltage.
The Functional Diagram shows the monitoring blocks of
the LTC4242. The group of comparators in the system
control includes the UVLO, ON and EN comparators.
These comparators are used to determine if the external
conditions are valid prior to turning on the switches. But
firsttheundervoltagelockoutcircuit(UVLO)mustvalidate
IN
The threshold of the ACL is set at 2x the ECB threshold.
The ACL amplifier limits the current in the load by reduc-
ing the gate-to-source voltage of the external MOSFETs
in an active control loop. When an overcurrent condition
persists for more than 20µs, the MOSFETs are shut off to
prevent overheating. FAULT is latched low to signal that
an overcurrent condition has occurred on the external
MOSFETs controlling the main channels.
the input supplies and the main supply V and generate
CC
the power up initialization to the logic circuits.
The FON inverter in the system control is used for op-
erating the LTC4242 in diagnostic mode. In this mode
of operation, all pass transistors are forced to turn on,
ignoring the undervoltage, circuit breaker/current limit-
The AUX FET’s control circuitry has a circuit breaker that
trips at 550mA after 20µs. It also incorporates an active
current limit amplifier that would limit the current flow-
ing in the AUX FET to about 1.65A. A thermal shutdown
circuit shuts off the AUX FET when the die temperature
rises above 150°C. AUXFAULT is latched low to signal
ing status and input commands. However, if V drops
CC
below its UVLO voltage, all switches would be shut off,
regardless of FON.
U
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APPLICATIO S I FOR ATIO
The typical LTC4242 application is in a backplane or moth-
erboard that controls power to two PCI Express slots. The
device reports fault and power good status to the system
hot plug controller (HPC).
Board Presence Detect
InPCIExpresssystems, thesystemboardconnectoruses
two signals, PRSNT1 and PRSNT2, to detect the pres-
ence of a board and ensure a fully inserted board in the
connector as shown in Figure 2. PRSNT2 is routed to the
system HPC. Upon a board insertion into the connector,
a turn-on command is generated by the HPC to LTC4242
after a programmed HPC debounce delay, as shown in
Figure 1. Another method to generate the debounce delay
is through the delay network shown in Figure 3.
The basic LTC4242 application circuit is shown in Fig-
ure 1. Discussion begins with board presence detection
in a PCI Express system, the normal turn on and off
sequence, the various fault conditons and recovery from
fault situations. The force on operation is discussed next
followed by the considerations for PCB layout. External
component selection is discussed in detail in the Design
Example section.
4242f
11
LTC4242
U
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APPLICATIO S I FOR ATIO
SLOT A
Q1
R1
8mΩ
Si7336ADP
12V
5.5A
12V
Q2
R2
13mΩ
R5
10Ω
Si7336ADP
3.3V
3A
3.3V
R
3
3
G1
47Ω
SMBus
SMBus
R
R6
G2
C
G1
18Ω
10Ω
15nF
C
G2
33
32
31
30
8
7
6
5
47nF
R
S
12V
12V
12V
12V
3V
3V
3V
3V
GATE1 OUT1
IN1
SENSE1
GATE1
OUT1
IN1
SENSE1
33Ω
10
3.3V
V
CC
C1
1µF
9
4
29
2
3.3V
AUXIN1
AUXOUT1
375mA
PRSNT2
PRSNT1
MRL1
AUXON1
BD_PRST1
3
ON1
FON1
EN1
PWREN1
1
PCIe CONNECTOR ×1
BD_PRST1
PWRFLT1
28
19
18
GND
EN2
36
35
34
20
21
22
FAULT1
AUXFAULT1
PGOOD1
FAULT2
AUXPWRFLT1
PGOOD1
FON2
LTC4242G
HPC
PWRFLT2
AUXFAULT2
PGOOD2
AUXPWRFLT2
PGOOD2
BD_PRST2
SLOT B
PWREN2
MRL2
17
ON2
PRSNT2
PRSNT1
BD_PRST2
16
11
AUXON2
AUXIN2
27
3.3V
375mA
3.3V
AUXOUT2
12V
12V
12V
12V
3V
3V
3V
3V
IN2
23
SENSE2
24
GATE2
25
OUT2
26
IN2
SENSE2
13
GATE2
14
OUT2
15
3
3
SMBus
SMBus
12
R
R
G4
G3
47Ω
18Ω
C
C
G4
G3
R7
10Ω
R8
10Ω
47nF
15nF
3.3V
3A
3.3V
12V
R4
13mΩ
Q4
Si7336ADP
12V
5.5A
R3
8mΩ
Q3
Si7336ADP
PCIe CONNECTOR ×1
4242 F01
Figure 1. Typical PCI Express Application
4242f
12
LTC4242
U
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APPLICATIO S I FOR ATIO
PCI EXPRESS ADD-IN CARD
TRACE ON THE ADD-IN CARD
(ACTUAL TRACE ROUTING IS LEFT
UP TO THE BOARD DESIGNER)
GOLD FINGERS
MATE LAST/BREAK FIRST
PULL-UP
SYSTEM
BOARD
CONNECTOR
HOT PLUG
CONTROL
LOGIC
PRSNT1
PRSNT2
SYSTEM BOARD
4242 F02
Figure 2. Plug-In Card Insertion/Removal
OUT
LTC4242
V
OUT
9µA
R
D
47k
BD_PRSNT
ENn
+
–
LOAD
C
D
1.235V
33nF
GND
4242 F03
CONNECTOR PLUG-IN
CARD
MOTHERBOARD
Figure 3. RC Network to Generate Delay During Card Plug-In
When the board is removed, the power to the slot is dis-
abled after a delay of:
When PRSNT2 pulls low after insertion of a board, the
ENn pin goes low after a delay as determined by the
values of C and R . For plug-in debounce delay of 1ms
D
D
0.765CD
and R of 47k:
tDELAY2
=
s = 2.8ms
D
9
t
DELAY1 (ms)
43.5
CD =
µF = 0.023µF
Turn-On Sequence
The PCI Express power supplies are controlled by the
externalN-channelpasstransistors, Q1throughQ4, inthe
12V and 3.3V power paths, and internal pass transistors
Choose C to be 33nF.
D
4242f
13
LTC4242
U
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APPLICATIO S I FOR ATIO
for the 3.3V auxiliary power paths. Sense resistors R1 to
ENn
5V/DIV
R4 provide input for current fault detection. Resistors R
G1
AUXOUTn
5V/DIV
to R and capacitors C to C compensate the current
G4
G1
G4
controlloops.CapacitorsC toC alsocontroltheoutput
G1
G4
power-up rate and the inrush current while resistors R5
to R8 prevent high frequency oscillations in N-channel
MOSFETs, Q1 to Q4 respectively.
12V
OUTn
5V/DIV
3V
5V/DIV
OUTn
The following conditions must be satisfied before the
external and internal switches can be turned on.
1. The device’s power supply, V , must exceed its
CC
PGOODn
5V/DIV
undervoltage lockout threshold. To turn on the exter-
nal/internal switches, the main/auxiliary input supplies
must exceed their UVLO thresholds.
4242 F04
10ms/DIV
2. The EN pin must be pulled low to begin the start-up
sequence.
Figure 4. Normal Power-Up Sequence
When these initial conditions are satisfied, the ON pins are
checked.TheLTC4242featuresperslotONpins,theAUXON
and ON, to allow independent control of the main input
supplies (12V and 3.3V) and the 3.3V auxiliary supplies. If
the ON pin is high, the switches turn on. If ON is low, the
switchesturnonwhentheONpinisbroughthigh.Figure 4
shows all supplies turning on after EN goes low.
Turn-Off Sequence
The switches can be turned off by a variety of conditions.
1. The ON/AUXON pin going low would turn off the main/
internal switches.
2. EN going high turns off all switches.
3. A variety of fault conditions will turn off the switches.
These include supply undervoltage and overcurrent
circuit breaker faults.
Each of the external switches is turned on by charging
the GATE with a 9µA current source. The voltage at the
GATE pins rises with a slope equal to 9µA/C and the
G
4. When thermal shutdown activates, the internal switch
is shut off.
supply inrush current is set at C /C • 9µA, where C is
L
G
L
the capacitance at the supply output.
When ON goes low, the main switches are turned off with
a 1mA current pulling down the gate to ground. When
the main supplies are shut off, the PGOOD signal pulls
high and the outputs are discharged to ground through
internal switches. Similarly, when an auxiliary supply is
turned off, the AUXPGOOD signal pulls high and its output
is discharged to ground through internal switches. Figure
5 shows all supplies being turned off by EN going high.
The gate of the internal switch is slewed resulting in the
3.3V
supply output powering up at an internally set
AUX
rate of about 1.25V/ms.
The circuit breaker (ECB) of the input supplies is armed
after the input supplies clear UVLO. Once the supplies
have been turned on and the outputs are within tolerance,
PGOOD for the main input supplies and AUXPGOOD for
the auxiliary input supplies (available for the QFN only)
are pulled low.
4242f
14
LTC4242
U
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APPLICATIO S I FOR ATIO
FAULTn
5V/DIV
ENn
5V/DIV
AUXOUTn
5V/DIV
3V
OUTn
5V/DIV
12V
OUTn
5V/DIV
3V
GATEn
5V/DIV
3V
OUTn
5V/DIV
I
LOAD
3A/DIV
PGOODn
5V/DIV
4242 F06
4242 F05
5µs/DIV
100ms/DIV
Figure 6. Overcurrent Fault on 3.3V Output
Figure 5. Normal Power-Down Sequence
FAULTn
5V/DIV
Thermal Shutdown
Each of the two internal switches for the 3.3V auxiliary
suppliesisprotectedbyanindependentthermalshutdown
circuit. If the temperature of an internal switch reaches
150°C,theswitchshutsdownimmediatelyandAUXFAULT
is latched low. All other power switches are not affected.
The switch is allowed to turn on again by recycling the
AUXON pin low then high with the temperature falling
below 120°C.
3V
OUTn
5V/DIV
3V
GATEn
5V/DIV
I
LOAD
10A/DIV
Overcurrent Fault
The LTC4242 features dual level glitch tolerant protection
against overcurrent faults for all the supplies. The sense
resistor (both internal and external) voltage drop is moni-
tored by an electronic circuit breaker (ECB) comparator
andanactivecurrentlimit(ACL)amplifier. Intheeventthat
a supply’s current exceeds the ECB threshold, an internal
timerisstarted. Ifthesupplyisstillovercurrentafter20µs,
the ECB trips and the MOSFET turns off immediately, as
shown in Figure 6.
4242 F07
5µs/DIV
Figure 7. Short-Circuit Fault on 3.3V Output
During an output short circuit, the surge current must be
brought to a controlled level within the shortest amount of
time to protect the system. The LTC4242’s active current
limitentersahighcurrentprotectionmodethatimmediately
turns off the output MOSFET by pulling its gate-to-source
voltage to zero. Current in the output MOSFET drops from
tens of amps to zero in a few hundred nanoseconds. The
input voltage drops during the high current and then
spikes upwards due to lead parasitic inductances as the
Duringstart-up,asupplyoutputcouldbeshortedtoground
in the worst case. The inrush current would be limited to
the ACL threshold, which is 2x the ECB threshold, and the
part will latch off after 20µs.
4242f
15
LTC4242
U
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APPLICATIO S I FOR ATIO
its UVLO threshold for more than 38µs, all switches are
turned off. The switches are allowed to turn on when
AUXFAULTn
5V/DIV
AUXOUTn
5V/DIV
the supply voltages and V rise above their respective
CC
undervoltage thresholds.
AUXINn
5V/DIV
Power Good Fault
A power good fault occurs when any supply output drops
below its power good threshold for more than 20µs.
A power good fault on the main/AUX supplies causes
the PGOOD/AUXPGOOD to be pulled high. There are a
variety of conditions which must be satisfied for PGOOD/
AUXPGOOD to be asserted low:
I
LOAD
5A/DIV
1. The output voltage is above power good threshold
2. EN pin is low
4242 F08
5µs/DIV
Figure 8. Short-Circuit Fault on 3.3V
Output
AUX
3. The input voltage is above the undervoltage threshold
4. ON pin is high
MOSFET shuts off (see Supply Transients). The compen-
sation network R /C assists the gate voltage recovery.
The ACL limits the current level to 2x the ECB threshold
G
G
5. Thermal shutdown not activated
by regulating the gate voltage.
Resetting Faults
For the internal switch, the ACL limits the supply current
to about 3x the circuit breaker current level of 550mA.
Toresetanovercurrentfaultonthemainoutputs,bringON
low or the faulting supply below its undervoltage lockout
(UVLO) threshold. To reset an overcurrent or thermal
shutdown fault on the auxiliary output, bring AUXON low
or the auxiliary suppy below its UVLO threshold. Bringing
TheECBhasa20µsfilterdelaybeforelatchingofftoprevent
unnecessary resets of the system due to minor transient
surges. An overcurrent fault on any of the main outputs
(12V or 3.3V) latches off both main outputs without af-
fectingthe3.3Vauxiliaryoutput. Similarly, anovercurrent
fault on the 3.3V auxiliary output latches off the auxiliary
output, without affecting the main outputs.
V
below its UVLO threshold resets all overcurrent and
CC
thermal shutdown faults. The part cannot be reset when
fault overide, FON, is high.
Auto-Retry After a Fault
When there is a shorted load with significant supply lead
inductance, the supply pin voltage could collapse before
the ACL brings down the gate of the external MOSFET. In
this case, the undervoltage lockout circuit, with 18µs filter
time, turns off the pass MOSFETs.
As shown in Figure 9, the LTC4242 can be configured to
automatically retry after a fault condition by connecting
both the FAULT and ON pins together with an RC network.
The auto-retry circuit will attempt to restart the LTC4242
after a circuit breaker trip, as shown in the timing diagram
of Figure 10.
Undervoltage Fault
An undervoltage fault occurs when any of the input sup-
plies, 12V , 3V or AUXIN, falls below its undervoltage
RAUTO •CAUTO • 1.235– V
(
)
OL
IN
IN
tOFF
≈
threshold for more than 18µs. This turns off the switches
immediately. An undervoltage on the 3.3V auxiliary sup-
ply will not cause the main supplies to shut off and vice
versa. An undervoltage fault on any of the main supplies
2.065+RAUTO •9µA
For the component values shown, t = 3.3ms. Since the
OFF
duration of a short is less than 40µs in the worst case, the
auto-retry duty cycle is 1.3%.
shuts off both main supply switches. If V falls below
CC
4242f
16
LTC4242
U
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APPLICATIO S I FOR ATIO
R2
Q2
V
CC
Power Supply
13mΩ
Si7336ADP
3.3V
TheLTC4242derivesitspowerfromV .Abypasscapacitor
CC
of 1µF should be connected between this pin and ground.
If V is derived from the input supplies of 3V or AUXIN,
3V
GATE
LOAD
CC
IN
3V
3V
3V
SENSE
IN
OUT
EN
a lowpass filter shown in Figure 11 should be used.
R
AUTO
LTC4242*
200k
BD_PRST
This RC network allows the LTC4242 to ride through a
FAULT
ON
3V /AUXIN short-circuit transient without collapsing
IN
C
AUTO
GND
0.1µF
below the V UVLO threshold. AUXIN or 3V may have
CC
IN
4242 F09
narrowbuthighglitchesduetoparasiticinductance.Since
the absolute maximum rating for V is 7V compared to
*ADDITIONAL DETAILS OMITTED FOR CLARITY
CC
10V for AUXIN and 3V , the R and C1 values should be
IN
S
Figure 9. Auto-Retry Application
chosen to damp the peak voltage seen by V below 7V.
CC
3V
R
S
33
IN
1.235V
0.6V
AUXIN
OR
V
CC
C1
1 F
3V
IN
V
OL
ON/FAULT
4242 F11
V
TH
3V
GATE
Figure 11. RC Network for V Filtering
CC
3V – 3V
IN
Force ON Operation
SENSE
V
CB
4242 F10
t
When the FON pin is pulled high and EN is low, the
LTC4242 operates in the diagnostic mode. All the input
supplies’ power switches are forced to turn on, regardless
ofundervoltageconditionsontheinputsupplies, statusof
the ON pins and the fault latch. The contents in the fault
latch would be preserved during this time and no change
of state would occur after the part is configured to operate
in the diagnostic mode. If the output current exceeds the
ECB threshold, FAULT/AUXFAULT is pulled low immedi-
OFF
t
CB
Figure 10. Auto-Retry Timing
GATE Pin Voltage
The minimum gate drive voltage is 4.5V, therefore, logic
level N-channel MOSFETs should be used for the external
switches to maintain adequate gate enhancement. The
GATE pins are clamped at a typical value of 5.5V above
the respective OUT pins.
ately, but does not latch. The undervoltage lockout on V
CC
turns off all the switches, regardless of the status of FON.
During thermal shutdown, the internal switch is shut off to
prevent overheating, even if FON is high. The main power
switches remain on as FON is high. Care must be taken to
ensure the outputs are not short circuited since there is
no current limit mechanism in diagnostic mode.
Compensating the Active Current Loop
The active current limit circuit is compensated using the
resistorR andtheslewratecontrolcapacitorC .Thevalue
G
G
of C is selected based on the inrush current allowed. The
G
R valueshouldbeexperimentallydetermined.Asuggested
G
value range for R is between 10Ω and 100Ω.
G
4242f
17
LTC4242
U
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APPLICATIO S I FOR ATIO
Yet another mode of operation is the Force ON with cur-
rent limit mode. To enter this mode, pull both FON and
EN high. In this mode of operation, the ACLs are enabled
with the 20µs filter time disabled. The fault latch of the
In Hot Swap applications where load currents can be 10A,
narrow PCB tracks exhibit more resistance than wider
tracks and hence, operate at higher temperatures. Since
the sheet resistance of 1oz copper foil is approximately
0.5mΩ/square, track resistances and voltage drops add
up quickly in high current applications. Thus, to keep PCB
track resistance, voltage drop and temperature rise to a
minimum, the suggested trace width in these applica-
tions for 1oz copper foil is 0.03" for each ampere of DC
current.
AUXsupplycanbelatchediftheAUX’sI
isexceeded.
CBAUX
AUXFAULT indicates whether the AUX channel FET is on
or off. To enter normal operation, pull FON and EN low
and recycle the ON and AUXON pins.
PCB Layout Considerations
For proper operation of the LTC4242’s circuit breaker,
a Kelvin connection to the sense resistors is required.
The Kelvin sense PCB layout traces should be minimum
length, closed together, balanced and symmetrical to
minimize wiring errors. In addition, the PCB layout for the
sense resistors and the power MOSFETs should include
good thermal management techniques for optimal device
power dissipation. A recommended PCB layout for the
12V sense resistor and the power MOSFET is illustrated
in Figure 12.
In the majority of applications, it will be necessary to use
plated-through vias to make circuitry connections from
components layers to power and ground layers internal
to the PCB. For 1oz copper foil plating, a general rule is
1A of DC current per via making sure the via is properly
dimensioned so that solder completely fills any void.
Check with your PCB fabrication facility for via current
specifications.
4242f
18
LTC4242
U
W U U
APPLICATIO S I FOR ATIO
In system board applications, large bypass capacitors
(≥10µF) are recommended at each of the system input
supplies to minimize supply glitches as a result of large
inrush or fault currents.
So a value of 15nF and 47nF ( 10%) should suffice for
the 12V and 3.3V supplies respectively. The worst-case
1
t and inrush currents are tabulated in Table 3.
Table 3. Worst-Case t and Inrush Current
1
It is important to put C1, the bypass capacitor for the V
CC
VOLTAGE SUPPLY
t
t
MAX I
INRUSH
1(MIN)
1(MAX)
pin as close as possible between the V and GND pins.
CC
12V
3.3V
13ms
11ms
40ms
34ms
2.4A
0.4A
Design Example
For the internal switch, the slew rate (SR) at the 3.3V
AUX
Consider a PCI Express Hot Swap application example
with the following power supply requirements:
supply output is limited to 1.7V/ms max. The inrush cur-
rent can then be calculated according to:
Table 1. PCI Express Power Supply Requirements
I
= C
• SR
MAX
(3)
INRUSH(MAX)
LOAD
MAXIMUM SUPPLY
MAXIMUM LOAD
CAPACITANCE
SUPPLY VOLTAGE
CURRENT
Theinrushcurrentmustbelowerthan385mA(I
for proper start-up. Assuming a tolerance of 30% for the
load capacitance, the value of C
170µF.
)
CBAUX(MIN)
12V
3.3V
5.5A
3.0A
2000µF
1000µF
150µF
should not exceed
LOAD
3.3V
375mA
AUX
1. Select an R
SENSE
lower circuit breaker threshold limit, ΔV
value for each supply. Calculate the
SENSE
3. Next is the selection of MOSFETs for the 12V and 3.3V
maininputsupplies.TheSi7336ADP’sonresistanceisless
than 4mΩ at V = 4.5V, 25°C and it is a good choice for
3.3V and 12V main supplies.
R
value based on the maximum load current and the
. In
SENSE(CB)(MIN)
GS
a PCI Express connector, five pins are allocated for the
12V supply, three pins for the 3.3V supply and one pin for
3.3V . The current rating of a connector pin is 1.1A. If
Since the maximum load for the 3.3V supply is 3A, the
MOSFET may dissipate up to 36mW. The Si7336ADP
has a maximum junction-to-ambient thermal resistance
of 50°C/W. This gives a junction temperature of 51.8°C
when operating at a case temperature of 50°C. Accord-
ing to the Si7336ADP’s Normalized On-Resistance vs
Junction Temperature curve, the device’s on resistance
can be expected to increase by about 12% over its room
AUX
a 1% tolerance is assumed for the sense resistors, then
the following values of resistances should suffice:
Table 2. Sense Resistance Values
VOLTAGE SUPPLY
R
(1%)
I
I
SENSE
TRIP(MIN)
5.6A
TRIP(MAX)
6.9A
12V
8mΩ
3.3V
13mΩ
3.4A
4.3A
temperature value. Recalculation for steady-state R
2. Assumenoloadcurrentatstart-upandtheinrushcurrent
charges the load capacitance. Compute gate capacitance
with:
ON
and junction temperature yield approximately 4.5mΩ
and 52°C, respectively. The voltage drop across the 3.3V
sense resistor and series MOSFET at 3A and at 50°C PCB
temperature is less than 53mV.
IGATE(UP) • t1
CGATE
=
(2)
VOUT
t is the time to charge up the load capacitor.
The MOSFET dissipates power during inrush charging of
the output load capacitor. Assuming no load current, the
MOSFET’s dissipated power equals the final load capaci-
tor stored energy. Therefore, average MOSFET dissipated
power is:
1
With I
= 13µA and t = 10ms:
1
GATE(UP)(MAX)
a. For 12V Supply, C
= 11nF
= 39nF
GATE
b. For 3.3V Supply, C
CL • VO2UT
GATE
(4)
PON
=
2 • t1
4242f
19
LTC4242
U
W U U
APPLICATIO S I FOR ATIO
short enough to cause minimal increase in the junction-
to-ambient temperature of the MOSFETs, in the event of
powering up into short circuit or short circuiting after
power up. Therefore, in these events, it can be safely
assumed that the MOSFETs would have minimal thermal
stress on them.
Using P and t to look up the MOSFETs’ single pulse
ON
1
θ
from the manufacturer’s Transient Thermal
JA(MAX)
Impedance Graph, the worst-case junction-to-ambient
temperature rise occurs for the 12V MOSFET.
Table 4. MOSFET Power-Up Temperature Rise Calculation
VOLTAGE SUPPLY
P
ON
θ
ΔT
JA(MAX)
IftheLTC4242operatesinthediagnosticmode, usermust
ensure a safe joule heating limit of the external MOSFET.
The internal switch will be disabled once the temperature
reaches 150°C, thereby preventing overheating.
12V
3.3V
11W
0.5W
0.75°C/W
0.6°C/W
8.3°C
0.3°C
There is a 20µs filter time when large current of 2x circuit
breaker’s threshold can flow in the switches. This time is
4242f
20
LTC4242
U
TYPICAL APPLICATIO
4242f
21
LTC4242
U
PACKAGE DESCRIPTIO
G Package
36-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
12.50 – 13.10*
(.492 – .516)
1.25 0.12
5.3 – 5.7
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
7.8 – 8.2
7.40 – 8.20
(.291 – .323)
0.42 0.03
0.65 BSC
5
7
8
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
6
9 10 11 12 13 14 15 16 17 18
2.0
(.079)
MAX
5.00 – 5.60**
(.197 – .221)
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.25
(.0035 – .010)
0.55 – 0.95
(.022 – .037)
0.05
0.22 – 0.38
(.009 – .015)
TYP
(.002)
NOTE:
MIN
1. CONTROLLING DIMENSION: MILLIMETERS
G36 SSOP 0204
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
4242f
22
LTC4242
U
PACKAGE DESCRIPTIO
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701)
0.70 0.05
5.50 0.05
(2 SIDES)
4.10 0.05
(2 SIDES)
3.15 0.05
(2 SIDES)
PACKAGE
OUTLINE
0.25 0.05
0.50 BSC
5.15 0.05 (2 SIDES)
6.10 0.05 (2 SIDES)
7.50 0.05 (2 SIDES)
RECOMMENDED SOLDER PAD LAYOUT
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
3.15 0.10
(2 SIDES)
0.75 0.05
5.00 0.10
(2 SIDES)
37 38
0.00 – 0.05
0.40 0.10
PIN 1
TOP MARK
(SEE NOTE 6)
1
2
5.15 0.10
(2 SIDES)
7.00 0.10
(2 SIDES)
0.40 0.10
0.200 REF 0.25 0.05
0.50 BSC
R = 0.115
TYP
(UH) QFN 0205
0.200 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
0.75 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4242f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC4242
U
TYPICAL APPLICATIO
Hot Swap Application for Two Advanced Mezzanine Cards (AMC)
MODULE 1
PAYLOAD
POWER
SOURCE
0.008Ω
Si7336ADP
12V
5.6A
MANAGEMENT
POWER
0.4Ω
Si2306DS
3.3V
100mA
SOURCE
BD_PRSNT1
PS1
PS0
10Ω
10Ω
22Ω
CARRIER AMC
33nF
33nF
CARD
12V
12V
12V
12V
3V
3V
3V
3V
IN1
SENSE1
GATE1
OUT1
IN1
SENSE1
GATE1
OUT1
33Ω
1µF
V
CC
AUXFAULT1
AUXFAULT2
NC
AUXIN1
AUXIN2
ON1
PGOOD1
ON2
PGOOD2
FAULT1
FAULT2
AUXOUT1
AUXOUT2
LTC4242G
FON1
FON2
INTELLIGENT
PLATFORM
MANAGEMENT
CONTROLLER
AUXON1
AUXON2
EN1
EN2
BD_PRSNT1
BD_PRSNT2
GND
3V
3V
3V
3V
12V
12V
12V
SENSE2 GATE2
12V
IN2
SENSE2
GATE2
OUT2
IN2
OUT2
22Ω
33nF
MODULE 2
33nF
10Ω
10Ω
PS0
PS1
12V
5.6A
BD_PRSNT2
PAYLOAD
POWER
SOURCE
0.008Ω
Si7336ADP
MANAGEMENT
POWER
3.3V
100mA
0.4Ω
SOURCE
Si2306DS
CARRIER AMC
CARD
4242 TA03
RELATED PARTS
PART NUMBER
LTC4210
LTC4213
LTC4214
LTC4215
LTC4216
LT®4220
LTC4221
LTC4241
DESCRIPTION
COMMENTS
6-Lead SOT-23 Package
Hot Swap Contoller
No R
TM Electronic Circuit Breaker
Three Selectable Circuit Breaker Thresholds
Controls Supplies from 0V to –16V
SENSE
Negative Low Voltage Hot Swap Controller
2
Hot Swap Controller with I C Compatible Monitoring
Ultralow Voltage Hot Swap Controller
Dual Supply Hot Swap Controller
Dual Hot Swap Controller
2.9V to 15V, 8-Bit ADC Monitors Current and Voltages
Load Voltages from 0V to 6V
2.7V to 16V Operation
Power Sequencer with Dual Speed, Dual Level Fault Protection
3.3V Auxiliary Supply
PCI-Bus Hot Swap Controller
No R
is a trademark of Linear Technology Corporation.
SENSE
4242f
LT 1106 • PRINTED IN USA
24 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
© LINEAR TECHNOLOGY CORPORATION 2006
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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