LTC4291-1 [ADI]
4-Port IEEE 802.3bt PoE PSE Controller;
| 型号： | LTC4291-1 |
| 厂家： | 
ADI |
| 描述： | 4-Port IEEE 802.3bt PoE PSE Controller |
| 文件： | 总40页 (文件大小：1613K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4291-1/LTC4292
4-Port IEEE 802.3bt
PoE PSE Controller
FEATURES
DESCRIPTION
n
Four PSE Ports
The LTC®4291-1/LTC4292 chipset is a 4-port power
sourcing equipment (PSE) controller designed for use in
IEEE 802.3bt Type 3 and 4 compliant Power over Ethernet
(PoE) systems. The LTC4291-1/LTC4292 is designed to
power compliant 802.3af, 802.3at, and 802.3bt PDs. The
LTC4291-1/LTC4292 chipset delivers lowest-in-indus-
try heat dissipation by utilizing low RDS(ON) external
MOSFETs and 0.15Ω sense resistance per power channel.
A transformer-isolated communication protocol replaces
expensive opto-couplers and complex isolated 3.3V sup-
ply, resulting in significant BOM cost savings.
n
Two Power Channels per Port
n
n
Fully Compliant IEEE 802.3bt Type 3 and 4 PSE
n
Compliant Support for Type 1, 2, 3, and 4 PDs
Low Power Path Dissipation per Channel
n
150mΩ Sense Resistance
30mΩ or Lower MOSFET R
n
DS(ON)
n
n
Chipset Provides Electrical Isolation
n
Eliminates Optos and Isolated 3.3V Supply
Very High Reliability Multipoint PD Detection
n
Connection Check Distinguishes Single-
Signature and Dual-Signature PDs
Continuous, Dedicated Per-Port Power and Current
Monitoring
Advanced power management features include per-port
14-bit current monitoring, programmable current limit,
and versatile fast shutdown of preselected ports. Advanced
power management host software is available under a no-
cost license. PD detection uses a proprietary multipoint
detection mechanism ensuring excellent immunity from
false PD identification. Autoclass and 5-event physical
classification are supported. The LTC4291-1/LTC4292
n
n
Per-Port Power Policing
2
2
n
n
n
1MHz I C Compatible Serial Control Interface
Pin or I C Programmable PD Power Up to 71.3W
Available in a 40-Lead 6mm × 6mm (LTC4292) and
24-Lead 4mm × 4mm (LTC4291-1) QFN Packages
2
includes an I C serial interface operable up to 1MHz. The
LTC4291-1/LTC4292 is pin or I2C programmable to nego-
tiate PD delivered power up to 71.3W.
APPLICATIONS
n
PoE PSE Switches/Routers
PoE PSE Midspans
All registered trademarks and trademarks are the property of their respective owners.
n
TYPICAL APPLICATION
ꢀꢁꢂꢃꢄ
10Ω
0ꢀꢁꢂꢃ
ꢀꢁꢀꢂ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀ00ꢁ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
0ꢀꢁꢁꢂꢃ
ꢀ00ꢁ
ꢀ
ꢀꢀ
ꢀꢁꢂ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢀ
ꢀꢁ0
ꢀꢁRꢂꢃ0
ꢀꢁꢂꢃꢄꢅꢀꢂꢆ
ꢀꢁꢂ
ꢀꢁRꢂꢃꢄ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢁ
4PVALID
ꢀꢁꢂ
0.15Ω
100Ω
100Ω
ꢀꢁꢂꢃ
ꢀ
ꢀꢀ
ꢀ
ꢀ
ꢀꢁꢀꢂ
ꢀ
ꢀꢁꢂꢀꢁꢃꢄ
ꢀꢁꢁꢂꢃ
ꢀꢀ
ꢀꢁꢂ ꢃ ꢀ
RESET
ꢀꢁꢂꢃꢄꢅꢀꢂꢆ
RꢀꢁꢂꢃRꢀꢄꢅ
100Ω
100Ω
ꢀ
MSD
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
0ꢀꢁꢁꢂꢃ
ꢀ00ꢁ
ꢀꢁꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢆꢇꢆ
ꢀꢁꢂꢃꢄꢅꢄ
ꢀꢁꢂ
INT
ꢀ
100Ω
100Ω
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁꢀꢂ
ꢀ
ꢀꢀ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄꢅ
ꢀ
100Ω
100Ω
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢀ
ꢀꢁꢂ
ꢀꢁꢂ
0.15Ω
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀꢀ
ꢀꢁꢂ
0ꢀꢁꢁꢂꢃ
ꢀ
ꢀꢁꢂꢀꢁꢃꢄ
ꢀꢁꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ000ꢁꢂꢃꢄꢅꢆ
Rꢀꢁꢂ
ꢀꢁꢂꢀ
ꢀ
ꢀꢁꢁꢂꢃ
0
ꢀꢀ
0.22μF, 100V
0.15Ω
ꢀꢁ ꢂꢃ ꢄ ꢅꢂRꢆꢇꢈ
ꢀꢁꢂꢃꢄ
ꢀ
ꢀꢀ
ꢀꢁꢁꢂꢃ
Rev 0
1
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For more information www.analog.com
LTC4291-1/LTC4292
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 4)
(Note 1)
LTC4292
LTC4291-1
Supply Voltages
Supply Voltages
AGNDP – V ......................................... –0.3V to 80V
VSSK12, VSSK34 (Note 7)... V – 0.3V to V + 0.3V
V
– DGND ......................................... –0.3V to 3.6V
EE
DD
Digital Pins
EE
EE
Digital Pins
SCL, SDAIN, SDAOUT, INT, RESET, MSD, ADn, AUTO,
4PVALID, GPn .................DGND – 0.3V to V + 0.3V
PWRMD0, PWRMD1 ........ V – 0.3V to CAP2 + 0.3V
EE
DD
Analog Pins
Analog Pins
SENSEnM, GATEnM, OUTnM V – 0.3V to V + 80V
CAP1 (Note 13) ...........................–0.3V to DGND + 2V
EE
EE
EE
EE
EE
EE
CAP2 (Note 13) ...................... V – 0.3V to V + 5V
CPD, CND, DPD, DND ......DGND – 0.3V to V + 0.3V
DD
CPA, CNA, DPA, DNA..............V – 0.3V to V + 0.3
Operating Ambient Temperature Range
Operating Ambient Temperature Range
LTC4291I-1 ..........................................–40°C to 85°C
Junction Temperature (Note 2) ............................ 125°C
Storage Temperature Range .................. –65°C to 150°C
LTC4292I .............................................–40°C to 85°C
Junction Temperature (Note 2) ............................ 125°C
Storage Temperature Range .................. –65°C to 150°C
PIN CONFIGURATION
LTC4292
LTC4291-1
ꢅꢆꢇ ꢈꢉꢊꢋ
ꢇꢈꢉ ꢊꢋꢌꢍ
ꢃ0 ꢂꢦ ꢂꢥ ꢂꢤ ꢂꢖ ꢂꢄ ꢂꢃ ꢂꢂ ꢂꢁ ꢂꢀ
ꢑꢎꢅꢊꢀꢎ
ꢆꢌꢅꢀꢎ
ꢑꢎꢅꢊꢀꢣ
ꢆꢌꢅꢀꢣ
ꢈꢙꢙꢐꢀꢁ
ꢏꢎꢇꢁ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢖ
ꢤ
ꢥ
ꢦ
ꢂ0 ꢑꢎꢅꢊꢃꢣ
ꢁꢦ ꢆꢌꢅꢃꢣ
ꢀꢁ ꢀꢂ ꢀꢀ ꢀꢃ ꢀ0 ꢃꢄ
ꢑꢎꢅꢊꢃꢎ
ꢆꢌꢅꢃꢎ
ꢁꢥ
ꢁꢤ
ꢐꢖ0
ꢐꢖꢃ
ꢃ
ꢀ
ꢂ
ꢁ
ꢡ
ꢦ
ꢃꢆ ꢚꢑꢕ
ꢚꢖꢐꢋꢜ
ꢃꢅ
ꢃꢦ
ꢃꢀ
ꢊꢊ
ꢁꢖ ꢈꢙꢙꢐꢂꢃ
ꢎꢑꢜꢔꢇ
ꢈ
ꢐꢖꢀ
ꢚꢖꢐꢈꢎꢇ
ꢀꢡ
ꢖꢓꢜꢖ
ꢁꢄ
ꢐꢖꢂ
ꢃꢡ INT
ꢑꢎꢅꢊꢁꢎ
ꢆꢌꢅꢁꢎ
ꢑꢎꢅꢊꢁꢣ
ꢁꢃ ꢑꢎꢅꢊꢂꢣ
ꢁꢂ ꢆꢌꢅꢂꢣ
ꢁꢁ ꢑꢎꢅꢊꢂꢎ
ꢁꢀ ꢆꢌꢅꢂꢎ
ꢖꢓꢜꢖ
4PVALID
RESET
ꢃꢁ
ꢃꢂ ꢖꢜꢑ
ꢅ
ꢆ
ꢄ ꢃ0 ꢃꢃ ꢃꢀ
ꢆꢌꢅꢁꢣ ꢀ0
ꢀꢀ ꢀꢁ ꢀꢂ ꢀꢃ ꢀꢄ ꢀꢖ ꢀꢤ ꢀꢥ ꢀꢦ ꢁ0
ꢎꢏ ꢉꢐꢑꢒꢐꢓꢌ
ꢀꢁꢔꢕꢌꢐꢖ ꢗꢁꢘꢘ × ꢁꢘꢘꢙ ꢉꢕꢐꢚꢇꢋꢑ ꢛꢏꢜ
ꢠ ꢃꢀꢡꢢꢑꢣ θ ꢠ ꢁꢢꢑꢤꢍꢣ θ ꢠ ꢁꢅꢢꢑꢤꢍ
ꢇ
ꢝꢞꢐꢟ
ꢝꢑ
ꢝꢐ
ꢌꢟꢉꢈꢚꢌꢖ ꢉꢐꢖ ꢗꢉꢋꢜ ꢀꢡꢙ ꢋꢚ ꢖꢓꢜꢖꢣ ꢞꢎꢚꢇ ꢥꢌ ꢚꢈꢕꢖꢌRꢌꢖ ꢇꢈ ꢉꢑꢥ
ꢌꢍ ꢇꢎꢏꢐꢎꢑꢊ
ꢃ0ꢒꢓꢊꢎꢔ ꢕꢖꢗꢗ × ꢖꢗꢗꢘ ꢇꢓꢎꢙꢅꢉꢏ ꢚꢛꢜ
ꢅ
ꢟ ꢀꢁꢄꢠꢏꢡ θ ꢟ ꢁꢠꢏꢢꢋꢡ θ ꢟ ꢂꢂꢠꢏꢢꢋ
ꢍꢝꢎꢞ
ꢍꢏ ꢍꢎ
ꢊꢞꢇꢆꢙꢊꢔ ꢇꢎꢔ ꢕꢇꢉꢜ ꢃꢀꢘ ꢉꢙ ꢈ ꢡ ꢝꢌꢙꢅ ꢣꢊ ꢙꢆꢓꢔꢊRꢊꢔ ꢅꢆ ꢇꢏꢣ
ꢊꢊ
Rev 0
2
For more information www.analog.com
LTC4291-1/LTC4292
ORDER INFORMATION
LEAD FREE FINISH
LTC4291IUF-1#PBF
LTC4292IUJ#PBF
TAPE AND REEL
PART MARKING PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 85°C
LTC4291IUF-1#TRPBF
LTC4292IUJ#TRPBF
42911
24-Lead (4mm × 4mm) Plastic QFN
40-Lead (6mm × 6mm) Plastic QFN
LTC4292UJ
–40°C to 85°C
Contact the factory for parts specified with wider operating temperature ranges.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGNDP – VEE = 54V and VDD – DGND = 3.3V unless otherwise noted.
(Notes 3 and 4)
SYMBOL
PARAMETER
CONDITIONS
AGNDP – V
MIN
TYP
MAX
UNITS
Main PoE Supply Voltage
EE
l
l
For IEEE Type 3 Compliant Output
For IEEE Type 4 Compliant Output
51
53
57
57
V
V
l
l
Undervoltage Lock-Out
AGNDP – V
20
25
3.3
2.7
1.84
4.3
9
30
V
V
EE
V
V
Supply Voltage
V
V
V
V
– DGND
3.0
3.6
DD
DD
DD
Undervoltage Lock-Out
– DGND
V
DD
V
V
Internal Regulator Supply Voltage
Internal Regulator Supply Voltage
– DGND
V
CAP1
CAP1
CAP2
– V
V
CAP2
EE
l
l
l
I
V
EE
V
EE
V
DD
Supply Current
Supply Resistance
Supply Current
(AGNDP – V ) = 55V
15
12
15
mA
kΩ
mA
EE
EE
R
(AGNDP – V ) < 15V
EE
EE
I
(V – DGND) = 3.3V
DD
10
DD
Detection/Connection Check
l
l
Forced Current
First Point, AGNDP – V
= 9V
OUTnM
220
143
240
160
260
180
µA
µA
OUTnM
Second Point, AGNDP – V
= 3.5V
Forced Voltage
AGNDP – V
First Point
, 5µA ≤ I
≤ 500µA
OUTnM
OUTnM
7
3
8
4
9
5
V
V
l
l
Second Point
l
l
l
Detection/Connection Check Current
AGNDP – V
AGNDP – V
AGNDP – V
= 0V
0.8
0.9
mA
OUTnM
Compliance
V
Detection/Connection Check Voltage
Compliance
, Open Port
, C = 0.15µF (Note 7)
10.4
12
V
OC
OUTnM
Detection/Connection Check Voltage
Slew Rate
0.01
V/µs
OUTnM PORT
l
l
Min. Valid Signature Resistance
Max. Valid Signature Resistance
15.5
27.5
17
18.5
32
kΩ
kΩ
29.7
Rev 0
3
For more information www.analog.com
LTC4291-1/LTC4292
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGNDP – VEE = 54V and VDD – DGND = 3.3V unless otherwise noted.
(Notes 3 and 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Classification
l
l
V
Classification Voltage
AGNDP – V
, 0mA ≤ I ≤ 50mA
OUTnM
16.0
53
20.5
67
V
CLASS
OUTnM
Classification Current Compliance
Classification Threshold Current
V
= AGNDP
61
mA
OUTnM
l
l
l
l
l
Class Signature 0 – 1
Class Signature 1 – 2
Class Signature 2 – 3
Class Signature 3 – 4
Class Signature 4 – Overcurrent
AGNDP – V , 0.1mA ≤ I ≤ 5mA
CLASS
5.5
6.5
14.5
23
33
48
7.5
mA
mA
mA
mA
mA
13.5
21.5
31.5
45.2
15.5
24.5
34.9
50.8
l
l
V
Classification Mark State Voltage
Mark State Current Compliance
7.5
53
9
10
67
V
MARK
OUTnM
V
= AGNDP
61
mA
OUTnM
Gate Driver
l
l
GATE Pin Pull-Down Current
Port Off, V
Port Off, V
= V + 5V
0.4
mA
mA
GATEnM
GATEnM
EE
= V + 1V
0.08
0.12
30
EE
GATE Pin Fast Pull-Down Current
GATE Pin On Voltage
V
V
= V + 5V
mA
V
GATEnM
GATEnM
EE
l
– V , I
= 1µA
8
12
14
EE GATEnM
Output Voltage Sense
Power Good Threshold Voltage
l
l
V
PG
V
– V
EE
2
2.4
2.8
V
OUTnM
OUT Pin Pull-Up Resistance to AGNDP 0V ≤ (AGNDP – V
) ≤ 5V
OUTnM
300
500
700
kΩ
Current Sense
V
Overcurrent Sense Voltage,
Single-Signature PD
V
– VSSKn
SENSEnM
CUT-2P
Class 1, CUTn[6:0] = 45h
Class 2, CUTn[6:0] = 48h
Class 3, CUTn[6:0] = 52h
Class 4, CUTn[6:0] = 62h
Class 5, CUTn[6:0] = 5Fh
Class 6, CUTn[6:0] = 67h
Class 7, CUTn[6:0] = 6Ch
l
l
l
l
l
l
l
l
13.5
21.6
47.5
92.0
84.0
105
14.1
22.5
50.5
96.0
87.0
110
14.6
23.4
53.5
100.0
91.0
114
mV
mV
mV
mV
mV
mV
mV
mV
119
124
129
Class 8, CUTn[6:0] = 74h (Note 12)
140
146
152
Overcurrent Sense Voltage,
Dual-Signature PD
V
– VSSKn
SENSEnM
Class 1, CUTn[6:0] = 45h
Class 2, CUTn[6:0] = 48h
Class 3, CUTn[6:0] = 52h
Class 4, CUTn[6:0] = 62h
Class 5, CUTn[6:0] = 74h (Note 12)
l
l
l
l
l
13.5
21.6
47.5
92.0
140
14.1
22.5
50.5
96.0
146
14.6
23.4
53.5
100.0
152
mV
mV
mV
mV
mV
V
Active Current Limit,
Single-Signature PD
V
– V < 10V
OUTnM EE
LIM-2P
Class 1 – Class 3, LIMn = 80h
Class 4 – Class 6, LIMn = C0h
Class 7, LIMn = D0h
l
l
l
l
61.2
122
153
168
63.6
128
159
175
67.3
135
169
185
mV
mV
mV
mV
Class 8, LIMn = E9h (Note 12)
Active Current Limit,
Dual-Signature PD
V
– V < 10V
EE
OUTnM
Class 1 – Class 3, LIMn = 80h
Class 4, LIMn = C0h
l
l
l
61.2
122
168
63.6
128
175
67.3
135
185
mV
mV
mV
Class 5, LIMn = E9h (Note 12)
V
V
Active Current Limit, Inrush
DC Disconnect Sense Voltage
AGNDP – V
> 30V (Note 17)
OUTnM
INRUSH-2P
l
l
LIMn = 80h
LIMn = 08h
61.2
30.6
63.6
31.8
67.3
33.7
mV
mV
V
– VSSKn
HOLD-2P
SENSEnM
CUTn[7] (Dis) Bit = 0
l
l
0.31
0.76
0.53
1.13
0.74
1.49
mV
mV
CUTn[7] (Dis) Bit = 1 (Note 12)
Rev 0
4
For more information www.analog.com
LTC4291-1/LTC4292
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGNDP – VEE = 54V and VDD – DGND = 3.3V unless otherwise noted.
(Notes 3 and 4)
SYMBOL
PARAMETER
CONDITIONS
– V – V
LIM
MIN
TYP
MAX
UNITS
l
l
V
Short-Circuit Sense
V
20
50
80
mV
SC
SENSEnM
EE
Port Current Readback
Full-Scale Range
(Notes 7, 15, 16)
– VSSKn, VSSKn = V (Note 15)
1.018
62.1
V
LSB Weight
V
61.0
63.5
µV/LSB
SENSEnM
EE
Averaging Period
FILTER_TYPE Bit = 1
FILTER_TYPE Bit = 0 (Note 7)
100
1000
ms
ms
Update Interval
(Note 7)
100
ms
Port Power Readback
2
Full-Scale Range
LSB Weight
(Notes 7, 15, 16)
83.8
V
2
l
(V
– VSSKn) × (AGNDP – V
)
EE
4.992
5.115
5.235
mV /LSB
SENSEnM
VSSKn = V (Note 15)
EE
Averaging Period
Update Interval
FILTER_TYPE Bit = 1
100
ms
ms
FILTER_TYPE Bit = 0 (Note 7)
1000
(Note 7)
100
ms
System Voltage Readback
Full-Scale Range
LSB Weight
(Note 7)
82
V
l
AGNDP – V
9.8
2.2
3.4
10.1
10.3
mV/LSB
EE
Averaging Period
FILTER_TYPE Bit = 1
FILTER_TYPE Bit = 0 (Note 7)
100
1000
ms
ms
Update Interval
(Note 7)
100
ms
Digital Interface
l
l
l
V
Digital Input Low Voltage
ADn, RESET, MSD, GPn, AUTO, 4PVALID (Note 6)
SCL, SDAIN (Note 6)
0.8
1.0
V
V
V
ILD
2
I C Input Low Voltage
V
Digital Input High Voltage
Digital Output Voltage Low
(Note 6)
IHD
l
l
I
I
= 3mA, I = 3mA
= 5mA, I = 5mA
0.4
0.7
V
V
SDAOUT
SDAOUT
INT
INT
Internal Pull-Up to V
ADn, RESET, MSD, GPn
AUTO, 4PVALID
50
50
kΩ
kΩ
DD
Internal Pull-Down to DGND
PWRMD
l
l
PWRMD Digital Input Low Voltage
PWRMD Digital Input High Voltage
Internal Pull Up to CAP2
V
V
– V
– V
0.8
V
V
PWRMDn
PWRMDn
EE
EE
PWRMD0, PWRMD1
50
320
12
kΩ
PSE Timing Characteristics (Note 7)
l
l
l
l
l
l
l
t
t
t
t
t
t
t
Detection Time
Beginning to End of Detection
500
ms
ms
ms
ms
ms
ms
ms
DET
Classification Reset Duration
Class Event Duration
15
6
CLASS_RESET
CEV
20
0.1
105
Class Event Turn On Duration
Long Class Event Duration
C
= 0.6µF
PORT
CEVON
LCE
88
6
Class Event I
Measurement Timing
CLASS
CLASS
Long Class Event I
Timing
Measurement
CLASS
6
75
CLASS_LCE
l
t
Autoclass I
Measurement Timing
88
ms
CLASS_ACS
CLASS
Rev 0
5
For more information www.analog.com
LTC4291-1/LTC4292
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGNDP – VEE = 54V and VDD – DGND = 3.3V unless otherwise noted.
(Notes 3 and 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
t
Mark Event Duration (Except Last Mark (Note 11)
Event)
6
8.6
12
ms
ME1
l
l
t
t
Last Mark Event Duration
(Note 11)
6
20
ms
ms
ME2
Power On Delay, Auto Mode
From End of Valid Detect to End of Valid Inrush
(Note 14)
400
1.6
3.5
0.3
PON
l
l
l
t
t
t
Autoclass Power Measurement Start
Autoclass Power Measurement End
From End of Inrush to Beginning of Autoclass
Power Measurement
1.4
3.1
s
s
s
AUTO_PSE1
From End of Inrush to End of Autoclass Power
Measurement
AUTO_PSE2
Autoclass Average Power Sliding
Window
0.15
0.2
AUTO_WINDOW
l
l
t
t
Fault Delay
From Power On Fault to Next Detect
1.0
52
1.3
59
1.5
66
s
ED
Maximum Current Limit Duration
During Inrush
ms
START
l
l
t
Maximum Overcurrent Duration After
Inrush
52
59
66
ms
%
CUT
Maximum Overcurrent Duty Cycle
5.8
6.3
6.7
t
Maximum Current Limit Duration After (Note 12)
LIM
l
l
Inrush
Type 3, t
Type 4, t
= 8h
= 5h
10
6
12
8
14
10
ms
ms
LIMn
LIMn
l
t
t
t
Maintain Power Signature (MPS) Pulse Current Pulse Width to Reset Disconnect Timer
1.6
3.6
ms
MPS
Width Sensitivity
(Note 8)
l
Maintain Power Signature (MPS)
Dropout Time
(Note 5)
320
350
2
380
ms
DIS
Masked Shut Down Delay
6.5
3
µs
s
MSD
2
l
l
I C Watchdog Timer Duration
1.5
3
Minimum Pulse Width for Masked Shut
Down
µs
l
Minimum Pulse Width for RESET
4.5
µs
2
I C Timing (Note 7)
l
l
l
l
l
l
l
l
l
l
l
l
l
l
f
t
t
t
t
t
t
t
t
t
t
t
Clock Frequency
1
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
SCLK
Bus Free Time
Figure 5 (Note 9)
Figure 5 (Note 9)
Figure 5 (Note 9)
Figure 5 (Note 9)
Figure 5 (Note 9)
Figure 5 (Note 9)
Figure 5 (Note 9)
Figure 5 (Note 9)
Figure 5 (Note 9)
Figure 5 (Note 9)
Figure 5 (Note 9)
(Notes 9, 10)
480
240
480
240
60
1
2
3
4
5
5
6
7
8
r
Start Hold Time
SCL Low Time
SCL High Time
SDAIN Data Hold Time
Data Clock to SDAOUT Valid
Data Set-Up Time
130
80
Start Set-Up Time
240
240
Stop Set-Up Time
SCL, SDAIN Rise Time
SCL, SDAIN Fall Time
Fault Present to INT Pin Low
Stop Condition to INT Pin Low
120
60
f
150
1.5
(Notes 9, 10)
Rev 0
6
For more information www.analog.com
LTC4291-1/LTC4292
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGNDP – VEE = 54V and VDD – DGND = 3.3V unless otherwise noted.
(Notes 3 and 4)
SYMBOL
PARAMETER
CONDITIONS
(Note 9)
MIN
TYP
MAX
1.5
UNITS
µs
l
l
ARA to INT Pin High Time
SCL Fall to ACK Low
(Note 9)
130
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. With the exception of (V
DGND), exposure to any Absolute Maximum Rating condition for extended
periods may affect device reliability and lifetime.
Note 9: Values Measured at V and V
Note 10: If a fault condition occurs during an I C transaction, the INT pin
will not be pulled down until a stop condition is present on the I C bus.
Note 11: Load characteristics of the LTC4292 during Mark: 7V <
.
ILD
IHD
2
–
DD
2
Note 2: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 140ºC when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 3: All currents into device pins are positive; all currents out of device
pins are negative.
Note 4: The LTC4292 operates with a negative supply voltage (with
respect to AGNDP). To avoid confusion, voltages in this data sheet are
referred to in terms of absolute magnitude.
(AGNDP – V
) < 10V or I
< 50µA.
OUTnM
OUTnM
Note 12: See the LTC4291 Software Programming documentation for
information on serial bus usage and device configuration and status
registers.
Note 13: Do not source or sink current from CAP1 and CAP2.
Note 14: For single-signature PDs, t
detect on either power channel. For dual-signature PDs, t
from the end of valid detect on the same power channel.
Note 15: Port current and port power measurements depend on sense
resistor value (0.15Ω typical). See External Component Selection for
details.
is measured from end of valid
PON
is measured
PON
Note 5: t is the same as t
defined by IEEE 802.3.
DIS
MPDO
Note 6: The LTC4291-1 digital interface operates with respect to DGND. All
logic levels are measured with respect to DGND.
Note 7: Guaranteed by design, not subject to test.
Note 8: The IEEE 802.3 specification allows a PD to present its
Note 16: The full-scale range for each power channel is half of the port
full-scale range.
Note 17: See Inrush Control for details on inrush threshold selection.
Maintain Power Signature (MPS) on an intermittent basis without being
disconnected. In order to stay powered, the PD must present the MPS for
t
within any t
time window.
MPS
MPDO
Rev 0
7
For more information www.analog.com
LTC4291-1/LTC4292
TYPICAL PERFORMANCE CHARACTERISTICS
802.3bt Single–Signature
Power On Sequence
802.3bt Single–Signature
802.3bt Dual–Signature
Power On Sequence
Classification and Power On
0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁꢂꢃꢃ ꢄ
ꢀꢁꢂꢁꢃꢂꢄꢅꢆ ꢇ
ꢀꢁꢂꢂꢃꢀꢄꢅꢁꢂ
ꢀꢁꢂꢀꢃ
ꢀꢁꢂꢁꢃꢂꢄꢅꢆ ꢇ
ꢀꢁꢂꢂꢃꢀꢄꢅꢁꢂ
ꢀꢁꢂꢀꢃ
ꢀꢁꢂꢃꢃꢄꢅꢄꢀꢂꢆꢄꢇꢈ
ꢀꢁꢂꢃꢃꢄꢅꢄꢀꢂꢆꢄꢇꢈ
ꢀꢁꢂꢃꢃꢄꢅꢄꢀꢂꢆꢄꢇꢈ
ꢀꢁꢂꢃR
ꢀꢁ
ꢀꢁꢂꢃR
ꢀꢁꢂꢃR
ꢀꢁ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁ
ꢀ
ꢀ
ꢀꢀ
ꢀ
ꢀꢀ
ꢀꢀ
ꢀꢁꢂꢃꢃ ꢄ0ꢃ
ꢀꢁꢂꢃꢃ ꢄ0ꢁ
ꢀꢁꢂꢃꢃ ꢄ0ꢅ
ꢀ00ꢁꢂꢃꢄꢅꢆ
ꢀ0ꢁꢂꢃꢄꢅꢆ
ꢀ00ꢁꢂꢃꢄꢅꢆ
802.3bt Single–Signature
Class Probe and Demotion
Open Circuit Detection
Classification Current Compliance
0
ꢀꢁ
0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁꢂꢃꢃ ꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄꢁ
ꢀꢁ
ꢀRꢁꢂꢃ
ꢀꢁꢂꢃꢃ ꢄ
ꢀꢁꢂꢃꢃ ꢀꢁꢂꢃꢃ ꢄ
Rꢀꢁꢀꢂ ꢀꢁꢂꢃꢄꢅꢃꢆ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄꢁ
ꢀꢁꢂꢃR
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁ
ꢀ
ꢀꢀ
ꢀꢁꢂꢃꢃ ꢄ0ꢅ
ꢀꢁꢂꢃꢃ ꢄ0ꢀ
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0ꢁꢂꢃꢄꢅꢆ
ꢀ0ꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢃꢄꢅꢄꢀꢂꢆꢄꢇꢈ ꢀꢉRRꢊꢈꢆ ꢋꢌꢂꢍ
ꢀꢁꢂꢃꢃ ꢄ0ꢅ
Power On Current Limits
Single–Signature
Power On Current Limits
Dual–Signature
Inrush Current Limits (Note 17)
ꢀ00
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢂ
ꢀ00
ꢀꢁ
ꢀꢁꢁꢁ
ꢀꢀꢁꢂ
ꢀ000
ꢀꢁꢁ
ꢀꢀꢁ
ꢀ00
ꢀꢀꢀ
ꢀꢁꢂ
0
ꢀ00
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢂ
ꢀ00
ꢀꢁ
ꢀꢁꢁꢁ
ꢀꢀꢁꢂ
ꢀ000
ꢀꢁꢁ
ꢀꢀꢁ
ꢀ00
ꢀꢀꢀ
ꢀꢁꢂ
0
ꢀ00
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢂ
ꢀ00
ꢀꢁ
ꢀꢁꢁꢁ
ꢀꢀꢁꢂ
ꢀ000
ꢀꢁꢁ
ꢀꢀꢁ
ꢀ00
ꢀꢀꢀ
ꢀꢁꢂ
0
ꢀꢁꢂꢃ ꢄ ꢅ0ꢆ
ꢀꢁꢂꢃꢃ ꢄ ꢅꢆ ꢇ
ꢀꢁꢂꢃꢃ ꢄ ꢅꢆ ꢇ
ꢀꢁꢂꢃꢃ ꢄ
ꢀꢁꢂꢃꢃ ꢄ ꢅꢆ ꢇ
ꢀꢁꢂꢃꢃ ꢄ
ꢀꢁꢂꢃꢃ ꢄ
ꢀꢁꢂꢃ ꢄ 0ꢅꢆ
R
= 0.15Ω
ꢀꢁꢂꢀꢁ
ꢀꢁꢂꢃꢃ ꢄ
R
ꢀꢁꢂꢀꢁ
= 0.15Ω
R
ꢀꢁꢂꢀꢁ
= 0.15Ω
ꢀ0
ꢀ0
ꢀ0
ꢀꢁ
ꢀꢁ
ꢀꢁ
0
0
0
0
ꢀꢀ
ꢀꢀ
ꢀꢀ
ꢀꢀ
ꢀꢀ
0
ꢀꢀ
ꢀꢀ
ꢀꢀ
ꢀꢀ
ꢀꢀ
ꢀꢀ
0
ꢀꢀ
ꢀꢀ
ꢀꢀ
ꢀꢀ
ꢀꢀ
ꢀꢁꢂꢃꢄ ꢅ ꢆ ꢀꢁꢂ
ꢀꢀ
ꢀꢁꢂꢃꢄ ꢅ ꢆ ꢀꢁꢂ
ꢀꢁꢂꢃꢄ ꢅ ꢆ ꢀꢁꢂ
ꢀꢀ
ꢀꢁꢂꢃꢃ ꢄ0ꢅ
ꢀꢁꢂꢃꢃ ꢄ0ꢂ
ꢀꢁꢂꢃꢃ ꢄ0ꢅ
Rev 0
8
For more information www.analog.com
LTC4291-1/LTC4292
TYPICAL PERFORMANCE CHARACTERISTICS
ILIM-2P vs Temperature
ICUT-2P vs Temperature
ꢀꢁꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢀ
ꢀꢀꢁ0
ꢀꢀꢁ0
ꢀꢀꢁ0
ꢀꢀꢁ0
ꢀꢀꢁ0
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁꢂ
ꢀꢁ0
ꢀ0ꢀꢁ
ꢀꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁꢂꢃ ꢄ ꢅꢆꢇ
= 0.15Ω
ꢀꢁꢂꢃ ꢄ ꢅꢆꢇ
R
R
ꢀꢁꢂꢀꢁ
= 0.15Ω
ꢀꢁꢂꢀꢁ
ꢀꢁꢂꢃꢄ ꢅ ꢆ
ꢀꢀ
ꢀꢁ0 ꢀꢁ0
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0 ꢀ00
ꢀꢁ0 ꢀꢁ0
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0 ꢀ00
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢃ ꢄꢃ0
ꢀꢁꢂꢃꢃ ꢄꢃꢃ
Voltage Readback ADC vs
Temperature
Power Readback ADC vs
Temperature
Current Readback ADC vs
Temperature
ꢀꢀꢁ0
ꢀꢁꢂꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂ0
ꢀꢁꢂꢁ
ꢀꢁꢂꢂ
ꢀꢁꢀꢂ
ꢀꢁꢀꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢁꢂ
ꢀꢁꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢀꢂ
ꢀꢁꢀꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢂ
ꢀꢁ0ꢂ
ꢀꢁꢂꢃꢄ ꢅ ꢆ ꢈ ꢉꢉꢆ
ꢇꢇ
ꢀꢁꢂꢃꢄ ꢅ ꢆ ꢈ ꢉꢉꢆ
ꢇꢇ
ꢀꢁꢂꢀꢁꢃꢄ ꢅ ꢆꢀꢀꢇꢃ ꢈ ꢉꢊꢉꢋꢆ
ꢀꢁꢂꢀꢁꢃꢄ ꢅ ꢆꢀꢀꢇꢃ ꢈ ꢉꢊꢉꢋꢆ
ꢀꢀꢁꢂ
ꢀꢀꢁꢂ
ꢀꢀ0ꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂꢀ
ꢀꢁꢂꢁ
ꢀꢁꢂꢃ
ꢀꢁꢀꢂ
ꢀꢁꢁꢂ
ꢀꢁꢂ0
ꢀꢁ0 ꢀꢁ0
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0 ꢀ00
ꢀꢁ0 ꢀꢁ0
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0 ꢀ00
ꢀꢁ0 ꢀꢁ0
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0 ꢀ00
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢃ ꢄꢃꢅ
ꢀꢁꢂꢃꢃ ꢄꢃꢀ
ꢀꢁꢂꢃꢃ ꢄꢃꢁ
Temporary Short Circuit on
Channel 1B
Powering Up into 180µF Load
ꢀꢁꢂꢃ ꢄꢅ
ꢀꢁRRꢂꢃꢄ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃꢄ
ꢀ0ꢁꢂꢃꢄꢁ
ꢀꢁꢂꢃꢄꢅ
ꢀ0ꢁꢂꢃꢄꢁ
ꢀ
ꢁꢁ
ꢀꢁꢂꢃ ꢄꢅꢀꢀꢆ ꢇꢈꢂRꢉꢊꢃ
ꢀ
ꢁꢁ
ꢀꢁꢂꢃꢃꢄꢅ
ꢀꢁRRꢂꢃꢄ
ꢀ00ꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆꢇ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀꢁRRꢂꢃꢄ
ꢀ0ꢁꢂꢃꢄꢁ
ꢀꢁꢂꢁꢃ
ꢀꢁꢂꢃꢄꢁ
ꢀ0ꢁꢂꢃꢄꢁ
ꢀ
ꢁꢁ
ꢀꢁꢂꢃꢄ
ꢀ0ꢁꢂꢃꢄꢁ
ꢀꢁꢂ ꢃꢄ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢃ ꢄꢃꢅ
ꢀꢁꢂꢃꢃ ꢄꢃꢅ
ꢀ00ꢁꢂꢃꢄꢅꢆ
Rev 0
9
For more information www.analog.com
LTC4291-1/LTC4292
TYPICAL PERFORMANCE CHARACTERISTICS
VDD Supply Current vs
Temperature
VEE Supply Current vs Voltage
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢀ
ꢀ0
ꢀ0ꢁ0
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢀ
ꢀꢁ0
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁ0ꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁ0ꢂꢃ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢀ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢂꢂꢃꢄ ꢅꢆꢃꢇꢈꢉꢊ ꢋꢅꢌ
ꢀ0 ꢀꢀ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀ0
ꢀ
ꢀꢀ
ꢀꢁꢂꢃꢄ ꢅ ꢆ ꢀꢁꢂ
ꢀꢀ
ꢀꢁꢂꢃꢃ ꢄꢃꢅ
ꢀꢁꢂꢃꢃ ꢄ0ꢃꢅ
TEST TIMING DIAGRAMS
ꢇꢊꢃꢊꢈꢃꢎꢁꢉ
ꢈꢁꢉꢉꢊꢈꢃꢎꢁꢉ
ꢈꢓꢊꢈꢔ
ꢈꢋꢌꢍꢍꢎꢏꢎꢈꢌꢃꢎꢁꢉ
ꢃꢂRꢉ ꢁꢉ
ꢐ
ꢇꢊꢃ
ꢏꢁRꢈꢊꢇꢑ
ꢀꢁꢋꢃꢌꢒꢊ
ꢏꢁRꢈꢊꢇꢑꢈꢂRRꢊꢉꢃ
0ꢀ
ꢖꢙꢜꢀ
ꢐ
ꢅꢊꢘ
ꢐ
ꢅꢊꢖ
ꢐ
ꢅꢊꢘ
ꢀ
ꢁꢂꢃꢄꢅ
ꢀ
ꢁꢈ
ꢀ
ꢅꢌRꢔ
ꢘꢚꢙꢚꢀ
ꢖ0ꢙꢚꢀ
ꢀ
ꢈꢋꢌꢍꢍ
ꢐ
ꢐ
ꢋꢈꢊ
ꢋꢈꢊ
ꢐ
ꢈꢊꢀ
ꢐ
ꢈꢊꢀ
ꢆꢇ
ꢈꢁꢉꢉꢊꢈꢃꢊꢇ
ꢐ
ꢈꢊꢀꢁꢉ
ꢐ
ꢈꢋꢌꢍꢍꢛRꢊꢍꢊꢃ
ꢀ
ꢊꢊ
ꢐ
ꢍꢃꢌRꢃ
ꢐ
ꢆꢁꢉ
INT
ꢕꢖꢗꢘꢘ ꢏ0ꢘ
Figure 1. Detect, Class and Turn-On Timing in Auto or Semi-Auto Modes
Rev 0
10
For more information www.analog.com
LTC4291-1/LTC4292
TEST TIMING DIAGRAMS
ꢀ
ꢁꢂꢃꢄꢅꢆ
0ꢀ
ꢀ
ꢇꢈꢉꢄꢅꢆ
ꢀ
ꢉꢎ ꢀ
ꢋꢋ
ꢊꢋꢌꢊꢋꢍꢃ
ꢓ
ꢕ ꢓ
ꢊꢉꢔRꢉ ꢇꢈꢉ
INT
ꢏꢅꢐꢑꢑ ꢒ0ꢅ
Figure 2. Current Limit Timing
ꢀ
ꢄꢅꢃꢄꢅꢆꢁ
ꢀ
ꢁꢂꢃ
ꢇꢈ ꢀ
ꢅꢅ
INT
ꢉ
ꢉ
ꢊꢂꢄ
ꢁꢋꢄ
ꢌꢍꢎꢏꢏ ꢐ0ꢑ
Figure 3. DC Disconnect Timing
ꢀ
ꢁꢂꢃꢄꢅꢆ
ꢀ
ꢄꢄ
ꢇ
MSD
MSD
ꢈꢉꢊꢋꢋ ꢌ0ꢈ
Figure 4. Shut Down Delay Timing
ꢅ
ꢅ
ꢉ
ꢈ
ꢅ
ꢅ
ꢊ
ꢏ
ꢀꢁꢂ
ꢀꢃꢄ
ꢅ
ꢅ
ꢅ
ꢍ
ꢅ
ꢎ
ꢅ
ꢋ
ꢌ
ꢇ
ꢏꢇꢐꢆꢆ ꢑ0ꢋ
ꢅ
ꢆ
Figure 5. I2C Interface Timing
Rev 0
11
For more information www.analog.com
LTC4291-1/LTC4292
I2C TIMING DIAGRAMS
ꢀꢁꢂ
ꢀꢃꢄ
ꢄꢃꢋ ꢄꢃꢆ ꢄꢃꢈ ꢄꢃ0 Rꢎꢏ ꢄꢁꢐ ꢄꢌ ꢄꢊ ꢄꢍ ꢄꢅ ꢄꢋ ꢄꢆ ꢄꢈ ꢄ0 ꢄꢁꢐ ꢃꢌ ꢃꢊ ꢃꢍ ꢃꢅ ꢃꢋ ꢃꢆ ꢃꢈ ꢃ0 ꢄꢁꢐ
0
ꢈ
0
ꢀꢑꢄRꢑ ꢒꢓ
ꢔꢄꢀꢑꢕR
ꢄꢁꢐ ꢒꢓ
ꢀꢂꢄꢖꢕ
ꢄꢁꢐ ꢒꢓ
ꢀꢂꢄꢖꢕ
ꢄꢁꢐ ꢒꢓ
ꢀꢂꢄꢖꢕ
ꢀꢑꢚꢛ ꢒꢓ
ꢔꢄꢀꢑꢕR
ꢉRꢄꢔꢕ ꢈ
ꢀꢕRꢗꢄꢂ ꢒꢘꢀ ꢄꢃꢃRꢕꢀꢀ ꢒꢓꢑꢕ
ꢉRꢄꢔꢕ ꢆ
RꢕꢙꢗꢀꢑꢕR ꢄꢃꢃRꢕꢀꢀ ꢒꢓꢑꢕ
ꢉRꢄꢔꢕ ꢋ
ꢃꢄꢑꢄ ꢒꢓꢑꢕ
ꢅꢆꢇꢈꢈ ꢉ0ꢊ
Figure 6. Writing to a Register
ꢀꢁꢂ
ꢀꢃꢄ
ꢄꢃꢆ ꢄꢃꢇ ꢄꢃꢅ ꢄꢃ0 Rꢌꢍ ꢄꢁꢎ ꢄꢈ ꢄꢉ ꢄꢊ ꢄꢋ ꢄꢆ ꢄꢇ ꢄꢅ ꢄ0 ꢄꢁꢎ
0
ꢄꢃꢆ ꢄꢃꢇ ꢄꢃꢅ ꢄꢃ0 Rꢌꢍ ꢄꢁꢎ ꢃꢈ ꢃꢉ ꢃꢊ ꢃꢋ ꢃꢆ ꢃꢇ ꢃꢅ ꢃ0 ꢄꢁꢎ
0
ꢅ
0
ꢅ
0
ꢀꢏꢄRꢏ ꢐꢑ
ꢒꢄꢀꢏꢓR
ꢄꢁꢎ ꢐꢑ
ꢀꢂꢄꢔꢓ
ꢄꢁꢎ ꢐꢑ
ꢀꢂꢄꢔꢓ
Rꢓꢘꢓꢄꢏꢓꢃ
ꢀꢏꢄRꢏ ꢐꢑ ꢒꢄꢀꢏꢓR
ꢄꢁꢎ ꢐꢑ
ꢀꢂꢄꢔꢓ
ꢙꢗ ꢄꢁꢎ ꢐꢑ
ꢒꢄꢀꢏꢓR
ꢀꢏꢗꢘ ꢐꢑ
ꢒꢄꢀꢏꢓR
ꢖRꢄꢒꢓ ꢅ
ꢀꢓRꢚꢄꢂ ꢐꢛꢀ ꢄꢃꢃRꢓꢀꢀ ꢐꢑꢏꢓ
ꢖRꢄꢒꢓ ꢇ
RꢓꢜꢚꢀꢏꢓR ꢄꢃꢃRꢓꢀꢀ ꢐꢑꢏꢓ
ꢖRꢄꢒꢓ ꢅ
ꢀꢓRꢚꢄꢂ ꢐꢛꢀ ꢄꢃꢃRꢓꢀꢀ ꢐꢑꢏꢓ
ꢖRꢄꢒꢓ ꢇ
ꢃꢄꢏꢄ ꢐꢑꢏꢓ
ꢋꢇꢕꢅꢅ ꢖ0ꢈ
Figure 7. Reading from a Register
ꢀꢁꢂ
ꢀꢃꢄ
0
ꢈ
0
ꢄꢃꢋ ꢄꢃꢆ ꢄꢃꢈ ꢄꢃ0 Rꢏꢐ
ꢉRꢄꢕꢖ ꢈ
ꢄꢁꢑ
ꢃꢌ ꢃꢍ ꢃꢎ ꢃꢅ ꢃꢋ ꢃꢆ ꢃꢈ ꢃ0
ꢄꢁꢑ
ꢀꢒꢙꢜ ꢓꢔ
ꢕꢄꢀꢒꢖR
ꢀꢒꢄRꢒ ꢓꢔ
ꢕꢄꢀꢒꢖR
ꢄꢁꢑ ꢓꢔ
ꢀꢂꢄꢗꢖ
ꢘꢙ ꢄꢁꢑ ꢓꢔ
ꢕꢄꢀꢒꢖR
ꢉRꢄꢕꢖ ꢆ
ꢃꢄꢒꢄ ꢓꢔꢒꢖ
ꢀꢖRꢚꢄꢂ ꢓꢛꢀ ꢄꢃꢃRꢖꢀꢀ ꢓꢔꢒꢖ
ꢅꢆꢇꢈꢈ ꢉ0ꢊ
Figure 8. Reading the Interrupt Register (Short Form)
ꢀꢁꢂ
ꢀꢃꢄ
0
0
0
ꢈ
ꢈ
0
0
Rꢋꢌ
ꢄꢁꢍ
0
ꢈ
0
ꢄꢃꢊ ꢄꢃꢆ ꢄꢃꢈ ꢄꢃ0
ꢈ
ꢄꢁꢍ
ꢀꢎꢕꢖ ꢏꢐ
ꢑꢄꢀꢎꢒR
ꢀꢎꢄRꢎ ꢏꢐ
ꢑꢄꢀꢎꢒR
ꢄꢁꢍ ꢏꢐ
ꢀꢂꢄꢓꢒ
ꢔꢕ ꢄꢁꢍ ꢏꢐ
ꢑꢄꢀꢎꢒR
ꢉRꢄꢑꢒ ꢈ
ꢄꢂꢒRꢎ Rꢒꢀꢖꢕꢔꢀꢒ ꢄꢃꢃRꢒꢀꢀ ꢏꢐꢎꢒ
ꢉRꢄꢑꢒ ꢆ
ꢀꢒRꢗꢄꢂ ꢏꢘꢀ ꢄꢃꢃRꢒꢀꢀ ꢏꢐꢎꢒ
ꢅꢆꢇꢈꢈ ꢉ0ꢇ
Figure 9. Reading from Alert Response Address
Rev 0
12
For more information www.analog.com
LTC4291-1/LTC4292
PIN FUNCTIONS
LTC4292
AGNDP (Pin 25): Analog Ground. Connect AGNDP to the
return for the V supply through a 10Ω resistor.
EE
V
(Pins 31, 33, 40, Exposed Pad Pin 41): Main PoE
EE
Supply Input. Connect to a –51V to –57V supply, relative
DNA (Pin 36): Data Transceiver Negative Input Output
(Analog). Connect to DND through a data transformer.
to AGNDP. Voltage depends on PSE Type (Type 3 or 4).
GATEnM (Pins 1, 3, 7, 9, 22, 24, 28, 30): Gate Drive,
Port n, Channel M. Connect GATEnM to the gate of
the external MOSFET for port n, channel M. When the
MOSFET is turned on, the gate voltage is driven to
DPA (Pin 37): Data Transceiver Positive Input Output
(Analog). Connect to DPD through a data transformer.
CNA (Pin 38): Clock Transceiver Negative Input Output
(Analog). Connect to CND through a data transformer.
12V (typ) above V . During a current limit condition, the
EE
CPA (Pin 39): Clock Transceiver Positive Input Output
(Analog). Connect to CPD through a data transformer.
voltage at GATEnM will be reduced to maintain constant
current through the external MOSFET. If the fault timer
expires, GATEnM is pulled down, turning the MOSFET off
and raising a port n fault event. If the channel is unused,
the GATEnM pin must be floated.
VSSK12 (Pin 5): Kelvin Sense to V . Connect to sense
EE
resistor common node for ports 1 and 2 through a 0.15Ω
resistor. Connect to AGNDP through a 0.22μF, 100V
capacitor. Do not connect directly to VEE plane. See Layout
Requirements.
OUTnM (Pins 2, 4, 8, 10, 21, 23, 27, 29): Output Voltage
Monitor, Port n, Channel M. Connect OUTnM to the output
channel. A current limit foldback circuit limits the power
dissipation in the external MOSFET by reducing the cur-
rent limit threshold when the drain-to-source voltage
exceeds 10V. The port n power good event is raised when
VSSK34 (Pin 26): Kelvin Sense to V . Connect to sense
EE
resistor common node for ports 3 and 4 through a 0.15Ω
resistor. Connect to AGNDP through a 0.22μF, 100V
capacitor. Do not connect directly to VEE plane. See Layout
Requirements.
the voltage from OUTnM to V drops below 2.4V (typ).
EE
A 500k resistor is connected internally from OUTnM to
AGNDP when the channel is idle. If the channel is unused,
the OUTnM pin must be floated.
Common Pins
NC, DNC (LTC4291-1 Pins 7, 13; LTC4292 Pins 32, 34,
35): All pins identified with “NC” or “DNC” must be left
unconnected.
CAP2 (Pin 6): Analog Internal 4.3V Power Supply Bypass
Capacitor. Connect a 0.22µF ceramic cap to V .
EE
LTC4291-1
PWRMDn (Pins 11, 20): Maximum Power Mode Input.
Logic input signals between V and V + 4.3V for config-
AD0 (Pin 1): Address Bit 0. Tie the address pins high or
EE
EE
2
uration of maximum output power per-port in auto mode.
See Auto Mode Maximum PSE Power section. Internally
pulled up to CAP2.
low to set the I C serial address to which the LTC4291-1
responds. The address will be (010A A A A )b. Internally
3 2 1 0
pulled up to V .
DD
SENSEnM (Pins 12, 13, 14, 15, 16, 17, 18, 19): Current
Sense Input, Port n, Channel M. SENSEnM monitors
the external MOSFET current via a 0.15Ω sense resistor
between SENSEnM and VSSKn. Whenever the voltage
across the sense resistor exceeds the overcurrent detection
threshold VCUT-2P, the current limit fault timer counts up. If
the voltage across the sense resistor reaches the current
AD1 (Pin 2): Address Bit 1. See AD0.
AD2 (Pin 3): Address Bit 2. See AD0.
AD3 (Pin 4): Address Bit 3. See AD0.
4PVALID (Pin 6): 4-Pair Valid Input, Active Low. When
low, the LTC4291-1/LTC4292 will not apply power to a
port unless both pairsets present a valid signature. When
high, the LTC4291-1/LTC4292 will power any pairset pre-
senting a valid signature, regardless of the other pairset.
Internally pulled down to DGND.
limit threshold V
, the GATEnM pin voltage is lowered
LIM-2P
to maintain constant current in the external MOSFET. See
Applications Information for further details. If the channel
is unused, the SENSEnM pin must be tied to V .
EE
Rev 0
13
For more information www.analog.com
LTC4291-1/LTC4292
PIN FUNCTIONS
CPD (Pin 8): Clock Transceiver Positive Input Output
(Digital). Connect to CPA through a data transformer.
SDAIN (Pin 17): Serial Data Input. High impedance data
input for the I2C serial interface bus. The LTC4291-1
uses two pins to implement the bidirectional SDA func-
CND (Pin 9): Clock Transceiver Negative Input Output
(Digital). Connect to CNA through a data transformer.
2
tion to simplify opto isolation of the I C bus. To imple-
ment a standard bidirectional SDA pin, tie SDAOUT and
SDAIN together. See Applications Information for more
information.
DPD (Pin 10): Data Transceiver Positive Input Output
(Digital). Connect to DPA through a data transformer.
DND (Pin 11): Data Transceiver Negative Input Output
SCL (Pin 18): Serial Clock Input. High impedance clock
2
(Digital). Connect to DNA through a data transformer.
input for the I C serial interface bus. The SCL pin should
2
be connected directly to the I C SCL bus line. SCL must
VDD (Pins 12, 20): VDD IO Power Supply. Connect to
a 3.3V power supply relative to DGND. VDD must be
bypassed to DGND near the LTC4291-1 with at least a
0.1μF capacitor.
2
be tied high if the I C serial interface bus is not used.
CAP1 (Pin 19): Core Power Supply Bypass Capacitor.
Connect a 1µF capacitance to DGND for the internal 1.8V
regulator bypass. Do not use other capacitor values.
RESET (Pin 14): Reset Input, Active Low. When RESET is
low, the LTC4291-1/LTC4292 is held inactive with all ports
off and all internal registers reset. When RESET is pulled
high, the LTC4291-1/LTC4292 begins normal operation.
RESET can be connected to an external capacitor or RC
network to provide a power turn-on delay. Internal filtering
of RESET prevents glitches less than 1μs wide from reset-
AUTO (Pin 21): Auto Mode Input, Active High. When high,
the LTC4291-1 detects, classifies and powers up valid
PDs without host interaction. AUTO determines the state
of the internal registers when the LTC4291-1 is reset or
comes out of UVLO (see LTC4291 Software Programming
documentation). The state of these register bits can sub-
sequently be changed via the I2C interface. Internally
pulled down to DGND.
ting the LTC4291-1/LTC4292. Internally pulled up to V .
DD
INT (Pin 15): Interrupt Output, Open Drain. INT will pull
low when any one of several events occur in the LTC4291-
1. It will return to a high impedance state when bits 6 or
7 are set in the Reset PB register (1Ah). The INT signal
can be used to generate an interrupt to the host proces-
sor, eliminating the need for continuous software polling.
Individual INT events can be disabled using the INT Mask
register (01h). See LTC4291 Software Programming
documentation for more information. INT is only updated
GP1 (Pin 22): General Purpose Digital Input Output for
customer applications. Referenced to DGND.
GP0 (Pin 23): General Purpose Digital Input Output for
customer applications. Referenced to DGND.
MSD (Pin 24): Maskable Shutdown Input, Active Low.
When pulled low, all ports that have their corresponding
mask bit set in the mconf register (17h) will be reset.
Internal filtering of the MSD pin prevents glitches less
than 1μs wide from resetting ports. The MSD Pin Mode
register can configure the MSD pin polarity. Internally
2
between I C transactions.
SDAOUT (Pin 16): Serial Data Output, Open Drain Data
2
Output for the I C Serial Interface Bus. The LTC4291-1
pulled up to V .
DD
uses two pins to implement the bidirectional SDA func-
2
tion to simplify opto isolation of the I C bus. To imple-
DGND (Pin 5, Exposed Pad Pin 25): Digital Ground. DGND
ment a standard bidirectional SDA pin, tie SDAOUT and
SDAIN together. See Applications Information for more
information.
should be connected to the return from the V supply.
DD
Rev 0
14
For more information www.analog.com
LTC4291-1/LTC4292
APPLICATIONS INFORMATION
OVERVIEW
PD delivered power from 25.5W to 71.3W, enabling IEEE-
compliant high power PD applications.
Power over Ethernet, or PoE, is a standard protocol for
sending DC power over copper Ethernet data wiring.
The IEEE group that administers the 802.3 Ethernet data
standards added PoE powering capability in 2003. This
original PoE standard, known as 802.3af, allowed for 48V
DC power at up to 13W. 802.3af was widely popular, but
13W was not adequate for some applications. In 2009,
the IEEE released a new standard, known as 802.3at or
The LTC4291-1/LTC4292 delivers power over two power
channels. Each pairset is driven by a dedicated power
channel. In this data sheet, the term “channel” refers to
the PSE circuitry assigned to a corresponding pairset. For
the purposes of this document, the terms channel and
pairset may be considered interchangeable.
In addition, IEEE 802.3bt enables substantially lower
Maintain Power Signature (MPS) currents, resulting in
significantly lower standby power consumption. This
allows new and emerging government or industry standby
regulations to be met using standard PoE components.
+
PoE , increasing the voltage and current requirements to
provide 25.5W of delivered power.
The IEEE standard also defines PoE terminology. A device
that provides power to the network is known as a PSE,
or power sourcing equipment, while a device that draws
power from the network is known as a PD, or powered
device. PSEs come in two types: Endpoints (typically net-
work switches or routers), which provide data and power;
and Midspans, which provide power but pass through
data. Midspans are typically used to add PoE capabil-
ity to existing non-PoE networks. PDs are typically IP
phones, wireless access points, security cameras, and
similar devices.
LTC4291-1/LTC4292 Product Overview
The LTC4291-1/LTC4292 is a fifth generation PSE control-
ler that implements four PSE ports in either an Endpoint
or Midspan application. Virtually all necessary circuitry
is included to implement an IEEE 802.3bt compliant PSE
design, requiring a pair of external power MOSFETs and
sense resistors per port; these minimize power loss com-
pared to alternative designs with onboard MOSFETs, and
increase system reliability.
++
PoE Evolution
The LTC4291-1/LTC4292 chipset implements a propri-
etary isolation scheme for inter-chip communication. This
architecture substantially reduces BOM cost by replacing
expensive opto-isolators and isolated power supplies with
a single low-cost transformer.
+
Even during the development of the IEEE 802.3at (PoE )
25.5W standard, it became clear there was a significant
and increasing need for more than 25.5W of delivered
power. In 2013, the 802.3bt task force was formed to
develop a standard capable of increasing delivered PD
power.
The LTC4291-1/LTC4292 offers advanced fifth genera-
tion PSE features including a configurable interrupt sig-
nal triggered by per-port events, per-channel power on
control and fault telemetry, per-port current monitoring,
The primary objective of the task force is to use all four
pairs of the Ethernet cable as opposed to the two pair
power utilized by 802.3at. Using all four pairs allows for
at least twice the delivered power over existing Ethernet
cables. Further, the amount of current per two pairs
(known as a pairset) has been increased while maintain-
ing the Ethernet data signal integrity. 802.3bt increases
V
monitoring, one second rolling current, voltage, and
EE
port power averaging, and two general purpose input/
output pins.
Rev 0
15
For more information www.analog.com
LTC4291-1/LTC4292
APPLICATIONS INFORMATION
VEE and port current measurements are performed simul-
taneously, providing fully coherent port power calcula-
tions. The reported port power calculations enable coher-
ent and precise per-port power monitoring.
PD presents the same valid signature resistor to both
pairsets simultaneously. A dual-signature PD pres-
ents two fully independent valid detection signatures,
one to each pairset.
n
n
PoE BASICS
Type 3 single-signature PDs request exactly one of six
possible power levels: 3.84W, 6.49W, 13W, 25.5W,
40W, or 51W.
Common Ethernet data connections consist of two or
four twisted pairs of copper wire (commonly known
as Ethernet cable), transformer-coupled at each end to
avoid ground loops. PoE systems take advantage of this
coupling arrangement by applying voltage between the
center-taps of the data transformers to transmit power
from the PSE to the PD without affecting data transmis-
sion. Figures 10 and 11 show high level PoE system
schematics.
Type 3 dual-signature PDs request exactly one of four
possible power levels on each pairset: 3.84W, 6.49W,
13W, or 25.5W. The total PD requested power is the
sum of the requested power on both pairsets.
n
Type 3 PD Classes overlap with Type 1 and 2 Classes
in order to provide additional Type 3 feature sets at
lower power levels.
To avoid damaging legacy data equipment that does not
expect to see DC voltage, the PoE standard defines a
protocol that determines when the PSE may apply and
remove power. Valid PDs are required to have a specific
25k common-mode resistance at their input. When such
a PD is connected to the cable, the PSE detects this sig-
nature resistance and applies power. When the PD is
later disconnected, the PSE senses the open circuit and
removes power. The PSE also removes power in the event
of a current fault or short circuit.
n
n
Type 4 single-signature PDs request exactly one of
two possible power levels: 62W or 71.3W.
Type 4 dual-signature PDs request exactly 35.6W on
at least one pairset and one of five possible power lev-
els on the other pairset: 3.84W, 6.49W, 13W, 25.5W,
or 35.6W. The total PD requested power is the sum
of the requested power on both pairsets.
n
Classification is extended to a possible maximum
of five class events. The additional events allow for
unique identification of existing and new PD Classes.
When a PD is detected, the PSE looks for a classification
signature that tells the PSE the maximum power the PD
will draw. The PSE can use this information to allocate
power among several ports, to police the current con-
sumption of the PD, or to reject a PD that will draw more
power than the PSE has available.
n
n
Type 3 and 4 PSEs issue a long first class event to
advertise Type 3 and 4 feature support to attached PDs.
Lower standby power is enabled by shortening the
length of the maintain power signature pulse (short
MPS). The PD duty cycle drops from ~23% to ~2%. A
PD is allowed to present short MPS if the PSE issues
a long first class event.
New in 802.3bt
The 802.3bt draft introduces several new features:
n
Power management is augmented by Autoclass, an
optional feature for 802.3bt PSEs and PDs. In an
Autoclass system the maximum PD power is mea-
sured and reported to the PSE host, enabling the PSE
to reclaim output power not used by the PD appli-
cation and losses in the Ethernet cabling (Table 1).
See Autoclass section and LTC4291 Software
Programming documentation for details.
n
Type 3 and Type 4 PSEs may provide power over all
four pairs (both pairsets), depending on connected
PD characteristics.
n
Type 3 and Type 4 PDs are required to be capable of
receiving power over all four pairs (both pairsets).
n
Type 3 and 4 PDs can be formed as either a single-
signature PD or dual-signature PD. A single-signature
Rev 0
16
For more information www.analog.com
LTC4291-1/LTC4292
APPLICATIONS INFORMATION
ꢀ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀ
ꢀ
ꢀꢁꢂꢁ ꢃꢁꢄRꢅ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢁ
ꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ ꢂ
ꢀꢁꢂꢃ
ꢅ
ꢀ
ꢀ
ꢇ
ꢈꢉꢊ
ꢀꢁ
ꢀ
ꢀ
ꢆ
ꢀꢁꢂ
ꢃꢄꢅꢂꢆꢇꢀꢈꢀꢁꢃꢄꢅꢂꢆꢇꢆ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀ
ꢀꢁꢂꢁ ꢃꢁꢄRꢅ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀ
ꢀ
ꢀ
ꢀꢀ
ꢀ000ꢁꢂꢃꢄꢅꢆ
ꢀ000ꢁꢂꢃꢄꢅꢆ
Rꢀꢁꢂ
Rꢀꢁꢂ
ꢀꢁꢂꢃꢃ ꢄꢃ0
ꢀꢁꢂꢃ
Figure 10. Power over Ethernet Single-Signature PD System Diagram
ꢀ
ꢀ
ꢅ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢇ
ꢈꢉꢊ
ꢀꢁꢂ
ꢀ
ꢀ
ꢆ
ꢀꢁꢂꢁ ꢃꢁꢄRꢅ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢁ
ꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ ꢂ
ꢀꢁꢂꢃ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂ
ꢃꢄꢅꢂꢆꢇꢀꢈꢀꢁꢃꢄꢅꢂꢆꢇꢆ
ꢀꢁꢂ
ꢀꢁꢂ
ꢅ
ꢈꢉꢊ
ꢆ
ꢇ
ꢀꢁꢂ
ꢀ
ꢀ
ꢀꢁꢂꢁ ꢃꢁꢄRꢅ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀ
ꢀ
ꢀ
ꢀꢀ
ꢀ000ꢁꢂꢃꢄꢅꢆ
ꢀ000ꢁꢂꢃꢄꢅꢆ
Rꢀꢁꢂ
Rꢀꢁꢂ
ꢀꢁꢂꢃꢃ ꢄꢃꢃ
ꢀꢁꢂꢃ
Figure 11. Power over Ethernet Dual-Signature PD System Diagram
Rev 0
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APPLICATIONS INFORMATION
Table 1. IEEE-Specified Power Allocations, Single-Signature PD
Special Compatibility Mode Notes
PSE OUTPUT
POWER
ALLOCATED
CABLING LOSS
PD INPUT
POWER
2
n
As with prior generations, each I C address provides
status and control for four PoE ports. Each port reg-
ister slice provides port control and status as well as
channel A vs B control and status.
PD CLASS
1
2
3
4
5
6
7
8
4W
6.7W
14W
30W
45W
60W
75W
90W
0.16W
0.21W
1W
3.84W
6.49W
13W
n
Certain status registers, e.g. Port Status and Power
Status, relate to a channel state, as opposed to port
state and are split into three copies; a generalized port
state, channel A state and channel B state.
4.5W
5W
25.5W
40W
9W
51W
13W
18.7W
62W
71.3W
n
Certain command registers, e.g., Power-on pushbutton,
likewise are bifurcated to allow per-channel control.
BACKWARD COMPATIBILITY
OPERATING MODES
The LTC4291-1/LTC4292 may be configured as an
802.3bt-compliant PSE, either Type 3 or Type 4. While
802.3bt PSEs cannot identify as an 802.3at Type 1 or
Type 2 PSE, there is no loss in PSE functionality; all
802.3bt-compliant PSEs are fully backwards compatible
with existing 802.3at Type 1 and Type 2 PDs as shown
in Table 2. In addition to full compatibility, 802.3bt PSEs
extend support for lower standby power, enhanced cur-
rent limit timing, and dynamic power management to all
PD Types (as supported by the PD application).
The LTC4291-1/LTC4292 includes four independent
ports, each of which can operate in one of three modes:
manual, semi-auto, or auto. A fourth mode, shutdown,
disables the port (see Table 3).
Table 3. Operating Modes
AUTOMATIC
AUTO
DETECT/
THRESHOLD
ASSIGNMENT
MODE
PIN OPMD CLASS
POWER-UP
Enabled
at Reset
1
0
0
11b
11b
10b
Automatically
Yes
Yes
No
Auto
Table 2. PSE Maximum Delivered Power, Per-Port
Host
Enabled
Automatically
Upon Request
DEVICE
PSE
STANDARD
802.3at
802.3bt
Host
Enabled
Semi-auto
TYPE
1
2
3
4
Once
Upon
1
2
3
4
13W
13W
13W
13W
Manual
0
0
01b
00b
Upon Request
Disabled
No
No
802.3at
802.3bt
13W*
25.5W 25.5W
51W
13W* 25.5W* 51W*
25.5W
51W
Request
PD
13W* 25.5W*
Shutdown
Disabled
71.3W
*Indicates PD allocated less power than requested.
In manual mode, the port waits for instructions from the
host system before taking any action. It runs a single
detection, or detection and classification cycle when com-
manded to by the host, and reports the result in its Port
Status register. The host system can command the port
to apply or remove power at any time.
Software register map compatibility with LTC4266 and
LTC4271-based PSEs has been maintained to the extent
possible. LTC4291-based PSEs utilize two channels to
control a single PSE port. This multiplicity of channel
status and control requires extensions to the existing
register map.
In semi-auto mode, the port repeatedly attempts to detect
and classify any PD attached to it. It reports the status of
these attempts back to the host, and waits for a command
from the host before applying power to the port. The host
must enable detection and classification.
For register map details please contact Analog Devices
to request the LTC4291 Software Programming
documentation.
Rev 0
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APPLICATIONS INFORMATION
Auto mode operates the same as semi-auto mode except
it will automatically apply power to the port if detec-
tion and classification are successful. Auto mode will
Table 4. Typical Auto Mode Power On Thresholds,
Single-Signature PD
PER-CHANNEL
PER-PORT
autonomously set the I
, I
, and P
values
CLASS
I
I
P
CUT-4P
LIM-2P
CUT-4P
CUT-2P
LIM-2P
based on the Class reCsUuTlt-.2PThis operational mode may
be entered by setting AUTO high at reset or by changing
the OPMD state to Auto. See Auto Mode Maximum PSE
Power section.
1
2
3
4
5
6
7
8
94mA
150mA
338mA
638mA
581mA
731mA
825mA
975mA
425mA
425mA
425mA
850mA
850mA
850mA
1063mA
1167mA
5.43W
8.69W
19.5W
36.4W
52.7W
70.0W
87.4W
96.6W
In shutdown mode the port is disabled and will not detect
or power a PD.
Regardless of which mode it is in, the LTC4291-1/
LTC4292 will remove power automatically from any port
and/or channel, as appropriate, that generates a fault. It
will also automatically remove power from any port/chan-
nel that generates a disconnect event if disconnect detec-
tion is enabled. The host controller may also command
the port to remove power at any time.
Table 5. Typical Auto Mode Power On Thresholds,
Dual-Signature PD
PER-CHANNEL
CLASS
I
I
P
*
CUT-2P
CUT-2P
LIM-2P
1
94mA
150mA
338mA
638mA
975mA
425mA
425mA
425mA
850mA
1167mA
5.43W
2
8.69W
19.5W
36.4W
48.3W
Reset and the AUTO Pin
3
The initial LTC4291-1/LTC4292 configuration depends on
the state of AUTO during reset. Reset occurs at power-up,
whenever RESET is pulled low, or when the global Reset
All bit is set. Changing the state of AUTO after power-
up will not change the port behavior of the LTC4291-1/
LTC4292 until a reset occurs.
4
5
*A per-port P
threshold holds the sum of P
for each
CUT-4P
CUT-2P
powered channel.
CONNECTION CHECK
Although typically actively managed by a host controller,
the LTC4291-1/LTC4292 may alternatively be configured
for autonomous operation by setting AUTO high. With
AUTO high, each port will detect and classify repeatedly
CUT-2P LIM-2P CUT-4P
according to the PSE assigned Class, apply power to valid
PDs, and remove power when a PD is disconnected.
Connection Check Overview
IEEE 802.3bt introduces a new detection subroutine known
as connection check. A connection check is required to
determine whether the attached PD is a single-signature
PD, a dual-signature PD or an invalid result.
until a PD is discovered, set I
, I
, and P
In 802.3at, only one PD configuration was described;
this is known as a single-signature PD and is shown in
Figure 10. A single-signature PD presents the same 25k
detection resistor to both the pairsets in parallel.
Tables 4 and 5 show the I
, I
, and P
val-
CUT-2P LIM-2P
CUT-4P
ues that will be automatically set in auto mode, based on
the PD requested Class.
New in 802.3bt is the dual-signature PD as shown in
Figure 11. A dual-signature PD presents two fully indepen-
dent 25k detection signature resistors, one to each pairset.
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APPLICATIONS INFORMATION
The PD configuration (single or dual) determines how the
PD is managed during subsequent detection, classifica-
tion and power on procedures. Throughout the remainder
of this data sheet attention will be called to the different
treatment of single-signature and dual-signature PDs.
Multipoint Detection
The LTC4291-1/LTC4292 uses a multipoint method to
detect PDs. False-positive detections are minimized by
checking for signature resistance with both forced current
and forced voltage measurements.
Connection check is performed with two current measure-
ments, at the same forced voltage, on the first channel.
The second channel is tested for aggressor behavior by
introducing a forced current on the second channel during
the second measurement. Comparison of the two result-
ing current measurements on the first channel allows
for the connected device to be categorized as a single-
signature PD, a dual-signature PD, or an invalid result.
Initially, two test currents are forced onto the channel (via
the OUTnM pin) and the resulting voltages are measured.
The detection circuitry subtracts the two V-I points to
determine the resistive slope while removing offset caused
by series diodes or leakage at the port (see Figure 13). If
the forced current detection yields a valid signature resis-
tance, two test voltages are then forced onto the channel
and the resulting currents are measured and subtracted.
Both methods must report valid resistances to report a
valid detection. PD signature resistances between 17k
and 29k (typically) are detected as valid and reported as
Detect Good in the corresponding Port Status register or
Channel Status register, as appropriate. Values outside
this range, including open and short circuits, are also
reported. If the channel measures less than 1V during
any forced current test, the detection cycle will abort and
Short Circuit will be reported. Tables 6 and 7 show the
possible detection results.
An invalid connection check result is reported when a
device is added or removed during connection check.
DETECTION
Detection Overview
To avoid damaging network devices that were not designed
to tolerate DC voltage, a PSE must determine whether the
connected device is a valid PD before applying power.
The IEEE specification requires that a valid PD have a
common-mode resistance of 25k 5% at any channel
voltage below 10V. The PSE must accept resistances that
fall between 19k and 26.5k, and it must reject resistances
above 33k or below 15k (shaded regions in Figure 12).
The PSE may choose to accept or reject resistances in
the undefined areas between the must-accept and must-
reject ranges. In particular, the PSE must reject standard
computer Network Interface Cards (NICs), many of which
have 150Ω common-mode termination resistors that will
be damaged if power is applied to them (the black region
at the left of Figure 12).
240
FIRST
DETECTION
POINT
25kΩ SLOPE
160
SECOND
DETECTION
POINT
VALID PD
0V-2V
OFFSET
VOLTAGE
42911 F13
Figure 13. PD Detection
RESISTANCE 0Ω
10k
20k
30k
150Ω (NIC)
23.75k
26.25k
26.5k
PD
PSE
15k 19k
33k
42911 F12
Figure 12. IEEE 802.3 Signature Resistance Ranges
Rev 0
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APPLICATIONS INFORMATION
Table 6. Port Detection Status
MEASURED PD SIGNATURE
the PD and report that result as well. The port will then
wait for at least 100ms, and will repeat the detection cycle
to refresh the data in the Port Status registers.
(TYPICAL)
PORT DETECTION RESULT
Detect Status Unknown
Short Circuit
Incomplete or Not Yet Tested
The port will not turn on in response to a power-on com-
mand unless the current detect result is Detect Good. Any
other detect result will generate a tSTART fault if a power-on
command is received.
V
< 1V
PD
R
PD
< 17k
R
SIG
Too Low
17k < R < 29k
Detect Good, Single-Signature PD
Too High
PD
R
R
> 29k
> 50k
> 10V
R
SIG
PD
PD
PD
Open Circuit
Behavior in auto mode is similar to semi-auto; however,
after Detect Good is reported and the port is classified, it
is automatically powered on without host intervention. In
auto mode the ICUT-2P, ILIM-2P, and PCUT-4P thresholds are
automatically set; see the Reset and the AUTO Pin section
for more information.
V
Port Voltage Outside Detect Range
Connection Check Invalid
Refer to Channel Detect Results
Connection Check = INVALID
Connection Check = DUAL or
Channel Detection Results Differ
Table 7. Channel Detection Status
Detection is disabled for a port when the LTC4291-1/
LTC4292 is initially powered up with AUTO low, when
the port is in shutdown mode, or when the corresponding
Detect Enable bit is cleared.
MEASURED PD SIGNATURE
(TYPICAL)
CHANNEL DETECTION RESULT
Incomplete or Not Yet Tested
Detect Status Unknown
Short Circuit
V
C
< 1V
PD
PD
> 2.7μF
< 17k
C
Too High
Too Low
PD
Detection of Legacy PDs
R
R
SIG
PD
17k < R < 29k
Detect Good, Dual-Signature PD
Too High
PD
Proprietary PDs that predate the original IEEE 802.3af
standard are commonly referred to today as legacy PDs.
One type of legacy PD uses a large common-mode capaci-
tance (>10μF) as the detection signature. Note that PDs in
this range of capacitance are defined as invalid, so a PSE
that powers legacy PDs is noncompliant with the IEEE
standard. The LTC4291-1/LTC4292 can be configured to
detect this type of legacy PD. Legacy detection is disabled
by default, but can be manually enabled on a per-port
basis. When enabled, the port will report Detect Good
when it sees either a valid IEEE PD or a high-capacitance
legacy PD. With legacy mode disabled, only valid IEEE
PDs will be recognized.
R
R
V
> 29k
> 50k
> 10V
R
SIG
PD
PD
Open Circuit
Channel Voltage Outside Detect Range
Connection Check Invalid
Refer to Port Detect Result
PD
Connection Check = INVALID
Connection Check = SINGLE or
Channel Detection Results Match
More on Operating Modes
The port’s operating mode determines when the
LTC4291-1/LTC4292 runs a detection cycle. In manual
mode, the port will idle until the host orders a detect cycle.
It will then run detection, report the result, and return to
idle to wait for another command.
If a nonstandard PD presents an invalid detection signa-
ture not included by legacy detection, the LTC4291-1/
LTC4292 may be configured to perform classification and/
or apply power regardless of detection result. To accom-
plish this, the LTC4291-1/LTC4292 introduces per-port
Force Power and Class Event overrides. These overrides
intentionally defeat compliance checks. See the LTC4291
Software Programming documentation for details.
In semi-auto mode the LTC4291-1/LTC4292 autono-
mously polls a port for PDs, but it will not apply power
until commanded to do so by the host. The Port Status
and Channel Status registers are updated at the end of
each detection/classification cycle.
In semi-auto mode, if a valid signature resistance is
detected and classification is enabled, the port will classify
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APPLICATIONS INFORMATION
Classification
Table 8. Type 1 and Type 2 PD Classification Values
CLASS
Class 0
Class 1
Class 2
Class 3
Class 4
RESULT
802.3af Classification
No Class Signature Present; Treat Like Class 3
3.84W
A PD may optionally present a classification signature
to the PSE to indicate the maximum power it will draw
while operating. The IEEE specification defines this sig-
nature as a constant current draw when the PSE port
6.49W
13W
25.5W (Type 2)
voltage is in the V
range (between 15.5V and 20.5V)
as shown in FiguCreLA1S5S, with the current level indicating
one of five possible PD signatures. Figure 14 shows a
typical PD load line, starting with the slope of the 25k
signature resistor below 10V, then transitioning to the
classification signature current (in this case, Class 3)
in the VCLASS range. Table 8 shows the possible clas-
sification values.
If classification is enabled, the PSE will classify the PD
immediately after a successful detection cycle. The PSE
measures the PD classification signature by applying
V
to the port via OUTnM and measuring the result-
CLASS
ing current; it then reports the discovered class in the Port
Status or Channel Status register, as appropriate. If the
LTC4291-1/LTC4292 is in auto mode, it will additionally
use the classification result to set the I
, I
, and
CUT-2P LIM-2P
ꢎ0
P
thresholds.
CUT-4P
ꢗꢉꢆ ꢂꢁꢄꢙ ꢂꢘꢌꢆ
ꢁꢀꢆR
ꢈꢋRRꢆꢌꢃ
ꢏ0
ꢐ0
ꢑ0
ꢒ0
ꢓ0
0
Classification is disabled for a port when the LTC4291-1/
LTC4292 is initially powered up with the AUTO pin low,
when the port is in shutdown mode, or when the corre-
sponding Class Enable bit is cleared.
ꢐꢚꢍꢄ
ꢈꢂꢄꢉꢉ ꢐ
ꢈꢂꢄꢉꢉ ꢑ
ꢑꢑꢍꢄ
ꢒꢑꢍꢄ
ꢈꢂꢄꢉꢉ ꢒ
ꢃꢖꢗꢘꢈꢄꢂ
ꢈꢂꢄꢉꢉ ꢑ
ꢗꢙ ꢂꢁꢄꢙ
ꢂꢘꢌꢆ
LLDP Classification
ꢓꢐꢛꢏꢍꢄ
ꢎꢛꢏꢍꢄ
ꢈꢂꢄꢉꢉ ꢓ
ꢈꢂꢄꢉꢉ 0
Introduced in 802.3at and extended by 802.3bt, the PoE
specification defines a Link Layer Discovery Protocol
(LLDP) method of classification. The LLDP method adds
extra fields to the Ethernet LLDP data protocol.
0
ꢏ
ꢓ0
ꢓꢏ
ꢒ0
ꢒꢏ
ꢀꢁꢂꢃꢄꢅꢆ ꢇꢀ
ꢊ
ꢈꢂꢄꢉꢉ
ꢐꢒꢔꢓꢓ ꢕꢓꢐ
Figure 14. PD Classification
Although the LTC4291-1/LTC4292 is compatible with this
classification method, it cannot perform LLDP classifica-
tion directly since it does not have access to the data path.
LLDP classification allows the host to perform LLDP com-
munication with the PD and update the PD’s power allo-
cation. The LTC4291-1/LTC4292 supports changing the
ꢗꢇꢘꢕR ꢇꢑ
ꢌꢍꢎꢏꢏ
ꢆ
ꢆ
ꢌꢍꢎꢏꢏꢋꢐꢑ
I
, I
, and P
levels dynamically, enabling
LIM-2P CUT-2P
CUT-4P
system-level LLDP support.
ꢋꢎRꢒꢋꢎꢓ
ꢖꢕꢉꢕꢌꢉ
802.3at 2-Event Classification
ꢆ
Rꢕꢏꢕꢉ
In 802.3at, 802.3af classification is named Type 1 clas-
sification. The 802.3at standard introduces an extension
of Type 1 classification: Type 2 (2-event) classification.
Type 2 PSEs are required to perform classification.
ꢆ
ꢏꢐꢔꢋꢐꢑ
ꢀꢁꢂꢃꢃ ꢄꢃꢅ
Figure 15. Type 1 PSE, 1-Event Class Sequence
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APPLICATIONS INFORMATION
A Type 2 PD requesting 25.5W presents class signature 4
during all class events. If a Type 2 PSE with 25.5W of
available power sees class signature 4 during the first
class event, it forces the PD to VMARK (9V typical), pauses
briefly, and issues a second class event as shown in
Figure 16. The second class event informs the PD that
the PSE has allocated 25.5W.
classification supersede Type 1 and Type 2 classifica-
tion. Type 1 and Type 2 classification are described in
the preceding sections as a historical reference and to
define common terminology such as power demotion,
class events, mark events, and electrical parameters.
IEEE 802.3bt defines eight PD Classes for single-signature
PDs and five PD Classes for dual-signature PDs, as shown
in Table 9.
ꢗꢇꢘꢕR ꢇꢑ
ꢃꢏꢉ
ꢌꢍꢎꢏꢏ
ꢁꢑꢖ
ꢌꢍꢎꢏꢏ
Classification treatment of single-signature and dual-
signature PDs differs. The following sections explain the
Physical Layer classification of each PD configuration
separately.
ꢆ
ꢆ
ꢌꢍꢎꢏꢏꢋꢐꢑ
ꢋꢎRꢒꢋꢎꢓ
ꢖꢕꢉꢕꢌꢉ
Table 9. Type 3 and Type 4 PD Classifications by PD Configuration
SINGLE-SIGNATURE PDs
DUAL-SIGNATURE PDs
ꢃꢏꢉ
ꢋꢎRꢒ
ꢁꢑꢖ
ꢆ
Rꢕꢏꢕꢉ
ꢋꢎRꢒ
PD AVAILABLE
CHANNEL AVAILABLE
*
ꢆ
CLASS
POWER
3.84W
6.49W
13W
CLASS
POWER
3.84W
6.49W
13W
ꢏꢐꢔꢋꢐꢑ
ꢀꢁꢂꢃꢃ ꢄꢃꢅ
Class 1
Class 2
Class 3
Class 4
Class 5
Class 6
Class 7
Class 8
Class 1
Class 2
Class 3
Class 4
Class 5
Figure 16. Type 2 PSE, 2-Event Class Sequence
Note that the second classification event only runs if
required by the IEEE classification procedure. For exam-
ple, a single-signature Class 0 to 3 PD will only be issued
a single class event in all situations.
25.5W
40W
25.5W
35.6W
51W
62W
The concept of demotion is introduced in 802.3at. A
Type 2 PD may be connected to a PSE only capable of
delivering 13W, perhaps due to power management limi-
tations. In this case, the PSE will perform a single classi-
fication event as shown in Figure 15, and note that 25.5W
is requested. Due to the limited power availability, the
PSE will not issue a second event and proceeds directly
to power on the PD. The presence of a single class event
informs the Type 2 PD it has been demoted to 13W. If
demoted, the PD is subject to power limitations and may
operate in a reduced power mode.
71.3W
*Dual-signature PD total available power is the sum of both channels
available power. Class signatures may differ between channels of a port,
e.g., Class 3 + Class 4 = 13W + 25.5W = 38.5W.
802.3bt Classification of Single-Signature PDs
Type 3 and Type 4 PSEs issue a single classification event
(see Figure 17) to Class 0 through 3 single-signature (SS)
PDs. A Class 0 through 3 SS PD presents its class signa-
ture to the PSE and is then powered on if sufficient power
is available. Power limited 802.3bt PSEs may also issue a
single classification event to Class 4 and higher SS PDs in
order to demote those PDs to 13W. See Figure 17.
802.3bt Multi-Event Classification
The LTC4291-1/LTC4292 implements Type 3 and Type 4
classification, as required by 802.3bt. Type 3 and Type 4
classification are backwards-compatible with Type 1 and
Type 2 PDs.
Type 3 and 4 PSEs present three classification events
to Class 4 SS PDs (see Figure 18) if sufficient power is
available. Class 4 SS PDs present class signature 4 on
all events. The third event differentiates a Class 4 SS PD
from a higher Class SS PD. Power limited IEEE 802.3bt
While Type 2 (802.3at) classification extends Type 1
(802.3af) classification, Type 3 and Type 4 (802.3bt)
Rev 0
23
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LTC4291-1/LTC4292
APPLICATIONS INFORMATION
ꢗꢇꢘꢕR ꢇꢑ
ꢘꢆꢙꢔR ꢆꢐ
ꢃꢏꢉ
ꢌꢍꢎꢏꢏ
ꢃꢎꢈ
ꢁꢐꢕ
ꢖRꢕ
ꢋꢌꢍꢎꢎ
ꢀꢈꢗ
ꢋꢌꢍꢎꢎ
ꢋꢌꢍꢎꢎ ꢋꢌꢍꢎꢎ
ꢆ
ꢅ
ꢅ
ꢌꢍꢎꢏꢏꢋꢐꢑ
ꢋꢌꢍꢎꢎꢊꢏꢐ
ꢆ
ꢋꢎRꢒꢋꢎꢓ
ꢊꢍRꢑꢊꢍꢒ
ꢖꢕꢉꢕꢌꢉ
ꢕꢔꢈꢔꢋꢈ
ꢃꢎꢈ
ꢊꢍRꢑ
ꢁꢐꢕ
ꢊꢍRꢑ
ꢖRꢕ
ꢊꢍRꢑ
ꢀꢈꢗ
ꢊꢍRꢑ
ꢃꢏꢉ
ꢋꢎRꢒ
ꢆ
ꢅ
Rꢕꢏꢕꢉ
Rꢔꢎꢔꢈ
ꢆ
ꢅ
ꢏꢐꢔꢋꢐꢑ
ꢎꢏꢓꢊꢏꢐ
ꢀꢁꢂꢃꢃ ꢄꢃꢅ
ꢀꢁꢂꢃꢃ ꢄꢃꢂ
Figure 17. Type 3 or 4 PSE, 1-Event Class Sequence
Figure 19. Type 3 or 4 PSE, 4-Event Class Sequence
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ꢙꢆꢚꢔR ꢆꢐ
ꢃꢏꢉ
ꢌꢍꢎꢏꢏ
ꢁꢑꢖ
ꢌꢍꢎꢏꢏ
ꢗRꢖ
ꢌꢍꢎꢏꢏ
ꢃꢎꢈ
ꢋꢌꢍꢎꢎ
ꢁꢐꢕ
ꢋꢌꢍꢎꢎ
ꢖRꢕ
ꢋꢌꢍꢎꢎ
ꢀꢈꢗ
ꢘꢈꢗ
ꢋꢌꢍꢎꢎ ꢋꢌꢍꢎꢎ
ꢆ
ꢆ
ꢌꢍꢎꢏꢏꢋꢐꢑ
ꢅ
ꢅ
ꢋꢌꢍꢎꢎꢊꢏꢐ
ꢋꢎRꢒꢋꢎꢓ
ꢊꢍRꢑꢊꢍꢒ
ꢖꢕꢉꢕꢌꢉ
ꢕꢔꢈꢔꢋꢈ
ꢃꢏꢉ
ꢋꢎRꢒ
ꢁꢑꢖ
ꢋꢎRꢒ
ꢗRꢖ
ꢋꢎRꢒ
ꢆ
Rꢕꢏꢕꢉ
ꢃꢎꢈ
ꢊꢍRꢑ
ꢁꢐꢕ
ꢊꢍRꢑ
ꢖRꢕ
ꢊꢍRꢑ
ꢀꢈꢗ
ꢊꢍRꢑ
ꢘꢈꢗ
ꢊꢍRꢑ
ꢅ
Rꢔꢎꢔꢈ
ꢆ
ꢏꢐꢔꢋꢐꢑ
ꢅ
ꢀꢁꢂꢃꢃ ꢄꢃꢅ
ꢎꢏꢓꢊꢏꢐ
ꢀꢁꢂꢃꢃ ꢄꢁ0
Figure 20. Type 4 PSE, 5-Event Class Sequence
Figure 18. Type 3 or 4 PSE, 3-Event Class Sequence
PSEs may issue three classification events to Class 5 and
higher SS PDs in order to demote those PDs to 25.5W.
802.3bt Classification of Dual-Signature PDs
Classification and power allocations to each pairset of a
dual-signature (DS) PD are fully independent. For exam-
ple, a DS PD may request Class 1 (3.84W) on one pairset
and a Class 4 (25.5W) on the second pairset for a total
PD requested power of 29.3W. As such, all classification
is performed to the pairset entity as opposed to the PD.
The terms should be considered interchangeable for the
remainder of this section.
Type 3 and 4 PSEs present four classification events (see
Figure 19) to Class 5 and 6 SS PDs if sufficient power is
available. Class 5 and 6 SS PDs present class signature
4 on the first two events. Class 5 and 6 SS PDs present
class signature 0 or 1, respectively, on the subsequent
events. Power limited PSEs may issue four events to Class
7 and 8 SS PDs in order to demote those PDs to 51W.
Type 4 PSEs present five classification events (see
Figure 20) to Class 7 and 8 SS PDs if sufficient power
is available. Class 7 and 8 PDs present class signature
4 on the first two events. Class 7 and 8 SS PDs present
class signature 2 or 3, respectively, on the subsequent
events.
Type 3 and Type 4 PSEs issue three classification events
(see Figure 18) to all Class 1 through 4 DS PDs.
Power limited Type 3 and Type 4 PSEs may issue a class
reset to Class 4 and 5 DS PDs in order to demote those
PDs to 13W (see Understanding 4PID section).
Rev 0
24
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LTC4291-1/LTC4292
APPLICATIONS INFORMATION
Power limited Type 3 and Type 4 PSEs may issue only
three events to Class 5 DS PDs in order to demote those
PDs to 25.5W.
An issue arises when a Class 4 or Class 5 dual-signature
PD is connected. In order to determine PD Type, three
class events are issued. Based on the class event count,
the PD has been allocated 25.5W. If the PSE desires to
both determine PD Type (3 events) and demote to 13W
(1 event), a class reset event must be issued as shown
in Figure 21.
Type 4 PSEs present four classification events (see
Figure 19) to Class 5 DS PDs if sufficient power is avail-
able. Class 5 DS PDs present class signature 4 on the first
two events and class signature 3 on subsequent events.
ꢖꢆꢗꢓR ꢆꢐ
Understanding 4PID
ꢃꢎꢈ
ꢁꢐꢔ
ꢕRꢔ
ꢃꢎꢈ
ꢋꢌꢍꢎꢎ ꢋꢌꢍꢎꢎ
ꢋꢌꢍꢎꢎ ꢋꢌꢍꢎꢎ
4-pair identification (4PID) refers to a set of conditions for
determining whether a PD is capable of receiving power
over both pairsets simultaneously.
ꢅ
ꢅ
ꢋꢌꢍꢎꢎꢊꢏꢐ
ꢊꢍRꢑꢊꢍꢒ
The PSE may apply 4-pair power if the PD presents a valid
detection signature on both pairsets and one or more of
the following conditions are met:
ꢔꢓꢈꢓꢋꢈ
ꢃꢎꢈ
ꢊꢍRꢑ
ꢁꢐꢔ
ꢊꢍRꢑ
ꢃꢎꢈ
ꢅ
Rꢓꢎꢓꢈ
ꢊꢍRꢑ
ꢋꢌꢍꢎꢎ
Rꢓꢎꢓꢈ
ꢀꢁꢂꢃꢃ ꢄꢁꢃ
•
•
•
The PD is single-signature configuration.
The PD is Type 3 or Type 4.
Figure 21. Class Reset Event Between Class Sequences
A class reset event is issued by maintaining the channel
The PD presents a valid detection signature on an
unpowered pairset when power is applied over the
other pairset.
voltage below 2.8V for at least t
. The subse-
CLASS_RESET
quent single event classification is used to demote the
PD to 13W.
Although PD signature configuration is not defined for
Type 1 and Type 2 PDs, a Type 3 or Type 4 PSE may
identify such a PD as single-signature or dual-signature.
Single-signature PDs may receive 4-pair power regardless
of PD Type. Certain pre-802.3bt “dual-signature” PDs may
be damaged by 4-pair power.
In auto mode the 4PID information and the state of
4PVALID are used to automatically determine the number
of powered channels.
LLDP signaling may, at some time later, determine the
pre-bt PD is actually four pair capable and the LTC4291-1/
LTC4292 may be instructed to deliver 4-pair power.
Type 3 and Type 4 dual-signature PDs are required to
present a unique classification response from pre-802.3bt
dual-signature PDs of the same Class. For dual-signature
PDs, the LTC4291-1/LTC4292 determines and reports
both PD Class and PD Type during classification.
Invalid Multi-Event Classification Combinations
The 802.3bt specification defines a set of valid class sig-
nature combinations. All PDs return the same classifica-
tion signature on the first two class events. Type 3 and 4
PDs modify the classification signature on all subsequent
class events. For example, a single-signature Class 5 PD
will respond to the class events 1, 2, 3, and 4 with a class
signature of 4, 4, 0, and 0, respectively.
Type 3, Type 4, and pre-802.3bt Class 1 through Class 4
dual-signature PDs present class signature 1 through 4,
respectively, during the first and second class events.
Type 3 and Type 4 dual-signature PDs present class sig-
nature 0 for all subsequent class events. Thus, a PSE can
conclusively determine PD Type by the third class event
for all dual-signature PDs.
Any individual class signature that exceeds the class cur-
rent limit is flagged as an invalid classification result. Any
sequence of class signatures that does not represent a
legal sequence based on PD configuration will likewise
be flagged as an invalid classification result.
Rev 0
25
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LTC4291-1/LTC4292
APPLICATIONS INFORMATION
Auto Mode Maximum PSE Power
During a typical inrush, the MOSFET gate voltage will rise
until the external MOSFET is fully enhanced or the channel
In auto mode the LTC4291-1/LTC4292 automatically
detects, classifies and powers all connected valid PDs.
In order to do this, the PSE must be configured for its
maximum power allocation. The maximum power alloca-
tion is a reflection of the power supply and power path
capability. The PWRMD pins must be set appropriately
to reflect the PSE system’s power delivery capabilities.
These pins are sampled at reset.
reaches the inrush current limit (I
). I
is
INRUSH-2P
set automatically by the PSE. When the PSEINisRUapSHp-l2yPing
4-pair power to a single-signature PD assigned Class 0
to Class 4, I
(LIMn = 08h). Otherwise, I
per channel (LIMn = 80h).
is 212.5mA (typical) per channel
INRUSH-2P
is 425mA (typical)
INRUSH-2P
The GATE pin will be servoed if channel current exceeds
, actively limiting current to I . When
I
INRUSH-2P
INRUSH-2P
Table 10. Auto Mode Maximum Delivered Power Capabilities
MAX PORT POWER MAX PAIRSET POWER
PWRMD1 PWRMD0 (SINGLE-SIGNATURE) (DUAL-SIGNATURE)
the GATE pin is not being servoed, the final VGS is 12V
(typical).
0
0
1
1
0
1
0
1
40W
51W
13W
During inrush, each powered channel runs a timer (tSTART).
25.5W
25.5W
35.6W
Each powered channel stays in inrush until t
expires.
When t
expires, the PSE inspects chSaTnAnReTl voltage
62W
START
71.3W
and current. When the PSE is applying power to a PD,
inrush is successful if the channel(s) are drawing current
below IINRUSH-2P, as appropriate per the PD configuration
and Class.
POWER CONTROL
The primary function of the LTC4291-1/LTC4292 is to con-
trol power delivery to the PSE port. With the LTC4291-1/
LTC4292, a PSE port is composed of two power chan-
nels; each power channel controls power delivery over a
pairset. Within this section, power delivery and control
are defined per-channel.
If inrush is not successful, power is removed and the
corresponding t
faults are set. Otherwise, the port
START
or channel, as appropriate, advances to power on and
the programmed current limiting thresholds are used as
described in the Current Limit section.
The LTC4291-1/LTC4292 delivers power by controlling
the gate drive voltage of an external power MOSFET while
monitoring the current (through an external sense resis-
tor) and the output voltage (across the OUT pin).
Port Power Policing
The power policing threshold (P
) is monitored on a
CUT-4P
per-port basis, up to 128W in 0.5W increments (typical).
When the total output power over a one second moving
average exceeds the specified threshold, power will be
The LTC4291-1/LTC4292 connects the VEE power sup
-
ply to the PSE port in a controlled manner, meeting the
power demands of the PD while minimizing power dis-
sipation in the external MOSFET and disturbances to the
removed from the port and the corresponding t faults
are set.
CUT
In particular, the port policing feature may be used to
ensure delivery of PD Class power while staying below
100W Limited Power Source (LPS) requirements.
V
EE
backplane.
Inrush Control
When commanded to apply power to a port, the
LTC4291-1/LTC4292 ramps up the GATE pin of one or
both channels (as commanded), raising the external
MOSFET gate voltage in a controlled manner.
Current Cutoff and Limit
Each LTC4291-1/LTC4292 port includes two current lim-
iting thresholds (I
and I
), each with a cor-
CUT-2P
LIM-2P
responding timer (t and t ). Setting the I
and
CUT-2P
CUT
ILIM-2P thresholds dependsLoIMn several factors: the PD
Rev 0
26
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LTC4291-1/LTC4292
APPLICATIONS INFORMATION
assigned Class, the main supply voltage (V ), the PSE
Configuration field should be set as shown in the LTC4291
Software Programming documentation.
EE
Type (Type 3 or 4), and the MOSFET SOA.
A single set of programmable port ICUT-2P and ILIM-2P
thresholds is shared by both channels. The thresholds
should be set based on the classification result as shown
in Table 4 and Table 5. For a dual-signature PD assigned
unequal Classes, the highest Class is used to set the
thresholds. For example, a dual-signature PD assigned
ICUT-2P is typically set to a lower value than ILIM-2P,
allowing the port to tolerate minor faults without current
limiting.
To maintain IEEE compliance, the programmed ILIM-2P
should be set as shown in Tables 4 and 5. The pro-
grammed I
setting is automatically applied follow-
LIM-2P
Class 1 and Class 5 would enforce I
based on Class 5.
and I
CUT-2P
LIM-2P
ing the completion of inrush.
The t and t timers are maintained on a per channel
CUT
LIM
CUT
Per the IEEE specification, the LTC4291-1/LTC4292 will
allow the channel current to exceed I for a limited
basis. When a t
or t fault occurs a determination is
LIM
CUT-2P
made to turn off one or both channels. See the Port Fault
period of time before removing power from the port, or
channel, as appropriate whereas it will actively control
the MOSFET gate drive to keep the channel current below
vs Channel Fault section for details.
I
Foldback
LIM-2P
I
. The channel does not take any action to limit the
LIM-2P
current when only the I
The LTC4291-1/LTC4292 ILIM-2P threshold is imple-
mented as a two-stage foldback circuit that reduces the
channel current if the channel voltage falls below the nor-
mal operating voltage. This keeps MOSFET power dissipa-
tion at safe levels. Current limit and foldback behavior are
programmable on a per-port basis.
threshold is exceeded, but
CUT-2P
does start the t
I
timer. If the current drops below the
CUT
threshold before its timer expires, the t
timer
CUT-2P
CUT
counts back down, but at 1/16 the rate that it counts up. If
the t timer reaches 59ms (typical), the port or channel,
CUT
as appropriate, is turned off and the corresponding t
CUT
faults are set. This allows the channel to tolerate intermit-
tent overload signals with duty cycles below about 6%;
longer duty cycle overloads will remove power from the
port or channel, as appropriate.
The LTC4291-1/LTC4292 supports current levels well
beyond the maximum values in the 802.3bt specifica-
tion. Large values of I
may require larger external
LIM-2P
MOSFETs, additional heat sinking, and setting the t
LIM
Timer Configuration field to a lower value.
The I
current limiting circuit is always enabled and
LIM-2P
actively limiting channel current. The tLIM timer is enabled
only when the t Timer Configuration field is set to a
non-zero value. This allows tLIM to be set to a shorter value
than tCUT to provide more aggressive MOSFET protection
and turn off a port before MOSFET damage can occur. The
MOSFET Fault Detection
LIM
LTC4291-1/LTC4292 PSE ports are designed to tolerate
significant levels of abuse, but in extreme cases it is pos-
sible for an external MOSFET to be damaged. A failed
MOSFET may short source to drain, which will make the
port appear to be on when it should be off; this condition
may also cause the sense resistor to fuse open, turning
off the port but causing SENSE to rise to an abnormally
high voltage. A failed MOSFET may also short from gate to
drain, causing GATE to rise to an abnormally high voltage.
OUT, SENSE and GATE are designed to tolerate up to 80V
faults without damage.
t
timer starts when the I
threshold is exceeded.
LIM
When the tLIM timer reachLeIsM1-2.P7ms (typical) times the
value in the t
Timer Configuration field, the port or
LIM
channel, as appropriate, is turned off and the appropriate
tLIM faults are set. When the tLIM Timer Configuration field
is set to 0, t
behaviors are tracked by the t
timer,
LIM
CUT
events.
LIM
which counts up during both I
and I
LIM-2P
CUT-2P
To maintain IEEE compliance, the programmed t Timer
Rev 0
27
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LTC4291-1/LTC4292
APPLICATIONS INFORMATION
If the LTC4291-1/LTC4292 sees a power good condition
on either channel of an unpowered port (neither channel
powered), it disables all port functionality, reduces the
gate drive pull-down current for the port and reports a FET
Bad fault. This is typically a permanent fault, but the host
can attempt to recover by resetting the port, or by reset-
ting the entire chip if a port reset fails to clear the fault.
If the MOSFET is in fact bad, the fault will quickly return,
and the port will disable itself again. The remaining ports
of the LTC4291-1/LTC4292 are unaffected.
subsequently connected to a non-PoE data device, poten-
tially causing damage.
The LTC4291-1/LTC4292 does not include AC discon-
nect circuitry. AC disconnect is not a supported feature
of 802.3bt.
Port Fault vs Channel Fault
The t , t
and t timers are maintained on a per-
DIS
CUT LIM
channel basis. When any channel timer expires, a deter-
mination is made to remove power from both, one, or
neither channel of the port.
An open or missing MOSFET will not trigger a FET Bad
fault, but will cause a tSTART fault if the LTC4291-1/
LTC4292 attempts to turn on the port.
Optional behavior is allowed by the 802.3bt standard
when faults occur on single-signature PDs. This option
allows a single-signature PD to remain powered on pair-
set X, even if a fault occurs on pairset Y. The FAULT2Pn bit,
when set, enables this optional behavior. This behavior is
not recommended for normal operation, as a fault in the
PD or cabling is indicative of imminent PD or cable failure.
Disconnect
The LTC4291-1/LTC4292 monitors powered channels to
ensure the PD continues to draw the minimum speci-
fied current. The I
HOLD-2P
used to determine if a PD has been disconnected.
threshold, monitored as the
HOLD-2P
V
threshold across the 0.15Ω sense resistor, is
Table 11. Channel Fault Effect on Port/Channel State
FAULT RESULT:
The I threshold is set automatically in auto mode
HOLD-2P
TURN OFF PORT OR CHANNEL
PD CON-
and is set by the user in semi-auto and manual modes.
FIGURATION
Single
FAULT2Pn
t
**
CUT
t
t
DIS
LIM
When powering a single-signature PD assigned Class 0 to
0
1
x
Port
Port
Port*
Class 4 over a single channel, set the I
threshold
HOLD-2P
Channel
Channel
Channel
Channel
to 7.5mA (typ) via the Disconnect Configuration bit. In all
other cases, set the I threshold to 3.5mA (typ).
Dual
Channel
HOLD-2P
*If t Expires on Both Channels
DIS
**Port power policing (P
power policing removes power from the port regardless of FAULT2Pn
configuration.
) raises a t
event. When enabled, port
A disconnect timer (t ) counts up whenever channel
CUT-4P
CUT
DIS
current is below the I
threshold, indicating that the
PD has been disconnHeOctLeDd-2.PIf the appropriate tDIS timer(s)
expire, the port or channel (Table 11) will be turned off
Fault Telemetry
and the corresponding t faults are set. If the current
DIS
As discussed in the preceding sections, faults may occur
on one or both channels, resulting in power removal on
one or both channels. The fault event registers have tra-
ditionally been implemented at the port level. In order to
trace faults to the offending channel, a second layer of fault
registers have been added to the LTC4291-1/LTC4292:
the Fault Telemetry registers. See the LTC4291 Software
Programming documentation for additional information.
increases above I
before the t timer expires, the
HOLD-2P
DIS
timer(s) reset. As long as the PD exceeds the minimum
current level before t expires, it will remain powered.
DIS
Although not recommended, the DC disconnect fea-
ture can be disabled by clearing the corresponding DC
Disconnect Enable bits. Disabling the DC disconnect fea-
ture forces the LTC4291-1/LTC4292 out of compliance
with the IEEE standard. A powered port will stay powered
after the PD is removed; the still-powered port may be
Rev 0
28
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LTC4291-1/LTC4292
APPLICATIONS INFORMATION
Autoclass
Figure 23 shows a 100W four port PSE servicing three
25.5W PDs over 10m cables. Such a system requires the
PSE to allocate 25.5W per PD and a further ~0.5W for
each 10m cable’s IR drop.
IEEE 802.3bt introduces a new optional feature, Autoclass.
Autoclass enables the PSE to reclaim power budget from
single-signature PDs requesting more power than needed
under worst-case operating conditions. 802.3bt does not Without Autoclass, the total power allocation is:
specify Autoclass for dual-signature PDs. The LTC4291-1/
LTC4292 fully supports Autoclass.
3 ports • (4.5W + 25.5W) = 90W
If an additional 13W PD is plugged into the fourth PSE
Prior versions of the 802.3 PoE standard specify mini-
port, only 10W is available and the PD cannot be powered
mum PSE output power for worst-case IR drop across
even though the IR drop is much less than in the prior
the Ethernet cable and minimum PSE output voltage.
example.
However, a method for the PSE to reclaim over-allocated
Assuming the system in Figure 23 is Autoclass-enabled,
the recovered power budget can be used to power addi-
tional ports. During classification, the PSE observes the
PD’s Autoclass request. After power on is completed, the
PD draws its maximum power while the PSE performs
an Autoclass measurement, as specified by 802.3bt. The
PSE in Figure 23 will measure and report 26W of power
consumption for each of the three 25.5W PDs. This result
allows the host to revise the PSE available power budget.
power is not specified. When a shorter Ethernet cable is
used, or when the guaranteed PSE output voltage is above
the specified minimum, the specified minimum PSE out-
put power substantially over-allocates power to the PD.
An example PoE system is shown in two versions.
Figure 22 shows a 100W four port PSE servicing three
25.5W PDs over 100m cables. Such a system requires
the PSE to allocate 25.5W per PD and a further 4.5W for
each 100m cable’s IR drop.
With Autoclass, the total power allocation for Figure 23 is:
3 Ports • 26W (Measured) = 78W
The total power allocation is:
3 Ports • (4.5W + 25.5W) = 90W
If an additional 13W PD is plugged into the fourth PSE
port, a full 22W is now available and the PD can be suc-
cessfully powered.
If an additional 13W PD is plugged into the fourth PSE
port, only 10W is available and the PD cannot be powered.
ꢀꢁꢂ ꢃꢄ
ꢀꢁꢂ ꢃꢄ
ꢀ00ꢈ ꢉꢊꢋꢌꢍ
ꢎꢇꢆꢂ ꢏR ꢄRꢐꢃ
ꢀ0ꢈ ꢉꢊꢋꢌꢍ
ꢎ0ꢇꢆꢂ ꢏR ꢄRꢐꢃ
ꢅꢆꢇꢆꢂ ꢃꢄ
ꢅꢆꢇꢆꢂ ꢃꢄ
ꢀ00ꢂ ꢃꢑꢍ
ꢀ00ꢂ ꢃꢑꢍ
ꢀ00ꢈ ꢉꢊꢋꢌꢍ
ꢀ0ꢈ ꢉꢊꢋꢌꢍ
ꢎꢇꢆꢂ ꢏR ꢄRꢐꢃ
ꢎ0ꢇꢆꢂ ꢏR ꢄRꢐꢃ
ꢅꢆꢇꢆꢂ ꢃꢄ
ꢅꢆꢇꢆꢂ ꢃꢄ
ꢀ00ꢈ ꢉꢊꢋꢌꢍ
ꢎꢇꢆꢂ ꢏR ꢄRꢐꢃ
ꢀ0ꢈ ꢉꢊꢋꢌꢍ
ꢎ0ꢇꢆꢂ ꢏR ꢄRꢐꢃ
ꢅꢆꢇꢆꢂ ꢃꢄ
ꢅꢆꢇꢆꢂ ꢃꢄ
ꢎꢅꢒꢀꢀ ꢓꢅꢅ
ꢒꢅꢓꢀꢀ ꢔꢅꢁ
Figure 22. 100W PoE System with 100m Cables
Figure 23. 100W PoE System with 10m Cables
Rev 0
29
For more information www.analog.com
LTC4291-1/LTC4292
APPLICATIONS INFORMATION
Autoclass Negotiation Procedure
7. The PSE measures the Autoclass response of the PD.
If class signature 0 is measured, the PD is requesting
Autoclass. When the measurement is complete the
first class event is ended.
A PSE may receive an Autoclass request from the PD by
Physical Layer classification or LLDP (by way of the PSE
host). For Physical Layer requests, the Autoclass negotia-
tion procedure listed below is shown in Figure 24.
8. The PD continues holding the class signature selected
in step 6 until the end of the first class event.
1. PSE begins issuing the long first class event. The PD
class signature is allowed to settle during this time.
Following the Autoclass negotiation procedure, PSE and
PD continue Physical Layer classification and power up
as normal. Regardless of Autoclass, the PD is required
to operate below the negotiated power allocation corre-
sponding to PD assigned Class.
2. The PD responds with a class signature correspond-
ing to its Class. The class signature during this time
period is unrelated to the Autoclass negotiation.
3. The PSE measures the PD class signature during this
time and uses the result for the normal Multi-event
Classification.
Autoclass Measurement Procedure
Autoclass measurements may be requested by the PD
through Physical Layer classification or, following power
on, through LLDP. Although the LTC4291-1/LTC4292 is
compatible with LLDP-based Autoclass requests, it can-
not receive LLDP Autoclass requests directly since it does
not have access to the data path.
4. The PD continues presenting its class signature.
5. The PSE continues the long class event and does not
measure the class signature current at this time.
6. The PD, if requesting Autoclass, transitions to class
signature 0. If the PD is not requesting Autoclass it
continues presenting its class signature.
If the PSE is commanded to perform an Autoclass mea-
surement following a Physical Layer request, the mea-
surement typically begins t
(1.5s typical) after
port inrush is successfullyAcUoTmO_pPlSeEte1d. For LLDP-based
Autoclass requests, the measurement begins immediately.
ꢈ
ꢚ
ꢖꢊꢙꢌꢍꢉꢎ
ꢛꢜꢝꢞꢍ
ꢈ
ꢖꢊꢙꢌꢍꢔꢕ
ꢚ
ꢊꢖꢉꢋꢋ
The Autoclass measurement period is tAUTO_PSE2 – tAUTO_
PSE1 (1.8s typical) using a sliding window of tAUTO_WINDOW
(0.2s typical). During the Autoclass measurement period,
ꢃ
ꢀ
ꢁ
ꢂ
ꢚ
ꢍꢉRꢟ
ꢈ
ꢊꢖꢉꢋꢋꢌꢍꢔꢕ
the PSE continuously monitors I
and V , calculat-
ꢈ
PORT
EE
ꢈ
ꢈ
ꢊꢖꢉꢋꢋꢌꢖꢊꢙꢌꢍꢉꢎ
ing maximum average power. Following the Autoclass
measurement period, the Autoclass measurements are
reported in the Port Parametric registers.
ꢊꢖꢉꢋꢋꢌꢉꢊꢋꢌꢍꢔꢕ
ꢔ
ꢛꢜꢝꢞꢍ
ꢈ
ꢊꢖꢉꢋꢋꢌꢗꢘꢌꢍꢉꢎ ꢏꢁꢑꢒꢓ
ꢊꢖꢉꢋꢋꢌꢋꢔꢠꢌꢄ
See the LTC4291 Software Programming documen-
tation for details on enabling Autoclass, the status of
the Autoclass negotiation, reading Autoclass measure-
ment results and dynamically requesting an Autoclass
measurement.
ꢇ
ꢄ
ꢅ
ꢆ
ꢊꢖꢉꢋꢋꢌꢋꢔꢠꢌ0
ꢈ
ꢈ
ꢏꢂꢁꢐꢁꢑꢒꢓ
ꢏꢆꢂꢐꢁꢑꢒꢓ
ꢉꢊꢋꢌꢍꢔꢕ
ꢄꢇꢡꢃꢃ ꢢꢇꢄ
ꢈ
ꢉꢊꢋꢌꢍꢉꢎ
Port Current Readback
Figure 24. Autoclass Negotiation, Voltage and Current
The LTC4291-1/LTC4292 measures the current at each
power channel with per-channel A/D converters. The total
port current (sum of both channels) is reported. Port
Rev 0
30
For more information www.analog.com
LTC4291-1/LTC4292
APPLICATIONS INFORMATION
current is only valid when at least one power channel of a
port is on and reads zero at all other times. The converter
has two modes:
General Purpose IO
Two general purpose IO pins, GP0 and GP1 are available
on the LTC4291-1. These fully bidirectional IO pins use
3.3V CMOS logic.
•
100ms mode: Samples are taken continuously and
the measured value is updated every 100ms
Code Download
•
1s mode: Samples are taken continuously; a moving
1 second average is updated every 100ms
The LTC4291-1 includes a default firmware image,
enabling 802.3bt-compliant operation with no user inter-
vention required. In addition, the LTC4291-1 firmware is
field-upgradable by downloading and executing firmware
images. Firmware images are volatile and must be re-
downloaded after each V power cycle, but will remain
valid during reset and V power events.
V
Readback
EE
The LTC4291-1/LTC4292 continuously measures the
VEE voltage with a dedicated A/D converter. This global
DD
EE
V measurement is fully synchronized to all port current
EE
measurements.
The LTC4291-1 is intended for use with Analog Devices
firmware images only. Contact Analog Devices for code
download procedures and firmware images.
Port Power Readback
The LTC4291-1/LTC4292 provides fully continuous and
synchronized port power measurements. The LTC4291-1/
LTC4292 calculates the port power by multiplying the port
SERIAL DIGITAL INTERFACE
Overview
current and V measurements.
EE
P
PORT
= I
× V
PORT EE
The LTC4291-1 communicates with the host using a
standard SMBus/I2C 2-wire interface. The LTC4291-1
is a slave-only device, and communicates with the host
master using standard SMBus protocols. Interrupts
are signaled to the host via INT. The Timing Diagrams
(Figure 5 through Figure 9) show typical communication
waveforms and their timing relationships. More infor-
mation about the SMBus data protocols can be found at
www.smbus.org.
The Port Power measurements replace the Port Voltage
measurements provided in prior ADI PSEs. Port voltage
may be characterized and extrapolated from the VEE mea-
surement in a user-defined manner.
Masked Shutdown
The LTC4291-1/LTC4292 provides a low latency port
shedding feature to quickly reduce the system load when
required. By allowing a pre-determined set of ports to be
turned off, the current on an overloaded main power supply
can be reduced rapidly while keeping high priority devices
powered. Each port can be configured to high or low prior-
ity; all low-priority ports will shut down within 6.5μs after
MSD is pulled low, high priority ports will remain powered.
If a port is turned off via MSD, the corresponding Detection
and Classification Enable bits are cleared, so the port will
remain off until the host explicitly re-enables detection.
The LTC4291-1 requires both the V and V supply rails
DD
EE
to be present for the serial interface to function.
Bus Addressing
The LTC4291-1’s primary 7-bit serial bus address is
010A3A2A1A0b, with the lower four bits set by AD3 – AD0;
this allows up to 16 LTC4291-1s on a single bus. Sixteen
LTC4291-1s are equivalent to 64 ports. All LTC4291-1s
also respond to the broadcast address 0110000b, allow-
ing the host to write the same command (typically
configuration commands) to multiple LTC4291-1s in a
single transaction.
In the LTC4291-1/LTC4292 chipset, the active level of
MSD is register configurable as active high or low. The
default behavior is active low.
Rev 0
31
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LTC4291-1/LTC4292
APPLICATIONS INFORMATION
If the LTC4291-1 is asserting INT, it will also respond to
the alert response address (0001100b) per the SMBus
specification.
The LTC4291-1/LTC4292 chipset simplifies PSE isolation
by allowing the LTC4291-1 chip to reside on the non-
isolated side. There it can receive power from the main
2
logic supply and connect directly to the I C/SMBus bus.
Each LTC4291-1/LTC4292 is logically composed of a
Isolation between the LTC4291-1 and LTC4292 is imple-
mented using a proprietary transformer-based commu-
nication protocol. Additional details are provided in the
Serial Bus Isolation section of this data sheet.
2
single four port quad, packed into a single I C address.
Interrupts and SMBAlert
Most port events can be configured to trigger an inter-
rupt, asserting INT and alerting the host to the event. This
removes the need for the host to poll the LTC4291-1,
minimizing serial bus traffic and conserving host CPU
cycles. Multiple LTC4291-1s can share a common INT
line, with the host using the SMBAlert protocol (ARA) to
determine which LTC4291-1 caused an interrupt.
EXTERNAL COMPONENT SELECTION
Power Supplies
The LTC4291-1/LTC4292 requires two supply voltages to
operate. V requires 3.3V (nominally) relative to DGND.
DD
V
requires a negative voltage of between –51V to –57V
EE
Register Description
for Type 3 PSEs, or –53V to –57V for Type 4 PSEs, rela-
tive to AGNDP.
For information on serial bus usage and device con-
figuration and status, refer to the LTC4291 Software
Programming documentation. Contact Analog Devices
to request this document.
Digital Power Supply
V
provides digital power for the LTC4291-1 processor.
ADcDeramic decoupling cap of at least 0.1μF should be
placed from V to DGND, as close as practical to each
DD
ISOLATION REQUIREMENTS
LTC4291-1. A 1.8V core voltage supply is generated inter-
nally and requires a 1µF ceramic decoupling cap between
the CAP1 pin and DGND.
IEEE 802.3 Ethernet specifications require that network
segments (including PoE circuitry) be electrically isolated
from the chassis ground of each network interface device.
However, network segments are not required to be iso-
lated from each other, provided that the segments are
connected to devices residing within a single building on
a single power distribution system.
In the LTC4291-1, V should be delivered by the host
DD
controller’s non-isolated 3.3V supply. To maintain required
isolation, LTC4292 AGNDP and LTC4291-1 DGND must
not be connected in any way.
For simple devices, such as small PoE switches, the isola-
tion requirement can be met by using an isolated main
power supply for the entire device. This strategy can be
used if the device has no electrically conducting ports
other than twisted-pair Ethernet. In this case, the SDAIN
and SDAOUT pins can be tied together and will act as a
Main PoE Power Supply
V
is the main isolated PoE supply that provides power
EE
to the PDs. Because it supplies a relatively large amount
of power and is subject to significant current transients,
it requires more design care than a simple logic supply.
For minimum IR loss and best system efficiency, set V
EE
2
standard I C/SMBus SDA pin.
near maximum amplitude (57V), leaving enough margin
to account for transient over or undershoot, temperature
drift, and the line regulation specifications of the particular
power supply used.
If the device is part of a larger system, contains additional
external non-Ethernet ports, or must be referenced to pro-
tective ground for some other reason, the PoE subsystem
must be electrically isolated from the rest of the system.
Rev 0
32
For more information www.analog.com
LTC4291-1/LTC4292
APPLICATIONS INFORMATION
Bypass capacitance between AGNDP and VEE is very
important for reliable operation. If a short circuit occurs
at one of the output ports it can take as long as 1μs for
the LTC4292 to begin regulating the current. During this
time the current is limited only by the small impedances
in the circuit; a high current spike typically occurs, caus-
transformers do not have common-mode chokes. These
transformers typically provide 1500V of isolation between
the LTC4291-1 and the LTC4292. For proper operation,
strict layout guidelines must be met.
External MOSFET
ing a voltage transient on the V supply and possibly
EE
Careful selection of the power MOSFET is critical to sys-
tem reliability. Choosing a MOSFET requires extensive
analysis and testing of the MOSFET SOA curve against the
various PSE current limit conditions. ADI recommends
the PSMN075-100MSE for PSEs configured to deliver
up to 51W maximum port power (single-signature) or
25.5W maximum pairset power (dual-signature). For
PSEs configured to power up to 71.3W maximum port
power (single-signature) or 35.6W maximum pairset
power (dual-signature), ADI recommends the PSMN040-
100MSE. These MOSFETs are selected for their proven
reliability in PoE applications. Contact ADI Applications
before using a MOSFET other than one of these recom-
mended parts.
causing the LTC4291-1/LTC4292 to reset due to a UVLO
fault. A 1μF, 100V X7R capacitor placed near the V and
EE
AGNDP pins along with an electrolytic bulk capacitor of at
least 47µF across the supply is recommended to minimize
spurious resets.
Serial Bus Isolation
The LTC4291-1/LTC4292 chipset uses transformers to
isolate the LTC4291-1 from the LTC4292 (see Figure 25).
In this case, the SDAIN and SDAOUT pins can be shorted
to each other and tied directly to the I2C/SMBus bus.
The transformers should be 10BASE-T or 10/100BASE-T
with a 1:1 turns ratio. It is optimal that the selected
AGNDP
10Ω
3.3V
ISOLATION
V
AGNDP
DD
GP0
GP1
CPD
CPA
PWRMD1
PWRMD0
4PVALID
RESET
MSD
AUTO
INT
SOLATION
UIRED ON
NTERFACE
100Ω
100Ω
•
•
•
3.3V
3.3V
V
EE
100Ω
100Ω
OUTnB
GATEnB
CND
DPD
CNA
DPA
LTC4291-1
LTC4292
SCL
SDAIN
SDAOUT
SENSEnB
100Ω
100Ω
PORTn
•
V
OUTnA
GATEnA
EE
AD0
AD1
AD2
AD3
100Ω
100Ω
SENSEnA
DND
DNA
V
DGND
EE
42911 F25
2nF 2kV
V
EE
Figure 25. LTC4291-1/LTC4292 Proprietary Isolation
Rev 0
33
For more information www.analog.com
LTC4291-1/LTC4292
APPLICATIONS INFORMATION
Sense Resistors
the LTC4292 AGNDP pin and V pin is a SMAJ58A 58V
EE
TVS (D1) and a 1µF, 100V bypass capacitor (C1). These
components must be placed close to the LTC4292 pins.
The LTC4291-1/LTC4292 is designed for a low 0.15Ω cur-
rent sense resistance per channel. Two parallel 0.3Ω resis-
tors must be laid out as shown in the Layout Requirements
Finally, each port requires a pair of S1B clamp diodes: one
from OUTnM to supply AGND and one from OUTnM to
section. In order to meet the I
, I
, and I
HOLD-2P CUT-2P
accuracy required by the IEEE specification, the LsIeMn-s2Pe
resistors should have 1% tolerance or better, and no
more than 200ppm/°C temperature coefficient.
supply V . The diodes at the ports steer harmful surges
EE
into the supply rails where they are absorbed by the surge
suppressors and the V bypass capacitance. The layout
EE
of these paths must be low impedance.
Port Output Cap
Each port requires a 0.22μF cap across OUTnM to AGNDP
(see Figure 25) to keep the LTC4292 stable while in cur-
rent limit during startup or overload. Common ceramic
capacitors often have significant voltage coefficients; this
means the capacitance is reduced as the applied voltage
increases. To minimize this problem, X7R ceramic capaci-
tors rated for at least 100V are recommended and must
be located close to the LTC4292.
LAYOUT REQUIREMENTS
Strict adherence to board layout, parts placement and
routing requirements is critical for IEEE compliance, para-
metric measurement accuracy, system robustness and
thermal dissipation. Refer to the DC2685A demo kit for
example layout references.
Sense Resistor Block Layout Requirements
A channel sense resistor may be affected by currents
flowing in other channels. To ensure IEEE parametric
compliance, the sense resistor layout is strictly defined
and must be adhered to. In addition, the sense resistor
Surge Protection
Ethernet ports can be subject to significant cable surge
events. To keep PoE voltages below a safe level and pro-
tect the application against damage, protection compo-
nents, as shown in Figure 26, are required at the main
supply, at the LTC4292 supply pins, and at each port.
block’s common V plane connections and layout are
EE
specified.
Figure 33 shows the component names for ports 1 and 2
as referenced in the remainder of this section. The sense
resistors (RST1 to RST4 and RSU1 to RSU4) for channels
1A, 1B, 2A, and 2B must be grouped together in a sense
resistor block. The same requirements apply to channel
3A, 3B, 4A, and 4B sense resistors and VSSK34.
Bulk transient voltage suppression (TVS
) and bulk
capacitance (CBULK) are required acrossBUthLeK main PoE
supply and should be sized to accommodate system level
surge requirements.
Each LTC4292 requires a 10Ω, 0805 resistor (R1) in series
from supply AGND to the LTC4292 AGNDP pin. Across
R1
10Ω
AGNDP
AGNDP
C1
1µF
100V
D1
SMAJ58A
LTC4292
V
+
EE
C
BULK
VSSKn SENSEnM GATEnM OUTnM
TVS
BULK
Cn
0.22µF
X7R
S1B
S1B
100V
OUTnM
TO
PORT
AGNDP
V
EE
QnM
RSENSEnM
V
42911 F26
EE
Figure 26. LTC4292 Surge Protection
Rev 0
34
For more information www.analog.com
LTC4291-1/LTC4292
APPLICATIONS INFORMATION
copper area and connect the common copper in this area
on all four layers. The power vias must be sized to a 17mil
drill and 30mil diameter annular ring.
Figure 27 shows the top layer PCB placement of sense
resistors RST1 to RST4. Each bottom layer sense resistor,
RSU1 to RSU4, is placed directly underneath its paired
top layer sense resistor. The V –facing side of the sense
EE
Figure 32 is the PCB layer structure defining the copper
thickness requirements for each layer.
resistors connect to a common V copper area on the
EE
solder pad top edge with a 5mil to 10mil overlap.
Kelvin Sense
Figure 28 shows the top component layer common V
EE
area copper requirements. On the top layer, the common
Proper Kelvin sensing must be implemented in the layout.
VSSK12 connects to a series resistor RK1 in Figure 33.
From RK1 (Figure 28), a Kelvin sense small signal trace
connects to VEE only on layer 3 at the centroid top of
the sense resistors (RST1 to RST4 and RSU1 to RSU4)
V
EE
area copper is extended at the bottom center down
to the length of the sense resistor pads to allow copper
to flow between the two center sense resistors and bot-
tom center power via. A 10mil keepout is placed around
the common V copper area and V pads of the sense
EE
EE
common V copper area (Figure 30). A 10mil keepout
EE
resistors. These instructions for the top component layer
must be placed around the RK1 solder pad that leads to
are repeated for the bottom component layer.
V
EE
(Figure 28); around the trace from RK1 to the cen-
troid (Figures 28 and 30); on all layers around any vias
that connect the trace to different layers (Figures 28, 29,
and 30).
Figure 29 shows the inner layer 2 (V plane) common
EE
EE
V
copper area requirements. A 10mil keepout is placed
around the common V copper area; the exception is the
EE
bottom center where the common VEE area copper opens
At each of the sense resistors, on the side facing
SENSEnM, a power via is placed as close to the respec-
tive solder pads as allowed by the layout DRC. This power
via connects the top and bottom sense resistor pair for
a channel. A Kelvin sense small signal trace connects
SENSEnM directly to the respective sense resistor pair
via shown in Figure 30. A separate power path wide trace
connects from the sense resistor pair to the MOSFET.
SENSEnM must not connect to anywhere else on the
power path between the sense resistor and the MOSFET.
up to the V plane. The common V copper area only
EE
EE
connects to V on layer 2.
EE
Figure 30 shows the inner layer 3 (AGND plane and rout-
ing) common VEE area copper requirements. A 10mil
keepout is placed around the common V copper area
EE
to separate it from the surrounding AGND plane.
Figure 31 shows the common V copper area power via
EE
placement. There are 15 power vias in the common V
EE
Rꢆꢂ
Rꢇꢂ
ꢆꢀꢀꢇꢂꢃ ꢆꢈꢉ
ꢄ00ꢇꢈꢉ
ꢊ0ꢇꢈꢉ
Rꢀꢁꢂ Rꢀꢁꢃ
Rꢀꢁꢄ Rꢀꢁꢅ
Rꢀꢁꢂ Rꢀꢁꢃ
Rꢀꢁꢄ Rꢀꢁꢅ
ꢂꢂ0ꢋꢌꢍ
ꢃꢊ0ꢋꢌꢍ
ꢅꢃꢊꢂꢂ ꢙꢃꢚ
ꢅꢃꢎꢂꢂ ꢏꢃꢐ
ꢋꢌꢁꢍꢀꢎ ꢏRꢐꢑꢒꢋꢓ ꢋꢌꢁ ꢁꢌ ꢀꢔꢐꢕꢍꢖ
Rꢆꢂ ꢌꢋꢕꢗ ꢌꢋ ꢁꢌꢘ ꢕꢐꢗꢍRꢖ
ꢑꢒꢁꢓꢀꢔ ꢕRꢉꢖꢈꢑꢗ ꢑꢒꢁ ꢁꢒ ꢀꢘꢉꢙꢓꢚ
ꢆꢀꢀꢇꢂꢃ ꢆꢈꢉ ꢈꢀꢒꢙꢉꢁꢓꢕ ꢒꢑ ꢁꢒꢛ ꢉꢑꢕ ꢜꢒꢁꢁꢒꢋ ꢙꢉꢝꢓRꢀꢚ
Figure 27. Top Component Layer Sense Resistors Placement
Figure 28. Top and Bottom Layer Sense Resistor Block Layout
Rev 0
35
For more information www.analog.com
LTC4291-1/LTC4292
APPLICATIONS INFORMATION
ꢕ00ꢚꢛꢜ
ꢅꢆ ꢈꢉꢊꢋꢇꢌ
ꢇꢇ
ꢀ00ꢁꢂꢃ
ꢄ0ꢁꢂꢃ
ꢓ0ꢚꢛꢜ
ꢍꢀ0ꢁꢂꢃ
ꢖꢇꢊꢀꢆ ꢗꢌꢇꢀꢃꢘ
ꢚꢙꢄꢍꢍ ꢛꢙꢄ
ꢒꢑꢓꢐꢐ ꢔꢕ0
ꢋꢎꢏꢇꢐꢑ ꢒRꢊꢓꢔꢋꢕ ꢋꢎꢏ ꢏꢎ ꢐꢖꢊꢉꢇꢗ
ꢆꢐꢐꢘꢍꢙ ꢆꢔꢊ ꢔꢐꢎꢉꢊꢏꢇꢒꢗ
ꢀꢁꢂꢃꢄꢅ ꢆRꢇꢈꢉꢀꢊ ꢀꢁꢂ ꢂꢁ ꢄꢋꢇꢌꢃꢍ
ꢎꢄꢄꢏꢐꢑ ꢎꢉꢇ ꢋꢁꢀꢀꢃꢋꢂꢄ ꢎ
ꢍ
ꢃꢃ
Figure 29. Inner Layer 2 Sense Resistor Block Layout
(VEE Plane)
Figure 30. Inner Layer 3 Sense Resistor Block Layout
(AGND/Signal Plane)
Rꢚꢑ
ꢏꢎ0ꢔꢕꢖ
ꢑꢘ0ꢔꢕꢖ
ꢙ0ꢔꢕꢖ
ꢎ0ꢔꢕꢖ
ꢎ0ꢔꢕꢖ
ꢏꢗꢔꢕꢖ
ꢎꢏꢐꢑꢑ ꢒꢓꢑ
ꢀꢁꢂꢃꢄ ꢅRꢆꢇꢈꢀꢉ ꢀꢁꢂ ꢂꢁ ꢊꢋꢆꢌꢃꢍ
Figure 31. Sense Resistor Block Via Specifications
Figure 32. PCB Layer Structure
Rev 0
36
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LTC4291-1/LTC4292
TYPICAL APPLICATION
Figure 33. Alternative A (MDI-X) and Alternative B(S), 1000BASE-T, IEEE 802.3bt, Type 3 or Type 4 PSE, Ports 1 and 2 Shown
ꢀꢁꢂꢃꢄ
10Ω
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
0.22μF
ꢀ00ꢁ
ꢀꢁ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀ
75Ω
ꢀꢁꢂꢃꢄꢁ
ꢀꢁ
ꢀꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢀꢁꢃꢄ
ꢀꢁRꢂ ꢃ
ꢀꢁꢂꢁ ꢁꢃꢀ
ꢀꢁꢂꢃR ꢁꢄꢅ
RST1
0.3Ω
RSU1
0.3Ω
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
75Ω
75Ω
75Ω
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢀ
ꢀꢁꢂꢃꢄ
Rꢀꢁꢂ
0.22μF
ꢀ00ꢁ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁ
ꢀꢁꢂꢀꢁꢃꢄ
ꢀ000ꢁꢂ
ꢀꢁꢂ
RST2
0.3Ω
RSU2
0.3Ω
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀ
ꢀꢀ
ꢀꢁꢂꢃꢄꢅꢄ
0.22μF
100V
PWRMD0
PWRMD1
Q1 TO Q4
ꢀꢁꢂ
0.15Ω
ꢀꢁꢁꢂꢃꢄ
0
0
0
R
0
ꢀ
ꢀꢀ
00
ꢀ
ꢀꢀ
0
R
0 0 00
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
0.22μF
ꢀ00ꢁ
ꢀꢁ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄꢁ
ꢀꢁꢂ
75Ω
ꢀꢁ
ꢀ
ꢀꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢀꢁꢃꢄ
ꢀꢁRꢂ ꢃ
RST3
0.3Ω
RSU3
0.3Ω
ꢀꢁꢂꢁ ꢁꢃꢀ
ꢀꢁꢂꢃR ꢁꢄꢅ
75Ω
75Ω
75Ω
ꢀ
ꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁRꢂꢃ0
ꢀꢁRꢂꢃꢄ
ꢀꢁꢂꢃꢄ
Rꢀꢁꢂ
0.22μF
ꢀ00ꢁ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁ
ꢀꢁꢂꢀꢁꢃꢄ
ꢀ000ꢁꢂ
ꢀꢁꢂ
RST4
0.3Ω
RSU4
0.3Ω
ꢀ
ꢀꢀ
ꢀꢁꢂ
ꢀ
ꢀ
ꢀꢀ
ꢀꢀ
ꢀꢁꢂ ꢀꢃꢄ ꢅꢆRꢀꢇ ꢈꢉꢊ0ꢃꢃ0ꢁꢋ
ꢀꢁꢂꢃꢀRꢄꢅꢆ ꢇꢆꢈꢉꢊꢋ0ꢃ
CT1-CT8: 0.01μF, 200V
ꢀꢁꢂ
ꢀ
ꢀꢀ
Rev 0
37
For more information www.analog.com
LTC4291-1/LTC4292
PACKAGE DESCRIPTION
UF Package
24-Lead Plastic QFN (4mm × 4mm)
ꢃReꢪeꢫeꢬꢭe ꢗꢋꢔ ꢆꢎꢏ ꢮ 0ꢡꢘ0ꢯꢘꢂꢤꢰꢥ Rev ꢑꢈ
0ꢁꢥ0 0ꢁ0ꢡ
ꢀꢁꢡ0 0ꢁ0ꢡ
ꢝꢁꢂ0 0ꢁ0ꢡ
ꢙꢁꢀꢡ 0ꢁ0ꢡ
ꢃꢀ ꢄꢅꢆꢇꢄꢈ
ꢐꢍꢔꢕꢍꢏꢇ ꢊꢖꢋꢗꢅꢉꢇ
0ꢁꢙꢡ 0ꢁ0ꢡ
0ꢁꢡ0 ꢑꢄꢔ
Rꢇꢔꢊꢒꢒꢇꢉꢆꢇꢆ ꢄꢊꢗꢆꢇR ꢐꢍꢆ ꢐꢅꢋꢔꢟ ꢍꢉꢆ ꢆꢅꢒꢇꢉꢄꢅꢊꢉꢄ
ꢑꢊꢋꢋꢊꢒ ꢚꢅꢇꢎꢜꢇꢛꢐꢊꢄꢇꢆ ꢐꢍꢆ
R ꢦ 0ꢁꢂꢂꢡ
ꢐꢅꢉ ꢂ ꢉꢊꢋꢔꢟ
R ꢦ 0ꢁꢙ0 ꢋꢣꢐ ꢊR
0ꢁꢝꢡ × ꢀꢡꢩ ꢔꢟꢍꢒꢞꢇR
0ꢁꢥꢡ 0ꢁ0ꢡ
ꢀꢁ00 0ꢁꢂ0
ꢃꢀ ꢄꢅꢆꢇꢄꢈ
ꢋꢣꢐ
ꢙꢝ ꢙꢀ
ꢐꢅꢉ ꢂ
ꢋꢊꢐ ꢒꢍRꢕ
ꢃꢉꢊꢋꢇ ꢤꢈ
0ꢁꢀ0 0ꢁꢂ0
ꢂ
ꢙ
ꢙꢁꢀꢡ 0ꢁꢂ0
ꢃꢀꢘꢄꢅꢆꢇꢄꢈ
ꢃꢖꢞꢙꢀꢈ ꢨꢞꢉ 0ꢂ0ꢡ Rꢇꢚ ꢑ
0ꢁꢙ00 Rꢇꢞ
0ꢁꢙꢡ 0ꢁ0ꢡ
0ꢁꢡ0 ꢑꢄꢔ
0ꢁ00 ꢧ 0ꢁ0ꢡ
ꢉꢊꢋꢇꢌ
ꢂꢁ ꢆRꢍꢎꢅꢉꢏ ꢐRꢊꢐꢊꢄꢇꢆ ꢋꢊ ꢑꢇ ꢒꢍꢆꢇ ꢍ ꢓꢇꢆꢇꢔ ꢐꢍꢔꢕꢍꢏꢇ ꢊꢖꢋꢗꢅꢉꢇ ꢒꢊꢘꢙꢙ0 ꢚꢍRꢅꢍꢋꢅꢊꢉ ꢃꢎꢏꢏꢆꢘꢛꢈꢜꢋꢊ ꢑꢇ ꢍꢐꢐRꢊꢚꢇꢆ
ꢙꢁ ꢆRꢍꢎꢅꢉꢏ ꢉꢊꢋ ꢋꢊ ꢄꢔꢍꢗꢇ
ꢝꢁ ꢍꢗꢗ ꢆꢅꢒꢇꢉꢄꢅꢊꢉꢄ ꢍRꢇ ꢅꢉ ꢒꢅꢗꢗꢅꢒꢇꢋꢇRꢄ
ꢀꢁ ꢆꢅꢒꢇꢉꢄꢅꢊꢉꢄ ꢊꢞ ꢇꢛꢐꢊꢄꢇꢆ ꢐꢍꢆ ꢊꢉ ꢑꢊꢋꢋꢊꢒ ꢊꢞ ꢐꢍꢔꢕꢍꢏꢇ ꢆꢊ ꢉꢊꢋ ꢅꢉꢔꢗꢖꢆꢇ
ꢒꢊꢗꢆ ꢞꢗꢍꢄꢟꢁ ꢒꢊꢗꢆ ꢞꢗꢍꢄꢟꢠ ꢅꢞ ꢐRꢇꢄꢇꢉꢋꢠ ꢄꢟꢍꢗꢗ ꢉꢊꢋ ꢇꢛꢔꢇꢇꢆ 0ꢁꢂꢡꢢꢢ ꢊꢉ ꢍꢉꢣ ꢄꢅꢆꢇꢠ ꢅꢞ ꢐRꢇꢄꢇꢉꢋ
ꢡꢁ ꢇꢛꢐꢊꢄꢇꢆ ꢐꢍꢆ ꢄꢟꢍꢗꢗ ꢑꢇ ꢄꢊꢗꢆꢇR ꢐꢗꢍꢋꢇꢆ
ꢤꢁ ꢄꢟꢍꢆꢇꢆ ꢍRꢇꢍ ꢅꢄ ꢊꢉꢗꢣ ꢍ RꢇꢞꢇRꢇꢉꢔꢇ ꢞꢊR ꢐꢅꢉ ꢂ ꢗꢊꢔꢍꢋꢅꢊꢉ
ꢊꢉ ꢋꢟꢇ ꢋꢊꢐ ꢍꢉꢆ ꢑꢊꢋꢋꢊꢒ ꢊꢞ ꢐꢍꢔꢕꢍꢏꢇ
Rev 0
38
For more information www.analog.com
LTC4291-1/LTC4292
PACKAGE DESCRIPTION
UJ Package
40-Lead Plastic QFN (6mm × 6mm)
ꢃReꢬeꢭeꢮꢯe ꢖꢌꢒ ꢇꢏꢐ ꢰ 0ꢣꢙ0ꢱꢙꢂꢨꢚꢱ Rev ꢫꢉ
0ꢁꢨ0 0ꢁ0ꢣ
ꢀꢁꢣ0 0ꢁ0ꢣ
ꢣꢁꢂ0 0ꢁ0ꢣ
ꢄꢁꢄꢚ 0ꢁ0ꢣ
ꢄꢁꢣ0 0ꢁ0ꢣ
ꢃꢄ ꢅꢆꢇꢈꢅꢉ
ꢄꢁꢄꢚ 0ꢁ0ꢣ
ꢓꢎꢒꢔꢎꢐꢈ ꢋꢕꢌꢖꢆꢊꢈ
0ꢁꢚꢣ 0ꢁ0ꢣ
0ꢁꢣ0 ꢞꢅꢒ
Rꢈꢒꢋꢜꢜꢈꢊꢇꢈꢇ ꢅꢋꢖꢇꢈR ꢓꢎꢇ ꢓꢆꢌꢒꢟ ꢎꢊꢇ ꢇꢆꢜꢈꢊꢅꢆꢋꢊꢅ
ꢎꢓꢓꢖꢢ ꢅꢋꢖꢇꢈR ꢜꢎꢅꢔ ꢌꢋ ꢎRꢈꢎꢅ ꢌꢟꢎꢌ ꢎRꢈ ꢊꢋꢌ ꢅꢋꢖꢇꢈRꢈꢇ
0ꢁꢨꢣ 0ꢁ0ꢣ
R ꢤ 0ꢁꢂꢂꢣ
ꢀꢁ00 0ꢁꢂ0
ꢃꢄ ꢅꢆꢇꢈꢅꢉ
ꢌꢢꢓ
R ꢤ 0ꢁꢂ0
ꢌꢢꢓ
ꢛꢦ ꢄ0
0ꢁꢄ0 0ꢁꢂ0
ꢂ
ꢓꢆꢊ ꢂ ꢌꢋꢓ ꢜꢎRꢔ
ꢃꢅꢈꢈ ꢊꢋꢌꢈ ꢀꢉ
ꢚ
ꢓꢆꢊ ꢂ ꢊꢋꢌꢒꢟ
R ꢤ 0ꢁꢄꢣ ꢋR
0ꢁꢛꢣ × ꢄꢣꢥ
ꢒꢟꢎꢜꢘꢈR
ꢄꢁꢄꢚ 0ꢁꢂ0
ꢄꢁꢣ0 Rꢈꢘ
ꢃꢄꢙꢅꢆꢇꢈꢅꢉ
ꢄꢁꢄꢚ 0ꢁꢂ0
ꢃꢕꢑꢄ0ꢉ ꢪꢘꢊ Rꢈꢗ ꢫ 0ꢄ0ꢀ
0ꢁꢚ00 Rꢈꢘ
0ꢁꢚꢣ 0ꢁ0ꢣ
0ꢁꢣ0 ꢞꢅꢒ
0ꢁ00 ꢩ 0ꢁ0ꢣ
ꢊꢋꢌꢈꢍ
ꢞꢋꢌꢌꢋꢜ ꢗꢆꢈꢏꢧꢈꢝꢓꢋꢅꢈꢇ ꢓꢎꢇ
ꢂꢁ ꢇRꢎꢏꢆꢊꢐ ꢆꢅ ꢎ ꢑꢈꢇꢈꢒ ꢓꢎꢒꢔꢎꢐꢈ ꢋꢕꢌꢖꢆꢊꢈ ꢗꢎRꢆꢎꢌꢆꢋꢊ ꢋꢘ ꢃꢏꢑꢑꢇꢙꢚꢉ
ꢚꢁ ꢇRꢎꢏꢆꢊꢐ ꢊꢋꢌ ꢌꢋ ꢅꢒꢎꢖꢈ
ꢛꢁ ꢎꢖꢖ ꢇꢆꢜꢈꢊꢅꢆꢋꢊꢅ ꢎRꢈ ꢆꢊ ꢜꢆꢖꢖꢆꢜꢈꢌꢈRꢅ
ꢄꢁ ꢇꢆꢜꢈꢊꢅꢆꢋꢊꢅ ꢋꢘ ꢈꢝꢓꢋꢅꢈꢇ ꢓꢎꢇ ꢋꢊ ꢞꢋꢌꢌꢋꢜ ꢋꢘ ꢓꢎꢒꢔꢎꢐꢈ ꢇꢋ ꢊꢋꢌ ꢆꢊꢒꢖꢕꢇꢈ
ꢜꢋꢖꢇ ꢘꢖꢎꢅꢟꢁ ꢜꢋꢖꢇ ꢘꢖꢎꢅꢟꢠ ꢆꢘ ꢓRꢈꢅꢈꢊꢌꢠ ꢅꢟꢎꢖꢖ ꢊꢋꢌ ꢈꢝꢒꢈꢈꢇ 0ꢁꢚ0ꢡꢡ ꢋꢊ ꢎꢊꢢ ꢅꢆꢇꢈꢠ ꢆꢘ ꢓRꢈꢅꢈꢊꢌ
ꢣꢁ ꢈꢝꢓꢋꢅꢈꢇ ꢓꢎꢇ ꢅꢟꢎꢖꢖ ꢞꢈ ꢅꢋꢖꢇꢈR ꢓꢖꢎꢌꢈꢇ
ꢀꢁ ꢅꢟꢎꢇꢈꢇ ꢎRꢈꢎ ꢆꢅ ꢋꢊꢖꢢ ꢎ RꢈꢘꢈRꢈꢊꢒꢈ ꢘꢋR ꢓꢆꢊ ꢂ ꢖꢋꢒꢎꢌꢆꢋꢊ ꢋꢊ ꢌꢟꢈ ꢌꢋꢓ ꢎꢊꢇ ꢞꢋꢌꢌꢋꢜ ꢋꢘ ꢓꢎꢒꢔꢎꢐꢈ
Rev 0
39
For more information www.analog.com
LTC4291-1/LTC4292
TYPICAL APPLICATION
Figure 34. IEEE 802.3bt Type 3 or Type 4 PSE, Alternative A (MDI-X) and Alternative B(S), 1000BASE-T, 1 of 4 Ports Shown
ꢀꢁꢂꢃꢄ
10Ω
ꢀꢁꢂꢃ ꢀꢁꢄꢅ ꢆꢇꢈꢉ0ꢊ0ꢋꢌ00ꢈꢇꢍ
ꢀꢁꢂ ꢃꢄꢅꢆꢇꢈꢉ
ꢀꢁꢂ
ꢀ00ꢁ
0ꢀꢁꢂꢃ
ꢀꢁꢀꢂ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁꢂ ꢃꢄꢅꢆꢇꢈꢅ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀ
0ꢀꢁꢁꢂꢃ
ꢀ00ꢁ
ꢀꢀ
ꢀꢁꢂ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢀꢂꢆ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢀ
ꢀꢁ0
ꢀꢁRꢂꢃ0
ꢀꢁꢂ
ꢀꢁRꢂꢃꢄ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢁ
4PVALID
ꢀꢁꢂ
0.15Ω
100Ω
100Ω
ꢀꢁꢂꢃ
ꢀ
ꢀꢀ
ꢀ
ꢀ
ꢀꢁꢀꢂ
ꢀ
ꢀꢁꢂꢀꢁꢃꢄ
ꢀꢁꢁꢂꢃ
ꢀꢀ
ꢀꢁꢂ ꢃ ꢀ
RESET
ꢀꢁꢂꢃꢄꢅꢀꢂꢆ
RꢀꢁꢂꢃRꢀꢄꢅ
ꢀ
100Ω
100Ω
MSD
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
0ꢀꢁꢁꢂꢃ
ꢀ00ꢁ
ꢀꢁꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢆꢇꢆ
ꢀꢁꢂꢃꢄꢅꢄ
ꢀꢁꢂ
INT
ꢀ
100Ω
100Ω
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁꢀꢂ
ꢀ
ꢀꢀ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄꢅ
ꢀ
ꢀꢁꢂ
0.15Ω
100Ω
100Ω
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀꢀ
0ꢀꢁꢁꢂꢃ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂꢀꢁꢃꢄ
ꢀꢁꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
Rꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ000ꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢀ
ꢀ
ꢀꢁꢁꢂꢃ
ꢀꢀ
0.22μF, 100V
0.15Ω
ꢀꢁ ꢂꢃ ꢄ ꢅꢂRꢆꢇꢈ
ꢀꢁꢂꢃꢄ
ꢀ
ꢀꢀ
ꢀꢁꢁꢂꢃ
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
External Switch, IEEE 802.3bt Support Configurable Class
++
+
LT4294
LT4295
LTPoE /PoE /PoE PD Controller
IEEE 802.3bt PD with Forward/Flyback
Switching Regulator Controller
External Switch, IEEE 802.3bt Support, Configurable Class, Forward or No-Opto Flyback
Operation, Frequency, PG/SG Delays, Soft-Start, and Aux Support as Low as 9V, Including
Housekeeping Buck, Slope Compensation
LTC4257-1
LTC4263
LTC4265
LTC4266
LTC4267
IEEE 802.3af PD Interface Controller
Single IEEE 802.3af PSE Controller
IEEE 802.3at PD Interface Controller
Quad IEEE 802.3at PoE PSE Controller
Internal 100V, 400mA Switch, Dual Current Limit, Programmable Class
Internal FET Switch
Internal 100V, 1A Switch, 2-Event Classification Recognition
With Programmable I /I , 2-Event Classification, and Port Current and Voltage Monitoring
CUT LIM
IEEE 802.3af PD Interface with Integrated
Switching Regulator
Internal 100V, 400mA Switch, Dual Inrush Current, Programmable Class
LTC4269-1
LTC4269-2
IEEE 802.3at PD Interface with Integrated
Flyback Switching Regulator
2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller,
50kHz to 250kHz, Aux Support
IEEE 802.3at PD Interface with Integrated
Forward Switching Regulator
2-Event Classification, Programmable Class, Synchronous Forward Controller, 100kHz to
500kHz, Aux Support
®
+ ++
12-Port PoE/PoE /LTPoE
++
PSE Controller Transformer Isolation, Supports Type 1, Type 2 and LTPoE PDs
LTC4270/
LTC4271
LTC4278
IEEE 802.3at PD Interface with Integrated
Flyback Switching Regulator
2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller,
50kHz to 250kHz, 12V Aux Support
+
++
++
Supports IEEE 802.3af, IEEE 802.3at, LTPoE and Proprietary PDs
LTC4279
Single PoE/PoE /LTPoE PSE Controller
+
++
++
Transformer Isolation, Supports IEEE 802.3af, IEEE 802.3at and LTPoE PDs
LTC4290/
LTC4271
8-Port PoE/PoE /LTPoE PSE Controller
Rev 0
D17158-0-10/18(0)
www.analog.com
40
ANALOG DEVICES, INC. 2018
相关型号：
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LTC4300-1/LTC4300-2 - Hot Swappable 2-Wire Bus Buffers; Package: MSOP; Pins: 8; Temperature Range: 0°C to 70°C
Linear
LTC4300-1CMS8#TRPBF
LTC4300-1/LTC4300-2 - Hot Swappable 2-Wire Bus Buffers; Package: MSOP; Pins: 8; Temperature Range: 0°C to 70°C
Linear
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Linear
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