LTC4372 [ADI]
Low Quiescent Current Ideal Diode Controller;
| 型号： | LTC4372 |
| 厂家： | 
ADI |
| 描述： | Low Quiescent Current Ideal Diode Controller |
| 文件： | 总20页 (文件大小：1410K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4372/LTC4373
Low Quiescent Current Ideal Diode Controller
FEATURES
DESCRIPTION
The LTC®4372/LTC4373 are positive high voltage ideal
diode controllers that drive an external N-channel
MOSFET to replace a Schottky diode. They control the
forward voltage drop across the MOSFET to ensure cur-
rent delivery or current transfer from one path to the other
even at light loads.
n
Reduces Power Dissipation by Replacing a Power
Schottky Diode
Low Quiescent Current: 5µA Operating, 0.5µA
Shutdown
Wide Operating Voltage Range: 2.5V to 80V
Reverse Supply Protection to –28V
High Side External N-Channel MOSFET Drive
Drives Back-to-Back MOSFETs for Inrush Control and
Load Switching
n
n
n
n
n
A 5µA operating current achieves high efficiency for inter-
mittent load applications or always-on backup power sup-
plies. If a power source fails or is shorted, a fast turn-
off minimizes reverse current transients. The LTC4372/
LTC4373 control back-to-back N-channel MOSFETs for
inrush current control and load switching.
n
n
Fast Reverse Current Turn-Off within 1.5µs
8-Lead MSOP and 3mm × 3mm DFN Packages
APPLICATIONS
The LTC4372 shutdown function reduces the quiescent
current to 0.5µA. The LTC4373 has a UV pin for undervolt-
age monitoring while the UVOUT pin provides hysteresis
adjustment and status information. During undervoltage,
the back-to-back MOSFETs are cut off and quiescent cur-
rent reduces to 0.5μA.
n
Automotive Battery Protection
n
Redundant Power Supplies
n
Portable Instrumentation
Solar Powered Systems
Energy Harvesting Applications
n
n
All registered trademarks and trademarks are the property of their respective owners.
n
Supply Holdup
TYPICAL APPLICATION
12V, 20A Reverse Battery Protection
Power Dissipation vs Load Current
ꢀ0
ꢀ
ꢄꢅꢀ
ꢅ0ꢆ
ꢁꢂꢃ
ꢀꢁꢂ0ꢃꢄꢅ0ꢆꢅꢁꢇ
ꢀ
ꢀ ꢁꢂꢃ
ꢁꢂ
ꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀ ꢀꢀꢀꢀꢀ ꢀꢀꢀꢀꢀ0ꢀ0ꢀꢀꢀ
ꢀ
ꢀꢁ ꢀꢁꢂRꢃꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂ
10μF
ꢀꢁꢂꢁ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢀꢀꢀR
ꢀꢀꢀꢀꢀ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢄꢄ
ꢀꢁꢂꢃꢁ ꢄꢅ0ꢆꢇ
ꢀ
ꢀ00ꢁꢂ
ꢀꢀꢀꢀꢀꢀ ꢀꢀꢀꢀ0ꢀꢀꢀ0ꢀꢀꢀꢁꢀ
0
ꢀ0
ꢀꢀ
0
ꢀ0
ꢀ
ꢀꢀRRꢀꢀꢀ ꢀꢀꢀ
ꢀꢁꢂꢃꢁ ꢄꢅ0ꢆꢇ
Rev. 0
1
Document Feedback
For more information www.analog.com
LTC4372/LTC4373
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Operating Ambient Temperature Range
IN, SOURCE ...............................................–28V to 100V
OUT..............................................................–2V to 100V
IN – OUT .................................................–100V to 100V
IN – SOURCE ...............................................–1V to 100V
SOURCE – OUT........................................–100V to 100V
GATE – SOURCE (Note 3) .......................... –0.3V to 10V
SHDN, UV, 2UPU, UVOUT......................... –0.3V to 100V
LTC4372C, LTC4373C.............................. 0°C to 70°C
LTC4372I, LTC4373I ............................–40°C to 85°C
LTC4372H, LTC4373H ....................... –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 Sec)
MSOP Package .................................................300°C
INTV ......................................................... –0.3V to 6V
CC
PIN CONFIGURATION
LTC4372
LTC4372
ꢀꢁꢂ ꢃꢄꢅꢆ
ꢆꢄꢔ ꢕꢌꢉꢖ
ꢁꢦꢀ
ꢋꢈꢀꢅ
ꢛ
ꢥ
ꢐ
ꢟ
ꢌ
ꢤ
ꢣ
ꢜ
ꢔꢧꢇꢖ
ꢥꢦꢂꢦ
ꢋꢖꢇ
ꢄꢅꢆ ꢀ
ꢇꢈꢆꢉ ꢁ
ꢎ ꢊꢒꢓꢍ
ꢏ ꢁꢅꢔꢅ
ꢐ ꢇꢍꢓ
ꢑ ꢌꢍꢆꢕ
ꢡ
ꢔꢁꢦRꢉꢅ
ꢄꢖ
ꢊꢄꢅRꢋꢉ
ꢂ
ꢃ
ꢌꢍ
ꢋꢋ
ꢄꢖꢀꢃ
ꢉꢉ
ꢗꢊꢎ ꢔꢈꢋꢘꢈꢇꢉ
ꢎꢙꢚꢉꢈꢓ ꢔꢚꢈꢊꢆꢌꢋ ꢗꢊꢄꢔ
ꢇꢇ ꢂꢈꢉꢊꢈꢋꢅ
ꢆ
ꢝ ꢀꢑ0ꢞꢋꢟ θ ꢝ ꢀꢐꢂꢞꢋꢠꢖ
ꢛꢗꢈꢜ
ꢛꢈ
ꢌꢍꢎꢅꢈꢇ ꢏꢐꢑꢑ ꢒ ꢐꢑꢑꢓ ꢂꢎꢈꢔꢀꢄꢉ ꢇꢕꢖ
ꢀ
ꢚ ꢛꢜ0ꢝꢉꢞ θ ꢚ ꢟꢐꢝꢉꢠꢆ
ꢗꢘꢈꢙ
ꢗꢈ
ꢅꢙꢂꢁꢔꢅꢇ ꢂꢈꢇ ꢏꢂꢄꢖ ꢡꢓ ꢂꢉꢢ ꢉꢁꢖꢖꢅꢉꢀꢄꢁꢖ ꢀꢁ ꢋꢖꢇ ꢄꢔ ꢁꢂꢀꢄꢁꢖꢈꢎ
LTC4373
LTC4373
ꢀꢁꢂ ꢃꢄꢅꢆ
ꢆꢄꢔ ꢒꢌꢉꢕ
ꢁꢦꢀ
ꢋꢈꢀꢅ
ꢛ
ꢥ
ꢐ
ꢟ
ꢌ
ꢤ
ꢣ
ꢜ
ꢦꢃ
ꢄꢅꢆ ꢀ
ꢇꢈꢆꢉ ꢁ
ꢎ ꢅꢒ
ꢏ UVOUT
ꢐ ꢇꢍꢓ
UVOUT
ꢋꢖꢇ
ꢡ
ꢔꢁꢦRꢉꢅ
ꢄꢖ
ꢊꢄꢅRꢋꢉ
ꢂ
ꢃ
ꢌꢍ
ꢑ ꢌꢍꢆꢒ
ꢋꢋ
ꢄꢖꢀꢃ
ꢉꢉ
ꢖꢊꢎ ꢔꢈꢋꢗꢈꢇꢉ
ꢎꢘꢙꢉꢈꢓ ꢔꢙꢈꢊꢆꢌꢋ ꢖꢊꢄꢔ
ꢇꢇ ꢂꢈꢉꢊꢈꢋꢅ
ꢆ
ꢜ ꢀꢑ0ꢝꢋꢞ θ ꢜ ꢀꢐꢂꢝꢋꢟꢕ
ꢚꢖꢈꢛ
ꢚꢈ
ꢌꢍꢎꢅꢈꢇ ꢏꢐꢑꢑ ꢒ ꢐꢑꢑꢓ ꢂꢎꢈꢔꢀꢄꢉ ꢇꢕꢖ
ꢀ
ꢚ ꢛꢜ0ꢝꢉꢞ θ ꢚ ꢟꢐꢝꢉꢠꢆ
ꢗꢘꢈꢙ
ꢗꢈ
ꢅꢙꢂꢁꢔꢅꢇ ꢂꢈꢇ ꢏꢂꢄꢖ ꢡꢓ ꢂꢉꢢ ꢉꢁꢖꢖꢅꢉꢀꢄꢁꢖ ꢀꢁ ꢋꢖꢇ ꢄꢔ ꢁꢂꢀꢄꢁꢖꢈꢎ
Rev. 0
2
For more information www.analog.com
LTC4372/LTC4373
ORDER INFORMATION
TUBE
TAPE AND REEL
PART MARKING*
LHGR
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
LTC4372CDD#PBF
LTC4372IDD#PBF
LTC4372HDD#PBF
LTC4372CMS8#PBF
LTC4372IMS8#PBF
LTC4372HMS8#PBF
LTC4373CDD#PBF
LTC4373IDD#PBF
LTC4373HDD#PBF
LTC4373CMS8#PBF
LTC4373IMS8#PBF
LTC4373HMS8#PBF
LTC4372CDD#TRPBF
LTC4372IDD#TRPBF
LTC4372HDD#TRPBF
LTC4372CMS8#TRPBF
LTC4372IMS8#TRPBF
LTC4372HMS8#TRPBF
LTC4373CDD#TRPBF
LTC4373IDD#TRPBF
LTC4373HDD#TRPBF
LTC4373CMS8#TRPBF
LTC4373IMS8#TRPBF
LTC4373HMS8#TRPBF
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead Plastic MSOP
LHGR
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
LHGR
LTHGS
LTHGS
8-Lead Plastic MSOP
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
LTHGS
8-Lead Plastic MSOP
LHMQ
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead Plastic MSOP
LHMQ
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
LHMQ
LTHMR
LTHMR
LTHMR
8-Lead Plastic MSOP
–40°C to 85°C
–40°C to 125°C
8-Lead Plastic MSOP
Contact the factory for parts specified with wider operating temperature ranges.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. IN = SOURCE =12V, SHDN = 0V, UV = 2V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
2.5
TYP
MAX
80
UNITS
l
l
V
V
Input Supply Voltage Range
Input Supply Undervoltage Lockout
Input Supply Undervoltage Lockout Hysteresis
V
V
IN
IN Rising
1.9
2.1
80
2.45
IN(UVL)
∆V
IN(HYST)
mV
l
V
Internal Regulator Voltage
Total Supply Current
I
= 0 to –10µA
2.5
3.5
4.5
V
INTVCC
INTVCC
I
Q
Diode Control: I
= –0.1µA
GATE
Single or Back-to-Back MOSFETs (Note 4)
(C-Grade, I-Grade)
I = I + I
+ I
OUT
Q
IN
SOURCE
l
l
5
5
10
20
µA
µA
(H-Grade)
Shutdown: SHDN = 2V, UV = 0V
Single MOSFET
l
l
3.5
0.5
10
2.5
µA
µA
Back-to-Back MOSFETs
Reverse Current: ∆V = –0.1V, IN = 12V
SD
l
l
Single MOSFET
20
10
30
20
µA
µA
Back-to-Back MOSFETs
l
l
I
I
I
OUT Current
IN – OUT = 4V
IN – OUT = –4V
–0.5
1.8
–10
5
µA
µA
OUT
l
IN + SOURCE Current During
Reverse Battery
IN = SOURCE = –24V, OUT = 24V
–1
–5
mA
NEG
l
l
OUT Current During Reverse Battery
Source-Drain Threshold (IN-OUT)
Maximum GATE Drive (GATE-SOURCE)
IN = SOURCE = –24V, OUT = 24V
0.3
30
0.5
45
mA
mV
OUT(NEG)
∆V
∆V
Low to High. Activates I
20
SD(T)
GATE(UP)
l
l
IN ≤ 5V, ∆V = 0.1V, I
= 0, –1µA
4.5
10
6.5
11.7
10
16
V
V
GATE(H)
SD
GATE
GATE
IN > 5V, ∆V = 0.1V, I
= 0, –1µA
SD
l
I
GATE Pull-Up Current
GATE = IN, ∆V = 0.1V
–15
–20
–25
µA
GATE(UP)
SD
Rev. 0
3
For more information www.analog.com
LTC4372/LTC4373
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. IN = SOURCE =12V, SHDN = 0V, UV = 2V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
0.5
70
TYP
1
MAX
3
UNITS
mA
mA
mA
V
l
l
l
l
l
l
l
I
GATE Pull-Down Current
Shutdown: SHDN = 2V, UV = 0V, ∆V
= 5V
GATE
GATE(DOWN)
Reverse Current: ∆V = –0.1V, ∆V
= 5V
130
130
–32
–1.8
0.5
230
230
–35
–2.7
1.5
SD
GATE
Reverse Battery: IN = SOURCE = –7V, GATE = –3V
= 10mA (Note 3)
70
V
V
GND-GATE clamp
I
–28
–0.9
GATE(NEG)
SOURCE(TH)
OFF
GATE
Reverse SOURCE Threshold for GATE Off
Gate Turn-Off Delay Time
Gate Turn-On Delay Time
GATE = 0V (Note 5)
∆V = Step 0.1V to –0.8V, C
V
t
t
= 0pF, ∆V <1V
GATE
µs
SD
GATE
IN = 12V, SOURCE = OUT = 0V, ∆V
> 4.5V,
GATE
100
500
1200
µs
ON
C
= 0pF, SHDN = 2V to 0V, UV = 0V to 1.25V
GATE
LTC4372
l
l
l
l
I
2UPU Pull-Up Current
SHDN Threshold
–1
1
–2
1.2
15
1
–3
1.4
40
50
µA
V
2UPU
V
SHDN Falling
SHDN = 1.2V
UV Falling
SHDN
VSHDN(HYST) SHDN Threshold Hysteresis
2
mV
nA
I
SHDN Leakage Current
SHDN
LTC4373
l
l
l
V
V
UV Threshold
1.174
2
1.191
15
1.208
40
V
mV
nA
UV
UV Threshold Hysteresis
UV Leakage Current
UVOUT Leakage Current
UV(HYST)
UV(LK)
I
I
UV = 1.2V
1
50
UV = 2V, UVOUT = 1.2V
(C-Grade, I-Grade)
(H-Grade)
UVOUT(LK)
l
l
1
1
50
200
nA
nA
l
l
R
UVOUT Output Low Resistance
I = 2mA
140
50
500
300
Ω
UVOUT#
t
UV
Under Voltage Detect to UVOUT Assert Low UV = Step 1.25V to 1.1V
10
µs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of
device pins are negative. All voltages are referenced to GND unless
otherwise specified.
Note 4: When testing the single MOSFET configuration, IN is connected to
SOURCE. When testing the back-to-back MOSFET configuration, SOURCE
is left unconnected.
Note 5: SOURCE ≤ –1.8V triggers a 130mA pull-down current from GATE
to SOURCE. An internal clamp limits the GATE pin to a minimum of 28V
below GND. Driving SOURCE to voltages beyond the clamp may damage
the device.
Note 3: An internal clamp limits the GATE pin to a minimum of 10V above
SOURCE or 100V above GND. A second internal clamp limits the GATE pin
to a minimum of 28V below GND. Driving this pin to voltages beyond the
clamp may damage the device.
Rev. 0
4
For more information www.analog.com
LTC4372/LTC4373
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C. IN = SOURCE = 12V, SHDN = 0V,
UV = 2V unless otherwise noted.
Total Supply Current
Total Supply Current vs
Temperature
Total Supply Current vs VIN
vs Load Current
ꢀ.0
ꢀ.ꢀ
ꢀ.0
ꢀ.ꢁ
ꢀ.0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ0
ꢀꢁꢂꢃ ꢄ ꢅꢆꢇꢈ0ꢉꢀꢊ0ꢀꢋꢌ
ꢀꢁꢂꢃ ꢄ ꢅꢆꢇꢈ0ꢉꢀꢊ0ꢀꢋꢌ
ꢀꢁꢂꢃ ꢄ ꢅꢆꢇꢈ0ꢉꢀꢊ0ꢀꢋꢌ
ꢀ
ꢀ ꢁ0ꢂꢃ
ꢀ
ꢀ ꢁ0ꢂꢃꢄ ꢅ
ꢀ ꢁ0.ꢂꢃꢄ
ꢀꢁ00ꢂꢃ
ꢀꢁꢂꢃ
ꢀ
ꢀ ꢁ0ꢂꢃꢄ ꢅ
ꢀ ꢁ0ꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀ
ꢀ ꢁ0.ꢂꢃꢄ
ꢀ
ꢀ
ꢀ ꢁ0.ꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀ0
ꢀ0
ꢀ0
0
0
ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0
ꢀꢁꢂ
ꢀꢁ
ꢀ0ꢁ ꢀ00ꢁ ꢀꢁ ꢀ0ꢁ ꢀ00ꢁ
ꢀꢁꢂ
ꢀ
ꢀ0
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀ
ꢀ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢁ ꢄ0ꢅ
ꢀꢁꢂꢃꢁ ꢄ0ꢃ
ꢀꢁꢂꢃꢁ ꢄ0ꢁ
Total Supply Current
vs GATE Leakage
Total Supply Current (Shutdown)
vs VIN
Total Supply Current (Shutdown)
vs Temperature
0.ꢀ0
0.ꢀꢀ
0.ꢀ0
0.ꢀꢁ
0.ꢀ0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
ꢀꢁ
ꢀ00
ꢀ0
ꢀꢁꢂꢃ ꢄ ꢅꢆꢇ ꢈꢆ ꢄ 0ꢆ
ꢉꢊꢋꢌꢍꢎꢏꢍꢉꢊꢋꢌ ꢐꢏꢀꢑꢒꢎꢓ
ꢀꢁꢂꢃ ꢄ ꢅꢆꢇ ꢈꢆ ꢄ 0ꢆ
ꢉꢊꢋꢌꢍꢎꢏꢍꢉꢊꢋꢌ ꢐꢏꢀꢑꢒꢎꢓ
ꢀ
0
ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0
ꢀꢁꢂ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
0.0ꢀ
0.ꢀ
ꢀ
ꢀ0
ꢀ00
ꢀ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂꢃꢁ ꢄ0ꢅ
ꢀꢁꢂꢃꢁ ꢄ0ꢅ
ꢀꢁꢂꢃꢁ ꢄꢀ
IN Current
SOURCE Current
OUT Current
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀꢁ
ꢀ0
ꢀ
ꢀ.0
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.0
0.ꢀ
0
ꢀꢁ ꢂ ꢃꢄꢅRꢆꢇ
ꢀꢁ ꢂ ꢃꢄꢅRꢆꢇ
ꢀꢁꢂ ꢃ ꢄꢅꢆ
ꢀꢁꢂ ꢃ ꢄꢅꢆ
ꢀꢁꢂ ꢃ ꢄꢅꢆ
ꢀꢁ ꢂ ꢃꢄꢅRꢆꢇ ꢂ ꢈꢉꢊ
ꢀꢁꢂ ꢃ ꢄꢅꢆ
ꢀꢁ ꢂ ꢃꢄꢅRꢆꢇ ꢂ ꢈꢉꢊ
ꢀ
ꢀ
ꢀ
ꢀ0.ꢁ
ꢀꢁ.0
0
0
ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0
ꢀꢁꢂ
0
ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0
ꢀꢁꢂ
0
ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0
ꢀꢁꢂ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢂRꢃꢄ
ꢀꢁꢂꢃꢁ ꢄ0ꢂ
ꢀꢁꢂꢃꢁ ꢄ0ꢅ
ꢀꢁꢂꢃꢁ ꢄ0ꢅ
Rev. 0
5
For more information www.analog.com
LTC4372/LTC4373
TA = 25°C. IN = SOURCE = 12V, SHDN = 0V,
OUT Current at Negative Input
TYPICAL PERFORMANCE CHARACTERISTICS
UV = 2V unless otherwise noted.
Pin Current at Shutdown
Pin Current at Negative Input
ꢀꢁ000
ꢀꢁ00
ꢀꢁ00
ꢀꢁ00
ꢀꢁ00
0
ꢀ00
ꢀ0
ꢀ
ꢀꢁ ꢂ ꢃꢄꢅRꢆꢇ
ꢀꢁ ꢂ ꢃꢄꢅRꢆꢇꢈ ꢄꢅꢉ ꢂ ꢊ0ꢋ
ꢀ
ꢀꢁꢂRꢃꢄ
ꢀꢁꢂ ꢃ ꢄ0ꢅ
ꢀꢁ0
ꢀ
ꢀꢁ
ꢀ
ꢀꢁ
ꢀ00
ꢀꢁ0
ꢀ00
ꢀ0
0.ꢀ
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂRꢃꢄ
0.0ꢀ
0.00ꢀ
ꢀꢁꢂꢃ ꢄ ꢅꢆꢇꢈꢆ ꢄ 0ꢆ
0
0
ꢀꢁ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁ0
0
ꢀꢁ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁ0
0
ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆ ꢇꢀꢈ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂꢃꢁ ꢄꢅꢅ
ꢀꢁꢂꢃꢁ ꢄꢅꢃ
ꢀꢁꢂꢃꢁ ꢄꢅ0
GATE Current
vs Forward Voltage Drop
∆VGATE (Average)
vs GATE Leakage
GATE Turn-Off Time
vs GATE Capacitance
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀ
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁ
ꢀ000
ꢀꢁ0
ꢀ00
ꢀꢁ0
0
ꢀꢁ ꢂ ꢃꢄꢅRꢆꢇ ꢂ ꢈꢉꢊ
ꢀꢁ ꢂ ꢃꢄꢅRꢆꢇ ꢂ ꢈꢉꢊ
∆V ꢀ ꢁ0ꢂꢃ ꢄꢅꢆꢇ ꢅꢈ ꢉ0.ꢊꢃ
ꢀꢁ
ꢀꢁꢂꢃ ꢄ ꢅꢆꢇRꢈꢃ ꢉ ꢊꢋ
ꢀꢁ ꢂ ꢃꢄꢅRꢆꢇ ꢂ ꢈꢉ
∆V ꢀꢁꢂꢀ ꢃꢄ ꢅꢄꢆ
ꢀꢁ
ꢀꢁ ꢂ ꢃꢄꢅRꢆꢇ ꢂ ꢈ.ꢉꢊ
ꢀ
ꢀ
0
ꢀ
∆V ꢀꢁꢂ ꢃꢁ ꢄꢅꢆꢄ
ꢀꢁ
0
ꢀ
0
ꢀꢁ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁ
0
ꢀ
ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0
0
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃ
ꢀ
ꢀ0
ꢀ
∆V ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢁ ꢄꢅꢀ
ꢀꢁꢂꢃꢁ ꢄꢅꢁ
ꢀꢁꢂꢃꢁ ꢄꢅꢆ
GATE Turn-Off Time
vs Forward Overdrive
UV Threshold
vs Temperature
Load Current vs VFWD
ꢀ
ꢀ
ꢀ
0
ꢀ.ꢁꢁ
ꢀ.ꢁꢀ
ꢀ.ꢁ0
ꢀ.ꢀꢁ
ꢀ.ꢀꢁ
ꢀ0
ꢀ
∆V = 50mV STEP TO FINAL ∆V
ꢀꢁꢂꢃꢄꢅꢆ0ꢆ
ꢀꢁꢂꢃꢄ0ꢅꢆꢇ
ꢀꢁ
SD
ꢀ
ꢀꢁꢂ ꢃꢁ ꢄꢅꢆꢄ
ꢀꢁ
ꢀ
ꢀꢁꢂꢃ0ꢄꢅꢆ0ꢅꢇꢈ
ꢀ
ꢀ
ꢀꢁ
ꢀꢁꢂꢀ ꢃꢄ ꢅꢄꢆ
ꢀ
0
0
ꢀ0.ꢁ
ꢀ0.ꢁ
ꢀ0.ꢁ
ꢀ0.ꢁ
ꢀꢁ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ00
FINAL ∆V ꢀꢁꢂ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
∆V ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂꢃꢁ ꢄꢅꢆ
ꢀꢁꢂꢃꢁ ꢄꢅꢂ
ꢀꢁꢂꢃꢁ ꢄꢅꢆ
Rev. 0
6
For more information www.analog.com
LTC4372/LTC4373
PIN FUNCTIONS
Exposed Pad (DD Package Only) : Exposed pad may be
left open or connected to device ground.
gate for forward voltage regulation and reverse current
turn-off. OUT is used as the supply to hold the MOSFET
off when IN is not available (below UVLO). Connect a 10µF
or larger capacitor to this pin.
GATE: MOSFET Gate Drive Output. The LTC4372/LTC4373
control the gate of the MOSFET to maintain the voltage
drop between 0mV to 30mV using a pulsed control
method. If reverse current flows, a fast pull-down cir-
cuit connects GATE to SOURCE within 0.5μs, turning off
the MOSFET.
SHDN (LTC4372): Shutdown Control Input. The LTC4372
can be shut down to a low current mode by pulling SHDN
above 1.215V. Connect to GND if unused.
SOURCE: MOSFET Source Connection. SOURCE is the
return path of the GATE fast pull-down. Connect this
pin as close as possible to the source of the external
N-channel MOSFET.
GND: Device Ground.
IN: Voltage Sense and Supply Voltage. IN is the anode of
the ideal diode. The voltage sensed at this pin is used to
control the MOSFET gate for forward voltage regulation
and reverse current turn-off. The positive supply input
ranges from 2.5V to 80V for normal operation. It can go
below GND by up to 28V during a reverse battery condi-
tion without damaging the part.
2UPU (LTC4372): 2μA Pull-Up Output. This pin has a
2μA pull-up to INTV . It can be connected to SHDN to
CC
facilitate on/off control of the LTC4372 by a microcontrol-
ler’s open-drain output. If unused, leave open or connect
to INTV .
CC
INTV : Internal 3V Supply Decoupling Output. Connect
UVOUT (LTC4373): UV Status Output. Open Drain output
that pulls low when UV goes below 1.191V (VUV) and goes
high impedance when UV exceeds 1.191V. UVOUT can be
used to adjust hysteresis for the UV monitor. This pin may
be left open or connected to GND if unused.
CC
a 0.1μF or larger capacitor to this pin. An external load of
less than 10µA can be connected at this pin.
OUT: MOSFET Drain Voltage Sense. OUT is the cathode
of the ideal diode and the common output when multiple
LTC4372/LTC4373’s are configured as an ideal diode-OR.
It connects to the drain of the N-channel MOSFET. The
voltage sensed at this pin is used to control the MOSFET
UV (LTC4373): Undervoltage Detection Input. The
LTC4373 goes into a low current shutdown mode when
UV is below 1.191V. Connect to INTV if unused.
CC
Rev. 0
7
For more information www.analog.com
LTC4372/LTC4373
BLOCK DIAGRAM
ꢀꢁ
ꢀꢁꢂRꢃꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂ
LTC4372
ꢀꢀ.ꢁꢂ
ꢀꢁꢂ
ꢁ
ꢀꢁꢂRꢃꢄ
ꢅꢆꢇꢅ
ꢈ ꢉ ꢊꢇꢁꢋ
ꢀꢁꢂꢃꢄꢅꢆꢁ
ꢀꢁꢂꢃ
ꢀꢁ.ꢂꢃ
ꢀ
ꢀꢁ
ꢀꢁꢂꢃꢄ
ꢅRꢅꢃꢆꢇ
RꢀꢁꢀRꢂꢀ
ꢀꢁRRꢂꢃꢄ
ꢈꢉꢃꢅ ꢊRꢆꢋꢅR
ꢀ
ꢀ
ꢁ
ꢀ0ꢁꢂ
ꢀ0ꢁꢂ
ꢁ
ꢀꢁꢂꢃ
ꢄꢄ
ꢀꢁꢂꢃ
ꢄꢄ
RꢀꢁꢂꢃꢄꢅꢆR
2μA
ꢀꢁꢂꢁ
ꢀꢁꢂꢃ
ꢄꢅꢆꢇ
ꢀꢁꢂꢃ
ꢀ
ꢁ
ꢀ.ꢁꢂ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢂRꢃꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂ
LTC4373
ꢀꢀ.ꢁꢂ
ꢁ
ꢀꢁꢂRꢃꢄ
ꢅꢆꢇꢅ
ꢈ ꢉ ꢊꢇꢁꢋ
ꢀꢁꢂꢃꢄꢅꢆꢁ
ꢀꢁꢂꢃ
ꢀꢁ.ꢂꢃ
ꢀ
ꢀꢁ
ꢀꢁꢂꢃꢄ
ꢅRꢅꢃꢆꢇ
RꢀꢁꢀRꢂꢀ
ꢀꢁRRꢂꢃꢄ
ꢈꢉꢃꢅ ꢊRꢆꢋꢅR
ꢀ
ꢀ
ꢁ
ꢀ0ꢁꢂ
ꢀ0ꢁꢂ
ꢁ
ꢀꢁꢂꢃ
ꢄꢄ
ꢀꢁꢂꢃ
ꢄꢄ
RꢀꢁꢂꢃꢄꢅꢆR
ꢀꢁ
ꢂꢃꢄꢅ
ꢀ.ꢀꢁꢀꢂ
ꢀ
ꢁ
ꢀꢁ
UVOUT
ꢀ.ꢀꢁꢀꢂ
ꢀ
ꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂꢃꢁ ꢄꢅ
Rev. 0
8
For more information www.analog.com
LTC4372/LTC4373
OPERATION
Blocking diodes are commonly placed in series with sup-
ply inputs for ORing redundant supplies and protecting
against supply reversal. The LTC4372/LTC4373 replace
the diodes such as in portable equipment and automo-
tive applications with N-channel MOSFETs acting as ideal
diodes. The forward voltage drop reduces as shown in
Figure 1, a feature that is readily appreciated at low input
voltages where headroom is tight.
The source of the external MOSFET is connected to IN
and SOURCE while its drain is connected to OUT. The
LTC4372/LTC4373 control the gate of the MOSFET to
regulate the voltage drop across the pass transistor to
less than 30mV.
In the event of a rapid drop in input voltage, such as an
input short-circuit fault or negative-going voltage spike,
reverse current temporarily flows through the MOSFET.
This current is provided by any load capacitance and
by other supplies or batteries that feed the output in
diode-OR applications. The reverse current comparator
quickly responds to this condition by turning the MOSFET
off in 500ns. This fast turn-off prevents the reverse cur-
rent from ramping up to a damaging level, thus minimiz-
ing the disturbance to the output bus.
ꢎ0
ꢉꢁꢊꢋꢆꢃ
ꢚꢒ
ꢇꢌꢊꢍ0ꢎꢏꢐ0ꢑꢐꢊꢒꢈ
ꢚ0
ꢊꢍꢓꢁꢃꢃꢔꢕ ꢖꢗꢁꢖꢆ
ꢒ
ꢇꢊꢌꢅꢎ0ꢘ0ꢍꢃꢈ
IN, SOURCE and GATE are protected against reverse
inputs of up to –28V. The negative comparator detects
negative input potentials at SOURCE and quickly connects
GATE to SOURCE, turning off the MOSFET and isolating
the load from the negative input.
0
0.0
0.ꢚ
0.ꢎ
0.ꢛ
0.ꢘ
0.ꢒ
ꢀꢁꢂꢃꢄꢅꢆ ꢇꢀꢈ
ꢘꢛꢜꢎꢛ ꢋ0ꢚ
Figure 1. Forward Voltage Drop Comparison Between MOSFET
and Schottky Diode
For the LTC4372, driving SHDN high pulls the MOSFET
gate down to SOURCE with a 1mA pull-down. I reduces
Q
to 0.5μA for a back-to-back MOSFET configuration and
GATE is held low with a 3μA pull-down to GND. When
SHDN goes low, the LTC4372 ramps GATE up to turn on
As a result of this lower forward voltage drop, there is a
dramatic reduction in power loss achieved in a practical
application as shown in the Typical Application curve on
Page 1. This represents significant savings in board area
by greatly reducing heat sinking requirements of the pass
device. In addition to these two desirable properties, the
LTC4372/LTC4373 feature a low operating current (5µA)
and shutdown current (0.5µA). This increases efficiency
in applications where the ideal diode is used for intermit-
tent loads or always on standby channels, making the
LTC4372/LTC4373 suitable for battery powered appli-
cations in the portable instrumentation, automotive and
renewable energy fields.
the external MOSFET. 2UPU has a 2μA pull-up to INTV
CC
which can be connected to SHDN to facilitate on/off con-
trol by a microcontroller’s open-drain output.
The LTC4373 can monitor the input voltage via an exter-
nal resistive voltage divider to UV. When UV goes below
1.191V, GATE pulls down to SOURCE with a 1mA pull-
down and UVOUT pulls low. I reduces to 0.5μA for a
Q
back-to-back MOSFET configuration and GATE is held low
with a 3μA pull down to GND. When UV recovers above
V
+ V
, the LTC4373 ramps GATE up to turn on
UV
UV(HYST)
the external MOSFET. An optional resistor can be con-
nected between UV and UVOUT to configure an external
hysteresis to override V
.
UV(HYST)
Rev. 0
9
For more information www.analog.com
LTC4372/LTC4373
APPLICATIONS INFORMATION
The LTC4372/LTC4373 operate from 2.5V to 80V and
withstands an absolute maximum range of –28V to 100V
without damage. In automotive applications the LTC4372/
LTC4373 can operate through load dump, cold crank and
two-battery jump starts, and survive reverse battery con-
nections while protecting the load.
Figure 5 shows a typical OUT ripple at an I
the circuit shown in Figure 2.
of 16A for
LOAD
IN
ꢀꢁꢂ
ꢀꢁꢂ ꢃꢄꢅ
ꢆ0ꢇꢈꢉꢊꢀꢈ
OUT
A 12V/20A ideal diode application is shown in Figure 2.
The following sections cover power-on, ideal diode oper-
ation, shutdown and various faults that the LTC4372/
LTC4373 detect and act upon.
ꢀꢁꢂ ꢃꢄꢅꢆ
GATE
ꢇꢈꢉꢊꢀꢈ
ꢀꢁꢂ
IN
43723 F03
50ms/DIV
ꢀꢁ
ꢀ
ꢉ ꢊ00ꢋꢂ
ꢁꢂꢃꢄꢅꢆꢄꢂꢇꢂꢁꢄꢈ
ꢂꢃꢄ0ꢅꢆꢇ0ꢈꢇꢃꢉ
ꢀ
ꢁꢂ
ꢀ
ꢁꢂꢃ
ꢀ ꢁꢂꢃ
ꢄꢅꢀ
ꢅ0ꢆ
Figure 3. Regulating ∆VSD at
Low ILOAD = 1µA
ꢀꢁ
ꢀꢁꢂRꢃꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂ
C
10μF
OUT
ꢀꢁꢂꢁ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢄꢄ
IN
ꢀꢁꢂꢃꢁ ꢄ0ꢅ
ꢀꢁꢂ
ꢀꢁ
ꢁ00ꢂꢃ
ꢀꢁꢂ ꢃꢄꢅ
ꢆ0ꢇꢈꢉꢊꢀꢈ
OUT
Figure 2. 12V/20A Ideal Diode with Reverse Input Protection
GATE
ꢀꢁꢂ ꢃꢄꢅꢆ
ꢇꢈꢉꢊꢀꢈ
Power-On and Ideal Diode Operation
ꢀꢁꢂ
IN
43723 F04
When power is applied, the initial load current flows
through the body diode of the MOSFET M1. When IN
exceeds the UVLO level of 2.1V and SHDN is low or UV is
high, the LTC4372/LTC4373 begin operation. An internal
charge pump asserts a 20µA pull-up on GATE to enhance
the MOSFET. To achieve a low supply current, the LTC4372/
LTC4373 employ a pulsed control style of operation where
the internal charge pump is not always on. Instead, the
charge pump periodically wakes up to recharge GATE after
it droops from leakage to keep ∆VSD ≤ 30mV. This pulsed
control creates a voltage ripple at OUT even with a stable
DC load. The amplitude of this ripple is dependent on gate
leakage, GATE capacitance, the load condition and the size
of the bypass capacitance at OUT. At low load or no-load
condition, this ripple can increase to 30mVPK–PK. Figure 3
5ms/DIV
ꢀ
ꢉ ꢊ00ꢋꢂ
ꢁꢂꢃꢄꢅꢆꢄꢂꢇꢂꢁꢄꢈ
Figure 4. Regulating ∆VSD at
Moderate ILOAD = 2A
IN
ꢀꢁꢂ
ꢀꢁꢂ ꢃꢄꢅ
ꢆ0ꢇꢈꢉꢊꢀꢈ
OUT
GATE
ꢀꢁꢂ ꢃꢄꢅꢆ
ꢇꢈꢉꢊꢀꢈ
ꢀꢁꢂ
IN
43723 F05
10ms/DIV
ꢀ
ꢉ ꢊ00ꢋꢂ
ꢁꢂꢃꢄꢅꢆꢄꢂꢇꢂꢁꢄꢈ
shows a typical OUT ripple at an ultralight I
for the circuit shown in Figure 2.
of 1µA
LOAD
Figure 5. Regulating ∆VGATE at
High ILOAD = 16A
With a moderate DC load, the ripple amplitude is about
10mVpk-pk. Figure 4 shows a typical OUT ripple at a mod-
erate I
of 2A for the circuit shown in Figure 2.
LOAD
Rev. 0
10
For more information www.analog.com
LTC4372/LTC4373
APPLICATIONS INFORMATION
Gate drive is compatible with 4.5V logic-level MOSFETs
over the entire operating range of 2.5V to 80V. In applica-
tions with supply voltages above 5V, standard 10V thresh-
old MOSFETs may be used. An internal clamp limits the
gate drive to 16V maximum between GATE and SOURCE.
As the load current increases, GATE is driven higher and
higher until a point is reached where ∆V
reaches
GATE
the maximum overdrive that the internal charge pump is
capable of (∆V ) but ∆V is still above 30mV. In
GATE(H)
SD
this situation, the internal charge pump will periodically
turn on to recharge GATE as needed to keep ∆V
GATE
The maximum allowable drain-source voltage, BVDSS
,
between ∆V
and ∆V
– 0.7V. ∆V is then
GATE(H)
GATE(H) SD
. There is now insignificant
must be higher than the power supply voltage. If the input
is grounded, the full supply voltage will appear across the
MOSFET. If a reverse battery is possible and the output
is held up by a charged capacitor, battery or power sup-
ply, then the sum of the input and output voltages will
equal to R
• I
DS(ON) LOAD
ripple on OUT as the 0.7Vpk-pk ripple on ∆V
has
GATE
little effect on the MOSFET R .
ON
Achieving Low Average I
Q
appear across the MOSFET and BV
must be higher
DSS
To lower average IQ in diode control mode when GATE
is high, the LTC4372/LTC4373 operate by turning on
the charge pump periodically. When in charge pump
than V +|V |.
OUT
IN
The MOSFET’s on-resistance, RDS(ON), directly affects
the forward voltage drop and power dissipation during a
sleep mode, the I is 3.5μA. Once the charge pump is
Q
heavy load. Desired forward voltage drop (V ) should
FWD
turned on to deliver a current pulse to GATE, I goes up
Q
be less than that of a diode for reduced power dissipa-
tion; 50mV is a good starting point. Since the LTC4372/
LTC4373 drop at least 30mV across the MOSFET, a very
low RDS(ON) may be wasted. Choose a MOSFET using
Equation 2.
to 300μA. The average I will depend on how often the
Q
charge pump is turned on and this is affected by GATE
leakage, GATE capacitance, OUT bypass capacitance and
ILOAD. To achieve the lowest possible average IQ, mini-
mize GATE leakage and ensure that GATE has a moderate
V
ILOAD
capacitance (>1nF). If the C of the MOSFET does not
FWD
GS
RDS(ON)
<
(2)
already exceed this, add a 1nF capacitor between GATE
and SOURCE. C
may be placed nearer to the load but
an OUT bypass LcOaApDacitance of at least 10μF low ESR and
ESL electrolytic or ceramic is required close to the drain
The resulting power dissipation is shown in Equation 3.
2
P = I
d
• R
DS(ON)
(3)
LOAD
pin of MOSFET M1 (see Figure 6a). Average I for Diode
Control mode can be estimated by Equation 1.
Q
Input Short-Circuit Faults
IGATE(LEAKAGE)
Input short-circuits that cause reverse current to flow can
occur in many ways. Some examples include PCB traces
getting accidentally shorted or bypass capacitors in the
upstream power supply failing shorted. The LTC4372/
LTC4373 utilize the external MOSFETs to add rugged input
short-circuit protection without utilizing large TVS clamps
or capacitors.
(1)
AVERAGEIQ = 3.5+
• 300µA
IGATE(UP)
The Typical Performance Characteristics section shows
relationship of I with I
and I
.
Q
GATE(LEAKAGE)
LOAD
MOSFET Selection
The LTC4372/LTC4373 drive N-channel MOSFETs to
conduct the load current. The important character-
istics of the MOSFET are the gate threshold voltage
Figure 6a models a low impedance input short with a
switch. When the short-circuit switch closes, reverse cur-
rent builds up in L , L
and M1 in the direction shown.
IN OUT
V
, the maximum drain-source voltage BV
and
GS(TH)
on-resistance R
DSS
The LTC4372/LTC4373 detect the reverse current quickly
and activate the internal 130mA GATE to SOURCE pull-
down current to turn M1 off. The reverse current build up
.
DS(ON)
Rev. 0
11
For more information www.analog.com
LTC4372/LTC4373
APPLICATIONS INFORMATION
RꢀꢁꢀRꢂꢀ ꢃꢄRRꢀꢅꢆ
ꢀ
ꢀ
ꢀ
ꢁꢂꢃ
ꢁ
ꢁꢂ
ꢁꢂꢃRꢄꢅ
ꢆꢇRꢇꢁꢈꢉꢈꢄ
ꢈꢊꢋꢃꢄꢉꢇꢊꢄꢅ
ꢁꢂꢃꢄꢅ
ꢃꢆRꢆꢇꢁꢅꢁꢈ
ꢁꢂꢉꢄꢈꢅꢆꢂꢈꢊ
ꢁꢂꢃꢄꢂꢃ
ꢄꢅRꢅꢆꢇꢃꢇꢈ
ꢇꢉꢊꢂꢈꢃꢅꢉꢈꢋ
GATE
ꢀꢁ
ꢀꢁꢂꢃꢄ ꢅꢆ
ꢀꢆꢇ
ꢈ0ꢉꢊꢇꢅꢉ
ꢂꢃꢄ0ꢅꢆꢇ0ꢈꢇꢃꢉ
IN
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢁꢂ
ꢀ
ꢁꢂꢃ
GND
0ꢀ
ꢀꢁ
ꢀ
ꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢅꢆꢇRꢄ
ꢂꢃꢄꢅꢆꢆꢄ
ꢇꢈꢉꢊꢋꢈꢌꢄꢍꢎ
ꢀꢁ ꢀꢁꢂRꢃꢄ ꢀꢁꢂꢃ ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢅ0ꢆꢇꢈꢀꢉ
0ꢀ
C
10μF
OUT
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂꢃꢁ ꢄ0ꢅꢆ
ꢂꢃꢁꢂꢁꢄꢅ
ꢆꢇꢈR ꢉ ꢋ ꢂꢌ.ꢍꢉꢎ
ꢊꢃ
43723 F06b
R
500ns/DIV
ꢀꢁꢂ
C
= 10μF
OUT
(b)
(a)
Figure 6. Reverse Recovery Produces Inductive Spikes at IN, SOURCE and OUT. The Polarity of
Inductive Spike is Shown Across Parasitic Inductances
in L and L
is interrupted and this causes IN to spike
power supply with a large source impedance. V col-
IN
OUT
IN
negative and OUT to spike positive. At OUT, C
clamps
lapses during the short-circuit and cannot build up cur-
OUT
the positive going spike caused by L
and commutates
rent in L . SOURCE will not see fast slew rates when the
I(LOUT) to zero. At IN, the internal OGUNTD – GATE clamp
asserts and holds GATE to 32V below GND, this causes M1
to turn back on as IN/SOURCE undershoots below GATE.
The current in LIN is diverted by M1 to COUT and safely
commutates to zero as shown in the short-circuit transient
of Figure 6b. If these transients cause too large of a ∆V at
short-circuit goes away.
S
Using the external MOSFETs to commutate the parasitic
inductor currents during an input short-circuit is feasible
with input voltages up to 33V. This ensures that during
the transient, the IN – OUT Absolute Maximum Voltage of
100V is not exceeded. During the short-circuit transient,
OUT, increase the capacitance of C
or add a TVS D1.
OUT
the MOSFET VDS sees |VGND|+|VGATE(NEG)|+VTH(M1)+VOUT
.
If a low source resistance power supply drives V , large
currents can build up in LS during the shortI-Ncircuit.
Choose the MOSFET BV
accordingly. For other tech-
niques to protect the LDTSCS4372/LTC4373 during input
short-circuits see the Design Examples section.
When the short-circuit goes away, I(L ) can cause IN and
S
SOURCE to spike positive until it is held by M1 body diode
Reverse Input Protection
to C . This fast slew rate at SOURCE can cause a large
OUT
shoot-through current to flow into the part from SOURCE
to GND potentially causing damage. Adding an external
GND
Negative voltages at IN can also occur if a battery
is plugged in backwards or a negative supply is inadver-
tently connected. Figure 7 shows the waveforms when the
application circuit in Figure 2 is hot plugged to –24V. Due
to the parasitic inductance in between input and IN/
SOURCE, the voltages at the pins can ring significantly
below –24V. Similar to the input short-circuit situation,
the GND – GATE clamp causes M1 to divert the current
in the parasitic inductances to COUT. The GND – GATE
clamp limits the maximum DC negative voltage that the
Figure 2 application can handle to –28V.
R
will limit this current to a safe level.
For applications where IN ≤ 13.2V, a 0805 size 100Ω for
is sufficient. For applications where IN > 13.2V, a
R
GND
larger value R , 1k, is necessary. To keep GND from
going too negGatNiDve when the GND – GATE clamp turns
on, a fast recovery diode like the 1N4148W is placed in
parallel with the 1k R
.
GND
For back-to-back MOSFET applications where SOURCE
is not driven by V , R
is not needed. R
can also
IN GND
GND
be omitted for a single MOSFET application driven by a
Rev. 0
12
For more information www.analog.com
LTC4372/LTC4373
APPLICATIONS INFORMATION
ꢀꢁꢂꢃꢄ
ꢅꢆꢇꢈꢀꢉ
ꢀꢁꢂ
ꢀꢁꢄ
ꢅꢇ
ꢀꢁꢂꢃ ꢀꢁꢄ
ꢅ0ꢆꢇꢈꢉꢀꢇ
ꢀꢁꢂRꢃꢄ
ꢅ0ꢆꢇꢈꢉꢆ
ꢀꢁꢂꢃ
ꢄ0ꢅꢆꢇꢈꢅ
ꢊꢂꢋꢌꢂ
ꢊꢂꢋꢌꢄ
ꢊꢂꢋꢌꢂꢃ
ꢊꢂꢋꢌꢄ
ꢍꢇꢈꢉꢀꢇ
ꢅꢇ
ꢀ
ꢁꢂꢃꢄꢅꢆꢇꢈRꢉꢄ
ꢊ0ꢀꢋꢌꢍꢀ
ꢀꢁꢂ
ꢃꢄꢅꢆꢇꢄ
43723 F07
1μs/DIV
(a)
Figure 7. LTC4372/LTC4373 Handling Reverse Input
ꢅꢋꢚꢑꢈꢎ
Paralleling Supplies
0.ꢀꢈꢃꢄꢅꢆ
0ꢈ
Multiple LTC4372/LTC4373’s can be used to combine the
outputs of two or more supplies for redundancy or for
droop sharing, as shown in Figure 8. For redundant sup-
plies, the supply with the highest output voltage sources
most or all of the load current. Figure 9a and Figure 9b
show the load transition between the two redundant
power supplies.
ꢅꢋꢚꢑꢐꢎ
0.ꢀꢈꢃꢄꢅꢆ
0ꢈ
ꢀꢆ
ꢛꢜꢉ
ꢀ0ꢁꢆꢃꢄꢅꢆ
ꢓꢔꢕꢖꢔ ꢗ0ꢘꢙ
ꢀ0ꢁꢂꢃꢄꢅꢆ
ꢅ
ꢏ ꢅ
ꢏꢑ00ꢒꢈ
ꢇꢈꢉꢊꢈꢋꢌꢊꢈꢍꢈꢇꢊꢎ ꢇꢈꢉꢊꢐꢋꢌꢊꢈꢍꢈꢇꢊꢎ
If the higher supply’s input is shorted to ground while
delivering load current, the flow of current temporarily
(b)
reverses and flows backwards through the higher supply’s
Figure 9. Load Transition of Redundant Power Supplies
ꢀꢁꢂ
ꢃꢄꢅꢁꢆ0ꢂꢇꢈ
ꢀꢁꢂ
MOSFET. The LTC4372/LTC4372 sense this reverse cur-
rent and activate a fast pull-down to quickly turn off the
MOSFET.
ꢀ
ꢁ
ꢀꢁꢂꢃR
ꢄꢅꢀꢀꢆꢇ
ꢈ
ꢀꢁ ꢀꢁꢂRꢃꢄ ꢀꢁꢂꢃ ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢁ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢆ
If all the load current was supplied by the channel that
suffered the short, the output will fall until the body diode
of the next MOSFET conducts. Meanwhile, the LTC4372/
LTC4372 charge the MOSFET gate with 20μA until the
forward drop is reduced to 30mV. If this supply was shar-
ing load current at the time of the fault, its associated
ORing MOSFET was already servoed to less than 30mV
drop. In this case, the LTC4372/LTC4372 will simply drive
the MOSFET gate higher to maintain a drop of 30mV at
full load.
ꢀꢁꢂꢃ ꢀꢁꢂꢃ
ꢄꢄ
ꢀ
ꢁꢂꢃ
ꢀꢁꢂ
ꢁ00ꢃꢄ
ꢄ00ꢅꢆ
R
GNDA
100Ω
ꢀꢁꢂ
ꢀꢁꢂ
ꢃꢄꢅꢁꢆ0ꢇꢈꢉ
ꢀ
ꢁ
ꢀꢁꢂꢃR
ꢄꢅꢀꢀꢆꢇ
ꢈ
ꢀꢁ ꢀꢁꢂRꢃꢄ ꢀꢁꢂꢃ ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢁ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂ
ꢀꢁꢂꢃ ꢀꢁꢂꢃ
ꢄꢄ
ꢀꢁꢂ
ꢁ00ꢃꢄ
Load sharing can be accomplished if both power sup-
ply output voltages and source impedances are nearly
equal. The 30mV regulation technique allows load sharing
between outputs. The degree of sharing is a function of
R
GNDB
100Ω
ꢀꢁꢂꢃꢁ ꢄ0ꢅ
Figure 8. Redundant Power Supplies
MOSFET R
, the source impedance of the supplies
DS(ON)
and their initial output voltages.
Rev. 0
13
For more information www.analog.com
LTC4372/LTC4373
APPLICATIONS INFORMATION
Using the LTC4372’s SHDN and 2UPU
Load Switching and Inrush Control
When SHDN goes high, the LTC4372 enters shutdown
and asserts a 1mA pull-down between GATE and SOURCE
to turn off the external MOSFET. It also turns off most of
By adding a second MOSFET as shown in Figure 10, the
LTC4372/LTC4373 can be used to control power flow in
the forward direction while retaining ideal diode behav-
ior in the reverse direction. The body diodes of M1 and
M2 prohibit current flow when the MOSFETs are off. M1
serves as the ideal diode while M2 acts as a switch to
control forward power flow. ON/OFF control is provided
by SHDN or UV. C2 and R2 may be added to further reduce
inrush current. While C2 and R2 may be omitted if soft
starting is not needed. R1 is necessary to prevent MOSFET
parasitic oscillations and must be placed close to M2.
the internal circuitry, reducing I to 0.5μA. GATE is held
IN
low with a 3μA pull-down to GND. If IN and SOURCE are
connected together, I = 3.0μA + 0.5μA = 3.5μA.
Q
Shutting down the part does not interrupt forward current
flow as a path is still present through M1’s body diode. A
second MOSFET may be added to block the forward path
(see Figure 10). In this case, GATE and SOURCE are pulled
to GND during shutdown. The 3μA pull-down on GATE is
pinched off and I = 0.5μA. With back-to-back MOSFETs,
When SHDN is driven low or UV driven high and
Q
SHDN serves as an on/off control for the forward path,
as well as enabling the diode function. When SHDN is
driven low, the LTC4372 exits shutdown and re-enters
ideal diode operation.
∆V > 30mV, GATE sources 20μA and gradually charges
DS
C2, pulling up both MOSFET gates. M2 operates as a
source follower as shown in Equation 4.
COUT
C2
IINRUSH
=
• 20µA
(4)
If SHDN is not needed, connect it to GND. SHDN may
be driven with a 3.3V or 5V logic signal. It can also be
driven with an open-drain or collector output with SHDN
tied to 2UPU. 2UPU provides an internal pull up current
If ∆V ≤ 30mV, the LTC4372/LTC4373 stay activated but
DS
holds M1 and M2 off until the input exceeds the output by
30mV. In this way normal diode behavior of the circuit is
preserved, but with soft starting when the diode turns on.
ꢀꢁ
ꢀꢁ
V
24V
10A
ꢂꢃꢄ0ꢁꢅꢆ0ꢇꢆꢃꢈ
ꢂꢃꢄ0ꢅꢆꢇ0ꢈꢇꢃꢉ
OUT
V
IN
24V
C
OUT
10µF
R2
1k
D3
SMAJ28A
28V
R1
10Ω
When SHDN is driven high or UV driven low, GATE pulls
the MOSFET gates down quickly to SOURCE with a 1mA
pull-down. Both forward and reverse paths are cut off and
C2
10nF
D2
SMAJ33A
33V
IN
SOURCE GATE
LTC4372
GND
OUT
I is reduced to 0.5μA.
Q
2UPU
SHDN
Configuring LTC4373’s UV and UVOUT for Voltage
Monitoring
INTV
CC
43723 F10
M3
BSS138N
OFF ON
C1
100nF
With back-to-back MOSFETs, the LTC4373 can imple-
ment voltage monitoring at IN. Connect a resistive voltage
divider between IN and ground to bias UV. UV has a high
to low threshold of 1.191V with 15mV of hysteresis. The
Figure 10. 24V Load Switch and Ideal Diode with Inrush Control
and Reverse Input Protection
UV hysteresis is around 1.3% referred to V .
UV
of 2μA to INTV . For higher pull-up currents, connect a
CC
When UV ramps high to low, the LTC4373 enters under-
voltage mode and asserts a 1mA pull-down between GATE
and SOURCE to turn off the external MOSFETs. It also turns
resistor from SHDN to INTV (capable of supplying up
CC
to 10μA) or IN.
off most of the internal circuitry, reducing I to 0.5μA.
Q
When UV ramps low to high, the LTC4373 exits under-
voltage mode and goes back into ideal diode operation.
Rev. 0
14
For more information www.analog.com
LTC4372/LTC4373
APPLICATIONS INFORMATION
Figure 11 demonstrates how UV can be used to monitor
IN. For the UV pin, the maximum input leakage current
is 50nA. For a maximum error of 1% due to leakage cur-
R4+R5
R5
R4+Rpa
VH2L = VUV •
rents, the resistive voltage divider current I
should be
VL2H = VUV •
RVD
Rpa
(6)
at least 100 times the sum of the leakage currents, or 5μA.
The IN Undervoltage threshold (VH2L) is used to calculate
the value of R4, R5 and Undervoltage Recovery threshold
R5 •R6
R5+R6
whereRpa = R5//R6 =
(V ) as shown in Equation 5.
L2H
As long as the external hysteresis to be implemented
exceeds 5% of VH2L, Equation 6 can disregard the default
UV hysteresis without affecting accuracy.
(5)
R4+R5
VH2L = VUV •
R5
R4+R5
With UVOUT connected to the resistive voltage divider,
the leakage current error needs to be re-visited. For the
UVOUT pin, the maximum input leakage current below
85°C is 50nA. While IN ramps high to low, the resistive
voltage divider sees the leakage currents from both UV
and UVOUT. This gives a total of 100nA of leakage cur-
rents. With 5μA through R4 and R5, this will add 2%
V
= VUV + V
(
•
)
L2H
UV(HYST)
R5
For applications that require a higher and more accurate
hysteresis, UVOUT can be used to program an external
hysteresis to override the default hysteresis. Comparator
C1 in the Block Diagram controls an internal 140Ω switch
pulling down on UVOUT. When UV ramps below 1.191V
inaccuracy to V . While IN ramps low to high, UVOUT
H2L
ꢐ
ꢋꢌ
is pulled low. The resistive voltage divider sees only the
ꢀ
ꢁ0ꢒꢃ
ꢈꢑꢊ
50nA of leakage current from UV. With 5μA through R4
and R5, this will add 1% inaccuracy to V . To lower the
L2H
Rꢄ
Rꢅ
leakage current error, increase I
.
RVD
ꢋꢌ
ꢓꢈꢑRꢀꢔ
ꢗꢍꢊꢔ
ꢈꢑꢊ
Layout Considerations
ꢑꢐ
ꢎꢊꢀꢅꢕꢖꢕ
Rꢆ
Connect IN, SOURCE and OUT as close as possible to
the MOSFET source and drain pins. Keep the drain and
source traces to the MOSFET wide and short to mini-
ꢇꢈꢉꢊꢋꢈꢌꢍꢎꢏ
ꢋꢌꢊꢐ
UVOUT
ꢀꢀ
ꢀꢁꢂ
ꢅꢕꢖꢘꢕ ꢃꢁꢁ
ꢀꢁ
ꢁ00ꢂꢃ
mize resistive losses as shown in Figure 12. Place C
OUT
close to the drain pin of MOSFET and keep the trace from
LTC4372/LTC4373 GATE pin to MOSFET gate short and
thin to minimize parasitic inductance and capacitance.
This practice will reduce the chance of MOSFET parasitic
oscillations. Place any surge suppressors and necessary
transient protection components close to the LTC4372/
LTC4373 using short lead lengths.
Figure 11. Configuration for Monitoring IN
and trips C1, the switch pulls UVOUT low. When UV ramps
above 1.191V and un-trips C1, the switch turns off and
UVOUT goes high impedance. By connecting R6 between
For the DFN package, pin spacing may be a concern at
voltages greater than 30V. Check creepage and clearance
guidelines to determine if this is an issue. To increase the
effective pin spacing between high voltage and ground
pins, leave the exposed pad connection open. Use
no-clean flux to minimize PCB contamination.
UV and UVOUT, R4 and R5 implements V
and V
.
H2L
L2H
Obtain R4 and R5 from Equation 5 and calculate R6 using
Equation 6.
Rev. 0
15
For more information www.analog.com
LTC4372/LTC4373
APPLICATIONS INFORMATION
and ground to clamp IN and SOURCE when they spike neg-
ative. During the input short-circuit transient, D2 diverts the
reverse recovery current in the input parasitic inductances
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢀꢀ
ꢀꢀ
ꢀꢀꢀꢀꢀꢀ
to ground while C
does the same for the output para-
sitic inductances. OTUhTe 100V, FDMS86101 with RDS(ON)
=
ꢀꢁꢂꢃ
ꢀꢁꢂ ꢃꢄꢅRꢆꢇ
8mΩ(max) can handle both the 5A load current as well as
the input short-circuit voltage transients.
ꢀꢀꢀ
ꢀ
ꢀꢀꢀ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢀꢁ
ꢀꢁꢂ
ꢀꢁ
ꢂꢃꢀꢄꢅꢆꢁ0ꢁ
ꢀ
ꢀ ꢁꢂꢃ
ꢁꢂ
ꢀ
ꢁꢂꢃ
ꢄꢅꢀ
ꢆꢇ
ꢀꢁ ꢀꢁꢂRꢃꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁ
ꢂꢃꢄꢅꢆ0ꢄ
ꢆ0ꢇ
C
10μF
OUT
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃ
ꢀꢁꢂꢁ
ꢀꢁꢂ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢀꢀ
ꢀꢀ
ꢀꢁꢂꢃ
ꢀ
ꢀ
ꢀ
ꢄꢄ
ꢀꢀꢀꢀꢀꢀ
ꢀꢁ
ꢁ00ꢂꢃ
R
ꢀꢁꢂ
ꢃꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢁ ꢄꢅꢁ
ꢀꢁꢂ
ꢀꢁꢂ ꢃꢄꢅRꢆꢇ
ꢀ
ꢀꢀꢀ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂ
ꢀꢁꢂ
Figure 13. 48V Ideal Diode without Reverse Input Protection
ꢀꢁꢂꢃꢁ ꢄꢅꢃ
Figure 14 shows a high voltage application with reverse
battery protection. To handle a potential worst-case
situation of –48V at the input side and 48V at the out-
put side, the BVDSS of the external MOSFET must be
greater than 48V + 48V = 96V with allowance. Choose
the 200V, IPB107N20N3G in the TO-263 package with
Figure 12. Layout, MS8 and DD8 Package
Design Examples
The following design example demonstrates the consid-
erations involved in selecting components for a 12V sys-
tem with 20A maximum load current (see Figure 2). First,
choose the N-channel MOSFET. The 80V BSC026N08NS5
R
= 10.7mΩ(max).
DS(ON)
When IN is –48V and OUTPUT is 48V, D3 breaks down
and clamps IN – GND at about –6V. The MOSFET is held
off and isolates the load from the negative input. D1 and
R7 clamps OUT – GND to about 70V. The combination of
D1, D2, D3 and R7 clamps IN – OUT to about 76V.
with R
= 2.6mΩ(max) offers a good solution. The
DS(ON)
maximum voltage drop across is:
∆V = 20A • 2.6mΩ = 52mV
SD
The maximum power dissipation in the MOSFET is:
P = 20A • 52mV = 1.04W
During an input short-circuit, M1 drain spikes positive
and IN spikes negative. D2, D3 and D4 commutates the
reverse recovery current in the input parasitic inductances
During input short-circuit voltage transients, using the
GND – GATE clamp to hold GATE should keep IN, SOURCE,
GATE and OUT within their Absolute Maximum Ratings. If
there is a problem with SOURCE to GND shoot through
while C
does the same for the output parasitic induc-
OUT
tances. D1, D2, D3, D4, R7 and R8 clamp IN, SOURCE,
OUT and GND to within their Absolute Maximum Ratings.
current during input short-circuits, add a R
of 100Ω.
GND
During normal ideal diode operation with GATE high, D4,
C3 and C4 help to handle I pulsating between 300μA
Q
Figure 13 shows a high voltage application. For the 48V
system, using the GND – GATE clamp to hold GATE during
input short-circuit voltage transients can exceed IN – OUT’s
–100V absolute maximum voltage. D2 is added between IN
(charging GATE) and 3.5μA (charge pump sleep mode)
while D1, D2 and D3 draw no current.
Rev. 0
16
For more information www.analog.com
LTC4372/LTC4373
APPLICATIONS INFORMATION
ꢀꢁ
ꢀ
ꢂꢃꢄꢁ0ꢅꢆꢇ0ꢆꢈꢉ
ꢀ
ꢁꢂꢃ
ꢁꢂ
ꢀ
ꢁꢂꢃ
ꢄꢅꢀ
ꢆꢇ
ꢀꢁ
Rꢀ
ꢁꢂ
ꢂꢃꢄ
ꢀꢁ
ꢂꢃꢄꢅꢆꢄ
ꢆꢇ
ꢀꢁ ꢀꢁꢂRꢃꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁ
ꢂꢃꢄꢅꢆ0ꢄ
ꢆ0ꢇ
C
OUT
ꢀꢁꢂꢁ
ꢀꢁꢂꢃꢄꢅꢆ
10μF
ꢀꢁ
ꢂꢃꢄꢅꢆ0ꢄ
ꢆ0ꢇ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢄꢄ
ꢀꢁ
ꢁ00ꢂꢃ
R
ꢀꢁꢂ
ꢃꢄ
ꢀꢁ
ꢂ00ꢃꢄ
ꢂ00ꢅ
ꢀꢁ
ꢂꢃꢄꢅꢆ0ꢄ
ꢆ0ꢇ
Rꢀ
ꢁ0ꢂ
ꢀꢁꢂꢃꢁ ꢄꢅꢀ
Figure 14. 48V Ideal Diode with Reverse Input Protection
D5*
SMAJ60A
60V
QUIESCENT CURRENT < 22µA FOR I-GRADE TEMPERATURE
V
R
SNS
20mΩ
OUT
M1
FDMS86101
M2
IRLR2908
V
IN
12V/2A
12V
WITHSTANDS
–28V TO 60V DC
OUTPUT
CLAMPED
AT 27V
C
10µF
C
L
22µF
D1
SMAJ60A
60V
OUT
R1
10k
R3
10Ω
R
100k
DRN
R2
33Ω
C3
47nF
IN
2UPU
GND
SOURCE
LTC4372
SHDN
GATE OUT
DRN GATE SOURCE
SNS
OUT
V
CC
LTC4380-2
TMR
C2
4.7µF
ON
INTV
GND
SEL
CC
43723 F15
ꢀꢁ
ꢁ00ꢂꢃ
C
TMR
220nF
D4
1N4148W
R
ꢀꢁꢂ
ꢃꢄ
*D5 IS NEEDED TO CLAMP TRANSIENTS IN CASE INPUT SHORT-CIRCUIT OCCURS AT V > 33V
IN
Figure 15. Micropower 12V Surge Stopper with Ideal Diode
Rev. 0
17
For more information www.analog.com
LTC4372/LTC4373
PACKAGE DESCRIPTION
DD Package
8-Lead Plastic DFN (3mm × 3mm)
ꢂReꢩeꢪeꢫꢬe ꢗꢋꢓ ꢆꢎꢏ ꢭ 0ꢠꢘ0ꢧꢘꢁꢣꢚꢧ Rev ꢓꢈ
0.ꢥ0 ±0.0ꢠ
ꢀ.ꢠ ±0.0ꢠ
ꢙ.ꢁ0 ±0.0ꢠ ꢂꢙ ꢄꢅꢆꢇꢄꢈ
ꢁ.ꢣꢠ ±0.0ꢠ
ꢔꢍꢓꢕꢍꢏꢇ
ꢊꢖꢋꢗꢅꢉꢇ
0.ꢙꢠ ±0.0ꢠ
0.ꢠ0
ꢐꢄꢓ
ꢙ.ꢀꢧ ±0.0ꢠ
Rꢇꢓꢊꢑꢑꢇꢉꢆꢇꢆ ꢄꢊꢗꢆꢇR ꢔꢍꢆ ꢔꢅꢋꢓꢞ ꢍꢉꢆ ꢆꢅꢑꢇꢉꢄꢅꢊꢉꢄ
ꢍꢔꢔꢗꢢ ꢄꢊꢗꢆꢇR ꢑꢍꢄꢕ ꢋꢊ ꢍRꢇꢍꢄ ꢋꢞꢍꢋ ꢍRꢇ ꢉꢊꢋ ꢄꢊꢗꢆꢇRꢇꢆ
R ꢦ 0.ꢁꢙꢠ
0.ꢃ0 ±0.ꢁ0
ꢋꢢꢔ
ꢠ
ꢧ
ꢀ.00 ±0.ꢁ0
ꢂꢃ ꢄꢅꢆꢇꢄꢈ
ꢁ.ꢣꢠ ±0.ꢁ0
ꢂꢙ ꢄꢅꢆꢇꢄꢈ
ꢔꢅꢉ ꢁ
ꢋꢊꢔ ꢑꢍRꢕ
ꢂꢉꢊꢋꢇ ꢣꢈ
ꢂꢆꢆꢧꢈ ꢆꢜꢉ 0ꢠ0ꢚ Rꢇꢛ ꢓ
ꢃ
ꢁ
0.ꢙꢠ ±0.0ꢠ
0.ꢥꢠ ±0.0ꢠ
0.ꢙ00 Rꢇꢜ
0.ꢠ0 ꢐꢄꢓ
ꢙ.ꢀꢧ ±0.ꢁ0
ꢐꢊꢋꢋꢊꢑ ꢛꢅꢇꢎꢤꢇꢝꢔꢊꢄꢇꢆ ꢔꢍꢆ
0.00 ꢨ 0.0ꢠ
ꢉꢊꢋꢇꢌ
ꢁ. ꢆRꢍꢎꢅꢉꢏ ꢋꢊ ꢐꢇ ꢑꢍꢆꢇ ꢍ ꢒꢇꢆꢇꢓ ꢔꢍꢓꢕꢍꢏꢇ ꢊꢖꢋꢗꢅꢉꢇ ꢑ0ꢘꢙꢙꢚ ꢛꢍRꢅꢍꢋꢅꢊꢉ ꢊꢜ ꢂꢎꢇꢇꢆꢘꢁꢈ
ꢙ. ꢆRꢍꢎꢅꢉꢏ ꢉꢊꢋ ꢋꢊ ꢄꢓꢍꢗꢇ
ꢀ. ꢍꢗꢗ ꢆꢅꢑꢇꢉꢄꢅꢊꢉꢄ ꢍRꢇ ꢅꢉ ꢑꢅꢗꢗꢅꢑꢇꢋꢇRꢄ
ꢃ. ꢆꢅꢑꢇꢉꢄꢅꢊꢉꢄ ꢊꢜ ꢇꢝꢔꢊꢄꢇꢆ ꢔꢍꢆ ꢊꢉ ꢐꢊꢋꢋꢊꢑ ꢊꢜ ꢔꢍꢓꢕꢍꢏꢇ ꢆꢊ ꢉꢊꢋ ꢅꢉꢓꢗꢖꢆꢇ
ꢑꢊꢗꢆ ꢜꢗꢍꢄꢞ. ꢑꢊꢗꢆ ꢜꢗꢍꢄꢞꢟ ꢅꢜ ꢔRꢇꢄꢇꢉꢋꢟ ꢄꢞꢍꢗꢗ ꢉꢊꢋ ꢇꢝꢓꢇꢇꢆ 0.ꢁꢠꢡꢡ ꢊꢉ ꢍꢉꢢ ꢄꢅꢆꢇ
ꢠ. ꢇꢝꢔꢊꢄꢇꢆ ꢔꢍꢆ ꢄꢞꢍꢗꢗ ꢐꢇ ꢄꢊꢗꢆꢇR ꢔꢗꢍꢋꢇꢆ
ꢣ. ꢄꢞꢍꢆꢇꢆ ꢍRꢇꢍ ꢅꢄ ꢊꢉꢗꢢ ꢍ RꢇꢜꢇRꢇꢉꢓꢇ ꢜꢊR ꢔꢅꢉ ꢁ ꢗꢊꢓꢍꢋꢅꢊꢉ
ꢊꢉ ꢋꢊꢔ ꢍꢉꢆ ꢐꢊꢋꢋꢊꢑ ꢊꢜ ꢔꢍꢓꢕꢍꢏꢇ
Rev. 0
18
For more information www.analog.com
LTC4372/LTC4373
PACKAGE DESCRIPTION
MS8 Package
8-Lead Plastic MSOP
ꢄReꢩeꢪeꢫꢬe ꢓꢐꢗ ꢕꢙꢌ ꢭ 0ꢍꢮ0ꢅꢮꢈꢎꢎ0 Rev ꢌꢆ
0.ꢅꢅꢥ 0.ꢈꢇꢣ
ꢄ.0ꢉꢍ .00ꢍꢆ
ꢍ.ꢈ0
ꢄ.ꢇ0ꢈꢆ
ꢀꢑꢒ
ꢉ.ꢇ0 ꢤ ꢉ.ꢡꢍ
ꢄ.ꢈꢇꢎ ꢤ .ꢈꢉꢎꢆ
ꢉ.00 0.ꢈ0ꢇ
ꢄ.ꢈꢈꢅ .00ꢡꢆ
ꢄꢒꢂꢐꢊ ꢉꢆ
0.ꢍꢇ
ꢄ.0ꢇ0ꢍꢆ
Rꢊꢛ
0.ꢎꢍ
ꢄ.0ꢇꢍꢎꢆ
ꢝꢁꢗ
0.ꢡꢇ 0.0ꢉꢅ
ꢄ.0ꢈꢎꢍ .00ꢈꢍꢆ
ꢐꢢꢃ
ꢅ
ꢣ ꢎ ꢍ
Rꢊꢗꢂꢀꢀꢊꢒꢕꢊꢕ ꢁꢂꢓꢕꢊR ꢃꢏꢕ ꢓꢏꢢꢂꢚꢐ
ꢉ.00 0.ꢈ0ꢇ
ꢄ.ꢈꢈꢅ .00ꢡꢆ
ꢄꢒꢂꢐꢊ ꢡꢆ
ꢡ.ꢥ0 0.ꢈꢍꢇ
ꢄ.ꢈꢥꢉ .00ꢎꢆ
ꢕꢊꢐꢏꢑꢓ ꢧꢏꢨ
0.ꢇꢍꢡ
ꢄ.0ꢈ0ꢆ
0ꢦ ꢤ ꢎꢦ ꢐꢢꢃ
ꢌꢏꢚꢌꢊ ꢃꢓꢏꢒꢊ
ꢈ
ꢇ
ꢉ
ꢡ
0.ꢍꢉ 0.ꢈꢍꢇ
ꢄ.0ꢇꢈ .00ꢎꢆ
ꢈ.ꢈ0
ꢄ.0ꢡꢉꢆ
ꢀꢏꢞ
0.ꢅꢎ
ꢄ.0ꢉꢡꢆ
Rꢊꢛ
ꢕꢊꢐꢏꢑꢓ ꢧꢏꢨ
0.ꢈꢅ
ꢄ.00ꢣꢆ
ꢁꢊꢏꢐꢑꢒꢌ
ꢃꢓꢏꢒꢊ
0.ꢇꢇ ꢤ 0.ꢉꢅ
0.ꢈ0ꢈꢎ 0.0ꢍ0ꢅ
ꢄ.00ꢥ ꢤ .0ꢈꢍꢆ
ꢄ.00ꢡ .00ꢇꢆ
0.ꢎꢍ
ꢄ.0ꢇꢍꢎꢆ
ꢝꢁꢗ
ꢐꢢꢃ
ꢀꢁꢂꢃ ꢄꢀꢁꢅꢆ 0ꢇꢈꢉ Rꢊꢋ ꢌ
ꢒꢂꢐꢊꢔ
ꢈ. ꢕꢑꢀꢊꢒꢁꢑꢂꢒꢁ ꢑꢒ ꢀꢑꢓꢓꢑꢀꢊꢐꢊRꢖꢄꢑꢒꢗꢘꢆ
ꢇ. ꢕRꢏꢙꢑꢒꢌ ꢒꢂꢐ ꢐꢂ ꢁꢗꢏꢓꢊ
ꢉ. ꢕꢑꢀꢊꢒꢁꢑꢂꢒ ꢕꢂꢊꢁ ꢒꢂꢐ ꢑꢒꢗꢓꢚꢕꢊ ꢀꢂꢓꢕ ꢛꢓꢏꢁꢘꢜ ꢃRꢂꢐRꢚꢁꢑꢂꢒꢁ ꢂR ꢌꢏꢐꢊ ꢝꢚRRꢁ.
ꢀꢂꢓꢕ ꢛꢓꢏꢁꢘꢜ ꢃRꢂꢐRꢚꢁꢑꢂꢒꢁ ꢂR ꢌꢏꢐꢊ ꢝꢚRRꢁ ꢁꢘꢏꢓꢓ ꢒꢂꢐ ꢊꢞꢗꢊꢊꢕ 0.ꢈꢍꢇꢟꢟ ꢄ.00ꢎꢠꢆ ꢃꢊR ꢁꢑꢕꢊ
ꢡ. ꢕꢑꢀꢊꢒꢁꢑꢂꢒ ꢕꢂꢊꢁ ꢒꢂꢐ ꢑꢒꢗꢓꢚꢕꢊ ꢑꢒꢐꢊRꢓꢊꢏꢕ ꢛꢓꢏꢁꢘ ꢂR ꢃRꢂꢐRꢚꢁꢑꢂꢒꢁ.
ꢑꢒꢐꢊRꢓꢊꢏꢕ ꢛꢓꢏꢁꢘ ꢂR ꢃRꢂꢐRꢚꢁꢑꢂꢒꢁ ꢁꢘꢏꢓꢓ ꢒꢂꢐ ꢊꢞꢗꢊꢊꢕ 0.ꢈꢍꢇꢟꢟ ꢄ.00ꢎꢠꢆ ꢃꢊR ꢁꢑꢕꢊ
ꢍ. ꢓꢊꢏꢕ ꢗꢂꢃꢓꢏꢒꢏRꢑꢐꢢ ꢄꢝꢂꢐꢐꢂꢀ ꢂꢛ ꢓꢊꢏꢕꢁ ꢏꢛꢐꢊR ꢛꢂRꢀꢑꢒꢌꢆ ꢁꢘꢏꢓꢓ ꢝꢊ 0.ꢈ0ꢇꢟꢟ ꢄ.00ꢡꢠꢆ ꢀꢏꢞ
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
19
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LTC4372/LTC4373
TYPICAL APPLICATION
UNDERVOLTAGE CUTOFF = 24V
UNDERVOLTAGE RECOVERY = 28V
M2
M1
V
28V
10A
BSC026N08NS5
BSC026N08NS5
OUT
V
28V
IN
R5A
3650k
R1
10Ω
C
OUT
100µF
R5B
200k
IN
UV
SOURCE
U1
GATE OUT
R4
200k
LTC4373
R6
2150k
GND
INTV
CC
UVOUT
C1
100nF
M3
BSC026N08NS5
V
BACKUP
23V
IN
SOURCE
GATE OUT
R9
100k
2UPU
U2
LTC4372
SHDN
GND
INTV
CC
43723 F16
ꢀꢁ
ꢂ00ꢃꢄ
D4
1N4148W
R
ꢀꢁꢂ
ꢃꢄ
Figure 16. 28V Supply with Voltage Monitoring and Backup Channel
RELATED PARTS
PART NUMBER
LTC4352
LTC4353
LTC4355
LTC4357
LTC4358
LTC4359
LTC4364
LTC4371
LTC4376
DESCRIPTION
COMMENTS
Ideal Diode Controller
Controls N-Channel MOSFET, 0V to 18V Operation
Dual Ideal Diode Controller
Controls Two N-Channel MOSFETs, 0V to 18V Operation
Controls Two N-Channel MOSFETs, 0.4μs Turn-Off, 80V Operation
Controls N-Channel MOSFET, 0.5μs Turn-Off, 80V Operation
Internal N-Channel MOSFET, 9V to 26.5V Operation
High Voltage Diode-OR Controller and Monitor
High Voltage Ideal Diode Controller
5A Ideal Diode
Ideal Diode Controller with Reverse Input Protection
Surge Stopper with Ideal Diode
Controls N-Channel MOSFET, 4V to 80V Operation, –40V Reverse Input
4V to 80V Operation, –40V Reverse Input, –20V Reverse Output
Dual Negative Voltage Ideal Diode-OR Controller and Monitor Controls Two MOSFETs, 220ns Turn-Off, Withstands > 300V Transients
7A Ideal Diode with Reverse Input Protection Internal N-Channel MOSFET, 4V to 40V Operation, –40V Reverse Input
Rev. 0
10/20
www.analog.com
ANALOG DEVICES, INC. 2020
20
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