LTC4381 [ADI]
Low Quiescent Current Surge Stopper with 9mΩ MOSFET;
| 型号： | LTC4381 |
| 厂家： | 
ADI |
| 描述： | Low Quiescent Current Surge Stopper with 9mΩ MOSFET |
| 文件： | 总24页 (文件大小：2110K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4381
Low Quiescent Current Surge
Stopper with 9mΩ MOSFET
FEATURES
DESCRIPTION
The LTC®4381 is an integrated solution for low quiescent
current surge stopper applications that protect loads from
high voltage transients. Overvoltage protection is pro-
vided by clamping the gate voltage of an internal 9mΩ
N-channel MOSFET to limit the output voltage to a safe
value during overvoltage events such as load dump in
automobiles. The MOSFET safe operating area is pro-
duction tested and guaranteed for the stresses during
high voltage transients. Fixed output clamp voltages are
selectable for 12V and 24V/28V systems. For systems of
any voltage up to 80V, use the adjustable clamp versions.
n
Withstands Surge Voltages Up to 100V
n
Internal 9mΩ N-Channel MOSFET
n
Guaranteed Safe Operating Area: 20ms at 70V, 1A
n
Low Quiescent Current: 6µA Operating
n
Operates Through Automobile Cold Crank
n
Wide Operating Voltage Range: 4V to 72V
n
Overcurrent Protection
n
Selectable Internal 28.5V/47V or Adjustable Output
Clamp Voltage (Table 1)
n
Reverse Input Protection to –60V
n
Adjustable Turn-On Threshold
n
Adjustable Fault Timer with MOSFET Stress
Overcurrent protection is also provided. An internal mul-
Acceleration
Latchoff and Retry Options (Table 1)
tiplier generates a TMR pin current proportional to V
DS
n
and I , so that operating time in both overcurrent and
D
n
Low Retry Duty Cycle During Faults (Table 1)
overvoltage conditions is limited in accordance with
MOSFET stress.
n
32-Lead DFN (7mm × 5mm) Package
The GATE pin can drive back-to-back MOSFETs for
reverse input protection, eliminating the voltage drop
and dissipation of a Schottky diode solution. A low 6µA
operating current permits use in always-on and battery
powered applications.
APPLICATIONS
n
Automotive 12V, 24V and 48V System
n
Avionic/Industrial Surge Protection
n
Hot Swap/Live Insertion
n
High Side Switch for Battery Powered Systems
All registered trademarks and trademarks are the property of their respective owners.
n
Automotive Load Dump Protection
TYPICAL APPLICATION
12V System with 100V/0.5A/400ms Load Dump Overvoltage Protection
12V, 0.5A with 100V Overvoltage Protection
ꢀꢁꢂꢃ0.ꢄꢅ
ꢀ00ꢁ ꢂꢃꢄꢅꢆ ꢇꢅRꢈꢉ
80mΩ
ꢀ
ꢀꢁ
ꢆꢇꢈꢉꢇꢈ
ꢊꢋꢅꢌꢉꢍꢎ
ꢅꢈ ꢁꢏ.ꢄꢂ
ꢀ
ꢅ 0.ꢆꢃ
ꢀꢁ
ꢀRꢁ
ꢀꢁꢀ
ꢀꢁꢂ
ꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁ00ꢂ
ꢀ00ꢁ
ꢀ
ꢀ0ꢁ
ꢀRꢁ
ꢀꢁ
ꢀ
ꢀꢀ
ꢀ
ꢀꢁ
ꢀꢀꢁꢂ
10Ω
ꢀꢁ
ꢀ0ꢁꢂꢃꢄꢁ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢆꢆꢇ
0.ꢀꢁꢂ
FLT
33Ω
ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ0ꢁꢂꢃꢄꢁ
ꢀꢁR
ꢀꢁꢂ
ꢀꢁꢂꢃ ꢄꢅ0ꢃꢆ
ꢀ0ꢁꢂ
ꢀꢁꢂꢃ ꢄꢅ0ꢃꢆ
ꢀ00ꢁꢂꢃꢄꢅꢆ
Rev. 0
1
Document Feedback
For more information www.analog.com
LTC4381
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
ꢄꢆꢘ ꢋꢌꢎꢙ
IN (Note 5)............................................... –0.3V to 100V
ꢄꢅR
ꢆꢇ
ꢍꢎꢏ
FLT
ꢆꢐꢄ
ꢍꢇꢍ
ꢇꢊ
ꢈꢑꢄꢎ
ꢈꢒꢎꢄ
ꢌꢇ
ꢍRꢊ
ꢍRꢊ
ꢍRꢊ
ꢍRꢊ
ꢍRꢊ
ꢍRꢊ
ꢍRꢊ
ꢍRꢊ
ꢃ
ꢂ
ꢁꢂ
ꢁꢃ
ꢁ0
ꢂꢓ
ꢂꢗ
ꢂꢔ
ꢂꢕ
ꢂꢖ
ꢂꢀ
ꢂꢁ
ꢂꢂ
ꢂꢃ
ꢂ0
ꢃꢓ
ꢃꢗ
ꢃꢔ
V , ON, SEL............................................... –60V to 80V
CC
DRN (Note 3), SNS, OUT, SRC
ꢈꢇꢉ
ꢉRꢇ
ꢇꢊ
ꢁ
ꢀ
ꢖ
LTC4381-1/LTC4381-2 ........................... –0.3V to 53V
LTC4381-3/LTC4381-4........................... –0.3V to 80V
SNS to OUT..................................................... –5V to 5V
GATE, GFET (Note 4)
ꢋ
ꢊꢊ
ꢕ
ꢌꢇ
ꢍRꢊ
ꢍRꢊ
ꢍRꢊ
ꢍRꢊ
ꢍRꢊ
ꢍRꢊ
ꢍRꢊ
ꢍRꢊ
ꢍRꢊ
ꢔ
ꢗ
ꢓ
ꢃ0
ꢃꢃ
ꢃꢂ
ꢃꢁ
ꢃꢀ
ꢃꢖ
ꢃꢕ
ꢁꢁ
ꢌꢇ
LTC4381-1/LTC4381-2 ........................... –0.3V to 53V
LTC4381-3/LTC4381-4........................... –0.3V to 86V
GATE to OUT, GATE to V ,
CC
GFET to SRC (Note 4) ............................ –0.3V to 10V
TMR............................................................. –0.3V to 5V
FLT ............................................................. –0.3V to 80V
I
.......................................................................2.5mA
DRN
ꢉꢚꢎ ꢘꢑꢊꢚꢑꢈꢎ
ꢁꢂꢛꢏꢎꢑꢉ ꢜꢔꢝꢝ ꢞ ꢖꢝꢝꢟ ꢘꢏꢑꢍꢄꢌꢊ ꢉꢒꢇ
Operating Junction Temperature Range
ꢄ
ꢢ ꢃꢖ0ꢣꢊꢤ θ ꢢ ꢂꢁꢣꢊꢥꢙ
ꢠꢑ
ꢠꢅꢑꢡ
LTC4381C ................................................ 0°C to 70°C
LTC4381I .............................................–40°C to 85°C
LTC4381H.......................................... –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
ꢎꢡꢘꢆꢍꢎꢉ ꢘꢑꢉ ꢜꢘꢌꢇ ꢁꢁꢟ ꢌꢍ ꢌꢇ
ORDER INFORMATION
TUBE
TAPE AND REEL
PART MARKING* PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
LTC4381CDKE-2#PBF
LTC4381IDKE-2#PBF
LTC4381HDKE-2#PBF
LTC4381CDKE-4#PBF
LTC4381IDKE-4#PBF
LTC4381HDKE-4#PBF
LTC4381CDKE-2#TRPBF
LTC4381IDKE-2#TRPBF
LTC4381HDKE-2#TRPBF
LTC4381CDKE-4#TRPBF
LTC4381IDKE-4#TRPBF
LTC4381HDKE-4#TRPBF
43812
43812
43812
43814
43814
43814
32-Lead (7mm × 5mm) Plastic DFN
32-Lead (7mm × 5mm) Plastic DFN
32-Lead (7mm × 5mm) Plastic DFN
32-Lead (7mm × 5mm) Plastic DFN
32-Lead (7mm × 5mm) Plastic DFN
32-Lead (7mm × 5mm) Plastic DFN
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
–40°C to 85°C
–40°C to 125°C
Contact ADI Sales for LTC4381-1/LTC4381-3 option. Contact ADI Sales for parts specified with wider operating temperature ranges. *The temperature
grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
Rev. 0
2
For more information www.analog.com
LTC4381
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = OUT = SNS = DRN = 12V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
DC Characteristics
l
V
V
Input Voltage Range
(Note 7)
4
80
V
IN
l
l
Operating Voltage Range
LTC4381-1/LTC4381-2 (Note 7)
LTC4381-3/LTC4381-4 (Note 7, 8)
4
4
80
72
V
V
CC
l
V
Operating Voltage Range
V
= OUT = SNS = DRN = 12V
CC
72
V
OUT
l
l
I
Q
Total Supply Current, ON
(Note 6)
C-Grade and I-Grade
H-Grade
6
12
20
µA
µA
l
l
l
l
l
V
= OUT = SNS = DRN = 4V
18
5
35
10
12
30
10
µA
µA
µA
µA
µA
CC
I
V
V
Current, Shutdown
Current, ON
ON = OUT = SNS = 0V
CC
CC
V
CC
V
CC
V
IN
= OUT = SNS = DRN = 12V
= OUT = SNS = DRN = 4V
4
CC
16
I
I
IN pin Leakage Current
Reverse Input Current
= 24V, V
= V
= 0V, ON = 0V
IN
GFET
SRC
l
l
V
V
= –60V, ON Open, SEL = 0V
= ON = SEL = –60V
0
–1
–2
–5
mA
mA
R
CC
CC
R
MOSFET On-Resistance
IN = V = 8V, 12V, I
= –1A, I = –1µA
GATE
9
13
28
mΩ
ON
CC
SRC
l
SOA
MOSFET Safe Operating Area
V
– V
= 70V, 1A, 10W√s
20
ms
IN
SRC
SNS, OUT, SEL, ON, DRN
l
l
I
I
I
SNS Current, ON
0.5
1.5
6
1.4
5.5
µA
µA
SNS
OUT Current, ON
OUT, ON
OUT, SD
l
l
OUT Current, Shutdown
C-Grade and I-Grade
H-Grade
12
80
µA
µA
l
l
∆V
Current Limit Sense Voltage
(SNS – OUT)
V
V
= 12V, 24V, OUT = 6V, 12V
= 12V, 24V, OUT = 0V
45
40
50
62
55
95
mV
mV
SNS
CC
CC
l
l
l
l
I
SEL Input Current
SEL = 0V to 80V
0.1
3
µA
V
SEL
V
SEL Input Threshold
ON Input Current
0.4
–1
SEL
I
V
= 1V
ON
–2
1.05
45
–4
1.1
µA
V
ON
V
V
ON Input Threshold
ON Input Hysteresis
DRN Voltage (DRN – OUT)
ON Rising
0.99
ON
mV
V
ON(HYST)
l
l
∆V
I
= 0.1mA
DRN
0.7
2.25
0.7
2.6
DRN
V
Overvoltage V Threshold
TMR = 0.8V, I = 2µA
DRN
0.58
0.3
0.8
1.0
V
V
DS(MAX)
DS
(DRN – OUT)
SRC, GATE, FLT, TMR
l
l
l
l
V
SRC Voltage Output Clamp
V
IN
V
IN
V
IN
V
IN
= V = 80V, SEL = 0V, I = –10mA, LTC4381-1/LTC4381-2
OUT
25.5
43.5
19.0
31.0
28.5
47.0
22.5
34.5
31.5
50.5
26.0
38.0
V
V
V
SRC
CC
= V = 80V, SEL = V , I
= –10mA, LTC4381-1/LTC4381-2
= –10mA, LTC4381-3/LTC4381-4
= –10mA, LTC4381-3/LTC4381-4
CC
CC OUT
= 80V, V = 12V, I
CC
OUT
OUT
= 80V, V = 24V, I
CC
l
l
l
V
MOSFET Threshold
I
= –10mA
1
3
4.6
14
V
V
V
GFET(TH)
SRC
∆V
∆V
GATE Drive (GATE – OUT)
SEL = SNS = OUT = V , 8V ≤ V ≤ 30V
10
12
11.1
13.5
GATE
CC
CC
GATE Clamp to V (GATE – V
)
SNS = OUT = 20V, I
= 0µA
15.5
CLAMP
CC
CC
GATE
Rev. 0
3
For more information www.analog.com
LTC4381
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = OUT = SNS = DRN = 12V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
l
l
V
GATE Clamp to GND
V
V
= 30V, SEL = 0V, LTC4381-1/LTC4381-2
30
47.5
31.5
50
33
52.5
V
V
GATE
CC
CC
= 60V, SEL = V LTC4381-1/LTC4381-2
CC,
l
I
I
GATE Pull-Up Current
V
= GATE = OUT = 12V, 24V
–8.5
–20
–35
µA
GATE(UP)
CC
)
GATE Pull-Down Current
Overcurrent
GATE(DN
∆V
= 200mV, GATE = 12V, OUT = 0V
l
l
l
l
50
0.3
2
100
5
5
3.5
mA
mA
mA
mA
SNS
Shutdown
ON = 0V, GATE = 20V
Input UV
V
= 1.5V, GATE = 10V
CC
Fault Time Out
TMR = 2V, GATE = 10V
1.5
l
I
FLT Leakage Current
FLT Output Low
FLT = 80V
2
µA
FLT
l
l
V
I
I
= 0.1mA
= 3mA
0.1
1
0.5
4
V
V
FLT(LOW)
SINK
SINK
l
l
l
I
I
I
TMR Pull-Down Current
TMR = 0.8V
1.2
–1
1.6
–2
2.75
–3
µA
µA
µA
TMR(DN)
(
TMR Pull-Up Current, Cool Down TMR = 2V
TMR UP, COOL)
TMR Pull-Up Current, Overvoltage TMR = 0.8V, OUT = 11V, V = 1.1V, ∆V
= 0mV
–0.7
–1.6
–2.4
TMR(UP)
DS
SNS
OUT = 28V, TMR = 0.8V
l
l
l
l
Small OV, Light Load
High OV, Light Load
Small OV, Heavy Load
High OV, Heavy Load
I
I
I
I
= 0.1mA, ∆V
= 10mV
–3.5
–13
–10
–60
–6.7
–30
–20
–12
–61
–30
µA
µA
µA
µA
DRN
DRN
DRN
DRN
SNS
SNS
SNS
SNS
= 1mA, ∆V
= 10mV
= 0.1mA, ∆V
= 1mA, ∆V
= 40mV
= 40mV
–120 –180
TMR Pull-Up Current, Overcurrent TMR = 0.8V
l
l
l
l
l
l
I
I
I
I
I
I
= 0mA, OUT = 11V
= 0mA, OUT = 0V
= 0.1mA, OUT = 11V
= 1mA, OUT = 11V
= 0.1mA, OUT = 0V
= 1mA, OUT = 0V
–3
–6
–9
µA
µA
µA
µA
µA
µA
DRN
DRN
DRN
DRN
DRN
DRN
–16
–16
–80
–35
–24
–27
–36
–38
Small OV, Light Load
High OV, Light Load
Small OV, Heavy Load
High OV, Heavy Load
–142 –206
–50
–60
–130 –170 –220
l
V
TMR Gate Off Threshold
TMR Rising
1.178 1.215 1.251
V
TMR(F)
AC Characteristics
l
l
D
Retry Duty Cycle; Overvoltage,
LTC4381-2/LTC4381-4
∆V
∆V
= 40mV, I
= 40mV, I
= 5µA, OUT = 28V, V = 29V
2.8
0.1
4.2
0.2
%
%
SNS
DRN
CC
= 500µA, OUT = 28V, V = 80V
SNS
DRN
CC
Retry Duty-Cycle; Overcurrent,
LTC4381-2/LTC4381-4
I
= 500µA
DRN
l
l
OUT = 0V
OUT = 6V
0.1
0.35
0.2
0.7
%
%
l
l
l
l
t
t
t
Turn-On Propagation Delay
Turn-Off Propagation Delay
ON Steps from 0V to 1.5V, OUT = SNS = 0V
ON Steps from 1.5V to 0V, OUT = SNS = V
7.5
1
25
5
ms
µs
µs
µs
ON(ON)
OFF(ON)
OFF(OC)
CC
Overcurrent Turn-Off
Propagation Delay
∆V
SNS
∆V
SNS
Steps from 0V to 250mV, OUT = 6V
2
4
Steps from 0V to 250mV, OUT = 0V
2
4
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4: Internal clamps limit the GATE pin to a minimum of 10V above the
OUT pin or V pin, or 50V (SEL = V ) or 31.5V (SEL = GND) above the
GND pin (LTC4381-1/LTC4381-2). Driving this pin to voltages beyond the
clamp may damage the device.
CC
CC
Note 2: All currents into device pins are positive; all currents out of
device pins are negative. All voltages are referenced to GND unless
otherwise specified.
Note 5: IN ABS MAX is rated at 25°C to 125°C only.
Note 6: Total supply current is the sum of the current into the V , OUT,
SNS and DRN pins.
CC
Note 3: Internal clamps limit the DRN pin to a minimum of 10V above the
OUT and SNS pins.
Note 7: The LTC4381 can operate through the cold crank down to 4V in
automotive applications, wheres V is powered with a 12V supply initially
CC
and stays above 8V during the cold crank period.
Note 8: Operating voltage is limited by the maximum GATE voltage of 86V.
Rev. 0
4
For more information www.analog.com
LTC4381
VCC = 12V, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Total Supply Current (IQ)
vs Input Voltage
Total Supply Current (IQ)
vs Gate Leakage
Total Supply Current (IQ)
vs Temperature
ꢀ0
ꢀ0
ꢀ0
0
ꢀ00
ꢀ0
ꢀ
ꢀ00
ꢀ0
ꢀ
ꢀꢁꢂ ꢃ ꢄ
ꢀꢀ
ꢀ
ꢀ 0
ꢀꢁꢂꢃ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀ
ꢀ 0
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢅꢆꢇ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢅꢆꢇ
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0.00ꢁ
ꢀ0.0ꢁ
ꢀ0.ꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁ0
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁꢂꢃ ꢄ0ꢃ
ꢀꢁꢂꢃ ꢄ0ꢅ
ꢀꢁꢂꢃ ꢄ0ꢁ
Supply Current (ICC
vs Supply Voltage
)
Supply Current (ICC
vs Temperature
)
ISNS vs Temperature
ꢀ0
ꢀ0
ꢀ0
0
ꢀ00
ꢀ0
ꢀ
ꢀ0
ꢀꢁꢀ ꢂ ꢃꢄꢅ ꢂ ꢆ
ꢀꢁꢀ ꢂ ꢃꢄꢅ ꢂ ꢆ
ꢀꢀ
ꢀꢁꢀ ꢂ ꢃꢄꢅꢂ ꢀꢆꢇ ꢂ ꢈ
ꢀꢀ
ꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ ꢁꢂ
ꢀ ꢁꢂꢃ
ꢀꢀ
ꢀꢀ
0.ꢀ
0
ꢀ0
ꢀ0
ꢀ0
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ
ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ
ꢀꢀ
ꢀꢁꢂꢃ ꢄ0ꢀ
ꢀꢁꢂꢃ ꢄ0ꢅ
ꢀꢁꢂꢃ ꢄ0ꢅ
Reverse Current
Gate Pull-Up Current
vs Temperature
Output Pin Current
vs Temperature
vs Reverse Voltage
ꢀ0
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁ
ꢀ00
ꢀ0
ꢀꢁꢂ ꢃ ꢄꢅ ꢃ ꢆ
ꢀꢀ
ꢀꢁꢀ ꢂ ꢃꢄꢅ ꢂ ꢆ
ꢀꢀ
ꢀ
ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢆꢇ
ꢀꢁꢂꢃ ꢄ 0ꢅ
ꢀꢁꢂꢃ ꢄ ꢅꢆꢇ
0.ꢀ
ꢀ
ꢀꢁ0 ꢀꢁ0 ꢀꢁ0 ꢀꢁ0 ꢀꢁ0 ꢀꢁ0 ꢀꢁ0 ꢀꢁ0
ꢀꢁꢂ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ
ꢀꢀ
ꢀꢁꢂꢃ ꢄ0ꢂ
ꢀꢁꢂꢃ ꢄ0ꢅ
ꢀꢁꢂꢃ ꢄ0ꢅ
Rev. 0
5
For more information www.analog.com
LTC4381
VCC = 12V, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Gate Drive vs Pull-Up Current
Gate Drive vs Temperature
Gate Drive vs Supply Voltage
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀ
ꢀꢁ
ꢀ0
ꢀ
ꢀꢁ
ꢀ0
ꢀ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂ ꢃ ꢄ
ꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ ꢁꢂ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢀ
ꢀꢀ
ꢀꢀ
ꢀꢀ
ꢀ ꢁꢂꢃ
ꢀ
ꢀ ꢁꢂ
0
0
0
0
ꢀꢁ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁꢂꢃ
0
ꢀ0
ꢀ0
ꢀ0
ꢀ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ
ꢀ
ꢀꢁꢂ
ꢀꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ ꢄꢃ0
ꢀꢁꢂꢃ ꢄꢃꢃ
ꢀꢁꢂꢃ ꢄꢃꢅ
TMR Pin Current vs Temperature,
Overcurrent Fault
TMR Pin Current vs Temperature,
Overvoltage Fault
VSRC vs Temperature
ꢀꢁ0
ꢀꢁꢁ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢂ0
ꢀꢁꢂ0
ꢀꢁꢂ0
ꢀꢁ00
ꢀꢁ0
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢀ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢀ
ꢀ
ꢀ 0.ꢁꢂꢃ
ꢀ
ꢀ ꢁꢂꢃ
ꢀRꢁ
ꢀRꢁ
∆V
ꢀꢁꢀ
ꢀ ꢁ0ꢂꢃ
ꢀ ꢁ0ꢂꢃ
ꢀꢁꢀ
∆V
ꢀꢁ0
ꢀꢁ0
ꢀꢁꢂ ꢃ 0ꢄ
ꢀꢁꢂ ꢃ ꢄꢅ
ꢀꢁ0
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃ ꢄꢃꢀ
ꢀꢁꢂꢃ ꢄꢃꢅ
ꢀꢁꢂꢃ ꢄꢃꢁ
Current Limit vs Output Voltage
DRN Voltage vs Current
ON Pin Current vs Voltage
ꢀꢁꢂ0
ꢀꢁꢂ0
ꢀꢁꢂ0
ꢀꢁ00
ꢀꢁ0
ꢀ.0
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.0
ꢀꢁ.0
ꢀꢁ.ꢂ
ꢀꢁ.0
ꢀꢁ.ꢂ
ꢀꢁ.0
ꢀꢁ.ꢂ
ꢀꢁ.0
ꢀ0.ꢁ
0
ꢀ
ꢀ ꢁꢂꢃ
ꢀRꢁ
∆V
ꢀ ꢁ
ꢀRꢁ ꢀꢁꢂ
ꢀ ꢁ
ꢀRꢁ
∆V
ꢀꢁꢀ
ꢀ ꢁ0ꢂꢃ
ꢀ ꢁ0ꢂꢃ
ꢀꢁꢀ
∆V
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁꢂꢃ
ꢀ
ꢀ0
ꢀ00
ꢀꢁ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ
ꢀ
ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂ
ꢀꢁ
ꢀRꢁ
ꢀꢁꢂꢃ ꢄꢃꢅ
ꢀꢁꢂꢃ ꢄꢃꢅ
ꢀꢁꢂꢃ ꢄꢃꢂ
Rev. 0
6
For more information www.analog.com
LTC4381
VCC = 12V, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
RON vs Temperature
RON vs VCC
MOSFET SOA Curve
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀꢁ
ꢀ00
ꢀ0
ꢀ
ꢀ ꢁꢂ
ꢀ ꢁꢂꢃ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢄꢀꢅ
ꢀꢀ
100μs
ꢀꢁꢂ
ꢀ
ꢀ
ꢀ0ꢁꢂ
ꢀ00ꢁꢂ
0
0
0.ꢀ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
0
ꢀ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ0
ꢀꢁ
ꢀ00 ꢀ00
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂ
ꢀꢀ
ꢀꢁ ꢀRꢁ
ꢀꢁꢂꢃ ꢄꢃꢅ
ꢀꢁꢂꢃ ꢄꢅ0
ꢀꢁꢂꢃ ꢄꢅꢃ
PIN FUNCTIONS
DRN: MOSFET Drain-Source Sense. The DRN pin voltage series resistor at the pin is necessary to compensate the
current limit amplifier. To avoid damaging the MOSFET
during an output short, GATE is also clamped internally
to 17V above OUT.
tracks the OUT pin. The resulting DRN pin current through
external resistor RDRN is proportional to the MOSFET VDS.
The DRN pin current and ∆V
(SNS – OUT) are mul-
SNS
tiplied internally to produce a TMR pin current approxi-
GFET: Gate of Internal N-Channel MOSFET. Connect this
pin to the GATE pin through a 10Ω resistor.
mately proportional to the MOSFET’s power dissipation.
This reduces the SOA requirement of the MOSFET by tim
-
GND: Device Ground.
ing out faster during more severe faults. Choose R to
DRN
limit the current to 1mA at the peak input voltage. Connect
IN: Input of MOSFET. This is the drain terminal of the inter-
nal MOSFET. Connect this pin to the supply input.
to OUT if unused.
FLT: Fault Output. This open-drain logic output pin pulls
low after the voltage at the TMR pin has reached the fault
threshold of 1.215V. It indicates that the MOSFET is off
because either the supply voltage has stayed at an ele-
vated level for an extended period of time (voltage fault)
or the device is in an overcurrent condition (current fault).
The fault output is capable of sinking up to 3mA. Leave
open or tie to GND if unused.
ON: Turn-On Control Input. The LTC4381 can be turned
on by pulling this pin above 1.05V or by leaving it open to
allow an internal 1MΩ resistor to turn the part on. Pulling
the pin below the threshold puts the part in shutdown
mode and reduces the supply current to 5µA. Limit the ON
leakage current to less than 1µA if no external pull-up is
used. The ON pin can be pulled up to 80V or below GND
by 60V without damage.
GATE: Gate Drive for Internal N-Channel MOSFET. The
GATE pin is pulled up by an internal 20µA charge pump
that is regulated to 11.5V above the OUT pin. An amplifier
controls the GATE pin to limit the current through the
MOSFET. A minimum of 47nF of capacitance and 33Ω
OUT: Output Voltage Sense. This pin senses the output
voltage at the output terminal of the current sense resistor.
An internal clamp limits the voltage in between the GATE
and OUT pins to 17V. Bypass the OUT pin with a minimum
of 22µF as close to the pin as possible.
Rev. 0
7
For more information www.analog.com
LTC4381
PIN FUNCTIONS
SEL: Output Clamp Voltage Select for LTC4381-1 and
TMR: Fault Timer Input. Connect a capacitor between this
pin and ground to set the fault turn-off time and cool
down period. The charging current during fault conditions
varies depending on the power dissipation of the MOSFET.
When TMR reaches 1.215V, the MOSFET turns off and
FLT pulls low. Upon gate off, the part immediately enters
a cool down period with a 2µA current pull up and pull
down on the TMR pin. After the cool down period has
concluded, the LTC4381-2 and LTC4381-4 immediately
restart, while the LTC4381-1and LTC4381-3 remain off
until the ON pin is pulled low momentarily for more than
100µs or power is cycled. A 10V rated X7R capacitor is
LTC4381-2. Connect the SEL pin to GND to set the inter-
nal output clamp voltage to 28.5V. Connect it to V or
OUT for a 47V output clamp voltage. The SEL pin can be
pulled up to 80V or below GND by 60V without damage.
Connect SEL to GND for LTC4381-3 and LTC4381-4.
CC
SNS: Current Sense Input. Connect to the input terminal
of the current sense resistor. The current limit amplifier
controls the GATE pin to limit the current sense voltage
to 50mV. This voltage increases to 62mV in a severe fault
when OUT is below 1.5V. A fixed 6µA is added to the TMR
pin current during an overcurrent condition to shorten the
turn-off time. In a severe short condition when the output
voltage is below 1.5V, the extra current increases to 24µA
to reduce the power dissipation in the MOSFET. ∆VSNS
(SNS – OUT) must be limited to less than 5V. Connect
to OUT if unused.
recommended for C
.
TMR
V : Positive Supply Voltage Input. The positive supply
CC
input ranges from 4V to 80V. For applications where the
input voltage is expected to exceed 80V, the V pin may
be protected by a Zener diode clamp or, in tChCe case of
short duration spikes, by a simple RC filter. Clamping the
SRC: Output of MOSFET. This is the source terminal of the
internal MOSFET, connect this pin to the sense resistor.
The SRC pin and output is indirectly clamped through
GATE pin during an overvoltage event. The LTC4381-1/
LTC4381-2 SRC pin is clamped at 28.5V above GND with
SEL = 0 V, or 47V above GND when SEL = V . It is also
clamped at 10.5V above VCC if the VCC volCtaCge is low.
The LTC4381-3/LTC4381-4 SRC pin does not have the
28.5V/47V clamp to GND, it is only clamped at 10.5V
V
pin with a Zener diode can also be used as a means of
CC
adjusting the output clamp voltage to a value less than the
internal 28.5V/47V clamps for the LTC4381-1/LTC4381-2.
For the adjustable versions, LTC4381-3/LTC4381-4,
which have no internal clamp, a Zener diode at the V
CC
pin is the only way to limit the voltage at the output. The
V
pin can also be powered separately from the V pin.
CC
IN
above V .
CC
Rev. 0
8
For more information www.analog.com
LTC4381
BLOCK DIAGRAM
R
SNS
INPUT
OUTPUT
V
GATE
GFET
IN
SRC
SNS
OUT
CC
9mΩ
17V
13.5V
CHARGE PUMP
REGULATED TO
V
+11.5V
OUT
20µA
(250kHz)
31.5V*
18.5V*
–
+
–
+
50mV/62mV
3.5V
R
DRN
SEL
IA
1M
ON
+
–
–
+
SNS
OUT
ON
1V
DRN
CONTROL
LOGIC
MULTIPLIER
V
CC
I
MULT
UV
RST GOFF
–
+
V
2.2V
MAX
3.5V
3.4V
0.1V
6µA, 24µA
3.5V
OVERCURRENT
3.6µA
3.5V
+
–
4µA
FLT
COOL
DOWN
OVERVOLTAGE
2µA
+
–
1.215V
TMR
GND
4381 BD
*ONLY IN LTC4381-1/LTC4381-2
Rev. 0
9
For more information www.analog.com
LTC4381
OPERATION
The LTC4381 is a low quiescent current surge stopper that
drives an internal 9mΩ N-channel MOSFET as the pass
device. In normal operation, a 20µA charge pump (see
Block Diagram) drives MOSFET M1 fully on, providing a
low impedance path from input to the load. The MOSFET
gate is clamped to ground by a Zener stack. If the input
voltage rises to the point where the output approaches
the gate clamp, the output is effectively limited to one
threshold voltage (typically 3V) below the gate clamp and
the input surge is blocked from reaching the load.
A multiplier sets the timer period depending on the power
dissipation in the MOSFET. Higher power dissipation cor-
responds to a shorter timer period, helping to keep the
MOSFET within its safe operating area (SOA).
The timer responds to stresses at start-up and during
voltage and current limiting. TMR pin current is integrated
on timing capacitor C
and if TMR charges to 1.215V,
TMR
the MOSFET is turned off. At this point, the LTC4381-1
and LTC4381-3 latch off, and can be reset by cycling
power or by pulling the ON pin low for at least 100µs.
For the LTC4381-2 and LTC4381-4, the TMR pin enters a
cool down phase, allowing time for the MOSFET tempera-
ture to equalize with its surroundings before automatically
restarting. The TMR pin slowly charges up and down in
between 3.4V and 1.215V for 15 times and discharges to
ground at the last cycle. When the TMR pin has reached
the 100mV threshold, the MOSFET is turned back on. The
cool down interval can be curtailed by pulling the ON pin
For the LTC4381-1 and LTC4381-2 versions, two output
clamping voltages to ground are available: 28.5V for use
in 12V systems, and 47V for use in 24V and 28V sys-
tems. The clamping voltage is selectable using the SEL
pin. Besides the output to ground clamp, the output is
also limited to 10.5V above the V pin.
CC
There is no GATE clamp to ground for the LTC4381-3
and LTC4381-4 versions and the output is only limited
low for at least 10ms/µF of C
.
TMR
to 10.5V above the voltage at the V pin. A Zener diode
CC
clamp connected from the V pin to ground thus clamps
In addition to resetting the timer, the ON pin is used for
on/off control and for undervoltage detection. The ON pin
threshold is 1.05V.
CC
CC
the voltages at both the V and SRC pins during over-
voltage events.
Load current is limited by a current limit amplifier (IA),
using a sense resistor in series with the MOSFET source
to monitor the current. The current limit threshold is
50mV, rising to 62mV when the output is less than 1.5V.
The open drain FLT pin pulls low whenever the timer is
faulted off and goes high again when reset by a power
cycle, by pulling the ON pin low for at least 100µs or in
the case of the LTC4381-2 and LTC4381-4, when the TMR
pin discharges to 100mV.
MOSFET stress is monitored by a timer, whose current is a
function of MOSFET’s V as well as I . V is monitored
Table 1. LTC4381 Options
DS
D
DS
by R
at the DRN pin, while I is monitored by sens-
ing the voltage drop across R . The timer allows the
PART NUMBER
LTC4381-1
LTC4381-2
LTC4381-3
LTC4381-4
OUTPUT CLAMP
FAULT BEHAVIOR
Latchoff
DRN
D
SNS
Internal 28.5V/47V to GND
Internal 28.5V/47V to GND
Externally Adjustable
Externally Adjustable
load to continue functioning during short transient events
while protecting the MOSFET from being damaged by a
sustained overvoltage, such as load dump in vehicles, or
an output overload or short circuit.
Auto Retry
Latchoff
Auto Retry
Contact ADI Sales for LTC4381-1/LTC4381-3 option.
Rev. 0
10
For more information www.analog.com
LTC4381
APPLICATIONS INFORMATION
The LTC4381 limits the voltage and current delivered
to the load during supply transient or output overload
events. The N-channel MOSFET provides a low resistance
path from the input to the load during normal operation. In
overvoltage conditions it limits the output to a threshold
voltage below the clamped gate voltage. The total fault
timer period is set to ride through short-duration faults,
while longer events cause the output to shut off and pro-
tect the MOSFET from damage.
Overvoltage Fault Protection
The LTC4381 limits the voltage at the output during an
overvoltage at the input. For the LTC4381-1/LTC4381-2
illustrated in Figure 1, an internal clamp limits the output
to either 28.5V or 47V, depending on the state of the SEL
pin. With the SEL pin grounded as shown, the output
is clamped at 28.5V. Tying the SEL pin high causes the
output to clamp at 47V.
The GATE pin may also be limited by the compliance of
the internal 20µA current source, to V + 13.5V. In the
LTC4381-3/LTC4381-4 the GATE pinCcClamp is entirely
Start-Up
Figure 1 shows a 12V, 1A application which limits the
output to approximately 28.5V. When power is first
disconnected, leaving only the V + 13.5V compliance
CC
limit. This arrangement allows the output to be effectively
clamped at any voltage from 14.5V to 72V, by clamping
applied with V ≥ 4V and ON ≥ 1.05V, there is a delay of
CC
about 10ms before the GATE pin begins charging C2 and
MOSFET’s gate terminal with a fixed 20µA current source.
The internal MOSFET operates as a source follower, ramp-
V
to between 4V and 61.5V.
CC
V
Pin
CC
ing the output up at a rate of I
/C2. Inrush current
GATE(UP)
is given by Equation 1.
The LTC4381 can withstand an input surge voltage of up to
100V. If the maximum expected surge voltage is less than
in the load capacitance C
OUT
COUT
C2
80V, the V pin can be connected directly to the input
IINRUSH = IGATE(UP)
•
(1)
CC
supply. If the surge voltage is between 80V to 100V, the
V
pin must be protected by filtering or clamping since
CC
where I
is typically 20µA.
GATE(UP)
its operating range is from 4V to 80V for LTC4381-1/
LTC4381-2 and 4V to 72V for LTC4381-3/LTC4381-4.
For short duration spikes and transients exceeding 80V,
Eventually, the GATE pin charges to the point where V ≈
IN
VOUT and stops only when ∆VGATE (VGATE – VOUT) reaches
its regulation point of 11.5V, fully enhancing the MOSFET.
filtering is the most sensible means of protecting the V
CC
pin. R1 and C1 provide filtering in Figure 1. Owing to the
Overcurrent Fault Protection
LTC4381’s low I , values up to 100k may be used for R1
CC
without seriously impairing the lower end of the operating
voltage range. For long duration surges such as auto-
motive load dump, C1 becomes prohibitively large and
The LTC4381 features an adjustable current limit that pro-
tects against short circuits and excessive load current.
During an overcurrent event, the GATE pin is regulated to
limit the current sense voltage across the SNS and OUT
Zener D1 is the most effective means of limiting the V
CC
pins (∆V ) to 50mV when OUT is above 3V. In the case
SNS
R
ꢀꢁꢀ
40mΩ
of a severe short at the output, where OUT is less than
1.5V, the current sense voltage is 62mV. Output current is
ꢀꢁꢂꢃꢀꢄ ꢅꢆꢇꢈꢆꢇ
ꢀ
ꢁꢂ
ꢃꢄꢀ
ꢀꢁ
ꢀRꢁ
ꢀꢁꢀ
ꢀꢁꢂ
ꢉꢊꢄꢋꢈꢌꢍ ꢄꢇ ꢁꢎ.ꢏꢂ
R
ꢀRꢁ
ꢂ00ꢃ
Rꢀ
ꢀ
ꢀꢁꢂ
ꢀꢀꢁꢂ
ꢀ0ꢁ
ꢀRꢁ
thereby limited to ∆V /R . Current limit may control
R3
10Ω
SNS SNS
ꢀ
ꢀꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈ
the startup ramp rate in extreme cases, such as if C
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
OUT
ꢀꢁ
ꢀ.ꢁꢂꢃ
ꢀꢁꢂ
is unusually large or if current limit is set to an unusually
Rꢀ
FLT
33Ω
low value, and artificially reduces C ’s inrush current
ꢀꢁR
ꢀꢁꢂ
OUT
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢆꢆꢇ
ꢀꢁꢂꢃ ꢄ0ꢃ
ꢀ
ꢀꢁR
below the value previously calculated.
ꢀꢀ0ꢁꢂ
Figure 1. 12V/1A, Output Limited to 28.5V
Rev. 0
11
For more information www.analog.com
LTC4381
APPLICATIONS INFORMATION
voltage. Using a 68V Zener assures that D1 will not over-
ride the internal GATE pin clamp in the LTC4381-1 and
LTC4381-2 devices. For the LTC4381-3 and LTC4381-4,
In the presence of a sustained fault, the timer current
charges the TMR pin to 1.215V. At this point, the FLT pin
pulls low to indicate a fault condition and the GATE pin
pulls low, shutting off the MOSFET. After faulting off, the
timer enters the cool down phase. At the end of the cool
down period, the LTC4381-1/LTC4381-3 remain off until
manually reset, while the LTC4381-2/LTC4381-4 auto-
matically restart.
the V operating range extends from 4V to 72V. Since
CC
the SRC pin is regulated to V + 10.5V, D1 is chosen to
achieve the desired output cClaCmping effect while at the
same time keeping the VCC pin within its 4V to 72V range.
The LTC4381 can operate through the cold crank down
to 4V in automotive applications, wheres V is powered
CC
Fault Timer Operation in Overvoltage or Large V
with a 12V supply initially and stays above 8V during the
DS
cold crank period.
During start-up or an overvoltage condition, where the
MOSFET’s V exceeds 0.7V, the TMR pin charges from
DS
Fault Timer Overview
0V to 1.215V with a current that varies principally as a
Overvoltage and overcurrent conditions, and high VDS
conditions in MOSFET are limited in duration by an adjust-
function of V and I . V is inferred from the current
DS D DS
flowing in the DRN pin resistor, R , while the voltage
DRN
able fault timer. A capacitor at the TMR pin (C
) sets
difference between the SNS and OUT pins (∆V ) rep-
TMR
SNS
the delay time before a fault condition is reported at the
FLT pin and MOSFET is turned off. CTMR also sets the cool
down time before MOSFET is permitted to turn back on
for the LTC4381-2 and LTC4381-4 auto retry versions.
The LTC4381-1 and LTC4381-3 versions simply latch off
at the end of the timer delay. A 10V or higher rated X7R
resents the MOSFET current, I .
D
The TMR pin current is given by Equation 2.
⎛
⎞
⎟
⎡
⎢
⎢
⎣
⎤
⎥
⎥
⎦
A
V
I
= 0.0917
•V
• IDRN − 70⎡µA⎤
⎣ ⎦
SNS
⎜
TMR
(2)
⎜
⎝
⎟
⎠
capacitor is recommended for C
ture and voltage sensitivity.
to minimize tempera-
TMR
where 0.0917√A/V is the gain term of the multiplier. If
I
I
is less than 70µA (for example during start-up), use
of 1.5µA.
DRN
TMR
Fault timing starts as soon as the input power is applied
with the part in the on condition, or when the part turns
on after application of power. A 1.5µA current is gener-
ated to pull up the TMR pin when the voltage across the
MOSFET is higher than 0.7V. The timer speeds up with
an additional current that varies with the power dissipated
in the MOSFET. The power dissipation is the product of
the voltage across the MOSFET (VDS) and the current
Substituting for ∆V
and I
is given by Equation 3.
SNS
DRN
⎛
⎞
⎡
⎢
⎣
⎤
A
V
VDS
RDRN
ITMR = 0.0917
• I •R
•
− 70 µA
[
]
(3)
⎥
⎜
D
SNS
⎟
⎝
⎠
⎦
If I
is less than 70µA (for example during start-up),
TMR
DRN
use I
of 1.5µA.
flowing through it (I ). V is inferred from the voltage
D
DS
When TMR reaches 1.215V, the FLT pin pulls low and the
MOSFET is turned off and allowed to cool for an extended
period. The total elapsed time between the onset of output
clamping and turning off is given by Equation 4.
drop across the drain pin resistor, RDRN, while ∆VSNS rep-
resents I .
D
At initial power-up, the 1.5µA pilot current charges the
TMR pin capacitor because the input supply is, at least
for a short time, more than 0.7V above the output voltage.
When the output rises to within 0.7V of the input supply
voltage, the pull-up current disappears and an internal
2µA current source discharges the TMR pin capacitor. The
capacitor must be sized to ride through the initial start-up
interval for successful power-up.
CTMR
ITMR
t
TMR = VTMR(F) •
(4)
Because I
is a function of V and I , the exact time
TMR
DS
D
spent in overvoltage before turning off depends upon the
input waveform and the load current.
Rev. 0
12
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LTC4381
APPLICATIONS INFORMATION
Fault Timer Operation in Overcurrent
timer continues to charge from 1.215V to 3.4V with 2µA,
and then discharge back down to 1.215V with 2µA. This
cycle repeats 14 times and at the 15th cycle the TMR pin
is pulled all the way to ground. The total cool down time
is given by Equation 8.
TMR pin behavior in overcurrent is substantially the same
as in overvoltage. In the presence of an overcurrent con-
dition when the LTC4381 regulates the output current, the
TMR pin charges from 0V to 1.215V with a current that
varies principally as a function of the power dissipated in
the MOSFET. In addition to the variable current, an addi-
tional 24µA hastens timeout in a low impedance short
where the output is less than 1.5V. This additional current
15 • 4.37V +(1.215V – 0.1V)
tCOOL = CTMR
•
2 µA
[
]
(8)
s
µF
⎡
⎤
= CTMR • 33.3
⎢
⎥
⎣
⎦
is reduced to 6µA when V
is above 3V.
OUT
The TMR pin current with V
by Equation 5.
less than 1.5V is given
OUT
where C
is in µF.
TMR
Up to this point the operation of the LTC4381-1/LTC4381-3
and LTC4381-2/LTC4381-4 is the same. Behavior at the
end of the cool down phase is entirely different.
⎛
⎞
⎡
⎢
⎣
⎤
⎥
⎦
A
VDS
ITMR = 0.0917
• I •R
•
− 70 µA
[ ]
D
⎜
SNS
⎟
V
RDRN
⎝
⎠
(5)
At the end of the cool down phase, when TMR crosses
the 100mV reset threshold, the LTC4381-1/LTC4381-3
remain latched off and FLT remains low. They may be
restarted by pulling the ON pin low for at least 100µs or
by cycling the power supply. The cool down phase may
be interrupted at anytime by pulling the ON pin low for at
least 10ms/µF of CTMR; the LTC4381-1/LTC4381-3 will
restart when ON goes high. The LTC4381-2/LTC4381-4
will automatically retry at the end of the cool down phase
without cycling the ON pin and the cool down phase
may be interrupted by pulling the ON pin low for at least
+24.5 µA
[
]
where 24.5μA is the extra TMR current during overcurrent
condition. If I
is less than 70µA, use I
of 24µA.
DRN
TMR
And with V
above 3V given by Equation 6.
OUT
⎛
⎞
⎡
⎢
⎣
⎤
⎥
⎦
A
V
VDS
RDRN
ITMR = 0.0917
• I •R
•
− 70 µA
[
]
D
⎜
SNS
⎟
⎝
⎠
(6)
+6 µA
[
]
where 6μA is the extra TMR current during overcurrent
condition. If I is less than 70µA, use I of 6µA.
10ms/µF of C
.
TMR
DRN
TMR
For both versions, the FLT pin goes high in shutdown and
When TMR reaches 1.215V, the FLT pin pulls low and the
MOSFET is turned off and allowed to cool for an extended
period. The total elapsed time between the onset of output
clamping and turning off is given by Equation 7.
is cleared high when power is first applied to V . If FLT
CC
is set low, it can be reset during the cool down phase by
pulling the ON pin low for at least 10ms/µF of C
.
TMR
CTMR
ITMR
Supply Transient Protection
t
TMR = VTMR(F) •
(7)
The LTC4381-1/LTC4381-2 is tested to operate to 80V
and the LTC4381-3/LTC4381-4 to 72V. The IN and V
CC
Because I
is a function of V and I , the exact time
TMR
DS
D
pins are guaranteed to be safe from damage up to 100V
and 80V, respectively. Voltage transients above these volt-
ages may cause permanent damage. During a short-cir-
cuit condition, the large change in current flowing through
power supply traces and associated wiring can cause
large inductive voltage transients. To minimize the voltage
transients, minimize the power trace parasitic inductance
spent in overcurrent before turning off depends upon the
input waveform, the output voltage and the time required
for the output current to come into regulation.
Cool Down Phase
Cool down behavior is the same whether initiated by over-
voltage or overcurrent. During the cool down phase, the
Rev. 0
13
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LTC4381
APPLICATIONS INFORMATION
by using short, wide traces. An RC filter at the V pin is
constants of t = 10µs, V = 80V and τ = 1ms. A surge
r PK
CC
an effective measure against voltage spikes.
condition known as load dump commonly has constants
of t = 5ms, V = 60V and τ = 200ms.
r
PK
Another way to limit transients to less than 80V at the V
CC
MOSFET stress is the result of power dissipated within
the device. For long duration surges of 100ms or more,
stress is increasingly dominated by heat transfer out of
the package; this is a matter of device packaging and
mounting and heat sink thermal mass. This is best ana-
lyzed by simulation using the MOSFET thermal model.
pin is to use a small Zener diode and a resistor, D1 and R1
in Figure 1. The Zener diode limits the voltage at the pin
while the resistor limits the current through the diode to a
safe level during the surge. However, D1 can be omitted if
the filtered voltage at the V pin, due to R1 and C1, stays
CC
below 80V. The inclusion of R1 in series with the V pin
CC
modestly increases the minimum required voltage at V
For short duration transients of less than 100ms, MOSFET
survival is a matter of safe operating area (SOA), an
intrinsic property of the MOSFET. SOA quantifies the
time required at any given condition of VDS and ID to
raise the junction temperature of the MOSFET to its rated
maximum. MOSFET SOA can be expressed in units of
watt-root-seconds (P√t), which is essentially constant
for intervals of less than 100ms for any given device
type and rises to infinity under DC operating conditions.
Destruction mechanisms other than bulk die temperature
distort the lines of an accurately drawn SOA graph so that
IN
due to the extra voltage drop across it from the small V
CC
current of the LTC4381 and the leakage current of D1.
A total bulk capacitance of at least 22µF low ESR electro-
lytic or ceramic is required close to the OUT pin.
Transient Stress in the MOSFET
During an overvoltage event, the LTC4381 clamps the
gate of the pass MOSFET to limit the output voltage at an
acceptable level. The load circuitry may continue operat-
ing throughout this interval, but only at the expense of
dissipation in the MOSFET pass device. MOSFET dissipa-
tion or stress is a function of the input voltage waveform,
output voltage and load current.
P√t is not the same for all combinations of I and V .
DS
In particular P√t tends to degrade as VDS aDpproaches
the maximum rating, rendering some devices useless for
absorbing energy above a certain voltage. The LTC4381
internal MOSFET has a guaranteed SOA of 20ms at 70V
and 1A, which gives a P√t of 10W√s. To survive a longer
overvoltage transient, reduce the load current according
to this P√t spec.
Most transient event specifications use the prototypi-
cal waveshape shown in Figure 2, comprising a linear
ramp of rise time t , reaching a peak voltage of V and
r
PK
exponentially decaying back to V with a time constant
IN
of τ. A common automotive transient specification has
ꢀ
ꢁꢂ
ꢀ
ꢁꢂ
τ
τ
ꢀ
Rꢊꢋ
ꢀ
ꢃꢄ
ꢀ
ꢃꢄ
ꢌ
ꢍ
ꢋ
ꢌ
ꢅꢆꢇꢈ ꢉ0ꢊ
ꢅꢆꢇꢈ ꢉ0ꢆ
Figure 2. Prototypical Transient Waveform
Figure 3. Safe Operating Area Required to Survive
Prototypical Transient Waveform
Rev. 0
14
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LTC4381
APPLICATIONS INFORMATION
Calculating Transient Stress
Limiting Inrush Current and GATE Pin Compensation
The LTC4381 limits the inrush current to any load capac-
itance by controlling the GATE pin voltage slew rate.
Connect an external capacitor, C2, from GATE to ground
to reduce the inrush current at the expense of slower
turn-off time. The gate capacitor is set using Equation 11.
P√t for a prototypical transient waveform is calculated
using Equation 9 and Figure 3.
Let
a = V
– V
IN
REG
b = V – V
COUT
IINRUSH
PK
IN
C2 = IGATE(UP)
•
(11)
(V = Nominal Input Voltage)
IN
Then
P t = ILOAD
The LTC4381 needs a minimum of 47nF capacitance (C2)
and a 33Ω (R2) resistor in series at the GATE pin to stabi-
lize the current limit amplifier during an overcurrent event.
C2 also limits self enhancement of the MOSFET. A 10Ω
resistor, R3, is connected to the gate of the MOSFET to
suppress parasitic oscillations.
•
3
(9)
⎤
⎡
b – a
b
1
3
1
2
b
a
(
)
⎛
⎝
⎞
tr
+ τ 2a2 ln + 3a2 +b2 – 4ab
⎢
⎥
⎜
⎟
⎠
⎢
⎥
⎦
⎣
For the transient conditions of V = 100V, V = 12V,
PK
IN
Automobile Cold Crank Ride Through
V
= 28.5V, t = 10µs, τ = 1ms, and a load current of
REG
r
1A, P√t is 1.4W√s which can be handled by the MOSFET.
The P√t of other transient waveshapes is evaluated by
integrating the MOSFET power over root of time. LTspice®
can be used to simulate timer behavior for more complex
transients and cases where overvoltage and overcurrent
faults coexist, as well as the peak temperature rise of
the MOSFET.
During cold crank, the battery potential drops from the
12V nominal to as low as 3V for up to 40ms. The LTC4381
needs at least 4V at the V pin to function correctly. The
CC
low quiescent current requirement of the part allows an
RC filter with reasonable values to be placed at the VCC pin
to ride through cold crank as shown in Figure 4.
R
ꢀꢁꢀ
40mΩ
ꢀꢁꢂꢃꢀꢄ ꢅꢆꢇꢈꢆꢇ
ꢀ
ꢀRꢁ
ꢀꢁꢀ
ꢀꢁꢂ
ꢀꢁ
ꢁꢂ
ꢉꢊꢄꢋꢈꢌꢍ ꢄꢇ ꢁꢎ.ꢏꢂ
R
Calculating Short-Circuit Stress
ꢃꢄꢀ
ꢅꢂꢆꢇꢁꢂꢈꢉ ꢊꢀ
ꢈꢋ ꢌꢆꢉꢍ
ꢀRꢁ
ꢂ00ꢃ
Rꢀ
ꢀ
ꢀ0ꢁ
ꢁꢂꢃ
ꢀRꢁ
ꢀꢀꢁꢂ
SOA stress must also be calculated for a short-circuit
condition. Short-circuit P√t is given by Equation 10.
ꢀ
R3
10Ω
ꢀꢀ
ꢌRꢈꢂꢎꢏ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
FLT
ꢀꢁ
ꢀ.ꢁꢂꢃ
ꢀꢁꢂ
Rꢀ
⎛
⎜
⎝
⎞
ΔVSNS
RSNS
(10)
33Ω
P t = ΔVDS
•
• tTMR
ꢀꢁR
ꢀꢁꢂ
⎟
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ ꢄ0ꢀ
⎠
ꢀ
ꢀꢁR
ꢀꢀ0ꢁꢂ
where ∆V is the voltage across the MOSFET, ∆V
is
SNS
DS
Figure 4. Automotive Cold Crank Ride Through
the current limit threshold and t
is the overcurrent
TMR
timer interval, given by Equation 5 and Equation 6.
For V = 15V, ∆V = 12V (V
= 3V), ∆V
= 50mV,
IN
DS
OUT
SNS
R
= 12mΩ, R
= 100kΩ and C
= 68nF, P√t is
SNS
DRN
TMR
4.95W√s – somewhat higher than the transient SOA cal-
culated in the previous example.
Rev. 0
15
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LTC4381
APPLICATIONS INFORMATION
The ON pin can be pulled up to 80V or below GND by up
to 60V without damage. Leaving the pin open allows an
internal resistor to pull it up and turn on the part. The leak-
age current at the pin should be limited to no more than
1µA if no pull-up device is used to help turn on the part.
Ignoring the supply current (I ), the V potential at the
CC
CC
end of cold crank is given by Equation 12.
–t
(12)
VCC = (VIN(NOM) – VIN(LOW))• eR1•C1 + V
IN(LOW)
where V
is the input voltage before the cold crank
is the lowest input voltage during cold
IN(NOM)
Layout Considerations
starts, V
IN(LOW)
To achieve accurate current sensing, use Kelvin connec-
tions to the current sense resistor (RSNS in Figure 5).
The minimum trace width for 1oz copper foil is 0.02" per
amp to ensure the trace stays at a reasonable tempera-
ture. 0.03" per amp or wider is recommended. Note that
1oz copper exhibits a sheet resistance of about 530µΩ/
square. Small resistances can cause large errors in high
current applications. During an overvoltage event, the
LTC4381 clamps the gate of the pass MOSFET to limit
the output voltage at an acceptable level. The load circuitry
may continue operating throughout this interval, but only
at the expense of dissipation in the MOSFET pass device.
The power dissipated in the MOSFET could be as high as
140W. To remove this heat, solder the IN exposed pad to
a copper trace that contains vias underneath the pad. The
SRC pins also conduct substantial heat from the MOSFET.
Connect all the SRC pins to a plane of 1oz or 2oz copper.
crank, and t is the duration of the cold crank.
With the combination of R1 (10kΩ) and C1 (6.8µF), V
CC
drops to 8V after the input voltage drops from 12V to 3V
for 40ms. During this time GATE stays high, keeping the
MOSFET on to continue providing current to the output.
Shutdown
The LTC4381 can be shut down to a lower current mode
by pulling the ON pin below the shutdown threshold of
1.05V. The quiescent current drops down to 5µA. An
external Zener diode from the input supply to the ON pin
can be used to implement undervoltage lockout, as illus-
trated in Figure 7. The UV threshold is the Zener voltage
plus 1.05V.
ꢀRꢁ
ꢂꢃꢄ
ꢅꢆ
ꢀRꢁ
ꢀꢁꢂꢃ ꢄ0ꢅ
Figure 5. Recommended PCB Layout
Rev. 0
16
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LTC4381
APPLICATIONS INFORMATION
R
ꢀꢁꢀ
40mΩ
ꢀ
ꢃꢄꢀ
ꢁꢂ
ꢀꢁꢂꢃꢀꢄ ꢅꢆꢇꢈꢆꢇ
ꢉꢊꢄꢋꢈꢌꢍ ꢄꢇ ꢁ0ꢂ
ꢀꢁ
ꢀRꢁ
ꢀꢁꢀ
ꢀꢁꢂ
R
ꢀꢁ.ꢂꢃ
ꢀRꢁ
Rꢀ
ꢀ00ꢁ
ꢀ
ꢀRꢁ
ꢀꢁꢂ
ꢀꢀꢁꢂ
Rꢀ
10Ω
ꢀ
ꢀꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢃ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂ
0.ꢀꢀꢁꢂ
Rꢀ
FLT
33Ω
ꢀꢁR
ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ ꢄ0ꢅ
ꢀꢁ
ꢀ.ꢁꢂ
ꢀ
ꢀꢁR
ꢀꢀ0ꢁꢂ
Figure 6. Design Example 1: 12V/1A Application Survives 100V, 2ms OV Transient
Design Example 1
CMHZ5236B can handle 500mW indefinitely and 1W for 1
second. The V pin needs at least 4V to operate through
CC
As a design example, take an application with the follow-
ing specifications: V = 10V to 14VDC with a transient
of 100V and duration of 2ms, V
to 3V for 40ms. Maximum load of 1A.
cold crank from 12V down to 3V for 40ms. The value of
C1 can be calculated by Equation 16.
IN
≤ 20V and cold crank
OUT
–40ms
100kΩ •In (4.5)
(16)
C1=
= 0.266µF
To clamp V
to less than 20V, the required V clamp
CC
OUT
is given by Equation 13.
0.33μF is chosen to accommodate for the supply current
of the part and other conditions. With C1 = 0.33μF and
R1 = 100kΩ, high voltage transients up to 100V with a
VCC (Clamp) = VOUT – 10.5V
(13)
= 20V – 10.5V = 9.5V
pulse width of less than 2ms are filtered out at the V
pin. Longer surges are suppressed by D1.
CC
The selection of a 7.5V Zener diode for D1 limits the
voltage at the V to less than 20V during a 100V surge.
OUT
R
is chosen to produce a current into the DRN pin of
DRN
The minimum required voltage at the V pin is 4V when
CC
1mA, during the maximum overvoltage transient event
V is at 10V; the V pin input current is less than 30μA.
IN
CC
(Equation 17). V is clamped to 7.5V + 10.5V or 18V.
OUT
The maximum value for R1 to ensure proper operation is
100V – 18V
1mA
given by Equation 14.
(17)
RDRN
=
= 82kΩ
Min V – Min VCC 10V – 4V
IN
R1=
=
= 200kΩ (14)
Supply Current
30µA
82.5kΩ is chosen as the next bigger value. The GATE pin
pull-up current is 20µA typically, it takes a while to pull
the GATE pin high during input transient. So the MOSFET
We used R1 of 100k to cover all condition.
The maximum current through R1 into D1 during tran-
sients is then calculated using Equation 15.
sees a larger V initially and the worst case P√t occur
DS
100V – 7.5V
ID1 =
= 0.925mA
(15)
100kΩ
Rev. 0
17
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LTC4381
APPLICATIONS INFORMATION
when V is minimum and load current is at its maximum
where (Equation 23).
IN
when the input transient occur (Equation 18).
V
• COUT
IN
I
tINRUSH
=
=
=
P t = ILOAD • VDS
•
t
INRUSH
(18)
V
• C2
P t = (1A) • (100V – 10V) • 2ms
P t = 4.02W s
IN
IGATE(UP)
14V • 47nF
20µA
(23)
= 32.9ms
Next calculate the sense resistor (R ) value with a
current limit of greater than 1A witShNS10% tolerance
(Equation 19).
ITMR(UP) ≈ 1.5µA at power up:
32.9ms
0.22µF
45mV
1.1•1A
(19)
VTMR = 1.5µA •
≈ 0.224V,
RSNS
=
= 40.9mΩ
We will use 40mΩ, which gives a current limit of 1.25A.
Next we select C to shut off the MOSFET if the 100V
which is much lower than the 1.215V trip off threshold.
Next, we need to check to make sure that in the case of
TMR
transient is longer than 2ms at maximum load of 1A
a severe output short where V
= 0V, the power dis-
OUT
(Equation 20).
sipation in the MOSFET is also within the safe operating
area (Equation 24).
⎛
⎞
⎡
⎢
⎣
⎤
⎥
⎦
VDS
RDRN
A
V
ITMR = 0.0917
• ID •RSNS
•
−70 µA
[ ]
⎜
⎟
⎝
⎠
1.215V
80.8µA
(20)
(24)
tOC = 0.22µF •
= 3.31ms
⎛
⎞
⎡
⎢
⎣
⎤
⎥
⎦
A
V
100V –10V
82.5k
ITMR = 0.0917
•1A •0.04Ω•
−70 µA
[ ]
⎜
⎟
⎝
⎠
The power dissipation in the MOSFET is given by
Equation 25.
Next the value is calculated using Equation 21 to achieve
a fault time of greater than 2ms:
62mV
40mΩ
P t = 1.248W s
P = 14V •
= 21.7W
(25)
tTMR
VTMR
CTMR = ITMR(UP)
CTMR = 0.193µF
•
(21)
During an output overload or soft short, the voltage at the
OUT pin could stay at 3V or higher. The total overcurrent
So we choose a C
= of 0.22μF. Next, we need to make
TMR
fault time when V
= 3V is given by Equation 26.
OUT
sure that the chosen C
allow enough time to power up
TMR
1.215V
42.5µA
the output (Equation 22).
tOC = 0.22µF •
= 6.29ms
(26)
ITMR(UP) • tINRUSH
(22)
CTMR
=
The power dissipation in the MOSFET is given by
Equation 27.
VTMR
50mV
40mΩ
P = (14V – 3V) •
P t = 1.09W s
= 13.75W
(27)
These conditions are within the 10W√s safe operating
area of the MOSFET.
Rev. 0
18
For more information www.analog.com
LTC4381
APPLICATIONS INFORMATION
Design Example 2
R
is chosen to produce a current into the DRN pin of
DRN
less than 1mA, during the maximum overvoltage transient
event (Equation 29).
A second design example has the following specifications:
V
= 24V with a transient of 100V peak and a dura-
IN
DC
tion of 400ms like a load dump waveform, V
≤ 60V,
100V – 24V
OUT
RDRN
=
= 76kΩ
(29)
load of 1A.
1mA
100kΩ is chosen to give enough margin.
The MOSFET stress can be calculated using the prototyp-
There are a few methods to clamp V
to less than 60V,
OUT
we can use the LTC4381-2 by connecting SEL pin to IN to
clamp VOUT to 47V. Or we can use a LTC4381-4 and clamp
ical transient waveform shown in Figure 3 using t = 5ms,
V
to <50V. A third method is to regulate V
directly
r
CC
OUT
V
= 100V and τ = 200ms (Equation 30).
using a 56V Zener and NPN as shown in Figure 7. This
PK
method gives a slightly tighter V
of more external components.
clamp at an expense
OUT
a = VREG – V = 56.7V − 24V = 32.7V
IN
b = VPK – V = 100V − 24V = 76V
IN
Since IN can goes as high as 100V, a clamp at V pin is
CC
1/2
3
⎡
⎤
⎥
⎥
⎥
needed to limit it to <80V. Use Zener CMZ5945B as D1
1 (b− a)
tr
⎢
⎢
⎢
which limits V to <68V.
CC
b
3
(30)
P t = ILOAD
1
2
b
a
The maximum current through R1 into D1 during tran-
sients is then calculated by Equation 28.
⎛
⎝
⎞
+ τ 2a2In + 3a2 +b2 − 4ab
⎢
⎥
⎜
⎟
⎠
⎣
⎦
ꢂ00ꢃ ꢄ ꢅꢆꢃ
ꢀꢁꢂ
=
= 0.ꢈꢉꢊꢋ
(28)
ꢂ00ꢇ
Power dissipated in D1 is 22mW.
P t = 9.3W s
This is within the LTC4381 SOA limit of 10W√s.
R
ꢀꢁꢀ
40mΩ
ꢀ
ꢁꢂꢃ
ꢀ
ꢂꢃ
ꢀꢁ
ꢀꢁ
ꢀRꢁ
ꢄꢅꢆꢇꢈꢉꢊ
ꢀ00ꢁ
R
ꢀ00ꢁ
ꢀRꢁ
ꢆꢃ ꢋꢌ.ꢍꢀꢎꢏꢆ
ꢀꢁꢀ
Rꢀ
ꢀ00ꢁ
ꢀ
ꢀRꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢀꢁꢂ
Rꢀ
ꢀ
ꢀꢀ
10Ω
ꢀꢁꢂꢃꢄꢅꢆꢇꢃ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁ
FLT
Rꢀ
ꢀꢁꢂ
ꢀꢀꢁꢂ
Rꢀ
ꢀꢁ
ꢀꢁꢂ
ꢃꢄꢅꢆꢇꢈꢆꢉ
ꢃꢄꢅꢀꢆꢇꢈꢉ
ꢀꢁR
ꢀꢁꢂ
100Ω
Rꢀ
ꢀꢁꢂꢃ ꢄ0ꢅ
ꢀ0ꢁ
ꢀꢁ
ꢂꢂꢃꢄꢅꢅꢅꢆꢇꢈꢇꢉ
ꢀ
Rꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁR
ꢀ.ꢁꢂꢃ
Figure 7. Surge Stopper with Output Clamped Below 60V with 100V/1A/400ms Overvoltage Protection
Rev. 0
19
For more information www.analog.com
LTC4381
APPLICATIONS INFORMATION
Next calculate the sense resistor (RSNS) value with a current
ITMR(UP) • tINRUSH
CTMR
=
limit of greater than 1A with 20% tolerance (Equation 31).
VTMR
50mV 50mV
V •COUT
RSNS
=
=
= 41.67mΩ
(31)
IN
tINRUSH
=
ILIM
1.2A
I
INRUSH
We will use 40mΩ, which gives a current limit of 1.25A.
V •C2
IGATE(UP)
IN
=
=
The load dump waveform can be represented as an
exponentially decaying waveform with a time constant of
0.2sec (Equation 32).
(35)
24V •47nF
20µA
TMR(UP) ≈1.5µA at power up:
= 56.4ms
(32)
V = 100 V e−t/0.2 s
[ ]
I
[ ]
IN
1.5µA •56.4ms
The LTC4381 clamps the VOUT at 56.7V, which means
that VDS and ITMR drops to zero when VIN drops to
56.7V. To find the time t1 when this happen, we use
Equation 33.
VTMR
=
≈18mV
4.7µF
Next, we need to check to makes sure that in the case of
a severe output short where VOUT = 0V, the power dis-
sipation in the MOSFET is also within the safe operating
area (Equation 36).
56.7V
100V
⎛
⎞
t = −0.2s •In
= 0.113s
(33)
⎜
⎝
⎟
⎠
1
4.7µF • 1.215V
VDS can be approximated as a triangular waveform with
a peak of 100V – 56.7V or 43.3V and a time base of
0.113sec. We take half of the peak, 21.65V to calculate
the ITMR (Equation 34).
tOC
=
= 58.2ms
(36)
98.1µA
The power dissipation in MOSFET is given by Equation 37.
62mV
40mΩ
P t = 8.97W s
⎛
⎞
P = 24V •
= 37.2W
⎡
⎢
⎣
⎤
⎥
⎦
VDS
RDRN
A
V
ITMR = 0.0917
• ID •RSNS
•
−70 µA
[ ]
⎜
⎟
(37)
⎝
⎠
⎛
⎞
⎡
⎢
⎣
⎤
⎥
⎦
A
V
21.65V
100k
ITMR = 0.0917
• 1A •0.04Ω•
−70 µA
[ ]
⎜
⎟
During an output overload or soft short, the voltage at the
OUT pin could stay at 3V or higher. The total overcurrent
fault time when VOUT = 3V is given by Equation 38.
⎝
⎠
ITMR = 44µA
(34)
t1 •ITMR
VTMR
CTMR
=
=
1.215V
60.3µA
tOC = 4.7µF •
= 94.8ms
(38)
0.113s•44µA
1.215V
CTMR
The power dissipation in MOSFET is given by Equation 39.
C
TMR = 4.1µF
50mV
40mΩ
P = (24V – 3) •
= 26.25W
We shall use a 4.7μF capacitor for more margin. Next, we
need to make sure that the chosen CTMR allow enough
time to power up the output (Equation 35).
(39)
P t = 8.08W s
These conditions are within the safe operating area of
the MOSFET.
Rev. 0
20
For more information www.analog.com
LTC4381
TYPICAL APPLICATION
R
ꢀ
ꢀꢁꢀ
ꢁꢂꢃ
ꢀ
ꢁꢂ
20mΩ
ꢀꢁꢂꢃꢁꢄ
ꢀꢁ
ꢀRꢁ
ꢀꢁꢂ
ꢀꢁꢂꢃꢁꢂ ꢄꢅꢆꢇꢃꢈꢉ
ꢀꢁ ꢂꢃ.ꢄꢅ
R
ꢀRꢁ
ꢀ0ꢁ
ꢂꢃ
Rꢀ
ꢀ00ꢁ
ꢀꢁꢀ
ꢀ0ꢁ
ꢀRꢁ
ꢀꢁ
ꢀ
ꢀꢁꢂ
ꢁꢂꢃ
ꢀ.ꢁꢂ
ꢀ
ꢁꢁ
Rꢀ
ꢀ00ꢁꢂ
ꢀꢀꢁꢂꢃꢂꢃꢄ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈ
10Ω
ꢀꢁ
ꢀꢀ0ꢁꢂ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
FLT
Rꢀ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢂ
ꢀꢀꢁ
Rꢀ
33Ω
ꢀꢁꢂꢃꢄꢅꢅꢆ
ꢀꢁ ꢂ ꢃ0.ꢄꢁ
ꢀꢁR
ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ ꢄ0ꢂ
ꢀ
ꢁꢂR
Rꢀ
ꢀꢁ0ꢂ
ꢀꢀ0ꢁꢂ
Figure 8. 12V Hot Swap Controller with Input UV Detection with 60V/2A/3.5ms Overvoltage Protection
R
ꢀ
ꢀꢁꢀ
ꢁꢂꢃ
40mΩ
ꢀꢁꢂꢃꢄꢅ
ꢀ
ꢀRꢁ
ꢀꢁꢀ
ꢀꢁꢂ
ꢀꢁ
ꢁꢂ
ꢀꢁꢂꢃꢁꢂ ꢄꢅꢆꢇꢃꢈꢉ
ꢀꢁ ꢂ0.ꢃꢄ
R
ꢀRꢁ
ꢃꢄꢀ
ꢅꢆ00ꢀ ꢀ
ꢀ00ꢁ
ꢀ
ꢉ
Rꢀ
ꢀꢁꢂ
ꢇꢈ
ꢀRꢁ
ꢀ0ꢁ
ꢀꢀꢁꢂ
Rꢀ
ꢀ
10Ω
ꢀꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢃ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢀ0ꢁꢂ
ꢀꢁꢂ
Rꢀ
FLT
ꢀꢁ
33Ω
ꢀ0ꢁ
ꢀꢁR
ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢅꢆꢇ
ꢀꢁꢂꢃ ꢄ0ꢅ
ꢀ
ꢀꢁR
ꢀꢁ0ꢂꢃ
Figure 9. 28V Surge Stopper with Output Clamped to Below 40V with 100V/1A/6ms Overvoltage Protection
Rev. 0
21
For more information www.analog.com
LTC4381
TYPICAL APPLICATION
R
ꢀꢁꢀ
ꢀꢁ
ꢀ
ꢁꢂꢃ
40mΩ
ꢀ
ꢀꢁ
ꢀRꢁRꢂꢃ0ꢄ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁ ꢂꢃ.ꢄꢅꢆꢇꢀ
ꢀꢁ
ꢀRꢁ
ꢀ00ꢁ
ꢀꢁ
R
ꢀRꢁ
ꢀꢁ
ꢀꢁꢂꢃ0ꢄ
ꢀꢁ0ꢂ
Rꢀ
ꢀ0ꢁ
ꢀꢁꢀ
Rꢀ
ꢀRꢁ
ꢀꢁ0ꢂ
ꢀ
ꢀꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀꢀ
Rꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈ
10Ω
ꢀꢁ
ꢀꢁ
ꢀ00ꢁꢂ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂꢃ
Rꢀ
ꢀꢁꢂ
ꢀꢁꢂꢀꢂꢃ
ꢀ0ꢁ
ꢀꢁꢂꢃꢄꢅꢆꢆꢇ
ꢀꢁꢂꢃ
Rꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁΩ
FLT
Rꢀ
ꢀꢁꢂꢀꢂꢃ
ꢀꢁR
ꢀꢁꢂ
33Ω
ꢀꢁꢂꢃ ꢄꢃ0
ꢀ
ꢀꢁ
ꢀꢁR
ꢀꢁꢂꢃ
ꢀꢀ0ꢁꢂ
Figure 10. –60V Reverse Battery Protection with 100V/1A/3ms Overvoltage Protection
Rev. 0
22
For more information www.analog.com
LTC4381
PACKAGE DESCRIPTION
DKE Package
32-Lead Plastic DFN (7mm × 5mm)
ꢚReꢪeꢫeꢬꢭe ꢔꢄꢌ ꢇꢉꢋ ꢮ 0ꢀꢕ0ꢥꢕꢁꢠꢥꢦ Rev ꢈꢜ
ꢑꢊꢂ ꢁ ꢂꢃꢄꢌꢘ
R ꢡ 0.ꢙ0 ꢄꢢꢑ ꢃR
0.ꢙꢀ × ꢧꢀ° ꢌꢘꢈꢎꢍꢅR
0.ꢠꢀ ± 0.0ꢀ
ꢀ.00 ±0.ꢁ0
0.00 ꢣ 0.0ꢀ
ꢙꢖ
ꢑꢊꢂ ꢁ
ꢄꢃꢑ ꢎꢈRꢒ
ꢚꢏꢅꢅ ꢂꢃꢄꢅ ꢛꢜ
ꢁ
ꢖ
ꢙꢁ
0.ꢁꢠ ±0.0ꢀ
ꢛ.ꢙ0 ±0.ꢁ0
ꢠ.00 ±0.ꢁ0
ꢛ.0 Rꢅꢍ
0.ꢧ0 ꢝꢏꢌ
ꢖ.ꢦꢧ ±0.ꢁ0
R ꢡ 0.ꢁꢖꢀ
ꢄꢢꢑ
0.ꢖ00 Rꢅꢍ
0.ꢠꢀ Rꢅꢍ
0.ꢀꢁ Rꢅꢍ
0.ꢧ0 ±0.ꢁ0
ꢝꢃꢄꢄꢃꢎ ꢗꢊꢅꢉꢞꢅꢟꢑꢃꢏꢅꢇ ꢑꢈꢇ
ꢚꢇꢒꢅꢙꢖꢜ ꢤꢍꢂ 0ꢥꢁꢦ Rꢅꢗ ꢈ
ꢂꢃꢄꢅꢆ
ꢁ. ꢇRꢈꢉꢊꢂꢋ ꢌꢃꢂꢍꢃRꢎꢏ ꢄꢃ ꢐꢅꢇꢅꢌ ꢑꢈꢌꢒꢈꢋꢅ
ꢃꢓꢄꢔꢊꢂꢅ ꢎ0ꢕꢖꢖ0 ꢗꢈRꢊꢈꢄꢊꢃꢂ ꢉꢘꢒꢇ
ꢖ. ꢇRꢈꢉꢊꢂꢋ ꢂꢃꢄ ꢄꢃ ꢏꢌꢈꢔꢅ
ꢧ. ꢇꢊꢎꢅꢂꢏꢊꢃꢂꢏ ꢃꢍ ꢅꢟꢑꢃꢏꢅꢇ ꢑꢈꢇ ꢃꢂ ꢝꢃꢄꢄꢃꢎ ꢃꢍ ꢑꢈꢌꢒꢈꢋꢅ ꢇꢃ ꢂꢃꢄ ꢊꢂꢌꢔꢓꢇꢅ
ꢎꢃꢔꢇ ꢍꢔꢈꢏꢘ. ꢎꢃꢔꢇ ꢍꢔꢈꢏꢘꢨ ꢊꢍ ꢑRꢅꢏꢅꢂꢄꢨ ꢏꢘꢈꢔꢔ ꢂꢃꢄ ꢅꢟꢌꢅꢅꢇ 0.ꢖ0ꢩꢩ ꢃꢂ ꢈꢂꢢ ꢏꢊꢇꢅ
ꢀ. ꢅꢟꢑꢃꢏꢅꢇ ꢑꢈꢇ ꢏꢘꢈꢔꢔ ꢝꢅ ꢏꢃꢔꢇꢅR ꢑꢔꢈꢄꢅꢇ
ꢛ. ꢏꢘꢈꢇꢅꢇ ꢈRꢅꢈ ꢊꢏ ꢃꢂꢔꢢ ꢈ RꢅꢍꢅRꢅꢂꢌꢅ ꢍꢃR ꢑꢊꢂ ꢁ ꢔꢃꢌꢈꢄꢊꢃꢂ
ꢃꢂ ꢄꢘꢅ ꢄꢃꢑ ꢈꢂꢇ ꢝꢃꢄꢄꢃꢎ ꢃꢍ ꢑꢈꢌꢒꢈꢋꢅ
ꢙ. ꢈꢔꢔ ꢇꢊꢎꢅꢂꢏꢊꢃꢂꢏ ꢈRꢅ ꢊꢂ ꢎꢊꢔꢔꢊꢎꢅꢄꢅRꢏ
ꢛ.00 Rꢅꢍ
0.ꢠ0 ±0.0ꢀ
ꢀ.ꢀ0 ±0.0ꢀ
ꢧ.ꢁ0 ±0.0ꢀ
ꢖ.ꢦꢧ ±0.0ꢀ
ꢛ.ꢙ0 ±0.0ꢀ
ꢑꢈꢌꢒꢈꢋꢅ
ꢃꢓꢄꢔꢊꢂꢅ
0.ꢁꢠ ±0.0ꢀ
0.ꢧ0 ꢝꢏꢌ
Rꢅꢌꢃꢎꢎꢅꢂꢇꢅꢇ ꢏꢃꢔꢇꢅR ꢑꢈꢇ ꢔꢈꢢꢃꢓꢄ
ꢈꢑꢑꢔꢢ ꢏꢃꢔꢇꢅR ꢎꢈꢏꢒ ꢄꢃ ꢈRꢅꢈꢏ ꢄꢘꢈꢄ ꢈRꢅ ꢂꢃꢄ ꢏꢃꢔꢇꢅRꢅꢇ
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
23
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LTC4381
TYPICAL APPLICATION
R
ꢀꢁꢀ
ꢀ
4mΩ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀRꢁ
ꢀꢁꢀ
R
ꢀꢁꢂ
ꢀRꢁ
ꢀ0ꢁ
ꢀ00ꢁ
ꢀ
ꢀꢁ
ꢀꢁꢂ
Rꢀ
ꢀ0ꢁ
ꢀRꢁ
ꢀꢀꢁ
ꢀꢀ0ꢁꢂ
ꢀꢁꢂꢃꢄꢀꢅꢅ
ꢀꢁꢂ
Rꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢃ
ꢁꢁ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢆꢆꢇ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁ
FLT
ꢀꢁR
ꢀꢁꢂ
ꢀꢁꢂꢃ ꢄꢃꢃ
Rꢀ
ꢀꢁ0ꢂ
ꢀ
ꢀꢁR
*MINIMUM C
IS 10μF
OUT
ꢀꢁ0ꢂꢃ
Figure 11. 48V, 10A eFuse
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LT4356
Surge Stopper with Current Limit
Ideal Diode Controller
4V to 80V Operation; 100V Protection; DFN-12, MSOP-10 and SO-16 Packages
4V to 80V Operation, –40V Input Protection, DFN-8 and MSOP-8 Packages
2.5V to 5.5V Operation, 80V Protection, TSOT-8 and DFN-8 Packages
4V to 80V Operation; >100V Protection; DFN-12, MSOP-12 and SO-16 Packages
LTC4359
LTC4361
LT4363
Overvoltage/Overcurrent Protection Controller
Surge Stopper with Current Limit
LTC4364
Surge Stopper with Ideal Diode
4V to 80V Operation; –40V to >100V Protection; DFN-14, MSOP-16 and
SO-16 Packages
LTC4365
LTC4366
LTC4367
LTC7860
LTC4380
OV, UV and Reverse Input Protection Controller
High Voltage Surge Stopper
2.5V to 34V Operation, –40V to 60V Protection, DFN-8 and TSOT-8 Packages
9V to >500V Operation, Floating Topology, TSOT-8 and DFN-8 Packages
2.5V to 60V Operation, –40V to 100V Protection, DFN-8 and MSOP-8 Packages
3.5V to 60V Operation, >100V Protection, MSOPE-12 Package
OV, UV and Reverse Input Protection Controller
Switching Surge Stopper
Low Quiescent Current Surge Stopper
4V to 72V Operation, –60V to >100V Protection, DFN-10 and MSOP-10 Packages
Rev. 0
04/21
www.analog.com
24
ANALOG DEVICES, INC. 2021
相关型号：
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Linear
LTC4400-1ES6#TR
LTC4400 - RF Power Controllers with 450kHz Loop BW and 45dB Dynamic Range; Package: SOT; Pins: 6; Temperature Range: -40°C to 85°C
Linear
LTC4400-1ES6#TRM
LTC4400 - RF Power Controllers with 450kHz Loop BW and 45dB Dynamic Range; Package: SOT; Pins: 6; Temperature Range: -40°C to 85°C
Linear
LTC4400-1ES6#TRMPBF
LTC4400 - RF Power Controllers with 450kHz Loop BW and 45dB Dynamic Range; Package: SOT; Pins: 6; Temperature Range: -40°C to 85°C
Linear
LTC4400-2EMS8#PBF
LTC4400 - RF Power Controllers with 450kHz Loop BW and 45dB Dynamic Range; Package: MSOP; Pins: 8; Temperature Range: -40°C to 85°C
Linear
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