LTC5594_技术文档

LTC5594

300MHz to 9GHz High Linearity

I/Q Demodulator with

Wideband IF Amplifier

DESCRIPTION

FEATURES

TheLTC^®5594isadirectconversionquadraturedemodula-

tor optimized for high linearity zero-IF and low-IF receiver

applications in the 300MHz to 9GHz frequency range.

The very wide IF bandwidth of more than 1GHz makes

the LTC5594 particularly suited for demodulation of very

wideband signals, especially in 5G fronthaul/backhaul

receiver applications. The outstanding dynamic range of

the LTC5594 makes the device suitable for demanding

infrastructure direct conversion applications. Proprietary

technology inside the LTC5594 provides the capability

to optimize OIP2 to 65dBm, and achieve image rejection

better than 60dB. The DC offset control function allows

nulling of the DC offset at the A/D converter input, thereby

optimizingthedynamicrangeoftruezero-IFreceiversthat

use DC-coupled IF signal paths. The wideband RF and LO

input ports make it possible to cover all the major wireless

infrastructure frequency bands using a single device. The

IFoutputsoftheLTC5594aredesignedtointerfacedirectly

with most common A/D converter input interfaces. The

highOIP3andhighconversiongainofthedeviceeliminate

the need for additional amplifiers in the IF signal path.

All registered trademarks and trademarks are the property of their respective owners.

n

True Zero IF Demodulation

n

Wideband Input Matched from 500MHz to 9GHz

n

Wide IF Bandwidth: DC to 1GHz (1dB Flatness)

n

37dB Image Rejection, Adjustable to 60dB

n

High Total OIP3: 37dBm at 5.8GHz

n

58dBm OIP2 at 5.8GHz, Adjustable to 65dBm

n

Max Power Conversion Gain: 9.2dB at 5.8GHz

n

Single-Ended RF Input with On-Chip Transformer

n

User Adjustable DC Offset Null

n

Serial Interface

n

IF Amplifier Gain Adjustable in Eight Steps

IF Amplifier Shutdown/Enable

Low Power Shutdown Mode

n

Operating Temperature Range (T ): –40°C to 105°C

C

n

32-Lead 5mm × 5mm QFN Package

APPLICATIONS

n

5G Base Station Fronthaul/Backhaul Receivers

n

Military and Satellite Receivers

n

Point-to-Point Broadband Radios

High Linearity Direct Conversion I/Q SDR

Test Instrumentation

DPD Receivers

n

Gain, OIP3, and OIP2 vs

Temperature (T_C) (Unoptimized)

TYPICAL APPLICATION

Direct Conversion I/Q Receiver

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Rev A

1

Document Feedback

For more information www.analog.com

LTC5594

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Note 1)

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V

Supply Voltage (Note 23) ................... –0.3V to 5.5V

DD

CC

OV , SDO Voltage (Note 20) ................... –0.3V to 3.8V

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RF DC Voltage..............................................1.5V to 2.0V

LOP, LOM DC Voltage ..................................2.1V to 2.8V

IFIM, IFIP, IFQP, IFQM DC Voltage............. –0.3V to 3.5V

AIM, AIP, AQM, AQP

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DC Voltage........................... V – 1.7V to V – 1.2V

CC

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MIM, MIP, MQM, MQP

DC Voltage........................... V – 1.7V to V – 1.2V

Voltage on Any Other Pin.......................... –0.3V to 5.5V

LOP, LOM, RF Input Power (Note 19).................+20dBm

Output Short Circuit Duration (Notes 16, 19)... Indefinite

Maximum Junction Temperature (T

Case Operating Temperature

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CC

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)............. 150°C

JMAX

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Range (T )......................................... –40°C to 105°C

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C

Storage Temperature Range .................. –65°C to 150°C

ORDER INFORMATION

LEAD FREE FINISH

TAPE AND REEL

PART MARKING

PACKAGE DESCRIPTION

TEMPERATURE RANGE

–40°C to 105°C

LTC5594IUH#PBF

LTC5594IUH#TRPBF

5594

32-Lead (5mm × 5mm) Plastic QFN

Consult ADI Marketing for parts specified with wider operating temperature ranges.

Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.

Rev A

2

For more information www.analog.com

LTC5594

ELECTRICAL CHARACTERISTICS ^T_C^{= 25°C, V}_CC= 5V, OV_DD= EN = CSB = 3.3V, SDI = SCK = AMPD = 0V,

V_CM= 0.9V, P_IF= 1.5dBm (–1.5dBm/tone for 2-tone tests), P_LO= 6dBm, all registers at default values, and all parameters listed for

combined performance of demodulator and amplifier unless otherwise noted. (Notes 2, 3, 6, 9, 21, 24)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

0.3 to 9.0

1.0

MAX

UNITS

GHz

f

RF Input Frequency Range

LO Input Frequency Range

IF Output Bandwidth

(Note 12)

RF(RANGE)

LO(RANGE)

(Note 12)

GHz

BW

–1dB Corner Frequency (Note 22)

GHz

IF

RL

RF Input Return Loss (Note 5)

f

= 300MHz to 500MHz

= 500MHz to 9.0GHz

>10

dB

RF

RL

LO Input Return Loss

LO Input Power Range

f

= 300MHz to 9.0GHz

>10

dB

LO

P

(Note 12)

–6 to 12

dBm

LO(RANGE)

G

P

Power Conversion Gain

AMPG = 0x06,

LOAD

f

RF

f

RF

f

RF

f

RF

f

RF

f

RF

= 400MHz

11.5

12.3

11.0

9.2

dB

= 1900MHz

= 3500MHz

= 5800MHz

= 7200MHz

= 8500MHz

R

= 100Ω Differential (Note 8)

7.0

5.2

NF

Noise Figure, Double Side Band (Note 4)

f

= 400MHz

15.7

16.0

17.9

21.2

23.5

28.6

dB

RF

= 1900MHz

= 3500MHz

= 5800MHz

= 7200MHz

= 8500MHz

Noise Figure Under Blocking Conditions

f

= 400MHz

16.7

17.0

18.9

22.2

24.5

29.6

dB

BLOCKING

RF

Double Side Band, P ,

= 1.5dBm

= 1900MHz

= 3500MHz

= 5800MHz

= 7200MHz

= 8500MHz

IF BLOCKER

(Note 7)

OIP3

OIP2

Output 3rd Order Intercept

Unadjusted/Adjusted

f

= 400MHz

40/44

37/43

37/42

37/40

33/38

33/35

dBm

RF

= 1900MHz

= 3500MHz

= 5800MHz

= 7200MHz

= 8500MHz

Output 2nd Order Intercept

Unadjusted/Adjusted

f

= 400MHz

75/80

68/75

68/70

58/65

48/55

43/48

dBm

RF

= 1900MHz

= 3500MHz

= 5800MHz

= 7200MHz

= 8500MHz

IIP3

Input 3rd Order Intercept without Amplifier

Unadjusted

f

= 400MHz

30

26

27

24

27

dBm

DEMOD

RF

= 1900MHz

= 3500MHz

= 5800MHz

= 7200MHz

= 8500MHz

OIP3

Output 3rd Order Intercept, Amplifier Only

(Note 17)

f

= 10MHz

42

41

38

37

35

30

dBm

AMP

IF

= 100MHz

= 200MHz

= 300MHz

= 500MHz

= 1000MHz

Rev A

3

For more information www.analog.com

LTC5594

ELECTRICAL CHARACTERISTICS ^T_C^{= 25°C, V}_CC= 5V, OV_DD= EN = CSB = 3.3V, SDI = SCK = AMPD = 0V,

V_CM= 0.9V, P_IF= 1.5dBm (–1.5dBm/tone for 2-tone tests), P_LO= 6dBm, all registers at default values, and all parameters listed for

combined performance of demodulator and amplifier unless otherwise noted. (Notes 2, 3, 6, 9, 21, 24)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

HD2

2nd Order Harmonic Distortion

Unadjusted/Adjusted

f

= 400MHz

–65

–64

–60

–56

–50

–46

dBc

RF

= 1900MHz

= 3500MHz

= 5800MHz

= 7200MHz

= 8500MHz

HD3

3rd Order Harmonic Distortion

Unadjusted/Adjusted

f

= 400MHz

–82

–80

–76

–70

–65

–68

dBc

RF

= 1900MHz

= 3500MHz

= 5800MHz

= 7200MHz

= 8500MHz

P1dB

Output 1dB Compression Point

DC Offset, Unadjusted (Note 13)

f

= 400MHz

13.2

dBm

RF

= 1900MHz

= 3500MHz

= 5800MHz

= 7200MHz

= 8500MHz

DC

f

= 400MHz

19

17

–26

–63

–19

mV

OFFSET

RF

= 1900MHz

= 3500MHz

= 5800MHz

= 7200MHz

= 8500MHz

DC

∆G

DC Offset Adjustment Range

DC Offset Step Size

DCOI, DCOQ = 0x00 to 0xFF

–75 to 75

640

mV

µV

OFF(RANGE)

OFF(STEP)

I/Q Gain Mismatch, Unadjusted

f

= 400MHz

0.05

0.06

0.07

0.44

dB

RF

= 1900MHz

= 3500MHz

= 5800MHz

= 7200MHz

= 8500MHz

∆G

I/Q Gain Mismatch Adjustment Range

I/Q Gain Mismatch Adjustment Step Size

I/Q Phase Mismatch, Unadjusted

GERR = 0x00 to 0x3F

–0.5 to 0.5

0.016

dB

(RANGE)

∆G(STEP)

∆φ

f

= 400MHz

0.9

1.1

3.1

1.6

1.1

1.0

Deg

RF

= 1900MHz

= 3500MHz

= 5800MHz

= 7200MHz

= 8500MHz

∆φ

I/Q Phase Mismatch Adjustment Range

I/Q Phase Mismatch Adjustment Step Size

PHA = 0x000 to 0x1FF

–2.5 to 2.5

0.05

Deg

(RANGE)

(STEP)

IRR

Image Rejection Ratio

Unadjusted/Adjusted

(Note 10)

f

= 400MHz

43/70

42/65

33/65

37/60

40/60

33/60

dB

RF

= 1900MHz

= 3500MHz

= 5800MHz

= 7200MHz

= 8500MHz

Rev A

4

For more information www.analog.com

LTC5594

ELECTRICAL CHARACTERISTICS ^T_C^{= 25°C, V}_CC= 5V, OV_DD= EN = CSB = 3.3V, SDI = SCK = AMPD = 0V,

V_CM= 0.9V, P_IF= 1.5dBm (–1.5dBm/tone for 2-tone tests), P_LO= 6dBm, all registers at default values, and all parameters listed for

combined performance of demodulator and amplifier unless otherwise noted. (Notes 2, 3, 6, 9, 21, 24)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

LR

LEAK

LO to RF Leakage

f

= 400MHz

–67

–65

–56

–52

–50

–55

dBm

LO

= 1900MHz

= 3500MHz

= 5800MHz

= 7200MHz

= 8500MHz

RL

ISO

RF to LO Isolation

f

= 400MHz

69

57

66

55

57

53

dB

RF

= 1900MHz

= 3500MHz

= 5800MHz

= 7200MHz

= 8500MHz

RI

RF to IF Isolation (Note 18)

LO to IF Isolation (Note 18)

f

= 400MHz

70

48

59

48

40

43

dB

ISO

RF

= 1900MHz

= 3500MHz

= 5800MHz

= 7200MHz

= 8500MHz

LI

f

= 400MHz

40

29

38

36

33

35

dB

ISO

LO

= 1900MHz

= 3500MHz

= 5800MHz

= 7200MHz

= 8500MHz

Power Supply and Other Parameters

V

Supply Voltage

4.75

450

230

5.0

5.25

500

270

900

V

mA

μA

CC

I

t

Supply Current

470

CC

Mixer Supply Current

Amplifier Disabled, AMPD = 3.3V

EN < 0.3V

250

CC(MIX)

CC(OFF)

CC(SLEEP)

ON

Shutdown Current

20

Sleep Current

EDEM = EDC = EADJ = EAMP = 0

EN Transition from Logic Low to High

EN Transition from Logic High to Low

4

mA

µs

Turn-On Time (Note 14)

Turn-Off Time (Note 15)

Digital I/O Supply Voltage

EN Input High Voltage (On)

EN Input Low Voltage (Off)

EN Pin Input Current

1

µs

OFF

OV

1.2 to 3.3

V

DD

V

0.7 • OV

V

DH

DD

0.3 • OV

V

DL

DD

I

EN

EN = 3.3V

41

0.774

–1.52

100||0.6

3.6

μA

V

TEMP Diode Bias Voltage

TEMP Diode Temperature Slope

Mixer Output Impedance

Mixer Output DC Voltage

Amplifier Input Impedance

Amplifier DC Input Voltage

Amplifier Output Impedance

Amplifier DC Output Short Circuit Current

I

= 100μA into TEMP Pin, T = 25°C

V

TEMP

J

= 100μA into TEMP Pin

mV/°C

Ω||pF

V

Z

Differential

MIX(OUT)

V

Common Mode

Differential

MIX(OUT)

Z

200||0.2

3.6

Ω||pF

V

AMP(IN)

V

Common Mode

Differential

AMP(IN)

AMP(OUT)

AMP(SC)

Z

4||0.5

100

kΩ||pF

mA

V

I

IFIP = IFIM = IFQP = IFQM = 0V

V

Pin Voltage Range (Notes 11, 12)

CM

0.5 to 2.0

CM(RANGE)

Rev A

5

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LTC5594

ELECTRICAL CHARACTERISTICS ^T_C^{= 25°C, V}_CC= 5V, OV_DD= EN = CSB = 3.3V, SDI = SCK = AMPD = 0V,

V_CM= 0.9V, P_IF= 1.5dBm (–1.5dBm/tone for 2-tone tests), P_LO= 6dBm, all registers at default values, and all parameters listed for

combined performance of demodulator and amplifier unless otherwise noted. (Notes 2, 3, 6, 9, 21, 24)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Serial Interface Pins

V

High Level Input Voltage

Low Level Input Voltage

Input Hysteresis Voltage

Input Current

CSB, SDI, SCK

0.7 • OV

V

IH

DD

CSB, SDI, SCK

0.3 • OV

10

IL

DD

CSB, SDI, SCK

250

mV

μA

V

IHYS

IN(SER)

I

CSB, SDI, SCK (Note 19)

SDO, 10mA Current Sink

SDO, 10mA Current Source

V

OH

V

OL

High Level Output Voltage

Low Level Output Voltage

0.7 • OV

DD

0.3 • OV

V

DD

Serial Interface Timing

t

SCK High Time

25

10

6

ns

CKH

CKL

CSS

CSH

DS

SCK Low Time

CSB Setup Time

CSB High Time

SDI to SCK Setup Time

SDI to SCK Hold Time

SCK to SDO Time

6

DH

To V /V /Hi-Z with 30pF Load

16

DO

IH IL

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may

cause permanent damage to the device. Exposure to any Absolute Maximum

Rating condition for extended periods may affect device reliability and

Note 9: Input P adjusted so that P = –1.5dBm/tone at the amplifier

RF IF

output. RF tone spacing set at 4MHz with high side LO, f = f + 30MHz.

LO

RF

Note 10: Image rejection is measured at f = 12MHz and calculated from

IF

lifetime. The voltage on all pins should not exceed V + 0.3V or be less than

CC

the measured gain error and phase error.

–0.3V, otherwise damage to the ESD diodes may occur.

Note 2: Tests are performed with the test circuit of Figure 1.

Note 3: The LTC5594 is guaranteed to be functional over the –40°C to

105°C case temperature operating range.

Note 4: DSB noise figure is measured at the baseband frequency of 15MHz

with a small-signal noise source without any filtering on the RF input and

no other RF signal applied.

Note 5: A 6.8pF shunt capacitor is used on the RF inputs for 300MHz to

500MHz. 0.2pF is used for 500MHz to 9GHz.

Note 11: If the V pin is left floating, it will self bias to a nominal 0.9V.

CM

Note 12: This is the recommended operating range, operation outside the

listed range is possible with degraded performance to some parameters.

Note 13: DC offset measured differentially between IFIP and IFIM and

between IFQP and IFQM. The reported value is the mean of the absolute

values of the characterization data distribution.

Note 14: IF amplitude is within 10% of final value.

Note 15: IF amplitude is at least 30dB down from its on state.

Note 16: IF outputs shorted to ground.

Note 6: The differential amplifier outputs (IFIP, IFIM and IFQP, IFQM) are

combined using a 180° combiner.

Note 17: IF tone spacing set at 1MHz.

Note 18: Worst case isolation measured to each IF single-ended port.

Note 19: Guaranteed by design characterization, not tested in production.

Note 20: The voltage on the OV pin must never exceed V + 0.3V,

Note 7: Noise figure under blocking conditions (NF

) is measured

BLOCKING

at an output frequency of 60MHz with RF input signal at f + 1MHz. Both

LO

RF and LO input signals are appropriately filtered, as well as the baseband

output.

DD

CC

otherwise damage to the ESD diodes may occur.

Note 21: Refer to Appendix for register definition and default values.

Note 22: Mixer outputs directly connected to amplifier inputs. Bandwidth

measured on single amplifier output, I or Q.

Note 8: Power conversion gain is defined from the RF input to the I or Q

output. Power conversion gain is measured with a 100Ω differential load

impedance on the I and Q outputs. Any losses due to IF combiner and

spectrum analyzer termination have been de-embedded.

Note 23: V should be ramped up slower than 5V/ms to prevent damage.

CC

Note 24: P measured at amplifier differential outputs.

IF

Rev A

6

For more information www.analog.com

LTC5594

V_CC= 5V, EN = 3.3V, T_C= 25°C, P_LO= 6dBm,

TYPICAL PERFORMANCE CHARACTERISTICS

HSLO, RF tone spacing = 4MHz, f_IF= 30MHz, P_IF= –1.5dBm per tone, and register defaults. DC Blocks, 50Ω terminations, and

MACOM H9 180° combiner at amplifier outputs de-embedded from measurement unless otherwise noted. Test circuit shown in

Figure 1 with 1GHz interstage filter.

TEMP Diode Voltage

vs Junction Temperature (T_J)

Noise Figure and Conversion

Gain vs Temperature (T_C)

Supply Current vs Supply Voltage

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A

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ꢀ_ꢀꢀ ꢁꢂꢃꢄ

ꢀ_ꢀꢀ ꢁꢂꢃꢄꢅ

ꢀꢁ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄ

ꢀAꢁꢂ

ꢀ

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ꢀꢁꢂꢃ

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RA

R

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ꢀꢀꢁꢂ ꢃꢄꢅ

Noise Figure and Conversion

Gain vs LO Power

Gain vs IF Frequency for Various

Fixed LO Frequencies

Gain vs IF Frequency for Various

Fixed LO Frequencies

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Rꢀ ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ

ꢀꢁ ꢁRꢂꢃꢄꢂꢅꢆꢇ ꢈꢉꢊꢋꢌ

ꢀꢀꢁꢂ ꢃꢄꢂ

ꢀꢀꢁꢂ ꢃꢄꢀ

ꢀꢀꢁꢂ ꢃꢄꢅ

OIP3 vs RF Frequency for Various

Fixed IF Frequencies

OIP3 vs RF Frequency for Various

Fixed IF Frequencies

Gain vs AMPG Register Value

ꢀꢁ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁꢂꢃ ꢄꢅꢃꢆ ꢁꢇꢂꢈRꢉꢂAꢅꢈ ꢊꢁꢋꢂꢈR

ꢀꢁꢂꢃ

ꢀꢁꢀꢂ

ꢀꢁ

ꢀ

ꢀꢁ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀꢁꢂ

ꢀ_Rꢀꢀ ꢁꢂꢃꢃꢄꢅꢆ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ

ꢀ

ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ

ꢀꢁ ꢁRꢂꢃꢄꢂꢅꢆꢇ ꢈꢉꢊꢋꢌ

Rꢀ ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ

ꢀꢀꢁꢂ ꢃꢄꢅ

ꢀꢀꢁꢂ ꢃꢄꢁ

Rev A

7

For more information www.analog.com

LTC5594

V_CC= 5V, EN = 3.3V, T_C= 25°C, P_LO= 6dBm,

TYPICAL PERFORMANCE CHARACTERISTICS

HSLO, RF tone spacing = 4MHz, f_IF= 30MHz, P_IF= –1.5dBm per tone, and register defaults. DC Blocks, 50Ω terminations, and

MACOM H9 180° combiner at amplifier outputs de-embedded from measurement unless otherwise noted. Test circuit shown in

Figure 1 with 1GHz interstage filter.

OIP3 vs Temperature (T_C)

OIP3 vs Supply Voltage (V_CC

)

OIP3 vs LO Power

ꢀꢁ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁ ꢂꢃ

ꢀꢁ ꢂꢃꢄꢂꢅ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁ ꢂꢃ

ꢀꢁ ꢂꢃꢄꢂꢅ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ

Rꢀ ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ

ꢀꢀꢁꢂ ꢃꢄꢅ

ꢀꢀꢁꢂ ꢃꢄꢄ

Optimized OIP3 vs

Temperature (T_C)

OIP3 vs Temperature (T_C) and

Register Value

OIP3 vs IF Tone Power

ꢀꢁ

ꢀ

ꢀꢁ

ꢀꢁꢂꢃAꢄꢄꢅꢆ

ꢀ_Rꢀꢀ ꢁꢂꢃꢃꢄꢅꢆ

ꢀꢁꢂꢃꢄꢃꢅꢆꢇ Aꢂ ꢈꢉꢊꢋ

ꢀꢁ

ꢀ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁꢂꢀꢃꢄ ꢅꢆꢇꢈꢉ

ꢀꢁꢂꢀꢃꢄ ꢅꢆꢇꢈ

ꢀꢁꢂꢀꢃꢄ ꢅꢆꢇꢈꢉ

ꢀꢁꢂꢀꢃꢄ ꢅꢆꢇꢈ

ꢀꢁꢂꢀꢃꢄ ꢅꢆꢇꢈꢉ

ꢀꢁ ꢂꢃꢄꢅꢆꢇꢈ

ꢀꢁ ꢂꢃꢄꢅꢆꢇ

ꢀꢁ ꢂꢃꢄꢅꢆꢇꢈ

ꢀꢁ ꢂꢃꢄꢅꢆꢇ

ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢀꢁ ꢀꢁꢂ

Rꢀ ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ

RꢀꢁꢂꢃꢄꢀR ꢅAꢆꢇꢀ ꢈꢂꢉꢄꢀꢁꢀRꢊ

ꢀꢀꢁꢂ ꢃꢄꢅ

ꢀꢀꢁꢂ ꢃꢄꢂ

ꢀꢀꢁꢂ ꢃꢄꢀ

OIP3 vs Temperature (T_C) and

Register Value

OIP3 vs IP3CC Register Value

OIP3 vs IP3IC Register Value

ꢀꢁ

ꢀ

ꢀꢁ

ꢀꢁ ꢂ

ꢀꢁꢂꢃAꢄꢄꢅꢆ

ꢀ_Rꢀꢀ ꢁꢂꢃꢃꢄꢅꢆ

ꢀꢁ ꢂ

ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢉꢊ

ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢉ

ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢉꢊ

ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢉ

ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢉꢊ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢀꢁ ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ

RꢀꢁꢂꢃꢄꢀR ꢅAꢆꢇꢀ ꢈꢂꢉꢄꢀꢁꢀRꢊ

Rꢀ ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ

ꢀꢀꢁꢂ ꢃꢄꢅ

Rev A

8

For more information www.analog.com

LTC5594

V_CC= 5V, EN = 3.3V, T_C= 25°C, P_LO= 6dBm,

TYPICAL PERFORMANCE CHARACTERISTICS

HSLO, RF tone spacing = 4MHz, f_IF= 30MHz, P_IF= –1.5dBm per tone, and register defaults. DC Blocks, 50Ω terminations, and

MACOM H9 180° combiner at amplifier outputs de-embedded from measurement unless otherwise noted. Test circuit shown in

Figure 1 with 1GHz interstage filter.

OIP3 vs LVCM Register Value

OIP2 vs Temperature (T_C)

OIP2 vs LO Power

ꢀꢁ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ ꢂ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ

Rꢀ ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ

ꢀꢀꢁꢂ ꢃꢄꢁ

ꢀꢀꢁꢂ ꢃꢄꢅ

Optimized OIP2 vs

Temperature (T_C)

OIP2 vs Temperature (T_C) and

Register Value

OIP2 vs Temperature (T_C) and

Register Value

ꢀꢁꢁ

ꢀꢁ

ꢀ

ꢀꢁꢁ

ꢀꢁ

ꢀ

ꢀꢁꢁ

ꢀꢁ

ꢀ

ꢀꢁꢂꢃꢄꢃꢅꢆꢇ Aꢂ ꢈꢉꢊꢋ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁꢂꢀꢃꢄ ꢅꢆꢇꢈꢉ

ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢉꢊ

ꢀꢁꢂꢃAꢄꢄꢅꢆ

ꢀ_Rꢀꢀ ꢁꢂꢃꢃꢄꢅꢆ

ꢀꢁꢂꢃAꢄꢄꢅꢆ

ꢀ_Rꢀꢀ ꢁꢂꢃꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁꢂꢀꢃꢄ ꢂꢅꢆꢇ

ꢀꢁꢂꢀꢃꢄ ꢅꢆꢇꢈ

ꢀꢁꢂꢀꢃꢄ ꢅꢆꢇꢈꢉ

ꢀꢁꢂꢃꢄꢅ ꢂꢆꢇꢈ

ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢉ

ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢉꢊ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢀꢁ ꢀꢁꢂ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢀꢁ ꢀꢁꢂ

Rꢀ ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ

RꢀꢁꢂꢃꢄꢀR ꢅAꢆꢇꢀ ꢈꢂꢉꢄꢀꢁꢀRꢊ

ꢀꢀꢁꢂ ꢃꢄꢄ

ꢀꢀꢁꢂ ꢃꢄꢅ

ꢀꢀꢁꢂ ꢃꢄꢂ

Optimized HD2 vs

Temperature (T_C)

HD2 vs Temperature (T_C)

HD2 vs LO Power

ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢂ

ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢂ

ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢂ

ꢀꢁꢂꢃꢄꢃꢅꢆꢇ Aꢂ ꢈꢉꢊꢋ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ

Rꢀ ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ

ꢀꢀꢁꢂ ꢃꢄꢀ

ꢀꢀꢁꢂ ꢃꢄꢅ

Rev A

9

For more information www.analog.com

LTC5594

V_CC= 5V, EN = 3.3V, T_C= 25°C, P_LO= 6dBm,

TYPICAL PERFORMANCE CHARACTERISTICS

HSLO, RF tone spacing = 4MHz, f_IF= 30MHz, P_IF= –1.5dBm per tone, and register defaults. DC Blocks, 50Ω terminations, and

MACOM H9 180° combiner at amplifier outputs de-embedded from measurement unless otherwise noted. Test circuit shown in

Figure 1 with 1GHz interstage filter.

HD2 vs Temperature (T_C) and

Register Value

HD2 vs Temperature (T_C) and

Register Value

HD3 vs Temperature (T_C)

ꢀꢁ

ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢂ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢉꢊ

ꢀꢁꢂꢃꢄꢅ ꢂꢆꢇꢈ

ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢉ

ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢉꢊ

ꢀꢁꢂꢃꢄꢅ ꢂꢆꢇꢈ

ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢉ

ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢉꢊ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁꢂꢃꢄꢅ ꢂꢆꢇꢈ

ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢉ

ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢉꢊ

ꢀꢁꢂꢃꢄꢅ ꢂꢆꢇꢈ

ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢉ

ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢉꢊ

ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢃAꢄꢄꢅꢆ

ꢀ_Rꢀꢀ ꢁꢂꢃꢃꢄꢅꢆ

ꢀꢁꢂꢃAꢄꢄꢅꢆ

ꢀ_Rꢀꢀ ꢁꢂꢃꢃꢄꢅꢆ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢀꢁ ꢀꢁꢂ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢀꢁ ꢀꢁꢂ

ꢀ

ꢀꢁ

RꢀꢁꢂꢃꢄꢀR ꢅAꢆꢇꢀ ꢈꢂꢉꢄꢀꢁꢀRꢊ

Rꢀ ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ

ꢀꢀꢁꢂ ꢃꢄꢅ

ꢀꢀꢁꢂ ꢃꢄꢁ

ꢀꢀꢁꢂ ꢃꢄꢅ

Optimized HD3 vs

Temperature (T_C)

HD3 vs Temperature (T_C) and

Register Value

HD3 vs Temperature (T_C) and

Register Value

ꢀꢁꢂ

ꢀꢁꢂꢂ

ꢀꢁꢁꢂ

ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢂ

ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢂ

ꢀꢁꢂꢃꢄꢃꢅꢆꢇ Aꢂ ꢈꢉꢊꢋ

ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢉꢊ

ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢉ

ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢉꢊ

ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢉ

ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢉꢊ

ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢉ

ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢉꢊ

ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢉ

ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢉꢊ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁꢂꢃAꢄꢄꢅꢆ

ꢀ_Rꢀꢀ ꢁꢂꢃꢃꢄꢅꢆ

ꢀꢁꢂꢃAꢄꢄꢅꢆ

ꢀ_Rꢀꢀ ꢁꢂꢃꢃꢄꢅꢆ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢀꢁ ꢀꢁꢂ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢀꢁ ꢀꢁꢂ

Rꢀ ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ

RꢀꢁꢂꢃꢄꢀR ꢅAꢆꢇꢀ ꢈꢂꢉꢄꢀꢁꢀRꢊ

ꢀꢀꢁꢂ ꢃꢄꢅ

ꢀꢀꢁꢂ ꢃꢄꢄ

ꢀꢀꢁꢂ ꢃꢄꢅ

Image Rejection vs

Temperature (T_C)

Output Referred P1dB

Image Rejection vs LO Power

ꢀꢁ

ꢀꢀ

ꢀꢁ

ꢀ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ

Rꢀ ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ

ꢀꢁ ꢂRꢃꢄꢅꢃꢆꢇꢈ ꢉꢊꢋꢌꢍ

ꢀꢀꢁꢂ ꢃꢄꢂ

ꢀꢀꢁꢂ ꢃꢄꢀ

ꢀꢀꢁꢂ ꢃꢄꢅ

Rev A

10

For more information www.analog.com

LTC5594

V_CC= 5V, EN = 3.3V, T_C= 25°C, P_LO= 6dBm,

TYPICAL PERFORMANCE CHARACTERISTICS

HSLO, RF tone spacing = 4MHz, f_IF= 30MHz, P_IF= –1.5dBm per tone, and register defaults. DC Blocks, 50Ω terminations, and

MACOM H9 180° combiner at amplifier outputs de-embedded from measurement unless otherwise noted. Test circuit shown in

Figure 1 with 1GHz interstage filter.

Optimized Image Rejection vs

Temperature (T_C)

Optimized Image Rejection vs

Baseband Frequency

Gain Error vs Temperature (T_C)

and GERR Register Value

ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢂ

ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢂ

ꢀꢁꢂ

ꢀ_ꢀꢀ ꢁꢁꢂꢃ

ꢀꢁꢂꢃꢄꢃꢅꢆꢇ Aꢂ ꢈꢉꢊꢋ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂAꢃꢄꢅ

ꢀꢁꢂꢃꢄꢃꢅꢆꢇ

ꢀꢁꢂꢃ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂꢃ

ꢀ_Rꢀꢀ ꢁꢂꢃꢃꢄꢅꢆ

ꢀꢁꢂꢃꢄ ꢅ_ꢀꢁꢀ ꢁꢂꢃꢃꢄꢅꢆ

ꢀꢁꢂꢃꢄꢃꢅꢆꢇ Aꢂ ꢈ_Rꢀꢀ ꢁꢂꢃꢃꢄꢅꢆ

ꢀ

ꢀꢁ

ꢀꢁ ꢀꢁꢂꢃ ꢀꢁꢂꢃ ꢀꢁꢂꢃ ꢀꢁꢂꢃ

ꢀ

ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ

Rꢀ ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ

ꢀAꢁꢂꢀAꢃꢄ ꢅRꢂꢆꢇꢂꢃꢈꢉ ꢊꢋꢌꢍꢎ

RꢀꢁꢂꢃꢄꢀR ꢅAꢆꢇꢀ ꢈꢂꢉꢄꢀꢁꢀRꢊ

ꢀꢀꢁꢂ ꢃꢄꢅ

ꢀꢀꢁꢂ ꢃꢄꢁ

Phase Error vs Temperature (T_C)

and PHA Register Value

DC Offset vs Temperature (T_C)

DC Offset vs LO Power

ꢀꢁꢁ

ꢀꢁ

ꢀꢁꢁ

ꢀꢁ

ꢀ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄ

ꢀꢁ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢂ

ꢀꢁꢂ

ꢀꢁꢂꢂ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄ

ꢀ_Rꢀꢀ ꢁꢂꢃꢃꢄꢅꢆ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢀꢁ ꢀꢁꢂ

ꢀꢁ ꢂRꢃꢄꢅꢃꢆꢇꢈ ꢉꢊꢋꢌꢍ

RꢀꢁꢂꢃꢄꢀR ꢅAꢆꢇꢀ ꢈꢂꢉꢄꢀꢁꢀRꢊ

ꢀꢀꢁꢂ ꢃꢂꢄ

Optimized DC Offset vs

Temperature (T_C)

DC Offset vs Temperature (T_C)

and Register Value

Blocking Noise Figure vs

LO Power

ꢀꢁꢁ

ꢀꢁ

ꢀꢁꢁ

ꢀꢁ

ꢀ_ꢀꢀ ꢁꢂꢃꢄ

ꢀ_ꢀꢁꢀ ꢁꢂꢃꢄꢅꢆꢇ

ꢀ_{R ꢁ ꢂꢃꢄꢅꢆ}ꢀ ꢁꢂꢃꢄꢅꢆꢇ

ꢀ_{ꢀ ꢂ ꢃꢄꢀꢅꢆ}ꢀ ꢁꢂꢃꢄꢅ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄꢃꢅꢆꢇ Aꢂ ꢈꢉꢊꢋ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂꢃ

ꢀꢁ

ꢀꢁꢂꢃꢄ

ꢀꢁ

ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢂ

ꢀꢁꢂ

ꢀꢁꢂꢂ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄ

ꢀ_ꢀꢁꢀ ꢁꢂꢃꢄꢅꢆꢇ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢀꢁ ꢀꢁꢂ

ꢀꢁꢂ

ꢀꢁ

ꢀ

ꢀꢁ ꢂRꢃꢄꢅꢃꢆꢇꢈ ꢉꢊꢋꢌꢍ

ꢀꢁ ꢂꢃꢃꢄꢅꢆ ꢀAꢁ ꢇꢈꢉꢆꢅꢊꢅRꢋ

Rꢀ ꢁꢂꢃꢄꢅ ꢃꢆꢇꢈR ꢉꢊꢋꢌꢍ

ꢀꢀꢁꢂ ꢃꢂꢄ

ꢀꢀꢁꢂ ꢃꢂꢀ

Rev A

11

For more information www.analog.com

LTC5594

V_CC= 5V, EN = 3.3V, T_C= 25°C, P_LO= 6dBm,

TYPICAL PERFORMANCE CHARACTERISTICS

HSLO, RF tone spacing = 4MHz, f_IF= 30MHz, P_IF= –1.5dBm per tone, and register defaults. DC Blocks, 50Ω terminations, and

MACOM H9 180° combiner at amplifier outputs de-embedded from measurement unless otherwise noted. Test circuit shown in

Figure 1 with 1GHz interstage filter.

Gain, IIP3, and IIP2 for

Mixer Only

RF to LO Isolation

LO to RF Leakage

ꢀꢁ

ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢂ

ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢂ

ꢀ

ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ

Rꢀ ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ

ꢀꢁ ꢂRꢃꢄꢅꢃꢆꢇꢈ ꢉꢊꢋꢌꢍ

ꢀꢀꢁꢂ ꢃꢂꢄ

OIP3 Distribution vs

Temperature (T_C)

RF to IF Isolation

LO to IF Isolation

ꢀ

ꢀꢁꢂ

ꢀꢁꢁ

ꢀꢁ

ꢀ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁꢂꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁꢂꢃ

ꢀꢁꢀꢂ

ꢀ_ꢀꢀ ꢁꢂꢃꢄ

ꢀAꢁꢂ ꢃ ꢄ

ꢀꢁꢂ ꢃ ꢄ

ꢀꢁꢂꢃ

ꢀꢁꢀꢂ

ꢀ_ꢀꢀ ꢁꢂꢃꢄ

ꢀAꢁꢂ ꢃ ꢄ

ꢀꢁꢂ ꢃ ꢄ

ꢀꢁꢂ

ꢀ_Rꢀꢀ ꢁꢂꢃꢄ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ

Rꢀ ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ

ꢀꢁꢂꢃ ꢄꢅꢆꢇꢈ

ꢀꢁ ꢂRꢃꢄꢅꢃꢆꢇꢈ ꢉꢊꢋꢌꢍ

ꢀꢀꢁꢂ ꢃꢂꢁ

ꢀꢀꢁꢂ ꢃꢀꢄ

OIP2 Distribution vs

Temperature (T_C)

Conversion Gain Distribution vs

Temperature (T_C)

Noise Figure Distribution vs

Temperature (T_C)

ꢀꢁꢁ

ꢀꢁ

ꢀ

ꢀꢁꢁ

ꢀꢁ

ꢀ

ꢀꢁꢁ

ꢀꢁ

ꢀ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀ_Rꢀꢀ ꢁꢂꢃꢄ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ

ꢀꢁꢂ

ꢀꢁ ꢀꢁꢂꢃ ꢀꢀ ꢀꢀꢁꢂ ꢀꢁ ꢀꢁꢂꢃ ꢀꢁ ꢀꢁꢂꢃ

ꢀꢁ ꢀꢀ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ

ꢀꢁꢂꢃ ꢄꢅꢆꢇꢈ

ꢀAꢁꢂ ꢃꢄꢅꢆ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢀꢁꢂ ꢃꢀꢄ

ꢀꢀꢁꢂ ꢃꢀꢂ

Rev A

12

For more information www.analog.com

LTC5594

V_CC= 5V, EN = 3.3V, T_C= 25°C, P_LO= 6dBm,

TYPICAL PERFORMANCE CHARACTERISTICS

HSLO, RF tone spacing = 4MHz, f_IF= 30MHz, P_IF= –1.5dBm per tone, and register defaults. DC Blocks, 50Ω terminations, and

MACOM H9 180° combiner at amplifier outputs de-embedded from measurement unless otherwise noted. Test circuit shown in

Figure 1 with 1GHz interstage filter.

Gain Error Distribution vs

Temperature (T_C)

Phase Error Distribution vs

Temperature (T_C)

Image Rejection Distribution vs

Temperature (T_C)

ꢀꢁꢁ

ꢀꢁ

ꢀ

ꢀꢁꢁ

ꢀꢁ

ꢀ

ꢀꢁꢁ

ꢀꢁ

ꢀ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄ

ꢀ_Rꢀꢀ ꢁꢂꢃꢄ

ꢀꢁꢂꢃꢁ ꢀꢁꢂꢃꢄ ꢀꢁꢂꢃꢁ ꢀꢁꢂꢁꢃ

ꢀ

ꢀꢁꢀꢂ ꢀꢁꢂꢀ

ꢀꢁꢂꢃ

ꢀ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ

ꢀAꢁꢂ ꢃRRꢄR ꢅꢆꢇꢈ

ꢀꢁAꢂꢃ ꢃRRꢄR ꢅꢆꢃꢇRꢃꢃꢈ

ꢀꢁꢂAꢃꢄ Rꢄꢅꢄꢆꢇꢁꢈꢉ ꢊꢋꢌꢍ

ꢀꢀꢁꢂ ꢃꢀꢀ

ꢀꢀꢁꢂ ꢃꢀꢄ

PIN FUNCTIONS

TEMP (Pin 2): Temperature Monitoring Diode. The diode

to ground at this pin can be used to measure the die

temperature. A forward bias current of 100µA can be

used into this pin and the forward voltage drop can be

measured as a function of die temperature.

DNC (Pins 11, 14, 30): DO NOT CONNECT. No connection

should be made to these pins.

AQM, AQP, AIP, AIM (Pins 12, 13, 28, 29): Amplifier

Differential Input Pins. When connected to the mixer

output pins, the DC bias point is V – 1.4V for each pin.

CC

RF (Pin 4): 50Ω RF Input. The pin should be DC-blocked

with a coupling capacitor; 1000pF is recommended.

A lowpass filter is typically used between the AQM(P) or

AIM(P) pins and the MQM(P) or MIM(P) pins to suppress

the high frequency mixing products. See the Applications

section for more information.

V

(Pin 6): IF Amplifier Common Mode Output Voltage

CM

Adjust. Source resistance should be 1k or lower. If this

pin is left unconnected, it will internally self-bias to 0.9V.

IFQM, IFQP, IFIP, IFIM (Pins 15, 16, 25, 26): IF Amplifier

Output Pins. The current used by the output amplifiers

is set by a resistance of 25Ω to 200Ω from each pin to

EN (Pin 7): Enable Pin. A logic high on this pin will enable

the chip. An internal 200k pull-down resistor ensures the

chip remains disabled if there is no connection to the pin

(open-circuit condition).

ground and the V control voltage.

CM

CSB (Pin 17): Chip Select Bar. When CSB is low, the

serial interface is enabled. It can be driven with 1.2V to

3.3V logic levels.

MQP, MQM, MIM, MIP (Pins 9, 10, 31, 32): Mixer Dif-

ferential Output Pins. When connected to the amplifier

input pins, the DC bias point is V – 1.4V for each pin.

V

(Pin 18): Positive Supply Pin. This pin should be

CC

A lowpass filter is typically used between the MQM(P) or

MIM(P) pins and the AQM(P) or AIM(P) pins to suppress

the high frequency mixing products. See the Applications

section for more information.

bypassed with a 1000pF and 4.7µF capacitor to ground.

LOP, LOM (Pins 19, 20): LO Inputs. External matching

is not needed. Can be driven 50Ω single-ended or 100Ω

differentially. The LO pins should be DC-blocked with

Rev A

13

For more information www.analog.com

LTC5594

PIN FUNCTIONS

couplingcapacitor;1000pFisrecommended.Whendriven

single-ended, the unused pin should be terminated with

50Ω in series with the DC-blocking capacitor.

capacitortoground.TheV supplymustbeappliedbefore

CC

the OV supply to prevent damage to the ESD diodes.

DD

AMPD (Pin 27): IF Amplifier Disable Pin. A logic high

on this pin will disable the IF amplifiers. The state of the

IF amplifers is the logical AND of AMPD and the EAMP

register. An internal 200k pull-down resistor ensures the

IF amplifiers are enabled by default if the is no connection

to the pin (open-circuit condition).

SDO (Pin 21): Serial Data Output. This output can accom-

modate logic levels from 1.2V to 3.3V. During read-mode,

data is read out MSB first.

SDI (Pins 22): Serial Data Input. Data is clocked MSB first

into the mode-control registers on the rising edge of SCK.

SDI can be driven with 1.2V to 3.3V logic levels.

GND(Pins1,3,5,8,ExposedPadPin33):Ground.These

pinsmustbesolderedtothecircuitboardRFgroundplane.

Thebacksideexposedpadgroundconnectionshouldhave

a low inductance connection and good thermal contact

to the printed circuit board ground plane using many

through-hole vias. See layout information.

SCK (Pin 23): Serial Clock Input. SDI can be driven with

1.2V to 3.3V logic levels.

OV (Pin 24): Positive Digital Interface Supply Pin. This

DD

pin sets the logic levels for the digital interface. 1.2V to

3.3V can be used. This pin should be bypassed with a 1µF

BLOCK DIAGRAM

ꢀꢁ

ꢀꢁ ꢀꢁ

ꢀꢁꢂ ꢀꢁꢀ

ꢀꢁ

Aꢀꢁ

ꢀꢁ

ꢀ

Aꢀꢁ Aꢀꢁꢂ

ꢁꢁ

ꢀꢁ

ꢀꢁAꢂ

ꢀꢁꢂꢃ ꢄAꢁꢂꢅꢆꢇ ꢈꢀꢀꢉꢃꢊꢅ

ꢀꢁꢂꢃꢄRꢃꢁꢄꢅ Aꢀꢆꢇꢂꢃ

ꢀ

ꢁꢂ

ꢀ

ꢀꢁꢂꢃ

ꢀ

ꢀꢁꢀꢂ

+

ꢀꢁ

ꢀꢁꢀꢂ

–

ꢀ ꢁꢂꢃꢄꢁ

Rꢀ

ꢀꢁꢂ

ꢀꢁ

ꢀ

ꢀꢁ

ꢀꢁ ꢂAꢃꢄꢅ

Aꢀꢁꢂꢃꢄ

ꢀꢁꢂ

ꢀꢁ

Aꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁꢂ

–

ꢀꢁ

ꢀ

ꢀꢁꢂ

+

ꢀꢁ

ꢀꢀ

ꢀꢁ

ꢀ ꢁꢂꢃꢄꢁ

Aꢀꢁꢂꢃꢄ

RꢀꢁꢂꢃꢄꢀRꢃ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂꢃ ꢄAꢁꢂꢅꢆꢇ ꢈꢀꢀꢉꢃꢊꢅ

ꢀꢁꢂꢃꢄRꢃꢁꢄꢅ Aꢀꢆꢇꢂꢃ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄꢀꢅ

ꢀ

ꢀꢁꢀ Aꢀꢁ

ꢀꢁ ꢀꢁ

ꢀꢁ

ꢀꢁꢂ

Aꢀꢁ

ꢀꢁ

ꢀAꢁ

ꢂꢂ

ꢀ

ꢀꢀ

ꢀꢀꢁꢂ ꢃꢄꢅꢆ

Rev A

14

For more information www.analog.com

LTC5594

TIMING DIAGRAMS

SPI Port Timing (Readback Mode)

ꢀ

ꢀꢁ

ꢀ

AꢀꢁꢂꢃꢄꢅꢆRꢇꢈꢇꢅꢁ

ꢀ

ꢀꢁꢂ

AꢀꢁꢂꢃꢄꢅꢆRꢇꢈꢇꢅꢁ

ꢀꢁꢁ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂ

ꢀ

ꢀꢁ

Rꢀꢀ Aꢀ Aꢀ Aꢀ Aꢀ Aꢀ Aꢀ Aꢀ ꢀꢀ ꢀꢀ ꢀꢀ ꢀꢀ ꢀꢀ ꢀꢀ ꢀꢀ ꢀꢀ ꢀꢀ ꢀꢀ ꢀꢀ ꢀꢀ ꢀꢀ ꢀꢀ ꢀꢀ ꢀꢀ

ꢀꢁꢂꢀꢃꢄ

ꢀꢁꢂ

Aꢀ Aꢀ Aꢀ Aꢀ Aꢀ Aꢀ Aꢀ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ

ꢀꢁꢂꢃꢄꢅꢃꢂꢆꢇꢈꢉ

ꢀꢁꢂꢀꢃꢄ

ꢀꢁꢂ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ

ꢀꢁꢂꢃꢄꢅꢃꢂꢆꢇꢈꢉ

SPI Port Timing (Write Mode)

ꢀ

ꢀꢁ

ꢀ

AꢀꢁꢂꢃꢄꢅꢆRꢇꢈꢇꢅꢁ

ꢀ

ꢀꢁꢂ

AꢀꢁꢂꢃꢄꢅꢆRꢇꢈꢇꢅꢁ

ꢀꢁꢁ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂ

ꢀ

ꢀꢁ

Rꢀꢀ Aꢀ Aꢀ Aꢀ Aꢀ Aꢀ Aꢀ Aꢀ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ

ꢀꢁꢂꢀꢃꢄ

ꢀꢁꢂ

Aꢀ Aꢀ Aꢀ Aꢀ Aꢀ Aꢀ Aꢀ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ

ꢀꢁꢂꢃꢄꢅꢃꢂꢆꢇꢈꢉ

ꢀꢁꢂꢀꢃꢄ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄꢅꢃꢂꢆꢇꢈꢉ

Rev A

15

For more information www.analog.com

LTC5594

TEST CIRCUIT

ꢀꢁꢂ

ꢀꢁꢀꢂ

ꢀꢁꢂꢃꢁꢂ

ꢀꢁ

ꢀꢁꢁ

Rꢀ

ꢀꢁ

Rꢀ

ꢀꢁꢀꢂꢃꢄ

ꢀꢁꢂ

ꢀꢁꢀꢂ

ꢀꢁꢂꢃꢁꢂ

Rꢀ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁꢀꢂꢃꢄ

ꢀꢁꢂꢃꢄ ꢀꢅꢆꢆꢆꢇꢈꢉ

ꢀꢁ

ꢂꢂ

ꢀ

ꢀꢁꢂ

ꢀꢁ

ꢀꢀ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁꢂ

ꢀꢁ

ꢂꢂ

ꢀꢁ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄ

ꢀꢁ

ꢀꢁꢂ

Rꢀ

ꢀꢁꢂꢃꢄ

ꢀꢁ

ꢀ

Rꢀ

ꢀꢁꢂ

ꢀꢁ

Rꢀ

ꢀꢁ

ꢀꢁꢂꢃꢃꢄꢅꢆꢇꢈ

ꢀꢁꢂ

ꢀꢁ

ꢀ

ꢁꢂ

ꢀꢁ

ꢀ

ꢀꢁ

ꢁꢁ

ꢀꢁꢂ

ꢀꢀ

ꢀ

ꢁꢁ

ꢀꢁꢂꢃꢄ ꢅꢆ ꢃꢁꢇꢃꢄ

ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢁꢂ

Rꢀꢁ

ꢀꢁꢂꢃ

ꢀꢁꢂ

Rꢀꢀ

Rꢀꢁ

ꢀꢁ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢁꢂ

ꢀꢁꢂ

Rꢀꢁ

ꢀꢀꢁꢂ ꢃꢄꢅ

REF DES

VALUE

1000pF

0.2pF

0.3pF

1.0pF

3.0pF

1μF

SIZE

0402

0201

0603

0805

VENDOR

Murata

REF DES

L1 TO L4

VALUE

SIZE

VENDOR

Coilcraft

C1, C6, C8, C42

8.2nH

49.9Ω

0Ω

0805

0402

C2

C5, C7

R1, R3, R4, R11, R12

R5, R13

R20

C9, C11, C13, C15

C10, C12, C14, C16

C40

40.2kΩ

C43

4.7μF

Figure 1. Test Circuit Schematic

Rev A

16

For more information www.analog.com

LTC5594

TEST CIRCUIT

5594 F02

Figure 2. Component Side of Evaluation Board

5594 F03

Figure 3. Bottom Side of Evaluation Board

Rev A

17

For more information www.analog.com

LTC5594

APPLICATIONS INFORMATION

The LTC5594 is an IQ demodulator designed for high

dynamic range receiver applications. It consists of an RF

balun, I/Q mixers, quadrature LO amplifiers, IF amplifiers,

and correction circuitry for DC offset, image rejection,

and nonlinearity.

internally by the device or by external amplifiers and fil-

ters. The DC offset in both IF channels can be adjusted in

order to minimize the accumulated DC offset at the A/D

converter input.

The IF gain, gain error and phase error adjust, DC offset

adjust, and nonlinearity adjust registers are digitally con-

trolled through a 4-wire serial interface. The register map

is detailed in the Appendix.

Operation

As shown in the Block Diagram for the LTC5594, the RF

input signal is converted to a differential signal by the

on-chip balun transformer before going to the I and Q

channel mixers.

RF Input Port

Figure 4 shows a simplified schematic of the demodula-

tor’s RF input connected to an on-chip balun transformer.

External DC voltage should not be applied to the RF input

pin. DC current flowing into the pin may cause damage

to the chip. Series DC blocking capacitors should be

used to couple the RF input pin to the RF signal source.

As shown in Figure 5, the RF input port is well matched

with return loss greater than 10dB over the frequency

range of 500MHz to 9GHz with a 0.2pF capacitor on C2.

A 0.1pF capacitor on C3 placed 3mm away from C1 on

the 50Ω input transmission line may improve return loss

at higher frequencies. The RF pin can also be externally

matched over the 300MHz to 500MHz frequency range

by changing C2 to 6.8pF. Table 1 shows the impedance

and input reflection coefficient for the RF input with C2 =

0.2pF. The input transmission line length is de-embedded

from the measurement.

The LO inputs are impedance matched using a program-

mablenetwork,andthenaccuratelyshiftedinphaseby90°

by an internal precision phase shifter. This phase shifter

maintains the accurate quadrature relation over the full LO

input range from 300MHz to 9GHz. In addition, the phase

shifter allows fine tuning of the phase difference between

the I- and Q-channel LO with a resolution of around 0.05

degrees to compensate for any phase mismatch between

themixersandphasemismatchintroducedintotheIFpath

by any filter component mismatch.

The differential mixer IF output signals are filtered off-chip

to remove the f + f signal and other high frequency

RF

LO

mixing products before being applied to the on-chip IF

amplifiers. The IF amplifiers have adjustable gain and

common mode output voltage to allow for direct interfac-

ing with A/D converters. The gain balance between both

IF output channels of the LTC5594 can be fine tuned with

a resolution of about 0.016dB in order to compensate

for gain mismatches in the IF signal path, either caused

ꢀ

ꢁꢁ

ꢀꢁꢂ

ꢀꢁꢂꢃꢃꢄꢅ

ꢀꢁ

ꢀꢁꢁꢁꢂꢃ

ꢀ

= 50Ω

ꢀ

ꢀ ꢁ ꢂꢃꢃ

Rꢀ

ꢀꢁꢂꢃꢄ

Rꢀ

ꢀꢁAꢂꢃꢄꢅꢆꢇ

ꢀꢁ

ꢀꢀꢁꢂ ꢃꢄꢂ

ꢀꢁꢂ

Figure 4. Simplified Schematic of the RF Input with External Matching Components

Rev A

18

For more information www.analog.com

LTC5594

APPLICATIONS INFORMATION

Table 1. RF Input Impedance

LO Input Port

S11

FREQUENCY

Thedemodulator’sLOinputinterfaceisshowninFigure6.

The input consists of a programmable input match and a

high precision quadrature phase shifter which generates

0° and 90° phase shifted LO signals for the LO buffer

amplifiers to drive the I/Q mixers. DC blocking capacitors

are required on the LOP and LOM inputs. When using a

single-ended LO input, it is necessary to terminate the

unused LO input (LOP in Figure 6) into 50Ω.

(MHz)

300

INPUT IMPEDANCE (Ω)

30.0 + j57.1

66.8 – j5.3

MAG

0.594

0.151

0.092

0.048

0.113

0.111

0.124

0.233

0.278

0.236

0.191

0.206

0.240

0.192

0.404

ANGLE (°)

122.5

–17.6

–94.0

133.7

96.0

1000

1500

2000

2500

3000

3500

4000

4500

5000

5500

6000

7000

8000

9000

49.4 – j10.4

46.8 + j4.0

48.9 + j12.8

56.5 + j10.6

62.7 – j5.8

56.5

–24.0

–62.6

–78.5

–97.9

–133.2

–162.0

–155.2

179.7

93.6

61.5 – j23.6

55.4 – j30.6

47.0 – j26.3

38.6 – j16.1

33.7 – j7.5

The programmable input match adjust is controlled by

the BAND, CF1, LF1, and CF2 registers as detailed in the

register map shown in Table 2. The return loss for the

register setting in Table 2 is shown in Figure 7.

Table 2. Register Settings for Single-Ended LO Matching

32.3 – j12.0

33.9 + j0.1

LO FREQUENCY (MHz)

BAND

CF1

31

21

14

17

10

15

14

8

LF1

CF2

31

24

23

31

23

31

27

21

31

28

26

31

3

300 to 339

0

1

3

48.0 + j44.0

339 to 398

3

398 to 419

3

ꢀ

ꢀ_ꢀꢀ ꢁꢂꢃꢄ

419 to 556

2

556 to 625

2

ꢀꢁ

625 to 801

1

ꢀꢁꢂ

801 to 831

1

831 to 1046

1046 to 1242

1242 to 1411

1411 to 1696

1696 to 2070

Default

1

31

21

17

15

8

3

2

ꢀꢁ ꢂ ꢃꢄꢁꢅꢆ

ꢀꢁ ꢂ ꢃꢄꢅꢆꢇ

1

3

ꢀ

ꢀꢁ

2070 to 2470

2470 to 2980

2980 to 3500

3500 to 9000

8

1

21

10

19

0

Rꢀ ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ

ꢀꢀꢁꢂ ꢃꢄꢀ

2

1

Figure 5. RF Input Return Loss with C2 = 0.2pF and 6.8pF

1

0

ꢀ

ꢁꢁ

ꢀꢁꢂ

ꢀꢁꢂꢃꢃꢄꢅ

ꢀꢁ

ꢀ

= 50Ω

ꢀ

ꢀꢁꢁꢁꢂꢃ

ꢀ ꢁ ꢀꢂ

ꢀꢁ

ꢀꢁꢂꢃꢄ

ꢀꢁAꢂꢃꢄꢅꢆꢇ

ꢀꢁꢂ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁ

ꢀAꢁꢂꢃ

Aꢀꢁꢂꢃꢄ

ꢀꢁ

ꢀꢁꢂ

Rꢀ

ꢀꢁ

ꢀꢀꢁꢂ ꢃꢄꢅ

ꢀꢁꢂ

Figure 6. Simplified Schematic of the LO Inputs with Single-Ended Drive

Rev A

19

For more information www.analog.com

LTC5594

APPLICATIONS INFORMATION

Figure 8 shows the high band LO input return loss for

various input TL1 transmission line lengths for LO input

frequencies from 6GHz to 9GHz. Return loss greater than

10dB can be achieved by using a 0.2pF capacitor at Cx on

the input 50Ω transmission line. The high band LO input

return loss is listed in Table 3 with no capacitor at Cx and

BAND, CF1, LF1, and CF2 registers set to 1,0,0,0.

Table 3. High Band LO Input Impedance

FREQUENCY

S11

(MHz)

5000

5500

6000

6500

7000

7500

8000

8500

9000

INPUT IMPEDANCE (Ω)

MAG

0.436

0.503

0.453

0.347

0.406

0.467

0.531

0.361

0.402

ANGLE (°)

46.4

87.2 + j37.9

121.5 + j32.1

132.1 + j5.4

27.8

4.8

95.2 – j17.7

–23.8

–58.2

–66.0

–59.9

–75.4

–122.6

73.5 – j39.5

ꢀ

69.0 – j47.5

ꢀ_ꢀꢀ ꢁꢂꢃꢄ

77.8 – j51.9

ꢀ

ꢀꢁ

77.8 – j38.8

58.8 – j38.8

ꢀꢁꢂ

Interstage Filter

An interstage IF filter should be used between the MIP

(MIM) and AIP (AIM) pins and the MQP (MQM) and AQP

ꢀꢁꢂ

(AQM) pins to suppress the large f + f and other mix-

RF LO

ꢀꢁ ꢂ ꢃꢄ

ing products from the mixer outputs. Without the filter, the

linearity of the amplifier can be degraded for the desired

signal. Figure 9 shows a recommended lowpass filter.

Table 4 shows typical values used for a lowpass response

of various bandwidths.

ꢀꢁꢂ

ꢀ

ꢀꢁ ꢂRꢃꢄꢅꢃꢆꢇꢈ ꢉꢊꢋꢌꢍ

ꢀꢁ ꢂꢃꢁ ꢂꢁ ꢂꢃ

ꢀꢁ ꢂꢃꢁ ꢄꢁ ꢅꢂ

ꢀꢁ ꢂꢃꢁ ꢂꢁ ꢄꢅ

ꢀꢁ ꢂꢀꢁ ꢃꢁ ꢂꢄ

ꢀꢁ ꢀꢂꢁ ꢀꢁ ꢃꢀ

ꢀꢁ ꢂꢁ ꢀꢁ ꢀꢃ

ꢀꢁ ꢀꢁ ꢂꢁ ꢀꢃ

ꢀꢁ ꢂꢁ ꢂꢁ ꢂ

ꢀꢀꢁꢂ ꢃꢄꢅ

Table 4. Component Values for Interstage Lowpass Filter

Figure 7. Single-Ended LO Input Return Loss

vs BAND, CF1, LF1, and CF2

1dB BW (MHz)

L1, L2 (nH)

C9, C11 (pF)

C10, C12 (pF)

20

50

330

150

68

39

15

120

47

ꢀ

100

300

500

1000

10

22

ꢀ_ꢀꢀ ꢁꢂꢃꢄ

ꢀ

ꢀꢁ

33

4.7

3.0

1.0

6.8

3.0

22

8.2

ꢀꢁꢂ

It is important that the placement of C10 and C12 be

as close as possible to the amplifier inputs. Long line

lengths on the amplifier inputs can lead to instability. As

shown in Figure 10, a 50Ω common mode termination

resistance can be used to better ensure stability with long

line lengths and/or higher order filtering. The placement

of C9 and C11 should be as close as possible to the mixer

ꢀꢁꢂ

ꢀꢁ ꢂ ꢃꢄꢄ

ꢀꢁ ꢂ ꢃꢄꢅꢆꢇꢇ

ꢀ

ꢀꢁ

ꢀꢁ ꢂRꢃꢄꢅꢃꢆꢇꢈ ꢉꢊꢋꢌꢍ

ꢀꢀꢁꢂ ꢃꢄꢅ

outputs for effective filtering of the 2xLO, f + f , and

other mixing products.

RF

LO

Figure 8. High Band LO Input Return Loss vs

Input Transmission Line Length Lt

By adjusting the values of the capacitors in the filter, it

is possible to add or remove frequency slope of the IF

response. The RF input has a frequency slope above 2GHz

of approximately –1dB/GHz. If a high side LO (HSLO) is

Rev A

20

For more information www.analog.com

LTC5594

APPLICATIONS INFORMATION

V

CC

LTC5594

0.2pF

PACKAGE

1pF 50Ω

2k

50Ω

1pF

PARASITICS

1.5nH

MIP

1.5nH

MIM

0.2pF

C11

C12

C9

42mA

AC CURRENT

SOURCE

L2

L1

V

CC

PACKAGE

PARASITICS

100Ω

C10

1.5nH

AIM

AIP

0.2pF

1.5nH

0.6pF

50Ω

0.6pF

50Ω

5594 F09

GND

Figure 9. Simplified Schematic of the Mixer Output and IF Amplifier Input with Interstage Filter

ꢀꢁꢂ

I-Channel and Q-Channel Outputs

ꢀꢁꢀ

ꢀꢁꢁ

ꢀꢁ

The phase relationship between the I-channel output

signal and the Q-channel output signal is fixed. When the

LO input frequency is higher (or lower) than the RF input

frequency, the Q-channel outputs (IFQP, IFQM) lead (or

lag) the I-channel outputs (IFIP, IFIM) by 90°.

ꢀꢁ

ꢀꢁꢂ

ꢀꢁ

ꢀꢁꢂ

Aꢀꢁ

ꢀꢀꢁꢂ ꢃꢄꢅ

Figure 11 shows a simplified schematic of the IF amplifier

outputs. The current-mode outputs require a terminating

resistance to establish a common mode voltage level. The

optimum operating current is 18mA per output. A 50Ω

termination is recommended on each output for a 0.9V

common mode voltage (R5, R6). Operation at a higher

common mode voltage is possible with the addition of

a common mode termination. For example, to operate

at 1.8V, an additional common mode resistance of 25Ω

(R5 = 66.5Ω and R6 = 0Ω, or R5 = R6 = 43.2Ω) would

be used to maintain an output current of 18mA. Alterna-

tively, a 100Ω termination to ground on each output can

be used for a 1.8V common mode voltage with 6dB more

50Ω

Figure 10. Interstage IF Filter with Common Mode Termination

used, the resulting IF slope will be 1dB/GHz. If a low side

LO (LSLO) is used, the resulting IF slope will be –1dB/

GHz.TheIFfiltercomponentvaluescanbeadjustedsothat

approximately 1dB of peaking or roll-off can be achieved

over the filter bandwidth to give an overall flat IF response

for the HSLO or LSLO case.

Rev A

21

For more information www.analog.com

LTC5594

APPLICATIONS INFORMATION

conversion gain. To operate at lower common mode volt-

ages, a lower termination resistance can be used on each

output at the expense of conversion gain, or a negative

supply can be used at the connection of the termination

resistors. Figure 12 shows the OIP3 of the amplifier alone

with various common mode voltages.

A typical anti-alias filter is shown in Figure 11 for interface

with an ADC. The parallel combinations of R3||R7 and

R4||R8 set the differential impedance for the ADC. The

input and output of the filter contain a common mode

terminationforhighfrequencies.TheseareformedbyC17,

C18 and 24.9Ω at the input and C23, C24 and 24.9Ω at

theoutput.Thecommonmodeterminationattheamplifier

output ensures stability and the common mode termina-

tion at the ADC input provides a termination for the high

frequency kickback from the sampling capacitors in the

ADC. Table 5 shows some typical values vs 1dB cutoff

frequency for the anti-alias filter. To optimize the flatness

and ripple of the IF band, both the IF interstage filter and

the anti-alias filter can be designed together in a simulator

including package parasitics. The additional slope due to

RF slope and HSLO or LSLO can be compensated by us-

ing this method. The layout of the anti-alias filter should

be done so that the amplifier outputs and ADC inputs are

as close as possible. This is to prevent long line lengths

from introducing additional parasitics.

ꢀꢁ

ꢀꢁ ꢂꢃꢄꢅꢆꢇAꢈꢀꢄꢉ ꢊ ꢋꢌꢍꢎ

ꢇ

ꢂ

ꢊ ꢏꢋꢐꢑꢒꢓꢔꢂꢃꢄꢅ

ꢊ ꢑꢑꢕꢈ

ꢀꢁ

ꢈ

ꢀꢁ

ꢀꢁꢂꢃ

ꢀꢁ

ꢀ

ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ

ꢃ

ꢀꢁ ꢁRꢂꢃꢄꢂꢅꢆꢇ ꢈꢉꢊꢋꢌ

ꢀꢀꢁꢂ ꢃꢄꢅ

Figure 12. OIP3 of Amplifier Only vs

Output Common Mode Voltage (V_CM

)

Theamplifiergaincanbeadjustedineightstepsofroughly

1dB from 8dB to 15dB using the AMPG register. Setting

AMPG = 0x7 sets the gain at about 15dB and setting

AMPG = 0x0 sets the gain to about 8dB.

ꢀ

ꢁꢁ

ꢀꢁꢂꢃꢃꢄꢅ

ꢀꢁꢂ ꢃRꢄꢅR

AꢆꢁꢇꢈAꢉꢇAꢊ

ꢀꢁꢂꢃꢄR

+

–

ꢀꢁ

ꢀꢁꢂ

0.9V

ꢀꢁꢂ

ꢀAꢁꢂAꢃꢄ

ꢀARAꢁꢂꢃꢂꢄꢁ

ꢀꢁꢂꢃꢄ

ꢀꢁ

R3

R7

ꢀꢁꢂ

68.1Ω

200Ω

ꢀꢁꢀꢂ

Aꢀ ꢀꢁRRꢂꢃꢄ

ꢀꢁꢂRꢃꢄ

R5

R6

0Ω

ꢀꢁꢂꢃꢄ

R2

24.9Ω

R9

0Ω

24.9Ω

ꢀꢁꢂꢃꢄ

ꢀꢁꢀꢂ

R4

R8

200Ω

ꢀꢁꢂꢃꢄ

ꢀꢁꢂ

Z

OUT

= 100Ω

ꢀꢁꢂ

68.1Ω

ꢀꢁ

ꢀꢁꢂ

5594 F11

0.9V

ꢀꢁꢂ

Figure 11. Simplified Schematic of the IF Amplifier Output with Anti-Alias Filter

Rev A

22

For more information www.analog.com

LTC5594

APPLICATIONS INFORMATION

Table 5. Component Values for Anti-Alias Lowpass Filter

Table 6. IF Amplifier S-Parameters (Differential-Mode)

1dB BW

(MHz)

L5 – L8

(nH)

C17, C18

(pF)

C20, C21

(pF)

C23, C24

(pF)

IF

S

22

11

21

12

MAG ANG MAG ANG MAG ANG MAG ANG

(MHz)

20

50

560

240

120

33

56

22

180

68

82

33

0.001 0.204 –179.9 2.129 180.0 1.8e-4 164.8 0.014 178.5

100 0.203 176.0 2.154 171.9 5.4e-4 118.0 0.026 –120.9

200 0.205 172.2 2.170 163.7 1.0e-4 102.8 0.050 –112.0

300 0.207 168.5 2.197 155.6 1.7e-4 92.8 0.079 –113.5

400 0.210 164.8 2.239 147.3 2.8e-4 93.7 0.111 –118.3

500 0.215 160.9 2.292 138.8 3.2e-4 95.4 0.147 –125.0

600 0.221 157.0 2.363 130.1 4.0e-4 92.0 0.186 –132.1

700 0.227 153.0 2.445 121.2 5.0e-4 92.1 0.230 –140.0

800 0.235 149.0 2.535 112.0 5.5e-4 86.2 0.279 –148.1

900 0.242 144.6 2.642 102.0 6.9e-4 93.2 0.334 –157.0

1000 0.251 140.6 2.770 92.3 7.9e-4 92.7 0.396 –166.2

1500 0.303 117.6 3.420 32.3 0.003 92.6 0.738 134.4

2000 0.365 90.2 3.318 –45.5 0.005 33.2 0.828 70.0

2500 0.385 56.1 2.232 –105.2 0.005 –3.1 0.666 13.1

3000 0.365 16.6 2.620 –160.2 0.005 –34.2 0.488 –38.4

3500 0.319 –28.2 1.021 157.4 0.005 –61.9 0.418 –94.7

4000 0.307 –83.4 0.742 113.3 0.005 –79.5 0.409 –150.6

100

300

500

1000

12

39

22

3.9

1.8

1.0

8.2

6.8

3.3

6.8

3.3

1.8

22

8

Tables 6 and 7 show the differential and common mode

S-parameters for the amplifier by itself with 50Ω termina-

tionsonallports. Inaddition, commonmodeterminations

were used on the input and output ports having a value of

2pF in series with 50Ω.

The common mode feedback amplifier holds the common

mode output voltage within about 20mV of the V pin

CM

voltage. The V pin interface is shown in Figure 13. The

CM

V

pin should be driven by a voltage source with an

CM

output impedance lower than 1kΩ. When the V pin is

CM

unbiased, the output common mode voltage will be held

Table 7. IF Amplifier S-Parameters (Common Mode)

at a nominal 0.9V given by the internal voltage divider

IF

S

22

11

21

12

MAG ANG MAG ANG MAG ANG MAG ANG

(MHz)

formed by the 40k and 8k resistors. Connecting the V

CM

0.001 0.184 –138.7 9.2e-4 –112.8 0.037 –65.3 0.985 179.8

100 0.186 172.5 0.085 –118.9 0.013 –68.6 0.152 126.7

200 0.188 166.6 0.173 –134.7 0.007 –91.8 0.125 116.7

300 0.191 160.2 0.237 –150.0 0.004 –113.1 0.097 97.3

400 0.196 154.4 0.291 –163.8 0.002 –145.4 0.067 75.2

500 0.202 148.4 0.340 –176.8 0.002 170.2 0.037 43.6

600 0.210 142.8 0.387 170.9 0.002 137.0 0.023 –38.0

700 0.219 137.2 0.436 159.1 0.003 118.1 0.051 –97.8

800 0.230 132.0 0.488 147.1 0.003 107.8 0.094 –121.5

900 0.243 126.5 0.550 134.9 0.004 106.6 0.148 –137.0

1000 0.252 120.9 0.612 122.2 0.006 104.8 0.211 –151.3

1500 0.325 96.7 0.981 43.4 0.020 80.4 0.749 136.1

2000 0.438 72.1 0.776 –46.1 0.036 18.6 1.005 55.9

pin to an ADC common mode reference pin allows the

output common mode voltage of the IF amplifier to track

the ADC common mode.

ꢀ

ꢁꢁ

ꢀꢁꢂꢃꢃꢄꢅ

ꢀꢁꢂ

250Ω

+

ꢀ

ꢁꢂ

–

ꢀꢁ

ꢀꢁꢂꢃꢄ

2500 0.549 40.1 0.496 –97.1 0.041 –21.9 0.873

2.9

3000 0.601 6.9 0.397 –143.2 0.042 –52.2 0.764 –37.3

3500 0.618 –27.5 0.281 –175.7 0.044 –80.3 0.668 –72.7

4000 0.595 –60.3 0.254 147.3 0.046 –101.2 0.620 –107.0

ꢀꢀꢁꢂ ꢃꢄꢅ

ꢀꢁꢂ

Figure 13. Simplified Schematic of the V_CMInput Pin

Rev A

23

For more information www.analog.com

LTC5594

APPLICATIONS INFORMATION

Temperature Diode

ablethedemodulator,amplifier,DCoffset,andnonlinearity

adjust circuits which are controlled by the EDEM, EAMP,

EDC,andEADJbits.Alternatively,writinganycombination

of bits to the four MSB’s of register 0x16 will enable or

disable the individual circuit blocks.

A schematic of the TEMP pin is shown in Figure 14. The

temperature diode can be used to directly measure the

die temperature. A 40k resistor is recommended to V

CC

to generate a 100µA current source for the diode readout.

The temperature slope is about –1.52mV/°C.

AMPD Interface

ꢀ

ꢁꢁ

Also shown in Figure 15 is the simplified schematic for

the AMPD IF amplifier disable pin. The IF amplifiers are

enabled if the logical AND of AMPD and the EAMP register

is 1. The IF amplifier state is detailed in Table 8.

ꢀꢁꢂꢃꢃꢄꢅ

Rꢀꢁ

ꢂꢁꢃꢀꢄ

100Ω

ꢀꢁꢂꢃ

ꢀ

ꢀꢁꢂꢃ

Table 8. IF Amplifier State vs Logic Levels

AMPD Pin

EAMP

Register

0

1

ꢀꢀꢁꢂ ꢃꢄꢂ

0

1

OFF

ON

OFF

ꢀꢁꢂ

Figure 14. Schematic of the TEMP Pin

Digital Input Pins

Enable Interface

Figure 16 shows the simplified schematics for the digital

input pins, SCK, CSB, and SDI. These pins should not be

leftfloating,sincethereisnointernalpull-downorpull-up.

A simplified schematic of the EN pin is shown in Figure 15.

TheenablevoltagenecessarytoturnontheLTC5594is0.7

• OV . To disable or turn off the chip, this voltage should

DD

ꢀ

ꢁꢁ

bebelow0.3•OV .IftheENpinisnotconnected,thechip

DD

is disabled. An internal 200kΩ pull-down keeps the part in

shutdown mode if the pin is left floating. The LTC5594 can

be put into a lower current sleep mode through the serial

interface by writing 0x00 to register 0x16. This will dis-

ꢀꢁꢂꢃꢃꢄꢅ

ꢀꢁ

ꢀꢁꢂꢁꢃAꢄ

ꢀꢁꢂꢃꢄ

ꢀ

ꢁꢁ

ꢀꢁꢂꢃꢃꢄꢅ

ꢀꢁ

ꢀꢀꢁꢂ ꢃꢄꢅ

ꢀꢁ

ꢅꢆꢇ Aꢈꢉꢊꢋ

ꢀꢁꢂ

ꢀꢁꢁꢂ

Figure 16. Simplified Schematic of the Digital

Input Pins (SCK, CSB, SDI)

OV Interface

DD

ꢀꢀꢁꢂ ꢃꢄꢀ

Figure 17 shows the simplified schematic of the OV

ꢀꢁꢂ

DD

interface. The OV pin supplies the voltage for the digital

DD

Figure 15. Simplified Schematic of the EN (or AMPD)

Pin Interface

inputs and SDO pin. By setting the pin at 1.2V to 3.3V, the

serial port can function with 1.2V to 3.3V logic levels. It is

important that when sequencing the supply voltages for

Rev A

24

For more information www.analog.com

LTC5594

APPLICATIONS INFORMATION

the chip that the V supply be brought up first before the

data is transferred to the internal register at the falling

CC

th

edge of the 16 clock cycle (parallel load).

OV supply. This is to prevent the ESD diode connected

DD

between OV and V from getting damaged.

DD

CC

Multiple Byte Transfers

ꢀ

ꢁꢁ

More efficient data transfer of multiple bytes is accom-

plished by using the LTC5594’s register address auto-

increment feature as shown in the timing diagram. The

serial port master sends the destination register address

in the first byte and reads or writes data in the second

byte as before, but on the third byte the address pointer

is auto-incremented by 1 and the serial port master can

read or write to subsequent registers. If the register ad-

dress pointer attempts to increment past 23 (0x17), it is

automatically reset to 0.

ꢀꢁꢂꢃꢃꢄꢅ

ꢀꢁꢂ

ꢀꢁ

ꢂꢂ

ꢀꢁꢂꢁꢃAꢄ

ꢀꢁꢂꢃꢄꢅ

ꢀꢀꢁꢂ ꢃꢄꢅ

ꢀꢁꢂ

Figure 17. Simplified Schematic of the OV_DDPin Interface

SDO_MODE Control Bit

SERIAL PORT

The SDO output has two modes of operation as shown

in the timing diagram. When register 0x16 control bit

SDO_MODE = 0, the SDO pin functions as a normal output

which is Hi-Z during a write command. If SDO_MODE = 1,

the SDO output is put into a serial repeater mode where

SDO echos the command written to SDI before readback

of register contents either in read or write mode. This

can be used in high bus noise environments where it is

necessary to perform error checking on commands sent

to the serial port.

The SPI compatible serial port provides control and moni-

toring functionality.

Communication Sequence

The serial bus is comprised of CSB, SCK, SDI and SDO.

Data transfers to the part are accomplished by the

serial bus master device first taking CSB low to enable the

LTC5594’s port. Input data applied on SDI is clocked on

the rising edge of SCK, with all transfers MSB first. The

communicationburstisterminatedbytheserialbusmaster

returning CSB high. See the timing diagrams for details.

A simplified schematic of the SDO output is shown in

Figure 18. The OV supply sets the logic level of the

DD

output, anda25Ωseriesresistorlimitstheoutputcurrent.

Data is read from the part during a communication burst

using SDO. Readback may be multidrop (more than one

LTC5594 or other serial device connected in parallel on

the serial bus), as SDO is high impedance (Hi-Z) when

CSB = 1.

ꢀꢁ

ꢂꢂ

ꢀ

ꢁꢁ

ꢀꢁꢂꢃꢃꢄꢅ

Single Byte Transfers

25Ω

ꢀꢁꢂ

The serial port is arranged as a simple memory map, with

status and control available in 23 registers as shown in

the appendix. All data bursts are comprised of at least two

8-bit bytes. The most significant bit of the first byte is the

read/write bit. Setting this bit to 1 puts the serial port into

read mode. The next 7 bits of the first byte are address bits

and can be set from 0x00 to 0x17. The subsequent byte,

or bytes, is data from/to the specified register address.

See the timing diagrams for details. Note that the written

ꢀꢀꢁꢂ ꢃꢄꢅ

ꢀꢁꢂ

Figure 18. Simplified Schematic of the SDO Pin Interface

Rev A

25

For more information www.analog.com

LTC5594

APPLICATIONS INFORMATION

Register Defaults

application is shown in Figure 19. A 2-tone source signal

is applied to the RF input and the I and Q ADC outputs are

measuredinthedigitaldomaintodeterminetheoptimized

register settings in the LTC5594 for minimization of the

impairments.

The register map and defaults are given in Tables 9 and

10 in the Appendix. When the device is powered up, the

registers may not be reset to their default values. By

writing a 1 to the SRST bit (bit[3]) of register 0x16, the

device will go into soft reset and the registers will be reset

to their default values.

Figure 20 shows the nonoptimized baseband spectrum

and Figure 21 shows the optimized baseband spectrum

for a 2-tone test signal at 5.8GHz.

Impairment Minimization

The LTC5594 contains circuitry for minimizing receiver

impairments such as DC offset, phase and gain error,

and nonlinearity. An example block diagram of a receiver

Aꢀꢁꢂꢃꢂꢂ

ꢀ

ꢀꢁ

Aꢀꢁꢂꢃꢄ

ꢀꢁꢂꢃꢃꢄꢅ

ꢀ

Aꢀꢁ

ꢀꢁꢂꢃꢄꢅ

ꢀꢁꢂꢃAꢄ

ꢀꢁꢂRꢃꢄ

ꢀꢁꢂꢃARꢁꢄꢅ

ꢀꢁ ꢂꢃꢃꢄꢅꢆ

ꢀꢁAꢂꢃ

ꢀꢁ

Rꢀ

ꢀꢁꢂ

ꢀꢁAꢂꢃRꢁꢀꢁꢄꢅ

Aꢀꢁ ꢂꢃꢄꢅꢆꢅꢇAꢄꢅꢂꢀ

Aꢀꢁꢂꢃꢄ

ꢀ

Aꢀꢁ

ꢀꢁꢂ

ꢀꢀꢁꢂ ꢃꢄꢁ

Figure 19. Example Block Diagram of a Receiver with 2-Tone Test Signal for Impairment Minimization

Rev A

26

For more information www.analog.com

LTC5594

APPLICATIONS INFORMATION

ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢂ

ꢀꢁꢂꢃ

ꢀꢀꢁꢂ ꢃꢄꢅ

ꢀꢁꢂꢂ

ꢀ

ꢀꢁꢁ

ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ

Figure 20. Nonoptimized 2-Tone Spectrum at 5.8GHz with 1GHz Anti-Alias Filter

ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢂ

ꢀꢁꢂꢃ

ꢀꢀꢁꢂ ꢃꢄꢅ

ꢀꢁꢂꢂ

ꢀ

ꢀꢁꢁ

ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ

Figure 21. Optimized 2-Tone Spectrum at 5.8GHz with 1GHz Anti-Alias Filter

Rev A

27

For more information www.analog.com

LTC5594

APPENDIX

Table 9. Serial Port Register Contents

ADDR

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

MSB

[6]

[5]

[4]

[3]

[2]

[1]

LSB

R/W

DEFAULT

0x80

0x04

0x82

0x48

0xE3

0x80

0x6A

0xF0

0x01

IM3QY[7]

IM3QX[7]

IM3IY[7]

IM3IX[7]

IM2QX[7]

IM2IX[7]

IM3QY[6]

IM3QX[6]

IM3IY[6]

IM3IX[6]

IM2QX[6]

IM2IX[6]

IM3QY[5]

IM3QX[5]

IM3IY[5]

IM3IX[5]

IM2QX[5]

IM2IX[5]

IM3QY[4]

IM3QX[4]

IM3IY[4]

IM3IX[4]

IM2QX[4]

IM2IX[4]

IM3QY[3]

IM3QX[3]

IM3IY[3]

IM3IX[3]

IM2QX[3]

IM2IX[3]

IM3QY[2]

IM3QX[2]

IM3IY[2]

IM3IX[2]

IM2QX[2]

IM2IX[2]

IM3QY[1]

IM3QX[1]

IM3IY[1]

IM3IX[1]

IM2QX[1]

IM2IX[1]

IM3QY[0]

IM3QX[0]

IM3IY[0]

IM3IX[0]

IM2QX[0]

IM2IX[0]

HD3QY[7] HD3QY[6] HD3QY[5]

HD3QX[7] HD3QX[6] HD3QX[5]

HD3QY[4] HD3QY[3] HD3QY[2] HD3QY[1] HD3QY[0]

HD3QX[4] HD3QX[3] HD3QX[2] HD3QX[1] HD3QX[0]

HD3IY[7]

HD3IX[7]

HD3IY[6]

HD3IX[6]

HD3IY[5]

HD3IX[5]

HD3IY[4]

HD3IX[4]

HD3IY[3]

HD3IX[3]

HD3IY[2]

HD3IX[2]

HD3IY[1]

HD3IX[1]

HD3IY[0]

HD3IX[0]

HD2QY[7] HD2QY[6] HD2QY[5]

HD2QX[7] HD2QX[6] HD2QX[5]

HD2QY[4] HD2QY[3] HD2QY[2] HD2QY[1] HD2QY[0]

HD2QX[4] HD2QX[3] HD2QX[2] HD2QX[1] HD2QX[0]

HD2IY[7]

HD2IX[7]

DCOI[7]

DCOQ[7]

0*

HD2IY[6]

HD2IX[6]

DCOI[6]

DCOQ[6]

0*

HD2IY[5]

HD2IX[5]

DCOI[5]

DCOQ[5]

0*

HD2IY[4]

HD2IX[4]

DCOI[4]

DCOQ[4]

0*

HD2IY[3]

HD2IX[3]

DCOI[3]

DCOQ[3]

0*

HD2IY[2]

HD2IX[2]

DCOI[2]

DCOQ[2]

IP3IC[2]

GERR[0]

CF1[2]

HD2IY[1]

HD2IX[1]

DCOI[1]

DCOQ[1]

IP3IC[1]

IP3CC[1]

CF1[1]

HD2IY[0]

HD2IX[0]

DCOI[0]

DCOQ[0]

IP3IC[0]

IP3CC[0]

CF1[0]

GERR[5]

LVCM[2]

BAND

GERR[4]

LVCM[1]

LF1[1]

GERR[3]

LVCM[0]

LF1[0]

GERR[2]

CF1[4]

CF2[4]

PHA[5]

AMPG[0]

EAMP

GERR[1]

CF1[3]

CF2[3]

CF2[2]

CF2[1]

CF2[0]

PHA[8]

PHA[0]

EDEM

PHA[7]

AMPG[2]

EDC

PHA[6]

AMPG[1]

EADJ

PHA[4]

PHA[3]

PHA[2]

AMPIC[1]

0*

PHA[1]

AMPIC[0]

0*

AMPCC[1] AMPCC[0]

SRST

0*

SDO_MODE

0*

CHIPID[1] CHIPID[0]

0*

1*

*Unused, do not change default value.

Rev A

28

For more information www.analog.com

LTC5594

APPENDIX

Table 10. Serial Port Register Bit Field Summary

BITS

FUNCTION

DESCRIPTION

VALID VALUES

DEFAULT

0x02

0x06

1

AMPCC[1:0]

AMPIC[1:0]

AMPG[2:0]

BAND

IF Amplifier IM3 CC Adjust

IF Amplifier IM3 IC Adjust

IF Amplifier Gain Adjust

LO Band Select

Used to optimize the IF amplifier IM3.

Adjusts the amplifier gain from 8dB to 15dB.

0x00 to 0x03

0x00 to 0x07

0, 1

Selects which LO matching band is used. BAND = 1 for high band. BAND

= 0 for low band.

CF1[5:0]

LO Matching Capacitor CF1 Controls the CF1 capacitor in the LO matching network.

LO Matching Capacitor CF2 Controls the CF2 capacitor in the LO matching network.

0x00 to 0x1F

0x00 to 0x03

0x00 to 0xFF

0, 1

0x08

0x03

0x00

0x80

1

CF2[5:0]

CHIPID

Chip Identification Bits

I-Channel DC Offset

Factory set to default value.

DCOI[7:0]

DCOQ[7:0]

EADJ

Controls the I-channel DC offset over a range from –200mV to 200mV.

Controls the Q-channel DC offset over a range from –200mV to 200mV.

Enables the nonlinearity adjustment circuitry if EADJ = 1.

Enables the IF amplifiers if EAMP = 1.

Q-Channel DC Offset

Enable Nonlinearity Adjust

Enable IF Amplifiers

Enable DC Offset Adjust

Enable Demodulator

EAMP

0, 1

1

EDC

Enables the DC offset adjustment circuitry if EDC = 1.

Enables the demodulator circuitry if EDEM = 1.

0, 1

1

EDEM

0, 1

1

GERR[5:0]

HD2IX[7:0]

HD2IY[7:0]

HD2QX[7:0]

HD2QY[7:0]

HD3IX[7:0]

HD3IY[7:0]

HD3QX[7:0]

HD3QY[7:0]

IM2IX[7:0]

IM2QX[7:0]

IM3IX[7:0]

IM3IY[7:0]

IM3QX[7:0]

IM3QY[7:0]

IP3CC[1:0]

IP3IC[2:0]

LF1[1:0]

I Gain Error Adjust

Controls the I gain error over a range from –0.5dB to 0.5dB.

0x00 to 0x3F

0x00 to 0xFF

0x00 to 0x03

0x00 to 0x07

0x00 to 0x03

0x00 to 0x07

0x000 to 0x1FF

0x20

0x80

0x02

0x04

0x03

0x02

0x100

Q

HD2 I-Channel X-Vector

HD2 I-Channel Y-Vector

HD2 Q-Channel X-Vector

HD2 Q-Channel Y-Vector

HD3 I-Channel X-Vector

HD3 I-Channel Y-Vector

HD3 Q-Channel X-Vector

HD3 Q-Channel Y-Vector

IM2 I-Channel X-Vector

IM2 Q-Channel X-Vector

IM3 I-Channel X-Vector

IM3 I-Channel Y-Vector

IM3 Q-Channel X-Vector

IM3 Q-Channel Y-Vector

RF Input IP3 CC Adjust

RF Input IP3 IC Adjust

LO Matching Inductor LF1

LO Bias Adjust

Controls the I-channel HD2 X-vector adjustment if EADJ = 1.

Controls the I-channel HD2 Y-vector adjustment if EADJ = 1.

Controls the Q-channel HD2 X-vector adjustment if EADJ = 1.

Controls the Q-channel HD2 Y-vector adjustment if EADJ = 1.

Controls the I-channel HD3 X-vector adjustment if EADJ = 1.

Controls the I-channel HD3 Y-vector adjustment if EADJ = 1.

Controls the Q-channel HD3 X-vector adjustment if EADJ = 1.

Controls the Q-channel HD3 Y-vector adjustment if EADJ = 1.

Controls the I-channel IM2 X-vector adjustment if EADJ = 1.

Controls the Q-channel IM2 X-vector adjustment if EADJ = 1.

Controls the I-channel IM3 X-vector adjustment if EADJ = 1.

Controls the I-channel IM3 Y-vector adjustment if EADJ = 1.

Controls the Q-channel IM3 X-vector adjustment if EADJ = 1.

Controls the Q-channel IM3 Y-vector adjustment if EADJ = 1.

Used to optimize the RF input IP3.

Controls the LF1 inductor in the LO matching network.

Used to optimize mixer IP3.

LVCM[2:0]

PHA[8:0]

I Phase Error Adjust

Q

Controls the I phase error over a range from –2.5 Degrees to 2.5

Q

Degrees.

SDO_MODE

SRST

SDO Readback Mode

Soft Reset

Enables the SDO readback mode if SDO_MODE = 1.

Writing 1 to this bit resets all registers to their default values.

0, 1

0

Rev A

29

For more information www.analog.com

LTC5594

PACKAGE DESCRIPTION

UH Package

32-Lead Plastic QFN (5mm × 5mm)

ꢄReꢩeꢪeꢫꢬe ꢗꢍꢔ ꢈꢏꢐ ꢭ ꢂꢀꢙꢂꢮꢙꢃꢣꢯꢞ Rev ꢈꢊ

ꢂꢁꢥꢂ ±ꢂꢁꢂꢀ

ꢀꢁꢀꢂ ±ꢂꢁꢂꢀ

ꢅꢁꢃꢂ ±ꢂꢁꢂꢀ

ꢞꢁꢅꢀ ±ꢂꢁꢂꢀ

ꢞꢁꢀꢂ Rꢉꢟ

ꢄꢅ ꢆꢇꢈꢉꢆꢊ

ꢞꢁꢅꢀ ±ꢂꢁꢂꢀ

ꢑAꢔꢕAꢐꢉ ꢌꢖꢍꢗꢇꢋꢉ

ꢂꢁꢚꢀ ±ꢂꢁꢂꢀ

ꢂꢁꢀꢂ ꢒꢆꢔ

Rꢉꢔꢌꢘꢘꢉꢋꢈꢉꢈ ꢆꢌꢗꢈꢉR ꢑAꢈ ꢗAꢢꢌꢖꢍ

Aꢑꢑꢗꢢ ꢆꢌꢗꢈꢉR ꢘAꢆꢕ ꢍꢌ ARꢉAꢆ ꢍꢜAꢍ ARꢉ ꢋꢌꢍ ꢆꢌꢗꢈꢉRꢉꢈ

ꢒꢌꢍꢍꢌꢘ ꢛꢇꢉꢏꢤꢉꢝꢑꢌꢆꢉꢈ ꢑAꢈ

ꢑꢇꢋ ꢃ ꢋꢌꢍꢔꢜ R ꢦ ꢂꢁꢞꢂ ꢍꢢꢑ

ꢌR ꢂꢁꢞꢀ × ꢅꢀ° ꢔꢜAꢘꢟꢉR

R ꢦ ꢂꢁꢂꢀ

ꢍꢢꢑ

ꢂꢁꢂꢂ ꢨ ꢂꢁꢂꢀ

R ꢦ ꢂꢁꢃꢃꢀ

ꢍꢢꢑ

ꢂꢁꢥꢀ ±ꢂꢁꢂꢀ

ꢀꢁꢂꢂ ±ꢂꢁꢃꢂ

ꢄꢅ ꢆꢇꢈꢉꢆꢊ

ꢞꢃ ꢞꢚ

ꢂꢁꢅꢂ ±ꢂꢁꢃꢂ

ꢑꢇꢋ ꢃ

ꢍꢌꢑ ꢘARꢕ

ꢄꢋꢌꢍꢉ ꢣꢊ

ꢃ

ꢚ

ꢞꢁꢅꢀ ±ꢂꢁꢃꢂ

ꢞꢁꢀꢂ Rꢉꢟ

ꢄꢅꢙꢆꢇꢈꢉꢆꢊ

ꢞꢁꢅꢀ ±ꢂꢁꢃꢂ

ꢄꢖꢜꢞꢚꢊ ꢧꢟꢋ ꢂꢅꢂꢣ Rꢉꢛ ꢈ

ꢂꢁꢚꢂꢂ Rꢉꢟ

ꢂꢁꢚꢀ ±ꢂꢁꢂꢀ

ꢂꢁꢀꢂ ꢒꢆꢔ

ꢋꢌꢍꢉꢎ

ꢃꢁ ꢈRAꢏꢇꢋꢐ ꢑRꢌꢑꢌꢆꢉꢈ ꢍꢌ ꢒꢉ A ꢓꢉꢈꢉꢔ ꢑAꢔꢕAꢐꢉ ꢌꢖꢍꢗꢇꢋꢉ

ꢘꢂꢙꢚꢚꢂ ꢛARꢇAꢍꢇꢌꢋ ꢏꢜꢜꢈꢙꢄꢝꢊ ꢄꢍꢌ ꢒꢉ AꢑꢑRꢌꢛꢉꢈꢊ

ꢚꢁ ꢈRAꢏꢇꢋꢐ ꢋꢌꢍ ꢍꢌ ꢆꢔAꢗꢉ

ꢞꢁ Aꢗꢗ ꢈꢇꢘꢉꢋꢆꢇꢌꢋꢆ ARꢉ ꢇꢋ ꢘꢇꢗꢗꢇꢘꢉꢍꢉRꢆ

ꢅꢁ ꢈꢇꢘꢉꢋꢆꢇꢌꢋꢆ ꢌꢟ ꢉꢝꢑꢌꢆꢉꢈ ꢑAꢈ ꢌꢋ ꢒꢌꢍꢍꢌꢘ ꢌꢟ ꢑAꢔꢕAꢐꢉ ꢈꢌ ꢋꢌꢍ ꢇꢋꢔꢗꢖꢈꢉ

ꢘꢌꢗꢈ ꢟꢗAꢆꢜꢁ ꢘꢌꢗꢈ ꢟꢗAꢆꢜꢠ ꢇꢟ ꢑRꢉꢆꢉꢋꢍꢠ ꢆꢜAꢗꢗ ꢋꢌꢍ ꢉꢝꢔꢉꢉꢈ ꢂꢁꢚꢂꢡꢡ ꢌꢋ Aꢋꢢ ꢆꢇꢈꢉ

ꢀꢁ ꢉꢝꢑꢌꢆꢉꢈ ꢑAꢈ ꢆꢜAꢗꢗ ꢒꢉ ꢆꢌꢗꢈꢉR ꢑꢗAꢍꢉꢈ

ꢣꢁ ꢆꢜAꢈꢉꢈ ARꢉA ꢇꢆ ꢌꢋꢗꢢ A RꢉꢟꢉRꢉꢋꢔꢉ ꢟꢌR ꢑꢇꢋ ꢃ ꢗꢌꢔAꢍꢇꢌꢋ

ꢌꢋ ꢍꢜꢉ ꢍꢌꢑ Aꢋꢈ ꢒꢌꢍꢍꢌꢘ ꢌꢟ ꢑAꢔꢕAꢐꢉ

Rev A

30

For more information www.analog.com

LTC5594

REVISION HISTORY

REV

DATE

DESCRIPTION

PAGE NUMBER

A

06/18 Added T = 25°C

5, 7

J

Rev A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications

subject to change without notice. No license is ante lic othe.arw er any patent or patent rights of Analog Devices.

31

For more information www nalog.com

gr d by imp atio or ise und

LTC5594

TYPICAL APPLICATION

Simplified Schematic of a 0.5GHz to 9.0GHz Receiver, (Only I-Channel Is Shown)

ꢀꢁꢂ ꢃꢄꢅꢆꢇ

ꢀꢁꢂ ꢃꢄꢁꢅꢆ

ꢀꢁꢂ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁꢁ

ꢀꢁꢂ

ꢀꢁꢂꢃ

AꢀꢁꢂꢃAꢄꢂAꢅ

ꢀꢁꢂꢃꢄR

ꢀꢁꢂ

ꢀꢁꢀ

Aꢀꢁ

ꢀꢁꢂꢃꢃꢄꢅ

ꢀꢁꢂ ꢃꢁꢄꢅ

ꢀꢁꢂ ꢃꢄꢅꢆ

ꢀꢁꢂꢃꢂ ꢄꢅꢆꢇꢈꢉ Aꢊꢋ

Rꢀ ꢁꢂꢃꢄꢅ

ꢀꢁꢂꢃꢄꢅ ꢆꢇ ꢈꢃꢄꢅ

ꢀꢁꢂ

ꢀꢁ

ꢀꢁꢂ

Rꢀ

Aꢀꢁꢂꢃꢄ

ꢀꢁꢂꢃꢄ

R2

25Ω

ꢀꢁꢁꢁꢂꢃ

ꢃ

ꢀꢁꢀꢂꢃ

73.2Ω

ꢀ

A

ꢀꢁꢀꢂ

ꢁꢂ

R9, 25Ω

RꢀA

Aꢀꢁ

ꢀꢁꢂꢃꢄꢅꢆꢇ

ꢃ

ꢀ

A

ꢀꢁꢀꢂ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄ

ꢀꢁ

ꢀꢁꢂꢃꢄ

Rꢀ

73.2Ω

ꢁꢂ

ꢀꢁꢂ

ꢀꢁꢀꢂꢃ

ꢀ

Rꢁꢂ

ꢀꢁꢂ

ꢁꢂ

ꢀꢁꢂ ꢃꢄꢅꢆ

ꢀꢁ

ꢀꢁꢁꢁꢂꢃ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁꢀꢂꢃꢄ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂ

ꢀꢁꢁꢁꢂꢃ

ꢀꢁꢀꢂꢃꢄ

ꢀꢁ ꢂꢃꢄꢅꢆ

ꢀꢁꢂꢃꢄꢅ ꢆꢇ ꢈꢃꢄꢅ

Rꢀ

49.9Ω

R32, 10Ω

ꢀꢀꢁꢂ ꢃAꢄꢅ

RELATED PARTS

PART

NUMBER

Infrastructure

LTC5553

DESCRIPTION

COMMENTS

3GHz to 20GHz Microwave Mixer with 500MHz to 9GHz IF

3GHz to 20GHz Microwave Mixer with DC to 6GHz IF

2GHz to 14GHz Mixer with Integrated LO Doubler

Up-or-Down Conversion, 21.5dBm IIP3 at 17GHz, 0dBm LO Drive

Up-or-Down Conversion, 18.3dBm IIP3 at 17GHz, 0dBm LO Drive

LTC5552

Ultra-Wideband Bidirectional Up-, or Down-Conversion Mixer, 22.8dBm IIP3

at 12GHz, 0dBm LO Drive, 500MHz to 6GHz IF Bandwidth

LTC5549

2GHz to 14GHz Mixer with IF Frequency Extending to DC

Ultra-Wideband Bidirectional Up-, or Down-Conversion Mixer, 18.7dBm IIP3

at 12GHz, 0dBm LO Drive with On-Chip Frequency Doubler, DC to 6GHz IF

Bandwidth

LTC5548

200MHz to 6GHz Quadrature Modulator

<100kHz to 1.4GHz High OIP3 Amplifier

31dBm OIP3, –160dBm/Hz Output Noise Floor, Excellent ACPR Performance

LTC5588-1

Fixed 15dB Gain, Single-Ended 50Ω Input and Output, 41dBm OIP3 at

240MHz, 3.3dB NF

LTC6433-15

RF PLL/Synthesizer with VCO

Microwave Wideband Synthesizer with Integrated VCO

54MHz to 13.6GHz, –221dBc/Hz Normalized In-Band Phase Noise Floor

ADF5355

LTC6948

Ultralow Noise Fractional-N Synthesizer with Integrated

VCO

370MHz to 6.39GHz PLL, No ∆∑ Modulator Spurs, 18-Bit Fractional

Denominator, –226dBc/Hz Normalized In-Band Phase Noise Floor

ADCs

14-Bit, 3Gsps JESD204B Dual ADC

16-Bit, 125Msps 1.8V Dual ADC

70dB SFDR, Integrated Input Buffer

AD9208

LTC2185

LTC2158-14

76.8dB SNR, 90dB SFDR, 185mW/Channel Power Consumption

14-Bit, 310Msps 1.8V Dual ADC, 1.25GHz Full-Power

Bandwidth

68.8dB SNR, 88dB SFDR, 362mW/Ch Power Consumption, 1.32V Input

Range

P-P

Rev A

D16967-0-6/18(A)

www.analog.com

32

 ANALOG DEVICES, INC. 2018

For more information www.analog.com


型号：	LTC5594
厂家：	ADI
描述：	300MHz to 9GHz High Linearity I/Q Demodulator with Wideband IF Amplifier
文件：	总32页 (文件大小：2812K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC5594 [ADI]

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