LTC6561DICE/DWF [ADI]
Analog Circuit;
| 型号： | LTC6561DICE/DWF |
| 厂家： | 
ADI |
| 描述： | Analog Circuit |
| 文件： | 总4页 (文件大小：207K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC6561 DICE/DWF
Four-Channel Multiplexed Transimpedance
Amplifier with Output Multiplexing
24
23
22
21
PAD # PAD NAME X COORDINATE (µm) Y COORDINATE (µm)
1
2
CHSEL1
417.9
302.9
303.24
303.24
303.24
303.24
303.24
303.24
303.24
303.24
172.5
V
CCO
3
CHSEL0
187.9
1
2
3
4
20
19
18
17
4
V
CC1
72.9
5
V
–72.9
REF1
6
GND
IN1
–187.9
–302.9
–417.9
–546.21
–546.21
–546.21
–546.21
–417.9
–302.9
–187.9
–72.9
7
8
GND
IN2
9
*(0, 0)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
V
57.5
16
15
14
13
5
6
7
8
REF2
REF3
V
–57.5
IN3
GND
IN4
–172.5
–303.24
–303.24
–303.24
–303.24
–303.24
–303.24
–303.24
–303.24
–172.5
–57.5
GND
DIE ID
V
REF4
V
CC2
72.9
O_MUX
187.9
9
10
11
12
V
CCO
302.9
Die Size: 36mils (914.4µm)× 55mils (1397µm)
Bond Pad Size: 4mils (102µm)× 4mils (102µm)
Bond Pad Opening: 3.2mils (82µm)× 3.2mils (82µm)
Bond Pad Metal Thickness: 0.29mils (7.4µm)
Wafer Saw Street Width: 2.4mils (61µm)
Wafer/Die Thickness: 8mils (200µm)
Backside Metal: None
DNC
OUTTERM
GND
417.9
546.21
546.21
546.21
546.21
GND
57.5
OUT
172.5
*Die center coordinate (0, 0)
Backside Potential: V–
All registered trademarks and trademarks are the property of their respective owners.
FEATURES
n
n
220MHz –3dB Bandwidth with 2pF Input Capacitance
Single 5V Supply
n
n
Single-Ended Output
200mW Power Dissipation for 4 Channels
n
n
74kΩ Transimpedance Gain
2V Output Swing on 100Ω Load
n
P-P
n
4.8pA/√Hz Input Current Noise Density at
Output MUX Combines Multiple 4-Channel Devices to
Create 4, 8,12,16, 24, 32 Channel Solutions
200MHz (2pF)
n
64nA
Integrated Input Current Noise Over
RMS
200MHz (2pF)
APPLICATIONS
n
n
n
n
Linear Input Range 0µA to 30µA
Overload Current > 400mA Peak
Fast Overload Recovery 12ns, 1mA
Fast Channel Switchover < 50ns
n
LIDAR Receiver
Industrial Imaging
n
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
1
LTC6561 DICE/DWF
DESCRIPTION
®
is needed and the device consumes only 200mW. Utilizing
the internal 4-to-1 MUX along with the LTC6561’s output
MUX; multiple 4-channel LTC6561 devices can be com-
bined to directly interface with 12-, 16- and 32-channel
APD arrays. The LTC6561’s fast overload recovery and
fast channel switchover make it well suited for LIDAR
receivers with multiple APDs. Its single-ended output can
The LTC 6561 is a low-noise, four-channel, transimped-
anceamplifier(TIA)with220MHzbandwidth.TheLTC6561
multi-channel transimpedance amplifier’s low noise, high
transimpedance, and low power dissipation are ideal for
LIDARreceiversusingAvalanchePhotodiodes(APDs).The
amplifier features 74kΩ transimpedance gain and 30µA
linear input current range. Using an APD input circuit with
a total capacitance of 2pF, the input current noise density
is 4.8pA/√Hz at 200MHz. With lower capacitance, noise
and bandwidth improve further. Only a 5V single supply
swing 2V on a 100Ω load while its low impedance op
P-P
amp style output can drive back-terminated 50Ω cables.
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Total Supply Voltage (V , V , V
to GND)......5.5V
Amplifier Output Current (OUT, OUTTERM)..........+80mA
Operating Temperature Range
LTC6561............................................. –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
Junction Temperature ........................................... 150°C
CC1 CC2 CCO
Input Voltage (CHSEL0, CHSEL1, O_MUX).....–0.3V to 5.5V
Amplifier Reference Current (V , V
,
REF1 REF2
)........................................................ 10mA
Amplifier Input Current (IN1, IN2,
V
, V
REF3 REF4
IN3, IN4)................. 400mA RMS 2A Transient (10ns)
DIE CROSS REFERENCE
FINISHED PART NUMBER
ORDER PART NUMBER
LTC6561 DICE/DWF
LTC6561
Please refer to ADI standard LTC6561 product data sheet for other applicable product information and typical performance information.
AC ELECTRICAL CHARACTERISTICS TA = 25°C, VCC1,2 = VCC0 = 5V, O_MUX = 0V, GND = 0V, ZLOAD = 100Ω.
Output taken from OUT pin.
SYMBOL
PARAMETER
CONDITIONS
200mV
MIN
TYP
220
74
MAX
UNITS
MHz
kΩ
BW
–3dB Bandwidth
and C
= 2pF
P-P,OUT
IN,TOT
R
R
R
Small Signal Transimpedance
Input Resistance
I
< 2µA
P-P
63
85
T
IN
f = 100kHz
236
3
Ω
IN
Output Resistance
f = 100kHz
Ω
OUT
I
Input Current Noise Density
f = 100MHz, C
f = 200MHz, C
= 2pF
= 2pF
4.3
4.8
43
pA/√Hz
pA/√Hz
n
IN,TOT
IN,TOT
Integrated Input Current Noise
f = 0.1MHz to 100MHz, C
f = 0.1MHz to 200MHz, C
f = 100MHz
= 2pF
nA
nA
IN,TOT
IN,TOT
RMS
= 2pF
64
RMS
Adjacent Channel to Channel Isolation
Non Adjacent Channel Isolation
Overload Recovery Time
–45
–65
12
dB
f = 100MHz
dB
ns
ns
t
t
Input Pulse <1mA
RECOVER
SWITCH
Channel Switchover Time
50
2
LTC6561 DICE/DWF
DC ELECTRICAL CHARACTERISTICS TA = 25°C, VCC1,2 = VCC0 = 5V, O_MUX = 0V, GND = 0V, ZLOAD = 100Ω.
Output taken from OUT pin.
SYMBOL
PARAMETER
Pins
CONDITIONS
MIN
TYP
MAX
UNITS
IN1,2,3,4 Pins and V
REF1,2,3,4
V
V
Input Bias Voltage
Active Channel
1.43
0.78
1.55
0.93
1.64
1.38
V
V
IN
Inactive Channel
Input Reference Voltage
Active Channel
Inactive Channel
1.43
1.34
1.55
1.50
1.63
1.67
V
V
REF
Offset
V
IN
– V
Active Channel
Inactive Channel
–12
–741
12
–116
mV
mV
REF
OUT Pin
V
OUT
Output Default Voltage
O_MUX = 0V (Output Enabled)
O_MUX = 3.3V, Standalone Device
0.83
0.32
1.10
0.60
1.47
0.88
V
V
OVR
Output Voltage Range
I
IN
Current Range = 0 to –50µA
1.22
44
1.90
56
2.58
70.8
V
P-P
OUTTERM
Internal Series Resistor for Optional Output
Ω
CHSEL0, CHSEL1, O_MUX Pins with Internal Pull-Down Resistors
V
V
0.7
V
V
IL
1.5
16.9
37
IH
I
I
Pin Voltage = 0.7V
Pin Voltage = 1.5V
20.7
47
26.0
57
µA
µA
pF
IL
IH
C
IN
1.5
29
R
22
35
kΩ
IN
Power Supply
V
Operating Supply Range
Input Supply Current
Output Supply Current
4.75
29
5
5.25
44
V
mA
mA
S
I
I
V
& V are Internally Tied Together
36.3
2.3
CC1,2
CC0
CC1
CC2
Both V
Together
Pins are Internally Tied
1.8
2.8
CCO
I
Total Supply Current (I
+ I )
S(VCC0)
30.8
21
38.6
25
46.8
mA
dB
dB
S
S(VCC1,2)
PSRR(V
PSRR(V
)
Input Power Supply Rejection Ratio
Output Power Supply Rejection Ratio
V
V
= 4.75V to 5.25V, V
= 5V
= 5V
CC1,2
CC1,2
CC0
)
CC0
= 4.75V to 5.25V, V
34
40
CC0
CC1,2
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All measurement were conducted in the dark.
3
LTC6561 DICE/DWF
PAD FUNCTIONS
CHSEL1: MSB for Channel Selection. CMOS input. The
CHSEL1 pad has a 29kΩ internal pull-down resistor.
Default value is 0V.
to V , it will float to a default voltage of approximately
REF
1.55V on a 5V supply. Each V pad should be bypassed
REF
withahighqualityceramicbypasscapacitorofatleast0.1µF.
The bypass cap should be located close to its V pad.
REF
V
CCO
:PositivePowerSupplyfortheOutputStage.Typically5V.
CCO
V
can be tied to V or V for single supply operation.
GND: Negative Power Supply. Normally tied to ground.
CC1
CC2
Between the positive supply and ground, bypass capacitors
of 1000pF and 0.1µF should be placed as close to the part as
IN1, IN2, IN3, IN4: Input Pad for Transimpedance Ampli-
fier for Channels 1, 2, 3, and 4 Respectively. This pad is
internally biased to 1.55V.
possible. V
pads are internally tied together.
CCO
CHSEL0: LSB for Channel Selection. CMOS input. The
CHSEL0 pad has a 29kΩ internal pull-down resistor.
Default value is 0V.
O_MUX: Output MUX. CMOS Input. This pad is functional
when multiple LTC6561s are combined at the output. When
O_MUX is low, the output is enabled. When O_MUX is high,
all 4 inputs are decoupled from the output. Default value is
0V. This MUX pad is ineffective unless a 2nd LTC6561 is DC-
coupledattheoutput. SeeApplicationssectiononhowtouse
O_MUXtoexpandthechannelcountwithmultipleLTC6561’s.
The O_MUX pad has a 29kΩ internal pull-down resistor.
V
, V : Positive Power Supply. Typically 5V. Between
CC1 CC2
the positive supply and ground, bypass capacitors of
1000pF and 0.1µF should be placed as close to the part
as possible. V
and V
are internally tied together.
CC1
CC2
V
, V
, V
, V
: Reference Voltage Pad for
REF1
REF2
REF3
REF4
Transimpedance Amplifier in Channel 1, 2, 3, and 4 Re-
spectively. This pad sets the input DC voltage for each
DNC: Do not connect.
OUTTERM:TIAOutputwithanInternalSeries50ΩResistor.
OUT: TIA Output without an internal series 50Ω Resistor.
transimpedance amplifier. The V
pad has a Thevenin
REF
equivalent resistance of approximately 1.4k and can be
overdriven by an external voltage. If no voltage is applied
BLOCK DIAGRAM
V
V
CC1,2
CCO
IN1
TIA
TIA
TIA
TIA
V
REF1
IN2
V
REF2
OUT
4:1
MUX
OUTPUT
STAGE
IN3
V
REF3
50Ω
GAIN
OUTTERM
IN4
V
REF4
GND
CHSEL0,1
O_MUX
6561 BD
Wafer level testing is performed per indicated specifications for dice. Considerable differences in performance can often be observed for dice versus
packaged units due to the influences of packaging and assembly on certain devices and/or parameters. Please consult factory for more information
on dice performance and lot qualifications via lot sampling test procedures.
Dice data sheet subject to change. Please consult factory for current revision in production.
I.D.No. 66-13-6561
01/19(0)
www.analog.com
4
ANALOG DEVICES, INC. 2019
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