LTC6812-1_技术文档

LTC2949

Current, Voltage, and Charge Monitor for

High Voltage Battery Packs

FEATURES

DESCRIPTION

The LTC^®2949 is a high precision current, voltage, tem-

perature,chargeandenergymeterforelectricalandhybrid

vehicles and other isolated current sense applications. It

infers charge and energy flowing in and out of the battery

pack by monitoring simultaneously the voltage drop over

up to two sense resistors and the battery pack voltage.

n

Measures Battery Stack Voltage, Current and Power

Indicates Accumulated Battery Charge and Energy

20-Bit Current Measurement with <1μV Offset

Built-In Isolated isoSPI™ or SPI Interface

LTC68xx/ADBMS68xx Compatible, Supports

Synchronous Measurements with Cell Monitors

Up to 12 Buffered Voltage Measurement Inputs

Up to 5 GPIOs, Configurable to Drive Ground, Supply

or Toggling at 400kHz

n

Low offset ΔΣ ADCs ensure accurate measurement of

voltage and current with insignificant power loss. Con-

tinuous integration of current and power ensures lossless

tracking of charge and energy delivered or received by

the battery pack.

n

High or Low Side Current Sense

0.3% Current and Voltage Accuracy

1% Energy and Charge Accuracy

True Average ADCs

The built-in serial interface can be configured to support

isolated isoSPI communication to the host or as SPI

interface.

2

I C EEPROM Interface to Store Board Calibration Factors

Threshold Registers for all Measured Quantities

Engineered for ISO26262 Compliant Systems

Open Wire Detection on Input Pins

The LTC2949 features 12 internally buffered high imped-

ance inputs (V1 to V12) for measuring voltages from

external sensors or resistor dividers allowing to measure

temperatures, HV-Link voltages, chassis isolation and

supervise contactor states. LTC2949 has up to five pro-

grammable digital outputs which can be set to ground,

supply or toggling at 400kHz.

Available in 48-Lead LQFP Package

AEC-Q100 Qualified for Automotive Applications

APPLICATIONS

n

Electric and Hybrid Vehicles

n

Isolated Current Sensing

Programmable threshold and tracking registers reduce

digital traffic to the host.

n

Backup Battery Systems

High Power Portable Equipment

n

All registered trademarks and trademarks are the property of their respective owners.

TYPICAL APPLICATION

Electric Vehicle Battery Meter

ꢂ

ꢄ

ꢀꢁ

ꢀAꢁ

ꢀꢁꢁꢂ

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ꢀꢁꢂꢃ

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RꢆꢁꢀꢁꢄAꢅꢇꢆ

ꢀꢁꢂꢃꢄꢅ ꢆ

ꢀꢁꢀꢂ

Aꢀꢁꢁ

ꢀꢁꢂꢂ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄꢅ

ꢀꢁꢂꢃꢄꢅꢄ

ꢀꢁꢂ

ꢀꢁꢂꢃ ꢄꢅꢀꢆAꢇꢈ

ꢀꢁꢀꢂ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄꢅ A

ꢀꢁꢂꢃ

ꢀꢁꢂ

ꢀꢀꢁ

ꢀꢁ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄ

ꢀꢁ

ꢀꢁꢂꢂ

ꢃꢄꢅꢆꢇꢄRꢈ

ꢀRꢁꢂ

ꢀAꢁꢂ

ꢀꢁꢁꢂ

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ꢃꢄꢃRꢅꢆ

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ꢄꢅꢆꢁAꢇꢈ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄꢅ ꢆ

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ꢀAꢁꢂ

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ꢀAꢁꢂꢃR

ꢀꢁꢂ

ꢀꢁꢂꢃꢄꢅꢆ

ꢀꢁꢂ

ꢀꢁRRꢂꢃꢄ

ꢀꢅARꢆꢂ

ꢀꢁꢂꢃꢁRAꢀꢄRꢁ

ꢀꢁꢂꢃꢄꢅ

ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄꢅ ꢀꢁꢂ

ꢀꢁꢂ

ꢀꢁꢁꢂ

ꢀꢁꢂꢃꢄꢅ A

ꢀꢁꢂ

ꢀꢁꢂꢃAꢄꢅꢆ ꢇꢂꢈꢈꢉꢊꢀꢇAꢄꢀꢂꢊ

ꢄ

50µΩ

ꢀꢁ

ꢀꢁꢂꢃ

ꢂ

ꢀꢁ

ꢀAꢁ

ꢀꢁꢂꢁ ꢃAꢄꢅ

Rev A

1

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LTC2949

TABLE OF CONTENTS

Features............................................................................................................................ 1

Applications ....................................................................................................................... 1

Typical Application ............................................................................................................... 1

Description......................................................................................................................... 1

Absolute Maximum Ratings..................................................................................................... 3

Order Information................................................................................................................. 3

Pin Configuration ................................................................................................................. 3

Electrical Characteristics........................................................................................................ 4

Typical Performance Characteristics .........................................................................................10

Pin Functions.....................................................................................................................11

Pin Functions.....................................................................................................................12

Block Diagram....................................................................................................................13

Operation..........................................................................................................................14

Overview............................................................................................................................................................... 14

Modes of Operation .............................................................................................................................................. 15

Data Acquisition Channels .................................................................................................................................... 16

Power Measurement............................................................................................................................................. 19

Charge, Energy and Time...................................................................................................................................... 20

Overcurrent Comparators ..................................................................................................................................... 21

SERIAL INTERFACES ............................................................................................................22

Serial Interfaces Overview .................................................................................................................................... 22

4-Wire Serial Peripheral Interface (SPI) Physical Layer........................................................................................ 22

2-Wire Isolated Interface (isoSPI) Physical Layer................................................................................................. 23

Data Link Layer..................................................................................................................................................... 28

Network Layer....................................................................................................................................................... 28

REGISTER MAP...................................................................................................................41

REGISTER Description ..........................................................................................................42

MEMORY MAP AND Paging Mechanism............................................................................................................... 42

Register Map PAGE0............................................................................................................................................. 44

Register Map PAGE1 ............................................................................................................................................ 62

Application Information.........................................................................................................68

Temperature Measurement .................................................................................................................................. 68

Sense Resistor Temperature Compensation ......................................................................................................... 69

Current and Voltage Input Filtering ....................................................................................................................... 74

Powering the LTC2949 ......................................................................................................................................... 75

Package Description ............................................................................................................78

Revision History .................................................................................................................79

Typical Application ..............................................................................................................80

Related Parts.....................................................................................................................80

Rev A

2

For more information www.analog.com

LTC2949

ABSOLUTE MAXIMUM RATINGS

(Notes 1, 2)

Supply Pins

PIN CONFIGURATION

ꢔꢚꢒ ꢊꢖꢘꢝ

AVCC to AGND........................................ –0.3V to 14.5V

DVCC to DGND........................................ –0.3V to 14.5V

AVCC to DVCC........................................... –0.1V to 0.1V

DGND to AGND......................................... –0.1V to 0.1V

Analog Pins

ꢊꢀ

ꢊꢁ

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢆ

ꢇ

ꢈ

ꢂꢅ ꢋꢌꢍ

ꢂꢄ ꢊRꢘꢗ

ꢊꢂ

ꢂꢃ ꢍꢏꢙꢚ

ꢊꢃ

ꢊꢄ

ꢋꢌꢍ

ꢊꢅ

ꢊꢆ

ꢊꢇ

ꢂꢂ ꢍꢏꢙꢖ

I1P, I1M, I2P, I2M ......................... –0.3V to V

+ 0.3V

AVCC

ꢂꢁ ꢋꢌꢍ

I1P to I1M, I2P to I2M .............................................. 1V

ꢃꢈ

ꢓꢌꢋ

ꢂꢀ ꢋꢌꢍ

ꢂꢉ ꢍꢎꢐ ꢛꢖꢕꢜ

ꢁꢈ ꢎꢍꢙ ꢛꢖꢒꢜ

ꢁꢇ ꢎꢋꢚ ꢛꢖꢐꢖAꢎꢜ

ꢁꢆ ꢎꢋꢖ ꢛꢖꢍꢕꢒꢜ

ꢁꢅ ꢖꢚꢊꢍꢍ

ꢁꢄ ꢐꢑꢒꢁ

VBATP, VBATM ............................. –0.3V to V

V1-V12......................................... –0.3V to V

+ 0.3V

AVCC

ꢊꢈ ꢀꢉ

ꢊꢀꢉ ꢀꢀ

ꢊꢀꢀ ꢀꢁ

CLKO, DNC.........................................................(Note 3)

Digital Input/Output Pins

IOVCC, CLKI, CSB(IM), SCK(IP)................... –0.3V to 5V

SDI (ICMP), SDO (IBIAS)............................. –0.3V to 5V

SDA, SCL ................................................ –0.3V to 2.75V

Current In/Out of Pins

IP, IM.................................................................... 30mA

SDO (IBIAS) .............................................. –1mA to 9mA

V8-V12 ................................................................... 2mA

VREF (Note 4) ....................................................... 2mA

BYP1 (Note 4)......................................... –10mA to 0mA

BYP2 (Note 4)......................................... –10mA to 0mA

Operating Ambient Temperature Range

ꢏꢞꢘ ꢒAꢍꢙAꢓꢘ

ꢃꢇꢟꢏꢘAꢋ ꢛꢆꢠꢠ × ꢆꢠꢠꢜ ꢒꢏAꢎꢔꢖꢍ ꢏꢡꢗꢒ

ꢋꢌꢍꢢ ꢋꢚ ꢌꢚꢔ ꢍꢚꢌꢌꢘꢍꢔ

ꢤ ꢀꢄꢉꢥꢍꢦ θ ꢤ ꢁꢉꢧꢃꢅꢥꢍꢨꢝꢦ θ ꢤ ꢂꢧꢅꢇꢥꢍꢨꢝ

ꢣA ꢣꢍ

ꢘꢞꢒꢚꢎꢘꢋ ꢒAꢋ ꢛꢒꢖꢌ ꢃꢈꢜꢦ ꢍꢚꢌꢌꢘꢍꢔ ꢔꢚ Aꢓꢌꢋ

ꢔ

ꢣꢕAꢞ

LTC2949I .................................................–40°C to 85°C

LTC2949H.............................................. –40°C to 125°C

Storage Temperature Range…............... –65°C to 150°C

ORDER INFORMATION

AUTOMOTIVE PRODUCTS**

TRAY (250PC)

TAPE AND REEL (2000PC) PART MARKING*

LTC2949ILXE#3ZZTRPBF LTC2949LXE

LTC2949HLXE#3ZZTRPBF LTC2949LXE

PACKAGE DESCRIPTION

48-LEAD PLASTIC eLQFP

MSL RATING TEMPERATURE RANGE

LTC2949ILXE#3ZZPBF

LTC2949HLXE#3ZZPBF

3

–40°C to 85°C

–40°C to 125°C

Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.

**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These

models are designated with a #3ZZ suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your local

Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models.

Rev A

3

For more information www.analog.com

LTC2949

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Power Supply

l

V

Analog Supply Voltage

4.5

14

V

AVCC

DVCC

UVLO

Digital Supply Voltage

Supply Undervoltage Lockout Threshold

Average Supply Current into AVCC and DVCC

V

, V

Falling

4.5

20

V

AVCC DVCC

I

CC

Core State: STANDBY or MEASURE

Core State: SLEEP

16

9

mA

µA

mA

V

15

l

Core State: SLEEP

150

5.8

7.8

3

Additional DVCC Supply Current if isoSPI in

READY/ACTIVE States

R

+ R = 2k

READY

ACTIVE

READY

ACTIVE

4.8

6.1

2.1

2.5

B1

B2

Note: ACTIVE State Current Assumes t = 1μs,

(Note 5)

CLK

R

+ R = 20k

B2

3.5

2.75

0

V

BYP1 Regulated Output Voltage

BYP1 Load Current

2.25

–10

–15

BYP1

mA

mV

V

BYP1 Load Regulation Error

BYP1 Undervoltage Lockout Threshold

BYP2 Regulation Output Voltage

BYP2 Load Current

I

= –10mA

0

LOAD

2.25

3.6

0

3

3.25

170

V

BYP2

–10

–60

mA

mV

°C

BYP2 Load Regulation Error

Thermal Shutdown Temperature

Current Sense ADC

Resolution (No Missing Codes)

l

Slow Mode Filtered (Note 7)

Slow Mode (Note 7)

20

18

15

Bit

mV

V

Fast Mode (Note 7)

Full-Scale Differential Input Voltage

Differential Input Voltage Range

Pin Voltage of I1P, I1M, I2P, I2M

Current Sense Quantization Step

V

-V , V -V

124

I1P I1M I2P I2M

l

VDIF

-V , V -V

I1P I1M I2P I2M

110

I

–0.11

V

+0.11

AVCC

Slow Mode Filtered

Slow Mode

237.5

950

nV

µV

nA

Fast Mode

7.60371

l

CFPx

Input Leakage Current at CF1P, CF1M, I1P,

I1M, CF2P, CF2M, I2P, I2M

Core State = SLEEP/STANDBY

60

Differential Input Current from CF1P to CF1M,

CF2P to CF2M

Core State: MEASURE; Pin Voltages: 0V ≤

VDIF /100kΩ

µA

I

V

, V

, V , V , V

, V

,

CF1P CF1M I1P I1M CF2P CF2M

V

, V ≤ V

I2P I2M

AVCC

Noise

Slow Mode Filtered

Slow Mode

160

320

3

nV

µV

RMS

Fast Mode

RMS

Gain Error

|VDIF | ≤ 110mV

0.15

0.3

1

%

I

l

%

µV

%

Offset Voltage

IADCx, IxP, IxM = 0V

Slow Mode

Fast Mode

0

V

|

= V

= 5V

2

AVCC

DVCC

|

Total Unadjusted Error

VDIF ≥ 25mV

0.3

I

Rev A

4

For more information www.analog.com

LTC2949

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

0.8211

4.8

UNITS

dB

l

Input Voltage Common Mode Rejection at DC

Input Sampling Frequency

Conversion Time

100

10.48

400

MHz

ms

Slow Mode Filtered

Slow Mode

100

ms

l

Fast Mode

0.782

ms

Voltage Measurement by Power ADC

l

Resolution (No Missing Codes)

Slow Mode (Note 7)

Fast Mode (Note 7)

18

15

Bit

V

VFS

Full-Scale Differential Input Voltage

Differential Input Voltage Range

Pin Voltage of VBATP, VBATM

V

– V

6.14

V

VBATP

VBATM

l

VDIF

V

≥ 5V

< 5V

–0.1

V

+0.1

AVCC

V

AVCC

V -1.5

AVCC

V

LSB

Differential Input Voltage Quantization Step

Slow Mode

46.875

µV

nA

MΩ

%

V

Fast Mode

375.183

l

Input Leakage Current

Core State: SLEEP/STANDBY

Core State: MEASURE; Pin Voltages 0V

60

Differential Input Resistance

50

20

≤ V

, V

≤ V

BATP BATM AVCC

l

Gain Error

0.3

3

Offset

V

BATP

= V

= 0V

0

LSB

V

BATM

Voltage Total Unadjusted Error

Input Voltage Common Mode Rejection at DC

Noise

1V ≤ |VDIF | ≤ 4.8V

0.4

%

V

80

dB

Slow Mode (Note 7)

Fast Mode (Note 7)

3

µV

RMS

30

Input Sampling Rate

Conversion Time

5.24

100

0.782

MHz

ms

Slow Mode

Fast Mode

l

0.8211

ms

Power Measurement by Power ADC

Resolution (No Missing Codes)

l

Slow Mode (Note 7)

Fast Mode (Note 7)

18

11

Bit

2

FS

Full-Scale Power

FS = VFS • VFS /R

/VDIV

v

0.76504

5.8368

1

[V /Ω]

P

V

I

ISENSE

17

2

LSB

Power Quantization Step

Power Offset

LSB = FS /2

µ[V /Ω]

P

POS

TUE

VDIF = 0

LSB

P

1

l

Power Total Unadjusted Error

1V ≤ |VDIF | ≤ 4.8V, 25mV ≤ |VDIF | ≤

0.9

%

P

V

I

110mV

RMS Noise

Slow Mode; VBATP – VBATM = 4.8V (Note 7)

Slow Mode; VBATP – VBATM = 0V (Note 7)

0.3

0.03

5.24

100

LSB

P

LSB

P

Input Sampling Frequency

Power Modulation Frequency

Conversion Time

MHz

ms

Slow Mode

Fast Mode

l

0.782

0.8211

ms

Rev A

5

For more information www.analog.com

LTC2949

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C.

SYMBOL

Energy Measurement

TUE Energy Total Unadjusted Error

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

1V ≤ |VDIF | ≤ 4.8V, 25mV ≤ |VDIF | ≤

0.9

%

E

V

I

110mV, Ideal External Clock or 4MHz

Crystal

1V ≤ |VDIF | ≤ 4.8V, 25mV ≤ |VDIF | ≤

1.9

%

V

I

110mV, Internal Clock

Charge Measurement

TUE Charge Total Unadjusted Error

l

1V ≤ |VDIF | ≤ 4.8V, 25mV ≤ |VDIF | ≤

0.4

1.4

%

C

V

I

110mV, Ideal External Clock or 4MHz

Crystal

1V ≤ |VDIF | ≤ 4.8V, 25mV ≤ |VDIF | ≤

V

I

110mV, Internal Clock

Voltage Measurement by AUXILIARY ADC

l

Resolution (No Missing Codes)

(Note 7)

15

Bit

V

VFS

Full-Scale Differential Input Voltage

Differential Input Voltage Range

V

– V

, V

– V

6.14

AUX

VBATP

VBATM MUXP

MUXN

l

VDIF

, V

VBATM MUXP

4.8

V

AUX

MUXN

Pin Voltage of VBATP, VBATM, V1 – V12, CF1P,

CF1M, CF2P, CF2M

≥ 5V

< 5V

–0.1

V

+0.1

AVCC

V

AVCC

–1.5

AVCC

V

LSB

Differential Voltage Quantization Step

Slow Mode

Fast Mode

375

375.183

1

µV

nA

MΩ

%

AUX

l

Input Leakage Current

Differential Input Resistance

Gain Error

60

40

80

13

|VDIF | ≤ 4.8V

0.3

1

AUX

Offset

V

BATP

= V

= 0V

0

LSB

V

BATM

Total Unadjusted Error

Input Voltage Common Mode Rejection at DC

Sampling Rate

1V ≤ |VDIF | ≤ 4.8V

0.4

%

dB

V

5.24

MHz

ms

l

Conversion Time

0.782

0.8211

On-Die Temperature Measurement by AUXILIARY ADC

Resolution (No Missing Codes)

(Note 7)

Bit

K

Full-Scale Temperature

819.2

0.2

3

ΔT

Temperature Quantization Step

Total Unadjusted Error

Conversion Time

K

LSB

K

13.1

20

ms

K/W

Self-Heating

Supply Voltage Measurement by AUXILIARY ADC

Resolution (No Missing Codes)

Full-Scale Differential Input Voltage

A/DVCC Measurement Quantization Step

Total Unadjusted Error

l

(Note 7)

14

Bit

V

18.43

2.2583

2

mV

%

5

Conversion Time

6.55

ms

AUX MUX

Signal Range

–0.1

V

+0.1

AVCC

V

Rev A

6

For more information www.analog.com

LTC2949

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

–250

250

MAX

UNITS

µA

l

Pull-Up Current Source

Pull-Down Current Source

Pin Voltage < V

− 3.0V

–150

AVCC

Pin Voltage > 2.5V

200

µA

Reference Voltages

VREF

Reference Pin Voltage

3

V

%

l

VREF Error

1

VREF Temperature Coefficient

VREF Long Term Drift

7

ppm/K

ppm/√kHr

mV

80

l

VREF Load Regulation Error

Internal Redundant Reference Voltage

VREF2 Error

–0.5mA ≤ I

≤ 0.5mA

–5

0

LOAD

VREF2

2.39

V

0.85

%

VREF2 Temperature Coefficient

VREF2 Long Term Drift

10

80

ppm/K

ppm/√kHr

Overcurrent Comparator

Pin Voltages I1P, I1M I2P, I2M

l

–0.11

V

+0.11

V

mV

µs

AVCC

Total Unadjusted Error

|Vthr| ≤ 103mV

|Vthr| > 103mV

|Vthr| = 310mV

5

10

20

Programmable Deglitch Time Delay

T

20, 80, 320µs

T

−10

T

+37

degl

1280µs

−26

+56

µs

Digital Input CLKI

l

Logic Input Threshold

Input Current DC Current

Input Capacitance

0.4

2

V

μA

1

(Note 7)

10

25

pF

External Clock Frequency

General Purpose Outputs GPIOx

0.1

MHz

l

Low Level Output Voltage at GPIOx

I

= 0.5mA

0.4

V

GPIOx

High Level Output Voltage at GPIOx

= –0.25mA

V

DVCC

–0.5

l

GPIOx Toggling Frequency

370

400

430

kHz

SPI Interface DC Specification IOVCC, CSB, SCK, SDI, SDO

l

V

IOVCC

SPI Mode IOVCC Operating Voltage

Pin Voltages CSB, SCK, SDI, SDO

Logic Input Threshold (CSB, SCK, SDI)

1.8

4.5

V

IOVCC

0.3 •

IOVCC

0.7 •

V

IOVCC

V

l

DC Input Current (CSB, SCK, SDI)

Input Capacitance (CSB, SCK, SDI)

Low Level Output Voltage at SDO

1

µA

pF

V

(Note 7)

≥ 3.3V, I

10

V

= 3mA, 1.8V ≤ V

IOVCC

0.4

IOVCC

SDO

≤ 3.3V, I

= 1mA

SDO

SPI Timing Requirements (See Figure 7)

l

t

SCK Period

(Note 6)

1

μs

ns

CLK

1

SDI Setup Time Before SCK Rising Edge

SDI Hold Time After SCK Rising Edge

25

2

Rev A

7

For more information www.analog.com

LTC2949

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C.

SYMBOL

PARAMETER

CONDITIONS

MIN

200

0.65

0.8

1

TYP

MAX

UNITS

ns

l

t

SCK Low

t

= t + t ≥ 1μs

3 4

3

4

5

6

7

8

CLK

SCK High

= t + t ≥ 1μs

ns

3

4

CSB Rising Edge to CSB Falling Edge

SCK Rising Edge to CSB Rising Edge

CSB Falling Edge to SCK Rising Edge

SCK Falling Edge to SDO Valid

μs

(Note 6)

μs

(Note 9), VIOVCC ≥ 3.3V

(Note 9), VIOVCC < 3.3V

60

ns

150

ns

isoSPI DC Specifications (See Figure 10)

l

Voltage at IOVCC to Select isoSPI

0.5

2.1

V

IBIAS

Voltage on IBIAS Pin

READY/ACTIVE State

IDLE

1.9

2

0

V

l

I

Isolated Interface Bias Current

Isolated Interface Current Gain

R

= 2kΩ to 20kΩ

BIAS

0.1

18

17

1

22

24.5

1.4

1.5

1

mA

B

A

V ≤ 1V, I = 1mA

A

20

mA/mA

V

IB

B

I = 0.1mA

B

V

Transmitter Pulse Amplitude

V = |V – V

A

|

A

IP

IM

Threshold-Setting Voltage on ICMP Pin

Input Leakage Current on ICMP Pin

Leakage Current on IP and IM Pins

Receiver Comparator Threshold Voltage Gain

V

= A

• V

ICMP

0.2

0.4

V

ICMP

TCMP

ICMP

TCMP

= 0V to V

µA

BYP2

IDLE State, V or V = 0V to V

1

µA

IP

IM

BYP2

A

V

= V

/2 to V

– 0.2V,

0.5

0.6

V/V

TCMP

CM

ICMP

BYP2

= 0.2V to 1.5V

Receiver Common Mode Bias

IP, IM Not Driving

V

–

V

CM

BYP2

/3 –

ICMP

167mV

l

Receiver Input Resistance

Single-Ended to IP, IM

27

35

43

kΩ

isoSPI IDLE/WAKE-UP Specifications (See Figure 3)

l

V

Differential Wake-Up Voltage

Dwell Time at V Before Wake Detection

t

= 240ns

DWELL

200

240

mV

ns

WAKE

DWELL

READY

IDLE

t

V

= 200mV

WAKE

Start-Up Time After Wake Detection

Idle Timeout Duration

10

8

µs

4.3

6.4

ms

isoSPI Pulse Timing Specifications (See Figures 10,11)

l

t

Chip-Select Signal Filter

Chip-Select Valid Pulse Window

Data Half-Pulse Width

Data Signal Filter

Receiver

70

220

40

90

270

50

115

330

60

ns

FILT(CS)

WNDW(CS)

1/2PW(D)

FILT(D)

Receiver

Transmitter

Receiver

10

25

35

Data Pulse Inversion Delay

Data Valid Pulses Window

Data Return Delay

Transmitter

Receiver

40

55

69

INV(D)

70

90

110

625

WNDW(D)

485

RTN

2

I C Interface DC Specification (SCL, SDA)

Logic Input Threshold (SDA)

l

0.9

1.6

1

V

μA

pF

V

DC Input Current (SDA)

Input Capacitance (SDA)

(Note 7)

10

0.4

Low Level Output Voltage at SDA, SCL

I = 0.5mA

Rev A

8

For more information www.analog.com

LTC2949

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

2

I C Interface Timing Specification (SCL, SDA)

l

f

t

Maximum SCL Clock Frequency

SCL Low Period

8

10

kHz

µs

SCL(MAX)

SCLLO

80

30

SDA Low Period

SDALO

Bus Free Time Between STOP/START

Minimum Repeated START Setup Time

BUF(MIN)

SU,STA(MIN)

HD,STA(MIN)

Minimum Hold Time (Repeated) START

Condition

l

t

Minimum Setup Time for STOP Condition

Minimum Data Setup Time Input

Minimum Data Hold Time Input

Minimum Data Hold Time Output

Data Output Fall Time

30

µs

ns

µs

ns

SU,STO(MIN)

SU,DAT(MIN)

HD,DAT(MIN)

HD,DATO

0

30

(Notes 7, 8)

20 + 0.1

OF

• C

B

Digital Core Timings (See Figure 3)

l

t

Core Boot-Up Time from SLEEP or POWER-OFF AVCC/DVCC Pins at Minimum Operating

100

ms

BOOT

to STANDBY

Voltage

l

t

Core STANDBY Cycle Time

(Note 10)

17

20

110

130

40

ms

s

IDLE_CORE

Core MEASURE Cycle Time

(Note 11)

90

100

CONT

Memory Lock Request to Acknowledge Time

Core Status MEASURE

Core Status STANDBY

MLCK,M

MLCK,S

ACKN

Time from Core Entering STANDBY to Return to No Write of 0x0 to Reg. WKUPACK, No

SLEEP, When Wake-Up is not Confirmed

0.6

1.5

Write of 0x8 to Reg. OPCTRL

Time Base

TUE

TUE Time Base

Internal Clock

0.5

1

%

TB

l

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect the device

reliability and lifetime.

Note 6: These timing specifications are dependent on the delay through

the cable, and include allowances for 50ns of delay each direction. 50ns

corresponds to 10m of CAT-5 cable (which has a velocity of propagation of

66% the speed of light). Use of longer cables would require derating these

specs by the amount of additional delay.

Note 2: Positive currents flow into pins, negative currents flow out of pins.

Minimum and maximum values refer to absolute values.

Note 7: Guaranteed by design and characterization, not subject to

production test.

Note 3: Do not apply a voltage or current source to these pins. They must

be unconnected, connected to capacitive loads or connected to a crystal

according to their pin description. Otherwise permanent damage may

occur.

Note 4: Do not apply a voltage source to these pins. Overloading these

pins might disrupt operation.

Note 8: C = capacitance of one bus line in pf (10pF < C < 400pF)

B

Note 9: These specifications do not include rise time of SDO due to pull up

resistance and load capacitance on SDO pin.

Note 10: Cycle time at which STATUS/FAULTS and V registers are

REF

updated.

Note 5: Active supply current (I ) is dependent on the amount of time

CC

Note 11: Cycle time at which STATUS/ALERT/FAULTS registers and all

slow channel measurement results are updated after the first update. The

first update after enabling any measurement is typically 50ms delayed.

that the output drivers are active on IP and IM. During those times I will

CC

increase by the 20 • I drive current. For the maximum data rate 1MHz, the

B

drivers are active approximately 5% of the time.

Rev A

9

For more information www.analog.com

LTC2949

TYPICAL PERFORMANCE CHARACTERISTICS

Current Measurement Gain Error

vs Temperature

Current Measurement Offset

vs Temperature

Current Measurement Offset

Distribution

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Current Measurement Noise Filter

Response

Power as Voltage Gain Error vs

Temperature

AUXADC Gain Error vs

Temperature

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Auxiliary ADC Measurement

Offset vs Temperature

Time Base Internal Clock TUE vs

Temperature

ADC Conversion Time Error Slow/

Fast vs Temperature

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Rev A

10

For more information www.analog.com

LTC2949

TYPICAL PERFORMANCE CHARACTERISTICS

VREF vs Temperature

VREF Load Regulation

VREF2 vs Temperature

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AVCC/DVCC Supply Current

Standby/Measure vs Temperature

AVCC/DVCC Supply Current vs

Temperature

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PIN FUNCTIONS

AVCC (Pin 19): Analog Supply Voltage. Bypass this pin to

AGND with a 0.1μF (or greater) capacitor. AVCC operating

range is 4.5V to 14V.

BYP2 (Pin 25): Internal 3.25V Supply Voltage. Bypass

BYP2 to DGND with a 1μF capacitor. Can supply external

circuitry(exampleSPIisolatorADuM141EorADuM4154)

with up to 10mA. Overloading might disrupt LTC2949

functionality.

AGND (Pin 18): Analog Ground. Bypass this pin to AVCC

with a 0.1μF (or greater) capacitor.

CF1P, CF1M (Pins 44, 43): Filter Capacitor Inputs for the

first current channel. Connect a 1µF capacitor between

CF1P and CF1M for filtering differential noise and fast cur-

rent variations. Connect 0.1µF capacitors between AGND

and the filter pins for damping high frequency common

mode variations.

BYP1 (Pin 16): Internal Supply Voltage. Bypass BYP1 to

DGND with a 1μF capacitor. BYP1 is regulated to 2.5V. Can

supply external circuitry (example EEPROM) with up to

10mA. Overloading might disrupt LTC2949 functionality.

Rev A

11

For more information www.analog.com

LTC2949

PIN FUNCTIONS

CF2P, CF2M (Pins 39, 40): Filter Capacitor Inputs for the

second current channel. Connect a 1µF capacitor between

CFI2P and CFI2M for filtering differential noise and fast

currentvariations.Connect0.1µFcapacitorsbetweenAGND

and the filter pins for damping high frequency common

mode variations.

preventsLTC2949togoautomaticallyintoSLEEPstateand

to execute HW memory BIST. Connect a 4.7k-10k pull-up

resistor from SDA to BYP1 to ensure correct operation of

auto-sleep and memory BIST.

SDI/ICMP (Pin 27): Serial Data Input in SPI mode or Iso-

lated Interface Comparator Voltage Threshold in isoSPI

mode. Tie ICMP to the resistor divider between IBIAS and

DGND to set the voltage threshold of the isoSPI receiver

comparators. The comparator thresholds are set to 1/2

the voltage on the ICMP pin.

CLKI (Pin 33): Clock Input. Connect to ground if internal

clock is used. For improved measurement accuracy, con-

necta4MHzcrystalbetweenCLKIandCLKOandmatching

capacitors to ground, or drive with an external clock. See

the Timebase Control section.

SDO/I

(Pin 28): Open Drain Serial Data Output in SPI

BIAS

CLKO (Pin 34): Clock Output. Connect a 4MHz crystal

between CLKO and CLKI if used; leave pin unconnected

otherwise.

mode or Isolated Interface Current Bias in isoSPI mode.

In SPI mode tie with a pullup resistor to IOVCC. In isoSPI

mode tie IBIAS to DGND through a resistor divider to set

theinterfaceoutputcurrentlevel.WhentheisoSPIinterface

is enabled, the IBIAS pin voltage is regulated to 2V. The

IP/IM output current drive is set to 20 times the current

IB, sourced from the IBIAS pin.

CSB/IM (Pin 30): Active Low Chip Select in SPI mode or

Isolated Interface Negative Input/Output in isoSPI mode.

DGND (Pin 17): Digital Ground. Connect to AGND.

DNC (Pins 6, 21, 22, 23, 24, 31, 32, 36, 37, 46): Do

V1, V2, V3, V4, V5, V6, V7 (Pins 1, 2, 3, 4, 5, 7, 8):

Voltage Measurement Inputs. Pins are internally buffered

before being applied to the AUXADC for ensuring high

input impedance (50MΩ) and low leakage. Can be left

floating if unused.

not connect.

DVCC (Pin 20): Supply Voltage. Bypass this pin to DGND

with a 1μF capacitor. Operating range is 4.5V to 14V.

I1P, I1M (Pins 45, 42): Differential Input of I1ADC and

overcurrent comparator 1. Tie to AGND if unused.

V8-V12/GPIO1-GPIO5 (Pins 9, 10, 11, 12, 13): General

PurposeVoltageIn–andDigitalOutputs.Pinsareinternally

buffered before being applied to the AUXADC for ensuring

high input impedance (50MΩ) and low leakage (<10nA).

Each pin can be switched to DVCC, switched to DGND or

to toggle at 400kHz (typ.) between DVCC and DGND. Pins

are tri-state in sleep mode. Can be left floating if unused.

I2P, I2M (Pins 38, 41): Differential Input of I2ADC and

overcurrent comparator 2. Tie to AGND if unused.

IOVCC (Pin 26): Serial Interface Configuration and Sup-

ply Pin. Tie pin to DGND for isoSPI communication. Tie

pin to a voltage ≥1.8V and ≤ 4.5V and bypass with 1µF

to DGND for standard SPI communication. In SPI mode

IOVCC supplies the digital input and output circuits of the

serial interface.

VBATP VBATM (Pins 48, 47): Battery Voltage Measure-

,

ment. The differential voltage between VBATP and VBATM

is internally buffered for ensuring high input impedance

(50MΩ) and low leakage (<10nA).

SCK/IP(Pin29):SerialClockInputinSPImodeorIsolated

Interface Positive Input/Output in isoSPI mode.

VREF (Pin 35): Reference Voltage Output. VREF provides

a buffered 3V reference voltage for temperature measure-

mentswithNTCs. Currentloadislimitedto0.5mA. Bypass

this pin to AGND with a 1μF capacitor.

2

SCL (Pin 14): I C Master Clock Open Drain Output. Con-

nect to clock input of EEPROM.

2

SDA (Pin 15): I C Data Input And Open Drain Output. Con-

EXPOSED PAD (Pin 49): Connect to AGND.

nect to data line of EEPROM. SDA driven low at power up

Rev A

12

For more information www.analog.com

LTC2949

BLOCK DIAGRAM

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* Measured value not accessible by user. Only used for internal diagnostics.

** VREF measurement value is only accessible by user from the AUX slow channel.

See also section 'Unused Input Pins V1-V12' for recommendation to allow VREF measurement from AUX fast channel.

See also 'Table 57. MUX Settings' for more details on AUX MUX conﬁguration.

Rev A

13

For more information www.analog.com

LTC2949

OPERATION

OVERVIEW

measured in slow mode, and the LTC2949 will set the

corresponding bit in the Alert Register if a threshold is

exceeded.Programmableheartbeatfunctionsonuptotwo

GPIOs allow to signal any enabled alert over an isolation

barrier, independent of the serial interface. Those pins

toggle at 400kHz and stop toggling in case of an alert.

The LTC2949 is a high precision current, voltage, charge

and energy meter for electrical and hybrid vehicles or

other applications requiring isolated data acquisition.

Operating from supply voltages from 4.5 to 14V, it infers

charge and energy flowing in and out of the battery pack

by monitoring simultaneously the current through up to

two sense resistors and the battery pack voltage. Five rail-

to-rail low-offset ΔΣ ADCs ensure accurate measurement

of currents, voltage and power with insignificant power

loss. The LTC2949 uses instantaneous multiplication of

voltage and current at a high sampling rate to infer ac-

curately power even in presence of fast load variations.

Additionally to the inputs for measuring currents and

battery voltage, the LTC2949 features 12 analog input

pins (V1 to V12) for measuring external voltages. Using

its built-in multiplexer, the LTC2949 performs differential

high input impedance rail-to-rail voltage measurements

between any pair of input pins. Pins V8 to V12 can be

configured as high voltage digital outputs, swinging from

ground to digital supply voltage (DVCC) for controlling

externalcomponentssuchashighvoltagetransistors.One

automatic measurement cycle of current, voltage, power,

temperature, supply voltage and two programmable mul-

tiplexer settings takes 100ms in slow mode. The LTC2949

repeatedlyperformssuchmeasurementsandrecalculates

energy, charge, timeandupdatestheminimum/maximum

tracking and threshold registers, resulting in continuous

integration of current and power with lossless tracking

of charge and energy delivered or received by the battery

pack. An on-chip oscillator provides a 1% precise time

baseforcalculatingtotalcharge,energyandtime.Ifhigher

accuracy is required, a 4MHz crystal connected between

pin CLKI and CLKO or an external clock can be used.

The LTC2949 features a programmable analog overcur-

rent comparator for each current channel for applications

which require fast detection of overcurrent conditions. A

programmable deglitch filter allows to discard overcur-

rent conditions shorter than a predefined time duration*.

A 3V reference voltage output (VREF) is provided for

connecting external NTCs or voltage dividers allowing to

measuresignalsbelowground.Inslowmode,theLTC2949

provides means for linearizing temperature readings of up

to two external NTCs by solving Steinhart-Hart equations

with programmable coefficients. The LTC2949 can be

configuredtoautomaticallycompensateuser-programmed

temperature coefficients of low-cost shunt resistors by

using linearized NTC temperature readings.

The LTC2949 features programmable gain correction

factors to compensate for tolerances of external shunt

2

resistors and resistor dividers. A master I C interface and

dedicated commands allow to read from and write to an

externalEEPROMwhichcanbeusedforstoringcalibration

factors and the entire register content of the LTC2949 to

guarantee data retention without supply. Storing correc-

tion factors in an EEPROM enables a modular approach

to factory-calibration of application boards.

Athermalshutdowncircuittripsatdietemperaturesabove

150°C and resets the IC to default state, only the thermal

shutdown bit itself is not reset.

Measuredquantitiesarestoredininternalregistersacces-

sibleviatheonboardSPIorLTC-proprietaryisoSPIinterface

which allows fully isolated operation of the LTC2949. The

LTC2949wasdevelopedforcompatibilitywithLinear’sMul-

ticell Battery Monitors (LTC68XX). Various bus structures

ineitherSPIorisoSPI,multi-dropand/ordaisychainingare

possible. The LTC2949 supports a limited set of Linear’s

Battery Cell Monitor compatible commands for triggering

synchronous ADC conversions and reading back data.

For time critical applications, a fast mode is available

which reduces conversion times to 782µs. Data acquired

during fast operation is stored in four FIFOs which contain

each up to 1000 fast ADC readings from 4 synchronously

measured parameters. Reading data from the FIFO yields

simultaneouslyconvertedconversionresults,enablingbat-

teryimpedancetracking,currentprofilingormonitoringof

other fast events, such as the pre-charging voltage before

closing contactors. Thresholds can be set for parameters

*An overcurrent condition is signaled by a dedicated heartbeat pin for fastest response times.

Rev A

14

For more information www.analog.com

LTC2949

OPERATION

CORE LTC2949

Digital data acquired in isolated operation is transferred

over external capacitors or transformers across an isola-

tion barrier. Bridging potential differences of several kV is

achieved by choosing appropriate external components.

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All those features enable a wide variety of applications

beyond current and charge measurement, like measur-

ing isolation resistance, controlling pre-charge switches,

signalingalarmconditions,monitoringstateofcontactors,

etc. The LTC2949 offers various diagnosis functions to

support functional safety critical systems, see the Safety

Manual for more information.

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MODES OF OPERATION

Core State Description

Figure 1. LTC2949 Operation State Diagram

t

willpreventtheLTC2949fromenteringSLEEPstate.

SLEEP

When all power supply voltages have risen above their

UVLO thresholds, the LTC2949 boots up, sets all registers

to their default state and enters after 1s its default SLEEP

state with a current consumption of 9µA (typ), prevent-

ing rapid discharge after insertion when being supplied

by a battery.

In SLEEP, internal analog supplies and BYP1 are switched

off, causing the UVLOA and UVLOD bits to be set when

the LTC2949 resumes from SLEEP. An internal always-on

regulatedvoltagesuppliesthememoryandguaranteesdata

retention during SLEEP. If AVCC or DVCC drop below the

UVLO threshold, the UVLO bit of the internal always-on

supply UVLOSTBY is set and a power-on-reset occurs,

resetting all registers to their default value. In STANDBY

state, all internal circuitry is active but no measurements

except the reference voltage (VREF) are being made.

From STANDBY, the LTC2949 can be instructed to go into

MEASURE state by setting the single shot (SSHOT) or

continuous (CONT) bit in the Operations Control Register

OPCTRL.

In SLEEP state, all GPIOs are tri-state and the LTC2949

monitorstheserialinterfaceandinitiatesthebootsequence

on a falling edge of CSB in SPI mode. In isoSPI mode the

isoSPIinterfacemustfirstbewokenupbyawake-uppulse

before a pulse generating a negative edge on the internal

CSB can be sent. During the boot sequence, the host can

polltheSLEEPbitintheOperationControlRegistertocheck

thattheLTC2949isawakeandinSTANDBYmode(seealso

Figure 20 about Wake-Up and Boot procedure). LTC2949

isoSPI State Description

enters STANDBY state maximum 100ms (t

) after the

BOOT

first falling edge of CSB. In STANDBY state all reference

voltages are powered up and a clock is provided to digital

circuits.TheLTC2949automaticallyreturnstoSLEEPstate

if no wake up confirmation command is received within 1

If the IOVCC pin is tied to a supply voltage ≥1.8V, the

LTC2949 operates in normal SPI mode and IOVCC sup-

plies the receiving circuit and output driving circuit for all

SPI signals.

second (t

) after entering STANDBY state. Wake up is

ACKN

Tying IOVCC to DGND enables the isoSPI port. The isoSPI

port has three different states: IDLE, READY and ACTIVE.

In IDLE state, the isoSPI port is powered down. Only

confirmed by writing 0x00 to register WKUPACK.

The LTC2949 enters SLEEP state ~200ms (t

) after

SLEEP

receivingasleepcommand.AnegativeedgeonCSBduring

Rev A

15

For more information www.analog.com

LTC2949

OPERATION

differential activity on IP-IM generates a wake-up signal

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and the isoSPI port will enter READY state after t

READY

(10µs) and be ready to send or receive data. The current

consumption increases by several mA in READY. When

communication takes place the isoSPI port is in ACTIVE

state and supply current rises further depending on clock

frequency. In order to save power the isoSPI port enters

IDLE state when there has been no differential activity on

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IP-IM for more than t

(6.4ms typ.). Communication

IDLE

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to the LTC2949 core is only possible if the isoSPI port is

not in IDLE state. This means that even when the LTC2949

coreisinSTANDBYorMEASUREstateandtheisoSPIport

is in IDLE state, communication can only take place 10µs

ꢘꢙꢚꢙ ꢛꢜꢘ

(t ) after differential activity on IP-IM.

READY

Figure 2. isoSPI State Diagram

Figure 2 displays the sequence of states which the isoSPI

interface and the LTC2949 core go through from waking

up the interface until effectuating ADC measurements.

See also Figure 20 for recommended wake-up sequence

implementations.

CH1 and CH2 can be individually set to an 18-bit high

precision mode (slow mode, default) or a 15-bit fast

mode. Activating fast mode reduces conversion times

from 100ms to 782µs on the selected channel. The power

ADCs can be individually configured as voltage ADCs by

disabling the power multiplication after the input buffers

by setting the corresponding Power as Voltage (PasV) bit

in ADC Configuration Register (ADCCONF).

DATA ACQUISITION CHANNELS

The LT2949 has two current ADCs (I1ADC, I2ADC), two

power ADCs (P1ADC, P2ADC) and one Auxiliary ADC

(AUXADC). I1ADC and P1ADC are grouped together and

form data acquisition channel 1 (CH1), I2ADC and P2ADC

form channel 2 (CH2) and the AUXADC together with

auxiliary multiplexer (AUXMUX), die-temperature sensor

and supply voltage sensor form channel AUX (CHAUX).

Slow, High Precision Mode

By default, LTC2949’s acquisition channels are in slow

high precision mode where conversions of CH1 or CH2

take 100ms and yield 18-bit conversion results of current

and power or current and voltage, if PasV set. During

these 100ms the auxiliary channel (CHAUX) measures

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Figure 3. Timing of IsoSPI and Core States

Rev A

16

For more information www.analog.com

LTC2949

OPERATION

sequentially six different quantities using its Round Robin

(RR) mode starting with VBATP – VBATM (BAT) then die-

temperature (TEMP), AVCC supply voltage (VCC), two

AUXMUX inputs (SLOT1 and SLOT2), selectable by the

Multiplexer Setting Registers and finally the Reference

Voltage(VREF). Furthermore, amovingaverageofthelast

four measurements of IADC1 and IADC2 in slow mode is

provided, yielding a 20-bit result. In slow, high precision

mode a single conversion or continuous conversions can

be triggered. The continuous slow mode (CONT) is the

most typical operation and also the prerequisite to make

fast conversions.

In continuous measurement mode, the host can poll for

the end of a measurement cycle by periodically checking

the corresponding time registers (TB1, TB2, TB3 or TB4)

for incrementation.

Accessing High Precision Results

At the end of each measurement cycle of 100ms, all result

register for the measured quantities are updated; in con-

tinuous mode, accumulated quantities are updated also.

Furthermore, the four preceding measurements of each

current channel are stored in Current History Registers

and their average in Current Average Registers, see the

Register Map section for more details. The completion

of register updates of the measurement results can be

detected by reading one of the time registers (TB1-TB4)

and looking for a changed value.

Single Shot Measurement Mode (SSHOT)

When bit SSHOT in the Operation Control Register is set,

the LTC2949 takes measurements of CH1 and CH2 as

well as the six auxiliary channel measurements described

above, updates the corresponding minimum, maximum

and threshold registers, resets bit SSHOT, sets the bit

UPDATE in Status Register and returns to the STANDBY

state.Notimemeasurementsaremadeandthechargeand

energy registers are not updated and therefore not com-

pared against minimum/maximum thresholds. The host

can poll the UPDATE bit in the STATUS Register to detect

thecompletionofthemeasurementcycle.Ameasurement

Fast Mode

The LTC2949 provides a fast mode with a reduced conver-

sion time of 782µs and a resolution of 15-bit. Fast mode

allows to start measurements at a precise point in time

andtherebyperformmeasurementssynchronizedwiththe

voltage measurements of LTC’s Battery Stack Monitors,

for example to deduce cell impedance of individual cells.

starts within 20ms (t

) after setting bit SSHOT.

IDLE_CORE

Fast Mode Configurations

The LTC2949 allows to set data acquisition channel 2 in

fast mode while data acquisition channel 1 stays in slow

high precision mode or to set both data acquisition chan-

nels 1 and 2 in fast mode by setting the corresponding bit

FACH1 or FACH2 in the Fast Control Register (FACTRL).

The auxiliary channel can be set to fast mode indepen-

dently of CH1 and CH2, converting only a single quantity

(selected by the Fast MUX Control Registers) instead of

Round-Robin (RR).

Continuous Measurement Mode (CONT)

When the bit CONT in the Operation Control is set, the

LTC2949repeatedlytakesmeasurementsofCH1andCH2as

wellasthesixauxiliarychannelmeasurements,recalculates

energy, charge, time and updates the minimum/maximum

tracking and status registers every 100ms. The start of

continuous high precision measurements can take up to

20ms (t

) after setting bit CONT. The current and

IDLE_CORE

power ADCs run continuously in this mode, ensuring that

nochargeorenergyismissed. IfapowerADCisconfigured

to measure voltage (PasV), the energy of the correspond-

ing channel is not accumulated. The LTC2949 remains in

continuous mode until bit CONT of the Operation Control

Register is reset by the user. If the SSHOT bit is set while

in continuous mode, the LTC2949 completes the current

measurement cycle and then enters single shot mode,

clearing the CONT bit in the Operation Control Register.

To enable short startup delays, the LTC2949 must be in

continuousmode(CONT=1)beforetriggeringfastconver-

sions. FastmeasurementsaretriggeredeitherbyanADCV

command (fast single shot) or by setting bit FACONV in

the Fast Control Register (FACTRL). The ADCV command

triggers a single fast conversion of the selected channels

right after the correct PEC is received, synchronous to

Rev A

17

For more information www.analog.com

LTC2949

OPERATION

LTC’s Battery Stack Monitors. If fast measurements are

triggered by setting FACONV=1, LTC2949 executes a

sequence of fast conversions until FACONV or CONT is

reset. Samples acquired during fast continuous mode are

storedinindividualFIFOsforuptofourfastinputchannels

(I1, I2, BAT via P1 or P2 and AUX).

since the whole FIFO was read (0x55, default), or has

been overwritten because the FIFO was filled without

being read (0xAA). The other FIFOs present the respec-

tive quantities accordingly. All tags are initialized to their

default value (0x55), if fast conversions are triggered by

an ADCV command (while FACONV = 0) or by setting

FACONV. Also leaving the continuous mode by resetting

CONT will clear the FIFOs.

CH1 and CH2 automatically restart in slow high precision

mode after completion of joint fast mode conversions. If

CH2 was in fast mode while CH1 continued in slow high

precisionmode, CH2willstopconvertingaftercompletion

offastmodeacquisitionsreadytoperformfurtherfastmode

conversionswhenrequestedeitherbyanADCVcommand

or by setting FACONV again. The auxiliary channel slow

mode Round-Robin (BAT, TEMP, VCC, SLOT1, SLOT2,

VREF)isautomaticallyrestartedafterallfastmeasurements

werestoppedfor300ms. Inapplicationswerecontinuous

high AUX measurement rates (faster than every 100ms)

are required, it is recommended to measure also VREF

and optionally VCC via external connections to V1-V12

and implement a manual Round-Robin by fast single shot

measurements in software.

The LSB sizes of the fast conversion results are the same

for the RDCV and FIFO readings and are listed in Table 28.

When CH1 and CH2 are both in fast mode, 128 conversion

results of IADC1 and IADC2 are averaged and stored in

theirrespectivenon-accumulatedresultsregistersCurrent1

and Current2 and are added to the Charge1 and Charge2

registers ensuring that battery charge and discharge is

monitored also in fast mode.

Similarly 128 conversion results of PADC1 and PADC2

with 11 bit resolution are averaged and stored in their

respective non-accumulated results registers Power1 at

and Power2 and are added to the Energy1 and Energy2

registersifthePADCsareinPowerMode(PasV=0). IfCH1

isinslowmodeandCH2infastmode, onlyCH1resultsare

reported in the Current and Power results registers, CH2

results can be accessed via RDCV or the respective FIFOs.

Accessing Fast Mode Results

The last results of fast conversions can be read out by

the RDCV command providing sequentially the results of

I1, I2, BAT via P1 or P2 and AUX followed by an indica-

tor if the data is new (0xF) or old (0x0). BAT is the result

of the power ADC, if the ADC is set in voltage mode (bit

PasV=1), otherwise, the power ADC result is 0. If both

channels are in fast mode with their power ADCs in volt-

age mode, BAT is obtained from PADC1. Please note that

to be compliant with LTCs Battery Stack Monitors, RDCV

reports LSByte first.

Recommended Configurations of Data Acquisition

Channels

Inatypicalapplicationcase,bothdataacquisitionchannels

offeredbyLTC2949couldmonitorthecurrentoverasingle

shunt resistor, where CH1 is used to do high precision

current and power measurements and charge and energy

integration, while channel two takes fast snapshots of cur-

rentandvoltageforexampleforimpedancemeasurement.

Furthermore, the last 1000 fast conversion results of I1,

I2, BAT via P1 or P2 and AUX are stored in First-In-First-

Out Registers accessible by FIFOI1, FIFOI2, FIFOBAT and

FIFOAUX. Reading continuously from FIFOI1 provides

successively 3 bytes for each sample of the first current

ADC: I1 MSB, I1 LSB and a qualifier (TAG) whether the

corresponding FIFO data is fine (0x00), has been already

read because no new data has been added to the FIFO

Alternatively, the two data acquisition channels offered

by LTC2949 might be used to monitor currents over two

different shunt resistors. In this application case, both

channelsmightbeusedineitherfastorslowmode.CHAUX

can be configured fully independently from CH1 and CH2.

The default mode of AUXADC is RR, which is deactivated

by enabling fast mode on CHAUX.

Rev A

18

For more information www.analog.com

LTC2949

OPERATION

Table 1. Acquisition Channels Configurations

Dual Shunt Fast Measurement Configuration

SINGLE SHUNT

Slow

DUAL SHUNT

CH1 and CH2 are both set to fast mode by setting bits

FACONV, FACH1 and FACH2. Charge is accumulated by

summing up 15-bit current results, energy by summing

up 11 bit power results.

CH1

CH2

Slow

Fast

CHAUX

RR/Fast

One conversion takes 782µs and a new RR cycle is started

afterevery100ms. Thisconfigurationfitstoanapplication

where two shunt resistors are used and fast current, volt-

age and power is required. E.g.: Fast impedance tracking

or measuring pre-charge voltage and current.

Single Shunt Configuration

If only one external shunt is used, CH1 can be used to

perform continuous high precision integrated charge and

energy measurements, while CH2 is used to perform fast

measurements synchronized with LTC's Battery Stack

Monitors. By setting bit CONT in the Operation Control

Register (OPCTRL) and bit FACH2 in the Fast Control

Register (FACTRL), CH1 will effectuate consecutive slow

measurements, while CH2 is available for fast measure-

ments triggered by an ADCV command. Measurements

of CH1 and its integrated quantities are updated every

100ms while CH2 results can be read out with an RDCV

command or obtained from the FIFO registers, in case of

fast continuous (FACONV) operation.

POWER MEASUREMENT

The LTC2949 measures power with additional ADCs that

multiply voltage (VBATP – VBATM) and current at the full

5.24MHzsamplingfrequency,priortoanyaveragingdueto

the analog-to-digital conversion. This maintains accuracy

even if current and voltage change in phase during the

100ms conversion time, which can happen if the power

is drawn from a battery with significant impedance. Figure

4 shows an example of the BAT voltage dropping from 4V

to 3V due to battery impedance when an AC current is

drawn by the load. In this example, the multiplication of

average current with average voltage would lead to a +8%

error in the calculated power as the voltage is significantly

lower than the average voltage at the moments where the

peak current is drawn. The scheme used by the LTC2949

avoids this error, maintaining specified accuracy with

signals up to 50kHz.

Dual Shunt High Precision Configuration

For dual shunt applications that require continuous un-

interrupted high precision coulomb counting and energy

measurement CH1 and CH2 should be both configured to

slow high precision mode by setting bit CONT in OPCTRL.

Conversions on CH1 and CH2 take 100ms and a new RR

cycleofCHAUXisstartedateverystartofconversionofCH1.

If fast voltage data is required, the AUXADC can be config-

ured for fast mode without interrupting charge and energy

accumulation on CH1 and CH2. After setting bits FACONV

and FACHA the AUXADC immediately stops RR mode and

continuously measures a single quantity selected by the

FastMUXControlRegisters.DataiswrittentotheFIFOAUX.

AfterclearingbitFACHAtheAUXADCautomaticallyreturns

to RR operation (after 300ms). Measurements of VREF,

internal die temperature and VCC are only available if RR

is enabled. Alternatively, external connections to V1-V12

can be applied to measure VREF and VCC (via an external

resistive divider) also in fast mode.

ꢑꢒꢈ

ꢓꢒꢑ

ꢓꢒꢈ

ꢔꢒꢑ

ꢔꢒꢈ

ꢕꢒꢑ

ꢕꢒꢈ

ꢖꢕꢈ

ꢖꢈꢈ

ꢗꢈ

ꢘꢈ

ꢓꢈ

ꢕꢈ

ꢈ

ꢀꢁꢂꢃAꢄꢅ ꢆꢀꢇAꢃꢈꢉꢀꢇAꢃꢊꢋ

ꢀꢁRRꢂꢃꢄ ꢅꢆꢇꢈꢆꢉꢊ

ꢈ

ꢈꢒꢖ ꢈꢒꢕ ꢈꢒꢔ ꢈꢒꢓ ꢈꢒꢑ ꢈꢒꢘ ꢈꢒꢛ ꢈꢒꢗ ꢈꢒꢙ

ꢀꢁꢂꢃ ꢄꢅꢆꢇ

ꢖ

ꢕꢙꢓꢙ ꢚꢈꢓ

Figure 4. Power Measurement of Transient Signals

Rev A

19

For more information www.analog.com

LTC2949

OPERATION

CHARGE, ENERGY AND TIME

ꢀꢁꢂꢃꢄꢅꢄ

The LTC2949 integrates the current and power measure-

ments over time to calculate charge and energy flowing

to the load. It also keeps track of total accumulated time

used for the integration.

ꢂꢀꢓꢔ

ꢂꢀꢓꢕ

ꢃꢄꢅꢄ ꢖꢍꢗ

ꢆꢇ

ꢘꢘꢙꢖ

ForthequantitieschargeandenergytheLTC2949provides

three sets of registers each, for the quantity "time" four

register sets.

ꢆꢇꢈ Aꢉꢀꢊꢃꢋꢅꢌꢍꢍꢍꢎꢏꢐꢋꢑꢅꢒꢋꢁ

Charge1, Energy1 and Time1 contain accumulated quan-

tities of Channel1. Charge2, Energy2 and Time2 contain

accumulated quantities of Channel2. Charge3 and Time3

contain the sum of charges monitored by Channel1 and

Channel2 and the corresponding time. Similarly Energy4

and Time4 contain the sum of energies monitored by

Channel1 and Channel2 and the corresponding time. See

the Accumulated Result Registers section in the Register

Map description for more details.

Figure 5. Reference Clock with a 4MHz Crystal

nal clock to the external frequency and represents Time,

Charge, and Energy as multiples of the external clock pe-

riod. To accommodate the large range of allowed external

frequencies, an internal prescaler must be configured via

the Timebase Control Register.

The prescaler consists of 2 stages, with the first divid-

PRE

ing the external frequency f

by a factor 2 , and the

REF

second by a factor DIV. PRE is set between 0 and 5 with

bits [2:0] of the Timebase Control Register. PRE should

be configured such that the external frequency divided by

is less than 1MHz as shown in Table 2:

Table 2. Parameter PRE with External Clock

Each register set can be separately configured to accumu-

late current and power based on the sign of the measured

current.Aminimumcurrentthresholdcanalsobesetbelow

which integration is stopped. See the Control Registers

section in the Register Map description for more details.

PRE

2

f_REF

PRE

2^PRE

1

PRE[2:0]

000

0.1MHz ≤ f ≤ 1MHz

0

1

2

3

4

5

7

Time Base

REF

1MHz ≤ f ≤ 2MHz

2

001

REF

Accurately measuring charge and energy by integrating

current and power requires a precise integration period.

The LTC2949 uses either a trimmed internal oscillator or

an external clock as the time base for determining the in-

tegration period. It can use either an external square wave

clock in a frequency range between 100kHz and 25MHz

or a 4MHz crystal as external clock input. If an external

square wave is used, it should be connected to the CLKI

pin and the CLKO pin should be left unconnected.

2MHz ≤ f ≤ 4MHz

4

010

REF

4MHz ≤ f ≤ 8MHz

8

011

REF

8MHz ≤ f ≤ 16MHz

16

32

100

REF

16MHz ≤ f ≤ 25MHz

101

REF

Internal

111

The second stage of the prescaler then divides the result

by a factor DIV. DIV is set between 0 and 31 by bits [7:3]

of the Time Base Control Register. DIV should be set to the

next lower integer value of the ratio between the output

Figure5showstherecommendedcircuitifacrystalisused

to generate the reference clock. In case the internal clock

is used, tie CLKI to ground and leave CLKO unconnected.

PRE

of the first stage of the prescaler (f _1 = f /2 ) and

REF

32768Hz or, in other terms:

⎛

⎞

f_REF

DIV = floor

⎜

⎟

Timebase Control

PRE

⎝

⎠

2

•32768Hz

The LTC2949 uses the internal oscillator by default. If

an external clock or a crystal is used, the PRE and DIV

parameters in the Timebase Control Register need to be

set appropriately. The LTC2949 then compares its inter-

If a crystal is used, the values are: PRE = 2, DIV = 30. The

Quick Eval™ Software for the LTC2949 contains an easy

to use calculator for these parameters. Table 3 gives a few

examples for common frequencies.

Rev A

20

For more information www.analog.com

LTC2949

OPERATION

Table 3. Timebase Settings for Common Frequencies

Bits OCCxPOLx control the polarity sensitivity of the

comparator as in Table 5.

Table 5. OCC Polarity Configuration

TIME BASE

f_REF[MHz] PRE 2^PREf_REF_1[MHz] DIV CONTROL [7:0]

1

1.5

4

0

1

2

4

5

7

1

2

1

30

22

30

19

23

X

1111 0000

1011 0001

1111 0010

1001 1100

1001 1101

1011 1101

XXXX X111

OCCxPOL1

OCCxPOL0

POLARITY

Both Polarities

0.75

1

0

1

0

1

0

4

Positive Currents

Negative Currents

10

20

25

Int.

16

32

0.625

0.781

The thresholds of the overcurrent comparators can be

programmed individually by means of the OCCxDACx bits

between 0 and 310mV.

Table 6. OCC Thresholds

Threshold

OVERCURRENT COMPARATORS

The LTC2949 features two fast differential over-current

comparators with rail to rail input common mode and

programmable threshold followed by configurable filters

to suppress input glitches. Overcurrent comparator 1

(OCC1)isconnectedtopinsI1PandI1Mwhileovercurrent

comparator 2 (OCC2) supervises the differential voltage

between I2P and I2M. Both overcurrent comparators can

individually be configured to detect either only positive or

only negative overcurrents or overcurrents independent

of their polarity. When at least one of the overcurrent

comparators is enabled, GPIO5 turns into a heartbeat

signal toggling at 400kHz while currents are within the

desired range and staying low if any current exceeds its

programmed limit.

OCCxDAC2

OCCxDAC1

OCCxDAC0

[mV]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

26

52

78

103

155

207

310

Similarly,thedurationofathresholdexceedingnotreported

bythecomparator(DeglitchTime)canbeprogrammedby

the bits OCCxDGLTx between 20µs to 1.28ms.

Table 7. OCC Deglitch Time

The overcurrent comparator 1 (OCC1) between I1P and

I1M is controlled by the control register OCC1CTRL

while overcurrent comparator 2 (OCC2) is controlled by

its control register at OCC2CTRL, both on page 0 of the

register map. Both OCC Control Registers are organized

as shown in Table 4.

OCCxDGLT1

OCCxDGLT0

DEGLITCH TIME [µs]

0

1

0

1

0

1

20

80

320

1280

Table 4. Overcurrent Comparator Control Registers

Overcurrents are reported by setting OCC1 and OCC2 of

VCC and OCC Status Register (STATVCC) and by stop-

ping the heartbeat signal on GPIO5. While the update of

the output register can take up to 100ms, the heartbeat

is stopped within 15µs after an overcurrent exceeded the

programmeddeglitchtime.Onceanovercurrentoccurred,

the result bits in the register remain set until they are read

by the host and subsequently cleared.

BIT #

NAME

OCCxEN

FUNCTION

Enable OCC

0

1

2

3

4

5

6

7

OCCxDAC0

OCCxDAC1

OCCxDAC2

OCCxDGLT0

OCCxDGLT1

OCCxPOL0

OCCxPOL1

Threshold DAC[0]

Threshold DAC[1]

Threshold DAC[2]

Deglitch [0]

Deglitch [1]

Polarity [0]

For diagnostic purposes, the overcurrent comparators

have a self-test built in using test input signals IPT and

IMT, see the Safety Manual for more information.

Polarity [1]

The overcurrent comparators are enabled by setting the

respective OCCxEN to 1.

Rev A

21

For more information www.analog.com

LTC2949

SERIAL INTERFACES

SERIAL INTERFACES OVERVIEW

A second interface composed by pins 14 and 15 is a mas-

2

ter I C interface, allowing to save and restore LTC2949’s

LTC2949hastwoserialinterfaces,oneforcommunication

withthehostandasecondtoaddressanexternalEEPROM.

The interface for host communication is composed by

pins 27 through 30 and can be configured to be either

a standard 4-wire serial peripheral interface (SPI) or a

2-wire isolated interface (isoSPI) based on the voltage

of the IOVCC pin. Regardless of which configuration is

selected, the LTC2949 acts as an SPI slave. The LTC2949

can be operated in addressable mode (SPI & isoSPI) or

as last element of a daisy chain of LTC68xx Cell Monitors

(isoSPI only).

register content to and from an external EEPROM see

the External EEPROM Control Register section for more

information.

4-WIRE SERIAL PERIPHERAL INTERFACE (SPI)

PHYSICAL LAYER

ConnectingpinIOVCCtoasupplyvoltage≥1.8Vconfigures

the serial port for 4-wire SPI. Logic input thresholds and

output swings are set by the voltage at the IOVCC pin,

which should be connected to the same supply as the SPI

master device. A 1µF bypass capacitor is recommended

from IOVCC to DGND. The pin SDI is often referred to

as MOSI, the pin SDO as MISO. The 4-wire serial port is

configured to operate in a SPI system using CPHA = 1 and

CPOL=1.Consequently,dataonSDImustbestableduring

the rising edge of SCK and data on SDO will be updated on

the falling edge of SCK. The timing is depicted in Figure 7.

The maximum data rate is 1Mbps. See Electrical Charac-

teristics. SDO is open drain and requires a pull-up.

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢃ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄꢅꢄ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁꢂꢀ

ꢀꢁꢂꢁ ꢃꢄꢅ

Figure 6. 4-Wire SPI External Connections

ꢉ

ꢍ

ꢋ

ꢇ

ꢈ

ꢌ

ꢉ

ꢎ

ꢀꢁꢂ

ꢀꢃꢄ

ꢃꢈ

ꢃꢎ

ꢃꢋ

ꢃꢐ

ꢃꢍꢑꢑꢑꢃꢇ

ꢃꢈ

ꢉ

ꢏ

ꢁꢀꢅ

ꢀꢃꢆ

ꢉ

ꢊ

ꢃꢇ

ꢃꢈ

ꢃꢎ

ꢃꢋ

ꢃꢐ

ꢃꢍꢑꢑꢑꢃꢇ

ꢃꢈ

ꢎꢙꢇꢙ ꢚꢐꢍ

ꢒRꢓꢔꢄꢆꢕꢀ ꢁꢆꢖꢖAꢗꢃ

ꢁꢕRRꢓꢗꢘ ꢁꢆꢖꢖAꢗꢃ

Figure 7. Timing Diagram of 4-Wire Serial Peripheral Interface

Rev A

22

For more information www.analog.com

LTC2949

SERIAL INTERFACES

2-WIRE ISOLATED INTERFACE (ISOSPI) PHYSICAL

LAYER

through an external transformer. Capacitive coupling with

10nF capacitors could also be used, but has a very limited

common mode noise rejection (only for low frequencies)

and is only recommended for short single PCB intercon-

nections with limited voltage transients at the isolation

barrier. Additional clamping Schottky diodes might be

necessary from IP and IM to VCC and GND. Standard SPI

signals are encoded into differential pulses. The strength

of the transmission pulse and the threshold level of the

receiver are set by two external resistors. The values of

the resistors allow the user to trade off power dissipation

for noise immunity. Figure 9 illustrates how the isoSPI

Tying IOVCC to local chip ground enables the isoSPI

2-wire interface which allows fully isolated operation of

theLTC2949.The2-wireinterfaceprovidesmeanstocom-

municate to LTC2949 using simple twisted pair cabling.

An LTC6820 should be used for translating standard SPI

signals from the SPI master into pulses that are sent over

an isolation barrier to the LTC2949.

Theinterfaceisdesignedforlowpacketerrorrateswhenthe

cabling is subjected to high RF fields. Isolation is achieved

ꢄꢅꢆꢇAꢈꢄꢆꢉ ꢊARRꢄꢋR

ꢂꢃꢃꢄꢅꢆ

ꢜꢂ

ꢂꢃꢃ

ꢂ

ꢃꢃ

ꢄꢏ

ꢅꢃꢘ

ꢄꢏ

ꢄꢎ

ꢄꢏ

ꢐꢗꢗ

ꢄꢎ

ꢃꢅꢊ

ꢇꢈꢃꢒꢓꢔꢓ

ꢄꢆꢂꢃꢃ

ꢇꢈꢃꢕꢖꢒꢗ

ꢌꢉꢍ

ꢙꢃ

ꢀ^{ꢔꢛꢜꢂꢝꢐꢔꢂ}

ꢁ

ꢄꢊꢄAꢅ

ꢎꢆꢅꢄ

ꢐꢑ

ꢄꢃꢎꢏ

ꢎꢄꢅꢆ

ꢐꢑ

ꢌꢉꢍ

ꢌꢉꢍꢄꢅꢆ

ꢒꢓꢔꢓ ꢚꢗꢖ

Figure 8. isoSPI Physical Layer

ꢓꢚꢊꢀꢁꢂꢁ

ꢉꢇꢙꢋꢀ

ꢍꢢꢣ

ꢎ

ꢉ

ꢅꢊꢆꢋ

ꢌꢍ ꢎ ꢏꢐꢑꢒꢉ

ꢞ

ꢡAꢠꢘꢟꢋ

ꢊꢅRꢊꢟꢅꢚ

ꢅꢗꢓꢘ

ꢚꢛ ꢝ ꢀꢄ ꢝ ꢅ

ꢇ

ꢚꢛ ꢜ ꢎꢏ

ꢚꢛ ꢜ ꢄ

ꢅꢋ

ꢈꢗꢔ

ꢓꢔꢕꢅꢊ

Aꢖꢗ

ꢆꢘꢆꢔRꢙ

ꢚꢛ ꢜ ꢞꢏ

ꢈꢗꢅ

ꢈꢊꢠ

ꢊꢈꢇ

R

ꢆ

ꢋꢟꢓꢈꢘ

ꢅꢆ

ꢘꢖꢊꢔꢗꢘRꢌ

ꢗꢘꢊꢔꢗꢘR

Rꢛ ꢜ ꢎꢏ

Rꢛ ꢜ ꢄ

ꢎ

ꢞ

ꢅ

ꢅꢇꢅAꢈ

ꢅꢊꢆꢋ

Rꢛ ꢜ ꢞꢏ

ꢇ

ꢎ

ꢀꢉ

ꢞ

R

ꢇꢏ

ꢏꢉ ꢝ R

ꢇꢀ

ꢊꢔꢆꢋARAꢚꢔR ꢚꢤRꢘꢈꢤꢔꢓꢗ ꢜ

R

ꢇꢏ

ꢎ R

ꢇꢀ

ꢄꢥꢢꢛ

ꢇꢀ

ꢀꢁꢂꢁ ꢃꢄꢁ

Figure 9. isoSPI Interface

Rev A

23

For more information www.analog.com

LTC2949

SERIAL INTERFACES

circuit operates. A 2V reference drives the IBIAS pin. Ex-

IBIAS is held at 2V, causing a current I to flow out of the

B

ternal resistors R and R create the reference current

IBIAS pin. The IP and IM pin drive currents are 20 • I .

B1

B2

B

I . This current sets the drive strength of the transmitter.

B

As an example, if divider resistor R is 2.8k and resistor

B1

R

and R also form a voltage divider of the 2V refer-

B1

B2

R

B2

is 1.21k (so that R

= 4k), then:

BIAS

ence at the ICMP pin. This sets the threshold voltage of

the receiver circuit.

2V

R_B1+R_B2

I_B=

=0.5mA

Waking Up the isoSPI Port

I

_DRV=I =I =20•I_B=10mA

IP IM

The isoSPI port has 3 modes of operation, IDLE, READY

and ACTIVE as described in the section isoSPI State De-

scription. In IDLE, the WAKEUP circuit monitors activity

on pins IP and IM. Differential activity on IP-IM wakes up

the isoSPI interface. The isoSPI port will return to the low

power IDLE state if there is no activity on IP/IM for a time

R_B2

R_B1+R_B2

V_ICMP=2V •

=I_B•R_B2=603mV

V_TCMP=0.5•V_ICMP=302mV

Inthisexample,thepulsedrivecurrentIDRVwillbe10mA,

andthereceivercomparatorswilldetectpulseswithIP-IM

amplitudes greater than 302mV. If the isolation barrier

uses 1:1 transformers connected by a twisted pair and

terminated with 100Ω resistors on each end, then the

transmitted differential signal amplitude ( ) will be:

of t . The LTC2949 will be ready to communicate when

IDLE

the core is not in SLEEP and the isoSPI state changes

to READY (within t after wakeup) as illustrated in

READY

Figure 3. Common mode signals will not wake up the

serial interface. The interface is designed to wake up

after receiving a large signal single-ended pulse, or a

low-amplitude symmetric pulse. The differential signal

R

2

V_A=I_DRV

•

^M=0.5V

|IP – IM|, must be at least V

= 200mV for a minimum

WAKE

duration of t

= 240ns to qualify as a wake up signal

(This result ignores transformer and cable losses, which

may reduce the amplitude).

DWELL

that powers up the serial interface.

"Long -1" or "Long +1" pulses (= drive CSB low, high)

generatedbyLTC6820andcompatibleisoSPIdevices(e.g.

LTC68xxCellMonitors)willalwaysmeetthisrequirement.

See following chapters for isoSPI pulse details.

isoSPI Pulse Detail

The transmitter can output three voltage levels: +V , 0V,

A

and–V .ApositiveoutputresultsfromIPsourcingcurrent

A

and IM sinking current across load resistor R . A nega-

M

Selecting Bias Resistors

tive voltage is developed by IP sinking and IM sourcing.

When both outputs are off, the load resistance forces

the differential output to 0V. To eliminate the DC signal

componentandenhancereliability,theisoSPIusesbipolar

pulses of two different pulse length. This allows for four

types of pulses to be transmitted, as shown in Table 8. A

+1 pulse will be transmitted as a positive pulse followed

by a negative pulse. A –1 pulse will be transmitted as a

negative pulse followed by a positive pulse. The duration

Theadjustablesignalamplitudeallowsthesystemtotrade

power consumption for communication robustness, and

the adjustable comparator threshold allows the system to

accountforsignallosses.TheisoSPItransmitterdrivecur-

rentandcomparatorvoltagethresholdaresetbyaresistor

divider (R

= R + R ) between the IBIAS and DGND.

BIAS

B1

B2

The divided voltage (V

) is connected to the ICMP pin

ICMP

which sets the comparator threshold (V

voltage. When the isoSPI interface is enabled (not IDLE)

) to 1/2 of this

ICMP

of each pulse is defined as t

, since each is half of the

1/2PW

required symmetric pair. (The total isoSPI pulse duration

is 2 • t ).

1/2PW

Rev A

24

For more information www.analog.com

LTC2949

SERIAL INTERFACES

Table 8. isoSPI Pulse Types

This allows for multiple slave devices on a single cable

without risk of collisions (Multidrop). Figure 11 shows the

isoSPI timing diagram for a READ command.

FIRST LEVEL

(t

SECOND LEVEL

(t

PULSE TYPE

Long +1

)

1/2PW

ENDING LEVEL

1/2PW

+V (150ns)

A

–V (150ns)

0V

A

Table 9. LTC2949 isoSPI Port Function

INTERNAL SPI

Long –1

–V (150ns)

A

+V (150ns)

A

Short +1

Short –1

+V (50ns)

–V (50ns)

A

RECEIVED PULSE PORT ACTION

RETURN PULSE

–V (50ns)

A

+V (50ns)

A

Long +1

Long –1

Short +1

Drive CSB High None

Drive CSB Low

An LTC6820 should be used to translate the SPI signals of

a micro controller into isoSPI pulses. On the other side of

the isolation barrier (i.e. at the other end of the cable), the

LTC2949 will have IOVCC tied to its local GND. It receives

transmitted pulses and reconstructs the SPI signals in-

ternally, as shown in Table 9. In addition, during a READ

command this port may transmit return data pulses which

1. Set SDI = 1

2. Pulse SCK

Short –1 Pulse if Reading a 0-bit

(No Return Pulse if Not in READ

Mode or if Reading a 1-bit)

Short –1

1. Set SDI = 0

2. Pulse SCK

Supported Bus Structures

The addressing feature of the LTC2949 and LTC68xx-2

Cell Monitors allows multiple devices with different ad-

dressestobeconnectedonasinglebusbymulti-dropping

them. Multi-dropping can be used in either SPI or isoSPI

(See Figure 12 (A)). The LTC2949 also operates in paral-

lel to or as last element of a daisy chain of LTC68xx Cell

Monitors (See Figure 12 (B&C)).

aretransmittedt afterthereceivedpulse. TheLTC2949

RTN

isoSPI port is a slave port and only transmits short –1

pulses, never long CSB pulses nor short +1 pulses. The

master port recognizes a null response as a logic 1 (for

this reason a no reply to a read command is equivalent to

read only 0xFF... on the MISO line, which will also cause a

PEC error, see chapters DATA LINK LAYER and following).

+1 PULSE

ꢇ

ꢍꢉꢔꢍ

ꢄARꢓꢈꢉ

ꢇ

ꢄARꢓꢈꢉ

ꢀꢁ

ꢐꢈꢒꢂ

ꢂꢃꢄꢅ

ꢇ

ꢄARꢓꢈꢉ

V

IP

– V

ꢇ

ꢐꢈꢒꢂ

IM

ꢊꢋꢌꢅꢍ

ꢇ

ꢆꢁ

ꢈꢉꢁ

ꢊꢋꢌꢅꢍ

ꢂꢃꢄꢅ

–1 PULSE

ꢇ

ꢀꢁ

ꢈꢉꢁ

ꢊꢋꢌꢅꢍ

ꢂꢃꢄꢅ

ꢇ

ꢄARꢓꢈꢉ

V

IP

– V

ꢊꢋꢌꢅꢍ

ꢐꢈꢒꢂ

IM

ꢇ

ꢄARꢓꢈꢉ

ꢆꢁ

ꢐꢈꢒꢂ

ꢂꢃꢄꢅ

ꢇ

ꢍꢉꢔꢍ

ꢌꢎꢏꢎ ꢐꢊꢑ

Figure 10. isoSPI Pulse Detail

Rev A

25

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LTC2949

SERIAL INTERFACES

ꢀꢁ

ꢀ

ꢎ

ꢁ

ꢃꢈꢄ

ꢀ

ꢍ

ꢏ

ꢌ

ꢂꢃꢄ ꢅꢆꢇꢈ ꢉ ꢊꢋ

ꢂꢃꢄ ꢅꢆꢇꢈ ꢉ ꢓꢋ

ꢀ

ꢐ

ꢀ

ꢊ

ꢑꢇꢂꢕ

ꢑꢕꢂꢇ

ꢕꢂꢇ

ꢃꢂꢛ ꢉ ꢓ

ꢑ

ꢚ

ꢑ

ꢚꢜꢊ

ꢑ

ꢇ

ꢃꢂꢛ ꢉ ꢊ

ꢂ

ꢕꢝꢚꢇRꢒꢘ

ꢚꢜꢊ

ꢚꢜꢐ

ꢕꢂꢇ

ꢀ

Rꢔꢚ

ꢂꢈAꢠꢒ ꢘꢇꢒꢂ ꢚꢇꢔ

ꢔRAꢚꢂꢑꢕꢔ ꢡꢊ

ꢂꢘꢕꢙꢕꢚꢔ

ꢂꢘꢇꢙꢕꢚꢔ

ꢂAꢑꢆꢈꢒ

ꢓ

ꢏꢓꢓ

ꢊꢓꢓꢓ

ꢊꢏꢓꢓ

ꢐꢓꢓꢓ

ꢐꢏꢓꢓ

ꢍꢓꢓꢓ

ꢍꢏꢓꢓ

ꢌꢓꢓꢓ

ꢌꢏꢓꢓ

ꢏꢓꢓꢓ

ꢐꢞꢌꢞ ꢟꢊꢊ

ꢔꢕꢑꢒ ꢅꢖꢗꢋ

Figure 11. isoSPI Timing Diagram

LTC2949 in Addressable/Multidrop Bus Configuration

LTC2949 Connected to Reversible isoSPI Ring

An LTC2949 can be directly connected to the master in SPI

or through an LTC6820 in isoSPI mode. When operating

together with LTC68xx Cell Monitors it is recommended to

use the LTC2949 in a multidrop bus configuration to take

advantage of the full feature set and minimize communica-

tion overhead. The LTC2949 can operate on the same SPI/

isoSPIwithotherLTC68xxCellMonitors(Figure12(A,B)).

The LTC2949 responds to address 0xF. This address is

hardwired and cannot be changed. Consequently, other

LTC68xx Cell Monitors on the same bus must be pin-

configured to different addresses. Simultaneous writing

to all devices on one bus is done by issuing a broadcast

command.ThisfeatureprovesusefulforsynchronousADC

conversions of LTC2949 and LTC68xx Cell Monitors. The

common SDO pin is open drain and requires a pull-up.

LTC2949 can be connected to one end of a reversible

isoSPI ring. In this scenario the default communication

to LTC2949 is done with direct commands, equivalent

to the scenario where LTC2949 is connected in parallel

to a daisychain. In case the direct link between the left

side LTC6820 and LTC2949 fails, the communication to

LTC2949canberoutedthroughthedaisychainviatheright

side LTC6820, equivalent to the scenario where LTC2949

is connected on top of a daisychain.

LTC2949 on Top of a Daisy Chain

ItisrecommendedtooperateLTC2949inparalleltoadaisy

chain of LTC68xx Cell Monitors in either isoSPI or normal

SPI by using its addressing feature. This is the mode with

the minimum communication overhead. However, also

operation as last element of a daisy chain is supported.

Rev A

26

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LTC2949

SERIAL INTERFACES

ꢀ

•

• •

ꢀ

•

• •

ꢀ

•

• •

ꢀ

•

• •

•

• •

ꢀ

Rev A

27

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LTC2949

SERIAL INTERFACES

As the LTC2949 has only one isoSPI port it must be

written or read from followed by the register data – see

following section Direct Read/Write Command (DCMD).

BesidetheDCMD,theLTC2949supportstheLTC68xxCell

Monitor compatible commands ADCV and RDCV.

th

placed as the last (M ) element in a daisy chain. The 0

element communicates to the master via port A which can

be configured as isoSPI or normal SPI mode, depending

on the connection of the ISOMOD pin. The 0th element

connects via port B to the 1st element of the daisy chain

using isoSPI, and so on. When the LTC68xx Cell Monitor

When LTC2949 is the last element in an isoSPI daisy

chain, the DCMD can be used to write to LTC2949 but not

to read data from the device, because the DCMD is not

supported by other LTC68xx Cell Monitors and thus they

do not pass data from their port B to port A. Therefore, the

RDCV command must be used to read from LTC2949 as

element of a daisy chain. LTC2949 registers read by the

RDCVcommandcanbeconfiguredbyaprecedingDCMD.

–

is operating with port A as SPI (ISOMD = V ), the SPI de-

tects one of four communication events: CSB falling, CSB

rising, SCK rising with SDI = 0, and SCK rising with SDI =

1. Each event is converted into one of the four pulse types

for transmission through the daisy chain. Long pulses are

used to transmit CSB changes and short pulses are used

to transmit data, as explained in Table 8. When both ports

are operated in isoSPI mode, isoSPI pulses on port A are

passed to port B within a short delay.

Table 10 summarizes the possibilities to communicate

to LTC2949.

Table 10. Communication with LTC2949

PARALLEL TO DAISY

CHAIN OR LTC2949 SOLE

LTC2949 ON TOP OF

DAISY CHAIN

DATA LINK LAYER

Read of

DCMD

Broadcast RDCV

All data transfers on LTC2949 occur in byte groups. Every

byteconsistsof8-bits. Bytesaretransferredwiththemost

significant bit (MSB) first. CSB must remain low for the

entiredurationofacommandsequence,includingbetween

a command byte and subsequent data. A write command

takes effect after a correct PEC is processed.

Registers

(RDCVCONF = 0, BCREN = 1)

Write of

Registers

DCMD

Trigger of

Fast ADC

Conversion

Addressed ADCV

Broadcast ADCV

Read of Fast

Addressed RDCV

Broadcast RDCV

Conversion (RDCVCONF = 1, BCREN = 0) (RDCVCONF = 1, BCREN = 1)

Results

NETWORK LAYER

The LTC2949 registers can be accessed by a direct read/

write command (DCMD) containing the registers to be

ꢂꢇꢀꢏꢐꢌꢑ

ꢒꢄꢊꢇ ꢓꢔ

ꢂꢇꢀꢏꢐꢌꢑ

ꢈAꢇꢇꢁRꢉ ꢊꢇAꢀꢋ

ꢃꢄꢅꢆꢇꢄR ꢂꢇꢀꢌꢍꢎꢍ

ꢀꢁꢂꢂ

ꢃꢄꢅꢆꢇꢄR

ꢀꢁꢂꢂ

ꢃꢄꢅꢆꢇꢄR

ꢀꢁꢂꢂ

ꢃꢄꢅꢆꢇꢄR

ꢀꢁꢂꢂ

ꢃꢄꢅꢆꢇꢄR

ꢌꢍꢎꢍ ꢕꢖꢗ

Figure 13. LTC2949 Connected to a Reversible isoSPI Ring

Rev A

28

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LTC2949

SERIAL INTERFACES

Fast Measurement Timings

The following timing diagrams shows LTC2949 fast single shot timing in relation to LTC6810’s timing of the ADCV

command for measuring all six cells. Other LTC681x Cell Monitors have similar timing diagram, just with different

number of ADCs and cells. The LTC681x devices have several ADC modes with different filter bandwidth and accuracy.

Typically, in the 7kHz normal mode, all cells are converted within a time window very close to LTC2949’s fast conver-

sion time which is nominal 782µs. For example, the LTC6810 converts all cells within 815µs in the normal mode.

As an example, only three (I2, BAT, AUX) of maximum four ADCs of LTC2949 are configured for fast conversions. The

displayed timings are valid for any allowed combinations of fast channels.

t

CYCLE,LTC681x,7kHz = 0.8ms

SERIAL

INTERFACE

ADCV + PEC

LTC6810

MEASURE

C1 TO C0

MEASURE

C2 TO C1

MEASURE

C3 TO C2

MEASURE

C4 TO C3

MEASURE

C5 TO C4

MEASURE

C6 TO C5

ADC1

CALIBRATE

t

0

t

3M

t

6M

t

C

1M

2M

4M

5M

I2ADC

P2ADC

MEASURE CURRENT

LTC2949

MEASURE STACK VOLTAGE

MEASURE AUX VOLTAGE

AUXADC

t

CYCLE,2949 = 0.8ms

2949 F14

Figure 14. Timing for ADCV Command Measuring Cell Voltages and LTC2949's Current and Voltage Inputs

ADCV

RDCV

ADC

I2

ADC

BAT

(AUX)

AUX

t

2

t

1*

or t

1

t

3*

or t

3

2949 F15

Figure 15. Timing for LTC2949’s ADCV Command Measuring Current and Voltage Inputs.

DESCRIPTION

PARAMETER

VALUE/TOLERANCE

6 to 8μs

ADVC's last PEC byte to start of conversion latency without AUX conversion

ADVC's last PEC byte to start of conversion latency with AUX conversion

Conversion time

t

1

t

6 to 170µs

1*

t

742 to 821µs

855 to 945µs

2

3

ADVC's last PEC byte to HS = 0x0F (hand shake byte read by RDCV indicating conversion

results ready, see note below) without AUX

t

ADVC's last PEC byte to HS = 0x0F (hand shake byte read by RDCV indicating conversion

results ready, see note below) with AUX

t

855 to 1260µs

3*

Rev A

29

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LTC2949

SERIAL INTERFACES

Note: If the first HS byte of the RDCV data is 0x0F, the conversion results of the very same data set are already valid. If

the first HS byte of the RDCV data is 0x00, the conversion results of the very same data set are not valid. A new RDCV

must be issued to check for updated conversion results. If the first HS byte of the RDCV data is 0x00 the host can

continue to read HS bytes until it changes to 0x0F. The following RDCV command for sure will have valid conversion

results, still, the HS byte of the very same data set will be 0x00, because it was already internally cleared after it was

read 0x0F in the previous RDCV.

The following diagram shows details on LTC2949’s fast continuous conversion timing. Fast continuous operation

is started by a direct write command that sets bit FACONV and at least one of the channel bits (CH1, CH2, AUX) in

register FACTRL.

FIFO READ

FACONV = 1

RDCV

ADC

I2

•

I2

ADC

BAT

AUX

BAT

AUX

BAT

AUX

BAT

AUX

ADC

AUX

2949 F16

t

or t

1

t

3

1*

2

Figure 16. Timing for LTC2949’s Fast Continuous Current and Voltage Measurements.

PARAMETER

DESCRIPTION

VALUE/TOLERANCE

6 to 8μs

Direct write's last PEC byte to start of conversion latency without AUX conversion

t

1

Direct write's last PEC byte to start of conversion latency with AUX conversion

Conversion time

t

6 to 170µs

1*

t

742 to 821µs

0 to 315µs

2

3

Any sample's start of conversion to HS = 0x0F (hand shake byte read by RDCV indicating

conversion results ready) or to sample available via FIFO read operation

t

Rev A

30

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LTC2949

SERIAL INTERFACES

Fast AUX Measurements

and disable FACONV periodically or to perform repetitive

FSSHT measurements it is recommended to configure

CH1 for slow and CH2 for fast mode, which ensures the

slow channel being updated periodically.

It is not possible to change the AUX MUX configuration

during fast continuous mode (FCM) measurements.

FAMUXP, FAMUXN can be written and the same value

read back at any time, but the internal MUX will only be

set to the requested configuration when receiving a new

fastconversionrequest.ThisiseithertheADCVcommand

for fast single shot (FSSHT) or the transition from 0 to 1

of the FACONV bit for FCM measurements.

Fast AUX Round-Robin Measurements

FSSHT measurements shall be used in applications that

require different inputs via the AUX MUX at high update

rates (faster than 100 ms). Optionally, the FSSHT mea-

surements can be surrounded by FCM periods, during

which a single MUX input is converted continuously. The

conversion results of the FCM periods can be read via the

FIFO registers or via RDCV. Reading of conversion results

from FIFOs is possible at any time. Still, the FSSHT trigger

command (ADCV while CONT= 1 and FACTRL unequal

zero) will clear all FIFOs.

When leaving the FCM (FACONV = 0), the host must wait

for the last conversion being completed before any new

fast conversion is triggered. This can be achieved by

waiting at least 1.26 ms.

If both channels are configured fast, it must be ensured

that either the FCM stays active for at least 128 samples

or FSSHT measurements are inhibited for at least 100ms.

Only after every 128 samples / 100 ms, the slow channel

registers (including STATUS, FAULTS, EXTFAULTS) are

updated. In applications in which it is required to enable

Following table shows an example sequence of 4 FSSHT

measurements that interrupt a FCM period. If only FSSHT

measurements are required, the rows CONT0, CONT1 can

be omitted.

NAME

MOSI / MISO

DESCRIPTION

CONT0

MOSI:FEF5EB50400EE4C6

MISO:XXXXXXXXXXXXXXXX

Write to FACTRL to disable FCM (FACONV = 0)

MUX0

ADCV

RDCV

MUX1

ADCV

RDCV

MUX2

ADCV

RDCV

MOSI:FEF3C7984500013D6E

MISO:XXXXXXXXXXXXXXXXXX

Write two bytes to FAMUXN to select V1 vs. GND

(NTC)

MOSI:FB60FADE

MISO:XXXXXXXX

ADCV to trigger conversion

MOSI:F8040970FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

MISO:XXXXXXXX010000000000FE4AE8180F0F0F0FC602

RDCV to read conversion results

MOSI:FEF3C798450016C1BA

MISO:XXXXXXXXXXXXXXXXXX

Write two bytes to FAMUXN to select VREF2 vs.

GND

MOSI:FB60FADE

MISO:XXXXXXXX

ADCV to trigger conversion

MOSI:F8040970FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

MISO:XXXXXXXX000000000000C212610F0F0F0F0F76B6

RDCV to read conversion results

MOSI:FEF3C7984517007512

MISO:XXXXXXXXXXXXXXXXXX

Write two bytes to FAMUXN to select GND vs.

VREF2_250k

MOSI:FB60FADE

MISO:XXXXXXXX

ADCV to trigger conversion

MOSI:F8040970FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

MISO:XXXXXXXX000000000000C212E7180F0F0F0F1A78

RDCV to read conversion results

Rev A

31

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LTC2949

SERIAL INTERFACES

NAME

MOSI / MISO

DESCRIPTION

MUX3

MOSI:FEF3C7984500174A88

MISO:XXXXXXXXXXXXXXXXXX

Write two bytes to FAMUXN to select

VREF2_250k vs. GND

ADCV

MOSI:FB60FADE

MISO:XXXXXXXX

ADCV to trigger conversion

RDCV

MOSI:F8040970FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

MISO:XXXXXXXX000000000000C2121AE70F0F0F0F7C26

RDCV to read conversion results

MUXCONT

MOSI:FEF3C79845111294A6

MISO:XXXXXXXXXXXXXXXXXX

Write two bytes to FAMUXN to select CF2P vs.

CF2M (necessary to do the open wire check

during the FCM)

CONT1

MOSI:FEF5EB50400F6FF4

MISO:XXXXXXXXXXXXXXXX

Write to FACTRL to enable FCM (FACONV = 1)

Note 1: MISO data is only shown as an example and the actual data may change. ‘X’ indicates don’t care data.

Note 2: A delay of ≥ 1.26 ms is mandatory between any ADCV and RDCV to ensure valid conversion result readings.

Note 3: Above MUX settings convert one external pin voltage V1 vs. GND and the internal VREF2 in three different ways. This example and

can be adjusted and extended to any MUX configurations required.

Note 4: CONT0 and MUX0 can be merged to a single 3-write command to FAMUXN, FAMUXP, FACTRL (MOSI: 0xFEF3C7984600010E9516)

Note 5: When LTC2949 is in STANDBY state it can be moved to MEASURE state at any time by writing CONT=1. From the write command

it takes t

until the MEASURE state is active and then worst case 140ms until the first slow channel conversion results can be read

IDLE_CORE

form LTC2949's registers. First fast measurements can be performed, if FACTRL was configured appropriately, already when MEASURE

state is active.

Note 6: The following sequence allows a fast and efficient initialization of LTC2949 before any fast conversions can be performed:

1. Wakeup, configure ADCCONF and perform ADJUPD as required.

2. Write 0x08 (CONT) to OPCTRL

3. 3-Byte-Write to FAMUXN (e.g. 0x00 = GND), FAMUXP (e.g. 0x16 = VREF2), FACTRL (e.g. 0x02 = FACHA or another allowed combination

to perform any fast conversion)

4. Send any ADxx (e.g. ADCV, see table 17)

5. Wait at least 1.2 ms

6. Send any RDxx (e.g. RDCVA, see table 18). If HS byte is unequal 0x0F go back to 3.

7. Initialization is done. LTC2949 is now in MEASURE mode and any fast conversions can be performed subsequently (e.g. the sequence

from above table)

Rev A

32

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LTC2949

SERIAL INTERFACES

Direct Read/Write Command (DCMD)

To access the full register map of the LTC2949, a special direct command (DCMD) is provided which is not used by

other LTC68xx Cell Monitors. DCMD allows to read/write arbitrary number of bytes from/to LTC2949's register map.

The LTC2949 auto-increments its address pointer after each data byte, so multiple registers can be written/read as part

of a single transaction. Data packets from one to up to 16 bytes are interleaved by a two-byte data PEC. Data packets

written without PEC are discarded. Read commands may stop at any byte.

Table 11. Direct Read/Write Command Format

Byte

0

1

2

3

4

5

…

N+4

N+5

N+6

N+7

…

2N+6

2N+7 2N+8

…

R/W

Master to slave (MOSI)

Write commands: Master to slave (MOSI)

Read commands: Slave to master (MISO)

Name DCMD RADDR PEC0 PEC1 ID

DATA

…

DATA

PEC0 PEC1 DATA

…

DATA2

N-1

PEC0 PEC1

…

0

N-1

N

ID byte is used to distinguish between read and write commands and it defines the number of data bytes per PEC (parameter N in above table). The ID

byte is not part of any PEC, instead it has intrinsic error detection via redundancy and error check bits. See following tables for details.

Table 12. Bit Definitions of Byte ID[7:0]

ID[7]

ID[6]

ID[5]

ID[4]

ID[3]

ID[2]

ID[1]

ID[0]

RW

NOT RW PECC[3] XOR PECC[2]

PECC[3] PECC[2] PECC[1] XOR PECC[0]

PECC[1]

PECC[0]

Table 13. ID[7:0] Byte Format Description

NAME

DESCRIPTION

RW

ID[7] = RW indicates read (RW=1) or write (RW=0) commands. For safe data transmission redundancy is added to ID[6] which

is the inverse of RW (NOT RW, meaning 0 for read and 1 for write).

PECC[3:0]

PEC Configure determines the number of data bytes after which a PEC is transmitted. Number of data bytes is

DECIMAL(PECC[3:0])+1 (parameter N in above table). Allowed values for PECC are 0 to 15 (1 to 16 data bytes per PEC). ID[5]

(= PECC[3] XOR PECC[2]) and ID[2] (=PECC[1] XOR PECC[0]) are error check bits for safe data transmission.

Table 14. Direct Read/Write Command Format Details

NAME

DESCRIPTION

DCMD[7:0]

RADDR[7:0]

PEC0,1

Direct command. It is fixed to the value 0xFE.

Starting register address from which data is read or to which data is written.

The Packet Error Code Bytes PEC0 and PEC1 hold a 15-bit CRC according to CAN BUS CRC15 which is right padded with

0 (see Table 22. Write/Read PEC Format). The PEC in bytes 2-3 is calculated on DCMD and RADDR. All following PECs are

calculated on preceding M data-bytes. The number of data bytes per PEC is defined by the ID byte, which is not part of any

PEC, see below.

For read commands the MOSI line is don’t care, the slave will send the data PEC on its MISO line and the master must

compare it to the PEC calculated on the data received. The read command was successful of both PECs match. For

write commands, the master must send the PEC on its MOSI line and LTC2949 will compare the received PEC with its

internal calculated PEC. In case of a PEC mismatch the data will be discarded and an external communication PEC error

(EXTCOMMERR) will be flagged in the FAULTS register.

DATA

Data bytes to be send to or read from LTC2949’s register map. The starting address is given by RADDR and is auto-

incremented for every data byte.

X

Rev A

33

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LTC2949

SERIAL INTERFACES

Commands Compatible with LTC68xx Cell Monitors

(RDCV, ADCV)

acquired samples can be read from the FIFO registers (FI-

FOI1, FIFOI2, FIFOBAT, FIFOAUX). Still, also in this mode,

it is possible to read the last fast conversion results via

RDCV(RDCVCONF=1).Iffastcontinuousmodeisdisabled

(FACONV=0), any ADCV command will clear all FIFOs.

If needed, samples within FIFOs should be read before

sending an ADCV command while FACONV is cleared.

The LTC2949 supports several RDCV and ADCV style

commands compatible with LTC68xx Cell Monitors.

RDCVA-RDCVF,RDAUXA-RDAUXD,RDCFGA,RDCFGB(all

referred as RDCV commands in this document), ADCV,

ADOW, ADOL, ADAX, ADAXD, ADCVAX and ADCVSC (all

referred as ADCV commands in this document) are sup-

portedasbroadcastandaddressedcommands.Addressed

commands are used to address LTC2949 exclusively. To

trigger actions on LTC2949 and LTC68xx Cell Monitors

simultaneously, broadcast commands are used. This is

forexampleusefultoinitiatingADCconversionsofseveral

devices at the same time. No matter if LTC2949 is con-

nected parallel to or on top of a daisy chain, addressed

ADCV commands can trigger measurements on LTC2949

only and broadcast ADCV commands can perform syn-

chronous ADC conversions on all devices connected to

the SPI / isoSPI bus. The conversion starts at the end of

the PEC for all devices.

In the configuration where LTC2949 is on top of a daisy

chain, after a broadcast RDCV command, the stacked

LTC68xxCellMonitorsturnintoacascadedshiftregister,in

whichdataisshiftedthrougheachdevicetothenextdevice

in the stack. In this scenario, LTC2949 responds to RDCV

commands only if the Broadcast Read Enable bit (BCREN)

in the Register Control Register (REGSCTRL) is set.

In the scenario where LTC2949 is placed in parallel to

a daisy chain of LTC68xx Cell Monitors, the bit BCREN

must be cleared (default) to avoid bus collisions. Still,

any broadcast RDCV may clear LTC2949's internal HS

byte (see below) if the bit RDCVCONF is set, no matter if

BCREN is set or not. For this reason, it is recommended

to read LTC2949’s fast conversion results before reading

from the LTC68xx Cell Monitors. Or, if for software tim-

ing reasons it is necessary to read from the LTC68xx Cell

Monitors first, the bit RDCVCONF must be cleared before

(it must be set again afterwards to read fast conversion

data from LTC2949).

In cases where LTC2949 is connected parallel to a daisy

chain, direct read commands (DCMD) must be used

to read register data and addressed RDCV commands

(with RDCVCONF=1) must be used to read the last fast

conversion results. If LTC2949 is connected on top of a

daisy chain, broadcast RDCV commands must be used

to read register data (RDCVCONF=0) or to read the last

fast conversion results (RDCVCONF=1) depending on

setting of REGSCTRL.RDCVCONF. Write to LTC2949’s

register map is always done with direct write commands

(DCMD) independent of the bus topology. See Table 10

(Communication with LTC2949) for a summary of all

possible communication scenarios.

The last results of any fast conversion can be read out by

the RDCV command, providing sequentially the results

of I1, I2, BAT and AUX (least significant bytes first to be

compatible with LTC68xx Cell Monitors) followed by one

or more hand shake (HS) bytes, indicating if the data is

new (0x0F) or old (0x00). Once LTC2949 sends the HS

byte, it will continue sending it as long as the master is

reading bytes. Still, a PEC will always be send for every 6

data bytes. Per transaction, the HS byte may only change

from 0x00 to 0x0F, once it is 0x0F it won’t change. This

allows the master to poll for conversion results being

ready by checking for a transition of the HS byte from

0x00 to 0x0F. If the first HS byte is 0x0F the conversion

data received with that command is already new and valid.

If the first HS byte is 0x00 the data received in the same

transaction was not yet updated. A subsequent RDCV

Before LTC2949 can react on ADCV commands it must be

runninginslowcontinuousmeasurementmode(bitCONT

in OPCTRL), at least one fast measurement channel must

be selected via the Fast Control Register (FACTRL) and

optionally, to make also fast BAT conversions via one of

the power ADCs (P1 or P2 in voltage mode), P1ASV and/

or P2ASV in the ADC configuration register (ADCCONF)

must be set. If LTC2949 is running in fast continuous

mode (FACONV=1) any ADCV command is ignored and

Rev A

34

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LTC2949

SERIAL INTERFACES

command is necessary to read the updated conversion

results, still, the HS byte will be reported as 0x00 for this

RDCV command, as it was internally already cleared after

it was read 0x0F with the previous RDCV.

Forfastcontinuousmeasurement,thesamplerateisfixedto

1.25kspsandthementioneddelayisjustalatencybetween

the actual measurements and the time the samples are

available to be read. The master shall wait at least 1.26ms

between the time fast continuous mode is enabled and the

firsttimeanyFIFOregisterisread, toallowthefirstsample

to be read from the FIFO. Alternatively, it is also possible

to use a RDCV command to check when the first sample

is ready (see HS byte above) and then read all samples

from the FIFO registers periodically.

LTC2949’s fast conversion time is typically 0.8ms. Addi-

tional processing time is necessary for the results being

ready to be read by the master. Worst case, 1.26 ms after

a conversion was triggered, the results can be read via a

FIFO register (in case of fast continuous mode) or via the

RDCV command. For fast single shot measurements, this

limits the maximum guaranteed sample rate to ~0.8ksps.

Table 15. Format of ADCV/RDCV Style Commands. Only for RDCV Commands the Slave Sends Data to the Master on the MISO Line

BYTE

0

1

2

3

4

…

9

10

11

12

…

17

18

19

…

R/W

Master to slave (MOSI)

Slave to master (MISO)

DATA6 PEC0 PEC1 DATA7

Name CMD0 CMD1 PEC0 PEC1 DATA0

…

DATA11

PEC0 PEC1

…

CMD0 and CMD1 are the command bytes. The format for the commands is shown in Table 16. CC[10:0] is the 11-bit command code. A list of

supported command codes is shown in Table 17 and Table 18. Broadcast commands have a value 0, addressed commands have a value 1 for

CMD0[7] through CMD0[3]. The PEC must be computed on the entire 16-bit command (CMD0 and CMD1).

Table 16. CMD0, CMD1 Command Bytes Format. Data is Send from Master to Slave (MOSI). A/B is 0 for Broadcast and 1 for

Addressed Commands.

NAME

CMD0

CMD1

BIT 7

A/B

BIT 6

A/B

BIT 5

A/B

BIT 4

A/B

BIT 3

A/B

BIT 2

CC[10]

CC[2]

BIT 1

CC[9]

CC[1]

BIT 0

CC[8]

CC[0]

CC[7]

CC[6]

CC[5]

CC[4]

CC[3]

Rev A

35

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LTC2949

SERIAL INTERFACES

Table 17. ADCV Style Commands. LTC2949 Performs a Fast Conversion Depending on FACTRL/ADCCONF Registers Upon Those

Commands

NAME

ADCV

CMD0[7:3]

CC[10:0]

DESCRIPTION

Broadcast: all 0

Addressed: all 1

0 1 x x 1 1 x 0 x x x

0 1 x x x 1 x 1 x x x

0 1 x x 0 0 x 0 0 0 1

1 0 x x 1 1 0 0 x x x

1 0 x x 0 0 0 0 x x x

1 0 x x 1 1 x 1 1 1 1

1 0 x x 1 1 x 0 1 1 1

LTC2949 reacts to all commands in the same way by triggering a fast

conversion (if enabled via FACTRL register).

ADOW

ADOL

ADAX

ADAXD

ADCVAX

ADCVSC

Table 18. RDCV Style Commands. Used to Read Fast Conversion Results or for Indirect Memory Map Reads from LTC2949

NAME

RDCFGA

RDCFGB

RDCVA

CMD0[7:3]

CC[10:0]

DESCRIPTION

Broadcast: all 0

Addressed: all 1

0 0 0 0 0 0 0 0 0 1 0

0 0 0 0 0 1 0 0 1 1 0

0 0 0 0 0 0 0 0 1 0 0

0 0 0 0 0 0 0 0 1 1 0

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 0 1 0 1 0

0 0 0 0 0 0 0 1 0 0 1

0 0 0 0 0 0 0 1 0 1 1

0 0 0 0 0 0 0 1 1 0 0

0 0 0 0 0 0 0 1 1 1 0

0 0 0 0 0 0 0 1 1 0 1

0 0 0 0 0 0 0 1 1 1 1

LTC2949 reacts to all commands in the same way by either transmitting fast

conversion results (default, RDCVCONF=1) or by transmitting register data

(RDCVCONF=0)

RDCVB

RDCVC

RDCVD

RDCVE

RDCVF

RDAUXA

RDAUXB

RDAUXC

RDAUXD

Rev A

36

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LTC2949

SERIAL INTERFACES

The RDCV command allows reading data packets much longer than the daisy chain shift register. The length of the

shift register is 64 • M bits, whereas M is the number of elements in the chain excluding LTC2949. Data from the

LTC2949 is received by the master after 64 • M data bits starting with bit I1[7] according to the figure below. A PEC

is calculated after every 6 data bytes. After the transmission of the conversions results, the LTC2949 continuously

sends the hand shake byte (HS) indicating if the data is new (0x0F) or old (0x00). A transition of the hand shake

byte from 0x00 to 0x0F indicates the arrival of new data, which can be read out by a subsequent RDCV command.

Table 19. RDCV Command Format. CMD0, CMD1 According to Table 18 (RDCV Style Commands). Requires RDCVCONF=1.

CMD0

BAT[15:8]

PEC0

CMD1

PEC0

PEC1

HS

PEC0

PEC1

HS

PEC1

AUX[7:0]

HS

I1[7:0]

AUX[15:8]

HS

I1[15:8]

I2[7:0]

I2[15:8]

BAT[7:0]

HS

PEC0

PEC1

HS

……

Note: The conversion results I1, I2, BAT, AUX are converted to volts by multiplication with the LSB size 7.60371 µV for the current and 375.183 µV for the

BAT and AUX channel.

Indirect Memory Access RDCV Command

DCMD is the recommended way of reading data from the LTC2949 in addressable mode. When LTC2949 is the last ele-

ment in a daisy chain, an RDCV has to be used to read data from the LTC2949, as DCMD is not supported by LTC68xx

Cell Monitors and therefore does not configure them as shift registers, In default, the LTC2949 will respond to RDCV

with the fast mode conversion results as described above (RDCVCONF = 1).

In order to gain access to the entire register map of LTC2949 an address pointer can be set causing the LTC2949 to

provide data starting at that register address on subsequent RDCV commands. To use this indirect memory access

RDCV command, the RDCV Configuration Bit (RDCVCONF) has to be reset and Broadcast Read Enable bit (BCREN) has

to be set in REGSCTRL and the starting pointer must be written to the RDCV Indirect Address Register (RDCVIADDR).

In this way any register can be read by subsequent RDCV commands. The address pointer is auto-incremented after

every data byte for reading data bursts of any length. A PEC is transmitted after every six data bytes. Once the REGSC-

TRL is written accordingly, only the Indirect Address Register must be updated to read from other memory locations.

PleasenotethattheRDCVIADDRcanalsobewrittenbeforetheREGSCTRLifasingleDCMDspanningfromRDCVIADDR

to REGSCTRL is used. For this single write burst, the two bytes between RDCVIADDR and REGSCTRL are don't care

and can be written 0x00.

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Figure 17. Indirect Memory Access Read Procedure Using RDCV Command

Table 20. Indirect Address RDCV Command Format, CMD0, CMD1 According to Table 18 (RDCV Style Commands), Requires

RDCVCONF = 0 and BCREN = 1

CMD0

PEC0

PEC1

PEC0

PEC1

……

PEC1

DATA

0

1

2

3

4

DATA

5

6

7

8

9

10

11

PEC0

DATA is the content of the register at the starting address that was written to RDCVIADDR. DATA is the content of

0

1

the register at the following address and so on.

Rev A

37

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LTC2949

SERIAL INTERFACES

Packet Error Code

4. Go back to step 2 until all the data is shifted. The final

PEC (16-bits) is the 15-bit value in the PEC register

right padded with 0. An example to calculate the PEC

for a 16-bit word (0x0001) is listed in Table 21. The

PEC for 0x0001 is computed as 0x3D6E after stuffing

a 0-bit at the LSB. For longer data streams, the PEC is

valid at the end of the last bit of data sent to the PEC

register. LTC2949 calculates PEC for any command

or data received and compares it with the PEC follow-

ing the command or data. The command or data is

regarded as valid only if the PEC matches. LTC2949

also attaches the calculated PEC at the end of the data

it shifts out. Table 22 shows the format of PEC while

writing to or reading from LTC2949.

The packet error code (PEC) is a 15-bit cyclic redundancy

check (CRC) value calculated for all of the bits in a reg-

ister group in the order they are passed, using the initial

PEC seed value of 000000000010000 and the following

characteristic polynomial: x15 + x14 + x10 + x8 + x7 +

x4 + x3 + 1. To calculate the 15-bit PEC value, a simple

procedure can be established:

1. Initialize the PEC to 000000000010000 (PEC is a 15-

bit register group)

2. For each bit DIN coming into the PEC register group,

set

IN0 = DIN XOR PEC [14]

IN3 = IN0 XOR PEC [2]

IN4 = IN0 XOR PEC [3]

IN7 = IN0 XOR PEC [6]

IN8 = IN0 XOR PEC [7]

IN10 = IN0 XOR PEC [9]

IN14 = IN0 XOR PEC [13]

3. Update the 15-bit PEC as follows

PEC [14] = IN14,

PEC [13] = PEC [12],

PEC [12] = PEC [11],

PEC [11] = PEC [10],

PEC [10] = IN10,

PEC [9] = PEC [8],

PEC [8] = IN8,

PEC [7] = IN7,

PEC [6] = PEC [5],

PEC [5] = PEC [4],

PEC [4] = IN4,

PEC [3] = IN3,

PEC [2] = PEC [1],

PEC [1] = PEC [0],

PEC [0] = IN0

Rev A

38

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LTC2949

SERIAL INTERFACES

Table 21. PEC Calculation for 0x0001

PEC[14]

PEC[13]

PEC[12]

PEC[11]

PEC[10]

PEC[9]

PEC[8]

PEC[7]

PEC[6]

PEC[5]

PEC[4]

PEC[3]

PEC[2]

PEC[1]

PEC[0]

IN14

0

1

0

1

0

1

0

1

0

1

0

2

0

1

0

1

0

3

0

1

0

4

0

1

0

1

0

5

0

1

0

6

0

1

0

7

0

1

0

8

0

1

0

1

0

9

1

0

1

0

10

1

0

1

0

1

0

1

0

1

0

1

0

1

0

11

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

12

1

0

1

0

1

0

1

0

1

0

13

1

0

1

0

1

0

1

0

1

0

14

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

15

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

IN10

PEC Word

IN8

IN7

IN4

IN3

IN0

DIN

Clock Cycle

16

Table 22. Write/Read PEC Format

NAME

PEC0

PEC1

RD/WR

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PEC[7]

0

PEC[14]

PEC[6]

PEC[13]

PEC[5]

PEC[12]

PEC[4]

PEC[11]

PEC[3]

PEC[10]

PEC[2]

PEC[9]

PEC[1]

PEC[8]

PEC[0]

Improved PEC Calculation

derived PEC calculation method. There are two functions,

thefirstfunctioninit_PEC15_Table()shouldonlybecalled

once when the microcontroller starts and will initialize a

PEC15 table array called pec15Table[]. This table will be

used in all future PEC calculations. The pec15 table can

also be hard coded into the microcontroller rather than

running the init_PEC15_Table() function at startup. The

pec15() function calculates the PEC and will return the

correct 15-bit PEC for byte arrays of any given length.

The PEC allows the user to have confidence that the serial

data read from the LTC2949 is valid and has not been cor-

ruptedbyanyexternalnoisesource.Thisisacriticalfeature

for reliable communication and the LTC2949 requires that

aPECbecalculatedforalldatabeingreadfromandwritten

to the LTC2949. For this reason it is important to have an

efficient method for calculating the PEC. The code below

demonstrates a simple implementation of a lookup table

Rev A

39

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LTC2949

SERIAL INTERFACES

/************************************

Permission to freely use, copy, modify, and distribute this software for any

purpose with or without fee is hereby granted, provided that the above

copyright notice and this permission notice appear in all copies:

THIS SOFTWARE IS PROVIDED “AS IS” AND LTC DISCLAIMS ALL WARRANTIES

INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO

EVENT SHALL LTC BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL

DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM ANY USE OF SAME, INCLUDING

ANY LOSS OF USE OR DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE

OR OTHER TORTUOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR

PERFORMANCE OF THIS SOFTWARE.

***********************************************************/

int16 pec15Table[256];

int16 CRC15_POLY = 0x4599;

void init_PEC15_Table()

{

for (int i = 0; i < 256; i++)

{

remainder = i << 7;

for (int bit = 8; bit > 0; --bit)

{

if (remainder & 0x4000)

{

remainder = ((remainder << 1));

remainder = (remainder ^ CRC15poly)

}

else

{

remainder = ((remainder << 1));

}

pec15Table[i] = remainder&0xFFFF;

}

unsigned int16 pec15 (char *data , int len)

{

int16 remainder,address;

remainder = 16;//PEC seed

for (int i = 0; i < len; i++)

{

address = ((remainder >> 7) ^ data[i]) & 0xff;//calculate PEC table address

remainder = (remainder << 8 ) ^ pec15Table[address];

}

return(remainder*2);//TheCRC15hasa0intheLSBsothefinalvaluemustbemultipliedby2

}

Rev A

40

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LTC2949

REGISTER MAP

Rev A

41

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LTC2949

REGISTER DESCRIPTION

Register Naming Conventions

RW Read-Write

DEF Default Value

RO

SO

Read Only

SI

UI

Signed Integer

Set Only (Note)

Unsigned Integer

Note: Write 1 to SO bits to request the associated action. Successful write can be checked by a read command directly following the write command. After

the action was performed the SO bit will be cleared automatically by LTC2949. Do not write to registers with SO bits, before all SO bits were read as 0. The

typical processing time per action is t

or t

depending on operation mode, see related bit description for details.

IDLE_CORE

CONT

MEMORY MAP AND PAGING MECHANISM

The memory map of the LTC2949 is organized in two pages, PAGE0 and PAGE1. PAGE0 contains all slow channel

result quantities, control and status registers while PAGE1 contains all threshold and configuration registers. Each

page has a register address space ranging from 0x00 to 0xEF, with each register consisting of one 8-bit byte of data.

Registers 0xF0 to 0xFF are common to both register pages. Register REGSCTRL at 0xFF is part of this range and is

used to switch between pages, see below. For clarity, all register addresses on PAGE1 are expressed as p1.0xYY in the

following while addresses on PAGE0 are simply referred to as 0xYY.

Multiple-byte data is stored with most significant byte at the lowest address (little-endian). For instance, the MSB

C1[47:40] of the quantity C1 is stored at address 0x00 in PAGE0.

Note that reading data from LTC2949's memory map (no matter if using direct command or indirect memory ac-

cess RDCV command with RDCVCONF=0) reports MSBytes first, while reading fast conversion results via RDCV

(RDCVCONF=1) reports LSBytes first.

Some addresses in the register map are not used and are reserved. Bits in non-reserved registers that are not explic-

itly described are also reserved. Writing to unused reserved registers or reserved bits in non-reserved registers may

result in unwanted behavior of the LTC2949, reserved bits in non-reserved registers should be written as 0; reading of

unused registers is generally harmless but will return random data. If software detection of device revision is neces-

sary, then contact the factory for details.

Register Control Register

The Register Control Register (0xFF) selects the active memory page, allows to configure the LTC2949 to respond to

broadcast read commands, configures the RDCV command to indirect memory access mode and provides a memory

locking mechanism.

Table 23. Control Register REGSCTRL (0xFF)

BIT

SYMBOL

TYPE

DEFAULT

OPERATION

0

PAGE

RW

0

Memory Map Page Select

0: PAGE0 of the memory map is selected.

1: PAGE1 of the memory map is selected.

2

BCREN

RW

0

Broadcast Read Enable

0: LTC2949 does not respond to broadcast read commands

1: LTC2949 responds to broadcast read commands

[5:4]

MLK[1:0]

00

Memory Lock

00: Memory not locked

01: Memory lock requested by master

10: Memory locked

7

RDCVCONF

RW

1

RDCV Configuration Bit

0: Indirect memory access mode. RDCV will report data starting at address written to

RDCVIADDR (0xFC).

1: RDCV command will report latest fast channel conversion results.

Rev A

42

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LTC2949

REGISTER DESCRIPTION

LTC2949 provides a mechanism to lock the memory to

keep coherency between registers when accessing the

memory.Amemorylockingcanberequestedbythemaster

by setting bits MLK[1:0] to 01. Now the LTC2949 updates

its registers, e.g. with measurement results. During this

time, read and write access to the LTC2949 memory apart

from registers REGSCTR and RDCVIADDR is blocked.

After all registers are updated by the LTC2949, it sets

MLK[1:0] to 10 to indicate to the Master that memory is

locked. The LTC2949 does not update the memory map

any more until the master unlocks the memory by writing

MLK[1:0] to 00.

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The LTC2949’s internal memory is still updated while the

memory is locked and thus accumulation of values and

updating of alerts is not interrupted. Once the memory is

locked the master can read consistent data even by single

byte access. Data does not change between those single

read transactions. It is also possible to manipulate result

parametervaluese.g.tosetacertainstartvalueforCharge

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Figure 19. Memory Locking

or Energy etc. Coherency within a single row of 16 bytes

(register ranges 0x00 to 0x0F, 0x10 to 0x1F, ... and 0xE0

to 0xEF) is always guaranteed for multiple byte read and

write bursts and does not require memory locking.

Table 24. Operation Control OPCTRL (0xF0)

BIT

SYMBOL TYPE DEFAULT OPERATION

0

SLEEP

RW

SO

0

0: Normal operation

1: SLEEP. The LTC2949 will exit SLEEP state if the pin CSB is pulled low in SPI mode or if a wake-up pulse

followed by another "Long -1" pulse is sent in isoSPI mode.

1

2

CLR

1: Clear. The Accumulation and Tracking (max/min) registers are cleared: C1, E1, TB1, C2, E2, TB2, C3, TB4, E4,

TB4 IMAX, IMIN, PMAX, PMIN, VMAX, VMIN, TEMPMAX, TEMPMIN, VDVCCMAX, VDVCCMIN, SLOTXMAX,

SLOTXMIN

SSHOT

1: Single Shot Measurement. LTC2949 enters state MEASURE and returns to state STANDBY after completion

of a single set of measurements of Current, Voltage, Power, Temperature, V , SLOT1, SLOT2, V . The result

CC

REF

registers are updated and SSHOT is cleared when returning to STANDBY. If CONT is set, it is cleared after

completion of any conversion cycle in progress and the single shot measurement is executed.

3

5

CONT

RW

SO

0

0: Continuous measurement is disabled

1: Continuous measurement is enabled after < t

. Measurement cycles run continuously. Charge, Energy

IDLE_CORE

and Time measurements are only active in Continuous mode.

ADJUPD

To insure data coherency, changes in the 2nd page's configuration registers, except threshold settings,

only become effective after an update procedure, which is initialized by setting bit ADJUPD. Once the new

configuration values are valid, LTC2949 resets the bit ADJUPD. Changes to the threshold registers may be done

at any time and don't require the ADJUPD procedure.

1: Request an update of configuration registers on 2nd memory page, except threshold settings.

0: Update done

7

RST

SO

0

0: Normal operation, 1: Reset device. As default the reset feature is locked and writing 1 to this bit has no effect.

See RSTUNLCK for procedure how to reset the device.

Note 9: ADJUPD shall be issued when in STANDBY mode only. The recommended implementation is to set ADJUPD as the last action of the initialization

routine, before entering continuous mode. Once ADJUPD is set it takes a maximum of 100ms until LTC2949 has finished the internal update process and the

bit ADJUPD is cleared automatically. Thus it is also possible to poll the bit ADJUPD for being cleared to indicate when the operation is done.

In cases where it is necessary to assert ADJUPD after CONT was enabled, it is necessary to clear the bit CONT before, wait 100ms to ensure that all

measurement cycles have completed and then assert ADJUPD. After ADJUPD was cleared automatically, the Continuous Mode may be entered again.

To avoid the 100ms wait time when going to STANDBY mode, it is also possible to clear CONT and set CLR at the same time and poll for the bit CLR being

cleared by LTC2949. This indicates also the end of any previously ongoing measurement cycle.

Rev A

43

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LTC2949

REGISTER DESCRIPTION

Reading of status (0x80), faults (0xDC-0xDD) and alert (0x81-0x87) registers may always be done without memory

locking. Still, once it is necessary to clear those registers, memory locking is mandatory to avoid missing any alert

and faults reporting. If an alert condition occurs while the memory is locked, LTC2949 will set the corresponding bit

after the memory is unlocked by the host. This rule must be followed independent of the core state, as certain faults

may also be raised in STANDBY mode.

Any fast conversions are not affected by the memory locking mechanism, thus it is still possible to change FAMUX

settings, trigger fast single shots, read results via RDCV. Also reading conversion results from the FIFOs during fast

continuous measurements is still possible.

Operation Control Register

The Operation Control Register OPCTRL (0xF0) controls LTC2949's transitions between its CORE States: SLEEP,

STANDBY, and MEASURE. Furthermore, it allows to clear accumulation and tracking registers, to validate changes of

the configuration registers and to reset the LTC2949.

REGISTER MAP PAGE0

Wake Up Acknowledge

The LTC2949 automatically returns to SLEEP state if no wake up confirmation command is received within 1 second

after entering STANDBY state. Wake up confirmation can be either writing 0x00 to register 0x70 or starting of a mea-

surement. Before wake up confirmation, WKUPACK will report a countdown from 0xFF to 0x00 within approximately

1 second. Countdown will stop and WKUPACK will statically report 0x00 after wake up confirmation.

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Note: When operating on top of a daisy chain, more than one dummy byte has to be send every time the isoSPI chain has to be woken up. See also

'Waking a Daisy Chain' chapters in latest cell monitor datasheets (e.g. LTC6812) for recommended procedures.

Figure 20a. Flow Chart of Recommended Wake-Up Procedure and Example SPI Transactions for Direct and Indirect Read Scenarios

Rev A

44

For more information www.analog.com

LTC2949

REGISTER DESCRIPTION

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Figure 20b. Flow Chart of Recommended Wake-Up Procedure Implemented in a Sequence Without Polling

Rev A

45

For more information www.analog.com

LTC2949

REGISTER DESCRIPTION

Table 25. Wake Up Acknowledge Register (0x70)

BIT

SYMBOL

TYPE

DEFAULT

OPERATION

[7:0]

WKUPACK

RW

see above 0x00: Wake up is confirmed. Part will not return to SLEEP.

Anything else: Wake up is not confirmed. Part will return to SLEEP.

In applications where LTC2949 is connected on top of a daisychain, the bit BCREN in REGSCTRL must be set before

being able to read from LTC2949. This is only possible after the boot sequence has finished. Polling of the SLEEP bit

being cleared can still be implemented by interleaving the read of OPCTRL with a write to REGSCTRL with BCREN=1 (all

other bits 0). As this scenario also implies indirect register reads via RDCV commands (for this reason RDCVCONF=0),

the write to REGSCTRL can be done in a single four byte burst together with RDCVIADDR (set to 0xF0); the two bytes

between RDCVIADDR and REGSCTRL set to 0x00. Thus the four bytes to be written are 0xF0,0x00,0x00,0x04 and the

following RDCV command will report the content of OPCTRL. Still, if the boot sequence is not completed, LTC2949

will ignore the broadcast RDCV command and thus the master will read always 0xFF (which is also compatible with

SLEEP=1), including PEC=0xFFFF if 8 bytes are read (its not necessary to read till the PEC in this case). After the boot

OPCTRL will be read as 0x00.

Accumulated Result Registers

The registers in Table 26 and Table 27 contain the accumulated quantities Charge, Energy and Time. The Time regis-

ters are unsigned integer values while the Charge and Energy registers are two’s complement signed integer values.

The value of each accumulated quantity can be determined by multiplying the respective register value with the cor-

responding LSB value from Table 26 (if the internal clock or crystal is used as a reference clock) or Table 27 (if an

external reference clock is used).

Table 26. Accumulated Results Register Parameters for Use with Crystal or Internal Clock

LSB (4MHz CRYSTAL OR PRE (4MHz DIV (4MHz

ADDRESS

NAME

TYPE

RW

DEFAULT

0x00

PARAMETER

INTERNAL CLOCK)

LSBC1 = 377.887e-12

LSBE1 = 2.32175e-09

CRYSTAL)

UNIT

SI/UI

SI

0x00

C1[47:0]

E1[47:0]

TB1[31:0]

C2[47:0]

E2[47:0]

TB2[31:0]

C3[63:0]

TB3[31:0]

E4[63:0]

TB4[31:0]

Charge1 = C1 • LSBC1

Energy1 = E1 • LSBE1

2

30

Vs

2

0x06

V s

SI

0x0C

0x10

Time1 = TB1 • LSBTB1 LSBTB1 = 397.777E-06

s

UI

SI

Charge2 = C2 • LSBC2

Energy2 = E2 • LSBE2

LSBC2 = 377.887e-12

LSBE2 = 2.32175e-09

Vs

2

0x16

V s

SI

0x1C

0x24

Time2 = TB2 • LSBTB2 LSBTB2 = 397.777E-06

Charge3 = C3 • LSBC3 LSBC3 = 377.887e-12

Time3 = TB3 • LSBTB3 LSBTB3 = 397.777E-06

Energy4 = E4 • LSBE4 LSBE4 = 2.32175e-09

Time4 = TB4 • LSBTB4 LSBTB4 = 397.777E-06

s

Vs

s

UI

SI

0x2C

0x34

UI

SI

2

V s

0x3C

s

UI

Charge1, Energy1 and Time1 contain accumulated quantities of Channel1. Charge2, Energy2 and Time2 contain accu-

mulated quantities of Channel2. Charge3 and Time3 contain the weighted sum of charges monitored by Channel1 and

Channel2 and the corresponding time. Similarly Energy4 and Time4 contain the weighted sum of energies monitored

by Channel1 and Channel2 and the corresponding time.

If different sense resistors are used on CH1 and CH2, the LTC2949 uses the ratio of the sense resistors (RSRATIO) set

in the Gain Configuration Registers to compute the correct weighted sums Charge3 and Energy4.

When the internal clock is used, PRE and DIV should be set to their default values which is done by writing 0x07 to register

(0xE9), otherwise the values of PRE(0xE9)[2:0] and DIV(0xE9)[7:3] should be set according to section Timebase Control.

Rev A

46

For more information www.analog.com

LTC2949

REGISTER DESCRIPTION

Table 27. Accumulated Results Register Parameters for Use with External Clock

ADDRESS

0x00

NAME

TYPE

RW

DEFAULT

0x00

PARAMETER

LSB

UNIT

SI/UI

SI

PRE

C1[47:0]

E1[47:0]

TB1[31:0]

C2[47:0]

E2[47:0]

TB2[31:0]

C3[63:0]

TB3[31:0]

E4[63:0]

TB4[31:0]

Charge1 = C1 • LSBC1

Energy1 = E1 • LSBE1

Time1 = TB1 • LSBTB1

Charge2 = C2 • LSBC2

Energy2 = E2 • LSBE2

Time2 = TB2 • LSBTB2

Charge3 = C3 • LSBC3

Time3 = TB3 • LSBTB3

Energy4 = E4 • LSBE4

Time4 = TB4 • LSBTB4

LSBC1 = 1.21899e–5 • 1/fext • 2

• (DIV+1)

Vs

PRE

2

0x06

LSBE1 = 7.4895e–5 • 1/fext • 2

• (DIV+1)

V s

SI

PRE

0x0C

0x10

LSBTB1 = 12.8315 • 1/fext • 2

LSBC2 = 1.21899e–5 • 1/fext • 2

s

UI

SI

PRE

• (DIV+1)

Vs

PRE

2

0x16

LSBE2 = 7.4895e–5 • 1/fext • 2

V s

SI

PRE

0x1C

0x24

LSBTB2 = 12.8315 • 1/fext • 2

LSBC3 = 1.21899e–5 • 1/fext • 2

s

Vs

s

UI

SI

PRE

• (DIV+1)

PRE

0x2C

0x34

LSBTB3 = 12.8315 • 1/fext • 2

LSBE4 = 7.4895e–5 • 1/fext • 2

UI

SI

PRE

2

• (DIV+1)

V s

PRE

0x3C

LSBTB4 = 12.8315 • 1/fext • 2

• (DIV+1)

s

UI

Note: Values of PRE and DIV should be calculated according to Timebase Control section.

For instance, an external clock frequency of 10MHz would require values PRE to be set to 4 and DIV to be set to 19.

With f =10MHz, LSBC1 is calculated as 390.078e-12 VS. To get the Charge1 value, the register content of C1 is

EXT

multiplied with LSBC1. In this case, a C1 register value of 0x 75 5A 10 or 7690768 and the resulting Charge1 is 0.003

VS. For a sense resistor of 300µΩ this corresponds to 10As.

++

LSB values may be calculated easily using the Quick Eval software for the LTC2949 or by using the C/C header files

provided in the code section of the LTC2949 (see LTC2949 evaluation board DC2732A manual for details). The registers

for Charge, Energy and Time can be preset to a non-zero initial value. In Continuous Mode all bytes of the respective

quantity must be written in the same multi-byte transaction or while the memory is locked.

Non-Accumulated Result Registers

Registers in Table 28 contain measured values of Currents, Powers, Voltages, Temperatures, VCC and VREF. All quanti-

ties are represented as two's complement signed integer values.

Current 1 represents the differential voltage sensed between CF1P and CF1M. Current 2 represents the differential volt-

age sensed between CF2P and CF2M. Battery voltage (BAT) is the differential voltage across pins VBATP and VBATM.

Power 1 is the instantaneous multiplication of BAT and current 1. Power 2 is the instantaneous multiplication of BAT

and current 2. Temperature is the temperature of the on-silicon temperature sensor. VCC is the voltage across pins

A/DVCC and AGND. Registers SLOT1 and SLOT2 contain the results of the two multiplexer inputs choosen ac-

cording to Table 58 and can be configured to give out voltage or temperature by means of the NTC Configuration

Registers (Table 70). VREF is the voltage across pins VREF and AGND. The moving average of the four preced-

ing current measurements are stored in I1AVG and I2AVG. The values of these four current measurements are

retained in the Current History registers; Current 1 History 1 is the result prior to Current 1, Current 1 History 2 is

the current result prior to Current 1 History 1, and so on. All measured values are scaled with the LSB values from

. To calculate the physical value of the measured parameter, multiply the register value by the appropriate LSB value.

Table 28. Non-Accumulated Results Register Parameters

ADDRESS

NAME

TYPE

DEFAULT

PARAMETER

Current 1

LSB

950

UNIT

SI/UI

SI

0x90

I1[23:0]

RO

0x00

nV

2

Power 1 (Power, P1ASV =0)

Power 1 (Voltage, P1ASV=1)

Current 2

5.8368

46.875

950

μ[V ]

SI

0x93

0x96

P1[23:0]

I2[23:0]

RO

0x00

µV

nV

SI

Rev A

47

For more information www.analog.com

LTC2949

REGISTER DESCRIPTION

Table 28. Non-Accumulated Results Register Parameters (continued)

ADDRESS

NAME

TYPE

DEFAULT

PARAMETER

Power 2 (Power, P2ASV =0)

Power 2 (Voltage, P2ASV=1)

Current 1 Moving Average

Battery Voltage

LSB

5.8368

46.875

237.5

375

UNIT

SI/UI

SI

2

μ[V ]

0x99

P2[23:0]

RO

0x00

µV

nV

μV

°C

0x9C

0xA0

0xA2

0xA4

0xA6

I1AVG[23:0]

BAT[15:0]

RO

0x00

TEMP [15:0]

VCC[15:0]

Temperature

0.2

Voltage at A/DVCC

SLOT 1 (Voltage)

2.26

mV

μV

°C

SLOT1[15:0]

375

SLOT 1 (Temp.)

0.2

0xA8

SLOT2[15:0]

RO

0x00

SLOT 2 (Voltage)

375

μV

°C

SLOT 2 (Temp)

0.2

0xAA

0xAC

0xB3

0xB6

0xB9

0xBC

0xC3

0xC6

0xC9

0xCC

0xF7

0xF8

0xF9

0xFA

VREF[15:0]

I2AVG[23:0]

I1H1[23:0]

I1H2[23:0]

I1H3[23:0]

I1H4[23:0]

I2H1[23:0]

I2H2[23:0]

I2H3[23:0]

I2H4[23:0]

FIFOI1[15:0]

FIFOI2[15:0]

FIFOBAT[15:0]

FIFOAUX[15:0]

RO

0x00

Voltage at VREF

375

μV

nV

μV

Current 2 Moving Average

Current 1 History 1

Current 1 History 2

Current 1 History 3

Current 1 History 4

Current 2 History 1

Current 2 History 2

Current 2 History 3

Current 2 History 4

Fast Current 1

237.5

950

7.60371

375.183

Fast Current 2

Fast Battery Voltage

Fast AUX HVMUX

The FIFO registers 0xF7 to 0xFA allow to read conversion results in fast continuous mode. When reading from those

registers, the internal address auto-increment stops, allowing to read any number of bytes the fixed addresses. For

each sample, three bytes have to be read which are MSB, LSB and TAG, see also fast mode section and below descrip-

tion for more details.

In Fast Mode, ADC conversion results turn negative when exceeding positive and clip when exceeding negative full-scale

values. In Slow Modes, ADC conversion results clip when exceeding positive and negative full-scale values. Full-scale

values are always beyond the specified input range.

Registers I1AVG (0x9C) and I2AVG (0xAC) are copied to registers 0xB0 and 0xC0, respectively. Thus, 0x9C-0x9E will

report the same values as 0xB0-0xB2 and 0xAC-0xAE will report the same values as 0xC0-0xC2.

Rev A

48

For more information www.analog.com

LTC2949

REGISTER DESCRIPTION

Table 29. FIFO Register Read Format.

DATA BYTE

NAME

S [15:8]

DESCRIPTION

0

MSB of measured sample N

LSB of measured sample N

Tag of sample N

N

1

S [7:0]

N

2

TAG

N

3

S

[15:8]

MSB of measured sample N+1

LSB of measured sample N+1

Tag of sample N+1

N+1

4

[7:0]

5

TAG

…

N+1

…

3*M

3*M+1

3*M+2

S

[15:8]

[7:0]

MSB of measured sample N+M

LSB of measured sample N+M

Tag of sample N+M

N+M

TAG

N+M

The column Data Byte does not count the PEC bytes, which depend on the setting of data bytes per PEC (ID-byte for

DCMD or fixed to six for RDCV). For maximum data throughput it is recommended to read the FIFOs with DCMDs with

16 bytes per PEC and multiples of 16 samples (= 48 data bytes + 3 • 2 PEC bytes).

Table 30. FIFO TAG Definitions.

TAG

NAME

OK

DESCRIPTION

0x00

0x55

0xAA

Valid, new sample

RDOVR

WROVR

Read overrun, sample was already read

Write overrun, FIFO was filled completely and at least one sample was already overwritten

It is recommended to connect LTC2949 always in parallel to a daisy chain. Also, in the scenario where LTC2949 is con-

nected at one end of a reversible isoSPI chain, the default communication should be done with direct read commands.

Only in case the direct isoSPI link to LTC2949 fails, the communication would be routed through the daisy chain.

InthisconfigurationwhereLTC2949isontopofadaisychain, afterthebroadcastRDCVcommand, thestackedLTC68xx

Cell Monitors turn into a cascaded shift register, in which data is shifted through each device to the next device in the

stack. In this scenario, at the end of the read transaction, there is always a fixed number of samples stuck in the shift

register, that is never transmitted to the master.

Several approaches are possible to avoid or minimize the loss of samples. Either fast continuous mode is stopped

(FACONV=0), the FIFO is read until empty and then fast continuous measurement is repeated (FACONV=1). This results

in a time window without measurements, equal to the time it takes to read the samples. For example, at 1Mbit/s serial

clock rate, it takes 0.8 ms (approximately one fast conversion time) to read 24 samples (four byte command and PEC,

72 data bytes, 24 data PEC bytes equals in total 100 bytes or 800 bits). For lower clock speeds or longer cycle times,

where more samples are read per cycle, the following approach is more efficient.

Alternatively, the FIFO read burst must be long enough to always empty the FIFO and read at least one sample with

TAG RDOVR. Still, also here, one sample with TAG OK can arrive after the RDOVR and would then be stuck in the daisy

chain’s shift register. If the latency of the shift register (number of devices in the daisy chain times eight bytes times

eight bit per byte divided by SPI clock speed) is longer than one fast conversion time, even more than one sample can

get stuck in the daisy chain.

Rev A

49

For more information www.analog.com

LTC2949

REGISTER DESCRIPTION

Tracking Registers

The tracking registers keep track of the maximum and minimum values of previous conversions since the last reset.

Value scaling is done in the same manner as the non-accumulated register values, using LSB values from Table 31.

Negative values are treated as smaller (more minimum) than positive values as the minimum registers are updated.

For example: A register value I1MAX(0x40,0x41) of 0000 0001 1111 0100b = 01 F4h = 500d indicates a resulting

maximum sense resistor signal of 500 • 3.8µV = 1.9mV. A register value I1MIN(0x42,0x43) of 1111 1010 0010 0100b

= FA 24h = –1500d indicates a minimum sense resistor signal of –1500 • 3.8µV = –5.7mV. The calculation of the other

tracked parameter values is done the same way with their corresponding LSB values.

Table 31. Tracking Registers

ADDRESS

0x40

0x48

0x42

0x4A

0x44

0x4C

0x46

0x4E

0x50

0x52

0x54

0x56

0x58

0x5A

0x5C

0x5E

0x60

0x62

NAME

TYPE

RW

DEFAULT

0x8000

0x7FFF

0x8000

0x7FFF

0x8000

0x7FFF

0x8000

0x7FFF

0x8000

0x7FFF

0x8000

0x7FFF

0x8000

0x7FFF

PARAMETER

Max I1 Current

LSB

3.8

UNIT

μV

SI/UI

SI

I1MAX[15:0]

I2MAX[15:0]

Max I2 Current

3.8

μV

I1MIN[15:0]

Min I1 Current

3.8

μV

I2MIN[15:0]

Min I2 Current

3.8

μV

2

P1MAX[15:0]

P2MAX[15:0]

P1MIN[15:0]

Max Power 1 (or Battery Voltage for P1ASV=1)

Max Power 2 (or Battery Voltage for P2ASV=1)

Min Power 1 (or Battery Voltage for P1ASV=1)

Min Power 2 (or Battery Voltage for P2ASV=1)

Max Battery Voltage

23.347 (187.5)

375

μ[V ] (µV)

2

μ[V ] (µV)

2

μ[V ] (µV)

2

P2MIN[15:0]

μ[V ] (µV)

BATMAX[15:0]

BATMIN[15:0]

TEMPMAX[15:0]

TEMPMIN[15:0]

VCCMAX[15:0]

VCCMIN[15:0]

SLOT1MAX[15:0]

SLOT1MIN[15:0]

SLOT2MAX[15:0]

SLOT2MIN[15:0]

μV

Min Battery Voltage

375

Max Temperature

0.2

°C

Min Temperature

0.2

°C

Max Voltage at A/DVCC

2.26

mV

Min Voltage at A/DVCC

2.26

mV

Max Voltage (or Temperature) at SLOT1

Min Voltage (or Temperature) at SLOT1

Max Voltage (or Temperature) at SLOT2

Min Voltage (or Temperature) at SLOT2

375 (0.2)

µV (°C)

Note that the tracking registers for current and power report only the 16MSBs of the respective 18-bit result registers, leading to a four times larger LSB

value.

STATUS, (EXT)FAULTS, Threshold and Overflow Alert Registers

The registers described in the following chapters are used to signal certain events, like a voltage threshold violation,

charger or energy overflow, supply undervoltage events and others. After power-up it is recommended to lock the

memory, read STATUS, FAULTS and EXTFAULTS registers, check for the default values, clear them and finally unlock the

memory. During normal operation those registers shall be checked periodically to be all zero, except for the UPDATE

bit. Any other value indicates a failure.

Any bits in the STATUS, alerts (0x81-0x87), FAULTS and EXTFAULTS registers are only set to 1 by LTC2949 in case

of an event, but never cleared automatically. After the master reads some bits being set, actions should be taken (e.g.

to clear the charge register in case of a charge overflow), the memory must be locked (see REGSCTRL), the registers

Rev A

50

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LTC2949

should be read again as other events may have occurred in the meantime, registers that or not 0x00 must be written

to 0x00 and finally the memory must be unlocked to proceed with normal operation.

It is not recommended to write those registers without usage of the memory lock, as this may lead to loss of failure

and alert reports.

Status and Fault Registers

The STATUS register reports the status of register updates, undervoltage lockout, and reference clock errors. On power

up, all undervoltage lockouts and the power-on reset are set to 1. After exit from shutdown, bits UVLOA and UVLOD

are set. UPDATE is set to 1 when the LTC2949 has finished a measurement cycle and updated the result registers, the

accumulation registers, and the tracking registers.

ADCERR is set to 1 if the supply voltage at AVCC is too low for a proper operation of the ADCs. The values in the result

registers are not valid and should be discarded if ADCERR is set. TBERR is set to 1 if the internal time base overflows.

This indicates an incorrect setting of the values PRE and DIV with respect to the external clock at CLKI. The values of

accumulated results registers should be discarded if TBERR is set.

Table 32. STATUS (0x80)

BIT

0

SYMBOL

UVLOA

TYPE

RW

DEFAULT

OPERATION

1

0

1: Undervoltage in the analog domain or ADCs during a conversion

1: Power-on reset has occurred due to undervoltage in the analog domain

1: Undervoltage in the standby domain

1

PORA

2

UVLOSTBY

UVLOD

3

1: Undervoltage in the digital domain

4

UPDATE

ADCERR

TBERR

1: Result registers have been updated

5

1: The ADC conversion is not valid due to undervoltage during a conversion

1: Overflow of the internal timebase register. The values of accumulated result registers are invalid

6

LTC2949 has several types of internal memory that are checked during boot-up via built-in self-test (BIST) routines.

Errors in individual blocks are reported by the EXTFAULTS and FAULTS registers. The FAULTS register additionally

reports error in the internal (on-chip) and external (from master to slave on the SPI/isoSPI interface) communication

and indicates thermal shutdown and fast channel error events.

Table 33. EXTFAULTS (0xDC)

BIT

0

SYMBOL

HD1BITERR

ROMERR

TYPE

RW

DEFAULT

OPERATION

0

1

1: Hamming decoder 1-bit error

1: ROM CRC error

1: Memory error

1

2

MEMERR

3

FCAERR

1: Fast channel error

1: XRAM error

4

XRAMERR

IRAMERR

5

1: IRAM error

7

HWMBISTEXEC

1: Memory BIST was executed. If SDA is externally pulled low during power-up, the memory

BIST will be skipped and this bit will be zero. Connect a 4.7k-10k pull-up resistor from SDA to

BYP1 to ensure correct operation of memory BIST.

Rev A

51

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LTC2949

REGISTER DESCRIPTION

Table 34. FAULTS (0xDD)

BIT

0

SYMBOL

PROMERR

TSD

TYPE

RW

DEFAULT

OPERATION

1: Error in trim values stored in internal PROM

0

1

1: Shutdown due to over temperature

2

INTCOMMERR

EXTCOMMERR

FAERR

1: Parity check of internal communication failed

1: PEC error in external communication (SPI/isoSPI) occurred

1: Fast mode error, see Safety Manual for more information

1: Error during hardware BIST.

3

4

5

HWBIST

6

CRCCFG

1: Internal RAM gain coefficient CRC Error

1: User accessible register CRC Error

7

CRCMEM

Threshold and Overflow Alert Registers

Threshold and overflow alert registers are set when the respective threshold values are exceeded or when registers

overflow. Thresholds are set in the Threshold Registers section.

The accumulated quantities are continuously checked against guard values to warn that a register is nearing overflow,

nominally set to 90% of each register’s maximum value. When any quantity crosses its guard threshold, the LTC2949

sets the corresponding overflow bit in the status register, generates an alert (if enabled) and continues accumulation.

At the maximum voltage inputs, rollover typically happens several hours after an overflow alert is signaled, allowing

the host time to take action to avoid data loss, by reading and clearing the concerned accumulators using the memory

locking procedure. The overflow thresholds for 32-bit quantities (time) are 3865470565 LSB; for 48-bit quantities

(charge and energy) is 126663739519794 LSB.

The threshold and overflow comparators for accumulated quantities charge, energy and time use a floating point

format internally. This can appear to cause slight bit-level comparison discrepancies, but the comparisons between

accumulatedresultregistersandtheirrespectivethresholdregisterswillalwayshaveanaccuracyofbetterthan0.001%.

An alert condition needs to be present for at least for 200ms to be reported by the alert registers (0x81-0x87). Only

overcurrent conditions detected by either OCC1 or OCC2 can be signaled to the host within some µs by stopping heart

beat on GPIO5.

To acknowledge and release an overcurrent alert the following steps can be performed:

1. Stop the overcurrent event

2. Lock the memory

3. Read STATUS-STATVCC, (EXT)FAULTS for any newly arrived error flags (including the asserted OCCx bits)

4. Clear STATUS-STATVCC, (EXT)FAULTS

5. Unlock the memory

6. Heartbeat on GPIO5 will start again

Rev A

52

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LTC2949

REGISTER DESCRIPTION

Table 35. Voltage, Temperature Threshold Alerts STATVT (0x81)

BIT

0

SYMBOL

BATH

TYPE

RW

DEFAULT

OPERATION

1: Voltage (VBATP – VBATM) high threshold exceeded

1: Voltage (VBATP – VBATM) low threshold exceeded

1: Temperature high threshold exceeded

1: Temperature low threshold exceeded

1: SLOT1 high threshold exceeded

0

1

BATL

2

TEMPH

TEMPL

SLOT1H

SLOT1L

SLOT2H

SLOT2L

3

4

5

1: SLOT1 low threshold exceeded

6

1: SLOT2 high threshold exceeded

7

1: SLOT2 low threshold exceeded

Table 36. Current, Power Threshold Alerts STATIP (0x82)

BIT

0

SYMBOL

I1H

TYPE

RW

DEFAULT

OPERATION

0

1: Current1 high threshold exceeded

1: Current1 low threshold exceeded

1: Power1 high threshold exceeded

1: Power1 low threshold exceeded

1: Current2 high threshold exceeded

1: Current2 low threshold exceeded

1: Power2 high threshold exceeded

1: Power2 low threshold exceeded

1

I1L

2

P1H

P1L

I2H

3

4

5

I2L

6

P2H

P2L

7

Table 37. Charge Threshold Alerts STATC (0x83)

BIT

0

SYMBOL

C1H

TYPE

RW

DEFAULT

OPERATION

0

1: Charge1 high threshold exceeded

1: Charge1 low threshold exceeded

1: Charge2 high threshold exceeded

1: Charge2 low threshold exceeded

1: Charge3 high threshold exceeded

1: Charge3 low threshold exceeded

1

C1L

2

C2H

3

C2L

4

C3H

5

C3L

Table 38. Energy Threshold Alerts STATE (0x84)

BIT

0

SYMBOL

E1H

TYPE

RW

DEFAULT

0

1: Energy1 high threshold exceeded

1: Energy1 low threshold exceeded

1: Energy2 high threshold exceeded

1: Energy2 low threshold exceeded

1: Energy4 high threshold exceeded

1: Energy4 low threshold exceeded

1

E1L

2

E2H

3

E2L

6

E4H

7

E4L

Table 39. Charge, Energy Overflow Alerts STATCEOF (0x85)

BIT

0

SYMBOL

C1OVF

C2OVF

C3OVF

E1OVF

E2OVF

E4OVF

TYPE

RW

DEFAULT

0

1: Charge1 overflow alert

1: Charge2 overflow alert

1: Charge3 overflow alert

1: Energy1 overflow alert

1: Energy2 overflow alert

1: Energy4 overflow alert

1

2

4

5

7

Rev A

53

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LTC2949

REGISTER DESCRIPTION

Table 40. Time Base Alerts STATTB (0x86)

BIT

0

SYMBOL

T1TH

TYPE

RW

DEFAULT

OPERATION

0

1: Time1 threshold exceeded

1: Time2 threshold exceeded

1: Time3 threshold exceeded

1: Time4 threshold exceeded

1: Time1 overflow

1

T2TH

2

T3TH

3

T4TH

4

T1OVF

T2OVF

T3OVF

T4OVF

5

1: Time2 overflow

6

1: Time3 overflow

7

1: Time4 overflow

Table 41. VCCOCC Threshold Alerts STATVCC (0x87)

BIT

0

SYMBOL

VCCH

TYPE

RW

DEFAULT

OPERATION

0

1: VCC high threshold exceeded

1: VCC low threshold exceeded

1

VCCL

2

OCC1H

OCC2H

1: Current1 above OCC1 threshold for more than deglitch time

1: Current2 above OCC2 threshold for more than deglitch time

3

Note: The memory must be locked to clear status (0x80), faults (0xDC-0xDD) and alert (0x81-0x87) registers to avoid missing of any failure and alert

reports. See REGSCTRL description for details.

Mask Registers

The mask registers control which alerts stop heartbeat. If a mask register bit is reset to 0, exceeding of the respective

threshold causes the heartbeat on GPIO4 pin to stop, if the latter is configured accordingly in the GPIO4HBCTRL register.

When a bit of the Status Mask Register (STATUSM) is set to 0, the corresponding bits of register STATUS (0x80) will stop

heartbeat. When a bit of the status mask register is set to 1, heartbeat is unaffected by the corresponding bits of register

STATUS (0x80).

Table 42. Status Mask STATUSM (0x88)

BIT

0

SYMBOL

UVLOAM

UVLODM

UPDATEM

ADCERRM

TBCERRM

TYPE

RW

DEFAULT

OPERATION

1

Mask UVLOA of STATUS(0x80)

Mask UVLOD of STATUS(0x80)

Mask UPDATE of STATUS(0x80)

Mask ADCERR of STATUS(0x80)

Mask TBCERR of STATUS(0x80)

3

4

5

6

When bits of STATVTM are set to 0, corresponding bits of register STATVT (0x81) will stop heartbeat. When a bit of

STATVTM is set to 1, heartbeat is unaffected by the corresponding bits of register STATVT (0x81).

Table 43. Voltage, Temperature Threshold Alert Mask STATVTM (0x89)

BIT

0

SYMBOL

BATHM

TYPE

RW

DEFAULT

OPERATION

1

Mask BATH of STATVT(0x81)

Mask BATL of STATVT(0x81)

Mask TEMPH of STATVT(0x81)

Mask TEMPL of STATVT(0x81)

Mask SLOT1H of STATVT(0x81)

Mask SLOT1L of STATVT(0x81)

Mask SLOT2H of STATVT(0x81)

Mask SLOT2L of STATVT(0x81)

1

BATLM

2

TEMPHM

TEMPLM

SLOT1HM

SLOT1LM

SLOT2HM

SLOT2LM

3

4

5

6

7

Rev A

54

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LTC2949

REGISTER DESCRIPTION

When bits from STATIPM are set to 0, bits from register STATIP(0x82) will stop heartbeat. When a bit of STATIPM

register is set to 1, heartbeat is unaffected by the corresponding bits of register STATIP(0x82).

Table 44. Current, Power Threshold Alert Mask STATIPM (0x8A)

BIT

0

SYMBOL

I1HM

TYPE

RW

DEFAULT

OPERATION

1

Mask I1H of STATIP (0x82)

Mask I1L of STATIP (0x82)

Mask P1H of STATIP (0x82)

Mask P1L of STATIP (0x82)

Mask I2H of STATIP (0x82)

Mask I2L of STATIP (0x82)

Mask P2H of STATIP (0x82)

Mask P2L of STATIP (0x82)

1

I1LM

2

P1HM

P1LM

I2HM

3

4

5

I2LM

6

P2HM

P2LM

7

When bits from STATCM are set to 0, bits from register STATC(0x83) will stop heartbeat. When a bit of STATCM register

is set to 1, heartbeat is unaffected by the corresponding bits of register STATC(0x83).

Table 45. Charge Threshold Alerts Mask STATCM (0x8B)

BIT

0

SYMBOL

C1HM

C1LM

C2HM

C2LM

C3HM

C3LM

TYPE

RW

DEFAULT

OPERATION

1

Mask C1H of STATC (0x83)

Mask C1L of STATC (0x83)

Mask C2H of STATC (0x83)

Mask C2L of STATC (0x83)

Mask C3H of STATC (0x83)

Mask C3L of STATC (0x83)

1

2

3

4

5

When bits from STATEM are set to 0, bits from register STATE(0x84) will stop heartbeat. When a bit of STATEM register

is set to 1, heartbeat is unaffected by the corresponding bits of register STATE(0x84).

Table 46. Energy Threshold Alerts Mask STATEM (0x8C)

BIT

0

SYMBOL

E1HM

E1LM

TYPE

RW

DEFAULT

OPERATION

1

Mask E1H of STATE (0x84)

Mask E1L of STATE (0x84)

Mask E2H of STATE (0x84)

Mask E2L of STATE (0x84)

Mask E4H of STATE (0x84)

Mask E4L of STATE (0x84)

1

2

E2HM

E2LM

3

6

E4HM

E4LM

7

When bits from STATCEOFM are set to 0, bits from register STATCEOF(0x85) will stop heartbeat. When a bit of STAT-

CEOFM register is set to 1, heartbeat is unaffected by the corresponding bits of register STATCEOF(0x85).

Table 47. Charge, Energy Overflow Alerts Mask STATCEOFM (0x8D)

BIT

0

SYMBOL

C1OFM

C2OFM

C3OFM

E1OFM

E2OFM

E4OFM

TYPE

RW

DEFAULT

OPERATION

1

Mask C1OVF of STATCEOF(0x85)

Mask C2OVF of STATCEOF(0x85)

Mask C3OVF of STATCEOF(0x85)

Mask E1OVF of STATCEOF(0x85)

Mask E2OVF of STATCEOF(0x85)

Mask E4OVF of STATCEOF(0x85)

1

2

4

5

7

Rev A

55

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LTC2949

REGISTER DESCRIPTION

When bits from STATTBM are set to 0, bits from register STATTB (0x86) will stop heartbeat. When a bit of STATTBM

register is set to 1, heartbeat is unaffected by the corresponding bits of register STATTB (0x86).

Table 48. Time Base Alerts STATTBM (0x8E)

BIT

0

SYMBOL

T1THM

T2THM

T3THM

T4THM

T1OFM

T2OFM

T3OFM

T4OFM

TYPE

RW

DEFAULT

OPERATION

1

Mask T1TH of STATTB(0x86)

Mask T2TH of STATTB(0x86)

Mask T3TH of STATTB(0x86)

Mask T4TH of STATTB(0x86)

Mask T1OVF of STATTB(0x86)

Mask T2OVF of STATTB(0x86)

Mask T3OVF of STATTB(0x86)

Mask T4OVF of STATTB(0x86)

1

2

3

4

5

6

7

When bits from STATVCCM are set to 0, bits from register STATVCC (0x87) will stop heartbeat. When a bit of STATVCCM

register is set to 1, heartbeat is unaffected by the corresponding bits of register STATVCC (0x87).

Table 49. V_CCThreshold Alerts STATVCCM (0x8F)

BIT

0

SYMBOL

VCCH

TYPE

RW

DEFAULT

OPERATION

1

Mask VCCH of STATVCC (0x87)

Mask VCCL of STATVCC (0x87)

1

VCCL

RW

Note that the bits reporting the result of the overcurrent comparators OCC1 and OCC2 in STATVCC (0x87) do not have a

corresponding mask bit in STATVCCM. Therefore the impact of OCC1 and OCC2 on heartbeat either on GPIO4 or GPIO5

cannot be masked. If overcurrent comparison is not desired the enable bit in OCCxCTRL has to be cleared (default).

Control Registers

The control registers select the multiplexer input, control the accumulation of charge, energy and time, configure the

GPIO pins, set the overcurrent comparator thresholds, and setup the timebase if an external clock is used.

The Overcurrent Control Registers allow to set the overcurrent comparator thresholds and deglitch filters, see also the

Overcurrent Comparators section.

Table 50. OCC1CTRL (0xDE)

BIT

0

SYMBOL

OCC1EN

TYPE

RW

DEFAULT

OPERATION

OCC1 enable bit. GPIO5 is configured as heartbeat

0

[3:1]

[5:4]

[7:6]

OCC1DAC [2:0]

OCC1DGLT [1:0]

OCC1POL [1:0]

000

00

OCC1 threshold setting bits, see Table 6 (OCC Thresholds)

OCC1 deglitch time setting bits, see Table 7 (OCC Deglitch Time)

OCC1 polarity setting bits, see Table 5 (OCC Polarity Configuration)

00

Table 51. OCC2CTRL (0xDF)

BIT

0

SYMBOL

OCC2EN

TYPE

RW

DEFAULT

OPERATION

OCC2 enable bit. GPIO5 is configured as heartbeat

0

[3:1]

[5:4]

[7:6]

OCC2DAC [2:0]

OCC2DGLT [1:0]

OCC2POL [1:0]

000

00

OCC2 threshold setting bits, see Table 6 (OCC Thresholds)

OCC2 deglitch time setting bits, see Table 7 (OCC Deglitch Time)

OCC2 polarity setting bits, see Table 5 (OCC Polarity Configuration)

00

Rev A

56

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LTC2949

REGISTER DESCRIPTION

The Accumulator Control and Deadband Registers allow to control the accumulation of Charge1, Energy1, Charge2,

Energy2, Charge3 and Energy4 (C1, E1, C2, E2, C3, E4). Accumulation can be enabled, disabled or conditionally enabled

based on the sign and absolute value of a measured current. C1 contains accumulated I1, C2 contains accumulated I2,

E1 contains accumulated P1 and E2 contains accumulated P2. C3 contains the accumulated sum of I1 and I2 weighted

by the gain setting parameters (see Gain Configuration Registers section) and E4 the accumulated weighted sum of

P1 and P2.

For example, by setting bit 0 of the ACCCTRL1 and bit 1 of ACCCTRL2, C1 contains the accumulation of positive cur-

rents I1 and C3 contains the accumulation of negative currents.

Table 52. Accumulator Control ACCCTRL1(0xE1)

BIT

SYMBOL

TYPE

RW

DEFAULT

OPERATION

[1:0]

[3:2]

ACC1I1[1:0]

ACC2I2[1:0]

00

Accumulation control of Charge1/Charge2 and Energy1/Energy2.

00: Accumulation takes place always,

01: Only if the current is positive,

RW

10: Only if the current is negative,

11: No accumulation takes place.

Table 53. Accumulator Control ACCCTRL2(0xE2)

BIT

SYMBOL

TYPE

RW

DEFAULT

OPERATION

[1:0]

[3:2]

[5:4]

[7:6]

ACC3I1[1:0]

ACC3I2[1:0]

ACC4I1[1:0]

ACC4I2[1:0]

00

Accumulation control of Charge3 and Energy4.

00: Accumulation takes place always,

01: Only if the current is positive,

10: Only if the current is negative,

11: No accumulation takes place.

Small offset voltages in the current measurement path lead to large charge errors after a long integration time. The

accumulator dead band registers allow to set a minimum absolute value of I1 and I2 before being accumulated.

Table 54. Accumulation Dead Band ACCIDB1(0xE4)

BIT

SYMBOL

TYPE

DEFAULT

OPERATION

[7:0]

ACCIDB1

RW

0x0

Current 1 deadband for accumulation. If the absolute value of I1 is higher than or equal this

value, I1 and P1 are accumulated and C1, E1, C3, E4 are updated. A comparison to the respective

thresholds takes place right after an update. If the absolute value of I1 is lower, I1 and P1 are not

accumulated and C1 and E1 are not updated. Unit is the same as LSB of current I1(0x90).

Table 55. Accumulation Dead Band ACCIDB2(0xE5)

BIT

SYMBOL

TYPE

DEFAULT

OPERATION

[7:0]

ACCIDB2

RW

0x0

Current 2 deadband for accumulation .If the absolute value of I2 is higher than or equal this

value, I2 and P2 are accumulated and C2, E2, C3, E4 are updated. A comparison to the respective

thresholds takes place right after an update. If the absolute value of I2 is lower, I2 and P2 are not

accumulated and C2 and E2 are not updated. Unit is the same as LSB of current I2(0x96).

Rev A

57

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LTC2949

REGISTER DESCRIPTION

The Time Base Control Register selects between the internal and an external reference clock, and sets the time base

parameters when an external reference clock is used. Set PRE[2:0] = 111b or 7d (default) to enable the internal refer-

ence clock. To use an external reference clock, set the values of PRE[2:0] and DIV[4:0] according to the external clock

frequency; see the Timebase Control section for more information.

Table 56. Timebase Control TBCTRL (0xE9), DEFAULT VALUE: 0x07

BIT

SYMBOL

TYPE

DEFAULT

OPERATION

[2:0]

PRE [2:0]

RW

111

Prescaler value [2:0],

binary coded,

see Table 2. Parameter PRE with External Clock

[7:3]

DIV [4:0]

RW

00000

Divider value [4:0],

binary coded,

see Table 3

The multiplexer inputs are selected by the Multiplexer Control Registers. For each of the multiplexer outputs MUXP

and MUXN, a 5-bit word selects the connected input.

Table 57. MUX Settings

MUXP/MUXN Setting

Selected Input

Binary [4:0]

11XXX

10111

10110

10101

10100

10011

10010

10001

10000

01111

01110

01101

01100

01011

01010

01001

01000

00111

00110

00101

00100

00011

00010

00001

00000

Dec

31-24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

Reserved

VREF2 via 250k, see Safety Manual for more information

VREF2

Reserved

CF1P

CF1M

CF2P

CF2M

VBATP

VBATM

IPT, see Safety Manual for more information

IMT, see Safety Manual for more information

V12

V11

V10

V9

8

V8

7

V7

6

V6

5

V5

4

V4

3

V3

2

V2

1

V1

0

AGND

Rev A

58

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LTC2949

REGISTER DESCRIPTION

In slow, high precision mode the auxiliary channel (CHAUX) converts in Round Robin mode two differential inputs

signals. For each of the two slots, the inputs multiplexed to MUXP and MUXN can be chosen by programming the

corresponding 5-bit setting in the following four registers.

In fast mode, the auxiliary channel (CHAUX) converts only one differential input signal, which can be chosen by choos-

ing the corresponding 5-bit setting in the Fast MUXP and MUXN Control registers.

During fast continuous measurements it is not possible to change the AUX MUX configuration. See note in chapter

'Fast Measurement Timings'.

Table 58. Multiplexer Control Registers in Slow Mode

ADDR

0xEB

0xEC

0xED

0xEE

BIT

SYMBOL

TYPE

RW

DEFAULT

00000

OPERATION

[4:0]

SLOT1MUXN [4:0]

SLOT1MUXP [4:0]

SLOT2MUXN [4:0]

SLOT2MUXP [4:0]

Slot1 MUXN [4:0] setting, binary coded, see Table 57

Slot1 MUXP [4:0] setting, binary coded, see Table 57

Slot2 MUXN [4:0] setting, binary coded, see Table 57

Slot2 MUXP [4:0] setting, binary coded, see Table 57

Table 59. Multiplexer Control Registers for Fast Mode

ADDR

0xF3

0xF4

BIT

SYMBOL

TYPE

RW

DEFAULT

00000

OPERATION

[4:0]

FAMUXN [4:0]

FAMUXP [4:0]

Fast Mode MUXN [4:0] setting, binary coded, see Table 57

Fast Mode MUXP[4:0] setting, binary coded, see Table 57

RW

00000

The Fast Control Register allows to configure and trigger fast conversions.

There is a timing constraint when writing to FGPIOCTRL and FACTRL, see description for FGPIOCTRL.

Table 60. Fast Control Register FACTRL (0xF5)

BIT

SYMBOL

TYPE

DEFAULT

OPERATION

0

FACONV

RW

0

Continuous fast conversion enable (1) / disable (0).

Conversion results are written to a FIFO if at least one of

bits FACHA, FACH1, FACH2 is set.

1

2

3

FACHA

FACH1

FACH2

RW

0

Channel AUX fast mode configuration bit. Fast conversion

starts within some us after rising edge of FACONV or

when issuing the ADCV command.

Channel 1 fast mode configuration bit. Fast conversion

starts within some us after rising edge of FACONV or

when issuing the ADCV command.

Channel 2 fast mode configuration bit. Fast conversion

starts within some us after rising edge of FACONV or

when issuing the ADCV command.

Rev A

59

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LTC2949

REGISTER DESCRIPTION

The GPIO control registers allow to configure the GPIO pins to be either tristate, low, high or toggling at 400kHz by

setting the corresponding GPIO CTRL bits in 0xF1 and 0xF2.

GPIO4 and GPIO5 can be used as heartbeat pins toggling with a frequency of 400kHz and become static low upon an

alert. While GPIO5 is activated by enabling any of the overcurrent comparators and is dedicated to alerts issued by

these comparators, GPIO4 can be configured by the GPIO4 heartbeat control register (0xE8) to respond on any alert

not masked by the mask registers. The setting in the GPIO4 heartbeat control register overrules the GPIO4CTRL setting

in 0xF2. Similarly GPIO5CTRL setting in 0xF1 is overruled by enabling the overcurrent comparators.

Table 61. GPIO4 Heartbeat Control GPIO4HBCTRL (0xE8)

BIT

SYMBOL

TYPE

DEFAULT

OPERATION

0

GPIO4HBEN

RW

0

GPIO4 heartbeat master enable control

0: GPIO4 is not configured as heart beat.

1: GPIO4 is configured as heart beat and unmasked alerts

(see mask registers) stop heart beat of GPIO4

Table 62. Current Source and GPIO5 Control FCURGPIOCTRL (0xF1)

BIT

SYMBOL

TYPE

DEFAULT

OPERATION

[1:0]

GPIO5CTRL [1:0]

RW

00

GPIO5 CTRL:

[00]=Tristate

[01]=LOW(DGND),

[10]=Toggle at 400kHz

[11] =HIGH(DVCC)

4

5

6

7

MUXPCURPOL

MUXPCUREN

MUXNCURPOL

MUXNCUREN

RW

0

0: MUXP sinks 250µA of current

1: MUXP sources 250µA of current

0: MUXP current source off

1: MUXP current source on

0: MUXN sinks 250µA of current

1: MUXN sources 250µA of current

0: MUXN current source off

1: MUXN current source on

The 250μA current sources at MUXP and MUXN allow open wire detection at all multiplexer inputs. If enabled, the

current sources connect to the inputs during the time the ADC is connected and performs the conversion, no matter

if it is the fast or slow channel. Typically, open wire detection is performed using the fast channel by first writing cur-

rent source, GPIO and MUX control (4-byte write to 0xF1-0xF4), triggering the fast conversion by sending the ADCV,

reading the results with RDCV and finally by writing again 4 bytes to 0xF1-0xF4 to set the next MUX input and current

source configuration. This way, the time when current sources are enabled on a dedicated pin, is precisely timed. See

the safety manual for more information.

Enabled current source on MUXP will alter the internal measurement of VREF (~4V/~0.7V when MUXPCURPOL = 1 /

0) and this change won't be visible on the external VREF pin. If enabled, also the NTC temperature measurement and

the compensation of a shunt resistor's temperature drift will be altered, as they depend on the internal VREF measure-

ment. The correct VREF voltage can always be measured via an external connection to one Vx pin, see also section

Unused Input Pins V1-V12.

Rev A

60

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LTC2949

REGISTER DESCRIPTION

Table 63. GPIO Control FGPIOCTRL (0xF2)

BIT

SYMBOL

TYPE

RW

DEFAULT

OPERATION

[1:0]

[3:2]

[5:4]

[7:6]

GPIO1CTRL [1:0]

GPIO2CTRL [1:0]

GPIO3CTRL [1:0]

GPIO4CTRL [1:0]

00

GPIO1-4 CTRL:

[00]=Tristate

[01]=LOW(DGND),

[10]=Toggle at 400kHz

[11] =HIGH(DVCC)

If set to tristate, the GPIO pins can be used as analog inputs (V8-V12) to the auxiliary channel by choosing the

corresponding multiplexer settings according to Table 57.

Write to register FCURGPIOCTRL does not take effect immediately. Instead any changes will only become active once

FGPIOCTRL is written. Thus it is recommended to always write both registers in a single burst.

Additionally there is a timing constraint when writing to FGPIOCTRL and FACTRL. Writing to those registers must

always be delayed by a minimum of 1ms. Thus, its not allowed to write FGPIOCTRL and FACTRL in a single burst.

Usually this can be easily achieved by partitioning code sections properly that control those registers.

Table 64. RDCV Indirect Address (0xFC)

BIT

SYMBOL

TYPE

DEFAULT

OPERATION

[7:0]

RDCVIADDR

RW

0

Address pointer for indirect memory access via RDCV

command, see section Indirectly Addressed RDCV

Command

The following register is provided for software debug purposes only. It allows synchronization of the host controller

to the CORE system tick. DBGCNT is reset by the CORE after the last register of memory page 0 was updated. This

happens typically 23ms after the end of a slow mode current/power conversion (EOC of I1, I2, P1, P2).

Table 65. DBGCNT (0xD5)

SYMBOL

SI/UI

OPERATION

DBGCNT

UI

Debug counter, counts milliseconds, resets once per core cycle. In MEASURE mode it typically

counts 0 to 100; in STANDBY mode it typically counts 0 to 17.

Rev A

61

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LTC2949

REGISTER DESCRIPTION

REGISTER MAP PAGE1

PAGE1 of the LTC2949 register map contains threshold and configuration registers. The threshold registers allow to set

threshold values for each measured quantity. The configuration registers allow to store application and board specific

parameters and settings, which usually do not need to be modified during operation.

Software Reset

The LTC2949 has a software reset feature, described in following table.

Table 66. RSTUNLCK (p1.0xA9)

SYMBOL

OPERATION

RSTUNLCK

Writing 0x55 to this register will unlock the RESET function within OPCTRL. After putting LTC2949 into SLEEP mode a

writing command to OPCTR with the value 0x80 will issue the reset. Detailed steps to reset LTC2949 are:

1. Write 0 to OPCTRL (0xF0)

2. Write 0x55 to RSTUNLCK (0xA9 on page 1)

3. Wait 130ms

4. Go to SLEEP (set bit SLEEP in OPCTRL)

5. Wait 20ms

6. Write 0x80 to OPCTRL (0xF0)

Threshold Registers

The threshold registers set threshold values for each measured quantity. When a measured value exceeds its threshold,

an alert is triggered and the corresponding bits in the threshold and overflow alert registers (0x81 to 0x87) are set.

When GPIO4 heartbeat is enabled in register GPIO4HBCTRL (0xE8), unmasked alerts in registers (0x88 to 0x8F) stop

heartbeat on GPIO4. Value scaling is done in the same manner as in the corresponding result register values, using

LSB values from Table 26, Table 27 and Table 28. Non-Accumulated Results Register Parameters.

Table 67. Threshold Registers

ADDRESS

p1.0x00

p1.0x06

p1.0x0C

p1.0x10

p1.0x16

p1.0x20

p1.0x26

p1.0x2C

p1.0x30

p1.0x36

p1.0x44

p1.0x4C

p1.0x54

NAME

TYPE

RW

DEFAULT

0x7FFF FFFF FFFF

0x8000 0000 0000

0xFFFF FFFF

0x7FFF FFFF FFFF

0x8000 0000 0000

0x7FFF FFFF FFFF

0x8000 0000 0000

0xFFFF FFFF

0x7FFF FFFF FFFF

0x8000 0000 0000

0x7FFF FFFF FFFF FFFF

0xFFFF FFFF

PARAMETER

C1TH[47:0]

C1TL[47:0]

TB1TH[31:0]

E1TH[47:0]

E1TL[47:0]

C2TH[47:0]

C2TL[47:0]

TB2TH[31:0]

E2TH[47:0]

E2TL[47:0]

C3TH[63:0]

TB3TH[31:0]

C3TL[63:0]

Charge1 threshold high

Charge1 threshold low

Timebase1 threshold high

Energy1 threshold high

Energy1 threshold low

Charge2 threshold high

Timebase2 threshold high

Energy2 threshold high

Energy2 threshold low

Charge3 threshold high

Timebase3 threshold high

Charge3 threshold low

0x8000 0000 0000 0000

Rev A

62

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LTC2949

REGISTER DESCRIPTION

Table 67. Threshold Registers (continued)

ADDRESS

p1.0x64

p1.0x6C

p1.0x74

p1.0x80

p1.0x82

p1.0x84

p1.0x86

p1.0x88

p1.0x8A

p1.0x8C

p1.0x8E

p1.0x90

p1.0x92

p1.0x94

p1.0x96

p1.0x98

p1.0x9A

p1.0xA0

p1.0xA2

p1.0xA4

p1.0xA6

NAME

E4TH[63:0]

TB4TH[31:0]

E4TL[63:0]

I1TH[15:0]

I1TL[15:0]

P1TH[15:0]

P1TL[15:0]

I2TH[15:0]

I2TL[15:0]

TYPE

RW

DEFAULT

0x7FFF FFFF FFFF FFFF

0xFFFF FFFF

0x8000 0000 0000 0000

0x7FFF

PARAMETER

Energy4 threshold high

Timebase4 threshold high

Energy4 threshold low

Current1 threshold high

Current1 threshold low

Power1 threshold high

Power1 threshold low

Current2 threshold high

Current2 threshold low

Power2 threshold high

Power2 threshold low

BAT threshold high

0x8000

0x7FFF

0x8000

0x7FFF

0x8000

0x7FFF

0x8000

0x7FFF

0x8000

0x7FFF

0x8000

0x7FFF

0x8000

0x7FFF

0x8000

0x7FFF

P2TH[15:0]

P2TL[15:0]

BATTH[15:0]

BATTL[15:0]

TEMPTH[15:0]

TEMPTL[15:0]

VCCTH[15:0]

VCCTL[15:0]

SLOT1TH[15:0]

SLOT1TL[15:0]

SLOT2TH[15:0]

SLOT2TL[15:0]

BAT threshold low

Die temperature threshold high

Die temperature threshold low

VCC threshold high

VCC threshold low

Slot1 threshold high

Slot1 threshold low

Slot2 threshold high

0x8000

Slot2 threshold low

FLOAT24 Format

The NTC configuration parameters and the gain correction factors described in the following paragraphs are stored as

floating point numbers represented by the FLOAT24 format according to IEEE 754 standard. The LTC2949 implemen-

tation uses 1-bit for sign, a 7-bit exponent in two’s complement format with 63 as bias and 16-bits for the mantissa,

with an implicit leading bit of value 1 unless the exponent is stored with all zeros. As an example the value of 0.95 is

represented by the 3 bytes number 0x3EE666 as shown below:

Table 68. FLOAT24 Example

3E

E6

66

0

1

0

1

0

1

0

1

0

1

0

Sign

1 x

Exponent

2^(62-63)

Mantissa MSB

Mantissa LSB

x

(1+0.899994)

= 0.5 • 1.899994 = 0.94999

The GUI controlling the LTC2949 demo board supports converting numbers to FLOAT24. The code section of the

LTC2949 (https://www.analog.com/en/products/ltc2949.html#product-tools) also provides conversion functions

++

written in C/C for this purpose.

LTC2949.cpp contains following conversion functions:

void LTC2949_FloatToF24Bytes(float f32, byte* bytes)

void LTC2949_F24BytesToFloat(byte* bytes, float* f32)

Rev A

63

For more information www.analog.com

LTC2949

REGISTER DESCRIPTION

Configuration Registers

The following registers allow to configure LTC2949 application specific. Please note that LTC2949 must be in STANDBY

and an update of these registers must be requested by setting the ADJUPD bit in the Operation Control Register (OPC-

TRL) to make changes effective.

ADC Configuration Register

The ADC Configuration Register allows to disable power multiplication on P1ADC and P2ADC, and to turn on NTC

linearization of Slot1/2 measurements.

Table 69. ADC Configuration ADCCONF (p1.0xDF)

BIT

SYMBOL

TYPE

DEFAULT

OPERATION

0

P1ASV

RW

0

0: P1ADC configured to power mode

1: P1ADC configured to voltage mode

1

3

P2ASV

NTC1

RW

0

0: P2ADC configured to power mode

1: P2ADC configured to voltage mode

0: SLOT1 voltage measurement.

SLOT1 output LSB = 375µV

1: SLOT1 NTC temperature measurement.

SLOT1 output LSB = 0.2˚C

4

6

NTC2

RW

0

0: SLOT2 voltage measurement.

SLOT2 output LSB = 375µV

1: SLOT2 NTC temperature measurement.

SLOT2 output LSB = 0.2˚C

NTCSLOT1

0: TC compensation of shunt for I1 (I2) is linked to temperature measurement via SLOT1 (SLOT2).

1: TC compensation of shunt for I1 and I2 is linked to temperature measurement via SLOT1 only.

See NTC Configuration Registers and section Temperature Measurement for more information regarding NTC tem-

perature measurement.

See Table 28 and Table 31 for effect of P1ASV/P2ASV on LSB sizes or Power-ADC related measurements/settings.

Table 70. Allowed Combinations of FACTRL and ADCVCONF (PxASV) Configurations.

FACONV

0 or 1

FACH1

FACH2

P1ASV

0 or 1

1

P2ASV

0 or 1

1

FAST BAT (b)

SLOW P1

Not Supported!

SLOW P2

1

0

1

0

1

0

1

0 or 1

N/A

P2

N/A

P2

P1

N/A

P2

P1

18-Bit Power or Voltage

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

18-Bit Power

18-Bit Voltage

11-Bit Power (c)

11-Bit Voltage (c)

18-Bit Power (a)

18-Bit Voltage (a)

N/A

1

0

11-Bit Voltage (c)

11-Bit Power (c)

18-Bit Voltage (a)

18-Bit Power (a)

P1

18-Bit Voltage (a)

a) Any fast single shot measurement will interrupt the slow channel measurements. Slow channel will only resume to be updated if there was no fast

single shot measurement for at least 160ms.

b) 15-bit Fast BAT (VBATP-VBATM) voltage measurement via one power ADC. It is always possible to measure VBATP-VBATM via AUX ADC in fast

(FACHA=1) or slow mode.

c) Power ADCs (PxASV=0) of channels configured to fast mode will provide 11-bit conversions at an update rate of 100ms via P1/P2 registers. The LSB

size stays the same, but the resolution in this case is only guaranteed to be 11-bit.

Rev A

64

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LTC2949

REGISTER DESCRIPTION

NTC Configuration Registers

When bits NTC1 and NTC2 in the ADC Configuration Register are set, LTC2949 reports the result of the corresponding

CHAUX slot in temperature by comparing NTC resistance to reference resistors and solving Steinhart-Hart equations.

The NTC Configuration Registers allow to set values of Steinhart-Hart coefficients (A,B,C) and reference resistors.

Furthermore, linear temperature coefficients of up to two external sense resistors can be compensated by thermally

closely coupled NTC thermistors. Temperature compensation is enabled by writing the respective temperature coef-

ficient and its reference temperature (T ) in the NTC Configuration Register. See section Temperature Measurement

0

and Sense Resistor Temperature Compensation for more details.

Table 71. NTC Configuration Registers

ADDRESS

p1.0xAA

p1.0xAD

p1.0xD0

p1.0xD3

p1.0xD6

p1.0xD9

p1.0xDC

p1.0xE0

p1.0xE3

p1.0xE6

p1.0xE9

p1.0xEC

p1.0x5C

p1.0x7C

NAME

TYPE

RW

DEFAULT

0x000000

0x0000

PARAMETER

NTC1 reference resistor

UNIT

Ω

FORMAT

Float24

RREF1[23:0]

RREF2[23:0]

NTC1A[23:0]

NTC1B[23:0]

NTC1C[23:0]

RS1TC[23:0]

RS1T0[16:0]

NTC2A[23:0]

NTC2B[23:0]

NTC2C[23:0]

RS2TC[23:0]

RS2T0[16:0]

RS1TC2[23:0]

RS2TC2[23:0]

NTC2 reference resistor

Ω

NTC1 Coefficient A

NTC1 Coefficient B

NTC1 Coefficient C

Sense resistor 1 (RS1) temperature coefficient (TC)

Reference temperature for TC compensation of RS1

NTC2 Coefficient A

1/K

°C

0x000000

0x0000

NTC2 Coefficient B

NTC2 Coefficient C

Sense resistor 2 (RS2) temperature coefficient (TC)

Reference temperature for TC compensation of RS2

2nd order TC of sense resistor 1

2nd order TC of sense resistor 2

1/K

°C

2

0x000000

1/K

2

1/K

Note that for the two 16-bit registers storing reference temperature RS1T0 and RS2T0 the least significant byte (LSB) of the mantissa is implicitly 0

Gain Configuration Registers

The LTC2949 can store gain correction factors for two current sense resistor, the battery voltage divider and four mul-

tiplexer inputs to compensate tolerances of external components in its Gain Setting Registers located between 0xB0

and 0xCF on measured page 1 of the register map. When these factors are set different than their default value of 1.0,

the LTC2949 corrects the computed values of current, voltage, power, charge and energy accordingly. As the LTC2949

accumulators can be configured to compute the sums of charge and energy flown through two sense resistors, also

the nominal ratio between the two sense resistors RSRATIO = R /R can be stored. The LTC2949 then multiplies the

S1 S2

measurements of CH2 (I2, P2) by RSRATIO before adding them to the sum of charge (C3) or energy (E4). All these

factors are stored in the Float24 format according to IEEE 754 standard described earlier.

Table 72. Gain Configuration Registers

ADDRESS

p1.0xB0

p1.0xB3

p1.0xB6

p1.0xB9

p1.0xC0

p1.0xC3

p1.0xC6

p1.0xC9

NAME

TYPE

RW

DEFAULT

0x3F00 00

PARAMETER

Sense resistor 1(R ) gain correction factor

FORMAT

Float24

RS1GC[23:0]

RS2GC[23:0]

RSRATIO[23:0]

BATGC[23:0]

MUX1GC[23:0]

MUX2GC[23:0]

MUX3GC[23:0]

MUX4GC[23:0]

S1

Sense resistor 2(R ) gain correction factor

S2

Nominal ratio of R to R

S1

S2

BAT gain correction factor

Gain correction factor for MUX setting 1

Gain correction factor for MUX setting 2

Gain correction factor for MUX setting 3

Gain correction factor for MUX setting 4

Rev A

65

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LTC2949

REGISTER DESCRIPTION

Table 72. Gain Configuration Registers (continued)

ADDRESS

p1.0xBC

p1.0xBD

p1.0xBE

p1.0xBF

p1.0xCC

p1.0xCD

p1.0xCE

p1.0xCF

NAME

TYPE

RW

DEFAULT

0x00

PARAMETER

MUXN gain correction setting 1

MUXP gain correction setting 1

MUXN gain correction setting 2

MUXP gain correction setting 2

MUXN gain correction setting 3

MUXP gain correction setting 3

MUXN gain correction setting 4

MUXP gain correction setting 4

FORMAT

MUXNSET1[4:0]

MUXPSET1[4:0]

MUXNSET2[4:0]

MUXPSET2[4:0]

MUXNSET3[4:0]

MUXPSET3[4:0]

MUXNSET4[4:0]

MUXPSET4[4:0]

MUXN binary coded, see Table 57

MUXP binary coded, see Table 57

MUXN binary coded, see Table 57

MUXP binary coded, see Table 57

MUXN binary coded, see Table 57

MUXP binary coded, see Table 57

MUXN binary coded, see Table 57

MUXP binary coded, see Table 57

As an example, if a sense resistor of nominal 100µΩ is used for CH1, but a board calibration reveals the sense resistor

value to be 102µΩ, a factor of 100/102 = 0.9804 should be written to RS1GC [23:0] = float24(0.9804) = 0x3EF5F5.

Assuming a sense resistor of nominal value 10mΩ but real value of 9.8mΩ is used for CH2 the factor 1.024 should be

programmed in RS2GC [23:0] = float24(1.024) = 0x3F0624 and a factor 0.01 should be programmed in RSRATIO[23:0]

= float24(0.01) = 0x3847AE.

In many applications the LTC2949 measures high voltages using external resistor dividers which suffer from gain

errors due to resistor tolerances. The LTC2949 allows to store gain correction factors for the measurement of battery

voltage and four programmable MUX settings. E.g.: The LTC2949 will apply gain correction of 0.9 to differential mea-

surements between V1 and V2 if registers MUX1GC[23:0] = 0x3ECCCC, MUXPSET1[7:0] = 0x01 and MUXNSET1[7:0]

= 0x02, see also Table 57.

The assignment between MUX[1-4]GC and MUX[P,N ]SET[1-4] is independent of the polarity of the MUX settings.

Related to the example above the same gain correction is applied for measurements V1-V2 and V2-V1. Also swap-

ping the register values of MUXPSET1 and MUXNSET1 leads to the same behaviour. The link between gain correction

parameters and measurements is summarized in Table 73.

All Gain Configuration Registers can be copied to an external EEPROM, enabling a modular approach to factory cali-

bration of application boards.

Table 73. Relation Between Gain Correction Parameters and Measurements

NAME

AFFECTED MEASUREMENTS

BATGC

BAT for slow and fast measurements

P1, P2, E1, E2, E4

SLOT[1,2] AUX measurements if SLOT[1,2]MUX[P, N ] is set to VBATP, VBATM of any polarity

Fast AUX conversions if FAMUX[P, N ] is set to VBATP, VBATM of any polarity

Slow and fast AUX measurements if SLOT[1,2]MUX[P, N ] or FAMUX[P, N ] matches MUX[P, N ]SET[1-4] of any polarity

I1, I2, P1, P2, C1, C2, C3, E1, E2, E4

MUX[1-4]GC

RS[1,2]GC

RSRATIO

C3, E4 (Note: The charge that is accumulated to C3 is (I1 + RSRATIO • I2) • dT, the energy that is accumulated to E4 is

(P1 + RSRATIO • P2) • dT.)

Rev A

66

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LTC2949

REGISTER DESCRIPTION

External EEPROM Control Register

To prevent data loss when the LTC2949 is not powered, it can store its entire register content in an external EEPROM

2

via its dedicated I C interface. The communication to an EEPROM is controlled by the EEPROM Control Register

(EEPROMCTRL).

Table 74. EEPROM Control Register EEPROMCTRL (p1.0x50)

BIT

0

SYMBOL

INIT

TYPE

SO

DEFAULT

OPERATION

Write signature to EEPROM

DURATION

40ms

0

1

CHECK

SO

Check the signature in EEPROM

Save MEM (but special row) to EEPROM

Restore EEPROM to MEM (but special row)

Result of INIT

25ms

2

SAVE

SO

1100ms

1250ms

3

RESTORE

INITRSL

CHECKRSL

SAVERSL

RESTORERSL

SO

4

RW

5

Result of CHECK

6

Result of SAVE

7

Result of RESTORE

The lower 4-bits of the EEPROMCTRL are SET ONLY and trigger dedicated communications with the EEPROM, while

the higher 4-bits are read/write and are set by the LTC2949 after the typical time given in the column Duration upon

a successful termination of a communication and must be reset by a write command from the host before the next

communication is requested.

Before any other interaction, the EEPROM must be initialized by setting the INIT bit, which causes LTC2949 to write a

defined signature to the EEPROM. Once the signature is written, LTC2949 will reset the INIT bit and set the INITRSL

2

bit if the EEPROM has acknowledged according to the I C protocol. Any other interaction with the EEPROM will be

preceded by reading and checking this signature – additionally the signature can be checked by setting bit CHECK and

verifying that bit CHECKRSL is set after bit CHECK was reset by LTC2949.

Setting bit SAVE causes the LTC2949 to save its entire memory except the last common row of both register pages

to the EEPROM together with a CRC calculated from the entire register content. LTC2949 signals a successful save

operation by setting bit SAVERSL, based on the check of the signature and the acknowledge of the EEPROM.

Setting bit RESTORE causes the LTC2949 to copy the content of the EEPROM to its internal RAM, calculate the CRC

and set bit RESTORERSL if the CRC was found correct.

Any communication with the external EEPROM requires the LTC2949 to be in STANDBY mode to prevent data loss or

data corruption.

Many applications require to store additional custom data, e.g. serial number. The reserved registers p1.0x1C - p1.0x1F

(4 bytes) and p1.0x3C - p1.0x3F (4 bytes) can be used for that purpose. Additionally, registers of LTC2949 that do not

require a board specific initialization and thus are initialized by the host controller, can be used to store custom data.

For example, all accumulators are either just initialized with zero or via some state-of-charge algorithm. All threshold

values are typically hard coded or initialized by some higher instance in the system. Mux setting registers are adjusted

programmatically. Min/maxtrackingregisterscanbeinitializedbythehostcontroller. TheregistermapshowninFigure18

gives an overview of those registers. Using all of them allows to increase the number of custom data bytes to 240 bytes.

To access this data the host commands an EEPROM RESTORE, reads all registers with custom data and initializes the

registers afterwards to their desired value.

Rev A

67

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LTC2949

REGISTER DESCRIPTION

ꢄꢅꢂꢆ

ꢓꢔꢍꢀ

ꢂꢃ

ꢏꢄꢋꢉꢐꢋꢑAꢀꢄꢂ

ꢒꢉꢙ

ꢇꢈꢉꢄꢊꢋꢊ

ꢒꢉꢇ

ꢒꢕA

ꢖꢗꢕ

ꢀꢁ

ꢌꢌꢍRꢎꢏ

ꢒꢕA

ꢄꢊꢋꢊ ꢘꢄꢀ

Figure 21. EEPROM Connection. Recommended 4k Bit Automotive Qualified EEPROM with Internal EEC:

M24C04-A125 from STMicroelectronics or without Internal EEC: AT24C04C or 24AA04 from Microchip.

APPLICATION INFORMATION

TEMPERATURE MEASUREMENT

The following table shows the relevant registers from the

NTC configuration register for the application shown in

Figure 22.

TheLTC2949shighimpedanceinputsV1-V12canbeused

to measure temperature by means of thermistors and a

reference resistor as shown below.

As VREF is measured with the same ADC as V1-V12,

imperfections of VREF and gain error of the ADC do not

impact the temperature measurement accuracy.

WhenbitsNTC1orNTC2intheADCConfigurationRegister

are set, LTC2949 reports the result of the corresponding

CHAUXslotinslowhighprecisionmodeintemperatureby

comparing the resistance of a thermistor (NTC) R

referenceresistorandsolvingtheSteinhart-Hartequation.

to a

NTC

ꢍRꢇꢎ

R

ꢊꢈꢑ

Rꢇꢎ

1

T

3

ꢀꢁꢂꢃꢄꢅꢄ

= A+B•InR_NTC+C•(InR_NTC

)

ꢍꢊ

ꢆꢁꢂ

ꢆꢁꢂꢀꢇꢃꢈꢉꢇꢉꢊꢈꢉꢋꢌꢈ

The value of the reference resistor R and the Steinhart-

REF

Hart coefficients (A, B, C) need to be stored in the NTC

Configuration Registers. Steinhart-Hart coefficients are

commonly specified parameters provided by thermistor

manufacturers or can be deduced from provided resis-

tance tables.

Aꢏꢆꢐ

ꢃꢄꢅꢄ ꢎꢃꢃ

Figure 22. Connecting Thermistors

Table 75. NTC1 Values in NTC Configuration Register

PARAMETER

NTC1 reference resistor

NTC1 Coefficient A

NTC1 Coefficient B

NTC1 Coefficient C

VALUE

10k

UNIT

ADDRESS

p1.0xAA

p1.0xD0

p1.0xD3

p1.0xD6

NAME

VALUE

FORMAT

Float24

Ω

RREF1[23:0]

NTC1A[23:0]

NTC1B[23:0]

NTC1C[23:0]

0x4C3880

0x352A5F

0x32E7F1

0x279079

1.1382e-3

2.3267e-4

0.93243e-7

Rev A

68

For more information www.analog.com

LTC2949

APPLICATION INFORMATION

SENSE RESISTOR TEMPERATURE COMPENSATION

The following linear equation system has to be solved to

calculateA,B,Cusingthreevalues,R1(T1),R2(T2),R3(T3)

from a R versus T (in K) resistor table:

The LTC2949 can be configured to compensate the tem-

perature dependency of the used current sense resistors

upto2ndorderbasedontemperaturemeasurementswith

external NTCs. The compensation is enabled by writing

thetemperaturecoefficients(TC,TC2)ofthesenseresistor

−1

T₁

1 lnR₁ln³R₁

⎛

⎜

⎞ ⎛

⎟ ⎜

⎞

⎟

⎛ ⎞

A

⎜ ⎟

−1

T₂= 1 lnR₂ln³R₂

B

⎜ ⎟

₋₁⎟ ⎜

⎜ ⎟

and the reference temperature (T ) in the NTC configura-

3

0

C

⎜

⎟ ⎜

⎟

⎝ ⎠

T₃

1 lnR3 ln R₃

⎝

⎠ ⎝

⎠

tion register. The LTC2949 will then compensate for the

temperature induced deviation of the sense resistor from

After solving the linear equation system, A, B, C can be

expressed as:

its nominal value R according to:

0

2

R_SENSE=R •[1+TC •(T−T )+TC2• T−T0 ]

(

)

O

l₁=lnR₁

l₂=lnR₂

l₃=lnR₃

The temperature coefficient and reference temperature

can be set for each sense resistor individually in the NTC

configuration register. Table 76 shows the programmed

coefficientsforacoppersenseresistorwithatemperature

coefficient of 3900ppm/K whose nominal value R was

measured at 20°C.

T₂⁻¹−T₁⁻¹

m₂=

l₂−l₁

0

T₃⁻¹−T₁⁻¹

m₃=

If temperature compensation is enabled for one or both

channels, thesense resistor connected to CH1 is compen-

sated with the temperature of NTC1 measured during the

first slot of CHAUX, while the sense resistor connected to

CH2 is compensated with the temperature of NTC2 mea-

sured during the second slot of CHAUX. The multiplexer

settings must be set such that the input pin connected

to the corresponding NTC is selected during the respec-

tive slot. If CHAUX is changed to fast mode, the last NTC

temperature measurements taken in Round Robin mode

are used for temperature compensation.

l₃−l₁

m₃−m₂

l₃−l₂

l₃+l₂+l₁

C=

B=m₂−C•(l₁²+l₁•l₂+l²₂)

A =T₁⁻¹−(B+l₁²•C)•l₁

Rev A

69

For more information www.analog.com

LTC2949

APPLICATION INFORMATION

For single shunt scenarios the temperature measured by

one NTC with SLOT1 can be used to compensate both

channels. See ADCCONF, bit NTCSLOT1.

setting I to 0.5mA is a good compromise between power

B

consumption and noise immunity. Using this I setting

B

with a 1:1 transformer and R = 100Ω, R should be

M

B1

set to 2.8k and R set to 1.2k. In a typical CAT5 twisted

B2

isoSPI Setup

pair these settings will allow for communication up to

50m. For applications that require cables longer than

The LTC2949 allows the isoSPI link in each application

to be optimized for power consumption or for noise

immunity. The power and noise immunity of an isoSPI

50m it is recommended to increase the I to 1mA. This

B

compensates for the increased insertion loss in the cable

and maintains high noise immunity. So when using cables

over 50m and, again, using a transformer with a 1:1 turns

system is determined by the programmed I current.

B

The I current can range from 100μA to 1mA. A low I

B

ratio and R = 100Ω, R would be 1.4k and R would

M

B1

B2

reduces the isoSPI power consumption in the READY and

ACTIVE states, while a high I increases the amplitude

be 600Ω. Other I settings can be used to reduce power

B

consumption or increase the noise immunity as required

of the differential signal voltage V across the matching

A

by the application. In these cases when setting threshold

termination resistor, R . I is programmed by the sum

M

B

voltage V

and choosing R and R resistor values

B1 B2

ICMP

of the R and R resistors connected between the I

B1

B2

BIAS

the following rules should be used:

pin and GND as shown in Figure 23. For most applications

Table 76. Sense Resistor Temperature Coefficients

PARAMETER

VALUE

0.0039

20

UNIT

1/K

°C

ADDRESS

p1.0xD9

p1.0xDC

NAME

VALUE

FORMAT

Float24

Sense resistor 1 (RS1) temperature coefficient (TC)

Reference temperature for TC compensation of RS1

RS1TC[23:0]

RS1T0[16:0]

0x36FF2E

0x4340

Float24, 2 bytes

Note: For copper only the first order temperature coefficient is relevant and thus TC2=0.0 (default).

Table 77. Procedure to Enable Temperature Compensation of Sense Resistor

WHAT

HOW AND WHERE

CONT= 0 in OPCTRL

ADDRESS

0xF0

Step 1

Step 2

Step 3

Step 4

Step 5

Step 6

Set LTC2949 to Standby Mode

Write NTC and R

DATA

NTC configuration Registers

NTCx = 1 in ADC Configuration Register

Mux Setting Registers

See Table 71.

p1.0xDF

0xEB-0xEE

0xF0

SENSE

Set AUX Slot to Temperature Mode

Select MUX input channel with connected NTC

Update Configuration Registers

ADJUP = 1 in OPCTRL

Set LTC2949 to Continuous Mode

CONT = 1 in OPCTRL

0xF0

ꢁꢄꢎꢋAꢌꢁꢎꢘ ꢃARRꢁꢕR

ꢙꢀAꢚ ꢛꢄꢕ ꢎꢘꢕ ꢎR ꢌꢔꢎ ꢌRAꢘꢉꢎRꢀꢕRꢄꢜ

ꢁꢄꢎꢀꢏ ꢁꢂꢃ

ꢁꢂ

ꢝ

ꢀAꢄꢌꢕR

R

ꢋꢌꢅꢑꢒꢓꢓ

ꢀꢎꢄꢁ ꢁꢀꢃ

ꢀꢁꢄꢎ ꢁꢃꢁAꢄ

ꢄꢅꢐ

ꢋꢌꢅꢆꢇꢈꢇ

ꢀ

ꢄꢏꢎ

ꢄꢏꢁ

ꢄꢅꢐ

ꢀꢁ

ꢁꢀ

ꢁꢃꢁAꢄ

ꢌꢔꢁꢄꢌꢕꢏꢖꢂAꢁR ꢅAꢃꢋꢕ

ꢔꢁꢌꢗ ꢅꢗARAꢅꢌꢕRꢁꢄꢌꢁꢅ ꢁꢀꢂꢕꢏAꢘꢅꢕ R

ꢀ

R

ꢃꢍ

ꢃꢆ

ꢃꢍ

ꢃꢆ

ꢀꢁ

ꢁꢅꢀꢂ

ꢆꢇꢈꢇ ꢉꢆꢊ

Figure 23. isoSPI Circuit

Rev A

70

For more information www.analog.com

LTC2949

APPLICATION INFORMATION

For cables under 50m:

inductances above 60µH and a 1:1 turns ratio. It is also

necessary to use a transformer with less than 2.5µH of

leakage inductance. In terms of pulse shape the primary

inductance will mostly effect the pulse droop of the 50ns

and 150ns pulses. If the primary inductance is too low,

the pulse amplitude will begin to droop and decay over

the pulse period. When the pulse droop is severe enough,

the effective pulse width seen by the receiver will drop

substantially, reducing noise margin. Some droop is ac-

ceptable as long as it is a relatively small percentage of

thetotalpulseamplitude.Theleakageinductanceprimarily

affects the rise and fall times of the pulses. Slower rise

and fall times will effectively reduce the pulse width. Pulse

width is determined by the receiver as the time the signal

is above the threshold set at the ICMP pin. Slow rise and

fall times cut into the timing margins. Generally it is best

to keep pulse edges as fast as possible. When evaluating

transformers, it is also worth noting the parallel winding

capacitance. While transformers have very good CMRR at

lowfrequency,thisrejectionwilldegradeathigherfrequen-

cies, largely due to the winding to winding capacitance.

When choosing a transformer, it is best to pick one with

less parallel winding capacitance when possible.

I = 0.5mA

B

V = (20 • I ) • (R /2)

A

B

M

V

TCMP

V

ICMP

= ½ • V

A

= 2 • V

TCMP

R

B2

R

B1

= V

/I

ICMP B

= (2/I ) – R

B

B2

For cables over 50m:

I = 1mA

B

V = (20 • I ) • (R /2)

A

B

M

V

TCMP

V

ICMP

= 1/4 • V

A

= 2 • V

TCMP

R

B2

R

B1

= V

/I

ICMP B

= (2/I ) – R

B

B2

The maximum data rate of an isoSPI link is determined by

the length of the cable used. For cables 10 meters or less

the maximum 1MHz SPI clock frequency is possible. As

the length of the cable increases the maximum possible

SPI clock rate decreases. This is a result of the increased

propagation delays through the cable creating possible

timingviolations.Figure24showshowthemaximumdata

rate is reduced as the cable length increases when using a

CAT 5 twisted pair. Cable delay affects three timing speci-

fications, t , t and t . In the Electrical Characteristics

ꢌꢑꢒ

ꢀAꢆꢚꢛ Aꢊꢊꢜꢉꢃꢍ

ꢌꢑꢓ

ꢓꢑꢔ

ꢓꢑꢖ

ꢓꢑꢕ

ꢓꢑꢒ

ꢓ

CLK

6

7

table, each is derated by 100ns to allow for 50ns of cable

delay. For longer cables, the minimum timing parameters

may be calculated as shown below:

t , t6 and t7 > 0.9μs + 2 • t

CLK CABLE

ꢌ

ꢌꢓ

ꢌꢓꢓ

ꢀAꢁꢂꢃ ꢂꢃꢄꢅꢆꢇ ꢈꢉꢃꢆꢃRꢊꢋ

Transformer Selection Guide

ꢒꢗꢕꢗ ꢘꢒꢙ

As shown in Figure 23, a transformer or pair of transform-

ers isolates the isoSPI signals between two isoSPI ports.

The isoSPI signals have programmable pulse amplitudes

Figure 24. Data Rate vs Cable Length

up to 1.6V and pulse widths of 50ns and 150ns. To be

P-P

able to transmit these pulses with the necessary fidelity

the system requires that the transformers have primary

Rev A

71

For more information www.analog.com

LTC2949

APPLICATION INFORMATION

When choosing a transformer, it is equally important to

pick a part that has an adequate isolation rating for the

application. The working voltage rating of a transformer

is a key spec when selecting a part for an application. In-

terconnecting daisy-chain links, devices see <60V stress

in typical applications and ordinary pulse and LAN type

transformers will suffice. Multi-drop connections and

connections to the LTC6820, in general, may need much

higherworkingvoltageratingsforgoodlong-termreliabil-

ity. Usually, matching the working voltage to the voltage

of the entire battery stack is conservative. Unfortunately,

transformervendorswilloftenonlyspecifyone-secondHV

testing, and this is not equal to the long-term (permanent)

rating of the part. For example, according to most safety

standards a 1.5kV rated transformer is expected to handle

230V continuously, and a 3kV device is capable of 1100V

long-term, though manufacturers may not always certify

to those levels (refer to actual vendor data for specifics).

Usually, the higher voltage transformers are called high

isolation or reinforced insulation types by the suppliers.

Table 78 shows a list of transformers that have been

evaluated in isoSPI links.

current rejection a common mode choke should also be

placed in series with the IP and IM lines of the LTC2949.

ThecommonmodechokewillbothincreaseEMIimmunity

and reduce EMI emission. When choosing a common

mode choke, the differential mode impedance should be

20Ω or less for signals 50MHz and below. Common mode

chokes similar to what is used in Ethernet applications are

recommended.

Layout of the isoSPI signal lines also plays a significant

role in maximizing the immunity of a circuit. The following

layout guidelines should be followed:

1. The transformer should be placed as close to the isoSPI

cable connector as possible. The distance should be

kept less than 2cm. The LTC2949 should be placed at

least 1cm to 2cm away from the transformer to help

isolate the IC from magnetic field coupling.

2. On the top component layer, no ground plane should

be placed under the transformer, the isoSPI connec-

tor, or in between the transformer and the connector.

3. The isoSPI signal traces should be isolated from sur-

roundingcircuitsandtracesbygroundmetalorspace.

No traces should cross the isoSPI signal lines, unless

separated by a ground plane on an inner layer.

EMC

For the best electromagnetic compatibility (EMC) perfor-

mance, it is recommended to use one of the circuits in

Figure 25 and Figure 26. The center tap of the transformer

should be bypassed with a 10nF capacitor. The center tap

capacitorwillhelpattenuatecommonmodesignals.Large

center tap capacitors greater than 10nF should be avoided

astheywillpreventtheisoSPItransmitterscommonmode

voltage from settling. If a transformer without a center tap

is used, the termination resistor should be split into two

equal halves and connected in series across the IP and IM

lines. The center of the two resistors should be bypassed

with a capacitor as shown. To improve common mode

The isoSPI drive currents are programmable and allow

for a trade-off between power consumption and noise

immunity. The noise immunity of the LTC2949 has been

evaluated using a bulk current injection (BCI) test. The

BCI test injects current into the twisted-pair lines at set

levels over a frequency range of 1MHz to 400MHz. With

the minimum I current, 100μA, the isoSPI serial link was

B

capable of passing a 40mA BCI test with no bit errors. A

40mABCItestlevelissufficientforindustrialapplications.

Automotive applications have a much higher BCI require-

mentsotheLTC2949I issetto1mA,themaximumpower

B

level. The isoSPI system is capable of passing a 200mA

BCI test with no transmitted bit errors. The 200mA test

level is typical for automotive requirements.

Rev A

72

For more information www.analog.com

LTC2949

APPLICATION INFORMATION

Table 78. Recommended Transformers

W

AEC-

Q200

SUPPLIER

PART NUMBER

TEMP RANGE

V

/60S CT CMC

HIPOT

H

L

(W/ LEADS) PINS

WORKING

Recommended Dual Transformers

l

–

l

–

Pulse

Sumida

Wurth

Halo

HX1188FNL

HX0068ANL

–40°C to 85°C

–40°C to 105°C

–40°C to 125°C

60V (est)

1000V

1.5kV

6.0mm 12.7mm

2.1mm 12.7mm

9.7mm

16SMT

10SMT

12SMT

16SMT

12SMT

16SMT

–

RMS

l

–

HM2100NL

4.3kVDC

3.4mm 14.7mm 14.9mm

4.9mm 14.8mm 14.7mm

9mm 17.5mm 15.1mm

l

HM2112ZNL

1000V

CLP178-C20114

CLP0612-C20115

7490140110

–40°C to 125°C 1000V (est) 3.75kV

RMS

600V

250V

3.75kV

4kV

5.7mm 12.7mm

9.4mm

–

RMS

l

–40°C to 85°C

0°C to 70°C

10.9mm 24.6mm 17.0mm

8.4mm 17.1mm 15.2mm

–

RMS

7490140111

1000V (est) 4.5kV

–

RMS

l

749014018

250V

4kV

–

RMS

l

TG110-AE050N5LF

–40°C to 85/125°C 60V (est)

1.5kV

6.4mm 12.7mm

9.5mm

RMS

Recommended Single Transformers

Pulse

Wurth

Halo

PE-68386NL

HM2101NL

–40°C to 130°C

–40°C to 105°C

–40°C to 125°C

–40°C to 105°C

–40°C to 125°C

–40°C to 105°C

60V (est)

1000V

1600V

250V

1.5kVDC

4.3kVDC

–

l

–

2.5mm 6.7mm

5.7mm 7.6mm

8.6mm

9.3mm

15.5mm

9.1mm

6SMT

4SMT

6SMT

6TH

–

l

–

l

HM2113ZNL

3.5mm

9mm

750340848

3kV

5kV

–

2.2mm 4.4mm

RMS

l

–

750317011

800V

7.62mm 9.14mm 12.95mm

–

TGR04-6506V6LF

TGR04-A6506NA6NL

TDR04-A550ALLF

ALT4532V-201-T001

300V

10mm 9.5mm

9.4mm 8.9mm

6.4mm 8.9mm

2.9mm 3.2mm

12.1mm

16.6mm

4.5mm

–

l

–

Halo

300V

Halo

1000V

60V (est)

600V

TDK

~1kV

6SMT

4SMT

8SMT

4SMT

8SMT

Sumida

TDK

CEEH96BNP-LTC6804/11 –40°C to 125°C

2.5kV

7mm

9.2mm

12.0mm

9.1mm

RMS

l

CEP99NP-LTC6804

ESMIT-4180/A

–40°C to 125°C

–40°C to 105°C

–40°C to 125°C

600V

10mm 9.2mm

3.5mm 5.2mm

–

l

250V

3kV

–

RMS

l

VGT10/9EE-204S2P4

250V (est)

2.8kV

10.6mm 10.4mm 12.7mm

–

RMS

COMMON

MODE

CHOKE

TRANSFORMER WITH

COMMON MODE CHOKE

IP

LTC2949

IM

51Ω

10nF

IP

LTC2949

IM

100Ω

2949 F26

Figure 26. Recommended isoSPI Circuit for Best EMC

Performance when Using a Transformer without Center Tap

10nF

2949 F25

Figure 25. Recommended isoSPI Circuit for EMC

Table 79. Recommended Common Mode Chokes

MANUFACTURER

TDK

PART NUMBER

ACT45B-220-2P

DLW43SH510XK2

744232102

Murata

Wurth

Rev A

73

For more information www.analog.com

LTC2949

APPLICATION INFORMATION

R

ꢎꢉ

c. VREF can be used to bias resistive dividers to al-

low measurement of voltages below GND. In those

scenarios the differential voltage between Vx and

VREF must be measured which is only possible if

VREF is connected to one of V1-V12 pins.

ꢉꢏꢏꢐ

ꢉꢐ

ꢏꢑꢉꢐ

Aꢋꢌꢍ ꢂꢆꢉꢔ ꢈꢉꢔ

2. Connect divided supply voltage AVCC/DVCC (e.g. 10k

betweenGND/Vxand20kbetweenVxandAVCC/DVCC)

to one of V1-V12

ꢈꢉꢊ ꢂꢆꢉꢊ

ꢕꢖAꢁꢊ

ꢀꢁꢂꢃꢄꢅꢄ

ꢖAꢁꢁ

ꢉꢏꢓ

ꢉꢔ

ꢅꢑꢇꢒ

a. Same as 1.a. Register VCC is not updated while

performing fast AUX conversions.

ꢕꢖAꢁꢔ

3. Connect NTC to one of V1-V12

ꢃꢄꢅꢄ ꢆꢃꢇ

a. See section Temperature Measurement

Figure 27. Input Filtering

4. Connect pin VREF via an external 4k resistor to one of

V1-V12

CURRENT AND VOLTAGE INPUT FILTERING

To ensure the full electrical performance of the ADCs for

current, power and voltage, apply the input filtering cir-

cuitry as depicted in Figure 27 to pins CFP, CFM, VBATP

andVBATM.Thesecomponentsensureanoptimizedinput

filteringfornoisereduction.Equaltimeconstantsatcurrent

andvoltageinputsminimizeerrorsinpowermeasurement

of transient signals due to different delays in both paths.

a. Allows to diagnose the internal current sources.

5. Connect pins BYP1 and BYP2 to separate unused pins

of V1-V12.

a. Allows to diagnose internal generated supply volt-

ages additionally to built-in self-tests.

High-Ohmic Resistive Dividers

Unused Input Pins V1-V12

Any high voltage to be measured by LTC2949 must be

divided down and optionally biased via VREF to move it

into the LTC2949’s supply voltage rails 100mV and into

theADC’sdifferentialinputvoltagerange( 4.8V).Typically,

several resistors are connected in series, to minimize the

voltage drop and power dissipation of individual resistors

(Figure 28). LTC2949 Operation State Diagram shows a

typical schematic, as an example the signal is measured

via V1 by the AUX ADC. The measurement is performed

similarly via the BAT inputs (VBATP, VBATM) by the AUX

or the Power ADCs (P1/P2 as voltage).

InputpinsV1-V12canbeleftfloatingorconnectedtoGND

if not used. Still, itis notrecommendedtoconnectV8-V12

to GND as those pins can be driven high optionally when

used as digital outputs.

Depending on the application and the configuration of

LTC2949, it might be beneficial or sometimes even nec-

essary to apply following external connections to inputs,

which were unused.

1. Connect pin VREF to one of V1-V12

a. SeelastparagraphofsectionFastModeConfigura-

tionsforeffectoffastAUXmeasurementoninternal

slow AUX Round-Robin. Register VREF is not

updated while performing fast AUX conversions.

AllvoltageinputsofLTC2949arebuffered. Thedifferential

input impedance during measurements is guaranteed to

be>50Meg. Fortypicalresistivedividers, likethoseshown

in the typical application, the effect of this equivalent

>50Meg resistor is negligible. The error can be calculated

as following:

b. The internal VREF measurement is altered while the

current sources (see register FCURGPIOCTRL) are

enabled. Connecting VREF to one Vx pin always mea-

surement of the correct VREF pin voltage at any time.

Nominal gain factor: g = R /(R +R

)

low

low high

Rev A

74

For more information www.analog.com

LTC2949

APPLICATION INFORMATION

Effective low side resistor: R

= R • R /

optional external EEPROM can be used as a nonvolatile

storage for those calibration factors.

lowd

low

d

(R +R ), R = 50e5

low

d

Effective gain factor: g = R

/(R +R )

lowd high

LTC2949’s gain correction registers are not limited to

values around 1.0, for example it is possible to write a

value of 10.0 and this factor would be applied just as any

other. Still, there is a limitation by the size of the result

registerswhichis16-bit(includingsign)foranyAUX-ADC

measurementlikeBAT,SLOT1/2andthefastAUXmeasure-

ment results. This leads to an absolute maximum register

d

lowd

3

Example values: R =30 , R =5 • 1.3e6

low

high

Gain factor error: err = g /g–1 = –0.06%

d

The differential input impedance during measurements

is nonlinear, it increases with decreasing input signal and

it may also change over temperature. For this reason, it

can be calibrated only partially during a post-production

board test procedure. Still, its guaranteed to be >50Meg

over the full-scale input range and the whole operating

temperature range and thus the error calculated above

gives the worst-case error.

15

valueofroughly12.3V(375µV•[2 -1]).Toavoidclipping

or overflowing of the results, it is always recommended

to use gain correction factors that correct the deviation

fromnominalfactors(e.g.deviationfromnominalresistor

dividerratio)likeintheexampleabove. Thehostcontroller

software then holds the hard-coded nominal factor (e.g.

6.53Meg/30k)andLTC2949isapplyingthefine-trimbased

on the values that were stored into the external EEPROM

during board calibration.

The high voltage is calculated from the ADC measurement

the following way:

Divider connected to GND: V

= V /g

ADC

HVa

Divider connected to VREF: V

= V /g+VREF

ADC

HVb

POWERING THE LTC2949

As any resistive divider is affected by static tolerances, it

can be calibrated by applying a known input signal and

calculating greal from the ADC measurement. LTC2949

can compensate for this error by writing the gain correc-

tion factor GC=gnominal/greal to one of the related gain

correction registers (BATGC, MUX1GC-MUX4GC). The

The LTC2949 requires a single supply voltage of 4.5 to

14V. The maximum supply current is 20mA when active

and 120µA when sleeping. If isoSPI is selected up to 7mA

are required additionally during communication. Any cur-

rent that is necessary to drive circuits connected to the

GPIO pins must also be considered when selecting and

designing a suitable power supply.

R

ꢁꢂꢁ

ꢂ ꢃꢄꢅꢆꢇ

ꢃ ꢄꢅꢆꢇꢈ

ꢀꢁꢀ

ꢀ

R

ꢀꢁꢂꢃ

ꢀ

ꢀꢁꢁꢂ

R

ꢀ

R

ꢀꢁꢂꢀ

ꢃ ꢄꢅRꢀ

ꢀꢁꢂꢃ

R

ꢀ

R

ꢀꢁꢂꢃ

ꢀꢁ

ꢀꢁꢂꢀ

Aꢀꢁꢂꢃꢃ

ꢀꢁꢂꢃꢄꢅꢄ

R ꢁ ꢂꢃꢄ

ꢀ

ꢀꢁ ꢂꢃꢃꢄ

ꢀꢁ ꢂꢃꢄꢅ

R

ꢀ

ꢀꢁ

ꢀꢁꢂꢃ

ꢀꢁꢂ

R

ꢀꢁꢂ

ꢀꢁꢂꢃꢄꢅꢄ

ꢁ ꢂꢃꢄ

ꢀꢁꢂꢃ

R

ꢀ

ꢀꢁꢂꢃ

ꢀꢁꢂ

ꢀꢁꢁꢁꢂ

ꢀRꢁꢂ

R

ꢀ

ꢀꢁ

R

ꢀꢁꢂ

ꢀꢁ

ꢀꢁꢂꢃ

ꢀꢁꢂ

ꢀꢁꢂꢃ

Aꢀꢁꢂꢃꢁ

ꢀꢁꢂꢁ ꢃꢀꢄ

Figure 28. Left: High-Ohmic Resistive Divider for Measuring 1000V Battery Voltage Via the AUX ADC Input V1.

Right: Resistive Divider Connected to VREF Allows to Measure 1000V.

Rev A

75

For more information www.analog.com

LTC2949

APPLICATION INFORMATION

Non-Isolated Supply

PART

POWER

SWITCH

NUMBER

V

RANGE

MAX. P

2W

PACKAGE

SOT23-5

SO-8E

IN

OUT

LTC provides a broad spectrum of non-isolated power

supply solutions including LDOs, switched mode power

suppliesandμModuleregulators.AstheLTC2949ismainly

targetinghighvoltagebatteryapplicationstheLT8315can

be considered. Using the LT8315 it is possible to supply

the LTC2949 directly out of a high voltage battery of up

to 560V as shown in Figure 29.

LT8300

LT8303

6V to 100V 0.26A/150V

5.5V to 100V 0.45A/150V

5W

LT8301

2.7V to 42V

2.8V to 42V

3V to 100V

1.2A/65V

3.6A/65V

2A/150V

6W

LT8302

18W

24W

LT8304/-1

SO-8E

Minimum load requirement of the flyback converters

must be considered which is typically much higher than

the sleep current of the LTC2949. To prevent the output

voltage from rising above LTC2949’s operating ratings

a 12V Zener diode (e.g. NXP: BZX384-B12,115) should

be placed.

Isolated supply

MosthighvoltagebatteryapplicationswheretheLTC2949

cannot be supplied directly out of the battery require an

isolatedpowersupply.AsimpleDC/DCconverterisshown

in Figure 30 using Linear Technology’s LT3999 DC/DC

converter and a high isolation-rated transformer.

Transformer specification and design is possibly the most

critical part of successfully applying the above mentioned

DC/DC converters. Data sheets of the suggested parts

give detailed information about critical parameters like

saturation current, inductance, isolation voltage rating

and creepage distance.

The LT830X family of flyback converters with a suitable

transformer is also a possible choice.

ꢀ

ꢀꢁ

ꢀꢁꢂ ꢃꢄ ꢅꢆꢁꢂ

ꢀꢁꢂ ꢃꢄꢅꢆRAꢇ ꢃꢈꢀꢉꢊꢋꢌꢍ

ꢀꢁꢂ ꢀꢃꢄ ꢅꢆꢇꢈRAꢉ ꢅꢊꢊRꢋꢌꢍꢎꢏ

ꢀꢁꢂ ꢃꢄꢅRꢆ ꢅꢆꢃꢃꢇRꢅꢄAꢈ ꢉꢃꢊꢋꢌꢍꢌꢎꢊꢏꢐꢑ

ꢀꢁꢂꢂꢃ

ꢀꢁꢂꢃ

ꢀꢁ

ꢀꢁAꢂ

ꢀꢁꢂ

ꢀꢁ

ꢀꢀꢁ

ꢀꢁꢂꢃꢄꢅꢆ

ꢀꢁ

ꢀꢁꢂꢃ

ꢀꢀ

ꢀꢁ

ꢀꢁꢂꢃꢄꢅ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄ

ꢀRAꢁꢂ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂꢃ

ꢀ

ꢀꢁꢂRꢃꢄ

ꢀꢀꢁꢂꢃ

ꢀRꢁꢂꢃꢄꢄ

ꢀꢁꢂ

330mΩ

ꢀꢁꢁꢂꢃ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂ

ꢀꢁA ꢂꢃ ꢄꢅꢆꢁA

ꢀꢀꢁꢂ

ꢀꢁ

ꢀꢁꢂꢁ ꢃꢀꢁ

Figure 29. Nonisolated Supply Generation

Rev A

76

For more information www.analog.com

LTC2949

APPLICATION INFORMATION

ꢠ

ꢀ

ꢁꢂ

ꢞꢀ

ꢜ

ꢖꢛꢁ

ꢇꢅ

ꢀꢅ

ꢅꢆꢅ

ꢘꢜ

ꢈ

ꢢꢥꢑꢒ

ꢏꢐꢀ

ꢜ

ꢁꢂ

ꢗꢎ

ꢔꢝꢞꢜ ꢁꢖ ꢅꢟꢜ

ꢅꢡA ꢁꢖ ꢔꢄꢄꢡA ꢢꢜ ꢣ ꢃꢝꢃꢜꢤ

ꢀ

ꢗꢎ

ꢊꢏ

ꢁꢂ

ꢀ

ꢅꢃꢋ

ꢋꢏ

ꢅꢡA ꢁꢖ ꢃꢄꢄꢡA ꢢꢜ ꢣ ꢘꢜꢤ

ꢗꢎ

ꢅꢄꢌꢈ

ꢨ

ꢞꢀ

ꢃꢀꢄꢅ

ꢆꢎA

ꢅꢡA ꢁꢖ ꢥꢘꢄꢡA ꢢꢜ ꢣ ꢅꢔꢜꢤ

ꢗꢎ

ꢟ

ꢅꢄꢌꢍ

ꢘꢅꢝꢅꢧ

ꢅꢄꢌꢍ

ꢈ

ꢏꢐꢑꢒ

ꢏꢐꢀ

ꢜ

ꢐꢘꢝA

ꢅꢃꢋ

ꢗꢎ

ꢒꢎꢚꢛꢜꢀꢖ

ꢀꢁꢂꢃꢄꢅ

ꢆꢇꢂꢈ

ꢨ

ꢥꢞꢌꢈ

ꢅꢀꢄꢅꢉꢊꢈ

ꢊꢋ

ꢦ

ꢄꢋꢌꢍꢍꢍ

ꢜ

ꢖꢛꢁ

Rꢊꢈ

ꢊꢔ

R

ꢇꢅꢆ ꢎꢏꢐ ꢐꢑꢒꢓꢃꢄꢔꢄꢒꢍ

ꢀꢅꢆ ꢕꢖꢗꢀꢕRAꢈꢁ ꢀꢐꢇꢘꢄꢃꢄꢙꢅꢄꢃꢑꢒꢉ

ꢈꢉ

Rꢋ

ꢆꢎꢠ

ꢓꢎꢇ

ꢁꢄꢁꢗꢉꢆꢆ

RꢠꢁAꢆ

ꢔꢩꢥꢩ ꢈꢃꢅ

ꢊꢏꢓ ꢊꢔꢕ ꢈꢖꢂꢋRAꢄ ꢆꢖꢗꢁꢘ ꢈꢗꢆꢙꢏꢚꢔꢐꢗ

ꢋꢏꢕ ꢈꢅꢁꢄꢈRAꢒꢋ ꢛAꢜꢌꢝꢌ

R

ꢏꢔꢘꢏꢣ

ꢏꢗꢙꢤ

ꢋ

ꢡꢂꢊ

R

ꢠꢁAꢆ

ꢢꢍꢘꢍꢣ

ꢔꢍꢢꢍ ꢒꢌꢐ

Figure 31. Isolated Supply Generation with Flyback Converter

Figure 30. Isolated Supply Generation with Push-Pull

Transformer

R

ꢀꢁꢂꢀꢁꢃ

ꢀꢁꢂ ꢃꢄRRꢅꢆꢇ ꢈAꢇꢉ ꢊAꢃꢋ ꢉꢅAꢇꢅRꢋ ꢌꢃꢍꢌꢃ ꢎꢏꢐ ꢅꢇꢃꢑꢒ

ꢀꢁꢂ

R

ꢀꢁꢂꢀꢁꢃ

ꢀꢁꢂꢀ ꢃꢄRRꢅꢆꢇ ꢈAꢇꢀ ꢉꢊꢋꢇꢋR ꢅꢇꢃꢌꢍ

ꢀꢁꢁꢂ

R

ꢀRꢁꢂꢃ

ꢀꢁꢂ

Aꢀꢁꢂꢂ

Aꢀꢁꢁ

ꢀꢁꢂ

ꢀꢁ

ꢀꢁꢂꢂ

ꢀꢁꢂꢃꢄꢅ

ꢀꢁꢂ

ꢀꢁ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄꢅꢆꢇ

ꢀꢁAꢂꢃ

ꢀꢁꢂ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁAꢂꢃ

ꢀꢁ

ꢀꢁꢂꢃꢄꢅꢆꢇ

ꢀꢁꢂꢃꢄꢅꢄ

ꢀꢁ

ꢀꢁꢂꢃ

Aꢀꢁꢂꢂ

ꢀꢁꢂꢃ

ꢀꢁ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈ

ꢀꢁꢂꢀꢃ

ꢀꢁ

ꢀAꢁꢁꢂRꢃ

ꢀꢁꢁꢂꢀꢁꢃꢄꢅꢆꢇꢈꢉꢂꢊ

ꢀꢁꢁ

ꢀꢁꢂꢃꢄꢅ

ꢀꢁ

ꢀꢁꢂ

ꢀRꢁꢂ

ꢀꢁꢁ

ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄꢅꢆ

ꢀꢁ

ꢀꢁꢂꢃꢄꢅ

ꢀꢁ

ꢀꢁꢀAꢂ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄꢅꢄAꢀ

ꢀꢁ

ꢀꢁꢂꢃꢄꢅꢆꢇ

ꢀꢁꢂꢃꢃ

ꢀꢁꢂꢃ

ꢀꢁꢂ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁꢂꢁ ꢃꢄꢀ

Figure 32. Battery Monitoring with High Side Current Sensing Over Two Sense Resistors, Battery Voltage Measurement, Temperature

Measurement and Pre-Charge Voltage Measurement Using Isolated Supply and Isolated NMOS Gate Drive as Well as PhotoMos Relay.

Rev A

77

For more information www.analog.com

LTC2949

PACKAGE DESCRIPTION

LXE Package

48-Lead Plastic Exposed Pad LQFP (7mm × 7mm)

ꢅReꢪeꢫeꢬꢭe ꢀꢞꢙ ꢠꢥꢚ ꢮꢊꢓꢨꢊꢄꢨꢌꢖꢗꢑ Rev ꢎꢆ

Exposed Pad Variation AA

ꢖꢒꢊꢊ ꢎꢘꢙ

ꢑꢒꢊꢊ ꢎꢘꢙ

ꢃꢒꢌꢓ ꢊꢒꢗꢊ

ꢃꢄ

ꢋꢑ

ꢃꢄ

ꢘꢂꢂ ꢜꢝꢞꢂꢟ ꢋ

ꢌ

ꢋꢔ

ꢌ

ꢖꢒꢊꢊ ꢎꢘꢙ

ꢑꢒꢊꢊ ꢎꢘꢙ

ꢃꢒꢌꢓ ꢊꢒꢗꢊ

A

ꢗꢓ

ꢌꢗ

ꢗꢓ

ꢙꢊꢒꢋꢊ ꢐ ꢊꢒꢓꢊ

ꢗꢃ

ꢌꢋ

ꢗꢃ

ꢎꢝꢞꢞꢝꢕ ꢝꢈ ꢉAꢙꢢAꢚꢂꢩꢂꢁꢉꢝꢘꢂꢠ ꢉAꢠ ꢅꢘꢣAꢠꢂꢠ ARꢂAꢆ

ꢌꢒꢔꢊ

ꢌꢌꢏ ꢐ ꢌꢋꢏ

ꢌꢒꢋꢓ ꢐ ꢌꢒꢃꢓ ꢕAꢁ

Rꢊꢒꢊꢄ ꢐ ꢊꢒꢗꢊ

ꢚAꢛꢚꢂ ꢉꢀAꢜꢂ

ꢊꢒꢗꢓ

ꢊꢏ ꢐ ꢑꢏ

ꢀꢁꢂꢃꢄ ꢅAAꢆ ꢀꢇꢈꢉ ꢊꢋꢌꢄ Rꢂꢍ ꢎ

ꢌꢌꢏ ꢐ ꢌꢋꢏ

ꢌꢒꢊꢊ Rꢂꢈ

ꢊꢒꢓꢊ

ꢎꢘꢙ

ꢊꢒꢊꢖ ꢐ ꢊꢒꢗꢊ

ꢊꢒꢌꢑ ꢐ ꢊꢒꢗꢑ

ꢘꢡꢠꢂ ꢍꢡꢂꢥ

ꢊꢒꢊꢓ ꢐ ꢊꢒꢌꢓ

ꢊꢒꢃꢓ ꢐ ꢊꢒꢑꢓ

ꢘꢂꢙꢞꢡꢝꢜ A ꢐ A

ꢜꢝꢞꢂꢟ

ꢌꢒ ꢠꢡꢕꢂꢜꢘꢡꢝꢜꢘ ARꢂ ꢡꢜ ꢕꢡꢀꢀꢡꢕꢂꢞꢂRꢘ

ꢗꢒ ꢠꢡꢕꢂꢜꢘꢡꢝꢜꢘ ꢝꢈ ꢉAꢙꢢAꢚꢂ ꢠꢝ ꢜꢝꢞ ꢡꢜꢙꢀꢛꢠꢂ ꢕꢝꢀꢠ ꢈꢀAꢘꢣꢒ ꢕꢝꢀꢠ ꢈꢀAꢘꢣ

ꢘꢣAꢀꢀ ꢜꢝꢞ ꢂꢁꢙꢂꢂꢠ ꢊꢒꢗꢓꢤꢤ ꢅꢌꢊ ꢕꢡꢀꢘꢆ ꢎꢂꢞꢥꢂꢂꢜ ꢞꢣꢂ ꢀꢂAꢠꢘ Aꢜꢠ ꢝꢜ Aꢜꢦ

ꢘꢡꢠꢂ ꢝꢈ ꢂꢁꢉꢝꢘꢂꢠ ꢉAꢠꢧ ꢕAꢁ ꢊꢒꢓꢊꢤꢤ ꢅꢗꢊ ꢕꢡꢀꢘꢆ Aꢞ ꢙꢝRꢜꢂR ꢝꢈ ꢂꢁꢉꢝꢘꢂꢠ

ꢉAꢠꢧ ꢡꢈ ꢉRꢂꢘꢂꢜꢞ

ꢋꢒ ꢉꢡꢜꢨꢌ ꢡꢜꢠꢂꢜꢞꢡꢈꢡꢂR ꢡꢘ A ꢕꢝꢀꢠꢂꢠ ꢡꢜꢠꢂꢜꢞAꢞꢡꢝꢜ

ꢃꢒ ꢠRAꢥꢡꢜꢚ ꢡꢘ ꢜꢝꢞ ꢞꢝ ꢘꢙAꢀꢂ

ꢑꢒꢌꢓ ꢐ ꢑꢒꢗꢓ

ꢓꢒꢓꢊ Rꢂꢈ

ꢃꢄ

ꢋꢑ

ꢋꢔ

ꢌ

ꢊꢒꢓꢊ ꢎꢘꢙ

ꢓꢒꢓꢊ Rꢂꢈ

ꢑꢒꢌꢓ ꢐ ꢑꢒꢗꢓ

ꢊꢒꢗꢊ ꢐ ꢊꢒꢋꢊ

ꢃꢒꢌꢓ ꢊꢒꢊꢓ

ꢌꢗ

ꢌꢋ

ꢗꢓ

ꢉAꢙꢢAꢚꢂ ꢝꢛꢞꢀꢡꢜꢂ

ꢗꢃ

ꢙꢝꢕꢉꢝꢜꢂꢜꢞ

ꢉꢡꢜ ꢯAꢌꢰ

ꢌꢒꢋꢊ ꢕꢡꢜ

ꢞRAꢦ ꢉꢡꢜ ꢌ

ꢎꢂꢍꢂꢀ

Rꢂꢙꢝꢕꢕꢂꢜꢠꢂꢠ ꢘꢝꢀꢠꢂR ꢉAꢠ ꢀAꢦꢝꢛꢞ

Aꢉꢉꢀꢦ ꢘꢝꢀꢠꢂR ꢕAꢘꢢ ꢞꢝ ARꢂAꢘ ꢞꢣAꢞ ARꢂ ꢜꢝꢞ ꢘꢝꢀꢠꢂRꢂꢠ

ꢉAꢙꢢAꢚꢂ ꢡꢜ ꢞRAꢦ ꢀꢝAꢠꢡꢜꢚ ꢝRꢡꢂꢜꢞAꢞꢡꢝꢜ

Rev A

78

For more information www.analog.com

LTC2949

REVISION HISTORY

REV

DATE

11/20 Changed GPOx to GPIOx.

Moved Temperature Measurement into sub-section Application Information.

Adapted Abs Max of SDO.

Changed TYP value of V

DESCRIPTION

PAGE NUMBER

A

Throughout

2

3

in EC-table.

4

BYP2

Changed Input Leakage current for CFPx from 40nA to 60nA.

4

Adapted I Average Supply Current in EC table and in text Modes of Operation.

4,15

5

CC

Changed Input Leakage current for Voltage Measurement by Power ADC from 10nA to 60nA.

Symbol names corrections in EC table.

6

Changed Input Leakage current for Voltage Measurement by AUXILIARY ADC from 10nA to 60nA.

EC-Table External Clock Frequency adapted MIN value.

6

7

Adapted t

MAX value.

8

lDLE

Adapted V Transmitter Pulse Amplitude MAX value.

8

A

Corrected symbol A

Corrected symbol V

in V

.

8

TCMP

ICMP

in A

wrong.

8

ICM

TCMP

Corrected Pin 6 missing in list of DNC-pins.

Core states vs fast conversions: Update of Figure 1.

Corrected wrong Figure 29.

12

15

16

20

21

41

48

65, 66

66

74

77, 80

Corrected wrong minimum frequency of 200kHz.

Corrected missing unit at first column of Table 3.

ISORPT still in register map table: Removed.

Register name typos: Corrected Register Map.

ADC limit behavior: Added sentence after Table 28.

Register name typos: Corrected Tables 71 and 72.

Adapted Description of MUX[1-4]GC in Table 73.

Corrected Wrong Figure 1.

MOSFET polarities: Update of several transistor symbols.

Rev A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications

79

subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

For more information www.analog.com

LTC2949

TYPICAL APPLICATION

Battery Metering with Low-Side Current & Charge Sensing, Battery Voltage Measurement,

Temperature Measurement, Contactor Supervision and Isolated Gate Drive of Pre-Charge FET.

ꢀ

ꢂ

ꢃAꢄ

ꢛꢞAꢖ ꢞR ꢜꢠARꢑꢗR

RꢒRꢗꢜꢠ ꢊꢄꢃꢋꢌꢍꢎꢈꢏ

ꢊꢄꢃꢋꢌꢍꢎꢈꢏ

ꢅꢆ

ꢇꢧ

ꢅꢈꢉ

ꢇꢈꢧ

ꢁ

ꢅꢆ

ꢊꢄꢃꢋꢌꢍꢎꢈꢏ

ꢂꢎꢐꢑꢒꢈꢇ

ꢂꢃAꢄꢒ

ꢂꢋꢐꢑꢒꢈꢅ

ꢂ

ꢃAꢄ

ꢂꢇꢈꢐꢑꢒꢈꢓ

ꢂꢅ

ꢇꢈꢉ

ꢊꢄꢃꢋꢌꢍꢎꢈꢏ

ꢂꢃAꢄꢆ

ꢝꢞꢂꢜꢜ

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RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LTC6810-1/

LTC6810-2

4th Generation 6-Cell Battery Stack

Monitor and Balancing IC

Measures Cell Voltages for Up to 6 Series Battery Cells. The isoSPI Daisy-Chain

Capability Allows Multiple Devices to Be Interconnected for Measuring Many Battery

Cells Simultaneously. The isoSPI Bus Can Operate Up to 1MHz and Can Be Operated

Bidirectionally for Fault Conditions, Such as a Broken Wire or Connector. Includes

Internal Passive Cell Balancing Capability of Up to 150mA.

LTC6811-1/

LTC6811-2

4th Generation 12-Cell Battery Stack

Monitor and Balancing IC

Measures Cell Voltages for Up to 12 Series Battery Cells. Daisy-Chain Capability Allows

Multiple Devices to Be Connected to Measure Many Battery Cells Simultaneously Via the

Built-In 1MHz, 2-Wire Isolated Communication (isoSPI). Includes Capability for Passive

Cell Balancing.

LTC6820

isoSPI Isolated Communications Interface Provides an Isolated Interface for SPI Communication Up to 100 Meters, Using a Twisted

Pair. Companion to the LTC6804, LTC6806, LTC6811, LTC6812 and LTC6813

LTC6812-1

4th Generation 15-Cell Battery Stack

Monitor and Balancing IC

Measures Cell Voltages for Up to 15 Series Battery Cells. The isoSPI Daisy-Chain

Capability Allows Multiple Devices to Be Connected to Measuring Many Battery

Cells Simultaneously. The isoSPI Bus Can Operate Up to 1MHz and Can Be Operated

Bidirectionally for Fault Conditions, Such as a Broken Wire or Connector. Includes

Internal Passive Cell Balancing Capability of Up to 200mA.

LTC6813-1

4th Generation 18-Cell Battery Stack

Monitor and Balancing IC

Measures Cell Voltages for Up to 18 Series Battery Cells. The isoSPI Daisy-Chain

Capability Allows Multiple Devices to Be Interconnected for Measuring Many Battery

Cells Simultaneously. The isoSPI Bus Can Operate Up to 1MHz and Can Be Operated

Bidirectionally for Fault Conditions, Such as a Broken Wire or Connector. Includes

Internal Passive Cell Balancing Capability of Up to 200mA.

Rev A

11/20

www.analog.com

 ANALOG DEVICES, INC. 2019-2020

80

For more information www.analog.com


型号：	LTC6812-1
厂家：	ADI
描述：	Current, Voltage, and Charge Monitor for High Voltage Battery Packs 电池
文件：	总80页 (文件大小：3353K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC6812-1 [ADI]

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