LTC6957-4 [ADI]
Low Phase Noise, Dual Output Logic Converter;
| 型号： | LTC6957-4 |
| 厂家： | 
ADI |
| 描述： | Low Phase Noise, Dual Output Logic Converter |
| 文件： | 总38页 (文件大小：1416K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Low Phase Noise, Dual
Output Buffer/Driver/
Logic Converter
FEATURES
DESCRIPTION
n
Low Phase Noise Buffer/Driver
The LTC®6957-1/LTC6957-2/LTC6957-3/LTC6957-4 is a
family of very low phase noise, dual output AC signal
buffer/driver/logic level translators. The input signal can
be a sine wave or any logic level (≤2V ). There are four
members of the family that differ inPt-hPeir output logic
signal type as follows:
n
Optimized Conversion of Sine Wave Signals to
Logic Levels
n
Three Logic Output Types Available
n
LVPECL
n
LVDS
n
CMOS
LTC6957-1: LVPECL Logic Outputs
n
Additive Jitter 45fs
(LTC6957-1)
RMS
LTC6957-2: LVDS Logic Outputs
n
n
n
n
n
Frequency Range Up to 300MHz
3.15V to 3.45V Supply Operation
Low Skew 3ps Typical
Fully Specified from –40°C to 125°C
12-Lead MSOP and 3mm × 3mm DFN Packages
LTC6957-3: CMOS Logic, In-Phase Outputs
LTC6957-4: CMOS Logic, Complementary Outputs
The LTC6957 will buffer and distribute any logic signal
with minimal additive noise, however, the part really
excels at translating sine wave signals to logic levels. The
early amplifier stages have selectable lowpass filtering
to minimize the noise while still amplifying the signal to
increase its slew rate. This input stage filtering/noise limit-
ing is especially helpful in delivering the lowest possible
phase noise signal with slow slewing input signals such
as a typical 10MHz sine wave system reference.
APPLICATIONS
n
System Reference Frequency Distribution
n
High Speed ADC, DAC, DDS Clock Driver
n
Military and Secure Radio
Low Noise Timing Trigger
Broadband Wireless Transceiver
High Speed Data Acquisition
Medical Imaging
Test and Measurement
n
n
n
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents 7969189 and 8319551.
n
n
TYPICAL APPLICATION
3.3V
Additive Phase Noise at 100MHz
0.1µF
ꢑꢏꢙꢐ
ꢂꢔꢈꢢꢞꢃꢟꢃꢈꢡꢃꢡ ꢂꢔꢈꢃ ꢣꢓꢠꢃ ꢔꢈꢒꢇꢄ
ꢓꢄ ꢤ7ꢕꢖꢥ ꢋ5ꢐꢐꢥꢠ
ꢎ
ꢅꢝꢂ
ꢁꢔꢞꢄꢓ ꢦ ꢁꢔꢞꢄꢖ ꢦ ꢢꢈꢡ
+
V
SD1
ꢑꢏꢙ5
ꢑꢏ5ꢐ
ꢑꢏ55
ꢑꢏ6ꢐ
ꢑꢏ65
FILTA
FILTB
TO PLL CHIPS
OR SYSTEM
SAMPLING CLOCKS
ꢞꢄꢉ6957ꢟꢛ ꢋꢞꢠꢡꢂꢎ
ꢞꢄꢉ6957ꢟꢙ ꢋꢉꢝꢀꢂꢎ
OUT1
100MHz
+7dBm
SINE WAVE
10nF
+
IN
OCXO
–
IN
50Ω
10nF
OUT2
ꢞꢄꢉ6957ꢟꢜ
ꢋꢉꢝꢀꢂꢎ
ꢞꢄꢉ6957ꢟꢏ ꢋꢞꢠꢒꢃꢉꢞꢎ
ꢏꢚ ꢏꢐꢚ
ꢀꢁꢁꢂꢃꢄ ꢁꢅꢃꢆꢇꢃꢈꢉꢊ ꢋꢌꢍꢎ
GND
SD2
6957 TA01a
ꢏꢐꢐ
ꢏꢐꢐꢚ
ꢏꢝ
6957ꢏꢛꢜꢙ ꢄꢓꢐꢏb
6957fb
1
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
(Note 1)
ABSOLUTE MAXIMUM RATINGS
+
Supply Voltage (V or V ) to GND..........................3.6V
Specified Temperature Range
DD
+
–
Input Current (IN , IN , FILTA, FILTB, SD1, SD2)
LTC6957I .............................................–40°C to 85°C
LTC6957H.......................................... –40°C to 125°C
Junction Temperature .......................................... 150°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (for MSOP Soldering, 10sec)...300°C
(Note 2) .......................................................... 10mA
LTC6957-1 Output Current ........................ 1mA, –30mA
LTC6957-2 Output Current ................................. 10mA
LTC6957-3, LTC6957-4 Output Current (Note 3).. 30mA
PIN CONFIGURATION
LTC6957-1, LTC6957-2
LTC6957-3, LTC6957-4
ꢀꢁꢂ ꢃꢄꢅꢆ
ꢀꢁꢂ ꢃꢄꢅꢆ
ꢌ
ꢍ
ꢑ
ꢙ
5
6
ꢌꢍ ꢔꢇꢌ
ꢌ
ꢍ
ꢑ
ꢙ
5
6
ꢌꢍ ꢔꢇꢌ
ꢕꢄꢏꢀꢈ
ꢕꢄꢏꢀꢈ
ꢛ
ꢜ
ꢜ
ꢛ
ꢛ
ꢛ
ꢌꢌ
ꢁꢚꢀꢌ
ꢌꢌ
ꢃ
ꢇꢇ
ꢃ
ꢃ
ꢛ
ꢛ
ꢌꢘ ꢁꢚꢀꢌ
ꢌꢘ ꢁꢚꢀꢌ
ꢄꢖ
ꢄꢖ
ꢌꢑ
ꢋꢖꢇ
ꢌꢑ
ꢋꢖꢇ
ꢜ
ꢜ
9
ꢗ
7
9
ꢗ
7
ꢁꢚꢀꢍ
ꢁꢚꢀꢍ
ꢔꢇꢍ
ꢁꢚꢀꢍ
ꢄꢖ
ꢄꢖ
ꢋꢖꢇꢁꢚꢀ
ꢔꢇꢍ
ꢋꢖꢇ
ꢋꢖꢇ
ꢕꢄꢏꢀꢝ
ꢕꢄꢏꢀꢝ
ꢇꢇ ꢂꢈꢉꢊꢈꢋꢅ
ꢌꢍꢎꢏꢅꢈꢇ ꢐꢑꢒꢒ × ꢑꢒꢒꢓ ꢂꢏꢈꢔꢀꢄꢉ ꢇꢕꢖ
ꢇꢇ ꢂꢈꢉꢊꢈꢋꢅ
ꢌꢍꢎꢏꢅꢈꢇ ꢐꢑꢒꢒ × ꢑꢒꢒꢓ ꢂꢏꢈꢔꢀꢄꢉ ꢇꢕꢖ
T
= 150°C, θ = 58°C/W, θ = 10°C/W
T
= 150°C, θ = 58°C/W, θ = 10°C/W
JMAX
JA
JC
JMAX JA JC
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
LTC6957-1, LTC6957-2
LTC6957-3, LTC6957-4
ꢇꢓꢕ ꢉꢅꢖꢗ
ꢇꢓꢕ ꢉꢅꢖꢗ
ꢀ
ꢁ
ꢂ
ꢃ
5
6
ꢀ
ꢁ
ꢂ
ꢃ
5
6
ꢄꢅꢆꢇꢈ
ꢀꢁ ꢒꢎꢀ
ꢀꢀ ꢓꢔꢇꢀ
ꢀꢐ ꢓꢔꢇꢀ
ꢄꢅꢆꢇꢈ
ꢀꢁ ꢒꢎꢀ
ꢀꢀ
ꢀꢐ ꢓꢔꢇꢀ
ꢊ
ꢊ
ꢌ
ꢌ
ꢊ
ꢊ
ꢉ
ꢅꢋ
ꢅꢋ
ꢉ
ꢅꢋ
ꢅꢋ
ꢉ
ꢎꢎ
ꢊ
ꢌ
ꢊ
ꢌ
9
ꢑ
7
ꢓꢔꢇꢁ
ꢓꢔꢇꢁ
ꢒꢎꢁ
9
ꢑ
7
ꢓꢔꢇꢁ
ꢍꢋꢎꢓꢔꢇ
ꢒꢎꢁ
ꢍꢋꢎ
ꢄꢅꢆꢇꢏ
ꢍꢋꢎ
ꢄꢅꢆꢇꢏ
ꢘꢒ ꢕꢈꢙꢚꢈꢍꢖ
ꢀꢁꢛꢆꢖꢈꢎ ꢕꢆꢈꢒꢇꢅꢙ ꢘꢒꢓꢕ
ꢘꢒ ꢕꢈꢙꢚꢈꢍꢖ
ꢀꢁꢛꢆꢖꢈꢎ ꢕꢆꢈꢒꢇꢅꢙ ꢘꢒꢓꢕ
T
= 150°C, θ = 145°C/W
T = 150°C, θ = 145°C/W
JMAX JA
JMAX
JA
6957fb
2
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
ORDER INFORMATION
http://www.linear.com/product/LTC6957-1#orderinfo
LEAD FREE FINISH
LTC6957IDD-1#PBF
LTC6957IDD-2#PBF
LTC6957IDD-3#PBF
LTC6957IDD-4#PBF
LTC6957IMS-1#PBF
LTC6957HMS-1#PBF
LTC6957IMS-2#PBF
LTC6957HMS-2#PBF
LTC6957IMS-3#PBF
LTC6957HMS-3#PBF
LTC6957IMS-4#PBF
LTC6957HMS-4#PBF
TAPE AND REEL
PART MARKING*
LFQJ
PACKAGE DESCRIPTION
12-Lead (3mm × 3mm) Plastic DFN
12-Lead (3mm × 3mm) Plastic DFN
12-Lead (3mm × 3mm) Plastic DFN
12-Lead (3mm × 3mm) Plastic DFN
12-Lead Plastic MSOP
SPECIFIED TEMPERATURE RANGE
–40°C to 85°C
LTC6957IDD-1#TRPBF
LTC6957IDD-2#TRPBF
LTC6957IDD-3#TRPBF
LTC6957IDD-4#TRPBF
LTC6957IMS-1#TRPBF
LTC6957HMS-1#TRPBF
LTC6957IMS-2#TRPBF
LTC6957HMS-2#TRPBF
LTC6957IMS-3#TRPBF
LTC6957HMS-3#TRPBF
LTC6957IMS-4#TRPBF
LTC6957HMS-4#TRPBF
LFQK
–40°C to 85°C
LFQM
–40°C to 85°C
LFQN
–40°C to 85°C
69571
69571
69572
69572
69573
69573
69574
69574
–40°C to 85°C
12-Lead Plastic MSOP
–40°C to 125°C
–40°C to 85°C
12-Lead Plastic MSOP
12-Lead Plastic MSOP
–40°C to 125°C
–40°C to 85°C
12-Lead Plastic MSOP
12-Lead Plastic MSOP
–40°C to 125°C
–40°C to 85°C
12-Lead Plastic MSOP
12-Lead Plastic MSOP
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
6957fb
3
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
ELECTRICAL CHARACTERISTICS LTC6957-1
The ldenotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3.3V,
SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, RLOAD = 50Ω connected to 1.3V, unless otherwise specified. All voltages are with respect to ground.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
–
+
Inputs (IN , IN )
l
l
l
f
Input Frequency Range
300
2
MHz
IN
V
V
Input Signal Level Range, Single-Ended
Input Signal Level Range, Differential
Minimum Input Pulse Width
0.2
0.2
0.8
0.8
0.5
2.06
2
V
V
INSE
INDIFF
MIN
P-P
2
P-P
t
High or Low
ns
+
–
l
l
V
Self-Bias Voltage, IN , IN
1.8
1.5
2.3
2.5
V
INCM
R
Input Resistance, Differential
kΩ
pF
IN
C
Input Capacitance, Differential
0.5
IN
BW
Input Section Small Signal Bandwidth (–3dB)
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
1200
500
160
50
MHz
MHz
MHz
MHz
IN
Outputs (LVPECL)
+
+
+
+
+
+
l
l
V
V
V
Output High Voltage
LTC6957I
LTC6957H
V – 1.22 V – 0.98 V – 0.93
V
V
OH
OL
OD
V – 1.22 V – 0.98 V – 0.87
+
+
+
+
+
+
l
l
Output Low Voltage
LTC6957I
LTC6957H
V – 2.1 V – 1.8 V – 1.67
V
V
V – 2.1 V – 1.8 V – 1.62
l
Output Differential Voltage
Output Rise Time
660
810
180
160
965
mV
ps
t
t
t
r
f
Output Fall Time
ps
l
l
l
l
Propagation Delay
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
0.35
0.5
0.6
1.1
3.2
0.7
0.8
1.3
4
ns
ns
ns
ns
PD
l
l
l
l
∆t /∆T Propagation Delay Variation Over Temperature
PD
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
0.1
0.1
0.11
0.15
ps/°C
ps/°C
ps/°C
ps/°C
l
l
l
∆t /∆V Propagation Delay Variation vs Supply Voltage
FILTB = L, FILTA = L
4
3
50
30
30
ps/V
ps
PD
t
t
Output Skew, Differential, CH1 to CH2
SKEW
+
–
Output Matching (OUTx to OUTx )
See Timing Diagram
2.5
ps
MATCH
Power
+
+
+
l
V
V Operating Supply Voltage Range
R
LOAD
= 50Ω to (V – 2V)
3.15
3.3
3.45
V
I
S
Supply Current
l
l
l
l
Both Outputs Enabled (SD1 = SD2 = L)
No Output Loads
18
15
0.7
58
22
19
1.2
72
mA
mA
mA
mA
One Output Enabled (SD1 = L, SD2 = H or SD1 = H, SD2 = L) No Output Loads
Both Outputs Disabled (SD1 = SD2 = H)
Including Output Loads
No Output Loads
+
R
LOAD
= 50Ω to (V – 2V), ×4
t
t
t
t
Output Enable Time, Other SDx = L
Output Enable Time, Other SDx = H
Output Disable Time, Other SDx = L
Output Disable Time, Other SDx = H
40
120
20
µs
µs
µs
µs
ENABLE
WAKEUP
DISABLE
SLEEP
20
6957fb
4
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
ELECTRICAL CHARACTERISTICS LTC6957-1
The ldenotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3.3V,
SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, RLOAD = 50Ω connected to 1.3V, unless otherwise specified. All voltages are with respect to ground.
SYMBOL PARAMETER
Digital Logic Inputs
CONDITIONS
MIN
TYP
MAX
UNITS
+
l
l
l
V
High Level SD or FILT Input Voltage
Low Level SD or FILT Input Voltage
Input Current SD or FILT Pins
V – 0.4
V
V
IH
V
0.4
10
IL
I
0.1
µA
IN_DIG
Additive Phase Noise and Jitter
f
f
f
= 300MHz Sine Wave, 7dBm (FILTA = L, FILTB = L)
at 10Hz Offset
IN
IN
IN
–130
–140
–150
–157
–157.5
–157.5
123
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
at 100Hz Offset
at 1kHz Offset
at 10kHz Offset
at 100kHz Offset
>1MHz Offset
Jitter (10Hz to 150MHz)
Jitter (12kHz to 20MHz)
fs
fs
RMS
RMS
45
= 122.88MHz Sine Wave, 0dBm (FILTA = H, FILTB = L)
at 10Hz Offset
–137
–146
–154.6
–157
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
at 100Hz Offset
at 1kHz Offset
at 10kHz Offset
at 100kHz Offset
–157.2
–157.2
200
>1MHz Offset
Jitter (10Hz to 61.44MHz)
Jitter (12kHz to 20MHz)
fs
RMS
fs
RMS
114
= 100MHz Sine Wave, 10dBm (FILTA = L, FILTB = L)
at 10Hz Offset
–138
–148.1
–156.8
–160.6
–161
–161
142
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
at 100Hz Offset
at 1kHz Offset
at 10kHz Offset
at 100kHz Offset
>1MHz Offset
Jitter (10Hz to 50MHz)
Jitter (12kHz to 20MHz)
fs
RMS
fs
RMS
90
6957fb
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For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
ELECTRICAL CHARACTERISTICS LTC6957-2
The ldenotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3.3V,
SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, RLOAD = 110Ω differential, unless otherwise specified. All voltages are with respect to ground.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
–
+
Inputs (IN , IN )
l
l
l
f
Input Frequency Range
300
2
MHz
IN
V
V
Input Signal Level Range, Single-Ended
Input Signal Level Range, Differential
Minimum Input Pulse Width
0.2
0.2
0.8
0.8
0.5
2
V
V
INSE
INDIFF
MIN
P-P
2
P-P
t
High or Low
ns
+
–
l
l
V
Self-Bias Voltage, IN , IN
1.8
1.5
2.3
2.5
V
INCM
R
Input Resistance, Differential
2
kΩ
pF
IN
IN
C
Input Capacitance, Differential
Input Section Small Signal Bandwidth
0.5
BW
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
1200
500
160
50
MHz
MHz
MHz
MHz
IN
Outputs (LVDS)
Output Differential Voltage
Delta V
l
l
l
l
l
V
250
360
0.2
450
50
mV
mV
V
OD
∆V
OD
OD
V
Output Offset Voltage
Delta V
1.125
1.25
1.5
1.375
50
OS
∆V
mV
mA
ps
OS
OS
I
t
t
t
Short-Circuit Current
Output Rise Time
Output Fall Time
3.9
6
SC
170
170
r
ps
f
l
l
l
l
Propagation Delay
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
0.65
0.84
0.9
1.35
3.5
1.15
1.3
1.8
4.4
ns
ns
ns
ns
PD
l
l
l
l
∆t /∆T Propagation Delay Variation Over Temperature
PD
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
0.5
0.6
0.7
1.8
ps/°C
ps/°C
ps/°C
ps/°C
l
l
∆t /∆V Propagation Delay Variation vs Supply Voltage
FILTB = L, FILTA = L
5
3
60
50
ps/V
ps
PD
t
Output Skew, Differential, CH1 to CH2
SKEW
Power
+
+
l
V
V Operating Supply Voltage Range
3.15
3.3
3.45
V
I
Supply Current
S
l
l
l
Both Outputs Enabled (SD1 = SD2 = L)
One Output Enabled (SD1 = L, SD2 = H or SD1 = H, SD2 = L)
Both Outputs Disabled (SD1 = SD2 = H)
38
26
0.7
45
30
1.2
mA
mA
mA
t
t
t
t
Output Enable Time, Other SDx = L
Output Enable Time, Other SDx = H
Output Disable Time, Other SDx = L
Output Disable Time, Other SDx = H
300
400
40
ns
ns
ns
ns
ENABLE
WAKEUP
DISABLE
SLEEP
50
6957fb
6
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
ELECTRICAL CHARACTERISTICS LTC6957-2
The ldenotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3.3V,
SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, RLOAD = 110Ω differential, unless otherwise specified. All voltages are with respect to ground.
SYMBOL PARAMETER
Digital Logic Inputs
CONDITIONS
MIN
TYP
MAX
UNITS
+
l
l
l
V
High Level SD or FILT Input Voltage
Low Level SD or FILT Input Voltage
Input Current SD or FILT Pins
V – 0.4
V
V
IH
V
IL
0.4
10
I
0.1
µA
IN_DIG
Additive Phase Noise and Jitter
f
IN
f
IN
f
IN
= 300MHz Sine Wave, 7dBm (FILTA = L, FILTB = L)
10Hz Offset
–124
–134
–143.5
–151.3
–154
–154
183
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
100Hz Offset
1kHz Offset
10kHz Offset
100kHz Offset
>1MHz Offset
Jitter (10Hz to 150MHz)
Jitter (12kHz to 20MHz)
fs
fs
RMS
RMS
67
= 122.88MHz Sine Wave, 0dBm (FILTA = H, FILTB = L)
10Hz Offset
–132.5
–142.5
–150.7
–156
–157
–157
203
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
100Hz Offset
1kHz Offset
10kHz Offset
100kHz Offset
>1MHz Offset
Jitter (10Hz to 61.44MHz)
Jitter (12kHz to 20MHz)
fs
RMS
fs
RMS
116
= 100MHz Sine Wave, 10dBm (FILTA = L, FILTB = L)
10Hz Offset
–132
–142
–151
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
100Hz Offset
1kHz Offset
10kHz Offset
–157.5
–159.5
–159.5
169
100kHz Offset
>1MHz Offset
Jitter (10Hz to 50MHz)
Jitter (12kHz to 20MHz)
fs
RMS
fs
RMS
107
6957fb
7
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
ELECTRICAL CHARACTERISTICS LTC6957-3/LTC6957-4
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
V+ = VDD = 3.3V, SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, RLOAD = 480Ω to VDD/2, unless otherwise specified. All voltages are with
respect to ground.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
–
+
Inputs (IN , IN )
l
l
l
f
Input Frequency Range
300
2
MHz
IN
V
V
Input Signal Level Range, Single-Ended
Input Signal Level Range, Differential
Minimum Input Pulse Width
0.2
0.2
0.8
0.8
0.6
2
V
V
INSE
INDIFF
MIN
P-P
2
P-P
t
High or Low
ns
+
–
l
l
V
Self-Bias Voltage, IN , IN
1.8
1.5
2.3
2.5
V
INCM
R
Input Resistance, Differential
2
kΩ
pF
IN
IN
C
Input Capacitance, Differential
Input Section Small Signal Bandwidth
0.5
BW
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
1200
500
160
50
MHz
MHz
MHz
MHz
IN
Outputs (CMOS)
l
l
V
OH
Output High Voltage
No Load
–3mA Load
V
DD
V
DD
– 0.1
– 0.2
V
V
l
l
V
OL
Output Low Voltage
No Load
3mA Load
0.1
0.2
V
V
t
t
t
Output Rise Time
Output Fall Time
Propagation Delay
320
300
ps
ps
r
f
l
l
l
l
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
0.8
0.95
1
1.5
3.6
1.6
1.8
2.4
4.8
ns
ns
ns
ns
PD
l
l
l
l
∆t /∆T Propagation Delay Variation Over Temperature
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
1.7
1.7
2
ps/°C
ps/°C
ps/°C
ps/°C
PD
3
+
l
∆t /∆V Propagation Delay Variation vs Supply Voltage
PD
FILTB = FILTA = L, V = V
100
200
ps/V
DD
t
Output Skew, CH1 to CH2
LTC6957-3
LTC6957-4
SKEW
l
l
5
120
35
250
ps
ps
Power
+
+
l
l
V
V Operating Supply Voltage Range
3.15
2.4
3.3
3.3
3.45
3.45
V
V
+
V
V
Operating Supply Voltage Range
V
Must Be ≤V
DD
DD
DD
I
Supply Current, Pin 2
S
l
l
l
Both Outputs Enabled (SD1 = SD2 = L)
One Output Enabled (SD1 = L, SD2 = H or SD1 = H, SD2 = L)
Both Outputs Disabled (SD1 = SD2 = H)
24
24
0.7
27.5
27.5
1.2
mA
mA
mA
l
l
I
Supply Current, Pin 11, No Load
Static
Dynamic, per Output
0.001
0.056
0.01
0.07
mA
mA/MHz
DD
t
t
t
t
Output Enable Time, Other SDx = L
Output Enable Time, Other SDx = H
Output Disable Time, Other SDx = L
Output Disable Time, Other SDx = H
200
300
20
ns
ns
ns
ns
ENABLE
WAKEUP
DISABLE
SLEEP
20
6957fb
8
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
ELECTRICAL CHARACTERISTICS LTC6957-3/LTC6957-4
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
V+ = VDD = 3.3V, SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, RLOAD = 480Ω to VDD/2, unless otherwise specified. All voltages are with
respect to ground.
SYMBOL PARAMETER
Digital Logic Inputs
CONDITIONS
MIN
TYP
MAX
UNITS
+
l
l
l
V
V
High Level SD or Filt Input Voltage
Low Level SD or Filt Input Voltage
Input Current SD or Filt Pins
V – 0.4
V
V
IH
0.4
10
IL
I
0.1
µA
IN_DIG
Additive Phase Noise and Jitter
f
IN
f
IN
f
IN
= 300MHz Sine Wave, 7dBm (FILTA = L, FILTB = L)
10Hz Offset
–123
–133
–143
–152
–156
–156
146
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
100Hz Offset
1kHz Offset
10kHz Offset
100kHz Offset
>1MHz Offset
Jitter (10Hz to 150MHz)
Jitter (12kHz to 20MHz)
fs
fs
RMS
RMS
53
= 122.88MHz Sine Wave, 0dBm (FILTA = H, FILTB = L)
10Hz Offset
–132
–142
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
100Hz Offset
1kHz Offset
–150.6
–156.5
–157.4
–157.4
192
10kHz Offset
100kHz Offset
>1MHz Offset
Jitter (10Hz to 61.44MHz)
Jitter (12kHz to 20MHz)
fs
fs
RMS
RMS
109
= 100MHz Sine Wave, 10dBm (FILTA = L, FILTB = L)
10Hz Offset
–135
–145
–153
–159.8
–161
–161
142
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
100Hz Offset
1kHz Offset
10kHz Offset
100kHz Offset
>1MHz Offset
Jitter (10Hz to 50MHz)
Jitter (12kHz to 20MHz)
fs
fs
RMS
RMS
90
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Input pins IN , IN , FILTA, FILTB, SD1 and SD2 are protected by
steering diodes to either supply. If the inputs go beyond either supply rail,
the input current should be limited to less than 10mA. If pushing current
into FILTB, the Pin 6 voltage must be limited to 4V. On the logic pins
(FILTA, FILTB, SD1 and SD2) the Absolute Maximum input current applies
only at the maximum operating supply voltage of 3.45V; 10mA of input
current with the absolute maximum supply voltage of 3.6V may create
permanent damage from voltage stress.
Note 3: With 3.6V Absolute Maximum supply voltage, the LTC6957-3/
LTC6957-4 CMOS outputs can sink 30mA while low, and source 30mA
while high without damage. However, if overdriven or subject to an
inductive load kick outside the supply rails, 30mA can create damaging
+
–
voltage stress and is not guaranteed unless V is limited to 3.15V.
DD
6957fb
9
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
TYPICAL PERFORMANCE CHARACTERISTICS
LTC6957-1
Input Self Bias Voltage
vs Temperature
Supply Current vs Supply Voltage
Supply Current vs Temperature
ꢕꢍꢕꢎ
ꢕꢍꢌ5
ꢕꢍꢌꢎ
ꢕꢍꢎ5
ꢕꢍꢎꢎ
ꢌꢍ95
ꢌꢍ9ꢎ
ꢔꢍ
ꢓꢕ
ꢓ6
ꢓꢖ
ꢓꢔ
ꢓꢍ
ꢕ
ꢌꢔꢍ6
ꢌꢔꢍꢔ
ꢌꢔꢍꢖ
ꢌꢔꢍꢓ
ꢌꢔꢍꢗ
ꢌ7ꢍꢔ
ꢌ7ꢍꢖ
ꢌ7ꢍꢓ
ꢌ7ꢍꢗ
ꢌ6ꢍꢔ
ꢌ6ꢍ6
ꢙ
ꢑꢜ ꢜꢆꢀꢃꢆꢀ ꢏꢜꢅꢝꢎ
ꢑꢆ ꢆꢁꢇꢂꢁꢇ ꢃꢆꢈꢛꢀ
ꢑ
ꢚ ꢖꢍꢗ5ꢑ
ꢚ ꢖꢍꢖꢑ
ꢚ
ꢇ
ꢈ
ꢘ ꢓꢔ5ꢙꢏ
ꢙ
ꢛ ꢕꢍꢖ5ꢙ
ꢙ
ꢚ
ꢙ
ꢛ ꢕꢍꢕꢙ
ꢙ
ꢑ
ꢚ
ꢛ ꢕꢍꢌ5ꢙ
ꢇ
ꢘ ꢚ55ꢙꢏ
ꢈ
ꢇ
ꢘ ꢔ5ꢙꢏ
ꢈ
ꢙ
ꢑ
ꢚ ꢖꢍꢌ5ꢑ
6
ꢖ
ꢔ
ꢍ
ꢋ55 ꢋꢕ5 ꢋꢌ5
5
ꢓ5 ꢖ5 65 ꢔ5 ꢌꢗ5 ꢌꢓ5
ꢋ55 ꢋꢖ5 ꢋꢌ5
5
ꢕ5 ꢗ5 65 ꢘ5 ꢌꢎ5 ꢌꢕ5
ꢀꢁꢂꢃꢁꢄꢅꢀꢆꢄꢁ ꢇꢈꢉꢊ
ꢍꢎ6 ꢍꢎ9 ꢓꢎꢔ ꢓꢎ5 ꢓꢎꢕ ꢔꢎꢓ ꢔꢎꢖ ꢔꢎ7 ꢗꢎꢍ ꢗꢎꢗ ꢗꢎ6
ꢀꢁꢂꢂꢃꢄ ꢅꢆꢃꢇꢈꢉꢊ ꢋꢅꢌ
ꢀꢁꢂꢃꢁꢄꢅꢀꢆꢄꢁ ꢇꢈꢉꢊ
6957ꢌꢓꢕꢖ ꢘꢗꢕ
6957ꢌꢕꢖꢗ ꢔꢎꢌ
6957ꢓꢔꢗꢖ ꢉꢍꢔ
Output Voltage vs Load Current
Output Voltage vs Temperature
Supply Current vs Temperature
2.4
2.2
1.6
1.4
ꢕꢐ55
ꢕꢐ5ꢏ
ꢕꢐꢗ5
ꢕꢐꢗꢏ
ꢕꢐꢑ5
ꢕꢐꢑꢏ
ꢎꢐ6ꢏ
ꢎꢐ55
ꢎꢐ5ꢏ
ꢎꢐꢗ5
ꢎꢐꢗꢏ
ꢎꢐꢑ5
58
56
54
52
50
48
46
+
V
= 3.3V
50Ω LOADS TO 1.3V
+
V
= 3.45V
V
OH
ꢓ
ꢁꢘ
+
V
= 3.3V
+
V
= 3.15V
ꢓ
ꢁꢀ
V
OL
50Ω “Y” LOAD TO GROUND
ON BOTH CHANNELS
–55 –35 –15
5
25 45 65 85 105 125
ꢍꢎꢏ
ꢍꢖ
ꢍ6
ꢍꢗ
ꢍꢕ
ꢏ
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
ꢀꢁꢂꢃ ꢄꢅꢆꢆꢇꢈꢉ ꢊꢋꢂꢌ
TEMPERATURE (°C)
69571234 G05
6957ꢎꢕꢑꢗ ꢔꢏꢗ
69571234 G06
Enable and Wakeup
Typical Distribution of Skew
Differential Output vs Frequency
ꢙꢗꢚ
ꢙꢗ6
ꢙꢗꢜ
ꢙꢗꢘ
ꢙꢗꢍ
ꢍꢗꢚ
ꢍꢗ6
ꢍꢗꢜ
ꢍꢗꢘ
ꢍ
ꢀꢉ5ꢇ
ꢀꢉꢁꢇ
ꢊꢉ5ꢇ
ꢀꢉ5ꢇ
ꢀꢉꢁꢇ
ꢊꢉ5ꢇ
ꢈꢉꢁꢇ
ꢁꢇ
ꢓꢉꢉ
ꢘꢉ
6ꢉ
ꢖꢉ
ꢔꢉ
ꢉ
ꢏꢋꢒꢓꢤ ꢒꢏ ꢏꢋꢒꢔꢤ ꢎꢑꢁꢑꢊꢗ ꢃꢛꢗꢃ
ꢒꢢꢚꢑꢜꢝꢟ ꢏꢐ ꢝꢟꢟ ꢏꢋꢒꢚꢋꢒ ꢃꢛꢗꢃꢁꢥꢚꢝꢑꢎꢁ
ꢢꢠꢚꢒꢣꢎꢑꢤ
ꢔꢎꢐꢑꢎꢐꢕ ꢢꢆꢐꢜ
ꢔꢐꢜꢒꢖ ꢙꢜꢠꢘꢘꢒꢏ ꢔꢥꢥ
ꢔ ꢟꢏꢒꢁꢞ ꢖꢉꢉ
ꢋꢊꢑꢒꢁ ꢃꢝꢜꢣꢞ
ꢕ ꢒꢃꢌꢚꢃꢎꢝꢒꢋꢎꢃꢁ
ꢦ ꢓꢔ5ꢧꢜ
ꢙꢘ5ꢟꢆ
ꢦ ꢔ5ꢧꢜ
ꢦ ꢙ55ꢧꢜ
ꢘ5ꢟꢆ
ꢒꢘꢠꢦꢏꢒꢤ ꢔꢎꢐꢑꢎꢐꢕ ꢢꢆꢐꢜ
ꢔꢐꢜꢒꢖ ꢙꢜꢠꢘꢘꢒꢏ ꢔꢘ
ꢕꢅ
ꢞ55ꢟꢆ
6957ꢊꢀꢈꢋ ꢌꢁ7
ꢀꢁꢂꢃꢄꢅꢆꢇ
ꢍꢠꢡꢢ ꢏꢅꢔꢄꢐ
ꢍꢎꢏꢐꢆꢑꢏꢒ ꢒꢓꢑꢔꢕꢎꢖꢒꢕꢗ ꢑꢒꢖꢕꢆꢕꢐꢒꢘꢙꢒ ꢍꢔꢅꢒ
ꢙꢏꢔꢙꢚ ꢆꢄꢔ ꢛ ꢊꢀꢁꢍꢜꢝ
ꢙꢓꢉ ꢙꢘ ꢙ6 ꢙꢖ ꢙꢔ
ꢉ
ꢔ
ꢖ
6
ꢍ
ꢘ5ꢍ 5ꢍꢍ 75ꢍ ꢙꢍꢍꢍ ꢙꢘ5ꢍ ꢙ5ꢍꢍ ꢙ75ꢍ
ꢀꢁꢂꢃꢄꢂꢅꢆꢇ ꢈꢉꢊꢋꢌ
ꢘ
ꢓꢉ
ꢘꢍꢍꢍ
ꢀ
ꢅꢆꢇꢈ
ꢁꢂꢃꢄ
6957ꢓꢔꢕꢖ ꢗꢉꢘ
ꢚꢎꢏꢛꢋꢜꢒꢑꢏꢊ ꢛꢝꢒꢝꢞ
ꢓꢆꢇ ꢎꢃꢁꢏꢟꢋꢒꢑꢏꢊꢞ ꢠꢓꢡꢔꢆꢇ ꢋꢊꢜꢃꢎꢒꢝꢑꢊꢒꢢ
6957ꢙꢘꢛꢜ ꢝꢍ9
6957fb
10
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
TYPICAL PERFORMANCE CHARACTERISTICS
LTC6957-1
Additive Phase Noise
vs Input Frequency
Additive Phase Noise
vs Amplitude
Additive Phase Noise
vs Temperature
ꢑꢏꢚꢐ
ꢑꢏꢚꢐ
ꢑꢏꢚ5
ꢑꢏꢙꢐ
ꢑꢏꢙ5
ꢑꢏ5ꢐ
ꢑꢏ55
ꢑꢏ6ꢐ
ꢑꢏ65
ꢑꢏꢚꢐ
ꢑꢏꢚ5
ꢑꢏꢙꢐ
ꢑꢏꢙ5
ꢑꢏ5ꢐ
ꢑꢏ55
ꢑꢏ6ꢐ
ꢑꢏ65
ꢂꢔꢈꢝꢠꢃꢡꢃꢈꢢꢃꢢ ꢂꢔꢈꢃ ꢣꢓꢤꢃ ꢔꢈꢒꢇꢄ
ꢓꢄ 7ꢕꢖꢥ ꢋ5ꢐꢐꢥꢤ
ꢁꢔꢠꢄꢓ ꢦ ꢁꢔꢠꢄꢖ ꢦ ꢠ
ꢂꢔꢈꢝꢡꢃꢤꢃꢈꢥꢃꢥ ꢏꢐꢐꢞꢌꢍ ꢂꢔꢈꢃ ꢦꢓꢧꢃ ꢔꢈꢒꢇꢄ
ꢂꢃꢃ ꢓꢒꢒꢡꢔꢉꢓꢄꢔꢀꢈꢂ ꢔꢈꢁꢀꢅꢞꢓꢄꢔꢀꢈ
ꢂꢔꢈꢝꢠꢃꢡꢃꢈꢢꢃꢢ ꢂꢔꢈꢃ ꢣꢓꢤꢃ ꢔꢈꢒꢇꢄꢥ
ꢎ
ꢏꢐꢐꢞꢌꢍ ꢦꢧ 7ꢕꢖꢨ ꢋ5ꢐꢐꢨꢤ
ꢁꢔꢠꢄꢓ ꢩ ꢁꢔꢠꢄꢖ ꢩ ꢠ
ꢎ
ꢅꢞꢂ
ꢅꢞꢂ
ꢑꢏꢚ5
ꢑꢏꢙꢐ
ꢑꢏꢙ5
ꢑꢏ5ꢐ
ꢑꢏ55
ꢑꢏ6ꢐ
ꢑꢏ65
ꢑꢏꢐꢕꢖꢟꢠ ꢁꢔꢡꢄꢓ ꢢ ꢡꢠ ꢁꢔꢡꢄꢖ ꢢ ꢌ
ꢐꢕꢖꢟꢠ ꢁꢔꢡꢄꢓ ꢢ ꢌꢠ ꢁꢔꢡꢄꢖ ꢢ ꢡ
ꢚꢐꢐꢞꢌꢍ
ꢏꢜ5ꢟꢉ
ꢏ5ꢚꢟ6ꢞꢌꢍ
ꢜ5ꢟꢉ
ꢏꢐꢐꢞꢌꢍ
ꢣꢏꢐꢕꢖꢟꢠ ꢁꢔꢡꢄꢓ ꢢ ꢁꢔꢡꢄꢖ ꢢ ꢡ
ꢑ55ꢟꢉ
ꢏꢐꢛ
ꢀꢁꢁꢂꢃꢄ ꢁꢅꢃꢆꢇꢃꢈꢉꢊ ꢋꢌꢍꢎ
ꢏꢐꢐ
ꢏꢛ
ꢏꢐꢛ
ꢏꢐꢐꢛ
ꢏꢞ
ꢏꢐꢐ
ꢏꢛ
ꢏꢐꢛ
ꢏꢐꢐꢛ
ꢏꢞ
ꢏꢐꢐ
ꢏꢛ
ꢏꢐꢐꢛ
ꢏꢞ
ꢀꢁꢁꢂꢃꢄ ꢁꢅꢃꢆꢇꢃꢈꢉꢊ ꢋꢌꢍꢎ
ꢀꢁꢁꢂꢃꢄ ꢁꢅꢃꢆꢇꢃꢈꢉꢊ ꢋꢌꢍꢎ
6957ꢏꢜꢚꢙ ꢝꢏꢐ
6957ꢏꢜꢚꢙ ꢝꢏꢏ
6957ꢏꢜꢚꢙ ꢝꢏꢜ
Additive Phase Noise
vs Supply Voltage
Additive Phase Noise at 122.88MHz
AM to PM Conversion
ꢑꢏꢚꢐ
ꢑꢏꢚ5
ꢑꢏꢙꢐ
ꢑꢏꢙ5
ꢑꢏ5ꢐ
ꢑꢏ55
ꢑꢏ6ꢐ
ꢑꢏ65
5
ꢙ
ꢑꢏꢚꢐ
ꢑꢏꢚ5
ꢑꢏꢙꢐ
ꢑꢏꢙ5
ꢑꢏ5ꢐ
ꢑꢏ55
ꢑꢏ6ꢐ
ꢑꢏ65
f
ꢟ ꢛꢑꢑꢆꢕꢠ
ꢟ ꢛꢢꢛꢞ
ꢂꢔꢈꢝꢡꢃꢢꢃꢈꢣꢃꢣ ꢂꢔꢈꢃ ꢤꢓꢠꢃ ꢔꢈꢒꢇꢄꢥ
ꢂꢔꢈꢝꢡꢃꢣꢃꢈꢤꢃꢤ ꢂꢔꢈꢃ ꢥꢓꢦꢃ ꢔꢈꢒꢇꢄ
ꢀꢁ
ꢡ
ꢞ
ꢏꢐꢐꢞꢌꢍ ꢦꢧ 7ꢕꢖꢨ ꢋ5ꢐꢐꢨꢠ
ꢁꢔꢡꢄꢓ ꢩ ꢁꢔꢡꢄꢖ ꢩ ꢡ
ꢎ
ꢅꢞꢂ
ꢛ
ꢚ
ꢐ
ꢏ55ꢜꢝ
ꢑ
ꢐꢕꢖꢟꢠ ꢁꢔꢡꢄꢓ ꢢ ꢌꢠ ꢁꢔꢡꢄꢖ ꢢ ꢡ
ꢏꢐ
ꢏꢚ
ꢏꢛ
ꢏꢙ
ꢏ5
ꢚꢟꢙ5ꢠ
ꢚꢟꢏ5ꢠ
ꢚꢟꢚꢠ
ꢐꢚ5ꢜꢝ
ꢚ5ꢜꢝ
7ꢕꢖꢟꢠ ꢁꢔꢡꢄꢓ ꢢ ꢁꢔꢡꢄꢖ ꢢ ꢡ
ꢏꢐꢐ ꢏꢛ ꢏꢐꢛ
ꢉꢅꢝꢕ ꢝꢃꢓꢞꢉ ꢁꢒꢓꢆꢅꢇꢀꢔꢉꢈ ꢄꢒ ꢑꢜ ꢅꢄ ꢑꢋꢌꢍ
ꢏꢐꢑ ꢏꢘ ꢏ6 ꢏꢙ ꢏꢚ ꢐꢑ
ꢏꢐꢐ
ꢏꢛ
ꢏꢐꢛ
ꢏꢐꢐꢛ
ꢏꢞ
ꢑ
ꢚ
ꢙ
6
ꢘ
ꢏꢐꢐꢛ
ꢀꢁꢁꢂꢃꢄ ꢁꢅꢃꢆꢇꢃꢈꢉꢊ ꢋꢌꢍꢎ
ꢏꢞ
ꢀꢁꢁꢂꢃꢄ ꢁꢅꢃꢆꢇꢃꢈꢉꢊ ꢋꢌꢍꢎ
ꢀꢁꢂꢃꢄ ꢅꢆꢂꢇꢀꢄꢃꢈꢉ ꢊꢋꢌꢍꢎ
6957ꢏꢜꢚꢙ ꢝꢏꢚ
6957ꢐꢚꢛꢙ ꢗꢐ5
6957ꢏꢜꢚꢙ ꢝꢏꢙ
tPD vs Supply Voltage and
Termination Voltage
tPD vs Temperature
tPD vs Temperature
0.550
0.525
0.500
0.475
0.450
ꢑꢒ5
ꢑꢒꢌ
ꢓꢒꢌ
ꢌꢒ5
ꢌ
0.56
0.54
0.52
0.50
0.48
0.46
+
V
= 3.0V, 50Ω LOADS TO 1.3V
ꢘꢙꢚꢀꢅ ꢛ ꢘꢙꢚꢀꢝ ꢛ ꢞ
+
V
= 3.6V, 50Ω LOADS TO 1.9V
+
50Ω LOADS TO V –2V
ꢘꢙꢚꢀꢅ ꢛ ꢚꢜ ꢘꢙꢚꢀꢝ ꢛ ꢞ
+
V
= 3.3V, 50Ω LOADS TO 1.3V
ꢘꢙꢚꢀꢅ ꢛ ꢞꢜ ꢘꢙꢚꢀꢝ ꢛ ꢚ
ꢘꢙꢚꢀꢅ ꢛ ꢘꢙꢚꢀꢝ ꢛ ꢚ
50Ω LOADS TO FIXED 1.3V
FILTA = FILTB = L
FILTA = FILTB = L
–55 –35 –15
5
25 45 65 85 105 125
ꢋ55 ꢋꢑ5 ꢋꢓ5
5
ꢖ5 ꢕ5 65 ꢔ5 ꢓꢌ5 ꢓꢖ5
3
3.1
3.2
3.3
3.4
3.5
3.6
TEMPERATURE (°C)
ꢀꢁꢂꢃꢁꢄꢅꢀꢆꢄꢁ ꢇꢈꢉꢊ
SUPPLY VOLTAGE (V)
69571234 G17
6957ꢓꢖꢑꢕ ꢗꢓ6
69571234 G18
6957fb
11
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
TYPICAL PERFORMANCE CHARACTERISTICS
LTC6957-2
Input Self Bias Voltage
vs Temperature
Supply Current vs Supply Voltage
Supply Current vs Temperature
ꢕꢍꢕꢎ
ꢕꢍꢌ5
ꢕꢍꢌꢎ
ꢕꢍꢎ5
ꢕꢍꢎꢎ
ꢌꢍ95
ꢌꢍ9ꢎ
ꢔ5
ꢔꢍ
ꢗ5
ꢗꢍ
ꢕ5
ꢕꢍ
ꢓ5
ꢓꢍ
5
ꢕꢖꢍꢔ
ꢕꢔꢍ5
ꢕꢔꢍꢔ
ꢌ9ꢍ5
ꢌ9ꢍꢔ
ꢌꢓꢍ5
ꢌꢓꢍꢔ
ꢌ7ꢍ5
ꢙ
ꢑ
ꢚ ꢖꢍꢗ5ꢑ
ꢚ
ꢙ
ꢛ ꢌꢍꢕ5ꢙ
ꢚ
ꢙ
ꢛ ꢌꢍꢌꢙ
ꢙ
ꢇ
ꢘ ꢓꢕ5ꢙꢏ
ꢑ
ꢚ ꢖꢍꢖꢑ
ꢈ
ꢇ
ꢘ ꢕ5ꢙꢏ
ꢈ
ꢚ
ꢙ
ꢛ ꢌꢍꢖ5ꢙ
ꢙ
ꢑ
ꢚ ꢖꢍꢌ5ꢑ
ꢇ
ꢘ ꢚ55ꢙꢏ
ꢈ
ꢍ
ꢋ55 ꢋꢖ5 ꢋꢌ5
5
ꢕ5 ꢗ5 65 ꢘ5 ꢌꢎ5 ꢌꢕ5
ꢀꢁꢂꢃꢁꢄꢅꢀꢆꢄꢁ ꢇꢈꢉꢊ
ꢍꢎ6 ꢍꢎ9 ꢓꢎꢕ ꢓꢎ5 ꢓꢎꢖ ꢕꢎꢓ ꢕꢎꢔ ꢕꢎ7
ꢀꢁꢂꢂꢃꢄ ꢅꢆꢃꢇꢈꢉꢊ ꢋꢅꢌ
ꢗ
ꢗꢎꢗ ꢗꢎ6
ꢋ55 ꢋꢌ5 ꢋꢖ5
5
ꢗ5 ꢕ5 65 ꢓ5 ꢖꢔ5 ꢖꢗ5
ꢀꢁꢂꢃꢁꢄꢅꢀꢆꢄꢁ ꢇꢈꢉꢊ
6957ꢌꢕꢖꢗ ꢔꢌ9
6957ꢓꢕꢗꢔ ꢉꢕꢍ
6957ꢖꢗꢌꢕ ꢘꢗꢖ
Output Voltages vs Load Resistor
Output Voltages vs Temperature
Output Voltages vs Loading
ꢌꢍ5
ꢌꢍꢚ
ꢌꢍꢘ
ꢌꢍꢛ
ꢌꢍꢌ
ꢌꢍꢎ
ꢚꢘꢎ
ꢚꢛꢎ
ꢚꢌꢎ
ꢚꢎꢎ
ꢘ9ꢎ
ꢘꢙꢎ
1.8
1.6
1.4
1.2
1.0
0.8
ꢌꢏ5
ꢌꢏꢓ
ꢌꢏꢒ
ꢌꢏꢐ
ꢌꢏꢌ
ꢌ
DC DATA,
+
–
IN > (IN + 50mV)
ꢏ
ꢇꢂꢁꢅꢖꢆꢄꢁꢕꢊ
ꢐꢑ
ꢌꢐ5ꢛꢜ
ꢐ5ꢛꢜ
ꢕ55ꢛꢜ
ꢔ
ꢅꢍꢁ
+
OUT
ꢏ
ꢇꢉꢅꢓꢉꢆꢓꢅꢀꢁꢕꢊ
ꢇꢉꢅꢓꢉꢆꢓꢅꢀꢁꢕꢊ
ꢐꢖ
ꢏ
ꢐꢕ
ꢕ
–
ꢅꢍꢁ
OUT
+
+
+
V
V
V
= 3.6V
= 3.3V
= 3V
ꢏ
ꢇꢂꢁꢅꢖꢆꢄꢁꢕꢊ
ꢐꢓ
ꢄꢅꢆꢇ ꢃꢁꢖꢂꢃꢃ ꢎꢂꢖ ꢁꢗꢆꢘꢂꢗꢆꢙ6ꢓꢓꢙꢆ ꢚꢗꢈꢍꢖꢂ ꢓ
ꢋꢏ6 ꢌꢏꢐ ꢌꢏꢑ
ꢄꢅꢆꢇ ꢀꢅꢄꢁꢆꢈꢂ ꢉꢀꢊ
ꢋ55 ꢋꢘ5 ꢋꢌ5
5
ꢛ5 ꢚ5 65 ꢙ5 ꢌꢎ5 ꢌꢛ5
0
50
100
150
200
250
ꢋ
ꢐꢏꢓ
ꢀꢁꢂꢃꢁꢄꢅꢀꢆꢄꢁ ꢇꢈꢉꢊ
LOAD RESISTOR (Ω)
ꢀ
ꢁꢂꢃꢁ
USE OF R
> 150Ω
6957ꢌꢛꢘꢚ ꢜꢛꢘ
69571234 G22
6957ꢌꢐꢒꢓ ꢈꢐꢓ
LOAD
NOT RECOMMENDED
f
MAY BE COMPROMISED
IN
Output Short-Circuit Current
vs Temperature
Enable and Wakeup
Differential Output vs Frequency
ꢖꢍꢗꢗ
900
800
700
600
500
400
300
200
100
0
ꢤꢠꢚꢒꢥꢎꢑꢣ
ꢀꢉꢁꢇ
ꢊꢉ5ꢇ
ꢊꢉꢁꢇ
ꢀꢉꢁꢇ
ꢊꢉ5ꢇ
ꢊꢉꢁꢇ
–55°C
ꢔꢎꢐꢑꢎꢐꢕ ꢤꢆꢐꢜ
ꢔꢐꢜꢒꢖ
ꢜ
ꢛ
ꢝ ꢌꢍꢖ5ꢛ
ꢌꢍ95
ꢌꢍ9ꢗ
ꢌꢍꢕ5
ꢌꢍꢕꢗ
ꢌꢍ75
ꢜ
ꢙꢜꢠꢘꢘꢒꢏ ꢔꢦꢦ
ꢛ
ꢝ ꢌꢍꢌꢛ
25°C
125°C
ꢜ
ꢛ
ꢝ ꢌꢍꢘ5ꢛ
ꢒꢘꢠꢢꢏꢒꢣ ꢔꢎꢐꢑꢎꢐꢕ ꢤꢆꢐꢜ
ꢔꢐꢜꢒꢖ ꢙꢜꢠꢘꢘꢒꢏ ꢔꢘ
ꢈꢉꢁꢇ
ꢁꢇ
ꢕꢅ
10dBm INPUT
6957ꢊꢀꢈꢋ ꢌꢀ5
FILTA = FILTB = L
ꢀꢁꢂꢃꢄꢅꢆꢇ
ꢅꢓꢞ ꢐꢓꢁ ꢇꢘꢊ ꢐꢆꢀꢃꢆꢀ
ꢎꢏꢐꢄꢀꢁꢟ ꢀꢐ ꢚꢄꢐꢆꢓꢟ
R
LOAD
= 100Ω
ꢍꢎꢏꢐꢆꢑꢏꢒ ꢒꢓꢑꢔꢕꢎꢖꢒꢕꢗ ꢑꢒꢖꢕꢆꢕꢐꢒꢘꢙꢒ ꢍꢔꢅꢒ
ꢙꢏꢔꢙꢚ ꢆꢄꢔ ꢛ ꢊꢀꢁꢍꢜꢝ
ꢕꢅ ꢅꢖꢆꢇꢒ ꢞ ꢊꢋꢁꢟꢜꢝꢗ ꢠꢕꢡꢘꢙꢜꢖꢔꢘꢔꢎꢕ
ꢋ55 ꢋꢌ5 ꢋꢘ5
5
ꢙ5 ꢖ5 65 ꢕ5 ꢘꢗ5 ꢘꢙ5
0
200
400
600
800 1000 1200
ꢀꢁꢂꢃꢁꢄꢅꢀꢆꢄꢁ ꢇꢈꢉꢊ
FREQUENCY (MHz)
6957ꢘꢙꢌꢖ ꢚꢙ6
69571234 G27
6957fb
12
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
TYPICAL PERFORMANCE CHARACTERISTICS
LTC6957-2
Additive Phase Noise
vs Input Frequency
Additive Phase Noise
vs Amplitude
Additive Phase Noise
vs Temperature
ꢑꢏꢙꢐ
ꢑꢏꢚꢐ
ꢑꢏꢚ5
ꢑꢏꢙꢐ
ꢑꢏꢙ5
ꢑꢏ5ꢐ
ꢑꢏ55
ꢑꢏ6ꢐ
ꢑꢏ65
ꢑꢏꢚꢐ
ꢑꢏꢚ5
ꢑꢏꢙꢐ
ꢑꢏꢙ5
ꢑꢏ5ꢐ
ꢑꢏ55
ꢑꢏ6ꢐ
ꢑꢏ65
ꢂꢔꢈꢝꢠꢃꢡꢃꢈꢢꢃꢢ ꢂꢔꢈꢃ ꢣꢓꢤꢃ ꢔꢈꢒꢇꢄꢥ
ꢂꢔꢈꢝꢡꢃꢢꢃꢈꢣꢃꢣ ꢂꢔꢈꢃ ꢤꢓꢥꢃ ꢔꢈꢒꢇꢄ
ꢓꢄ 7ꢕꢖꢦ ꢋ5ꢐꢐꢦꢥ
ꢁꢔꢡꢄꢓ ꢧ ꢁꢔꢡꢄꢖ ꢧ ꢡ
ꢂꢔꢈꢝꢡꢃꢣꢃꢈꢤꢃꢤ ꢏꢐꢐꢞꢌꢍ ꢂꢔꢈꢃ ꢥꢓꢦꢃ ꢔꢈꢒꢇꢄ
ꢂꢃꢃ ꢓꢒꢒꢡꢔꢉꢓꢄꢔꢀꢈꢂ ꢔꢈꢁꢀꢅꢞꢓꢄꢔꢀꢈ
ꢏꢐꢐꢞꢌꢍ ꢓꢄ 7ꢕꢖꢦ ꢋ5ꢐꢐꢦꢤ
ꢁꢔꢠꢄꢓ ꢧ ꢁꢔꢠꢄꢖ ꢧ ꢠ
ꢎ
ꢅꢞꢂ
ꢎ
ꢑꢏꢙ5
ꢑꢏꢜꢐ
ꢑꢏꢜ5
ꢑꢏ5ꢐ
ꢑꢏ55
ꢑꢏ6ꢐ
ꢑꢏ65
ꢅꢟꢂ
ꢑꢏꢐꢕꢖꢟꢠ ꢁꢔꢡꢄꢓ ꢢ ꢡꢠ ꢁꢔꢡꢄꢖ ꢢ ꢌ
ꢐꢕꢖꢟꢠ ꢁꢔꢡꢄꢓ ꢢ ꢌꢠ ꢁꢔꢡꢄꢖ ꢢ ꢡ
ꢏ5ꢚꢠ6ꢟꢌꢍ
ꢚꢐꢐꢟꢌꢍ
ꢛ5ꢟꢉ
ꢏꢛ5ꢟꢉ
ꢑ55ꢟꢉ
ꢏꢐꢐꢟꢌꢍ
ꢏꢐꢕꢖꢟꢠ ꢁꢔꢡꢄꢓ ꢢ ꢁꢔꢡꢄꢖ ꢢ ꢡ
ꢏꢐꢐ
ꢏꢚ
ꢏꢐꢚ
ꢏꢐꢐꢚ
ꢏꢞ
ꢏꢐꢐ
ꢏꢛ
ꢏꢐꢛ
ꢏꢐꢐꢛ
ꢏꢟ
ꢏꢐꢐ
ꢏꢛ
ꢏꢐꢛ
ꢏꢐꢐꢛ
ꢏꢞ
ꢀꢁꢁꢂꢃꢄ ꢁꢅꢃꢆꢇꢃꢈꢉꢊ ꢋꢌꢍꢎ
ꢀꢁꢁꢂꢃꢄ ꢁꢅꢃꢆꢇꢃꢈꢉꢊ ꢋꢌꢍꢎ
ꢀꢁꢁꢂꢃꢄ ꢁꢅꢃꢆꢇꢃꢈꢉꢊ ꢋꢌꢍꢎ
6957ꢏꢛꢙꢜ ꢝꢙꢐ
6957ꢏꢜꢚꢙ ꢝꢜꢞ
6957ꢏꢜꢚꢙ ꢝꢜ9
Additive Phase Noise
vs Supply Voltage
Additive Phase Noise at 122.88MHz
AM to PM Conversion
ꢑꢏꢙꢐ
ꢑꢏꢙ5
ꢑꢏꢜꢐ
ꢑꢏꢜ5
ꢑꢏ5ꢐ
ꢑꢏ55
ꢑꢏ6ꢐ
ꢑꢏ65
ꢑꢏꢚꢐ
ꢑꢏꢚ5
ꢑꢏꢙꢐ
ꢑꢏꢙ5
ꢑꢏ5ꢐ
ꢑꢏ55
ꢑꢏ6ꢐ
ꢑꢏ65
5
ꢙ
ꢂꢔꢈꢝꢡꢃꢢꢃꢈꢣꢃꢣ ꢂꢔꢈꢃ ꢤꢓꢠꢃ ꢔꢈꢒꢇꢄꢥ
ꢂꢔꢈꢝꢡꢃꢣꢃꢈꢤꢃꢤ ꢂꢔꢈꢃ ꢥꢓꢦꢃ ꢔꢈꢒꢇꢄ
f
ꢟ ꢛꢑꢑꢆꢕꢠ
ꢟ ꢛꢢꢛꢞ
ꢀꢁ
ꢡ
ꢏꢐꢐꢞꢌꢍ ꢓꢄ 7ꢕꢖꢦ ꢋ5ꢐꢐꢦꢠ
ꢁꢔꢡꢄꢓ ꢧ ꢁꢔꢡꢄꢖ ꢧ ꢡ
ꢎ
ꢞ
ꢅꢞꢂ
ꢛ
ꢚ
ꢐ
ꢙꢟꢜ5ꢠ
ꢏ55ꢜꢝ
ꢑ
ꢏꢐ
ꢏꢚ
ꢏꢛ
ꢏꢙ
ꢏ5
ꢚ5ꢜꢝ
ꢐꢕꢖꢟꢠ ꢁꢔꢡꢄꢓ ꢢ ꢌꢠ ꢁꢔꢡꢄꢖ ꢢ ꢡ
7ꢕꢖꢟꢠ ꢁꢔꢡꢄꢓ ꢢ ꢁꢔꢡꢄꢖ ꢢ ꢡ
ꢙꢟꢙꢠ
ꢙꢟꢏ5ꢠ
ꢐꢚ5ꢜꢝ
ꢉꢅꢝꢕ ꢝꢃꢓꢞꢉ ꢁꢒꢓꢆꢅꢇꢀꢔꢉꢈ ꢄꢒ ꢑꢜ ꢅꢄ ꢑꢋꢌꢍ
ꢏꢐꢑ ꢏꢘ ꢏ6 ꢏꢙ ꢏꢚ
ꢀꢁꢂꢃꢄ ꢅꢆꢂꢇꢀꢄꢃꢈꢉ ꢊꢋꢌꢍꢎ
ꢏꢐꢐ
ꢏꢚ
ꢏꢐꢚ
ꢏꢐꢐꢚ
ꢏꢞ
ꢏꢐꢐ
ꢏꢛ
ꢏꢐꢛ
ꢏꢐꢐꢛ
ꢏꢞ
ꢑ
ꢚ
ꢙ
6
ꢘ
ꢐꢑ
ꢀꢁꢁꢂꢃꢄ ꢁꢅꢃꢆꢇꢃꢈꢉꢊ ꢋꢌꢍꢎ
ꢀꢁꢁꢂꢃꢄ ꢁꢅꢃꢆꢇꢃꢈꢉꢊ ꢋꢌꢍꢎ
6957ꢏꢛꢙꢜ ꢝꢙꢏ
6957ꢏꢜꢚꢙ ꢝꢚꢜ
6957ꢐꢚꢛꢙ ꢗꢛꢛ
tPD vs Temperature
tPD vs Temperature
tPD vs Supply Voltage
0.96
0.94
0.92
0.90
0.88
0.86
0.84
4.0
3.0
1.5
1.0
0.5
0.950
0.925
0.900
0.875
0.850
0.825
FILTA = FILTB = L
100Ω LOAD
FILTA = FILTB = H
+
V
= 3.0V
125°C
+
V
= 3.6V
25°C
FILTA = L, FILTB = H
+
V
= 3.3V
FILTA = H, FILTB = L
FILTA = FILTB = L
FILTA = FILTB = L
100Ω LOAD
–55°C
100Ω LOAD
3
3.1
3.2
3.3
3.4
3.5
3.6
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105
125
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
69571234 G36
69571234 G34
69571234 G35
6957fb
13
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
TYPICAL PERFORMANCE CHARACTERISTICS
LTC6957-3/LTC6957-4
Input Self Bias Voltage
vs Temperature
Supply Current vs Supply Voltage
Supply Current vs Temperature
ꢕꢍꢕꢎ
ꢕꢍꢌ5
ꢕꢍꢌꢎ
ꢕꢍꢎ5
ꢕꢍꢎꢎ
ꢌꢍ95
ꢌꢍ9ꢎ
ꢔ5
ꢔꢊ
ꢓ5
ꢓꢊ
5
ꢕꢌꢍ5
ꢕꢌꢍꢖ
ꢕꢖꢍ5
ꢕꢖꢍꢖ
ꢌ9ꢍ5
ꢙ
ꢑ
ꢚ ꢖꢍꢗ5ꢑ
ꢚ ꢖꢍꢖꢑ
ꢏ
ꢎ
ꢛ ꢗꢍꢘ5ꢎ
ꢙ
ꢑ
ꢔ5ꢚꢏ
ꢏ
ꢎ
ꢛ ꢗꢍꢗꢎ
ꢙ
ꢑ
ꢚ ꢖꢍꢌ5ꢑ
ꢓꢔ5ꢚꢏ
ꢏ
ꢎ
ꢛ ꢗꢍꢌ5ꢎ
ꢙ55ꢚꢏ
ꢔꢕꢗ
ꢊ
ꢋ55 ꢋꢖ5 ꢋꢌ5
5
ꢕ5 ꢗ5 65 ꢘ5 ꢌꢎ5 ꢌꢕ5
ꢀꢁꢂꢃꢁꢄꢅꢀꢆꢄꢁ ꢇꢈꢉꢊ
ꢊꢕ6
ꢘ
ꢋꢗ5
ꢕ5
ꢀꢁꢂꢃꢁꢄꢅꢀꢆꢄꢁ ꢇꢈꢉꢊ
ꢙ5 ꢌꢖ5
ꢌꢕ5
ꢊ
ꢓꢕꢔ
ꢓꢕꢖ
ꢘꢕ6
ꢋ55
ꢋꢌ5
5
ꢘ5 65
ꢁ
ꢀ
ꢀꢂꢃꢄꢅꢆꢇ ꢈꢀꢉ
6957ꢌꢕꢖꢗ ꢔꢖ7
6957ꢓꢔꢘꢗ ꢆꢘꢖ
6957ꢌꢕꢗꢘ ꢚꢗ9
Additive Phase Noise
vs Supply Voltage
Output Voltages vs Load Current
Output Voltages vs Load Current
ꢏ
ꢏ
ꢃꢃ
ꢃꢃ
ꢑꢏꢚꢐ
ꢑꢏꢚ5
ꢑꢏꢙꢐ
ꢑꢏꢙ5
ꢑꢏ5ꢐ
ꢑꢏ55
ꢑꢏ6ꢐ
ꢑꢏ65
ꢂꢔꢈꢝꢡꢃꢢꢃꢈꢣꢃꢣ ꢂꢔꢈꢃ ꢤꢓꢠꢃ ꢔꢈꢒꢇꢄꢥ
ꢏꢐꢐꢞꢌꢍ ꢦꢧ 7ꢕꢖꢨ ꢋ5ꢐꢐꢨꢠ
ꢁꢅꢉꢎꢅꢉ ꢜꢚꢐꢜꢘ
ꢙꢁꢅꢆꢄꢚꢈꢐ ꢄꢅꢆꢆꢇꢈꢉ
ꢎ
ꢅꢞꢂ
ꢓ55ꢝꢄ
ꢔꢒ5ꢝꢄ
ꢏ
ꢓꢍꢑꢒ5
ꢓꢍꢑ5
ꢏ
ꢓꢍꢑꢒ5
ꢓꢍꢑ5
ꢩ
ꢒ5ꢝꢄ
ꢃꢃ
ꢃꢃ
ꢠ
ꢪ ꢚꢟꢚꢠꢥ ꢠ ꢓꢂ ꢂꢌꢀꢤꢈ
ꢣꢣ
ꢁꢅꢉꢎꢅꢉ ꢜꢚꢐꢜꢘ
ꢙꢁꢅꢆꢄꢚꢈꢐ ꢄꢅꢆꢆꢇꢈꢉ
ꢁꢔꢡꢄꢓ ꢪ ꢁꢔꢡꢄꢖ ꢪ ꢡ
ꢏ
ꢏ
ꢃꢃ
ꢃꢃ
ꢏ
ꢃꢃ
ꢏ
ꢃꢃ
ꢏ
ꢃꢃ
ꢏ
ꢃꢃ
ꢏ
ꢃꢃ
ꢝ ꢕꢑ6ꢏ
ꢝ ꢕꢑꢕꢏ
ꢝ ꢕꢏ
ꢝ ꢒꢑ7ꢏ
ꢝ ꢒꢑꢖꢏ
ꢜꢟꢙꢠ
ꢏ
ꢓꢍꢑ75
ꢍꢑ5ꢍ
ꢍꢑꢒ5
ꢍ
ꢏ
ꢓꢍꢑ75
ꢍꢑ5ꢍ
ꢍꢑꢒ5
ꢍ
ꢏ
ꢞ ꢕꢑꢕꢏ
ꢃꢃ
ꢃꢃ
ꢃꢃ
ꢜꢟ7ꢠ
ꢔꢒ5ꢝꢄ
ꢓ55ꢝꢄ
ꢁꢅꢉꢎꢅꢉ ꢀꢁꢗꢘ
ꢙꢚꢈꢛꢚꢈꢐ ꢄꢅꢆꢆꢇꢈꢉ
ꢚꢟꢐꢠ
ꢚꢟꢚꢠ
ꢒ5ꢝꢄ
ꢁꢅꢉꢎꢅꢉ ꢀꢁꢗꢘ
ꢙꢚꢈꢛꢚꢈꢐ ꢄꢅꢆꢆꢇꢈꢉ
ꢍ
5
ꢔꢍ
ꢔ5
ꢒꢍ
ꢍ
5
ꢔꢍ
ꢔ5
ꢒꢍ
ꢏꢐꢐ
ꢏꢛ
ꢏꢐꢛ
ꢏꢐꢐꢛ
ꢏꢞ
ꢀꢁꢂꢃ ꢄꢅꢆꢆꢇꢈꢉ ꢊꢋꢂꢌ
ꢀꢁꢂꢃ ꢄꢅꢆꢆꢇꢈꢉ ꢊꢋꢂꢌ
ꢀꢁꢁꢂꢃꢄ ꢁꢅꢃꢆꢇꢃꢈꢉꢊ ꢋꢌꢍꢎ
6957ꢔꢒꢕꢖ ꢐꢖꢍ
6957ꢔꢒꢕꢖ ꢐꢖꢔ
6957ꢏꢜꢚꢙ ꢝꢙꢜ
Output Voltage Swing
vs Frequency
Supply Current vs Supply Voltage
Supply Current vs Temperature
3.0
2.5
2.0
1.5
1
5
ꢖꢌ
ꢖꢘ
ꢌ9
ꢌꢕ
ꢌ7
ꢌꢘꢘ
ꢌꢘ
ꢥ
ꢍ
ꢦ ꢍ ꢦ ꢗꢛꢗꢍ
ꢎꢎ
125°C
ꢕ
ꢑ
ꢓ
ꢐ
ꢊ
–55°C
25°C
CAUTION: AT VERY
HIGH FREQUENCIES,
THE CMOS OUTPUTS
MAY NOT TOGGLE
AT ALL DEPENDING
ON INPUT FREQ-
UENCY, AMPLITUDE,
SUPPLY VOLTAGE,
OR TEMPERATURE
ꢎꢑꢒꢅꢂꢜꢉꢝ ꢞꢒꢁ ꢇꢌꢊ
ꢞꢆꢀꢃꢆꢀ ꢅꢉꢀꢜꢍꢁ ꢅꢀ ꢗꢌꢖꢛ5ꢂꢟꢠꢝ
ꢌꢗꢡꢢ ꢐꢞꢅꢎꢝ ꢐꢁꢢꢀ ꢅꢣꢜꢏ
ꢌ
ꢞꢀꢟꢁꢄ ꢞꢆꢀꢃꢆꢀ ꢎꢜꢏꢅꢤꢐꢁꢎ
10dBm INPUT
FILTA = FILTB = L
IN DC1766A
ꢘꢛꢌ
ꢘꢛꢘꢌ
ꢗ55ꢖꢋ
ꢓ5ꢖꢋ
ꢏꢀꢅꢀꢜꢉꢝ ꢒꢞ ꢎꢉ ꢐꢞꢅꢎꢝ
ꢄꢜꢚꢟꢀ ꢇꢐꢞꢚꢅꢄꢜꢀꢟꢂꢜꢉꢊ
ꢅꢣꢜꢏ
ꢐꢓ5ꢖꢋ
R
LOAD
= 133Ω AC-COUPLED
0
100 200 300 400 500 600 700 800 9001000
FREQUENCY (MHz)
ꢊ
ꢊꢒ6
ꢐꢒꢓ
ꢀ
ꢐꢒꢔ
ꢓꢒꢕ
ꢑ
ꢑꢒ6
ꢋ55 ꢋꢗ5 ꢋꢌ5
5
ꢖ5 ꢙ5 65 ꢕ5 ꢌꢘ5 ꢌꢖ5
ꢀꢂꢃꢄꢅꢆꢇ ꢈꢀꢉ
ꢀꢁꢂꢃꢁꢄꢅꢀꢆꢄꢁ ꢇꢈꢉꢊ
ꢁꢁ
69571234 G45
6957ꢐꢓꢑꢕ ꢆꢕꢑ
6957ꢌꢖꢗꢙ ꢚꢙꢙ
6957fb
14
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
TYPICAL PERFORMANCE CHARACTERISTICS
LTC6957-3/LTC6957-4
Additive Phase Noise
vs Input Frequency
Additive Phase Noise
vs Amplitude
Additive Phase Noise
vs Temperature
ꢑꢏꢙꢐ
ꢑꢏꢚꢐ
ꢑꢏꢚ5
ꢑꢏꢙꢐ
ꢑꢏꢙ5
ꢑꢏ5ꢐ
ꢑꢏ55
ꢑꢏ6ꢐ
ꢑꢏ65
ꢑꢏꢚꢐ
ꢑꢏꢚ5
ꢑꢏꢙꢐ
ꢑꢏꢙ5
ꢑꢏ5ꢐ
ꢑꢏ55
ꢑꢏ6ꢐ
ꢑꢏ65
ꢂꢔꢈꢝꢡꢃꢣꢃꢈꢤꢃꢤ ꢏꢐꢐꢞꢌꢍ ꢂꢔꢈꢃ ꢥꢓꢦꢃ ꢔꢈꢒꢇꢄ
ꢂꢃꢃ ꢓꢒꢒꢡꢔꢉꢓꢄꢔꢀꢈꢂ ꢔꢈꢁꢀꢅꢞꢓꢄꢔꢀꢈ
ꢂꢔꢈꢝꢡꢃꢢꢃꢈꢣꢃꢣ ꢂꢔꢈꢃ ꢤꢓꢥꢃ ꢔꢈꢒꢇꢄꢦ
ꢂꢔꢈꢝꢟꢃꢠꢃꢈꢡꢃꢡ ꢂꢔꢈꢃ ꢢꢓꢣꢃ ꢔꢈꢒꢇꢄ
ꢓꢄ 7ꢕꢖꢤ ꢋ5ꢐꢐꢤꢣ
ꢁꢔꢟꢄꢓ ꢥ ꢁꢔꢟꢄꢖ ꢥ ꢟ
ꢏꢐꢐꢟꢌꢍ ꢓꢄ 7ꢕꢖꢧ ꢋ5ꢐꢐꢧꢥ
ꢁꢔꢡꢄꢓ ꢨ ꢁꢔꢡꢄꢖ ꢨ ꢡ
ꢎ
ꢎ
ꢅꢟꢂ
ꢅꢞꢂ
ꢑꢏꢙ5
ꢑꢏꢜꢐ
ꢑꢏꢜ5
ꢑꢏ5ꢐ
ꢑꢏ55
ꢑꢏ6ꢐ
ꢑꢏ65
ꢚꢐꢐꢞꢌꢍ
ꢑꢏꢐꢕꢖꢟꢠ ꢁꢔꢡꢄꢓ ꢢ ꢡꢠ ꢁꢔꢡꢄꢖ ꢢ ꢌ
ꢐꢕꢖꢟꢠ ꢁꢔꢡꢄꢓ ꢢ ꢌꢠ ꢁꢔꢡꢄꢖ ꢢ ꢡ
ꢏ5ꢚꢦ6ꢞꢌꢍ
ꢛ5ꢠꢉ
ꢏꢐꢐꢞꢌꢍ
ꢏꢛ5ꢠꢉ
ꢑ55ꢠꢉ
ꢏꢐꢕꢖꢟꢠ ꢁꢔꢡꢄꢓ ꢢ ꢁꢔꢡꢄꢖ ꢢ ꢡ
ꢏꢐꢐ
ꢏꢛ
ꢏꢐꢛ
ꢏꢐꢐꢛ
ꢏꢞ
ꢏꢐꢐ
ꢏꢚ
ꢏꢐꢚ
ꢏꢐꢐꢚ
ꢏꢟ
ꢏꢐꢐ
ꢏꢛ
ꢏꢐꢛ
ꢏꢐꢐꢛ
ꢏꢞ
ꢀꢁꢁꢂꢃꢄ ꢁꢅꢃꢆꢇꢃꢈꢉꢊ ꢋꢌꢍꢎ
ꢀꢁꢁꢂꢃꢄ ꢁꢅꢃꢆꢇꢃꢈꢉꢊ ꢋꢌꢍꢎ
ꢀꢁꢁꢂꢃꢄ ꢁꢅꢃꢆꢇꢃꢈꢉꢊ ꢋꢌꢍꢎ
6957ꢏꢜꢚꢙ ꢝꢙ7
6957ꢏꢛꢙꢜ ꢝꢜꢞ
6957ꢏꢜꢚꢙ ꢝꢙ6
Additive Phase Noise
vs Supply Voltage
Additive Phase Noise at 122.88MHz
AM to PM Conversion
ꢑꢏꢙꢐ
ꢑꢏꢙ5
ꢑꢏꢜꢐ
ꢑꢏꢜ5
ꢑꢏ5ꢐ
ꢑꢏ55
ꢑꢏ6ꢐ
ꢑꢏ65
ꢑꢏꢚꢐ
ꢑꢏꢚ5
ꢑꢏꢙꢐ
ꢑꢏꢙ5
ꢑꢏ5ꢐ
ꢑꢏ55
ꢑꢏ6ꢐ
ꢑꢏ65
5
ꢙ
ꢉꢅꢝꢕ ꢝꢃꢓꢞꢉ ꢁꢒꢓꢆꢅꢇꢀꢔꢉꢈ ꢄꢒ ꢑꢜ ꢅꢄ ꢑꢋꢌꢍ
ꢂꢔꢈꢝꢡꢃꢢꢃꢈꢣꢃꢣ ꢂꢔꢈꢃ ꢤꢓꢠꢃ ꢔꢈꢒꢇꢄꢥ
ꢂꢔꢈꢝꢡꢃꢣꢃꢈꢤꢃꢤ ꢂꢔꢈꢃ ꢥꢓꢦꢃ ꢔꢈꢒꢇꢄ
f
ꢟ ꢛꢑꢑꢆꢕꢠ
ꢏꢐꢐꢞꢌꢍ ꢓꢄ 7ꢕꢖꢦ ꢋ5ꢐꢐꢦꢠ
ꢎ
ꢀꢁ
ꢅꢞꢂ
ꢡ
ꢧ
ꢞ ꢟ ꢞ ꢟ ꢛꢢꢛꢞ
ꢈꢈ
ꢠ
ꢨ ꢠ
ꢣꢣ
ꢛ
ꢁꢔꢡꢄꢓ ꢨ ꢁꢔꢡꢄꢖ ꢨ ꢡ
ꢚ
ꢐ
ꢑ
ꢙꢟꢏ5ꢠ
ꢐꢕꢖꢟꢠ ꢁꢔꢡꢄꢓ ꢢ ꢌꢠ ꢁꢔꢡꢄꢖ ꢢ ꢡ
ꢏ55ꢜꢝ
ꢏꢐ
ꢏꢚ
ꢏꢛ
ꢏꢙ
ꢏ5
ꢙꢟꢜ5ꢠ
ꢏꢐꢐꢚ
ꢚ5ꢜꢝ
ꢐꢚ5ꢜꢝ
7ꢕꢖꢟꢠ ꢁꢔꢡꢄꢓ ꢢ ꢁꢔꢡꢄꢖ ꢢ ꢡ
ꢙꢟꢙꢠ
ꢏꢐꢐ
ꢏꢚ
ꢏꢐꢚ
ꢏꢞ
ꢏꢐꢐ
ꢏꢛ
ꢏꢐꢛ
ꢏꢐꢐꢛ
ꢏꢞ
ꢏꢐꢑ ꢏꢘ ꢏ6 ꢏꢙ ꢏꢚ
ꢑ
ꢚ
ꢙ
6
ꢘ
ꢐꢑ
ꢀꢁꢁꢂꢃꢄ ꢁꢅꢃꢆꢇꢃꢈꢉꢊ ꢋꢌꢍꢎ
ꢀꢁꢁꢂꢃꢄ ꢁꢅꢃꢆꢇꢃꢈꢉꢊ ꢋꢌꢍꢎ
ꢀꢁꢂꢃꢄ ꢅꢆꢂꢇꢀꢄꢃꢈꢉ ꢊꢋꢌꢍꢎ
6957ꢏꢛꢙꢜ ꢝꢜ9
6957ꢏꢜꢚꢙ ꢝ5ꢐ
6957ꢐꢚꢛꢙ ꢗ5ꢐ
tPD vs Temperature
tPD vs Temperature
tPD vs Supply Voltage
ꢒꢍꢌ
ꢓꢍꢌ
ꢔꢍ5
ꢔꢍꢌ
ꢌꢍ5
ꢒꢍꢒ5
ꢒꢍꢒꢌ
ꢒꢍꢌ5
ꢒꢍꢌꢌ
ꢌꢍ95
ꢌꢍ9ꢌ
ꢌꢍꢔ5
ꢌꢍꢔꢌ
ꢌꢍ75
ꢕꢏꢑ6
ꢕꢏꢑꢐ
ꢕꢏꢑꢎ
ꢕꢏꢑꢑ
ꢑꢏ9ꢗ
ꢑꢏ96
ꢑꢏ9ꢐ
ꢘꢙꢚꢀꢅ ꢛ ꢘꢙꢚꢀꢜ ꢛ ꢞ
ꢘ
ꢀ
ꢙ ꢖꢏꢐ5ꢀ
ꢄꢚꢜꢚꢛꢗ ꢁꢏꢗꢁ
ꢘꢙꢚꢀꢅ ꢛ ꢚꢝ ꢘꢙꢚꢀꢜ ꢛ ꢞ
ꢘꢙꢚꢀꢅ ꢛ ꢞꢝ ꢘꢙꢚꢀꢜ ꢛ ꢚ
ꢘ
ꢀ
ꢙ ꢀ
ꢁꢁ
ꢘꢅꢙꢙꢚꢛꢗ ꢁꢏꢗꢁ
ꢘꢙꢚꢀꢅ ꢛ ꢘꢙꢚꢀꢜ ꢛ ꢚ
ꢚꢛꢂꢛꢜꢊ ꢋꢁꢊꢋ
ꢎꢏꢐ ꢎꢏ55 ꢎꢏ7 ꢎꢏꢗ5
ꢂꢃꢄꢄꢅꢆ ꢀꢇꢅꢈꢉꢊꢋ ꢌꢀꢍ
ꢘꢚꢙꢀꢅ ꢝ ꢘꢚꢙꢀꢞ ꢝ ꢙ
ꢖ5 ꢕ5 65 ꢔ5 ꢒꢌ5 ꢒꢖ5
ꢀꢁꢂꢃꢁꢄꢅꢀꢆꢄꢁ ꢇꢈꢉꢊ
ꢘꢅꢚꢚꢙꢟꢗ ꢁꢏꢗꢁ
ꢋ55 ꢋꢓ5 ꢋꢔ5
5
ꢖ5 ꢒ5 65 ꢕ5 ꢔꢌ5 ꢔꢖ5
ꢋ55 ꢋꢓ5 ꢋꢒ5
5
ꢖ
ꢖꢏꢕ5 ꢖꢏꢖ ꢖꢏꢐ5 ꢖꢏ6
ꢀꢁꢂꢃꢁꢄꢅꢀꢆꢄꢁ ꢇꢈꢉꢊ
ꢀ
ꢁꢁ
6957ꢔꢖꢓꢒ ꢗ5ꢖ
6957ꢒꢖꢓꢕ ꢗ5ꢓ
6957ꢕꢎꢖꢐ ꢊ5ꢐ
6957fb
15
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
PIN FUNCTIONS
FILTA, FILTB (Pin 1, Pin 6): Input Bandwidth Limiting
Control. These CMOS logic inputs control the bandwidth
of the early amplifier stages. For slow slewing signals
substantially lower phase noise is achieved by using this
feature. See the Applications Information section for more
details.
LTC6957-2 Only
–
+
OUT1 , OUT1 (Pin 10, Pin 11): LVDS Outputs, Mostly
TIA/EIA-644-A Compliant. Refer to the Applications
Information section for more details.
OUT2–, OUT2+ (Pin 9, Pin 8): LVDS Outputs, Mostly
TIA/EIA-644-A Compliant. Refer to the Applications
Information section for more details.
+
V (Pin 2): Supply Voltage (3.15V to 3.45V). This sup-
ply must be kept free from noise and ripple. It should be
bypassed directly to GND (Pin 5) with a 0.1µF capacitor.
LTC6957-3/LTC6957-4 Only
+
–
IN , IN (Pin 3, Pin 4): Input Signal Pins. These inputs
are differential, but can also interface with single-ended
signals. The input can be a sine wave signal or a CML,
LVPECL, TTL or CMOS logic signal. See the Applications
Information section for more details.
OUT1, OUT2 (Pin 10, Pin 9): CMOS Outputs. Refer to the
Applications Information section for more details.
V
(Pin 11): Output Supply Voltage (2.4V to 3.45V). For
DD
+
best performance connect this to the same supply as V
(Pin 2). If the output needs to be a lower logic rail, this
supply can be separately connected, but this voltage must
be less than or equal to that on Pin 2 for proper operation.
This supply must also be kept free from noise and ripple.
It should be bypassed directly to the GNDOUT pin (Pin 8)
with a 0.1µF capacitor.
GND (Pin 5): Ground. Connect to a low inductance ground
plane for best performance. The connection to the bypass
+
capacitor for V (Pin 2) should be through a direct, low
inductance path.
SD1, SD2 (Pin 12, Pin 7): Output Enable Control. These
CMOS logic inputs control the enabling and disabling of
their respective OUT1 and OUT2 outputs. When both out-
puts are disabled, the LTC6957 is placed in a low power
shutdown state.
GNDOUT (Pin 8): Output Logic Ground. Tie to a low
inductance ground plane for best performance. The con-
nection to the bypass capacitor for V (Pin 11) should
DD
be through a direct, low inductance path.
LTC6957-1 Only
LTC6957-xDD Only
OUT1–,OUT1+(Pin10,Pin11):LVPECLOutputs.Differential
Exposed Pad (Pin 13): Always tie the underlying DFN
logic outputs typically terminated by 50Ω connected to a
exposed pad to GND (Pin 5). To achieve the rated θ of
JA
+
supply 2V below the V supply. Refer to the Applications
the DD package, there should be good thermal contact
Information section for more details.
to the PCB.
OUT2–, OUT2+ (Pin 9, Pin 8): LVPECL Outputs. Differential
logic outputs typically terminated by 50Ω connected to a
+
supply 2V below the V supply. Refer to the Applications
Information section for more details.
6957fb
16
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LTC6957-3/LTC6957-4
BLOCK DIAGRAMS
ꢌ
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ꢂꢃꢄꢅꢀ
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6
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ꢉꢉ
ꢉꢑ
ꢋ
ꢇꢈꢅꢉ
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ꢇꢈꢅꢌ
9
ꢒ
ꢐꢍꢁ
ꢎꢁꢌ
5
7
LTC6957-1 and LTC6957-2
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ꢂꢃꢄꢅꢀ
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6
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9
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6957 ꢀꢁ
5
7
LTC6957-3 and LTC6957-4
6957fb
17
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LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
TIMING DIAGRAM
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6957 ꢀꢁꢂ
6957fb
18
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
APPLICATIONS INFORMATION
General Considerations
in the timing before the system performance is degraded.
Users are encouraged to keep this distinction in mind
while designing the entire clocking signal chain before,
during, and after the LTC6957.
The LTC6957-1/LTC6957-2/LTC6957-3/LTC6957-4 are
low noise, dual output clock buffers that are designed
for demanding, low phase noise applications. Properly
applied, they can preserve phase noise performance in
situations where alternative solutions would degrade the
phase noise significantly. They are also useful as logic
converters.
Input Interfacing
The input stage is the same for all versions of the LTC6957
and is designed for low noise and ease of interfacing to
sine-wave and small amplitude signals. Other logic types
can interface directly, or with little effort since they pres-
ent a smaller challenge for noise preservation.
However, no buffer device is capable of removing or
reducing phase noise present on an input signal. As with
most low phase noise circuits, improper application of
the LTC6957-1/LTC6957-2/LTC6957-3/LTC6957-4 can
result in an increase in the phase noise through a variety
of mechanisms. The information below will, hopefully,
allow a designer to avoid such an outcome.
Figure 1 shows a simplified schematic of the LTC6957
input stage. The diodes are all for protection, both during
ESD events and to protect the low noise NPN devices from
being damaged by input overdrive.
The resistors are to bias the input stage at an optimal
DC level, but they are too large to leave floating without
increasing the noise. Therefore, for low noise use, always
connect both inputs to a low AC impedance. A capacitor to
ground/return is imperative on the unused input in single-
ended applications.
The LTC6957 is designed to be used with high perfor-
mance clock signals destined for driving the encode
inputs of ADCs or mixer inputs. Such clocks should not
be treated as digital signals. The beauty of digital logic is
that there is noise margin both in the voltage and the tim-
ing, before any deleterious effects are noticed. In contrast,
high performance clock signals have no margin for error
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ꢋ
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ꢀꢃꢄꢅꢇ
6
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ꢂꢎꢒꢐ
ꢉ
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ꢑ
ꢊ
ꢃꢈ
ꢔ
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ꢒꢓꢆ
ꢑꢎꢒꢐ
ꢌꢈꢍ
5
6957 ꢀꢁꢂ
Figure 1
6957fb
19
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LTC6957-3/LTC6957-4
APPLICATIONS INFORMATION
Figure 2a shows how to interface single-ended LVPECL
logic to the LTC6957, while Figure 2b shows how to drive
the LTC6957 with differential LVPECL signals. The capaci-
tors shown are 10nF and can be inexpensive ceramics,
preferably in small SMT cases. For use above 100MHz,
lower value capacitors may be desired to avoid series
resonance, which could increase the noise in Figure 2a
even though the capacitor is just on the DC input. This
comment applies to all capacitors hooked to the inputs
throughout this data sheet.
In Figure 2b, both inputs to the LTC6957 are driven,
increasing the differential input signal size and minimiz-
ing noise from any common mode source such as V ,
TT
both of which improve the achievable phase noise.
A variety of termination techniques can be used, and
as long as the two sides use the same termination, the
configuration used won't matter much. In Figure 2b, the
RTERMs are shown in a "Y" configuration that creates a pas-
sive V at the common point. Most 3.3V LVPECL devices
TT
have differential outputs and can be terminated with three
50Ω resistors as shown.
In Figure 2a, the R
implementation is up to the user
TERM
and is to terminate the transmission line. If it is connected
Figure 3 shows a 50Ω RF signal source interface to the
LTC6957. For a pure tone (sine wave) input, Figure 3 can
handle up to 10dBm maximum. A broadband 50Ω match
as shown should suffice for most applications, though
for small amplitude input signals a narrow band reactive
matching network may offer incremental improvements
in performance.
to a V that is passively generated and heavily bypassed
TT
to ground, the 10nF to ground shown on the inverting
LTC6957 input is the appropriate connection to use.
However, if the termination goes to an actively generated
V
voltage, lower noise may be achieved by connecting
TT
the capacitor on the inverting input to that V rather than
TT
ground.
ꢎꢏꢎꢐ
10nF
50Ω
+
LTC6957
50Ω
–
ꢋ
6957 F03
10nF
SOURCE
ꢌꢇꢍ6957
ꢆ
ꢇꢈꢆꢉ
ꢊ
6957 ꢀꢁꢂꢃ
ꢄꢁꢅꢀ
Figure 3. Single-Ended 50Ω Input Source
Figure 2a. Single-Ended LVPECL Input
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ꢌꢇꢍ6957
ꢊ
6957 ꢀꢁꢂb
ꢎꢑ
ꢆ
ꢇꢈꢆꢉ
Figure 2b. Differential LVPECL Input
Figure 2
6957fb
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LTC6957-3/LTC6957-4
APPLICATIONS INFORMATION
Figure 4 shows the interface between current mode logic
(CML) signals and the LTC6957 inputs. The specifics of
terminating will be dependent on the particular CML driver
used; Figure 4 shows terminations only at the load end
of the line, but the same LTC6957 interface is appropri-
ate for applications with the source end of the line also
terminated. In Figure 4a, a differential signal interface to
the LTC6957 is shown, which must be AC-coupled due to
the DC input levels required at the LTC6957.
Figure 4b shows a single-ended CML signal driving the
LTC6957. This is not commonly used because of noise
and immunity weaknesses compared to the differen-
tial CML case. Because the signal is created by a cur-
rent pulled through the termination resistor, the signal
is inherently referenced to the supply voltage to which
R
is tied. For that reason, the other LTC6957 should
TERM
be AC-referenced to that supply voltage as shown.
The polarity change shown here is for graphic clarity only,
and can be reversed by swapping the LTC6957 input
terminals.
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ꢄ
ꢅꢆꢄꢇ
ꢌꢁꢍꢀ
ꢌꢁꢍꢀ
ꢉ
ꢈ
ꢊꢅꢋ6957
6957 ꢀꢁꢂꢃ
Figure 4a. Differential CML Input
ꢌꢁꢍꢀ
ꢉ
ꢄ
ꢊꢅꢋ6957
ꢅꢆꢄꢇ ꢌꢁꢍꢀ
ꢈ
6957 ꢀꢁꢂb
Figure 4b. Single-Ended CML Input
Figure 4
6957fb
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LTC6957-3/LTC6957-4
APPLICATIONS INFORMATION
Figure 5 shows the LTC6957 being driven by an LVDS
(EIA-644-A) signal pair. This is simply a matter of differ-
entially terminating the pair and AC-coupling as shown
into the LTC6957 whose DC common mode voltage is
incompatible with the LVDS standard.
CMOS on the other hand cannot drive 50Ω loads, is usu-
ally routed single-ended, and by its nature is coupled to
the potentially noisy supply voltage half the time.
The LTC6957-3/LTC6957-4 provide CMOS outputs, so it
may seem surprising to read herein that CMOS is a poor
choice for low phase noise applications. However, these
devices should prove useful for designers that recognize
the challenges and limitations of using CMOS signals for
low phase noise applications. See the CMOS Outputs of
the LTC6957-3/LTC6957-4 section for further information.
10nF
+
110Ω
LTC6957
10nF
–
6957 F05
The best method for driving the LTC6957 with CMOS sig-
nals would be to provide differential drive, but if that is not
available, there are few ways to create a differential CMOS
signal without running the risk of corrupting the skew or
creating other problems. Therefore, single-ended CMOS
signals are the norm and care must be taken when using
this to drive the LTC6957.
Figure 5. LVDS Input
The choice of 110Ω versus 100Ω termination is arbitrary
(the EIA-644-A standard allows 90Ω to 132Ω) and should
be made to match the differential impedance of the trace
pair. The termination and AC-coupling elements should be
located as close as possible to the LTC6957.
If DC-coupling is desired, for example to control the
LTC6957 output phasing during times the LVDS input
clocks will be halted, a pair of 3k resistors can parallel
the two capacitors in Figure 5. An EIA/TIA-644-A compli-
ant driver can drive this load, which is less load stress
than specification 4.1.1. The differential voltage into the
LTC6957 when clocked (>100kHz) will be full LVDS levels.
When the clocks stop, the DC differential voltage created
by the resistors and the 1.2k internal resistors (Figure
1) will be 100mV, still sufficient to assure the desired
LTC6957 output polarity. Choosing the smallest capaci-
tors needed for phase noise performance will minimize
the settling transients when the clocks restart.
The primary concern is that all routing should be termi-
nated to minimize reflections. With CMOS logic there is
usually plenty of signal (more than the LTC6957 can han-
dle without attenuation) and the amplitude of the LTC6957
input signal will generally be of secondary importance
compared to avoiding the deleterious effects of signal
reflections. The primary concern about terminations is
that the input waveform presented to the LTC6957 should
have full speed slewing at the all important transitions.
If a rising edge is slowed by the destructive addition of
the ringing/settling of a prior edge reflection, or even the
start of the current edge, the phase noise performance will
suffer. This is true for all logic types, but is particularly
problematic when using CMOS because of the fast slew
rates and because it does not naturally lend itself to clean
terminations.
Interfacing with CMOS Logic
The logic families discussed and illustrated to this point
are generally a better choice for routing and distributing
low phase-noise reference/clock signals than is CMOS
logic. All of the logic types shown so far are well suited
for use with low impedance terminations. Most of the time
there is a differential signal when using LVPECL or CML,
and LVDS always has a differential signal. Differential
signals provide lots of margin for error when it comes
to picking up noise and interference that can corrupt a
reference clock.
Point-to-point routing is best, and care should be taken
to avoid daisy-chain routing, because the terminated
end may be the only point along the line that sees clean
transitions. Earlier loads may even see a dwell in the
transition region which will greatly degrade phase noise
performance.
6957fb
22
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LTC6957-3/LTC6957-4
APPLICATIONS INFORMATION
Figure 6 shows a suggested CMOS to LTC6957 interface.
The transmission line shown is the PCB trace and the
component values are for a characteristic impedance of
50Ω, though they could be scaled up or down for other
values of Z0. The R1/R2 divider at the CMOS output cuts
phase noise spectrum related to the other signals pro-
cessed in the driver.
Input Resistors
The LTC6957 input resistors, seen in Figure 1, are present
at all times, including during shutdown. Although they
constitute a large portion of the shutdown current, this
behavior prevents the shutdown and wake-up cycling of
the LTC6957 from “kicking back” into prior stages, which
could create large transients that could take a while to
settle. Particularly in the common case of AC-coupling
where the coupling cap charge is preserved.
the Thevenin voltage in half when the Z
of the driver is
OUT
included. More importantly, it drives the transmission line
with a Thevenin driving resistance of 50Ω, matching the
Z0 of the line. On the other end of the line, a 50Ω load is
presented, minimizing reflections. This results in a second
2:1 attenuation in voltage, so the LTC6957 input will be
approximately 800mVP-P with 3V CMOS; 1.25VP-P with 5V
and 600mV with 2.5V. All of these levels are less than
P-P
the maximum input swing of 2V yet with clean edges
P-P
Input Filtering
and fast slew rates should be able to realize the full phase
The LTC6957 includes input filtering with three narrow-
band settings in addition to the full bandwidth limitation
of the circuit design.
noise performance of the LTC6957.
CMOS
R1
75Ω
Table 1
+
Z0 = 50Ω
FILTA
Low
High
Low
High
FILTB
Low
BANDWIDTH
1200MHz (Full Bandwidth)
500MHz (–3dB)
50Ω
LTC6957
R2
100Ω
–
R
OUT
≈ 25Ω
Low
6957 F06
High
High
160MHz (–3dB)
50MHz (–3dB)
Figure 6. CMOS Input
For slow slewing signals (i.e., <100MHz sine wave sig-
nals) substantially lower phase noise can be achieved by
using this feature. Bandwidth limiting is useful because it
limits the impact of all of the spectral energy that will alias
down to (on top of) the fundamental frequency.
The various capacitors are for AC-coupling and should
have Z << 50Ω at the operating frequency. The capacitors
allow the LTC6957 to set its own DC input bias level, and
reduce the DC current drain, which at 12.4mA (for the
case of a driver powered from 3.3V) is significant. This
current drain can be reduced (with some potential for a
noise penalty) by increasing the attenuation at the R1/
R2 network, taking care to keep the Thevenin impedance
equal to the Z0 of the trace.
The best filter setting to use for a given application will
depend on the clock frequency, amplitude, and waveform
shape, with the single biggest determinant being the slew
rate at the input of the LTC6957. Any amplifier noise will
add phase noise inversely proportional to its input slew
rate, just from the dV/dt changing voltage noise to time
base noise. But a fast slew rate may not be possible with
other design constraints, such as the use of sine waves
for EMI/RFI reasons, signal losses, etc. A limiting ampli-
fier such as the LTC6957 should have enough bandwidth
to preserve the slew rate of the input. But any additional
bandwidth will provide no improvement in phase noise
due to slew rate preservation, while incurring a phase
noise penalty from noise aliasing.
When using CMOS logic, it is important to consider how
all of the output drivers, in the same IC, are being used.
For best performance, the entire IC should be devoted to
driving the LTC6957, or if other gates in the same pack-
age must be put to use, they should only carry the same
timing signal (such as for fan-out) or be multiplexed in
time so that only one timing signal is being processed at
a time, such as for multiplexing selective shutdowns of
different segments of a system. Otherwise performance
is likely to suffer with spurs or other interference in the
6957fb
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APPLICATIONS INFORMATION
Table 2 has the slew rate ranges most suitable for the four
different filter settings.
Figure 7 has LTC6957-1 100MHz additive phase noise
measurements that illustrate the trade-offs between filter
settings at various input slew rates. Each of the three
charts has all four filter settings, and one input amplitude;
Figure 7a has a +10dBm input, Figure 7b has a 0dBm
input, and Figure 7c has a –10dBm input. The four filter
settings are shown in the same colors throughout.
Table 2
FILTA
Low
High
Low
High
FILTB
Low
INPUT SLEW RATE (V/µs)
>400
125 to 400
40 to 125
<40
Low
High
High
With +10dBm at 100MHz, the input slew rate is 628V/µs
and Table 2 indicates the best filter setting to use is FILTA
= FILTB = L, which is seen to be the case in Figure 7a.
Another way to look at this is to consider the case of sine
waves, for which the frequency ranges will depend on
input amplitudes, as illustrated in Table 3.
The noise at the next filter setting is only slightly higher,
but for the maximum filtering case there is a full 10dB of
additional noise.
Table 3
FREQUENCY RANGE
With 0dBm at 100MHz, the input slew rate is 198V/µs and
Table 2 indicates the best filter setting to use is FILTA = H,
FILTB = L. Again this is seen to be the case in Figure 7b.
Astheinputwasdecreased10dBfromFigure7atoFigure7b,
the blue trace rose 5dB while the green trace only rose
3dB.
INPUT
FILTA = L,
FILTA = H,
FILTB = L
(MHz)
FILTA = L,
FILTB = H
(MHz)
FILTA = H,
FILTB = H
(MHz)
AMPLITUDE FILTB = L
(dBm)
10
(MHz)
>63
20 to 63
35 to 112
63 to 200
>112
6.3 to 20
11 to 35
20 to 63
35 to 112
63 to 200
<6.3
<11
<20
<35
<63
5
>112
>200
0
–5
With –10dBm at 100MHz, the input slew rate is 63V/µs and
Table 2 indicates the best filter setting to use is FILTA = L,
FILTB = H. Again this is seen to be the case in Figure 7c. As
the input was decreased 10dB from Figure 7a to Figure 7b,
and again to Figure 7c, the red trace rose just 3dB then
another 4dB, while the green and blue traces rose much
faster.
–10
>200
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ꢂꢔꢈꢡꢞꢃꢢꢃꢈꢣꢃꢣ ꢂꢔꢈꢃ ꢤꢓꢥꢃ ꢔꢈꢒꢇꢄꢠ
ꢏꢐꢐꢝꢌꢍ ꢓꢄ ꢑꢏꢐꢕꢖꢦ ꢋꢛꢐꢐꢦꢥ
ꢞꢄꢉ6957ꢢꢏ
ꢎ
ꢒꢢꢒ
ꢁꢔꢟꢄꢓ ꢠ ꢁꢔꢟꢄꢖ ꢠ ꢟ
ꢑꢏ65
ꢏꢐꢐ
ꢏꢚ
ꢏꢐꢚ
ꢏꢐꢐꢚ
ꢏꢞ
ꢏꢐꢐ
ꢏꢚ
ꢏꢐꢚ
ꢏꢐꢐꢚ
ꢏꢝ
ꢏꢐꢐ
ꢏꢚ
ꢏꢐꢚ
ꢏꢐꢐꢚ
ꢏꢝ
ꢀꢁꢁꢂꢃꢄ ꢁꢅꢃꢆꢇꢃꢈꢉꢊ ꢋꢌꢍꢎ
ꢀꢁꢁꢂꢃꢄ ꢁꢅꢃꢆꢇꢃꢈꢉꢊ ꢋꢌꢍꢎ
ꢀꢁꢁꢂꢃꢄ ꢁꢅꢃꢆꢇꢃꢈꢉꢊ ꢋꢌꢍꢎ
6957ꢏꢛꢜꢙ ꢁꢐ7ꢝ
6957ꢏꢛꢜꢙ ꢁꢐ7ꢗ
6957ꢏꢛꢜꢙ ꢁꢐ7b
(a)
(b)
(c)
Figure 7. 100MHz Additive Phase Noise with Varying Input Amplitudes
6957fb
24
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
APPLICATIONS INFORMATION
One important observation to take away from Figures 7a
to 7c is that while the worst filter settings for a given set
of conditions should certainly be avoided, it doesn't mat-
ter nearly as much if the optimal or next to optimal filter
setting is used, because they are always fairly comparable
in terms of phase noise. So if a design will have an octave
or two range of amplitudes or frequencies, it is sufficient
to choose the filter setting whose range most closely
matches the application's range when using Tables 2 or
3 and the noise penalty will not be severe anywhere in
the range.
duty cycle is not exactly 50%. The LTC6957 inputs are
internally DC-coupled, and as shown in Figure 1, biasing
is provided at ~64% of the supply voltage. AC-coupled
input signals with a duty cycle of exactly 50% will see
symmetric levels of overdrive for the two signal direc-
tions. If, for example, the input signal is a 100mVP-P
square wave with a duty-cycle of 48%, meaning it is high
48% of the time and low 52% of the time, the DC average
will be 48mV above the low voltage level. This means the
rising edge has 52mV of overdrive, and the falling edge
has 48mV of overdrive.
Evidently, the input filtering will not significantly help with
large and fast slewing input signals to the LTC6957. As
seen in Figure 1, the input has a differential pair before the
filters, so the limiting will already have happened before
the filter. Fortunately, with large input signals, perfor-
mance is typically better than with smaller input signals
because phase noise is a signal-to-noise phenomenon.
As a result of this, the rising edge tPD will be faster than the
falling edge tPD. Fortunately, this will make the output duty
cycle closer to 50% than the input duty cycle. Figure 8
is from measurements on the LTC6957-2, with a 2V to
–
+
2.1V square wave on IN , and with IN set to various DC
voltages between those two levels. The X-axis is the over-
drive level for the tPD+ data, and is 100mV minus the over-
drive level for the t – data, to illustrate the level of t
PD
PD
Input Drive and Output Skew
changes that can unexpectedly occur with AC-coupling.
The lines are dashed where the measurement uncertainty
All versions of the LTC6957 have very good output skew;
the specification limits consist almost entirely of test mar-
gins. Even laboratory verification of the skew between dif-
ferent outputs is a challenging exercise, given the need to
measure within 1ps. With electromagnetic propagation
velocity in FR-4 being well known as 6" per nanosecond,
the skew of the LTC6957 will be impacted by PCB trace
routing length differences of just 6mils.
becomes large, when single digit millivolts and picosec-
1
onds are being measured . As can be seen, the t +/t –
PD PD
mismatch is very good at 50mV where the two overdrive
levels are the same.
ꢏ5ꢉꢉ
ꢏꢒꢉꢉ
ꢏꢑꢉꢉ
ꢏꢐꢉꢉ
The LTC6957 t and t
are specified for a 100mV
SKEW
PD
step with 50mV of overdrive. This is common for high
speed comparators, though it may not reflect the typi-
cal application usage of parts such as the LTC6957. The
propagation delay of the LTC6957 will increase with less
overdrive and decrease with more overdrive, as would
that of a high speed comparator. To a lesser extent, hav-
ing the same overdrive but a larger signal (for instance a
differential input step of –200mV to 50mV) will increase
propagation delay, though this effect is smaller and can
usually be ignored.
ꢏꢏꢉꢉ
ꢏꢉꢉꢉ
9ꢉꢉ
ꢎꢉꢉ
7ꢉꢉ
6ꢉꢉ
5ꢉꢉ
ꢊ
ꢖ
ꢊ
ꢔ
ꢋꢄ
ꢋꢄ
ꢖ
ꢅꢕ ꢀꢓꢓꢗꢂꢘꢘꢂꢄ 5ꢉꢇꢁ
ꢔ
ꢄꢙ
ꢅꢕ ꢄꢃꢅꢁꢂꢕ ꢏꢉꢉꢇꢁ
ꢋꢚꢋ
ꢓꢅꢛꢘꢜ ꢝ ꢓꢅꢛꢘꢞ ꢝ ꢛ
ꢉ
ꢏꢉ ꢐꢉ ꢑꢉ ꢒꢉ 5ꢉ 6ꢉ 7ꢉ ꢎꢉ 9ꢉ ꢏꢉꢉ
ꢀꢁꢂꢃꢄꢃꢅꢁꢂ ꢆꢇꢁꢈ
6957 ꢓꢉꢎ
Figure 8. LTC6957-2 Propagation Delay vs Overdrive
A consequence of this behavior may be a perceived mis-
match between the propagation delay for rising versus
falling edges when driven with an AC-coupled input whose
1
Below 2mV to 3mV, the input offset and the small input hysteresis play a role too. Fortunately,
neither is large enough to be a concern in normal operation.
6957fb
25
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
APPLICATIONS INFORMATION
This data is shown for the LTC6957-2, but the effect is
due to the input stage that is common to all versions, so
any other version will have the same general behavior.
The simplest way to terminate and bias the LTC6957-1
outputs is to route the differential output to the differential
receiver and terminate the lines at that point with the three
resistor network shown in Figure 9. The differential ter-
mination will be 100Ω, while the common mode termina-
tion will be 75Ω which could result in additional common
mode susceptibility. A bypass capacitor on the midpoint
of the Y can be used to improve this.
The LTC6957-3 and LTC6957-4 CMOS outputs may have
additional t + vs t – discrepancies due to differences
PD
PD
between the NMOS and PMOS output devices, particularly
when driving heavy loads. These are independent of input
overdrive, but can change with supply voltage and tem-
perature, and can vary part to part. The complementary
outputs of the LTC6957-4 will therefore be higher skew
than the like edges of the LTC6957-3. Both the LTC6957-3
If the common mode termination impedance is not an
issue, the three resistor Y configuration can be changed
to a three resistor delta configuration, which is a simpler
layout in most cases.
+
–
and LTC6957-4 will have large (120ps typ) t
to t
PD
PD
discrepancies compared to LVPECL or LVDS outputs.
During transitions to and from shutdown, the LTC6957-1
outputs are not guaranteed to comply with the specified
output levels for any length of time after the rising edge
LVPECL Outputs of the LTC6957-1
Figure 9 shows a simplified schematic of the LTC6957-1
LVPECL output stage. As with most ECL outputs, there are
no internal pull-down devices so the user must provide
both termination and biasing external to the device. Note
that only the current source is cut off during shutdown.
The bases of the output NPNs are still tied to the pull-up
resistors, so both outputs will be pulled high in shutdown,
and it is the user’s responsibility to disconnect the exter-
nal loading if power reduction is to be realized.
of SD1/SD2, nor for any time before sufficient t
ENABLE
/
WAKEUP
t
subsequent to the falling edge of SD1/SD2. The
output common mode and differential voltage could have
a slow settling time compared to the signal frequency, and
a long string of runt pulses could be seen. The LTC6957-1
shutdown capability should be used as a slow on/off con-
trol, not a logic gating/enable control.
+
V
+
V
24Ω
+
V
5Ω
+
V
+
50Ω
PCB ROUTING TRACES
Z0 = 50Ω
50Ω
24Ω
+
V
50Ω
–
5Ω
6957 F09
LTC6957-1
Figure 9. LTC6957-1 LVPECL Outputs
6957fb
26
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
APPLICATIONS INFORMATION
Power Supplies for LVPECL Operation
With all four outputs terminated or otherwise driving
heavy loads, the LTC6957-1 power consumption and
temperature rise may be an issue.
The LTC6957-1 can operate from 3.15V to 3.45V total
supply voltage difference, irrespective of the absolute
level of those voltages. The convention in LVPECL is that
the negative supply is ground, while in ECL the positive
supply may be ground or 2.0V. The LTC6957-1 can work
in all of these situations provided the total supply voltage
difference is within the 3.15V to 3.45V range. No special
supply sequencing will be needed. With a 2V rail the out-
put terminations go to ground, while, with the positive
supply grounded, the outputs can tolerate short circuits
to ground. However, the four CMOS logic input signals
will need to be driven with respect to whatever absolute
levels of supply voltages are used. If FILTA, FILTB, SD1,
and SD2 are fixed, they can be tied to the appropriate rail
and this is not a problem. Interface logic levels could get
tricky if they need to be programmed in-system.
Fortunately, the data sheet specification for supply cur-
rent with output loads does not need to be multiplied
by the entire supply voltage to calculate on-chip power
dissipation because most of that current flows through
the loads which will dissipate a significant portion of the
total system power.
Typically, the internal power consumption will be (20mA •
3.3V = ) 66mW, while the on-chip power dissipation from
the output loading will be less than half that number. With
a total power dissipation on-chip of 90mW, the tempera-
ture rise in the MS-12 package will be 13°C given the
θ
JA
of that package. For use to 125°C ambient (H-grade)
designers should be sure to check the temperature rise
using their specific output loading and supply levels. The
Absolute Maximum rating for Junction Temperature is
150°C, and must be avoided to prevent damaging the
device, and as stated in Note 1: "Exposure to any Absolute
Maximum Rating condition for extended periods of time
may affect device reliability and lifetime."
In any voltage configuration, be aware that the LVPECL
output stage depends on the external load to complete its
biasing and, as such, is susceptible to phase modulation
as the supply voltage changes. The LTC6957-1 is gener-
ally less sensitive to variations in the supply voltage if the
termination voltage tracks the supply rather than ground.
6957fb
27
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
APPLICATIONS INFORMATION
LVDS Outputs of the LTC6957-2
rising edge of SD1/SD2, nor for any time before sufficient
t
/t
subsequent to the falling edge of SD1/
WAKEUP
SD2. The EoNuAtBpLuEt common mode voltage (VOS in 644-A
parlance) could have a slow settling time compared to the
signal frequency, and a long string of runt pulses could
be seen. The LTC6957-2 shutdown capability should be
used as a slow, power-saving on/off control, not a logic
gating/enable control.
Figure 10 shows a simplified schematic of the LTC6957-2
LVDS output stage. The TIA/EIA-644-A standard speci-
fies the generator electrical requirements for this type of
interface, and the LTC6957-2 has been verified against
that standard using the following test methods:
SPECIFICATION
LEVEL OF TESTING
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
6a
100% Production Tested
100% Production Tested
100% Production Tested
100% Production Tested*
Lab Verification of Design Only
100% Production Tested
100% Production Tested
100% Production Tested
Power Supplies for LVDS Operation
The LTC6957-2 has a single supply that should be within
the 3.15V to 3.45V range.
The LTC6957-2 power supply voltage can corrupt the
spectral purity of the clock signal, though to a lesser
degree than with any of the other options. See the Typical
6b
6c
Performance Characteristic chart t vs Supply Voltage.
PD
*The t
/t
of the LTC6957-2 are not compliant with the standard so
RISE FALL
as to preserve full phase noise performance. To slow the edge rates, add
differential capacitance across the outputs. 2.7pF is sufficient to meet the
standard.
When using both LVDS channels, the LTC6957-2 power
consumption can exceed 120mW, which results in a
junction-to-ambient rise of 17.4°C in the MS-12 package,
more when operated at 3.45V. Again, it is up to the user
to always avoid junction temperatures above the Absolute
Maximum rating, and to stay comfortably below it for any
extended periods of time.
The TIA/EIA-644-A standard does not cover driver charac-
teristics during shutdown nor the transitions to and from
shutdown. The LTC6957-2 outputs are not guaranteed to
comply with the standard for any length of time after the
LTC6957-2
3.7mA
+
V
650Ω
+
PCB ROUTING TRACES
Z0 = 50Ω TO 60Ω
110Ω
+
V
–
650Ω
6957 F10
1.25V
Figure 10. LTC6957-2 LVDS Outputs
6957fb
28
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
APPLICATIONS INFORMATION
CMOS Outputs of the LTC6957-3/LTC6957-4
outputs may have one or two errant transitions resulting
in runt pulses being seen. The LTC6957-3/LTC6957-4
shutdown capability should be used as a slow, power-
saving on/off control, not a logic gating/enable control,
and because they can not be put in a high impedance
(3-state) condition, the shutdown functionality is not
usable as a way to multiplex multiple outputs or devices.
Figure 11 shows a simplified schematic of the LTC6957-3/
LTC6957-4 CMOS output stage. The LTC6957-3 outputs
are driven synchronously in-phase, while the LTC6957-4
outputs are driven differentially out-of-phase.
Although the LTC6957-3/LTC6957-4 are specified for a
resistive load, the outputs can drive capacitive loads as
well. With more than a few picoFarads of load, the rise
and fall times will be degraded in direct proportion to the
load capacitance.
Power Supplies for CMOS Operation
The LTC6957-3/LTC6957-4 operate with V+ from 3.15V to
3.45V only. If the LTC6957-3/LTC6957-4 are used to drive
CMOS logic at a lower voltage rail, the output stage can
During shutdown, the LTC6957-3 outputs will both be
set to a logic low.
be powered (Pin 11) by a lower voltage, down to 2.4VMIN
.
Note that significant degradation of the spectral purity
During shutdown, the LTC6957-4 OUT1 will be set to a
logic low, while OUT2 will be set to a logic high.
could occur if the output supply, V , is not clean, either
DD
because of additional broadband noise or discrete spec-
tral tones. The nature of a CMOS logic gate forms an AM
modulator of low frequency disturbances on the power/
ground that modulate the signal propagating through the
CMOS gate. Numerous common phenomena can serve
to convert the AM to PM/FM and, even if the conversion
efficiency is low, corrupt the phase noise to unacceptable
levels in demanding applications.
During transitions to and from shutdown, the LTC6967-3/
LTC6957-4 outputs may not comply with the specified
output levels for any length of time after the rising edge
of SD1/SD2, nor for any time before sufficient t
ENABLE
/
WAKEUP
t
subsequent to the falling edge of SD1/SD2. The
ꢊꢄꢋ6957ꢌꢍꢎꢊꢄꢋ6957ꢌꢏ
If two separate supplies are used, the only supply sequenc-
ing issue to be aware of is that if the V comes up first,
the OUT1/OUT2 CMOS outputs will bDeDhigh impedance
until V+ > ~1V. Note that the four CMOS control inputs are
ꢅ
ꢆꢆ
+
all referenced to V , not the output supply. Also note that
during operation the output supply should be equal to or
ꢂꢃꢄꢁ
+
less than V . The LTC6957-3/LTC6957-4 will function with
+
V
several hundred millivolts above the V supply, but
DD
depending on the load, this margin for error can largely
be consumed by transient load steps.
When driving capacitive loads at high frequencies, the
LTC6957-3/LTC6957-4 VDD power consumption can jump
ꢂꢃꢄꢉ
+
considerably over the quiescent power taken from V . The
Dynamic current specification is with no load and adds
directly to the current needed to repetitively charge and
discharge a capacitive load.
ꢇꢈꢆ
ꢂꢃꢄ
+
With 24mA drawn from V at 3.3V, and another 20mA
to 30mA drawn from V (easy to do with two outputs
active at 300MHz), the total power consumption can be
145mW to 178mW, resulting in a junction-to-ambient rise
6957fb
DD
Figure 11. LTC6957-3/LTC6957-4 CMOS Outputs
29
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
APPLICATIONS INFORMATION
of 21°C to 26°C in the MS-12 package. For use to 125°C
ambient (H-grade) designers should be sure to check the
temperature rise using their specific output frequency,
loading, and supply voltages. The Absolute Maximum
rating for Junction Temperature is 150°C, which must be
avoided to prevent damaging the device, and as stated
in Note 1: "Exposure to any Absolute Maximum Rating
condition for extended periods of time may affect device
reliability and lifetime."
Unfortunately, the term “low jitter” has become so over-
used that it is rendered virtually meaningless. High speed
communication links doing de-serialization and the like
can require jitter on the order of 30ps to 50ps. This is
lower jitter than required for a clock on a micro-controller,
but for high frequency sampling, even 1ps can severely
impact the dynamic range achievable. Therefore, it is best
to ignore the term “low jitter” and look for measured val-
ues of jitter, and preferably phase noise. To analyze and
measure true low noise components, most instruments
measure phase noise (in dBc/Hz) rather than jitter.
Low Phase Noise Design Considerations
Phase noise is a frequency domain representation of the
random variation in phase of a periodic signal. It is char-
acterized as the power at a given offset frequency relative
to the power of the fundamental frequency. Phase noise
is specified in dBc/Hz, decibels relative to the carrier in
a 1Hz bandwidth. It is essentially a frequency dependent
signal-to-noise ratio.
A second consideration when designing for low phase
noise is that any clock signal is an analog signal and
should be thought of and routed as such. They should
not be run through large FPGAs with lots of activities at
multiple frequencies, they should not be routed through
PCB traces alongside digital data lines, and they should
not be routed through clock fan-out devices that have
features such as zero delay or programmable skew. The
specifics of the PCB traces and what surrounds them
should be analyzed as if the clock signals were among
your most sensitive analog signals, because in demanding
applications that is what your clock signals are. Note that
signal integrity software intended for analyzing crosstalk
in digital systems may only give yes or no answers and
that clocking performance can be compromised at levels
40dB to 60dB below what is required to get that “yes”
answer.
Designing for low phase noise is challenging, even with a
solid understanding of phase noise. Any designer attempt-
ing such a task will find a good working understanding of
what phase noise is, and how it behaves, to be the most
important tool to achieve success. One of the most intui-
tive explanations is found in Chapter 3, “The Relationship
Between Phase Jitter and Noise Density,” of W.P. Robins’
1982 text, “Phase Noise in Signal Sources.”
With a solid base of understanding, the designer will now
see that the entire clocking chain is full of potential phase
modulators. The noise of an amplifier is usually thought
of as an additive term, but for phase noise the bias noise,
to the extent that the amplifier bandwidth is dependent on
the bias level, is not an additive term but a modulating
term. The LTC6957 is a monolithic clock limiting ampli-
fier carefully designed so that users do not have to worry
about such details.
Common pitfalls with clock signals are the same as for
sensitive analog signals: routing near or alongside digital
traces of any kind, crossing digital traces on an adjacent
layer within a sandwich of ground planes, using digital
power planes as part of layer sandwiches, and assuming
all of these are sufficiently mitigated by using differential
clock signaling.
The way to address these issues is also the same as for
sensitive analog signals: routing away from digital traces
wherever possible; routing with shielding of ground,
either planes, adjacent traces, or both; making realistic
assumptions of common mode rejections (30dB to 40dB
at most); and keeping a critical eye out for unintended
couplers during the design and debug phases.
However, users of the LTC6957 still need to pay attention
to external considerations that can result in corruption of
the good phase noise performance available from all the
components used.
Timing jitter is a term used to describe the integration
of phase noise over a specified bandwidth which is pre-
sented as a time domain specification.
6957fb
30
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
APPLICATIONS INFORMATION
Even if the world’s cleanest reference clock were used
to feed the LTC6957, simply routing it through a poorly
designed system would result in compromised spectral
performance. This often catches designers by surprise
because the mechanisms above are typically additive and
linear, which result in filtering and additional spectral com-
ponents, but don’t by themselves create phase modula-
tion. Unfortunately, any limiter, including the LTC6957,
will, through its nonlinear action, transform additive terms
into phase modulation. When a small tone is added to a
large pure tone, the larger tone will appear to have its
amplitude and phase modulated at a rate equal to the dif-
ference of the two frequencies. Pass this through a limiter
and only the phase modulation remains.
AM to PM Conversion at the LTC6957 Inputs
The LTC6957 input stage has some AM to PM conversion,
but as seen in the Typical Performance Characteristics
section, even at 300MHz this is less than 0.5°/dB. One
source of AM to PM conversion at the LTC6957 input is
the optional lowpass filtering, because the upper side-
band and the lower sideband will be attenuated by slightly
different amounts. This difference is quite small for low
offset frequencies, but the difference grows both as the
frequency of the modulation increases, and as the carrier
frequency approaches the filter cutoff frequency where
the filter has a steeper roll-off.
Therefore, if small amounts of AM are known to be present
and an unacceptable level of PM is seen at the LTC6957
output, it may be helpful to change the input filter setting
to a higher cutoff frequency.
In large complex systems, it may be impractical to elimi-
nate all potential corrupting of the clock signals. In such
a case, a narrow band filter placed at the inputs of the
LTC6957 can remove the unwanted spectral components
that are far enough away from the fundamental.
Cross Talk from Loading at the LTC6957 Outputs
Another mechanism to be aware of in the LTC6957 is
cross-modulation of the outputs. Except for the CMOS
LTC6957-3/LTC6957-4, there is minimal direct AM or
PM modulation of the outputs by the power supply. In
Close-in spectral anomalies will likely be impervious to
such filtering. Therefore, it is doubly important to keep an
eye out for modulating mechanisms. If the clock is routed
through CMOS logic gates, the power supply used for that
gate will AM modulate the signal at the very least. The
modulation could manifest itself as sideband tones if the
power supply has repetitive disturbances, common with
switching power supplies, or it could manifest itself as
random noise if the noise of a linear regulator is too high.
the CMOS case, the V power supply will directly AM
DD
modulate the outputs, with a small amount of AM to PM
conversion.
The thing to be aware of here is that there can be load-
induced disturbances internal to the LTC6957 that can
modulate the other output. For instance, hooking up one
output to an ADC encode input and the second output to
the FPGA that performs the first DSP on the ADC outputs,
can result in considerable kickback of FPGA generated
signals into the LTC6957. If this cross-modulates over to
the other output, all kinds of deleterious effects may be
seen including tones, images, etc.
Another source of corruption in large systems or labora-
tory measurements is the use of flexible cabling, which
can have a low level piezoelectric effect that modulates the
electrical length in response to mechanical vibration.
Rigid or semi-rigid cabling and PCB routing can be used
to eliminate this source of signal corruption.
The CMOS LTC6957-3/LTC6957-4 are more susceptible
to this than the LVPECL and LVDS (LTC6957-1/LTC6957-
2). To prevent this, a buffer can be placed between the
LTC6957 and the FPGA, even one that compromises the
full jitter performance considerably. Because it is the ADC
that is doing the sampling—the FPGA clock input has
enough margin for error to qualify as a digital signal.
6957fb
31
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
APPLICATIONS INFORMATION
50Ω TERMINATION
2V
N5500A
REF
MINI-CIRCUITS
ZHL-2010+
–1.3V
DUT
1
2
MINI-CIRCUITS
ZFBT-6GW-FT
AGILENT 8644
122.88MHz
12.5dBm
MCL
LFCN
–150
MCL
LFCN
–150
MINI-CIRCUITS
ZX10-2-12-5
SIG
SPUR
INPUT
CAL TONE
MONITOR
3dB
6dB
10dB
10dB
ATTENUATOR
ATTENUATOR
ATTENUATOR
ATTENUATOR
COUPL
COUPL
3dB
ATTENUATOR
6957 F12
OUT
IN
IN
OUT
LINE STRETCHER
ARRA L9428A
MINI-CIRCUITS MINI-CIRCUITS
ZFDC-20-5-5+ ZFDC-20-5-5+
MINI-CIRCUITS
ZHL-2010+
Figure 12. Setup for LTC6957-1 Phase Noise Measurement Using Agilent E5505
In theory, all the phase noise in the signal source will be
rejected with the reading reflecting only the difference in
noise between the two paths. However, the rejection is
not perfect, particularly at very high offset frequencies
where the phase difference between the two paths pro-
gressively increases, thus the successive lowpass filters
on the signal source.
Phase Noise Measurement
Additive (also called residual) phase noise can be par-
ticularly challenging to measure. Figure 12 shows a typi-
cal laboratory set-up for testing the LTC6957-1 phase
noise. The LTC6957-1 has the lowest broadband phase
noise of the various dash numbers (equal to that of the
LTC6957-3/LTC6957-4) and the lowest close-in noise
with a corner frequency below 2kHz, so it presents the
most challenging case.
The Agilent 5505 measurement system uses the N5500A
front end, which includes a mixer to compare the signal
and reference phases. For amplifier noise, it is appro-
priate to feed the DUT path to the signal input, but for
clock buffers that create fast clock edges, it is usually
advantageous to use the reference input, which seems to
be sensitive only to the edges and not noise throughout
the period. This is a reasonable thing to do because the
LTC6957 is designed to drive ADC encode inputs or mixer
ports which have the same qualitative properties.
The various components and their role will be discussed
as this will illustrate both the care that must be taken
to realize the full performance of the LTC6957, and the
demanding nature of making phase noise measurements.
The signal starts with a 122.88MHz CW tone from the
Agilent 8644 synthesizer at a fairly high power level of
12.5dBm. Two series LPFs at 150MHz cut out all the high
frequency noise components that would otherwise con-
tribute noise because of the aliasing caused by the limiting
action of the LTC6957. A signal splitter then separates the
signal in two; one path will propagate through the DUT
and the other won’t, a common method used for measur-
ing residual phase noise.
Both the signal and reference inputs to the test set need
to be fairly large (15dBm to 20dBm) to realize the best
noise floor, so both signal paths include Mini-Circuits
ZHL-2010+ low noise amplifiers to boost the signal. The
LTC6957-1 was operated from 2V/–1.3V supplies so it
6957fb
32
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
APPLICATIONS INFORMATION
To calibrate E5505/N5500 measurements, the gain of the
mixer must be known. The surest way to measure it at
the actual frequencies being used is to inject a calibration
tone. For a 10kHz offset, a 122.89MHz low level (–10dBm)
signal is fed into the first coupler port. The requirements
for this signal are not demanding, so a general purpose
synthesizer that can be frequency locked, such as the
HP8657B, can be used.
could drive a 50Ω load to ground directly, but this cre-
ates a DC offset (the signal is always positive) that the
amplifier cannot take, so a bias tee was included in the
DUT signal path.
Only the 122.88MHz sine wave will be in the path without
the DUT, going to the N5500A signal port, until the first
coupler. This coupler allows a spur input to be injected,
while a second coupler allows the size of the spur, relative
to the carrier, to be measured. More on that in a min-
ute. The three attenuators in this signal path work with
the ZHL-2010+ to manage the dynamic range, while the
attenuators on the coupling ports keep these terminals
from degrading the measured noise.
The E5505 measures the amplitude of the resulting 10kHz
mixer output, but to put that in context (so that it can later
calculate results in dBc) it needs to know the size of the
injected spur relative to the carrier. Therefore, that relative
difference is measured using a spectrum analyzer con
nected to the attenuator on the second coupler.
-
Finally, an ARRA L9428A line stretcher is used to adjust
for quadrature. One last attenuator helps with impedance
matching between the N5500A input and the line stretcher
output port. The E5505A can automatically adjust the sig-
nal source phase/frequency for quadrature when mea-
suring VCOs or synthesizers, but for additive noise this
adjustment is manual because the adjustment must be
made after the signal is split into the two paths. The line
stretcher has a range of just 166ps, but with 122.88MHz,
up to 20ns of adjustment may be needed (1/4 cycle). Not
shown is the various short lengths of SMA cables and
barrel couplers that can also be added or subtracted to
adjust the relative phase of the two signal paths.
Hopefully the above discussion conveys the meticulous
effort needed to measure additive phase noise of a single
device, at a single operating frequency. While the circuitry
in Figure 12 can be used to measure the entire spectrum
of phase noise (all offset frequencies) as well as the phase
noise at other clock frequencies, every clock frequency
will require manual adjusting for quadrature. The input
LPFs will either need to be changed to match the new
clock frequency, or possibly amplitudes at various places
will have to be adjusted to account for the frequency roll-
off therein.
6957fb
33
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
TYPICAL APPLICATIONS
Crystal Oscillator
5V
IN
+
0.01µF
OUT
BP
LT1761-3.3V
3.3V
10µF
1µF
+
TO ALL V POINTS
+
0.1µF
V
2
12
+
V
SD1
0.1µF
50MHz
BANDWIDTH
FILTA
V
+
+
DD
V
V
1
6
11
10
FILTB
OUT1
+
IN
30pF
3
4
–
IN
OUT TO 50Ω
0.3V
450Ω
OUT2
2k
9
8
P-P
SQUARE WAVE
GNDOUT
SD2
LTC6957-3
GND
5
7
100Ω
10MHz
AT CUT
150Ω
75pF
6957 TA02a
Total Phase Noise of 10MHz Crystal Oscillator
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6957 ꢀꢁꢂꢃb
6957fb
34
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC6957-1#packaging for the most recent package drawings.
DD Package
12-Lead Plastic DFN (3mm × 3mm)
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6957fb
35
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC6957-1#packaging for the most recent package drawings.
MS Package
12-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1668 Rev A)
0.889 ±0.127
(.035 ±.005)
5.10
3.20 – 3.45
(.201)
(.126 – .136)
MIN
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
0.65
(.0256)
BSC
0.42 ±0.038
(.0165 ±.0015)
TYP
0.406 ±0.076
(.016 ±.003)
REF
12 11 10 9 8 7
RECOMMENDED SOLDER PAD LAYOUT
DETAIL “A”
0° – 6° TYP
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
4.90 ±0.152
(.193 ±.006)
0.254
(.010)
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
1
2 3 4 5 6
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.1016 ±0.0508
(.004 ±.002)
MSOP (MS12) 0213 REV A
0.650
(.0256)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6957fb
36
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
10/15 Corrected connections and part values in the Typical Applications schematic.
12/17 Corrected the Timing Diagram and added clarification text.
36
18
B
6957fb
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
37
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
TYPICAL APPLICATION
10MHz Frequency Reference Input Stage with Dual CMOS Outputs
Additive Phase Noise
vs Input Amplitude
3.3V
3.3V
–140
–145
–150
–155
–160
–165
–170
0.1µF
0.1µF
FILTA = L, FILTB = L
FILTA = H, FILTB = L
FILTA = L, FILTB = H
FILTA = H, FILTB = H
OPTIMUM FILT SETTINGS
LTC6957-3
1
2
3
4
5
6
12
11
10
9
FILTA
SD1
FILTA
+
R1
V
V
DD
COILCRAFT
WBC16-1T
0.1µF
0.1µF
0.1µF
100Ω
HSMS-281C
CMOS OUT1,
10MHz
+
10MHz
REF IN
–10dBm to
24dBm
IN
IN
OUT1
OUT2
•
•
–
CMOS OUT2,
10MHz
R2
604Ω
0.1µF
8
GND
GNDOUT
SD2
7
FILTB
FILTB
R1
100Ω
6957 TA03a
–10 –8 –6 –4 –2
0
2
4
6
8
10
10MHz REFERENCE INPUT POWER
WITH REFERENCE TO 50Ω (dBm)
69571234 TA03b
0.1µF
100Ω
TO PHASE NOISE MEASUREMENT
100Ω
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTC6945
Ultralow Noise and Spurious Integer-N Synthesizer 350MHz to 6GHz, –226dBc/Hz Normalized In-Band Phase Noise Floor,
–157dBc/Hz Wideband Output Phase Noise Floor
LTC6946-x
LTC6947
Ultralow Noise and Spurious Integer-N Synthesizer 370MHz to 6.4GHz, –226dBc/Hz Normalized In-Band Phase Noise Floor,
with Integrated VCO
–157dBc/Hz Wideband Output Phase Noise Floor
Ultralow Noise and Spurious Fractional-N
Synthesizer
350MHz to 6GHz, –226dBc/Hz Normalized In-Band Phase Noise Floor,
–157dBc/Hz Wideband Output Phase Noise Floor, Integer-N Spurious Performance
LTC6948-x
LTC6950
Ultralow Noise and Spurious Fractional-N
Synthesizer with Integrated VCO
370MHz to 6.4GHz, –226dBc/Hz Normalized In-Band Phase Noise Floor,
–157dBc/Hz Wideband Output Phase Noise Floor, Integer-N Spurious Performance
1.4GHz Low Phase Noise, Low Jitter PLL with Clock Four Independent LVPECL Outputs with 18fs
Distribution
Additive Jitter
RMS
(12kHz to 20MHz)
LTC6954-x
Low Phase Noise, Triple Output Clock Distribution
Divider/Driver
LVPECL, LVDS and CMOS Outputs with < 20fs
(12kHz to 20MHz)
Additive Jitter
RMS
6957fb
LT 1217 REV B • PRINTED IN USA
www.linear.com/LTC6957-1
38
ANALOG DEVICES, INC. 2017
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