LTC7063 [ADI]
100V Half-Bridge Driver with Floating Grounds and Adjustable Dead-Time;
| 型号： | LTC7063 |
| 厂家： | 
ADI |
| 描述： | 100V Half-Bridge Driver with Floating Grounds and Adjustable Dead-Time |
| 文件： | 总18页 (文件大小：2229K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC7060
100V Half-Bridge Driver with Floating
Grounds and Adjustable Dead-Time
FEATURES
DESCRIPTION
The LTC®7060 drives two N-Channel MOSFETs in a
half-bridge configuration with supply voltages up to
100V. Both high-side and low-side drivers can drive the
MOSFETs with a different ground reference, providing
excellent noise and transient immunity.
n
Unique Symmetric Floating Gate Driver Architecture
High Noise Immunity,Tolerates 10V Ground
Difference between Input and Output Grounds
100V Maximum Input Voltage Independent of IC
n
n
Supply Voltage V
CC
n
n
n
n
n
n
n
n
n
n
n
6V to 14V V Operating Voltage
CC
Its powerful 0.8Ω pull-down and 1.5Ω pull-up MOSFET
drivers allows the use of large gate capacitance high volt-
age MOSFETs. Additional features include UVLO, Three-
State PWM input, adjustable turn-on/-off delays and
shoot-through protection.
4V to 14V Gate Driver Voltage
0.8Ω Pull-Down, 1.5Ω Pull-Up for Fast Turn-On/Off
Adaptive Shoot-Through Protection
Programmable Dead-Time
Three-State PWM Input with Enable Pin
See chart below for a similar driver in this product family.
V
UVLO/OVLO and Floating Supplies UVLO
CC
Drives Dual N-Channel MOSFETs
PARAMETER
LTC7060
LTC7061
LTC7062
LTC7063
Open-Drain Fault Indicator
Input Signal
Three-State
PWM
CMOS/
TTL Logic
CMOS/
TTL Logic
Three-State
PWM
Available in Thermally Enhanced 12-LEAD MSOP
AEC-Q100 Automotive Qualification in Progress
Shoot-Through
Protection
Yes
115V
5.3V
Yes
115V
4.3V
No
Yes
155V
5.3V
Absolute Max
Voltage
115V
4.3V
APPLICATIONS
n
V
Falling
Automotive and Industrial Power Systems
CC
UVLO
n
Telecommunication Power Systems
n
Half-Bridge and Full-Bridge Converters
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
ꢀ
ꢀꢁ
ꢀꢁꢂ
ꢀ
ꢀꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃꢃ
ꢀꢁꢁ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
FLT
ꢀꢁꢂꢃꢄꢅꢄ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁRꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁ
ꢀ
ꢀꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢀ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁRꢂꢃ
ꢀꢁꢂꢃꢄꢅꢄ
ꢀꢁꢂ
ꢀꢁꢂ
FLT
ꢀꢁ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂꢁ ꢃAꢁꢄ
Rev. A
1
Document Feedback
For more information www.analog.com
LTC7060
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
(Note 1)
V
Supply Voltage .................................... –0.3V to 15V
ꢌꢖꢆ ꢍꢗꢉꢇ
CC
Top Side Driver Voltage (BST) ..................–0.3V to 115V
ꢆꢇꢈ
ꢉꢊ
FLT
ꢋꢌ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢀꢁ ꢏꢕꢌ
ꢀꢀ ꢌꢐ
ꢀꢑ ꢕꢇ
Bottom Side Driver Voltage (BGV ).........–0.3V to 115V
CC
ꢀꢂ
ꢕꢐꢊꢋ
SW, BGRTN................................................–10V to 100V
ꢒ
ꢓ
ꢔ
ꢊꢎ
ꢏꢐ
ꢏꢐRꢌꢊ
ꢍ
ꢏꢐꢍ
ꢎꢎ
ꢎꢎ
(BST-SW)................................................... –0.3V to 15V
(BGV -BGRTN) ........................................ –0.3V to 15V
CC
ꢈꢕꢉ ꢆAꢎꢘAꢐꢉ
ꢀꢁꢙꢚꢉAꢋ ꢆꢚAꢕꢌꢗꢎ ꢈꢕꢖꢆ
ꢝ ꢀꢄꢑꢞꢎꢟ θ ꢝ ꢃꢑꢞꢎꢠꢇ
ꢛA
ꢉꢜꢆꢖꢕꢉꢋ ꢆAꢋ ꢡꢆꢗꢊ ꢀꢂꢢ ꢗꢕ ꢕꢐꢊꢋꢟ ꢈꢣꢕꢌ ꢏꢉ ꢕꢖꢚꢋꢉRꢉꢋ ꢌꢖ ꢆꢎꢏ
EN, FLT ....................................................... –0.3V to 15V
DT, PWM...................................................... –0.3V to 6V
Driver Output TG (with Respect to SW)..... –0.3V to 15V
Driver Output BG
ꢌ
ꢛꢈAꢜ
(with Respect to BGRTN)........................... –0.3V to 15V
Operating Junction Temperature Range
(Note 2, 3)..... ......................................... –40°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
Note: All voltages are referred to SGND unless otherwise
noted.
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
LTC7060
PACKAGE DESCRIPTION
12-Lead Plastic MSSOP
12-Lead Plastic MSSOP
12-Lead Plastic MSSOP
12-Lead Plastic MSSOP
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–40°C to 150°C
LTC7060EMSE#PBF
LTC7060IMSE#PBF
LTC7060EMSE#TRPBF
LTC7060IMSE#TRPBF
LTC7060JMSE#TRPBF
LTC7060HMSE#TRPBF
LTC7060
LTC7060JMSE#PBF
LTC7060HMSE#PBF
AUTOMOTIVE PRODUCTS**
LTC7060EMSE#WPBF
LTC7060IMSE#WPBF
LTC7060JMSE#WPBF
LTC7060HMSE#WPBF
LTC7060
LTC7060
LTC7060EMSE#WTRPBF
LTC7060IMSE#WTRPBF
LTC7060JMSE#WTRPBF
LTC7060HMSE#WTRPBF
LTC7060
LTC7060
LTC7060
LTC7060
12-Lead Plastic MSSOP
12-Lead Plastic MSSOP
12-Lead Plastic MSSOP
12-Lead Plastic MSSOP
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–40°C to 150°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
these models.
Rev. A
2
For more information www.analog.com
LTC7060
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
temperature range, otherwise specifications are at TA = 25°C (Note 2). VCC = VBGVCC = VBST =10V, VBGRTN = VSW = 0V, unless
otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Supply and V Supply
CC
V
V
Input Supply Operating Range
IC Supply Operating Range
100
14
V
V
IN
6
5
CC
I
V
V
Supply Current
V
V
= V
= 0V, R = 100kΩ
0.4
5.3
mA
V
VCC
CC
CC
EN
PWM
DT
V
Undervoltage Lockout Threshold
Falling
5.6
14
UVLO_VCC
OVLO_VCC
CC
Hysteresis
Rising
0.3
V
V
V
OVLO Threshold
V
CC
14.6
0.8
V
CC
Hysteresis
V
BG Gate Driver Supply (BGV -BGRTN)
CC
V
BG Driver Supply Voltage Range
(With Respect to BGRTN)
4
4
V
BGVCC-BGRTN
I
Total BGV Current (Note 4)
BG = Low
BG = High
8
µA
µA
V
BGVCC
CC
100
3.4
0.3
V
Undervoltage Lockout Threshold
BGV Falling, With Respect to BGRTN
UVLO_BGVCC
CC
Hysteresis
V
TG Gate Driver Supply (BST-SW)
V
TG Driver Supply Voltage Range
(With Respect to SW)
14
V
BST-SW
I
Total BST Current (Note 4)
TG = Low
8
µA
µA
V
BST
TG = High
100
3.4
0.3
V
Undervoltage Lockout Threshold
BST Falling, With Respect to SW
Hysteresis
UVLO_BST
V
Input Signal (PWM, EN)
l
l
l
l
V
V
V
V
V
TG Turn-On Input Threshold
TG Turn-Off Input Threshold
BG Turn-On Input Threshold
BG Turn-Off Input Threshold
PWM Input Three-State Float Voltage
PWM Internal Pull-Up Resistor
PWM Internal Pull-Down Resistor
EN Pin Rising Threshold
PWM Rising
PWM Falling
PWM Falling
PWM Rising
2.6
2.45
0.5
3.1
2.95
1
3.6
3.45
1.5
V
V
IH(TG)
IL(TG)
V
IH(BG)
IL(BG)
0.75
1.9
1.25
2.1
48
1.75
2.3
V
V
PWM_TRI
R
R
To Internal 4.5V Supply
kΩ
kΩ
V
UP_PWM
DOWN_PWM
ENR
42
l
V
V
EN Rising
EN Falling
1.1
1.2
1.1
2
1.3
EN Pin Falling Threshold
V
ENF
R
EN Pin Internal Pull-Down Resistor
MΩ
EN
Dead-Time and FAULT (DT, FLT)
t
t
BG/TG Low to TG/BG High Propagation
Delay (Dead-Time)
R
= 0Ω
32
ns
PLH(BG) /
PLH(TG)
DT
R
R
R
R
= 24.9kΩ
= 64.9kΩ
= 100kΩ
= Open
43
62
ns
ns
ns
ns
Ω
DT
DT
DT
DT
76
250
60
R
Open Drain Pull-Down Resistance
FLTb
t
FLT Pin Release Delay
Low to High
100
µs
FLTb
Rev. A
3
For more information www.analog.com
LTC7060
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
temperature range, otherwise specifications are at TA = 25°C (Note 2). VCC = VBGVCC = VBST =10V, VBGRTN = VSW = 0V, unless
otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Low Side Gate Driver Output (BG)
V
V
BG High Output Voltage
BG Low Output Voltage
BG Pull-Up Resistance
BG Pull-Down Resistance
I
I
= –100mA, V
= V
– V
BG
150
80
mV
mV
Ω
OH(BG)
BG
BG
OH(BG)
BGVCC
= 100mA, V
=V – V
BGRTN
OL(BG)
OL(BG) BG
R
R
V
V
=10V
=10V
1.5
0.8
UP(BG)
BGVCC-BGRTN
BGVCC-BGRTN
Ω
DOWN(BG)
High Side Gate Driver Output (TG)
V
V
TG High Output Voltage
TG Low Output Voltage
TG Pull-Up Resistance
TG Pull-Down Resistance
I
I
= –100mA, V
= V
– V
150
80
mV
mV
Ω
OH(TG)
OL(TG)
TG
TG
OH(TG)
BST
TG
= 100mA, V
= V – V
TG
OL(TG)
SW
R
R
V
V
= 10V
= 10V
1.5
0.8
UP(TG)
BST-SW
BST-SW
Ω
DOWN(TG)
Switching Time
t
t
t
t
t
t
t
t
PWM High to BG Low Propagation Delay
PWM Low to TG Low Propagation Delay
BG Output Rise Time
17
17
18
13
18
13
30
36
ns
ns
ns
ns
ns
ns
ns
ns
PHL(BG)
PHL(TG)
r(BG)
C
C
C
C
= 3.3nF (Note 5)
= 3.3nF (Note 5)
= 3.3nF (Note 5)
= 3.3nF (Note 5)
LOAD
LOAD
LOAD
LOAD
BG Output Fall Time
f(BG)
TG Output Rise Time
r(TG)
TG Output Fall Time
f(TG)
EN High to TG/BG High Propagation Delay
EN Low to TG/BG Low Propagation Delay
PH(EN)
PL(EN)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Ratings for extended periods may affect device reliability and
lifetime.
for junction temperatures greater than 125°C. Note that the maximum
ambient temperature consistent with these specifications is determined by
specific operating conditions in conjunction with board layout, the rated
package thermal impedance and other environment factors.
Note 2: The LTC7060E is guaranteed to meet performance specifications
from 0°C to 85°C junction temperature. Specifications over the −40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC7060I is guaranteed over the −40°C to 125°C operation junction
temperature range. The LTC7060J is guaranteed over the −40°C to 150°C
operation junction temperature range. The LTC7060H is guaranteed over
the −40°C to 150°C operation junction temperature range. High junction
temperature degrades operation lifetimes; operating lifetime is derated
Note 3: T is calculated from the ambient temperature T and power
dissipation PD according to the following formula
J
A
T = T + (P • 51°C/W) for LFCSP package; T = T + (P • 40°C/W) for
J
A
D
J
A
D
MSOP package.
Note 4: The total current includes both the current from BGV /BST to
CC
BGRTN/SW and the current to SGND. Dynamic supply current is higher
due to the gate charge being delivered at the switching frequency.
Note 5: Rise and fall times are measured using 10% and 90% levels.
Rev. A
4
For more information www.analog.com
LTC7060
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
PWM Pin Thresholds vs
Temperature
EN Pin Thresholds vs
Temperature
Quiescent Supply Current vs
Supply Voltage
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢀ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀꢁꢁ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁ
ꢀ
ꢀꢁꢂꢃꢄꢅ
ꢀ
ꢀꢁꢁ
ꢀ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁ Rꢂꢃꢂꢁꢄ
ꢀ
ꢀ ꢁꢂ ꢃ ꢄ
ꢀꢁꢂꢃꢃ
ꢀ
ꢀ ꢁꢂ ꢃ ꢄ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁ ꢂAꢃꢃꢄꢁꢅ
ꢀ
ꢀ ꢀ ꢁꢂ ꢃ ꢄ
ꢀꢁꢂꢃꢃ
ꢀꢁꢂꢃꢄꢅ
ꢀ ꢀ ꢁꢂ ꢃ ꢄ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢀ ꢀꢁ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢁ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢀ ꢀꢁ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢁ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢀ
ꢀ ꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀ ꢁ
ꢀꢀ ꢀꢁꢂꢃꢃꢄꢀꢁRꢅꢆ ꢀꢁꢂꢃꢁꢄ
ꢀꢁꢂꢁ ꢃꢁꢄ
ꢀꢁꢂꢁ ꢃꢁꢄ
ꢀꢁꢂꢁ ꢃꢁꢄ
VCC Undervoltage Lockout
Thresholds vs Temperature
VCC Overvoltage Lockout
Thresholds vs Temperature
Supply Current vs Input
Frequency
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁꢁ
ꢀꢁꢁ
ꢀꢁꢁ
ꢀꢁꢁ
ꢀꢁꢁ
ꢀꢁꢁ
ꢀꢁꢁ
ꢀꢁꢁ
ꢀ
ꢀꢁ.ꢂ
ꢀꢁ.ꢂ
ꢀꢁ.ꢂ
ꢀꢁ.ꢂ
ꢀꢁ.ꢂ
ꢀ
ꢀ ꢁꢂꢃ ꢀ ꢁꢂꢃ ꢀ ꢄꢅꢆ
ꢀꢀ
ꢀꢀ
ꢀꢁ
ꢀ
ꢀ ꢁ ꢀ ꢁ.ꢁꢂꢃ
ꢀꢁ
ꢀꢁ ꢂ ꢃꢄRꢅꢆ ꢂ ꢇꢈ
ꢀ
Rꢀꢁꢀꢂꢃ
ꢀꢀ
ꢀ
Rꢀꢁꢀꢂꢃ
ꢀꢀ
ꢀ
ꢀAꢁꢁꢂꢃꢄ
ꢀꢀ
ꢀ
ꢀꢀ
ꢀAꢁꢁꢂꢃꢄ
ꢀ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢀ ꢀꢁ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢁ
ꢀ
ꢀꢁꢁ
ꢀꢁꢁ
ꢀꢁꢁ
ꢀꢁꢁ
ꢀꢁꢁꢁ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢀ ꢀꢁ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢁ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀꢁꢂꢁ ꢃꢁꢂ
ꢀꢁꢂꢁ ꢃꢁꢄ
ꢀꢁꢂꢁ ꢃꢁꢄ
Switching Supply Current vs Load
Capacitance
Rise and Fall Time vs Floating
Supply Voltage
Rise and Fall Time vs Load
Capacitance
ꢀꢁ
ꢀꢁꢁ
ꢀꢁꢁ
ꢀꢁ
ꢀ
ꢀ
ꢀ ꢁ.ꢁꢂꢃ
ꢀ
ꢀ ꢁꢂꢃ ꢀ ꢁꢂꢃ ꢀ ꢄꢅꢆ
ꢀꢀ ꢀꢀ
ꢀ
ꢀ ꢁꢂꢃ ꢀ ꢁꢂꢃ ꢀ ꢄꢅꢆ
ꢀꢀ
ꢀꢁAꢂ
ꢀꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢂ ꢃꢄRꢅꢆ ꢂ ꢇꢈ
ꢀ ꢁꢂ.ꢃꢄ
ꢀꢁ ꢂ ꢃꢄRꢅꢆ ꢂ ꢇꢈ
ꢀ ꢁꢂ.ꢃꢄ
R
R
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁ
ꢀꢁꢂꢃꢄ
ꢀ
ꢀ
ꢀ
ꢀ ꢁ ꢀ ꢁ ꢀ ꢁꢂꢂꢃꢄꢅ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢃ ꢀꢁꢂ ꢀꢁ
ꢀ ꢁ ꢀ ꢁ ꢀ ꢁꢂꢂꢃꢄꢅ
ꢀꢁꢂꢃꢃ ꢀꢁꢂ ꢀꢁ
ꢀ ꢁ ꢀ ꢁꢂꢂꢃꢄꢅ
ꢀꢁꢁ ꢀꢁ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁ ꢀꢀ ꢀꢁ ꢀꢁ ꢀꢁ
ꢀ
ꢀꢁ
ꢀꢁAꢂ ꢃAꢄAꢃꢅꢆAꢇꢃꢈ ꢉꢊꢋꢌ
ꢀꢁ
ꢀ
ꢀꢁ
ꢀꢁAꢂ ꢃAꢄAꢃꢅꢆAꢇꢃꢈ ꢉꢊꢋꢌ
ꢀꢁ
ꢀ
ꢀ ꢁ
ꢀꢁꢂ
ꢀꢁꢂꢃꢃꢄꢀꢁRꢅꢆ ꢀꢁꢂꢃꢁꢄ
ꢀꢁꢂꢁ ꢃꢁꢀ
ꢀꢁꢂꢁ ꢃꢁꢄ
ꢀꢁꢂꢁ ꢃꢁꢄ
Rev. A
5
For more information www.analog.com
LTC7060
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
Propagation Delay vs Floating
Supply Voltage
Propagation Delay vs
Temperature
Dead-Time vs RDT
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ ꢁꢂꢃ ꢀ ꢁꢂꢃ ꢀꢄꢅꢆ
ꢀꢀ
ꢀꢀ
ꢀ
ꢀꢁRꢂꢃ ꢄ ꢅꢆ ꢄ ꢇꢈ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢂꢁAꢃ
ꢀ
ꢀꢁꢂꢃꢄꢅ
ꢀ
ꢀꢁꢂꢃꢄꢅ
ꢀ
ꢀꢁꢂꢃꢄꢅ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
(kΩ)
ꢀꢁ
ꢀꢁꢁ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢀ ꢀꢁ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢁ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁ
R
ꢀꢁ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀ ꢁ
ꢀꢁꢂꢃꢃꢄꢀꢁRꢅꢆ ꢀꢁꢂꢃꢁꢄ
ꢀꢁꢂꢁ ꢃꢄꢅ
ꢀꢁꢂꢁ ꢃꢄꢄ
ꢀꢁꢂꢁ ꢃꢄꢁ
Dead-Time vs Floating Supply
Voltage
Dead-Time vs Temperature
ꢀꢁꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂ ꢀ ꢁꢂꢃ ꢀꢄꢅꢆ
ꢀꢀ
ꢀꢁRꢂꢃ ꢄ ꢅꢆ ꢄ ꢇꢈ
ꢀꢁ ꢂꢁAꢃ
ꢀ ꢀ R = 64.9kΩ
ꢀꢁꢂꢃꢄꢅꢆꢇꢅꢈ ꢀꢁ
ꢀ ꢀ R = 64.9kΩ
ꢀꢁꢂꢃꢄꢅꢆꢇꢅꢈ ꢀꢁ
ꢀ ꢀ R = 24.9kΩ
ꢀꢁꢂꢃꢄꢅꢆꢇꢅꢈ ꢀꢁ
ꢀ
ꢀ R = 24.9kΩ
ꢀꢁꢂꢃꢄꢅꢆꢇꢅꢈ ꢀꢁ
ꢀ ꢀ R = 0Ω
ꢀꢁꢂꢃꢄꢅꢆꢇꢅꢈ ꢀꢁ
ꢀ
ꢀ R = 0Ω
ꢀꢁꢂꢃꢄꢅꢆꢇꢅꢈ ꢀꢁ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢀ ꢀꢁ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢁ
ꢀ ꢁ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀꢁꢂꢃꢃꢄꢀꢁRꢅꢆ ꢀꢁꢂꢃꢁꢄ
ꢀꢁꢂꢁ ꢃꢄꢅ
ꢀꢁꢂꢁ ꢃꢄꢅ
TG/BG Pull-Up and Pull-Down
Resistance vs Floating Supply
Voltage
TG/BG Pull-Up and Pull-Down
Resistance vs Temperature
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂ ꢀ ꢁꢂꢃ ꢀꢄꢅꢆ
ꢀꢀ
ꢀꢁRꢂꢃ ꢄ ꢅꢆ ꢄ ꢇꢈ
R
ꢀ R
ꢀꢁꢂꢃꢄꢅ ꢀꢁꢂꢃꢄꢅ
R
R
R
R
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃꢄꢅꢆꢇ
ꢀꢁꢂꢃꢄꢅ
R
ꢀ R
ꢀꢁꢂꢃꢄꢅꢆꢇ ꢀꢁꢂꢃꢄꢅꢆꢇ
ꢀꢁꢂꢃꢄꢅꢆꢇ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢀ ꢀꢁ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢁ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀ ꢁ
ꢀꢁꢂꢃꢃꢄꢀꢁRꢅꢆ ꢀꢁꢂꢃꢁꢄ
ꢀꢁꢂꢁ ꢃꢄꢅ
ꢀꢁꢂꢁ ꢃꢄꢂ
Rev. A
6
For more information www.analog.com
LTC7060
PIN FUNCTIONS
V : V Supply. IC bias supply referred to the SGND pin.
TG: Top MOSFET Gate Driver Output. This pin drives the
gate of the N-channel MOSFET between SW and BST.
CC
AnCCinternal 4.5V supply is generated from the V supply
CC
to bias most of the internal circuitry. A bypass capacitor
with a minimum value of 0.1uF should be tied between
this pin and the SGND pin.
DT: Dead-Time Program Pin Referred to the SGND Pin.
A single resistor from this pin to SGND sets the BG/TG
low to TG/BG high propagation delay. See the operation
section for details.
BGVCC: Bottom MOSFET Driver Supply. The bottom
MOSFET gate driver is biased between this pin and the
BGRTN pin. An external capacitor should be tied between
this pin and BGRTN and placed close to the IC.
PWM: Three-State Gate Driver Input Signal Referred to
the SGND Pin. The TG/BG state is determined by the volt-
age at this pin. If this pin is floating, an internal resistor
divider triggers the High-Z mode in which both BG and
TG are turned off. Trace capacitance on this pin should
be minimized.
BGRTN: Bottom MOSFET Driver Return. The bottom
gate driver is biased between BGV and BGRTN. Kelvin
CC
connect BGRTN to the bottom MOSFET source pin for
high noise immunity. The voltage difference between the
BGRTN pin and the SGND can be –10V to 100V.
EN: Enable Control Input Pin Referred to the SGND Pin.
A voltage on this pin above 1.2V enables the gate drivers.
The TG and BG pins are both in the low state if this pin
is logic low.
BG: Bottom MOSFET Gate Driver Output. This pin drives
the gate of the N-channel MOSFET between BGRTN and
BGV .
CC
FLT: Open Drain Fault Output Pin Referred to the SGND
Pin. Open-drain output that pulls to SGND during VCC
UVLO/OVLO and floating supplies UVLO condition. The
typical pull-down resistance is 60Ω.
BST: Top MOSFET Driver Supply. The top MOSFET gate
driver is biased between this pin and the SW pin. An exter-
nal capacitor should be tied between this pin and the SW
pin and placed close to the IC.
NC: No Internal Connection. Always keep this pin floating.
It is intentionally skipped to isolate adjacent high voltage
pins.
SW: Top MOSFET Driver Return. The top gate driver is
biased between BST and SW. Kelvin connect SW to the top
MOSFET source pin for high noise immunity. The voltage
difference between the SW pin and SGND can be –10V
to 100V.
SGND: Chip Ground. The exposed pad must be soldered
to the PCB ground for electrical contact and for rated
thermal performance.
BLOCK DIAGRAM
FLT
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂAꢃ
ꢀRꢁꢂꢃR
ꢀꢁꢂꢃ
ꢀ
ꢀꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢀ
ꢀꢁ
ꢀꢁ
ꢅ
ꢆ
ꢀRꢁꢂꢃR
ꢄꢅꢆꢁꢇ
ꢀꢁꢂꢁꢀ
ꢀꢁꢂꢃꢄꢅR
ꢀꢁ
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢂꢃꢄ
ꢀꢁꢂꢁꢀ
ꢀꢁꢂꢃꢄꢅR
ꢀ.ꢁꢂ
ꢅ
ꢆ
ꢃꢁRꢂꢅꢆꢁ
ꢀꢁꢂ
ꢀꢀ
ꢇRꢂꢃꢈꢉꢃꢊꢂꢋ
ꢀꢁꢂ
ꢀRꢁꢂꢃR
ꢀꢁ
ꢅ
ꢆ
ꢀꢁꢂꢃ
ꢀ.ꢁꢂ
ꢀꢁRꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢁ ꢃꢄ
Rev. A
7
For more information www.analog.com
LTC7060
TIMING DIAGRAM
ꢀꢁ
ꢀꢀꢁꢂ
ꢀꢀꢁR
ꢀꢀꢁꢂꢃꢄꢅ
ꢀꢀꢁꢂꢃꢄꢅ
ꢀꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ
ꢀꢀꢁꢂꢃꢄ
ꢀꢀꢁꢂꢃꢄ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢀꢁꢂꢃꢄꢅ
ꢀꢀꢁꢂꢃꢄ
ꢀꢀꢁꢂꢃꢄꢅꢆ
ꢀꢀꢁꢂꢃꢄꢅꢆ
ꢀꢀꢁꢂꢃꢄꢅꢆ
ꢀꢀꢁꢂꢃꢄꢅ
ꢀꢀꢁꢂꢃꢄ
ꢀꢀꢁꢂꢃꢄꢅꢆ
ꢀꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢁ ꢃꢄ
OPERATION
OVERVIEW
the transition thresholds and three input states of the
LTC7060 is illustrated in Figure 1. When the voltage on
PWM is greater than the threshold VIH(TG), TG is pulled up
to BST, turning the high side MOSFET on. This MOSFET
The LTC7060 receives a ground-referenced, low volt-
age digital PWM signal to drive two N-channel power
MOSFETs in a half-bridge configuration. The gate of the
low side MOSFET is driven high or low, swinging between
will stay on until PWM falls below V
. Similarly, when
IL(TG)
PWM is less than V
, BG is pulled up to BGV , turn-
IH(BG)
CC
BGV and BGRTN, depending on the state of the PWM
CC
ing the low side MOSFET on. BG will stay high until PWM
pin. Similarly, the gate of the high side MOSFET is driven
complimentary to the low side MOSFET, swinging between
BST and SW.
increases above the threshold V
.
IL(BG)
The hysteresis between the corresponding VIH and VIL
voltage levels eliminates false triggering due to the noise
during switch transitions. However, care should be taken
to keep noise from coupling into the PWM pin, particularly
in high frequency, high voltage applications.
Both the low side and high side drivers are floating gate
drivers. The unique double floating architecture makes the
gate driver outputs robust and less sensitive to ground
noise. The symmetric design allows the half-bridge output
to be inverting or non-inverting of the input logic.
The thresholds are positioned to allow for a region in
which both BG and TG are low. An internal resistor divider
V
SUPPLY
CC
ꢀꢁ ꢂꢃꢁꢂ
V
is the power supply for the LTC7060’s internal circuitry.
ꢄ
ꢃꢂꢅꢀꢁꢆ
ACnCinternal 4.5V supply is generated from the V supply
ꢀꢁ ꢂꢃꢁꢂ
ꢀꢁ ꢇꢌꢊ
ꢀꢁ ꢇꢌꢊ
ꢄ
ꢄ
ꢃꢇꢅꢀꢁꢆ
CC
to bias most of the internal circuits referred to SGND. The
V
ꢉꢊꢋ
pin may be tied to the BGV pin if SGND and BGRTN
CC
CC
are at the same potential. V is independent of V .
CC
IN
ꢈꢁ ꢇꢌꢊ
ꢈꢁ ꢂꢃꢁꢂ
ꢄ
ꢃꢇꢅꢈꢁꢆ
ꢈꢁ ꢇꢌꢊ
ꢈꢁ ꢂꢃꢁꢂ
ꢃꢂꢅꢈꢁꢆ
INPUT STAGE (PWM, EN)
ꢍꢎꢏꢎ ꢐꢎꢑ
The LTC7060 employs a three-state PWM input with
fixed transition thresholds. The relationship between
Figure 1. Three-State PWM Operation
Rev. A
8
For more information www.analog.com
LTC7060
OPERATION
sets the PWM pin voltage into this region if the signal
driving the PWM pin goes into a high impedance state.
output pull-up and pull-down resistance may increase
with lower driver supply voltage.
The EN pin can also be used to keep both BG and TG low
if the high impedance state is not available from the PWM
driving signal. Driving the EN pin low keeps both TG and
BG off, and driving the EN pin high enables TG and BG
switching based on the PWM input. There is an internal
2MΩ pull-down resistor from the EN pin to SGND, keep-
ing the EN default state low if its input is not driven.
Since the power MOSFETs generally account for the
majority of the power loss in a converter, it is important
to turn them on and off quickly, thereby minimizing the
transition time and power loss. The LTC7060’s typical
1.5Ω pull-up resistance and 0.8Ω pull-down resistance
are equivalent to 3A peak pull-up current and 6A peak pull
down current at a 10V driver supply. Both BG and TG can
produce a rapid turn-on transition for the MOSFETs with
capability of driving a 3.3nF load with 18ns rise time.
Both three-state PWM and EN pin can be used by the
controller IC to perform the Discontinuous Conduction
Mode (DCM) in switching regulator applications.
Furthermore, a strong pull-down on the driver outputs
prevents cross-conduction current. For example, in the
half-bridge configuration shown in Figure 2, when BG
turns the low side power MOSFET off and TG turns the
high side power MOSFET on, the voltage on the SW pin
OUTPUT STAGE
A simplified version of the LTC7060’s output stage is
shown in Figure 2. The BG and TG design are symmetric
and they both have floating gate driver outputs. The pull-
could rise to V very rapidly. This high frequency posi-
IN
tive voltage transient will couple through the C capaci-
GD
up device is a PMOS with a typical 1.5Ω R
and the
DS(ON)
DS(ON)
tance of the low side power MOSFET to the BG pin. If the
BG pin is not held down sufficiently, the voltage on the
BG pin could rise above the threshold voltage of the low
side power MOSFET, momentarily turning it back on. As
a result, both the high side and low side MOSFETs would
be conducting, which would cause significant cross-con-
pull-down device is a NMOS with a typical 0.8Ω R
.
The wide driver supply voltage ranging from 4V to 14V
enables the driving of different power MOSFETs, such
as logic level or higher threshold MOSFETs. However,
the LTC7060 is optimized for higher threshold MOSFETs
(e.g. BST-SW = 10V and BGV -BGRTN = 10V). The driver
CC
duction current to flow through the MOSFETs from V
IN
to ground, thereby incurring substantial power loss and
potentially damaging the MOSFETs. For this reason, short
PCB traces for the BG and TG pins, which minimize the
parasitic inductances, are recommended.
ꢀꢀꢁ
ꢀꢁꢂꢃꢄꢅꢄ
ꢀꢁꢂ
1.5Ω
ꢀ
ꢁꢂ
ꢀꢁ
ꢀꢁꢂꢀ ꢃꢁꢄꢅ
ꢀꢁꢂꢃR ꢄꢁꢅꢆꢃꢇ
ꢀ
ꢁꢂ
PROTECTION CIRCUITRY
0.8Ω
ꢀꢁ
When using the LTC7060, care must be taken not to
exceed any of the ratings specified in the Absolute
Maximum Ratings section. As an added safeguard, the
LTC7060 incorporates overtemperature shutdown fea-
ture. If the junction temperature reaches approximately
180°C, the LTC7060 will enter thermal shutdown mode
and BG will be pulled to BGRTN; TG will be pulled to SW.
Normal operation will resume when the junction tempera-
ture cools down below 165°C. The overtemperature level
is not production tested. The LTC7060 is guaranteed to
operate below 150°C.
ꢀꢁꢂ
ꢃꢃ
1.5Ω
ꢀ
ꢁꢂ
ꢀꢁ
ꢀꢁꢂ ꢃꢄꢅꢆ
ꢀꢁꢂꢃR ꢄꢁꢅꢆꢃꢇ
ꢀ
ꢁꢂ
0.8Ω
ꢀꢁRꢂꢃ
ꢀꢁꢂꢁ ꢃꢁꢄ
Figure 2. Simplified Output Stage in Half-Bridge Configuration
Rev. A
9
For more information www.analog.com
LTC7060
OPERATION
The LTC7060 contains both undervoltage and overvoltage
lockout detectors that monitor the V supply. When V
applications, the LTC7060 provides a DT pin which can
be used to program the propagation delay during BG/TG
low to TG/BG high transition (Dead-Time). An external
CC
CC
falls below 5.3V or rises above 14.6V, BG and TG pins are
pulled to BGRTN and SW, respectively, turning off both
resistor (R ) from the DT pin to the SGND equally sets
DT
the external MOSFETs. When V has adequate supply
both the BG low to TG high propagation delay and the TG
low to BG high propagation delay. Their relationship can
be seen in Figure 3. The Dead-Time can be estimated by
CC
voltage but less than the overvoltage threshold, normal
operation will resume.
the following equation when the R is less than 100kΩ:
DT
Additional undervoltage lockout circuitry is included in
each floating driver supply. The BG will be pulled down to
BGRTN when the floating voltage from BGV to BGRTN
falls below 3.3V. Similarly, the TG will be CpCulled down
to SW when the floating voltage from BST to SW is less
than 3.3V.
Dead-Time = R • 0.44ns/kΩ + 32ns
DT
If the DT pin is shorted to SGND, the Dead-Time is 32ns.
If the DT Pin is floating, the Dead-Time is around 250ns.
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
The normal operation and undervoltage/overvoltage logic
table is shown in Table 1.
Table 1. Normal Operation and Undervoltage/Overvoltage Logic
V
(BGV -
CC
CC
UVLO or (BST-SW) BGRTN)
PWM
EN
L
OVLO
UVLO
UVLO
TG
L
BG
L
X
X
Y
N
N
N
N
X
X
X
X
X
N
Y
X
X
X
N
Y
X
X
X
X
X
L
L
ꢀ
ꢀꢁ
ꢀꢁ
R
ꢀꢁ
(kΩ)
ꢀꢁ
ꢀꢁꢁ
L
H
H
H
H
H
L
H
L
ꢀꢁ
ꢀꢁꢂꢁ ꢃꢁꢄ
L
L
Figure 3. Dead-Time vs RDT
H
H
H
L
L
L
FAULT FLAG
HIGH-Z
L
L
The FLT pin is connected to the open-drain of an internal
Note: “X” means "Don't Care"
N-channel MOSFET. It needs a pull-up resistor (e.g. 51k)
tied to a supply such as V or any other bias voltage up
ADAPTIVE SHOOT-THROUGH PROTECTION
CC
to 15V. The FLT pin is pulled low to SGND immediately if
Internal adaptive shoot-through protection circuitry moni-
tors the external MOSFETs to ensure that they do not
conduct simultaneously. The LTC7060 does not allow the
bottom MOSFET to turn on until the gate-source voltage
on the top MOSFET is sufficiently low, and vice-versa. This
feature improves efficiency and reliability by eliminating
potential shoot-through current through the MOSFETs
during switching transitions.
any of these conditions are met:
a. The VCC is below its UVLO threshold or above its
OVLO threshold.
b. (BGV -BGRTN) is below its UVLO threshold.
CC
c. (BST-SW) is below its UVLO threshold.
d. The junction temperature reaches approximately
180°C.
PROGRAMMABLE DEAD-TIME
When all the faults are cleared, the FLT pin is pulled up by
the external resistor after a built-in 100µs delay.
To ensure robust shoot-through protection in high voltage
half-bridge configuration and switched capacitor converter
Rev. A
10
For more information www.analog.com
LTC7060
APPLICATIONS INFORMATION
BOOTSTRAPPED SUPPLY (BGV -BGRTN, BST-SW)
Power dissipation consists of standby, switching and
capacitive load power losses:
CC
Either or both of the BGV -BGRTN and BST-SW sup-
CC
plies can be bootstrapped supplies. An external boost
P = P + P + P
D
DC
AC
QG
capacitor, C , connected between BGV and BGRTN, or
B
CC
where:
between BST and SW, supplies the gate driver voltage for
P
DC
= quiescent power loss
its respective MOSFET driver. When the external MOSFET
is turned on, the driver places the C voltage across the
B
P
AC
P
QG
= internal switching loss at input frequency f
IN
gate-source of the MOSFET. This enhances the MOSFET
= loss due to turning on and off external MOSEFT
with gate charge Q at frequency f
and turns it on.
G
IN
The charge to turn on the external MOSFET is referred to
gate charge, Q , and is typically specified in the external
The LTC7060 consumes very little quiescent current. The
DC power loss at VCC = 10V is only (10V)(0.4mA) = 4mW.
MOSFET data Gsheet. The boost capacitor, C , needs to
B
have at least 10 times the gate capacitance to turn on the
external MOSFET fully. Gate charge can range from 5nC
to hundreds of nC and is influenced by the gate drive level
and type of external MOSFET used. For most applica-
At a particular switching frequency, the internal power
loss increases due to both AC currents required to charge
and discharge internal nodal capacitances and cross-con-
duction currents in the internal logic gates. The sum of the
quiescent current and internal switching current with no
load are shown in the Typical Performance Characteristics
plot of Switching Supply Current vs Input Frequency.
tions, a capacitor value of 0.1uF for C will be sufficient.
B
However, if multiple MOSFETs are paralleled and driven
by the LTC7060, C capacitance needs to be increased
B
correspondingly.
The gate charge losses are primarily due to the large AC
currents required to charge and discharge the capacitance
of the external MOSFETs during switching. For identical
An external supply, typically VCC connected through a
Schottky diode, is required to keep the C charged. The
B
LTC7060 does not charge the C and always discharges
B
pure capacitive loads C
on BG and TG at switching
LOAD
the C . When the BG/TG is high, the total current from
B
frequency f , the load losses would be:
IN
BGV /BST to BGRTN/SW and SGND is typically 100µA;
CC
2
2
P
= (C
)(f )[(V
) + (V
) ]
CLOAD
LOAD IN
BST-SW
BGVCC-BGRTN
when the BG/TG is low, the total current from BGV /BST
CC
is typically 8µA.
In a typical synchronous buck configuration, the V is
CC
connected to the power for the bottom MOSFET driver,
BGV . V
is equal to V -V , where V is the for-
CC BST-SW
CC D D
POWER DISSIPATION
ward voltage drop of the external Schottky diode between
and BST. If this drop is small relative to V , the load
To ensure proper operation and long-term reliability, the
LTC7060 must not operate beyond its maximum tem-
perature rating. Package junction temperature can be
calculated by:
V
CC
CC
losses can be approximated as:
2
P
≈ 2(C )(f )(V )
LOAD IN CC
CLOAD
Unlike a pure capacitive load, a power MOSFET’s gate
capacitance seen by the driver output varies with its V
voltage level during switching. A MOSFET’s capacitiGveS
load power dissipation can be calculated using its gate
T = T + (P )(θ )
J
A
D
JA
where:
T = junction temperature
J
charge, Q . The Q value corresponding to the MOSFET’s
G
VGS value (VCC iGn this case) can be readily obtained
T = ambient temperature
A
P = power dissipation
D
from the manufacturer’s Q vs V curves. For identical
G
GS
MOSFETs on BG and TG:
θ
JA
= junction-to-ambient thermal resistance
P
QG
≈ 2(Q )(f )(V )
G
IN
CC
Rev. A
11
For more information www.analog.com
LTC7060
APPLICATIONS INFORMATION
BYPASSING AND GROUNDING
•
•
Plan the power/ground routing carefully. Know where
the large load switching current is coming from and
going to. Maintain separate ground return paths for
the input pin and the output power stage.
The LTC7060 requires proper bypassing on the VCC,
VBST-SW, and VBGVCC-BGRTN supplies due to its high
speed switching (nanoseconds) and large AC currents
(amperes). Careless component placement and PCB
trace routing may cause excessive ringing and under/
overshoot.
Kelvin connect the TG pin to the top MOSFET gate and
SW pin to the top MOSFET source. Kelvin connect
the BG pin to the bottom MOSFET gate and BGRTN
to the bottom MOSFET source. Keep the copper trace
between the driver output pin and load short and
wide.
To obtain the optimum performance form the LTC7060:
•
Mount the bypass capacitors as close as possible
between the VCC and SGND pins, the BGVCC and
BGRTN pins, and the BST and SW pins. The leads
should be shortened as much as possible to reduce
lead inductance.
•
Be sure to solder the Exposed Pad on the back side of
the LTC7060 packages to the board. Failure to make
good thermal contact between the exposed back side
and the copper board will result in thermal resistances
far greater than specified for the packages.
•
Use a low inductance, low impedance ground plane
to reduce any ground drop and stray capacitance.
Remember that the LTC7060 switches greater than
5A peak currents and any significant ground drop will
degrade signal integrity.
Rev. A
12
For more information www.analog.com
LTC7060
TYPICAL APPLICATIONS
ꢀ
ꢀ
ꢁ
ꢁ
ꢁ
ꢁ
ꢀ
Rev. A
13
For more information www.analog.com
LTC7060
TYPICAL APPLICATIONS
Rev. A
14
For more information www.analog.com
LTC7060
TYPICAL APPLICATIONS
Up to 100A High Efficiency 4 to 1 Switched Capacitor Converter
ꢀꢁ
ꢀꢁ
ꢀꢁꢂ ꢃꢄ ꢅꢁꢂ
ꢀ.ꢁꢂꢃ ꢄꢀ
ꢀꢁꢁꢂ
ꢀꢁꢁꢂꢃ ꢄꢅ
ꢀꢁꢂ
2.2Ω
ꢀ.ꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢀ.ꢁꢂ
ꢀꢁꢂꢀ
ꢀ
ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁRꢂ
ꢀRꢁ
ꢀꢁRꢂꢃꢄꢅꢂꢂꢆꢇ
ꢀꢁꢂꢃ
ꢀꢁ.ꢂꢃ
ꢀ.ꢁꢂꢃ
Rꢀꢁ
ꢀꢁ ꢂꢃꢄꢂRꢅAꢆ
ꢇꢈꢉꢉꢆꢊ
ꢀꢀ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀꢁꢂꢃꢄꢄꢅꢅ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢁꢄꢅꢆ
ꢀꢁꢂꢂꢃ
ꢀRꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ.ꢁꢂꢃ
ꢀꢁꢁꢂ
ꢀAꢁꢂꢃꢂꢃꢄꢅꢂꢆꢇꢈ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢆꢃꢇꢆꢁꢈ
ꢀ.ꢁꢂꢃꢄ
ꢀ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
2mΩ
ꢀ.ꢀꢁꢂ ꢃꢀ
ꢀꢁꢁꢂ
ꢀRꢁꢂꢃꢄ
ꢀꢁꢁꢂꢃ
ꢀꢁ.ꢂꢃ
ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢆꢃꢇꢆꢁꢈ
ꢀ.ꢁꢂꢃ
ꢀ.ꢁꢂꢃ
ꢀꢁ.ꢂꢃ
ꢀꢁꢂ
ꢃ
ꢀꢁꢂ
ꢀꢁꢂꢀꢁ
ꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀRꢁꢂꢁ
ꢀꢁꢂ
ꢀꢁꢂꢀꢁ
ꢀꢁ
ꢀꢁꢁꢂꢃ
ꢀꢀ
ꢀꢁ
ꢀ.ꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂ
549Ω
ꢃ
ꢀ
ꢀꢁꢁꢂꢃꢄ
ꢀꢁ
ꢀꢁꢂꢀꢁ
ꢀ.ꢁꢂꢃ
ꢃ
ꢀ
ꢀꢁꢂꢃA
ꢀ.ꢁꢂꢃ
ꢀꢁꢂꢀꢁ
ꢀ
ꢀꢁꢂ
ꢁꢂꢃꢁꢄꢅꢆꢇꢅꢆ
FꢀꢁLT
ꢀꢁꢁꢂꢃꢄ
ꢀ.ꢁꢂꢃꢄ
ꢀꢁ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢀ
ꢀꢁꢂꢃ
2.2Ω
ꢀ.ꢁꢂꢃ
ꢀ
ꢀꢁꢂ
ꢀꢀ
ꢀꢁꢂꢂꢃ
ꢀꢁꢁꢂꢃꢄ
ꢀꢁ
ꢀ.ꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂ
Rꢀꢁ
ꢀꢁꢂꢃA
ꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ.ꢀꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄRꢅꢆ
ꢀꢁ
ꢀꢁꢂꢃA
ꢀRꢁꢂ
ꢀꢁ
ꢀꢁꢁꢂ
ꢀꢁꢂꢃR
ꢀ
ꢁꢂꢃꢄꢅꢆꢇꢅꢆ
ꢀꢁ.ꢂꢃ
ꢀ.ꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀ.ꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁRꢂꢃꢄꢅꢂꢂꢆꢇ
ꢀ.ꢀꢁꢂ ꢃꢄꢅ
ꢀꢁꢁꢂ
ꢀꢁꢂꢃ ꢄꢅ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢄ
ꢀꢀ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂꢃꢄꢃꢅꢆꢁꢇ
FLT
ꢀꢁ
ꢀꢁꢂꢃA
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ.ꢂꢃ
ꢀꢁꢂꢃꢄꢃꢅꢃꢆꢇꢁꢈ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁRꢂꢃ
ꢀꢁꢂ
ꢀꢀ
ꢀꢁꢂꢃ ꢄꢅꢁ
ꢀ.ꢀꢁꢂ
ꢀꢁRꢂꢃꢄꢅꢂꢂꢆꢇ
ꢀꢁꢂ
ꢀꢁRꢂꢃꢄꢅꢂꢂꢆꢇ
ꢀꢁꢂꢃ ꢄꢅꢁ
ꢀ
ꢀꢁꢂ
ꢀꢀ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢄ
ꢀꢁꢂꢃꢄꢃꢅꢃꢆꢇꢁꢈ
FLT
ꢀꢁ
ꢀꢁꢂꢃA
ꢀꢁꢂ
ꢀꢁꢂꢃ ꢄꢅꢁ
ꢀꢁ
ꢀꢁ.ꢂꢃ
ꢀꢁꢂꢃꢄꢃꢅꢆꢇꢈꢁꢉ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂ
ꢀꢁ ꢂꢃ ꢄꢅꢅA
ꢀꢁRꢂꢃ
ꢀꢁꢂ
ꢀꢀ
ꢀꢁꢂꢃꢄ ꢅꢆ
ꢀ.ꢁꢂꢃ ꢄꢅꢆ
ꢀꢀꢁꢂ ꢃꢄꢅ
ꢀꢁꢂ
ꢀ.ꢀꢁꢂ
ꢀꢁRꢂꢃꢄꢅꢂꢂꢆꢇ
ꢀ.ꢁꢂꢃ
ꢀ.ꢀꢁꢂ
ꢀ.ꢀꢁꢂ
ꢀꢁRꢂꢃꢄꢅꢂꢂꢆꢇ
ꢀꢁRꢂꢃꢄꢅꢂꢂꢆꢇ
ꢀꢁRꢂꢃꢄꢅꢂꢂꢆꢇ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢀ
ꢀꢁꢂ
ꢀꢀ
ꢀꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂꢃꢄꢃꢅꢆꢇꢈꢁꢉ
ꢀꢁꢂꢃꢄꢃꢅꢆꢇꢈꢁꢉ
ꢀꢁꢂꢃꢄꢅꢄ
ꢀꢁꢂꢃꢄꢃꢅꢆꢇꢈꢁꢉ
ꢀꢁꢂꢃꢄꢅꢄ
ꢀꢁꢂꢃꢄꢅꢄ
FLT
FLT
FLT
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂꢃA
ꢀꢁꢂ
ꢀꢁꢂꢃA
ꢀꢁꢂ
ꢀꢁꢂꢃA
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ.ꢂꢃ
ꢀꢁ.ꢂꢃ
ꢀꢁ.ꢂꢃ
ꢀꢁꢂꢃꢄꢃꢅꢆꢇꢈꢁꢉ
ꢀꢁꢂꢃꢄꢃꢅꢆꢇꢈꢁꢉ
ꢀꢁꢂꢃꢄꢃꢅꢆꢇꢈꢁꢉ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁRꢂꢃ
ꢀꢁRꢂꢃ
ꢀꢁRꢂꢃ
ꢀꢁꢂ
ꢀꢀ
ꢀꢁꢂ
ꢀꢀ
ꢀꢁꢂ
ꢀꢀ
ꢀ.ꢁꢂꢃ
ꢀ.ꢁꢂꢃ
ꢀ.ꢁꢂꢃ
ꢀꢁꢂꢁ ꢃAꢁꢄ
Rev. A
15
For more information www.analog.com
LTC7060
PACKAGE DESCRIPTION
MSE Package
12-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1666 Rev G)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ±0.102
(.112 ±.004)
2.845 ±0.102
(.112 ±.004)
0.889 ±0.127
(.035 ±.005)
1
6
0.35
REF
1.651 ±0.102
(.065 ±.004)
5.10
(.201)
MIN
1.651 ±0.102
(.065 ±.004)
3.20 – 3.45
(.126 – .136)
0.12 REF
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
DETAIL “B”
12
7
0.65
(.0256)
BSC
0.42 ±0.038
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
(.0165 ±.0015)
TYP
0.406 ±0.076
RECOMMENDED SOLDER PAD LAYOUT
(.016 ±.003)
12 11 10 9 8 7
REF
DETAIL “A”
0.254
(.010)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
0° – 6° TYP
4.90 ±0.152
(.193 ±.006)
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
1
2 3 4 5 6
DETAIL “A”
0.86
(.034)
REF
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.1016 ±0.0508
(.004 ±.002)
MSOP (MSE12) 0213 REV G
0.650
(.0256)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL
NOT EXCEED 0.254mm (.010") PER SIDE.
Rev. A
16
For more information www.analog.com
LTC7060
REVISION HISTORY
REV
DATE
04/20 Updated Order Information.
changed from 64.9kΩ to 100kΩ in I
DESCRIPTION
PAGE NUMBER
A
2
3
R
DT
row.
VCC
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license isgrantedbyimplicationor otherwiseunderany patent or patent rights of Analog Devices.
17
LTC7060
TYPICAL APPLICATION
High Input Voltage Buck Converter
ꢀ.ꢁꢁꢂꢃ
ꢀ
ꢀꢀ
ꢀ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
10Ω
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢀ
ꢀ
ꢀꢁ
ꢀꢀ
ꢀꢁꢂꢃꢄꢅꢄ
ꢀ.ꢁꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂ
FLT
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁ
ꢀꢁ.ꢂꢃ
ꢀꢁRꢂꢃ
ꢀꢁꢂ
ꢀꢁRꢂꢃ ꢄꢂꢅꢆRꢂꢇꢇꢈR ꢉꢄꢊ
ꢀꢁꢂ
ꢀꢁꢂꢁ ꢃAꢁꢄ
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTC4449
High Speed Synchronous N-Channel MOSFET Driver
Up to 38V Supply Voltage, 4V ≤ V ≤ 6.5V, 3.2A Peak Pull-Up/4.5A Peak
CC
Pull-Down
LTC4442/
LTC4442-1
High Speed Synchronous N-Channel MOSFET Driver
Up to 38V Supply Voltage, 6V ≤ V ≤ 9.5V, 2.4A Peak Pull-Up/5A Peak
CC
Pull-Down
LTC4446
High Voltage Synchronous N-Channel MOSFET Driver
without Shoot-Through Protection
Up to 100V Supply Voltage, 7.2V ≤ V ≤ 13.5V, 2.5A Peak Pull-Up/3A Peak
CC
Pull-Down
LTC4444/
LTC4444-5
High Voltage Synchronous N-Channel MOSFET Driver
with Shoot-Through Protection
Up to 100V Supply Voltage, 4.5V/7.2V ≤ V ≤ 13.5V, 2.5A Peak Pull-Up/3A
CC
Peak Pull-Down
LTC3774
LTC3861
LTC7851
LTC7820
LTC7821
LTC7871
LTC7801
Dual, Mulitphase Curent Mode Synchronous Step-Down
DC/DC Controller for Sub-Milliohm DCR Sensing
Operates with DrMOS, Power Blocks or External Drivers/MOSFETs, 4.5V≤ V
IN
≤ 38V, 0.6V ≤ V
≤ 3.5V
OUT
Dual, Multiphase Step-Down Voltage Mode DC/DC
Controller with Accurate Current Sharing
Operates with Power Blocks, DrMOS or External MOSFETs, 3V≤ V ≤ 24V
IN
Quad Output, Multiphase Step-Down Voltage Mode DC/DC Operates with DrMOS, Power Blocks or External Drivers/MOSFETs, V Range
Controller with Accurate Current Sharing
IN
Depends on External Components, 3V≤ V ≤ 5.5V, 0.6V ≤ V
≤ V −0.5V
CC
OUT CC
Fixed Ratio High Power Inductorless (Charge Pump)
DC/DC Controller
6V ≤ V ≤ 72V, 2:1 Voltage Divider, 1:2 Voltage Doubler, 1:1 Voltage Inverter,
IN
Low Noise Soft Switching, 4mm × 5mm QFN-28
Hybrid Step-Down Synchronous Controller
10V ≤ V ≤ 72V, 0.9V ≤ V
≤ 20V, Low Noise Soft Switching, 5mm × 5mm
IN
OUT
QFN-32
Six-Phase, Synchronous Bidirectional Buck or Boost
Controller
V
HIGH
up to 100V, V
up to 60V, SPI Interface, 64-Lead LQFP
LOW
150V Low I , Synchronous Step-Down DC/DC Controller, 4V ≤ V ≤ 140V, 150V , 0.8V ≤ V
≤ 60V, I = 40µA, PLL Fixed
Q
Q
IN
PK
OUT
100% Duty Cycle Capability, Adjustable 5V to 10V Gate
Frequency 50kHz to 900kHz
Drive
Rev. A
05/20
www.analog.com
ANALOG DEVICES, INC. 2020
18
相关型号：
LTC7103EUHE#PBF
LTC7103 - 105V, 2.3A Low EMI Synchronous Step-Down Regulator; Package: QFN; Pins: 36; Temperature Range: -40°C to 85°C
Linear
LTC7103EUHE#TRPBF
LTC7103 - 105V, 2.3A Low EMI Synchronous Step-Down Regulator; Package: QFN; Pins: 36; Temperature Range: -40°C to 85°C
Linear
LTC7103HUHE#PBF
LTC7103 - 105V, 2.3A Low EMI Synchronous Step-Down Regulator; Package: QFN; Pins: 36; Temperature Range: -40°C to 125°C
Linear
LTC7103IUHE#PBF
LTC7103 - 105V, 2.3A Low EMI Synchronous Step-Down Regulator; Package: QFN; Pins: 36; Temperature Range: -40°C to 85°C
Linear
LTC7103IUHE#TRPBF
LTC7103 - 105V, 2.3A Low EMI Synchronous Step-Down Regulator; Package: QFN; Pins: 36; Temperature Range: -40°C to 85°C
Linear
LTC7103MPUHE#PBF
LTC7103 - 105V, 2.3A Low EMI Synchronous Step-Down Regulator; Package: QFN; Pins: 36; Temperature Range: -55°C to 125°C
Linear
©2020 ICPDF网 联系我们和版权申明