LTC7132IY [ADI]
25A, Dual PolyPhase Regulator with Digital Power System Management;
| 型号： | LTC7132IY |
| 厂家： | 
ADI |
| 描述： | 25A, Dual PolyPhase Regulator with Digital Power System Management |
| 文件： | 总118页 (文件大小：4190K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC7132
25A, Dual PolyPhase Regulator with
Digital Power System Management
FEATURES
DESCRIPTION
2
The LTC®7132 is a dual output PolyPhase DC/DC synchro-
n
PMBus/I CCompliantSerialInterface
2
–TelemetryRead-BackIncludesV ,I ,V ,I
TemperatureandFaults
,
nous step-down monolithic regulator with an I C-based
PMBus compliant serial interface. The regulator employs
a constant-frequency current mode architecture, together
with a unique scheme to provide excellent performance
in sub-milliohm DCR applications. The LTC7132 is sup-
ported by the LTpowerPlay® software development tool
with graphical user interface (GUI).
IN IN OUT OUT
–ProgrammableVoltage,CurrentLimit,DigitalSoft-
Start/Stop,Sequencing,Margining,OV/UV/OC
Sub-Milliohm DCR Current Sensing
Digitally Adjustable Loop Compensation Parameters
±±0.5OutputVoltageAccuracyOverTemperature
IntegratedInputCurrentSenseAmplifier
n
n
n
n
n
n
Programmable loop compensation allows the regulator to
be compensated digitally. The switching frequency, chan-
nel phasing and device address can be programmed both
by the digital interface as well as the external configura-
tion resistors. Additionally, parameters can be set via the
digital interface and stored in EEPROM. Both outputs have
independent power good indicators and FAULT function.
InternalEEPROMwithECCandFaultLogging
IntegratedN-ChannelMOSFETGateDrivers
PowerConversion
n
WideV Range:4.5Vto20V
OUT
IN
n
V
Range:0.5Vto3.5V(withUltralowDCRSetting);
0.5Vto5.5V(TypicalDCRSetting)
AccuratePolyPhase® CurrentSharingforUpto6Phases
Available in a 140-Lead (9mm × 11.25mm × 2.22mm)
BGA Package
n
n
The LTC7132 can be configured to operate in discontinu-
ous (pulse-skipping) mode or forced continuous conduc-
tion mode. Each channel can deliver up to 25A of load
current; the total current capability will depend on the
total power dissipations on both channels.
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents including 5481178, 5705919, 5929620, 6144194, 6177787, 6580258, 5408150,
7420359, 8648623, 8786265, 8823352, 7000125. Licensed under U.S. Patent 7000125 and
other related patents worldwide.
APPLICATIONS
n
Telecom, Datacom and Storage Systems
Industrial and Point-of-Load Applications
n
TYPICAL APPLICATION
1µF
1Ω
2mΩ
V
IN
4.5V TO 15V
Efficiency and Power Loss
vs Load Current
10µF
×2
10µF
×2
4.7µF
C10
+
–
D2
D4
INTV
PV
SV
I
I
IN
CC
IN IN
270µF
×2
PV
IN0
IN1
ꢀ00
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
0.1µF
0.1µF
ꢀꢁꢂꢃ ꢅ ꢆꢇꢆꢃ
ꢄꢄ
DCR = 0.29mΩ
L2 0.3µH
DCR = 0.29mΩ
L1 0.3µH
ꢃ
ꢍꢎ
ꢄꢄꢓ
ꢅ ꢊꢋꢃ
ꢈꢉ
BOOST0
SW0
SDA
SCL
BOOST1
SW1
FAULT0
FAULT1
PGOOD0
PGOOD1
SHARE_CLK
ꢌ
ꢅ ꢏꢋꢆꢐꢑꢒ
LTC7132*
FAULT MANAGEMENT
PMBus
ALERT
RUN0
RUN1
INTERFACE
TO/FROM
OTHER LTC DEVICES
EXTV
CC
931Ω
931Ω
+
+
I
I
SENSE0
SENSE1
0.22µF
0.22µF
–
–
+
I
V
I
V
SENSE0
SENSE1
SENSE1
V
V
OUT0
1.8V, 20A
OUT1
+
SENSE0
1V, 20A
330µF
×2
330µF
×2
100µF
×2
100µF
×2
–
–
V
V
SENSE0
SENSE1
0
ꢀ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀ0
TSNS0
TSNS1
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
7132 TA01a
I
I
I
TH0
TH_R0
TH1
TH_R1
PGND SGND V
ꢀꢁꢂꢃ ꢄꢅ0ꢁꢆ
150pF
150pF
I
ꢀꢙꢙꢈꢄꢈꢀꢉꢄꢚ
ꢔꢕꢎꢀR ꢖꢕꢍꢍ
C5
10nF
V
DD33
DD25
1500pF
ꢃ
ꢃ
ꢅ ꢊꢇꢘꢃ
ꢅ ꢊꢇ0ꢃ
ꢃ
ꢃ
ꢅ ꢊꢇꢘꢃ
ꢅ ꢊꢇ0ꢃ
ꢕꢗꢂ
ꢕꢗꢂ
ꢕꢗꢂ
ꢕꢗꢂ
4700pF
1µF
1µF
*SOME DETAILS OMITTED FOR CLARITY
Rev 0
1
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LTC7132
TABLE OF CONTENTS
Features00000000000000000000000000000000000000000000000000000 1
Applications 000000000000000000000000000000000000000000000000 1
Typical Application 0000000000000000000000000000000000000000 1
Description00000000000000000000000000000000000000000000000000 1
Table of Contents 000000000000000000000000000000000000000000 2
Absolute Maximum Ratings000000000000000000000000000000 4
Order Information000000000000000000000000000000000000000000 4
Pin Configuration 000000000000000000000000000000000000000000 4
Electrical Characteristics000000000000000000000000000000000 .
Typical Performance Characteristics 00000000000000000011
Pin Functions00000000000000000000000000000000000000000000001.
Block Diagram00000000000000000000000000000000000000000000017
Operation00000000000000000000000000000000000000000000000000018
Overview................................................................. 18
Main Control Loop.................................................. 19
EEPROM ................................................................. 19
Power-Up and Initialization .....................................20
Soft-Start................................................................20
Time-Based Sequencing.........................................21
Voltage-Based Sequencing.....................................21
Shutdown ...............................................................22
Light-Load Current Operation .................................22
Switching Frequency and Phase.............................22
PWM Loop Compensation......................................23
Output Voltage Sensing ..........................................23
Device Addressing..................................................30
Responses to V
and I /I Faults ...................30
OUT
IN OUT
Output Overvoltage Fault Response ...................31
Output Undervoltage Response..........................31
Peak Output Overcurrent Fault Response...........31
Responses to Timing Faults....................................31
Responses to V OV Faults....................................32
IN
Responses to OT/UT Faults.....................................32
Internal Overtemperature Fault Response ..........32
External Overtemperature and Undertemperature
Fault Response...................................................32
Responses to Input Overcurrent and Output
Undercurrent Faults................................................32
Responses to External Faults..................................32
Fault Logging..........................................................32
Bus Timeout Protection ..........................................33
2
Similarity Between PMBus, SMBus and I C 2-Wire
Interface .................................................................33
PMBus Serial Digital Interface................................33
PMBus Command Summary 000000000000000000000000000038
PMBus Commands.................................................38
*Data Format..........................................................43
Applications Information 0000000000000000000000000000000044
Current Limit Programming....................................44
I
and I
Pins......................................44
SENSE0
SENSE1
INTV /EXTV Power...........................................23
Inductor DCR Sensing ........................................45
CC
CC
Output Current Sensing and Sub-Milliohm DCR
Inductor Value Calculation ......................................46
Inductor Core Selection ..........................................46
Low Value Resistor Current Sensing.......................46
Slope Compensation and Inductor Peak Current ....47
Variable Delay Time, Soft-Start and Output Voltage
Ramping .................................................................48
Digital Servo Mode.................................................48
Soft Off (Sequenced Off)........................................49
Current Sensing......................................................24
Input Current Sensing.............................................25
PolyPhase Load Sharing.........................................25
External/Internal Temperature Sense......................25
RCONFIG (Resistor Configuration) Pins..................26
Fault Detection and Handling..................................27
Status Registers and ALERT Masking.................27
Mapping Faults to FAULT Pins ............................29
Power Good Pins................................................29
CRC Protection...................................................29
Serial Interface .......................................................29
Communication Protection.................................30
INTV /EXTV Power...........................................49
CC
CC
Topside MOSFET Driver Supply (C , D ) ................50
B
B
Undervoltage Lockout.............................................50
C and C
Selection ........................................... 51
IN
OUT
Fault INDICATION.................................................... 51
Rev 0
2
For more information www.analog.com
LTC7132
TABLE OF CONTENTS
Open-Drain Pins .....................................................52
Phase-Locked Loop and Frequency Synchronization .
53
Input Current and Limits ....................................82
Temperature............................................................82
External Temperature Calibration........................82
Timing ....................................................................84
Timing—On Sequence/Ramp.............................84
Timing—Off Sequence/Ramp ............................85
Precondition for Restart.....................................86
Fault Response .......................................................86
Fault Responses All Faults..................................86
Fault Responses Input Voltage ...........................87
Fault Responses Output Voltage.........................87
Fault Responses Output Current.........................90
Fault Responses IC Temperature ........................91
Fault Responses External Temperature...............92
Fault Sharing...........................................................93
Fault Sharing Propagation ..................................93
Fault Sharing Response......................................95
Scratchpad .............................................................95
Identification...........................................................96
Fault Warning and Status........................................97
Telemetry..............................................................104
NVM Memory Commands .................................... 108
Store/Restore ................................................... 108
Fault Logging.................................................... 109
Block Memory Write/Read................................ 112
Typical Applications000000000000000000000000000000000000 113
Package Description 00000000000000000000000000000000000 117
Typical Application 0000000000000000000000000000000000000 118
Related Parts00000000000000000000000000000000000000000000 118
Minimum On-Time Considerations..........................53
External Temperature Sense...................................54
Input Current Sense Amplifier.................................54
External Resistor Configuration Pins (RCONFIG)....55
Voltage Selection................................................55
Frequency Selection ...........................................56
Phase Selection..................................................56
Address Selection Using RCONFIG.....................57
Efficiency Considerations .......................................57
Thermal Considerations .........................................58
Programmable Loop Compensation .......................59
Checking Transient Response.................................59
PolyPhase Configuration ....................................60
PC Board Layout Checklist .....................................61
PC Board Layout Debugging...................................61
Design Example......................................................63
Additional Design Checks .......................................64
2
Connecting the USB to I C/SMBus/PMBus Controller
to the LTC7132 in System.......................................64
LTpowerPlay: An Interactive GUI for Digital Power .65
PMBus Communication and Command Processing65
PMBus Command Details 000000000000000000000000000000068
Addressing and Write Protect.................................68
General Configuration Commands..........................70
On/Off/Margin ........................................................71
PWM Configuration ................................................73
Voltage....................................................................76
Input Voltage and Limits.....................................76
Output Voltage and Limits..................................77
Output Current and Limits ......................................80
Rev 0
3
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LTC7132
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
ꢝꢦꢁ ꢥꢤꢄꢣ
+
–
SV , PV , PV , I , I ...................... –0.3V to 20V
IN
IN0
IN1 IN IN
+
+ –
(V –I ), (I –I ) ................................ –0.3V to 0.3V
IN IN
IN
IN
BOOST0, BOOST1...................................... –0.3V to 26V
Switch Transient Voltage (SW0, SW1) .......... –5V to 26V
ꢥ
ꢫ
ꢫ
ꢍ
ꢎ
ꢨꢄꢌꢨꢄ0
+
–
+
–
ꢤ
ꢤ
ꢫ
ꢬ
ꢤꢌ
ꢤꢌ
I
V
V
, I
, I
, I
,
SENSE0 SENSE0
SENSE1 SENSE1
...................................... –0.3V to 6V
................................... –0.3V to 0.3V
+
+
ꢌꢂ
ꢌꢂ
ꢁꢆꢦꢦꢃ0
ꢎꢦꢦꢨꢝ0
ꢨꢣ0
, V
SENSE0
SENSE0
SENSE1
SENSE1
ꢂ
ꢃ
ꢄ
Rꢪꢌ0
Rꢪꢌꢀ
ꢍꢨꢄꢊ0
–
–
ꢨꢥ
ꢤꢌ
ꢄꢞꢝꢥꢂꢂ
ꢁꢆꢌꢃ
ꢥ
ꢤꢌꢝꢥ
, V
ꢤ
ꢣꢁ
ꢝꢇꢀ
ꢨꢄꢌꢨꢄꢀ
ꢂꢂ
(BOOST0-SW0), (BOOST1-SW1) ................. –0.3V to 6V
EXTV , INTV ........................................... –0.3V to 6V
PGOOD0, PGOOD1.................................... –0.3V to 3.6V
RUN0, RUN1, SDA, SCL, ALERT ................ –0.3V to 5.5V
ꢅRꢄꢮꢭꢂꢅꢆ
ꢍꢨꢄꢊꢀ
ꢁꢇꢍꢨꢄꢭꢂꢅꢆ
ꢌꢂ
ꢤ
ꢝꢇRꢀ
ꢁꢆꢦꢦꢃꢀ
ꢎꢦꢦꢨꢝꢀ
ꢨꢣꢀ
ꢨꢇꢍRꢄꢭꢂꢊꢉ
CC
CC
ꢅ
ꢥ
ꢦꢪꢝꢀꢭꢂꢅꢆ
ꢥ
ꢥ
ꢌꢂ
ꢥ
ꢬ
ꢃꢃꢖꢓ
ꢃꢃꢕꢕ
ꢨꢄꢌꢨꢄꢀ
ꢆ
ꢇ
ꢈ
ꢁꢥ
ꢤꢌ0
ꢁꢆꢌꢃ
ASEL0, ASEL1, V
, V
, FREQ_CFG,
OUT0_CFG0 OUT1_CFG
ꢁꢥ
ꢁꢆꢌꢃ
ꢨꢣ0
ꢤꢌꢀ
PHASE_CFG............................................ –0.3V to 2.75V
FAULT0, FAULT1, SHARE_CLK, WP, SYNC –0.3V to 3.6V
TSNS0, TSNS1.......................................... –0.3V to 2.2V
ꢉ
ꢊ
ꢋ
ꢌ
ꢁ
I
, I , I
, I
.............................. –0.3V to 2.7V
TH0 TH1 THR0 THR1
Operating Junction Temperature Range
ꢨꢣꢀ
(Notes 2, 17, 18).......................................–40°C to 125°C
ꢀ
ꢖ
ꢕ
ꢔ
ꢓ
ꢒ
ꢎꢆꢍ ꢁꢍꢂꢉꢍꢆꢄ
ꢀꢔ0ꢗꢊꢄꢍꢃ ꢘꢀꢀꢙꢖꢓꢚꢚ ꢛ ꢏꢙ00ꢚꢚ ꢛ ꢖꢙꢖꢖꢚꢚꢜ
ꢟ ꢀꢖꢓꢠꢂꢡ θ ꢟ ꢀꢔꢙꢓꢠꢂꢢꢣꢡ θ ꢟ ꢀꢙꢀꢠꢂꢢꢣ
ꢑ
ꢐ
ꢏ
ꢀ0
Storage Temperature Range .................. –40°C to 125°C
*See Derating EEPROM Retention at Temperature in Applications
Information section for junction temperatures in excess of 125°C.
ꢝ
ꢈꢋꢍꢞ
θ
ꢈꢍ
ꢈꢂ
ꢃꢄRꢤꢥꢄꢃ ꢅRꢦꢋ ꢊꢝꢂꢑꢀꢕꢖ ꢃꢄꢋꢦ ꢎꢦꢍRꢃ
ꢣꢄꢤꢆꢇꢝ ꢟ 0ꢙꢓꢖꢧ
ꢈꢍ
ꢌꢂ ꢘꢁꢤꢌꢨ ꢎꢖꢡ ꢎꢔꢡ ꢄꢐꢡ ꢄꢏꢡ ꢅꢒꢜ ꢍRꢄ ꢌꢦ ꢂꢦꢌꢌꢄꢂ ꢡ ꢁꢤꢌꢨ ꢍRꢄ ꢌꢦꢝ
ꢂꢦꢌꢌꢄꢂꢝꢄꢃ ꢤꢌꢝꢄRꢌꢍꢊꢊꢩꢙ ꢅꢊꢦꢍꢝ ꢦR ꢆRꢦꢪꢌꢃ ꢝꢇꢄꢨꢄ ꢁꢤꢌꢨ
ORDER INFORMATION
PART MARKING*
PACKAGE
TYPE
MSL
RATING
TEMPERATURE RANGE
(SEE NOTE 2)
PART NUMBER
LTC7132EY#PBF
LTC7132IY#PBF
PAD OR BALL FINISH
DEVICE
FINISH CODE
SAC305 (RoHS)
LTC7132Y
e1
BGA
4
–40°C to 125°C
• Contact the factory for parts specified with wider operating temperature
ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures
• LGA and BGA Package and Tray Drawings
Rev 0
4
For more information www.analog.com
LTC7132
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 2.°C (Note 2)0 VIN = 12V, EXTVCC = ±V, VRUN±,1 = 303V,
fSYNC = .±±kHz (externally driven) and all programmable parameters at factory default, unless otherwise specified0
SYMBOL
PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
Input Voltage
l
SV , PV
IN
Input Voltage Range
(Note 11)
4.5
20
V
IN0/1
I
Q
Input Voltage Supply Current
V
V
= 3.3V (Note 16)
= 0V (Note 16)
25
23
mA
mA
RUN0,1
RUN0,1
V
Undervoltage Lockout Threshold
V
V
Falling
Rising
3.55
3.90
V
V
UVLO
INTVCC
INTVCC
When V > 4.3V
IN
t
t
Initialization Time
Time from V Applied Until the TON_DELAY
35
ms
INIT
IN
Timer Starts
Short Cycle Retry Time
120
ms
OFF(MIN)
Control Loop
V
Range 1 Maximum V
0.6V ≤ V ≤ 2.5V
OUT
2.75
V
%
OUTRL
OUT
l
Set Point Accuracy (0.6V ~ 2.5V)
Resolution
MFR_PWM_MODE[1] = 1
(Notes 9, 10, 13)
–0.5
–0.5
0.5
12
0.688
Bits
mV
LSB Step Size
l
l
V
Range 0 Maximum V
1.2V ≤ V
≤ 5.5V
5.5
V
%
Bits
mV
OUTRH
OUT
OUT
Set Point Accuracy (0.6V ~ 5.0V)
Resolution
MFR_PWM_MODE[1] = 0
(Notes 9, 10, 13)
0.5
12
1.375
LSB Step Size
l
V
V
Line Regulation
Load Regulation
6V < V < 20V
0.02
%/V
LINEREG
IN
l
l
∆V = 1.35V ~ 0.7V
0.01
–0.01
0.1
–0.1
%
%
LOADREG
ITH
∆V = 1.35V ~ 2V
ITH
l
I
Input Pin Bias Current
0V ≤ V ≤ 5.5V
1
50
3
µA
kΩ
mV
ISENSE0,1
PIN
V
V
V
V
Input Resistance to GND
0V ≤ V ≤ 5.5V
PIN
SENSERIN0,1
SENSE
l
MFR_PWM_MODE[7],[2]=0, 1, I [3:0]=1100, V ≤ 3.5V
14.5
16.5
18.5
ILIMIT
ILIM_HIGH
LIM
OUT
(Note 15)
MFR_PWM_MODE[7],[2]=0, 1, I [3:0]=0001, V ≤ 3.5V
V
V
9.5
–7.5
mV
mV
ILIM_LOW
REV
LIM
OUT
OUT
MFR_PWM_MODE[7],[2]=0, 1, V ≥ V
OV
l
l
l
V
V
V
MFR_PWM_MODE[7][2]=1, 1, I [3:0]=1100,V ≤ 3.5V
27.0
35
29.5
17.0
–15
31.0
49
mV
mV
mV
ILIM_HIGH
ILIM_LOW
REV
LIM
OUT
MFR_PWM_MODE[7][2]=1, 1, I [3:0]=0001,V ≤ 3.5V
LIM
OUT
MFR_PWM_MODE[7][2]=1, 1, V ≥ V
OUT
OV
V
V
V
MFR_PWM_MODE[7][2]=0, 0, I [3:0]=1100
41.38
25
–18.8
mV
mV
mV
ILIM_HIGH
ILIM_LOW
REV
LIM
MFR_PWM_MODE[7][2]=0, 0, I [3:0]=0001
LIM
MFR_PWM_MODE[7][2]=0, 0, V ≥ V
OUT
OV
V
V
V
MFR_PWM_MODE[7][2]=1, 0, I [3:0]=1100
67.5
74.5
43.5
–37.5
81.5
mV
mV
mV
ILIM_HIGH
ILIM_LOW
REV
LIM
MFR_PWM_MODE[7][2]=1, 0, I [3:0]=0001
LIM
MFR_PWM_MODE[7][2]=1, 0, V ≥ V
OUT
OV
g
Resolution
I
= 1.35V, MFR_PWM_CONFIG[7:5] = 0 to 7
3
Bits
mmho
mmho
mmho
m0,1
TH0,1
Error Amplifier g
Error Amplifier g
LSB Step Size
4.6
0.8
0.54
m(MAX)
m(MIN)
R
Resolution
Compensation Resistor R
Compensation Resistor R
MFR_PWM_CONFIG[4:0] = 0 to 31 (See Figure 1)
5
62
0
Bits
kΩ
kΩ
TH0, 1
TH(MAX)
TH(MIN)
t
Minimum On-Time
90
ns
ON(MIN)
R
R
R
DS(ON)
Top Power NMOS On-Resistance
7.3
2.1
mΩ
mΩ
TOP
Bottom Power NMOS On-Resistance
BOTTOM
Rev 0
5
For more information www.analog.com
LTC7132
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 2.°C (Note 2)0 VIN = 12V, EXTVCC = ±V, VRUN±,1 = 303V,
fSYNC = .±±kHz (externally driven) and all programmable parameters at factory default, unless otherwise specified0
SYMBOL
PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
OV/UV Output Voltage Supervisor Channel ±/1
N
Resolution
9
Bits
mV
mV
V
V
V
V
V
V
V
LSB Step Size
MFR_PWM_MODE[1] = 1 (Note 13)
MFR_PWM_MODE[1] = 0 (Note 13)
MFR_PWM_MODE[1] = 1
5.6
OUSTPSP_RL
OUSTPSP_RH
RANGE_RL
RANGE_RH
THAC0_RL
THAC1_RH
PROPOV
LSB Step Size
11.2
2.86
5.74
Range 0 Maximum Threshold
Range 1 Maximum Threshold
MFR_PWM_MODE[1] = 0
V
l
l
Threshold Accuracy 1V < V
< 2.75V MFR_PWM_MODE[1] = 1
1.5
1.5
%
OUT
Threshold Accuracy 2V < V < 5.5V MFR_PWM_MODE[1] = 0
%
OUT
t
t
OV Comparator Response Time
UV Comparator Response Time
V
OD
V
OD
= 10% of Threshold
= 10% of Threshold
100
100
µs
µs
PROPUV
V
IN
Voltage Supervisor
N
Resolution
9
Bits
mV
V
V
V
V
LSB Step Size
Full-Scale Voltage
76
20
INSTP
IN
l
l
Threshold Accuracy 9V < V < 20V
Threshold Accuracy 4.5V < V ≤ 9V
3
6.0
%
%
INTHACCM
IN
IN
t
Comparator Response Time
(VIN_ON and VIN_OFF)
V
= 10% of threshold
= 0 (Note 8)
100
µs
PROPVIN
OD
Output Voltage Readback
N
Resolution
16
244
8
Bits
µV
V
V
V
V
V
LSB Step Size
OUTSTP
F/S
Full-Scale Sense Voltage
Total Unadjusted Error
Zero-Code Offset Voltage
Update Rate
V
V
RUNn
l
l
> 0.6V (Note 8)
OUT
–0.5
0.5
%
OUT_TUE
OS
500
µV
ms
t
(Note 6)
90
CONVERT
V
IN
Voltage Readback
N
Resolution
(Note 5)
10
20
Bits
V
V
V
Full-Scale Input Voltage
Total Unadjusted Error
(Note 11)
F/S
V
VIN
> 4.5V (Note 8)
0.5
2
%
%
INTUE
l
t
Update Rate
(Note 6)
90
10
ms
CONVERT
Output Current Readback
N
Resolution
(Note 5)
Bits
+
–
V
LSB Step Size
0V ≤ |V
– V
| < 16mV
15.63
31.25
62.5
µV
µV
µV
µV
IOUTSTP
ISENSE
ISENSE
+
–
16mV ≤ |V
32mV ≤ |V
64mV ≤ |V
– V
– V
– V
| < 32mV
| < 64mV
| < 100mV
ISENSE
ISENSE
ISENSE
ISENSE
ISENSE
ISENSE
+
+
–
–
125
I
I
Full-Scale Input Current
Total Unadjusted Error
Zero-Code Offset Voltage
Update Rate
(Note 7) DCR or R
= 1mΩ
100
A
%
F/S
ISENSE
+
–
l
100mV > (V
– V
) > 6mV (Note 8)
1.25
50
OUT_TUE
ISENSE
ISENSE
V
µV
ms
OS
t
(Note 6)
90
CONVERT
Rev 0
6
For more information www.analog.com
LTC7132
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 2.°C (Note 2)0 VIN = 12V, EXTVCC = ±V, VRUN±,1 = 303V,
fSYNC = .±±kHz (externally driven) and all programmable parameters at factory default, unless otherwise specified0
SYMBOL
Input Current Readback
Resolution
PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
N
(Note 5)
10
Bits
+
+
+
–
V
IINSTP
LSB Step Size Full-Scale Range = 16mV Gain = 8, 0V ≤ |V
LSB Step Size Full-Scale Range = 32mV Gain = 4, 0V ≤ |V
LSB Step Size Full-Scale Range = 64mV Gain = 2, 0V ≤ |V
– V | ≤ 5mV
15.26
30.52
61
µV
µV
µV
IIN
IIN
IIN
IIN
–
–
– V | ≤ 20mV
IIN
– V | ≤ 50mV
IIN
+
–
I
Total Unadjusted Error
Gain = 8, 2.5mV ≤ |V
– V | ≤ 5mV (Note 8)
2
1.3
1.2
%
%
%
IN_TUE
IIN
IIN
+
–
Gain = 4, 4mV ≤ |V
Gain = 2, 6mV ≤ |V
– V | ≤ 20mV (Note 8)
– V | ≤ 50mV (Note 8)
IIN
IIN
IIN
+
–
IIN
V
Zero-Code Offset Voltage
Update Rate
50
µV
OS
t
(Note 6)
(Note 5)
90
ms
CONVERT
Supply Current Readback
N
Resolution
10
Bits
µV
V
LSB Step Size Full-Scale Range =
256mV
244
ICHIPSTP
+
l
I
t
Total Unadjusted Error
Update Rate
20mV ≤ |V
(Note 6)
– V | ≤ 150mV (Note 19)
3
%
CHIPTUE
IIN
IN
90
ms
CONVERT
Temperature Readback (T±, T1)
T
Resolution
0.25
°C
RES_T
T0_TUE
External Temperature Total
Unadjusted Readback Error
TSNS0, TSNS1 ≤ 1.85V (Note 8)
MFR_PWM_MODE_[5] = 0
MFR_PWM_MODE_[5] = 1 (Note 14)
l
l
–3
–10
3
10
°C
°C
T1_TUE
Internal TSNS TUE
Update Rate
V
= 0.0, f
= 0kHz (Note 8)
SYNC
1
°C
RUN0,1
t
(Note 6)
100
ms
CONVERT
INTV Regulator/EXTV
CC
CC
l
l
V
V
V
V
V
V
Internal V Voltage No Load
6V ≤ V ≤ 20V
5.25
4.5
5.5
0.5
4.7
290
50
5.75
2
V
%
INTVCC
CC
IN
INTV Load Regulation
I = 0mA to 20mA, 6V ≤ V ≤ 20V
CC IN
LDO_INT
EXTVCC
LDO_HYS
LDO_EXT
IN_THR
CC
EXTV Switchover Voltage
V
IN
≥ 7V, EXTV Rising
4.9
V
CC
CC
EXTV Hysteresis
mV
mV
V
CC
EXTV Voltage Drop
I
= 20mA, V
Rising
= 5.5V
EXTVCC
100
7.4
CC
CC
V
Threshold to Enable EXTV
V
IN
CC
IN
Switchover
V
V
Hysteresis to Disable EXTV
V
IN
Rising – V Falling
600
mV
IN_HYS
IN
CC
IN
Switchover
V
Regulator
DD33
DD33
LIM
V
Internal V
Voltage
4.5V < V
or 4.8V < V
EXTVCC
3.2
3.3
100
3.5
3.1
3.4
V
mA
V
DD33
INTVCC
I
V
V
V
Current Limit
V
= GND, V = INTV = 4.5V
IN CC
DD33
DD33
DD33
DD33
DD25
V
V
V
V
Overvoltage Threshold
DD33_OV
Undervoltage Threshold
V
DD33_UV
Regulator
DD2.
DD25
LIM
Internal V
Voltage
2.5
80
V
DD25
I
V
Current Limit
V
= GND, V = INTV = 4.5V
mA
DD25
IN
CC
Rev 0
7
For more information www.analog.com
LTC7132
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 2.°C (Note 2)0 VIN = 12V, EXTVCC = ±V, VRUN±,1 = 303V,
fSYNC = .±±kHz (externally driven) and all programmable parameters at factory default, unless otherwise specified0
SYMBOL
PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
Oscillator and Phase-Locked Loop
l
l
f
f
PLL SYNC Range
Syncronized with Falling Edge of SYNC
Frequency Switch = 250kHz to 1000kHz
200
1000
7.5
kHz
%
RANGE
Oscillator Frequency Accuracy
SYNC Input Threshold
OSC
V
V
SYNC
V
SYNC
Falling
Rising
1
1.5
V
V
TH(SYNC)
V
SYNC Low Output Voltage
I
= 3mA
0.2
0.4
5
V
OL(SYNC)
LOAD
I
SYNC Leakage Current in Slave Mode 0V ≤ V ≤ 3.6V
µA
LEAK(SYNC)
PIN
θSYNC-θ0
SYNC to Ch0 Phase Relationship
Based on the Falling Edge of Sync
and Rising Edge of TG0
MFR_PWM_CONFIG[2:0] = 0,2,3
0
Deg
Deg
Deg
Deg
MFR_PWM_CONFIG[2:0] = 5
MFR_PWM_CONFIG[2:0] = 1
MFR_PWM_CONFIG[2:0]= 4,6
60
90
120
θSYNC-θ1
SYNC to Ch1 Phase Relationship
Based on the Falling Edge of Sync
and Rising Edge of TG1
MFR_PWM_CONFIG[2:0] = 3
MFR_PWM_CONFIG[2:0] = 0
MFR_PWM_CONFIG[2:0] = 2,4,5
MFR_PWM_CONFIG[2:0] = 1
MFR_PWM_CONFIG[2:0] = 6
120
180
240
270
300
Deg
Deg
Deg
Deg
Deg
EEPROM Characteristics
l
l
l
Endurance
Retention
(Note 12)
(Note 12)
0°C < T < 85°C EEPROM Write Operations
10,000
10
Cycles
Years
ms
J
T < 125°C
J
Mass_Write Mass Write Operation Time
STORE_USER_ALL, 0°C < T < 85°C
440
4100
J
During EEPROM Write Operation
Leakage Current SDA, SCL, ALERT, RUN
l
l
I
Input Leakage Current
Leakage Current FAULTn, PGOODn
Input Leakage Current
Digital Inputs SCL, SDA, RUNn, FAULTn
OV ≤ V ≤ 5.5V
5
2
µA
µA
OL
PIN
I
GL
OV ≤ V ≤ 3.6V
PIN
l
l
V
V
V
C
Input High Threshold Voltage
Input Low Threshold Voltage
Input Hysteresis
1.35
V
V
IH
0.8
IL
SCL, SDA
WP
0.08
10
V
HYST
PIN
Input Capacitance
10
pF
Digital Input WP
Input Pull-Up Current
I
µA
V
PUWP
Open-Drain Outputs SCL, SDA, FAULTn, ALERT, RUNn, SHARE_CLK, PGOODn
V
OL
Output Low Voltage
I
= 3mA
0.4
1.8
SINK
Digital Inputs SHARE_CLK, WP
l
l
V
V
Input High Threshold Voltage
Input Low Threshold Voltage
1.5
1
V
V
IH
0.6
IL
Digital Filtering of FAULTn
Input Digital Filtering FAULTn
I
3
µs
FLTG
Rev 0
8
For more information www.analog.com
LTC7132
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 2.°C (Note 2)0 VIN = 12V, EXTVCC = ±V, VRUN±,1 = 303V,
fSYNC = .±±kHz (externally driven) and all programmable parameters at factory default, unless otherwise specified0
SYMBOL
Digital Filtering of PGOODn
Output Digital Filtering PGOODn
Digital Filtering of RUNn
Input Digital Filtering RUN
PMBus Interface Timing Characteristics
PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
I
60
µs
FLTG
I
10
µs
FLTG
l
l
f
t
Serial Bus Operating Frequency
10
400
kHz
µs
SCL
BUF
Bus Free Time Between Stop and
Start
1.3
l
t
Hold Time After Repeated Start
Condition After This Period, the First
Clock is Generated
0.6
µs
HD(STA)
l
l
t
t
t
Repeated Start Condition Setup Time
Stop Condition Setup Time
0.6
0.6
10000
0.9
µs
µs
SU(STA)
SU(ST0)
HD(DAT)
Data Hold Time
Receiving Data
Transmitting Data
l
l
0
0.3
µs
µs
t
t
Data Setup Time
Receiving Data
SU(DAT)
0.1
µs
Stuck PMBus Timer Non-Block Reads Measured from the Last PMBus Start Event
Stuck PMBus Timer Block Reads
32
255
ms
TIMEOUT_SMB
l
l
t
t
Serial Clock Low Period
Serial Clock High Period
1.3
0.6
10000
µs
µs
LOW
HIGH
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels. C
design.
= 3500pF is guaranteed by
LOAD
Note .: The data format in PMBus is 5 bits exponent (signed) and 11 bits
mantissa (signed). This limits the output resolution to 10 bits though the
internal ADC is 16 bits and the calculations use 32-bit words.
Note 2: The LTC7132 is tested under pulsed load conditions such that T ≈
J
T . The LTC7132E is guaranteed to meet performance specifications from
A
0°C to 85°C. Specifications over the –40°C to 125°C operating junction
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC7132I is guaranteed over the full
Note 6: The data conversion is done by default in round robin fashion. All
inputs signals are continuously converted for a typical latency of 90ms.
Setting MFR_ADC_CONTRL value to be 0 to 12, LTC7132 can do fast data
conversion with only 8ms to 10ms. See section PMBus Command for
details.
Note 7: The IOUT_CAL_GAIN = 1.0mΩ and MFR_IOUT_TC = 0.0. Value as
read from READ_IOUT in Amperes.
–40°C to 125°C operating junction temperature range. T is calculated from
J
the ambient temperature T and power dissipation P according to the
A
D
following formula:
T = T + (P • θ )
JA
J
A
D
The maximum ambient temperature consistent with these specifications is
determined by specific operating conditions in conjunction with board layout,
the rated package thermal impedance and other environmental factors.
Note 8: Part tested with PWM disabled. Evaluation in application
demonstrates capability. TUE(%) = ADC Gain Error (%) +100 •
(Zero code Offset + ADC Linearity Error)/Actual Value.
Note 3: All currents into device pins are positive; all currents out of device pins
are negative. All voltages are referenced to ground unless otherwise specified
Note 9: All V
commands assume the ADC is used to auto zero the
OUT
output to achieve the stated accuracy. LTC7132 is tested in a feedback
loop that servos V to a specified value.
OUT
Rev 0
9
For more information www.analog.com
LTC7132
ELECTRICAL CHARACTERISTICS
Note 1±: The maximum programmable V
voltage is 5.5V when the
Note 17: The LTC7132 includes overtemperature protection that is
intended to protect the device during momentary overload conditions.
Junction temperature will exceed 125°C when overtemperature protection
is active. Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
OUT
output voltage range is High and 2.75V when the output voltage range is
Low.
Note 11: The maximum V voltage is 20V.
IN
Note 12: EEPROM endurance and retention are guaranteed by design,
characterization and correlation with statistical process controls. Data
retention is production tested via a high temperature at wafer level. The
minimum retention specification applies for devices whose EEPROM
has been cycled less than the minimum endurance specification. The
RESTORE_USER_ALL command (NVM read) is valid over the entire
operating junction temperature range.
Note 18: Write operations above T = 85°C or below 0°C are possible
J
although the Electrical Characteristics are not guaranteed and the EEPROM
will be degraded. Read operations performed at temperatures below 125°C
will not degrade the EEPROM. Writing to the EEPROM above 85°C will
result in a degradation of retention characteristics.
Note 19: Properly adjust the input current sensing resistor R to set the
VIN
sensing voltage within the maximum voltage of 150mV.
Note 13: MFR_PWM_MODE[1]=1 or 0 sets the output voltage range Low
or High.
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
Note 14: MFR_PWM_MODE_[5] = 0 or 1 sets the temperature
measurement method through ∆V , or through 2V
Note 1.: MFR_PWM_MODE[2] = 1 or 0 sets device in ultralow DCR mode
or typical DCR mode respectively. MFR_PWM_MODE[7]=1 or 0 sets device
in high output current range or low current range. See “Output Current
Sensing and Sub-Milliohm DCR Current Sensing” in Operation Section for
.
BE
BE
details. Only V
codes 1-9 are supported for DCR sensing.
LIMIT
Note 16: The LTC7132 quiescent current (I ) equals the I of V plus the
I of EXTV
Q
Q
Q
IN
.
CC
0
0
ꢀ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ ꢄ0ꢁ
Figure 10 Programmable RTH
Rev 0
10
For more information www.analog.com
LTC7132
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 12V, L = 0 .3µH, DCR = 0 .29mΩ, EXTVCC = 0 V unless otherwise noted.
Efficiency vs Load Current
Efficiency vs Load Current
Power Loss vs Load Current
ꢀ00
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ00
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
0
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀ ꢁꢂꢃꢄ
ꢀ ꢁꢂꢃꢄ
ꢀ ꢁꢂ0ꢃ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀ ꢁꢂꢃꢄ
ꢀ ꢁꢂꢃꢄ
ꢀ ꢁꢂ0ꢃ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀ ꢁꢂꢃꢄ
ꢀ ꢁꢂꢃꢄ
ꢀ ꢁꢂ0ꢃ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ0 ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀ0
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ0 ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀ0
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ0 ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀ0
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄ0ꢁ
ꢀꢁꢂꢃ ꢄ0ꢃ
ꢀꢁꢂꢃ ꢄ0ꢂ
Efficiency and Power Loss vs
Load Current
Load Step
Power Loss vs Output Current
(Forced Continuous Mode)
ꢀ00
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢀ
ꢀ0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
0
ꢀ
ꢁꢂꢃ
ꢄ00ꢅꢀꢆꢇꢈꢀ
ꢉꢊꢋꢊꢁꢂꢌꢍꢎꢇ
ꢀꢁꢁꢂꢃꢂꢀꢄꢃꢅ
0
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃ ꢄ0ꢅ
ꢀ ꢁꢂꢃꢄ
ꢀ ꢁꢂꢃꢄ
ꢀ ꢁꢂ0ꢃ
ꢀ0ꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃR ꢄꢁꢅꢅ
0
ꢀ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ0 ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀ0
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄ0ꢅ
ꢀꢁꢂꢃ ꢄ0ꢅ
Load Step
(Discontinuous Mode)
Inductor Current at Light Load
ꢀ
ꢁꢂꢃ
ꢀꢁRꢂꢃꢄ
ꢄ00ꢅꢀꢆꢇꢈꢀ
ꢉꢊꢋꢊꢁꢂꢌꢍꢎꢇ
ꢀꢁꢂꢃꢄꢂꢅꢁꢅꢆ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢅ
0
0
ꢀꢁꢂꢃꢄꢅꢆꢁꢅꢇꢄꢇꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃ ꢄ0ꢀ
ꢀꢁꢂꢃ ꢄ0ꢅ
ꢀ0ꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆ
Rev 0
11
For more information www.analog.com
LTC7132
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 12V, L = 0 .3µH, DCR = 0 .29mΩ, EXTVCC = 0 V unless otherwise noted.
Soft-Start Ramp
Start-Up Into a Pre-Biased Output
Soft-Off Ramp
Rꢀꢁ
ꢂꢃꢄꢅꢆꢃ
0ꢃ
Rꢀꢁ
ꢂꢃꢄꢅꢆꢃ
0ꢃ
Rꢀꢁ
ꢂꢃꢄꢅꢆꢃ
0ꢃ
ꢃ
ꢃ
ꢃ
ꢇꢀꢈ
ꢇꢀꢈ
ꢇꢀꢈ
ꢉꢃꢄꢅꢆꢃ
0ꢃ
ꢉꢃꢄꢅꢆꢃ
0ꢃ
ꢉꢃꢄꢅꢆꢃ
0ꢃ
ꢗꢉꢘꢂ ꢙ0ꢚ
ꢕꢉꢖꢂ ꢗꢉꢉ
ꢔꢉꢕꢂ ꢖꢉ0
ꢊꢋꢌꢄꢅꢆꢃ
ꢊꢋꢌꢄꢅꢆꢃ
ꢊꢋꢌꢄꢅꢆꢃ
ꢍ
ꢍ
ꢑ ꢉ0ꢋꢌ
ꢑ ꢊꢋꢌ
ꢍ
ꢒ ꢊꢋꢌ
ꢇꢎꢎꢏꢎꢐꢑꢑ
ꢍ
ꢑ ꢉ0ꢋꢌ
ꢇꢁꢎRꢆꢏꢐ
ꢇꢁꢎRꢆꢏꢐ
ꢇꢀꢈ
ꢍ
ꢒ ꢉ0ꢋꢌ
ꢇꢎꢎꢏꢅꢓꢑꢐꢔ
ꢃ
ꢑ ꢉꢒꢓꢃ
ꢇꢁꢎꢅꢐꢒꢓꢔ
ꢃ
ꢑ ꢉꢕꢖꢃ
ꢇꢀꢈ
Dynamic Current Sharing
During a Load Transient in a
2-Phase System
Dynamic Current Sharing
During a Load Transient in a
2-Phase System
Dynamic Current Sharing
During a Load Transient in a
4-Phase System
ꢀꢁ
ꢀꢁꢂꢃꢄꢅ
ꢀ0ꢁꢂꢃꢄꢅ
ꢀ0ꢁꢂꢃꢄꢅ
0ꢀ
ꢀꢁꢂꢃ ꢄꢁꢃ
ꢀꢁꢂꢃ ꢄꢁꢂ
ꢀꢁꢂꢃ ꢄꢁꢅ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀ0ꢁꢂꢃꢄꢅꢆ
ꢀ
ꢇꢈ
ꢄ ꢅꢀ
ꢀ
ꢇꢈ
ꢄ ꢅꢀ
ꢀ
ꢄ ꢅꢀ
ꢁꢂꢃ
ꢁꢂꢃ
ꢁꢂꢃ
ꢆ
ꢄ ꢉꢊꢋꢌꢍꢎ
ꢆ
ꢄ ꢉꢊꢋꢌꢍꢎ
ꢆ
ꢄ ꢉꢊꢋꢌꢍꢎ
ꢇꢈ
0ꢏ ꢃꢁ ꢊ0ꢏ ꢐꢁꢏꢑ ꢇꢃꢒꢓ
0ꢏ ꢃꢁ ꢊ0ꢏ ꢐꢁꢏꢑ ꢇꢃꢒꢓ
0ꢏ ꢃꢁ ꢉ0ꢏ ꢐꢁꢏꢑ ꢇꢃꢒꢓ
Dynamic Current Sharing During
a Load Transient in a 4-Phase
System
Current Limit During an Output
Short Condition
DC Output Current Matching in a
2-Phase System
ꢀꢁ
ꢀꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁꢂꢃꢄꢁꢅꢄꢆꢇꢂꢈꢃꢄꢈꢀꢉꢀꢃ ꢊ ꢋ0ꢇ
ꢀ
ꢀꢁꢂ
ꢀ00ꢁꢂꢃꢄꢅꢂ
ꢀꢁ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁ
0ꢀ
ꢀ0ꢁꢂꢃꢄꢅ
ꢀꢁ0
ꢀꢁꢂ
ꢀ
ꢀꢁꢂꢃ ꢄꢁꢅ
ꢀꢁꢂꢃ ꢄꢁꢅ
ꢀ0ꢁꢂꢃꢄꢅꢆ
ꢀ0ꢁꢂꢃꢄꢅꢆ
ꢀ
ꢀ
ꢇꢈ
ꢄ ꢅꢀ
ꢁꢂꢃ
ꢆ
ꢄ ꢉꢊꢋꢌꢍꢎ
0
0ꢏ ꢃꢁ ꢉ0ꢏ ꢐꢁꢏꢑ ꢇꢃꢒꢓ
0
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀꢁꢀꢂꢃ ꢁꢄꢀꢅꢄꢀ ꢆꢄRRꢇꢈꢀ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢁꢀ
Rev 0
12
For more information www.analog.com
LTC7132
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 12V, L = 0 .3µH, DCR = 0 .29mΩ, EXTVCC = 0 V unless otherwise noted.
Current Sense Threshold
vs Duty Cycle
SHARE_CLK Frequency
vs Input Voltage
INTVCC Line Regulation
ꢀꢁꢂ
ꢀꢁꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢂ0
ꢀꢀꢁꢂ
ꢀꢀꢁꢂ
ꢀ0ꢁꢂ
ꢀ0ꢁꢂ
ꢀ0ꢁ0
ꢀꢁꢂ
ꢀ0ꢁ
ꢀ0ꢁ
ꢀ0ꢁ
ꢀ00
ꢀꢁ
ꢀꢁꢀꢂꢃꢄꢀꢂꢀꢅꢆꢇꢈꢉꢊꢈꢋꢊ ꢌ 0ꢍꢎ
ꢀꢁꢂꢃꢄꢁꢅꢄꢆꢇꢂꢈꢃꢄꢈꢀꢉꢀꢃꢊ ꢋꢌꢍꢎꢇ
ꢀꢁꢂ
ꢀꢁꢀ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁ
0
ꢀ
ꢀ0
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀ0
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀ
ꢀ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁ
ꢀ0
ꢀ
ꢀꢁꢂꢃ ꢄꢃꢄꢅꢆ ꢇꢈꢉ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂꢃ ꢄꢁꢅ
ꢀꢁꢂꢃ ꢄꢁꢅ
ꢀꢁꢂꢃ ꢄꢃ0
Quiescent Current
vs Input Voltage
Supply Current Measurement
Error vs Supply Current
VREF vs Temperature
ꢀ0ꢁ0
ꢀꢁꢂꢃ
ꢀꢁꢂ0
ꢀꢀꢁꢂ
ꢀ0ꢁ0
ꢀꢁꢂꢃ
ꢀꢁꢂ0
ꢀꢁ0
0ꢀꢁ
ꢀꢁꢂꢂꢂ0
ꢀꢁꢂꢂꢀꢃ
ꢀꢁꢂꢂꢀꢃ
ꢀꢁꢂꢂꢀꢃ
ꢀꢁꢂꢂꢀ0
ꢀꢁꢂꢂ0ꢃ
ꢀꢁꢂꢂ0ꢃ
ꢀꢁꢂꢂ0ꢃ
ꢀꢁꢂꢂ00
ꢀꢁꢂꢀꢃꢄ
ꢀꢁꢂꢀꢃꢄ
ꢀꢁꢂꢀꢃꢄ
ꢀꢁꢂꢀꢃ0
R
ꢀꢁꢂ
= 2Ω
0ꢀꢁ
0ꢀꢁ
0ꢀꢁ
0ꢀ0
ꢀ0ꢁꢂ
ꢀ0ꢁꢂ
ꢀ0ꢁꢂ
ꢀ0ꢁꢂ
ꢀꢁꢂ0
ꢀ
ꢀ
ꢀꢁ
ꢃꢀꢄ
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀꢁꢁ
ꢀꢁ0
ꢀꢁ
ꢀ0
ꢀꢁꢂ
ꢀ
ꢀꢁꢂꢂꢃꢄ ꢅꢁRRꢆꢇꢈ ꢉꢊꢋꢌ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢁꢂ
ꢀꢁꢂꢃ ꢄꢃꢁ
ꢀꢁꢂꢃ ꢄꢃꢃ
ꢀꢁꢂꢃ ꢄꢃꢂ
V
OUT Overvoltage Threshold
vs Temperature (Target 1V)
V
OUT Overvoltage Threshold
VOUT vs Temperature
vs Temperature (Target 2V)
ꢀꢁ00ꢂ
ꢀꢁ00ꢂ
ꢀꢁ00ꢂ
ꢀꢁ00ꢂ
ꢀꢁ00ꢀ
ꢀꢁ000
0ꢀꢁꢁꢁ
0ꢀꢁꢁꢂ
0ꢀꢁꢁꢂ
0ꢀꢁꢁꢂ
0ꢀꢁꢁꢂ
ꢀꢁ0ꢀꢂ
ꢀꢁ0ꢀ0
ꢀꢁ00ꢂ
ꢀꢁ000
0ꢀꢁꢁꢂ
0ꢀꢁꢁ0
0ꢀꢁꢂꢃ
ꢀꢁ0ꢂ0
ꢀꢁ0ꢀ0
ꢀꢁ0ꢂ0
ꢀꢁ000
ꢀꢁꢂꢂ0
ꢀꢁꢂꢃ0
ꢀꢁꢂꢃ0
ꢀꢁꢁ
ꢀꢁ0
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁ0
ꢀꢁ
ꢀ0
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁ0
ꢀꢁ
ꢀ0
ꢀꢁꢂ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃ ꢄꢃꢅ
ꢀꢁꢂꢃ ꢄꢃꢅ
ꢀꢁꢂꢃ ꢄꢃꢅ
Rev 0
13
For more information www.analog.com
LTC7132
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 12V, L = 0 .3µH, DCR = 0 .29mΩ, EXTVCC = 0 V unless otherwise noted.
V
OUT Overvoltage Threshold
vs Temperature (Target 4V)
SHARE_CLK vs Temperature
Underlock Voltage vs Temperature
ꢀꢁ0ꢂ
ꢀꢁ0ꢀ
ꢀꢁ0ꢂ
ꢀꢁ00
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀ0ꢁ
ꢀ0ꢁ
ꢀ0ꢁ
ꢀ0ꢁ
ꢀ0ꢀ
ꢀ00
ꢀꢀ
ꢀꢁꢂ0
ꢀꢁꢂꢃ
ꢀꢁꢂ0
ꢀꢁ0ꢂ
ꢀꢁ00
ꢀꢁꢂꢃ
ꢀꢁꢂ0
ꢀꢁꢂꢃ
ꢀꢁꢂ0
ꢀꢁꢂꢃ
ꢀꢁꢂ0
Rꢀꢁꢀꢂꢃ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂꢂꢃꢄꢅ
ꢀꢁ
ꢀꢁ
ꢀꢁꢁ
ꢀꢁ0
ꢀꢁ
ꢀ0
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁ0
ꢀꢁ
ꢀ0
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁ0
ꢀꢁ
ꢀ0
ꢀꢁꢂ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃ ꢄꢃꢀ
ꢀꢁꢂꢃ ꢄꢃꢅ
ꢀꢁꢂꢃ ꢄꢃꢅ
VOUT Command INL
VOUT Error vs VOUT
VOUT Command DNL
0ꢀꢁ0
0ꢀꢁꢂ
ꢀꢁ00
ꢀꢁꢂ0
ꢀꢁ00
0ꢀꢁ0
0
0ꢀꢁ0
0ꢀꢁ0
0ꢀꢁꢂ
0ꢀꢁ0
0ꢀ0ꢁ
0ꢀꢁ0
0ꢀ00
0ꢀ00
ꢀ0ꢁ0ꢂ
ꢀ0ꢁꢂꢃ
ꢀ0ꢁꢂꢂ
ꢀ0ꢁꢂ0
ꢀ0ꢁꢂ0
ꢀ0ꢁꢂ0
ꢀ0ꢁꢂ0
ꢀ0ꢁꢂ0
ꢀꢁꢂ00
0ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢄꢀꢅ
ꢀꢁꢂ
ꢀꢁꢀ
0ꢀꢁ0
ꢀꢁꢂ0
ꢀꢁꢂ0
ꢀꢁꢂ0
ꢄꢀꢅ
ꢀꢁꢂ0
ꢀꢁꢀ0
0ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢄꢀꢅ
ꢀꢁꢂ
ꢀꢁꢀ
ꢀ
ꢀ
ꢀ
ꢁꢂꢃ
ꢁꢂꢃ
ꢁꢂꢃ
ꢀꢁꢂꢃ ꢄꢂ0
ꢀꢁꢂꢃ ꢄꢂꢁ
ꢀꢁꢂꢃ ꢄꢂꢃ
IOUT Error vs IOUT
Input Current Error vs Input Current
ꢀ0ꢁ00
ꢀꢁꢂꢃ
ꢀ
ꢀ
ꢀ
0
0
R
= 5mΩ
ꢀꢀꢁꢂꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁ0ꢂ00
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
0ꢀꢁ
ꢀꢁ0
ꢀꢁꢂ0
ꢀꢁꢂ0
ꢀꢁꢂ
ꢀꢁꢂ0
ꢀ0ꢁ0
0
ꢀ
ꢀ
ꢀ
ꢀ0
ꢀ
ꢀꢁꢂꢃꢄ ꢅꢃRRꢆꢁꢄꢇꢈꢉ
ꢀꢁꢂ
ꢀꢁꢂꢃ ꢄꢂꢂ
ꢀꢁꢂꢃ ꢄꢂꢅ
Rev 0
14
For more information www.analog.com
LTC7132
PIN FUNCTIONS
+
VSENSE0 +/VSENSE1 (A9/F7): Positive Output Voltage
ASEL0 /ASEL1 (D1/E1): Serial Bus Address Select Inputs.
Connect optional 1% resistor dividers between VDD25
and SGND to these pins to select the serial bus interface
address. Refer to the Applications Information section for
more details. Minimize capacitance when the pin is open
to assure accurate detection of the pin state.
Sense Inputs.
–
VSENSE0 –/VSENSE1 (A10 /E7): Negative Output Voltage
Sense Inputs.
I
/I
(A7/E5): Current Control Threshold and Error
TH0 TH1
Amplifier Compensation Nodes. Each associated chan-
nel’s current comparator tripping threshold increases with
VOUT0 _CFG/VOUT1_CFG (D2/F1): Output Voltage Select Pins.
Connect optional 1% resistor divider between VDD25
VOUT_CFG and SGND in order to select output voltage
for each channel. If the pin is left open, the IC will use the
value programmed in EEPROM. Refer to the Applications
Information section for more details. Minimize capaci-
tance when the pin is open to assure accurate detection
of the pin state.
its I voltage.
TH
I
/I
(B7/E6): Loop Compensation Nodes.
THR0 THR1
+
ISENSE0 +/ISENSE1 (B6/A8): Current sense comparator
positive inputs, normally connected to DCR sensing net-
works or current sensing resistors.
–
ISENSE0 –/ISENSE1 (A6/B8): Current sense comparator
FREQ_CFG (E2): Frequency Select Pin. Connect optional
1% resistor divider between VDD25 and FREQ_CFG
SGND in order to select PWM switching frequency. Refer
to the Applications Information section for more details.
Minimize capacitance when the pin is open to assure
accurate detection of the pin state.
negative inputs, normally connected to outputs.
SYNC (A4): External Clock Synchronization Input and
Open-Drain Output Pin. If an external clock is present at
this pin, the switching frequency will be synchronized to
the external clock. If clock master mode is enabled, this
pin will pull low at the switching frequency with a 500ns
pulse to ground. A resistor pull-up to 3.3V is required in
the application if the LTC7132 is the master.
PHASE_CFG (F2): Phase Select Pin. Connect 1% resis-
tor divider between VDD25 PHASE_CFG SGND to this
pin to configure the phase of each PWM channel rela-
tive to SYNC. If the pin is left open, the IC will use the
value programmed in the NVM. Refer to the Applications
Information section for more details. Minimize capaci-
tance when the pin is open to assure accurate detection
of the pin state.
SCL (B3): Serial Bus Clock Input. Open-drain output can
hold the output low if clock stretching is enabled. A pull-
up resistor to 3.3V is required in the application.
SDA (A3): Serial Bus Data Input and Output. A pull-up
resistor to 3.3V is required in the application.
VDD25 (F3): Internally Generated 2.5V Power Supply
Output Pin. Bypass this pin to SGND with a low ESR 1μF
capacitor. Do not load this pin with external current except
for the 1% resistor dividers required for the configura-
tion pins.
ALERT (A2): Open-Drain Digital Output. Connect the
SMBALERT signal to this pin. A pull-up resistor to 3.3V
is required in the application.
FAULT0/FAULT1 (A1/B1): Digital Programmable FAULT
Inputs and Outputs. Open-drain output. A pull-up resistor
to 3.3V is required in the application.
WP (E4): Write Protect Pin Active High. An internal 10μA
current source pulls the pin to V . If WP is high, the
DD33
PMBus writes are restricted.
RUN0 /RUN1 (C1/C2): Enable Run Input and Output. Logic
high on these pins enables the controller. An open-drain
output holds the pin low until the LTC7132 is out of reset.
A pull-up resistor to 3.3V is required in the application.
SHARE_CLK (E3): Share Clock, Bidirectional Open-Drain
Clock Sharing Pin. Nominally 100kHz. Used to syn-
chronize the timing between multiple LTC7132s. Tie all
SHARE_CLK pins together. All LTC7132s will synchronize
to the fastest clock. A pull-up resistor to 3.3V is required.
Rev 0
15
For more information www.analog.com
LTC7132
PIN FUNCTIONS
VDD33 (F4): Internally Generated 3.3V Power Supply
Output Pin. Bypass this pin to SGND with a low ESR 1μF
capacitor. Do not load this pin with external current except
for the pull-up resistors required for FAULTn, SHARE_CLK,
SYNC and possibly RUNn, SDA and SCL, PGOODn.
TSNS0 /TSNS1 (A5/B5): External Diode Temperature
Sense. Connect to the anode of a diode connected PNP
transistor and star-connect the cathode to GND (Pin 49)
in order to sense remote temperature. A bypass capaci-
tor between the anode and cathode must be located in
close proximity to the transistor. If external temperature
sense elements are not installed, short pin to ground and
set the UT_FAULT_LIMIT to –275°C and the UT_FAULT_
RESPONSE to ignore.
INTVCC (E10 ): Internal Regulator 5.5V Output. The control
circuits are powered from this voltage. Decouple this pin
to PGND with a minimum of 4.7μF low ESR tantalum or
ceramic capacitor. This regulator is mainly designed for
internal circuits, not to be used as supply for the other ICs.
+
I
(B10 ): Positive Current Sense Comparator Input. If
IN
the input current sense amplifier is not used, this pin must
be shorted to the I and V pins.
EXTV (D9): External Power Input to an Internal Switch
ConnCeCcted to INTV . This switch closes and supplies
–
IN
IN
CC
the IC power, bypassing the internal regulator whenever
EXTVCC is higher than 4.7V and VIN is higher than 7V.
IIN– (B9): Negative Current Sense Comparator Input. If the
input current sense amplifier is not used, this pin must be
+
EXTV also powers up V
when EXTV is higher than
shorted to the I and V pins.
DD33
CC
IN
IN
4.7V CaCnd INTV is lower than 3.8V. Do not exceed 6V
CC
PGOOD0 /PGOOD1 (C8/F8): Power Good Indicator
Outputs. Open-drain logic output that is pulled to ground
when the output exceeds the UV and OV regulation win-
dow. The output is deglitched by an internal 60µs filter.
A pull-up resistor to 3.3V is required in the application.
on this pin. Decouple this pin to PGND with a minimum
of 4.7μF low ESR tantalum or ceramic capacitor. If the
EXTV pin is not used to power INTV , the EXTV pin
CC
CC
CC
must be tied to GND. The EXTV pin may be connected
CC
to a higher voltage than the V pin.
IN
SGND (C3, C4, C5, C6, C7, D3, D4, D5, D6, D7): Internal
Signal Ground. All small-signal and compensation com-
ponents should connect to this ground, which in turn
connects to PGND at a single point.
SVIN (D8): Signal VIN. This pin is the input voltage to
power the internal 5.5V INTV LDO. Tie this pin to V
CC
IN
with a 2.2Ω resistor in series between VIN and SV .
IN
Decouple this pin to PGND with a ceramic capacitor (1µF
to 10µF typical).
PV /PV (G6, G7, G8, G9, G10 , H6, H7, J6, J7, K6,
IN0
IN1
K7, L6, L7, M6, M7/H1, H2, J1, J2, K1, K2, L1, L2, M1,
M2): Main Input Supply. These pins connect directly to the
drain of the internal high side power MOSFETs. Decouple
BOOST0 /BOOST1(C9/F10 ): Boosted Floating Driver
Supplies. The (+) terminal of the booststrap capacitors
connect to these pins. These pins swing from a diode
these pins to PGND with the input capacitance C .
IN
voltage drop below INTV up to V + INTV .
CC
IN
CC
PGND (Pins D10 , G1, G2, G3, G4, G5, H3, H4, H5, H8,
H9, H10 , J3, J4, J5, J8, J9, J10 , K3, K4, K5, K8, K9,
K10 , L3, L4, L5, L8, L9, L10 , M3, M4, M5, M8, M9,
M10 ): Power Ground.
SW0 /SW1 (C10 , N6, N7, N8, N9, N10 , P6, P7, P8, P9,
P10 /F9, N1, N2, N3, N4, N5, P1, P2, P3, P4, P5): Switch
Node Connections to the Output Inductors. Voltage swings
at the pins are from a diode (internal body diode) voltage
drop below ground to V .
IN
Rev 0
16
For more information www.analog.com
LTC7132
BLOCK DIAGRAM (UK PACKAGE)
ꢏ
ꢉꢄ
ꢀ
R
ꢏꢉꢄ
ꢏ
ꢑꢖꢎꢎꢚꢡ
ꢉ
ꢉꢄ
ꢌ
ꢉꢄ
ꢤꢅR
R
ꢜꢨR
R
ꢏ
ꢉꢄ
ꢞꢄꢮꢞꢦꢦ
ꢀ
ꢁ
ꢀ
ꢂ ꢃ ꢄꢁ
R
ꢁ
ꢉꢉꢄꢑꢄꢑ
ꢉ
ꢉꢄ
ꢒꢗꢊꢏ
ꢌꢌ
ꢞꢏ
ꢖꢏ
ꢎꢠꢞꢞꢋ0
ꢎꢠꢞꢞꢋ0
ꢨꢢꢨꢏRꢒꢠ
ꢒꢗꢊꢏ
ꢌꢌ
ꢟꢇꢈꢉꢊ ꢏ
ꢋꢂꢌ
ꢉꢄ
ꢉꢄꢊꢏ
ꢌꢌ
ꢉꢄꢊꢏ
ꢌꢌ
ꢏ
ꢋꢋꢜꢜ
ꢜꢢꢜꢏ
ꢑꢖꢈRꢒꢠ
ꢏ
ꢋꢋꢜꢜ
ꢑ
R
ꢎꢓꢔꢐꢌꢚꢞꢌꢥ
ꢋ
ꢈ
ꢈꢞꢞꢑꢊ0
ꢑꢓ0
ꢧ
ꢦꢌꢄꢊ
ꢉ
ꢨꢪ
ꢌꢔꢎ
Rꢒꢏ
ꢌ
ꢈ
ꢁ
ꢀ
ꢎRꢒꢈꢉꢂꢑ
ꢞꢄ
ꢀ
ꢁ
ꢔꢅ
ꢔꢘ
ꢑꢓꢉꢊꢌꢍ
ꢚꢞꢠꢉꢌ
ꢂꢄꢋ
ꢂꢄꢊꢉꢇ
ꢑꢍꢞꢞꢊꢇ
ꢊꢍRꢞꢖꢠꢍ
Rꢒꢏ
ꢖꢏ
ꢖꢏꢚꢞ
ꢑꢑ
ꢏ
ꢞꢖꢊ0
ꢌ
ꢞꢖꢊ
Rꢖꢄ
ꢉ
Rꢂꢄꢠꢒ ꢑꢒꢚꢒꢌꢊ
ꢍꢉꢕ ꢅꢕꢅ
ꢚꢞꢕ ꢅꢕꢅꢢꢩ
ꢚꢉꢔ
ꢎꢠꢄꢋ
ꢀ
ꢌ
ꢞꢏ
ꢏꢌꢌ
ꢅ
ꢨꢪ
ꢉ
ꢉ
ꢑꢒꢄꢑꢒ0
ꢁ
ꢑꢒꢄꢑꢒ0
ꢑꢚꢞꢎꢒ
ꢀ
ꢁ
ꢁ
ꢀ
ꢌꢞꢔꢎꢒꢄꢑꢂꢊꢉꢞꢄ
ꢀ
ꢁ
ꢁ
ꢀ
ꢀ
ꢠꢔ
ꢉꢄꢊꢏ
ꢌꢌ
ꢖꢏꢚꢞ
ꢣR
ꢅꢅR
ꢅꢅR
ꢅ0ꢕꢅ ꢁ
ꢀ
ꢉ
ꢉ
ꢏꢉꢄꢐꢑꢄꢑꢅ
ꢀ
ꢉ
ꢔꢖꢗ ꢁ
ꢊꢍ0
ꢂꢌꢊꢉꢏꢒ
ꢌꢚꢂꢔꢎ
ꢉ
ꢋꢂꢌ
ꢁ
ꢀ
ꢚꢉꢔ
ꢏ
ꢑꢒꢄꢑꢒ0
ꢀ
ꢁ
ꢁ
ꢛꢜ ꢈꢉꢊꢑꢝ
ꢀ
ꢅꢆꢇꢈꢉꢊ
ꢂꢋꢌ
ꢑꢒꢄꢑꢒꢅ
ꢑꢒꢄꢑꢒꢅ
ꢂꢋ ꢀ
ꢁ
ꢌ
ꢌꢘ
ꢁ
ꢀ
ꢁ
ꢀ
ꢉ
ꢀ
ꢁ
ꢏ
R
ꢏ
ꢏ
ꢑꢒꢄꢑꢒ0
ꢊꢍ
ꢉ
ꢑꢒꢄꢑꢒꢅ
ꢑꢒꢄꢑꢒꢅ
ꢊꢍR0
ꢣR
ꢎꢓꢔ0
ꢌ
ꢌꢅ
ꢁ
ꢀ
ꢉ
ꢘꢙꢂ
ꢜꢘꢙꢂ
ꢌꢍꢉꢎ
ꢁ
ꢒꢂ
ꢖꢏ
ꢞꢏ
ꢁ
ꢁ
ꢁ
ꢀ
ꢀ
ꢀ
ꢊꢑꢄꢑ0
ꢏ
ꢑꢊꢈꢡ
ꢊꢔꢖꢗ
ꢅ0R
ꢤR
Rꢒꢦ
ꢑꢠꢄꢋ
ꢑꢠꢄꢋ
ꢅꢢꢘꢘꢏ
ꢎꢍꢂꢑꢒ ꢋꢒꢊ
ꢑꢡꢄꢌ
ꢅꢘꢇꢈꢉꢊ
ꢑꢒꢊ ꢎꢞꢉꢄꢊ
ꢋꢂꢌ
ꢟꢇꢈꢉꢊ
ꢖꢏ
ꢋꢂꢌ
ꢟꢇꢈꢉꢊ
ꢞꢏ
ꢋꢂꢌ
ꢏ
ꢌꢞ
ꢎꢓꢔ
ꢌꢚꢞꢌꢥ
ꢎꢍꢂꢑꢒ ꢑꢒꢚꢒꢌꢊꢞR
ꢌꢚꢞꢌꢥ ꢋꢉꢏꢉꢋꢒR
ꢏ
ꢋꢋꢜꢜ
ꢏ
ꢋꢋꢜꢜ
ꢏ
ꢋꢋꢘꢨ
ꢑꢌꢚ
ꢑꢋꢂ
ꢘꢢꢨꢏ
ꢏ
ꢑꢚꢂꢏꢒ
ꢔꢉꢑꢞ
ꢋꢋꢜꢜ
ꢏ
ꢋꢋꢘꢨ
ꢑꢖꢈRꢒꢠ
ꢎꢔꢈꢬꢭ
ꢌꢞꢔꢎꢂRꢒ
ꢉꢄꢊꢒRꢦꢂꢌꢒ
ꢛꢤ00ꢪꢍꢫ
ALERT
ꢓꢎ
ꢌꢞꢔꢎꢂꢊꢉꢈꢚꢒꢝ
ꢌꢚꢥ ꢔꢞꢑꢉ
ꢔꢂꢑꢊꢒR
ꢞꢑꢌ
ꢛꢜꢘꢔꢍꢫꢝ
ꢂꢑꢒꢚ0
ꢂꢑꢒꢚꢅ
ꢔꢂꢉꢄ
ꢌꢞꢄꢊRꢞꢚ
ꢜ
ꢑꢉꢄꢌ
ꢖꢏꢚꢞ
ꢌꢞꢄꢦꢉꢠ
ꢋꢒꢊꢒꢌꢊ
ꢏ
ꢞꢖꢊ0ꢐꢌꢦꢠ
FAULT0
Rꢖꢄ0
ꢦRꢒꢧꢐꢌꢦꢠ
ꢌꢍꢂꢄꢄꢒꢚ
ꢊꢉꢔꢉꢄꢠ
ꢔꢂꢄꢂꢠꢒꢔꢒꢄꢊ
ꢎRꢞꢠRꢂꢔ
Rꢞꢔ
Rꢂꢔ
ꢒꢒꢎRꢞꢔ
ꢎꢍꢂꢑꢒꢐꢌꢦꢠ
ꢑꢍꢂRꢒꢐꢌꢚꢥ
ꢣꢅꢜꢘ ꢦ0ꢘ
Figure 2. Block Diagram, One of Two Channels (Channel 0 Shown)
Rev 0
17
For more information www.analog.com
LTC7132
OPERATION
OVERVIEW
n
Phase-Locked Loop for Synchronous PolyPhase
Operation (2, 3, 4 or 6 Phases).
The LTC7132 is a dual channel/dual phase, constant-
frequency, analog peak current mode controller for DC/
DC step-down applications with a digital interface. The
LTC7132 digital interface is compatible with PMBus
which supports bus speeds of up to 400kHz. A Typical
Application circuit is shown on the first page of this data
sheet.
n
n
n
Integrated Gate Drivers
Nonvolatile Configuration Memory with ECC
Optional External Configuration Resistors for Key
Operating Parameters
n
Optional Timebase Interconnect for Synchronization
Between Multiple Controllers
Major features include:
n
n
n
n
n
n
n
n
n
WP Pin to Protect Internal Configuration
Sub-Milliohm DCR Sensing
Stand Along Operation After User Factory Configuration
PMBus, Version 1.2, 400kHz Compliant Interface
Dedicated Power Good Indicators
Direct Input and Chip Current Sensing
Programmable Loop Compensation Parameters
The PMBus interface provides access to important power
management data during system operation including:
T
Start-Up Time: 35ms
INIT
n
Internal Controller Temperature
PWM Synchronization Circuit, (See Frequency and
Phasing Section for Details)
n
External System Temperature via Optional Diode Sense
Elements
n
n
MFR_ADC_CONTROL for Fast ADC Sampling of One
Parameter (as Fast as 8ms) (See PMBus Command
for Details)
n
Average Output Current
n
Average Output Voltage
Fully Differential Output Sensing for Both Channels;
VOUT0 /1 Both Programmable Up to 5.5V
n
Average Input Voltage
n
Average Input Current
n
n
n
n
Power-Up and Program EEPROM with EXTV
Input Voltage Up to 20 V
CC
n
Average Chip Input Current from V
IN
n
Configurable, Latched and Unlatched Individual Fault
and Warning Status
Dual Diode Temperature Sensing
SYNC Contention Circuit (Refer to Frequency and
Phase Section for Details)
Individual channels are accessed through the PMBus
using the PAGE command, i.e., PAGE 0 or 1.
n
n
n
Fault Logging
Fault reporting and shutdown behavior are fully con-
figurable. Two individual FAULT0, FAULT1 outputs are
provided, both of which can be masked independently.
Three dedicated pins for ALERT, PGOOD0/1 functions are
provided. The shutdown operation also allows all faults
to be individually masked and can be operated in either
unlatched (hiccup) or latched modes.
Programmable Output Voltage
Programmable Input Voltage On and Off Threshold
Voltage
n
n
n
n
n
Programmable Current Limit
Programmable Switching Frequency
Programmable OV and UV Threshold voltage
Programmable ON and Off Delay Times
Programmable Output Rise/Fall Times
Individual status commands enable fault reporting over
the serial bus to identify the specific fault event. Fault or
warning detection includes the following:
n
Output Undervoltage/Overvoltage
Rev 0
18
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LTC7132
OPERATION
n
Input Undervoltage/Overvoltage
is turned on. In continuous conduction mode, the bottom
MOSFET stays on until the end of the switching cycle.
n
Input and Output Overcurrent
n
Internal Overtemperature
EEPROM
n
External Overtemperature
The LTC7132 contains internal EEPROM (nonvolatile
memory) with error correction coding (ECC) to store user
configuration settings and fault log information. EEPROM
endurance retention and mass write operation time are
specified in the Electrical Characteristics and Absolute
n
Communication, Memory or Logic (CML) Fault
MAIN CONTROL LOOP
The LTC7132 is a constant-frequency, current mode step-
down controller containing two channels operating with
user-defined relative phasing. During normal operation
the top MOSFET is turned on when the clock for that
channel sets the RS latch, and turned off when the main
Maximum Ratings sections. Write operations above T =
J
85°C are possible although the Electrical Characteristics
are not guaranteed and the EEPROM will be degraded.
Read operations performed at temperatures between
–40°C and 125°C will not degrade the EEPROM. Writing
to the EEPROM above 85°C will result in a degradation of
retention characteristics. The fault logging function, which
is useful in debugging system problems that may occur
at high temperatures, only writes to fault log EEPROM
locations. If occasional writes to these registers occur
above 85°C, the slight degradation in the data retention
characteristics of the fault log will not take away from the
usefulness of the function.
current comparator, I
inductor current at which I
, resets the RS latch. The peak
CMP
CMP
resets the RS latch is con-
trolled by the voltage on the I pin which is the output
TH
of each error amplifier, EA. The EA negative terminal is
+
equal to the differential voltage between VSENSE and
–
V
divided by 5.5 (or 2.75 if MFR_PWM_MODE[1]
SENSE
= 1). The positive terminal of the EA is connected to the
output of a 12-bit DAC with values ranging from 0V to
1.024V. The output voltage, through feedback of the EA,
will be regulated to 5.5 times the DAC output (or 2.75
times). The DAC value is calculated by the part to syn-
thesize the user's desired output voltage. The output volt-
age is programmed by the user either with the resistor
configuration pins detailed in Table 3 or by the PMBus
VOUT command (either from EEPROM or by PMBus com-
mand). Refer to the PMBus command section of the data
sheet or the PMBus specification for more details. The
PMBus VOUT_COMMAND can be executed at any time
while the device is running. This command will typically
have a latency less than 10ms. The user is encouraged to
refer to the PMBus Power System Management Protocol
Specification to understand how to program the LTC7132.
It is recommended that the EEPROM not be written when
the die temperature is greater than 85°C. If the die tem-
perature exceeds 130°C, the LTC7132 will disable all
EEPROM write operations. All EEPROM write operations
will be re-enabled when the die temperature drops below
125°C. (The controller will also disable all the switching
when the die temperature exceeds the internal overtem-
perature fault limit 160°C with a 10°C hysteresis)
The degradation in EEPROM retention for temperatures
>125°C can be approximated by calculating the dimen-
sionless acceleration factor using the following equation:
ꢆ
ꢂ
ꢉ
ꢃ
ꢀ
ꢀ
ꢃ
ꢅ
ꢄ
Ea
k
1
1
•
–
ꢈ
ꢋ
ꢅ
ꢂ
AF =eꢇꢁ
where:
T
USE+273 TSTRESS+273
ꢄ
ꢊ
ꢁ
Continuing the basic operation description, the current-
mode controller will turn off the top gate when the peak
current is reached. If the load current increases, sense
voltage will slightly droop with respect to the DAC refer-
ence. This causes the I voltage to increase until the
average inductor current matches the new load current.
After the top MOSFET has turned off, the bottom MOSFET
AF = acceleration factor
TH
Ea = activation energy = 1.4eV
–5
K = 8.617 • 10 eV/°K
T
T
= 125°C specified junction temperature
USE
= actual junction temperature in °C
STRESS
Rev 0
19
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LTC7132
OPERATION
Example: Calculate the effect on retention when operating
at a junction temperature of 135°C for 10 hours.
and 2.5V linear regulators must be within approximately
20% of the regulated values. In addition to power supply,a
PMBus RESTORE_USER_ALL or MFR_RESET command
can initialize the part too.
T
T
= 130°C
STRESS
= 125°C,
–5
([(1.4/8.617 • 10 ) • (1/398 – 1/403)] )
USE
The EXTVCC pin is driven by an external regulator to
improve efficiency of the circuit and minimize power loss
AF = e
= 16.6
on the LTC7132 when V is high. The EXTV pin must
IN
exceed approximately 4.8V, and SVIN mustCCexceed 7V
The equivalent operating time at 125°C = 16.6 hours.
Thus the overall retention of the EEPROM was degraded by
16.6 hours as a result of operating at a junction temperature
of 130°C for 10 hours. The effect of the overstress is negligi-
ble when compared to the overall EEPROM retention rating of
87,600 hours at a maximum junction temperature of 125°C.
before the INTV LDO operates from the EXTV pin. To
CC
CC
minimize application power, the EXTV pin can be sup-
CC
plied by a switching regulator.
During initialization, the external configuration resistors
are identified and/or contents of the NVM are read into
the controller’s commands. The RUNn and FAULTn and
PGOODn are held low. The LTC7132 will use the con-
tents of Tables 12 to 15 to determine the resistor defined
parameters. See the Resistor Configuration section for
more details. The resistor configuration pins only control
some of the preset values of the controller. The remaining
values are programmed in NVM either at the factory or
by the user.
The integrity of the entire onboard EEPROM is checked with
a CRC calculation each time its data is to be read, such as
after a power-on reset or execution of a RESTORE_USER_
ALL command. If a CRC error occurs, the CML bit is set in
the STATUS_BYTE and STATUS_WORD commands, the
EEPROM CRC Error bit in the STATUS_MFR_SPECIFIC
command is set, and the ALERT and RUN pins pulled
low (PWM channels off). At that point the device will only
respond at special address 0x7C, which is activated only
after an invalid CRC has been detected. The chip will also
respond at the global addresses 0x5A and 0x5B, but use
of these addresses when attempting to recover from a
CRC issue is not recommended. All power supply rails
associated with either PWM channel of a device reporting
an invalid CRC should remain disabled until the issue is
resolved. See the Applications Information section or con-
tact the factory for details on efficient in-system EEPROM
programming, including bulk EEPROM Programming,
which the LTC7132 also supports.
If the configuration resistors are not inserted or if the
ignore RCONFIG bit is asserted (bit 6 of the MFR_
CONFIG_ALL configuration command), the LTC7132
will use only the contents of NVM to determine the DC/
DC characteristics. The ASEL0/1 value read at power-up
or reset is always respected unless the pin is open. The
ASEL0/1 will set the MSB and the LSB from the detected
threshold. See the Applications Information section for
more details.
After the part has initialized, an additional comparator
monitors SV . The SVIN_ON threshold must be exceeded
IN
before the output power sequencing can begin. After SVIN
is initially applied, the part will typically require 70ms
to initialize and begin the TON_DELAY timer. The read-
back of voltages and currents may require an additional
0ms to 90ms.
POWER-UP AND INITIALIZATION
The LTC7132 is designed to provide standalone supply
sequencing and controlled turn-on and turn-off operation.
It operates from a single input supply (4.5V to 20V) while
three on-chip linear regulators generate internal 2.5V,
3.3V and 5.5V. If VIN does not exceed 6V, and the EXTVCC
SOFT-START
pin is not driven by an external supply, the INTV and
CC
SV pins must be tied together. The controller configu-
The method of start-up sequencing described below is
time based. The part must enter the run state prior to
soft-start. The run pins are released by the LTC7132 after
Rev 0
IN
ration is initialized by an internal threshold based UVLO
where SV must be approximately 4V and the 5.5V, 3.3V
IN
20
For more information www.analog.com
LTC7132
OPERATION
the part is initialized and SVIN is greater than the SVIN_ON
threshold. If multiple LTC7132s are used in an applica-
tion, they all hold their respective run pins low until all
devices are initialized and SVIN exceeds the SVIN_ON
threshold for every device. The SHARE_CLK pin assures
all the devices connected to the signal use the same time
base. The SHARE_CLK pin is held low until the part has
TIME-BASED SEQUENCING
The default mode for sequencing the outputs on and off
is time based. Each output is enabled after waiting TON_
DELAY amount of time following either a RUN pin going
high, a PMBus command to turn on or the V rising above
IN
a pre-programmed voltage. Off sequencing is handled in
a similar way. To assure proper sequencing, make sure all
ICs connect the SHARE_CLK pin together and RUN pins
together. If the RUN pins cannot be connected together
for some reasons, set bit 2 of MFR_CHAN_ CONFIG to 1.
This bit requires the SHARE_CLK pin to be clocking before
the power supply output can start. When the RUN pin is
pulled low, the LTC7132 will hold the pin low for the MFR_
RESTART_DELAY. The minimum MFR_RESTART_ DELAY
is TOFF_DELAY + TOFF_FALL + 136ms. This delay assures
proper sequencing of all rails. The LTC7132 calculates this
delay internally and will not process a shorter delay. However,
a longer commanded MFR_RESTART_DELAY will be used
by the part. The maximum allowed value is 65.52 seconds.
been initialized after V is applied. The LTC7132 can be
IN
set to turn-off (or remain off) if SHARE_CLK is low (set
bit 2 of MFR_CHAN_CONFIG to 1). This allows the user to
assure synchronization across numerous ADI ICs even if
the RUN pins cannot be connected together due to board
constraints. In general, if the user cares about synchro-
nization between chips it is best not only to connect all
the respective RUN pins together but also to connect all
the respective SHARE_CLK pins together and pull up to
V
with a 10k resistor. This assures all chips begin
DD33
sequencing at the same time and use the same time base.
After the RUN pins release and prior to entering a con-
stant output voltage regulation state, the LTC7132 per-
forms a monotonic initial ramp or “soft-start”. Soft-start
is performed by actively regulating the load voltage while
digitally ramping the target voltage from 0V to the com-
manded voltage set-point. Once the LTC7132 is com-
manded to turn on (after power up and initialization),
the controller waits for the user specified turn-on delay
(TON_DELAY) prior to initiating this output voltage ramp.
The rise time of the voltage ramp can be programmed
using the TON_RISE command to minimize inrush cur-
rents associated with the start-up voltage ramp. The soft-
start feature is disabled by setting the value of TON_RISE
to any value less than 0.25ms. The LTC7132 PWM always
uses discontinuous mode during the TON_RISE opera-
tion. In discontinuous mode, the bottom gate is turned
off as soon as reverse current is detected in the inductor.
This will allow the regulator to start up into a pre-biased
load. When the TON_MAX_FAULT_LIMIT is reached, the
part transitions to continuous mode, if so programmed.
If TON_MAX_FAULT_LIMIT is set to zero, there is no time
limit and the part transitions to the desired conduction
VOLTAGE-BASED SEQUENCING
The sequence can also be voltage based. As shown in
Figure 3, The PGOODn pin is asserted when the UV
threshold is exceeded for each output. It is possible to
feed the PGOOD pin from one LTC7132 into the RUN pin
of the next LTC7132 in the sequence, especially across
multiple LTC7132s. The PGOODn has a 60μs filter. If the
V
voltage bounces around the UV threshold for a long
OUT
period of time it is possible for the PGOODn output to
toggle more than once. To minimize this problem, set the
TON_RISE time under 100ms.
Voltage-Based Sequencing by Cascading PGs Into RUN Pins
Rꢇꢈ 0
ꢉꢊꢋꢋꢌ0
ꢍꢁꢎRꢁ
ꢀꢁꢂꢃꢄꢅꢆ
Rꢇꢈ ꢄ
ꢉꢊꢋꢋꢌꢄ
Rꢇꢈ 0
Rꢇꢈ ꢄ
ꢉꢊꢋꢋꢌ0
ꢉꢊꢋꢋꢌꢄ
ꢀꢁꢂꢃꢄꢅꢆ
mode after TON_RISE completes and V
has exceeded
OUT
ꢃꢄꢅꢆ ꢏ0ꢅ
the VOUT_UV_FAULT_LIMIT and IOUT_OC is not present.
However setting TON_MAX_FAULT_LIMIT to a value of 0
is not recommended.
ꢁꢋ ꢈꢐꢑꢁ ꢂꢒꢎꢈꢈꢐꢀ
ꢓꢈ ꢁꢒꢐ ꢍꢐꢔꢇꢐꢈꢂꢐ
Figure 3. Event (Voltage) Based Sequencing
Rev 0
21
For more information www.analog.com
LTC7132
OPERATION
If a fault in the string of rails is detected, only the faulted
rail and downstream rails will fault off. The rails in the
string of devices in front of the faulted rail will remain on
unless commanded off.
LIGHT-LOAD CURRENT OPERATION
The LTC7132 has two modes of operation: high effi-
ciency discontinuous conduction mode or forced continu-
ous conduction mode. Mode selection is done using the
MFR_PWM _MODE command (discontinuous conduc-
tion is always the start-up mode, forced continuous is the
default running mode).
SHUTDOWN
The LTC7132 supports two shutdown modes. The first
mode is closed-loop shutdown response, with user
defined turn-off delay (TOFF_DELAY) and ramp down rate
(TOFF_FALL). The controller will maintain the mode of
operation for TOFF_FALL. The second mode is discontinu-
ous conduction mode, the controller will not draw current
from the load and the fall time will be set by the output
capacitance and load current, instead of TOFF_FALL.
If a controller is enabled for discontinuous operation, the
inductor current is not allowed to reverse. The reverse
current comparator’s output, I , turns off the bottom
gate of the external MOSFET RjuEVst before the inductor
current reaches zero, preventing it from reversing and
going negative.
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined solely
by the voltage on the ITH pin. In this mode, the efficiency at
light loads is lower than in discontinuous mode operation.
However, continuous mode exhibits lower output ripple
and less interference with audio circuitry, but may result in
reverse inductor current, which can cause the input supply
to boost. The VIN_OV_FAULT_LIMIT can detect this and
turn off the offending channel. However, this fault is based
The shutdown occurs in response to a fault condition
or loss of SHARE_CLK (if bit 2 of MFR_CHAN_ CONFIG
is set to a 1) or SV falling below the VIN_OFF thresh-
IN
old or FAULT pulled low externally (if the MFR_FAULT_
RESPONSE is set to inhibit). Under these conditions the
power stage is disabled in order to stop the transfer of
energy to the load as quickly as possible. The shutdown
state can be entered from the soft-start or active regula-
tion states or through user intervention.
on an ADC read and can take up to t
to detect. If
CONVERT
There are two ways to respond to faults; which are retry
mode and latched off mode. In retry mode, the con-
troller responds to a fault by shutting down and enter-
ing the inactive state for a programmable delay time
(MFR_RETRY_DELAY). This delay minimizes the duty
cycle associated with autonomous retries if the fault that
causes the shutdown disappears once the output is dis-
abled. The retry delay time is determined by the longer of
the MFR_RETRY_ DELAY command or the time required
for the regulated output to decay below 12.5% of the
programmed value. If multiple outputs are controlled by
the same FAULTn pin, the decay time of the faulted output
determines the retry delay. If the natural decay time of
the output is too long, it is possible to remove the volt-
age requirement of the MFR_RETRY_DELAY command
by asserting bit 0 of MFR_CHAN_CONFIG. Alternatively,
latched off mode means the controller remains latched-
off following a fault and clearing requires user interven-
tion such as toggling RUNn or commanding the part
OFF then ON.
there is a concern about the input supply boosting, keep
the part in discontinuous conduction mode.
If the part is set to discontinuous mode operation, as
the inductor average current increases, the controller will
automatically modify the operation from discontinuous
mode to continuous mode.
SWITCHING FREQUENCY AND PHASE
The switching frequency of the PWM can be established
with an internal oscillator or an external time base. The
internal phase-locked loop (PLL) synchronizes PWM con-
trol to this timing reference with proper phase relation,
whether the clock is provided internally or externally. The
device can also be configured to provide the master clock
to other ICs through PMBus command, NVM setting, or
external configuration resistors as outlined in Table 4.
As clock master, the LTC7132 will drive its open-drain
SYNC pin at the selected rate with a pulse width of 500ns.
Rev 0
22
For more information www.analog.com
LTC7132
OPERATION
An external pull-up resistor between SYNC and VDD33
is required in this case. Only one device connected to
SYNC should be designated to drive the pin. But if mul-
tiple LTC7132s programmed as clock masters are wired
to the same SYNC line with a pull-up resistor, just one of
the devices is automatically elected to provide clocking,
and the others disable their SYNC outputs.
The transconductance of the LTC7132 PWM error amplifier
can be adjusted using bit[7:5] of the MFR_PWM_COMP
command. These two loop compensation parameters can
be programmed when device is in operation. Refer to
the Programmable Loop Compensation subsection in the
Applications Information section for further details.
OUTPUT VOLTAGE SENSING
The LTC7132 will automatically revert to an external
SYNC input, disabling its own SYNC, as long as the
external SYNC frequency is greater than 80% of the
programmed SYNC frequency. The external SYNC input
shall have a duty cycle between 20% and 80%.
Both channels in LTC7132 have differential amplifiers,
which allow the remote sensing of the load voltage
+
–
between V
and V
pins. The telemetry ADC
SENSEn
SENSEn
is also fully differential and makes measurements between
+
–
V
and V
pins respectively. The maximum
Whether configured to drive SYNC or not, the LTC7132
can continue PWM operation using its own internal
oscillator if an external clock signal is subsequently lost.
The device can also be programmed to always require
an external oscillator for PWM operation by setting bit
4 of MFR_CONFIG_ALL. The status of the SYNC driver
circuit is indicated by bit 10 of MFR_PADS.
SENSEn
SENSEn
allowed sense voltages for both channels is 5.5V.
INTV /EXTV POWER
CC
CC
Power for the top and bottom MOSFET drivers and most
of the internal circuitry is derived from the INTVCC pin.
When the EXTVCC pin is shorted to GND or tied to a voltage
less than 4.7V, an internal 5.5V linear regulator supplies
The MFR_PWM_CONFIG command can be used to
configure the phase of each channel. Desired phase
can also be set from EEPROM or external configuration
resistors as outlined in Table 5. Designated phase is
the relationship between the falling edge of SYNC and
the internal clock edge that sets the PWM latch to turn
on the top power switch. Additional small propagation
delays to the PWM control pins will also apply. Both
channels must be off before the FREQUENCY_SWITCH
and MFR_PWM_CONFIG commands can be written to
the LTC7132.
INTV power from SV . If EXTV is taken above 4.7V
CC
IN
CC
and SV is higher than 7.0V, the 5.5V regulator is turned
IN
off and an internal switch is turned on, connecting EXTV
to INTV . Using the EXTV allows the INTV powerCtoC
CC
CC
CC
be derived from a high efficiency external source such as
a switching regulator output.
EXTVCC can provide power to the internal 3.3V linear
regulator even when V is not present, which allows the
IN
LTC7132 to be initialized and programmed even without
main power being applied.
The phase relationships and frequency are independent
of each other, providing numerous application options.
Multiple LTC7132 ICs can be synchronized to realize
a PolyPhase array. In this case the phases should be
separated by 360/n degrees, where n is the number of
phases driving the output voltage rail.
Each top MOSFET driver is biased from the floating boot-
strap capacitor, CB, which normally recharges during each
off cycle through an external diode when the bottom
MOSFET turns on. If the input voltage V decreases to
IN
a voltage close to V , the loop may enter dropout and
attempt to turn on OthUeT top MOSFET continuously. The
dropout detector detects this and forces the top MOSFET
off for about one-twelfth of the clock period plus 100ns
PWM LOOP COMPENSATION
The internal PWM loop compensation resistors R
of
ITHn
every three cycles to allow C to recharge. However, it is
B
the LTC7132 can be adjusted using bit[4:0] of the MFR_
PWM_COMP command.
recommended that a load be present or the IC operates
at low frequency during the drop-out transition to ensure
C is recharged.
B
Rev 0
23
For more information www.analog.com
LTC7132
OPERATION
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢉꢑꢂR
R
ꢇ
ꢇ
ꢇ
ꢇ
ꢁꢈ0
ꢁꢈꢄ
ꢁꢈR0
ꢁꢈRꢄ
ꢚ
ꢛ
ꢄ0ꢜ ꢣꢤꢥꢥꢜ ꢄ0ꢜ ꢄ0ꢜ ꢄ0ꢜ
ꢇ
ꢇ
ꢖ
ꢖ
ꢎꢌꢊꢎꢌ0
ꢎꢌꢊꢎꢌ0
ꢂ
ꢂ
ꢚ
ꢛ
ꢎꢌꢊꢎꢌ0
ꢎꢌꢊꢎꢌ0
FAULT0
Rꢘꢊ
Rꢘꢊ0
Rꢘꢊꢄ
ALERT
FAULT1
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ꢎꢈꢐRꢌꢟꢂꢀꢠ
ꢖ
ꢀꢉꢑꢂR
R
ALERT
FAULT
ꢎꢔꢊꢂ
ꢚ
ꢛ
ꢚ
ꢛ
ꢇ
ꢇ
ꢖ
ꢎꢌꢊꢎꢌꢄ
ꢎꢌꢊꢎꢌꢄ
ꢎꢌꢊꢎꢌꢄ
ꢎꢌꢊꢎꢌꢄ
ꢎꢈꢐRꢌꢟꢂꢀꢠ
ꢑꢑꢅꢅ
ꢖ
ꢄꢢꢓ
ꢎꢡꢊꢑ
ꢒꢡꢊꢑ
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ꢐꢊꢑ ꢂꢋꢏꢒꢋꢊꢌꢊꢁꢎ ꢋꢏꢇꢁꢁꢌꢑ
ꢓꢋR ꢂꢀꢐRꢇꢁꢔ
ꢕꢋꢁꢈ ꢂꢈꢇꢒꢎ ꢈꢐꢖꢌ ꢁꢈꢌ ꢇꢊꢁꢌRꢊꢐꢀ
ꢓRꢌꢗꢘꢌꢊꢂꢔ ꢂꢋꢏꢏꢐꢊꢑ ꢎꢌꢁ ꢁꢋ ꢁꢈꢌ
ꢎꢐꢏꢌ ꢑꢌꢎꢇRꢌꢑ ꢒꢙꢏ ꢓRꢌꢗꢘꢌꢊꢂꢔ
ꢄꢉꢆ ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢉꢑꢂR
R
ꢇ
ꢇ
ꢁꢈ0
ꢁꢈR0
Rꢘꢊ0
ꢚ
ꢛ
ꢇ
ꢇ
ꢎꢌꢊꢎꢌ0
ꢎꢌꢊꢎꢌ0
ALERT
ꢂ
FAULT0
ꢚ
ꢛ
ꢎꢔꢊꢂ ꢝꢑꢇꢎꢐꢕꢀꢌꢑꢞ
ꢎꢈꢐRꢌꢟꢂꢀꢠ
ꢖ
ꢖ
ꢎꢌꢊꢎꢌ0
ꢎꢌꢊꢎꢌ0
ꢖ
ꢑꢑꢅꢅ
ꢀꢋꢐꢑ
ꢄꢢꢓ
ꢎꢡꢊꢑ
ꢡꢊꢑ
ꢃꢄꢅꢆ ꢓ0ꢣ
Figure 4. Load Sharing Connections for 3-Phase Operation
OUTPUT CURRENT SENSING AND SUB-MILLIOHM
DCR CURRENT SENSING
system loads. So the new DCR sensing scheme provides a
perfect solution for larger power, and noise sensitive sys-
tems. In the meantime, the current limit threshold is still
a function of the inductor peak current and its DCR value,
and can be accurately set with the MFR_PWM_MODE[2],
MFR_PWM_MODE[7]. See Figure 26.
For DCR current sense applications, a resistor in series
with a capacitor is placed across the inductor. In this
configuration, the resistor is tied to the SW side of the
inductor while the capacitor is tied to the load side of the
inductor as shown in Figure 4. If the RC values are cho-
sen such that the RC time constant matches the inductor
time constant (L/DCR, where DCR is the inductor series
resistance), the resultant voltage appearing across the
capacitor equals the voltage across the inductor series
The RC calculations are based on the room temperature
DCR of the inductor. The RC time constant should remain
constant as a function of temperature. This assures the
transient response of the circuit is the same regardless
of the temperature. The DCR of the inductor has a large
temperature coefficient, approximately 3900ppm/°C. The
temperature coefficient of the inductor must be written
to the MFR_IOUT_CAL_GAIN_TC register. The exter-
nal temperature is sensed near the inductor and used
to modify the internal current limit circuit to maintain
resistance (V ) and thus represents the current flowing
DCR
through the inductor. In addition to this regular current
sensing, the LTC7132 employs a unique architecture to
enhance the signal-to-noise ratio by 14dB, enabling it to
operate with a small sense signal (as low as 2mV) via a
sub-milliohm value of inductor DCR (such as 0.2mΩ) to
improve the power efficiency for the heavy load applica-
an essentially constant current limit with temperature.
+
In this application, the I
pin is connected to the
tions while V
≤ 3.5V. As shown in Figure 4, externally
FET side of the DCR seSnEsNinSgEnfilter capacitor while the
OUT
–
the new architecture only requires reducing R by 4/5, i.e.,
= 1/5Rnomdcr. Better signal-to-noise ratio helps
I
pin is placed on the load side of the capacitor.
SENSEn
R
The current sensed from the input is then given by the
expression VDCR/DCR. VDCR is digitized by the LTC7132’s
LOWDCR
to reduce jitter at the output with as low as 2mV sens-
ing signal. Low DCR improves power efficiency in heavy
telemetry ADC with an input range of 128mV, a noise
Rev 0
24
For more information www.analog.com
LTC7132
OPERATION
+
floor of 7μV , and a peak-peak noise of approximately
RMS
Multiple chips need to tie all the V
pins together, and
SENSE
pins together, and I
–
46.5μV. The LTC7132 computes the inductor current
using the DCR value stored in the IOUT_CAL_GAIN com-
mand and the temperature coefficient stored in command
MFR_IOUT_CAL_GAIN_TC. The resulting current value is
returned by the READ_IOUT command.
all the V
as well.
and I together
THR TH
SENSE
Do not assert bit[5] of MFR_PWM_CONFIG except in a
PolyPhase application.
EXTERNAL/INTERNAL TEMPERATURE SENSE
INPUT CURRENT SENSING
External temperature can best be measured using a
remote, diode-connected PNP transistor such as the
MMBT3906.The emitter should be connected to a TSNS
pin while the base and collector terminals of the PNP
transistor should be returned directly to the LTC7132
SGND pin. Two different currents are applied to the diode
To sense the total input current consumed by the LTC7132
and the power stage, a resistor is placed between the input
+
–
supply voltage and the PV pins. The I and I pins
IN
IN
IN
are connected to the sense resistor. The filtered voltage is
amplified by the internal high side current sense amplifier
and digitized by the LTC7132’s telemetry ADC. The input
current sense amplifier has three gain settings of 2x, 4x,
and 8x set by the bit[6:5] of the MFR_PWM_CONFIG com-
mand. The maximum input sense voltage for the three
gain settings is 50mV, 20mV, and 5mV respectively. The
LTC7132 computes the input current using the R value
stored in the IIN_CAL_GAIN command. The resulting
measured power stage current is returned by the READ_
IIN command.
ꢀꢁꢂꢁ
ꢈꢀꢉꢊꢋꢅꢌ
ꢁꢏꢂꢐ
ꢋ0ꢍꢎ
ꢃꢃꢄꢀꢅꢆ0ꢇ
ꢁꢏꢂꢐ
ꢊꢋꢅꢌ ꢎ0ꢑ
Figure 5. Temperature Sense Circuit
(nominally 2μA and 32μA) and the temperature is calcu-
lated from a ∆V measurement made with the internal
BE
The LTC7132 uses the RVIN resistor to measure the VIN
pin supply current being consumed by the LTC7132. This
value is returned by the MFR_READ_ICHIP command.
The chip current is calculated by using the R value stored
in the MFR_RVIN command. Refer to the subsection
titled Input Current Sense Amplifier in the Applications
Information section for further details.
16-bit monitor ADC (see Figure 5).
The LTC7132 also supports direct VBE based external
temperature measurements. In this case the diode or
diode network is trimmed to a specific voltage at a spe-
cific current and temperature. In general this method does
not yield as accurate result as the single PNP transistor
∆V method, but may function better in a noisy applica-
BE
tion. Refer to MFR_PWM_MODE in the PMBus Command
Details section for additional information on programming
the LTC7132 for these two external temperature sense
configurations. The calculated temperature is returned by
the PMBus READ_TEMPERATURE_1 command. Refer to
the Applications Information section for details on proper
layout of external temperature sense elements and PMBus
commands that can be used to improve the accuracy of
calculated temperatures. The READ_TEMPERATURE_2
command returns the internal junction temperature of the
PolyPhase LOAD SHARING
Multiple LTC7132s can be arrayed in order to provide a
balanced load-share solution by bussing the necessary
pins. Figure 4 illustrates the shared connections required
for load sharing.
If an external oscillator is not provided, the SYNC pin
should only be enabled on one of the LTC7132s. The
other(s) should be programmed to disable SYNC using
bit 4 of MFR_CONFIG_ALL. If an external oscillator is
present, the chip with the SYNC pin enabled will detect
the presence of the external clock and disable its output.
LTC7132 using an on-chip diode with a ∆V measure-
BE
ment and calculation.
Rev 0
25
For more information www.analog.com
LTC7132
OPERATION
The slope of the external temperature sensor can be
modified with the temperature slope coefficient stored in
MFR_TEMP_1_GAIN. Typical PNPs require temperature
slope adjustments slightly less than 1. The MMBT3906
has a recommended value in this command of approxi-
mately MFR_TEMP_1_GAIN = 0.991 based on the ide-
ality factor of 1.01. Simply invert the ideality factor to
calculate the MFR_TEMP_1_GAIN. Different manufactur-
ers and different lots may have different ideality factors.
Consult with the manufacturer to set this value. The off-
set of the external temperature sense can be adjusted by
MFR_TEMP_1_OFFSET. A value of 0 in this register sets
the temperature offset to –273.15°C.
The following parameters are set as a percentage of the
output voltage if the RCONFIG pins are used to determine
the output voltage:
n
VOUT_OV_FAULT_LIMIT.................................. +10%
n
VOUT_OV_WARN_LIMIT................................. +7.5%
n
VOUT_MAX...................................................... +7.5%
n
VOUT_MARGIN_HIGH...........................................5%
n
VOUT_MARGIN_LOW............................................5%
n
VOUT_UV_WARN_LIMIT....................................6.5%
n
VOUT_UV_FAULT_LIMIT.......................................7%
The FREQ_CFG pin settings are described in Table 4. This
pin selects the switching frequency. The phase relation-
ships between the two channels and SYNC pin are deter-
mined by the PHASE_CFG pin described in Table 5. To syn-
chronize to an external clock, the part should be put into
external clock mode (SYNC output disabled but frequency
set to the nominal value). If no external clock is supplied,
the part will clock at the programmed frequency. If the
application is multiphase and the SYNC signal between
chips is lost, the parts will not operate at the designed
phase even if they are programmed and trimmed to the
same frequency. This may increase the ripple voltage
on the output, possibly produce undesirable operation.
If the external SYNC signal is being generated internally
and external SYNC is not selected, bit 10 of MFR_PADS
will be asserted. If no frequency is selected and the exter-
nal SYNC frequency is not present, a PLL_FAULT will
occur. If the user does not wish to see the ALERT from
a PLL_FAULT even if there is not a valid synchronization
signal at power-up, the ALERT mask for PLL_FAULT must
be written. See the description on SMBALERT_MASK for
more details. If the SYNC pin is connected between mul-
tiple ICs only one of the ICs should have the SYNC pin
enabled, and all other ICs should be configured to have
the SYNC pin disabled.
If the PNP cannot be placed in direct contact with the
inductor, the slope or offset can be increased to account
for temperature mismatches. If the user is adjusting the
slope, the intercept point is at absolute zero, –273.15°C, so
small adjustments in slope can change the apparent mea-
sured temperature significantly. Another way to artificially
increase the slope of the temperature term is to increase
the MFR_IOUT_CAL_GAIN_TC term. This will modify the
temperature slope with respect to room temperature.
RCONFIG (RESISTOR CONFIGURATION) PINS
There are six input pins utilizing 1% resistor dividers
between V
and SGND to select key operating param-
DD25
eters. The pins are ASEL0, ASEL1, FREQ_CFG, V
,
OUT0_CFG
VOUT1_CFG, PHASE_CFG. Refer to Tables 3, 4, 5 and 6
for more details of recommended values of these resis-
tive dividers. If pins are floated, the value stored in the
corresponding NVM command is used. If bit 6 of the
MFR_CONFIG_ALL configuration command is asserted
in NVM, the resistor inputs are ignored upon power-up
except for ASEL0 and ASEL1 which are always respected.
The resistor configuration pins are only measured dur-
ing a power-up reset or after a MFR_RESET or after a
RESTORE_USER_ALL command is executed.
The ASEL0,1 pin settings are described in Table 6. ASEL1
selects the top 3 bits of the slave address for the LTC7132.
ASEL0 selects the bottom 4 bits of the slave address for
the LTC7132. If ASEL1 is floating, the 3 most significant
bits are retrieved from the NVM MFR_ADDRESS command.
If ASEL0 is floating, the 4 LSB bits stored in NVM MFR_
ADDRESS command are used to determine the 4 LSB bits
of the slave address. For more detail, refer to Table 6.
The VOUTn_CFG pin settings are described in Table 3. These
pins select the output voltages for the LTC7132’s analog
PWM controllers. If the pin is open, the VOUT_COMMAND
command is loaded from NVM to determine the output
voltage. The default setting is to have the switcher off
unless the voltage configuration pins are installed.
Rev 0
26
For more information www.analog.com
LTC7132
OPERATION
Note: Per the PMBus specification, pin programmed
parameters can be overridden by commands from the
digital interface with the exception of ASEL which is
always honored. Do not set any part address to 0x5A or
0x5B because these are global addresses and all parts
will respond to them.
command operation is performed. The MFR_FAULT_
PROPAGATE command determines if the FAULT pins are
pulled low when a fault is detected.
Output and input fault event handling is controlled by the
corresponding fault response byte as specified in Tables 7
to 12. Shutdown recovery from these types of faults can
either be autonomous or latched. For autonomous recov-
ery, the faults are not latched, so if the fault conditions
not present after the retry interval has elapsed, a new
soft-start is attempted. If the fault persists, the controller
will continue to retry. The retry interval is specified by the
MFR_RETRY_DELAY command and prevents damage to
the regulator components by repetitive power cycling,
assuming the fault condition itself is not immediately
destructive. The MFR_RETRY_DELAY must be greater
than 120ms. It can not exceed 83.88 seconds.
FAULT DETECTION AND HANDLING
A variety of fault and warning reporting and handling
mechanisms are available. Fault and warning detection
capabilities include:
n
Input OV FAULT Protection and UV Warning
n
n
n
n
Average Input OC Warn
Output OV/UV Fault and Warn Protection
Output OC Fault and Warn Protection
Status Registers and ALERT Masking
Internal and External Overtemperature Fault and Warn
Protection
Figure 6 summarizes the internal LTC7132 status regis-
ters accessible by PMBus command. These contain indi-
cation of various faults, warnings and other important
operating conditions. As shown, the STATUS_BYTE and
STATUS_WORD commands also summarize contents of
other status registers. Refer to PMBus Command Details
for specific information.
n
n
n
External Undertemperature Fault and Warn Protection
CML Fault (Communication, Memory or Logic)
External Fault Detection via the Bidirectional FAULTn
Pins.
In addition, the LTC7132 can map any combination of
fault indicators to their respective FAULTn pin using the
propagate FAULTn response commands, MFR_FAULT_
PROPAGATE. Typical usage of a FAULTn pin is as a driver
for an external crowbar device, overtemperature alert,
overvoltage alert or as an interrupt to cause a micro-
controller to poll the fault commands. Alternatively, the
FAULTn pins can be used as inputs to detect external faults
downstream of the controller that require an immediate
response.
NONE OF THE ABOVE in STATUS_BYTE indicates that
one or more of the bits in the most-significant nibble of
STATUS_WORD are also set.
In general, any asserted bit in a STATUS_x register also
pulls the ALERT pin low. Once set, ALERT will remain low
until one of the following occurs.
n
A CLEAR_FAULTS or MFR_RESET Command Is Issued
n
The Related Status Bit Is Written to a One
n
The Faulted Channel Is Properly Commanded Off and
Any fault or warning event will always cause the ALERT
pin to assert low unless the fault or warning is masked by
the SMBALERT_MASK. The pin will remain asserted low
until the CLEAR_FAULTS command is issued, the fault bit
is written to a 1 or bias power is cycled or a MFR_RESET
command is issued, or the RUN pins are toggled OFF/ON
or the part is commanded OFF/ON via PMBus or an ARA
Back On
n
The LTC7132 Successfully Transmits Its Address
During a PMBus ARA
n
Bias Power Is Cycled
Rev 0
27
For more information www.analog.com
LTC7132
OPERATION
STATUS_VOUT*
STATUS_WORD
ꢇꢈ ꢐꢑꢗꢬ
ꢇꢉ ꢛꢑꢗꢬ
ꢇꢊ ꢛꢡꢁꢗꢬ
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
ꢐꢑꢗꢬꢪꢑꢐ ꢒꢓꢔꢕꢖ
ꢐꢑꢗꢬꢪꢑꢐ ꢩꢓꢘꢜꢝꢜꢭ
ꢐꢑꢗꢬꢪꢗꢐ ꢩꢓꢘꢜꢝꢜꢭ
ꢐꢑꢗꢬꢪꢗꢐ ꢒꢓꢔꢕꢖ
ꢐꢑꢗꢬꢪꢱꢂꢵ ꢩꢓꢘꢜꢝꢜꢭ
ꢬꢑꢡꢪꢱꢂꢵ ꢒꢓꢔꢕꢖ
ꢬꢑꢒꢒꢪꢱꢂꢵ ꢩꢓꢘꢜꢝꢜꢭ
ꢀꢘeꢓꢙꢚ 0ꢆ
STATUS_INPUT
ꢐꢛꢡꢪꢑꢐ ꢒꢓꢔꢕꢖ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢐꢛꢡꢪꢗꢐ ꢩꢓꢘꢜꢝꢜꢭ
ꢀꢘeꢓꢙꢚ 0ꢆ
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ꢇꢋ ꢱꢒRꢪꢟꢁꢄꢞꢛꢒꢛꢞ
ꢇꢇ ꢁꢑꢩꢄRꢪꢃꢑꢑꢅꢸ
ꢇ0 ꢀꢘeꢓꢙꢚ 0ꢆ
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
ꢌ
ꢍ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢀꢘeꢓꢙꢚ 0ꢆ
STATUS_BYTE
ꢀꢁꢂꢃꢄꢅꢆ
ꢛꢛꢡꢪꢑꢞ ꢩꢓꢘꢜꢝꢜꢭ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
ꢰꢗꢟꢠ
ꢑꢒꢒ
ꢐꢑꢗꢬꢪꢑꢐ
ꢛꢑꢗꢬꢪꢑꢞ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢬꢄꢱꢁꢄRꢂꢬꢗRꢄ
ꢞꢱꢫ
ꢡꢑꢡꢄ ꢑꢒ ꢬꢳꢄ ꢂꢰꢑꢐꢄ
STATUS_IOUT
STATUS_MFR_SPECIFIC
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
ꢛꢑꢗꢬꢪꢑꢞ ꢒꢓꢔꢕꢖ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢛꢑꢗꢬꢪꢑꢞ ꢩꢓꢘꢜꢝꢜꢭ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
ꢛꢜꢖeꢘꢜꢓꢕ ꢬeꢷꢯeꢘꢓꢖꢔꢘe ꢒꢓꢔꢕꢖ
ꢛꢜꢖeꢘꢜꢓꢕ ꢬeꢷꢯeꢘꢓꢖꢔꢘe ꢩꢓꢘꢜꢝꢜꢭ
ꢄꢄꢁRꢑꢱ ꢞRꢞ ꢄꢘꢘꢢꢘ
ꢛꢜꢖeꢘꢜꢓꢕ ꢁꢫꢫ ꢗꢜꢕꢢꢣꢤeꢙ
ꢒꢓꢔꢕꢖ ꢫꢢꢭ ꢁꢘeꢚeꢜꢖ
ꢐꢅꢅꢊꢊ ꢗꢐ ꢢꢘ ꢑꢐ ꢒꢓꢔꢕꢖ
ꢐꢑꢗꢬ ꢟꢨꢢꢘꢖ ꢞꢦꢣꢕeꢙ
FAULT ꢁꢔꢕꢕeꢙ ꢫꢢꢮ ꢰꢦ ꢄꢧꢖeꢘꢜꢓꢕ ꢅevꢝꢣe
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢀꢘeꢓꢙꢚ 0ꢆ
MFR_COMMON
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
ꢞꢨꢝꢯ ꢡꢢꢖ ꢅꢘꢝvꢝꢜꢭ ALERT ꢫꢢꢮ
ꢞꢨꢝꢯ ꢡꢢꢖ ꢰꢔꢚꢦ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆ
ꢛꢜꢖeꢘꢜꢓꢕ ꢞꢓꢕꢣꢔꢕꢓꢖꢝꢢꢜꢚ ꢡꢢꢖ ꢁeꢜꢙꢝꢜꢭ
ꢑꢔꢖꢯꢔꢖ ꢡꢢꢖ ꢛꢜ ꢬꢘꢓꢜꢚꢝꢖꢝꢢꢜ
ꢄꢄꢁRꢑꢱ ꢛꢜꢝꢖꢝꢓꢕꢝꢲeꢙ
ꢀꢘeꢓꢙꢚ 0ꢆ
STATUS_TEMPERATURE
MFR_PADS
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
ꢑꢬ ꢒꢓꢔꢕꢖ
ꢇꢈ ꢐꢅꢅꢊꢊ ꢑꢐ ꢒꢓꢔꢕꢖ
ꢇꢉ ꢐꢅꢅꢊꢊ ꢗꢐ ꢒꢓꢔꢕꢖ
ꢇꢊ ꢀꢘeꢓꢙꢚ 0ꢆ
ꢇꢋ ꢀꢘeꢓꢙꢚ 0ꢆ
ꢇꢇ ꢛꢜvꢓꢕꢝꢙ ꢂꢅꢞ Reꢚꢔꢕꢖꢀꢚꢆ
ꢇ0 ꢟꢠꢡꢞ ꢞꢕꢢꢣꢤeꢙ ꢥꢦ ꢄꢧꢖeꢘꢜꢓꢕ ꢟꢢꢔꢘꢣe
ꢑꢬ ꢩꢓꢘꢜꢝꢜꢭ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢗꢬ ꢒꢓꢔꢕꢖ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢟꢳꢂRꢄꢪꢞꢫꢴꢪꢫꢑꢩ
ꢩꢁ ꢁꢝꢜ ꢳꢝꢭꢨ
MFR_INFO
ꢇꢈ Reꢚeꢘveꢙ
ꢇꢉ Reꢚeꢘveꢙ
ꢇꢊ Reꢚeꢘveꢙ
ꢇꢋ Reꢚeꢘveꢙ
ꢇꢇ Reꢚeꢘveꢙ
ꢇ0 Reꢚeꢘveꢙ
ꢌ
ꢍ
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
ꢞꢨꢓꢜꢜeꢕ ꢇ ꢝꢚ ꢁꢑꢩꢄRꢪꢃꢑꢑꢅ
ꢞꢨꢓꢜꢜeꢕ 0 ꢝꢚ ꢁꢑꢩꢄRꢪꢃꢑꢑꢅ
ꢫꢬꢞꢎꢇꢊꢋ ꢒꢢꢘꢣꢝꢜꢭ Rꢗꢡꢇ ꢫꢢꢮ
ꢫꢬꢞꢎꢇꢊꢋ ꢒꢢꢘꢣꢝꢜꢭ Rꢗꢡ0 ꢫꢢꢮ
Rꢗꢡꢇ ꢁꢝꢜ ꢟꢖꢓꢖe
ꢀꢁꢂꢃꢄꢅꢆ
STATUS_CML
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
ꢛꢜvꢓꢕꢝꢙꢶꢗꢜꢚꢔꢯꢯꢢꢘꢖeꢙ ꢞꢢꢷꢷꢓꢜꢙ
ꢛꢜvꢓꢕꢝꢙꢶꢗꢜꢚꢔꢯꢯꢢꢘꢖeꢙ ꢅꢓꢖꢓ
ꢁꢓꢣꢤeꢖ ꢄꢘꢘꢢꢘ ꢞꢨeꢣꢤ ꢒꢓꢝꢕeꢙ
ꢱeꢷꢢꢘꢦ ꢒꢓꢔꢕꢖ ꢅeꢖeꢣꢖeꢙ
ꢁꢘꢢꢣeꢚꢚꢢꢘ ꢒꢓꢔꢕꢖ ꢅeꢖeꢣꢖeꢙ
ꢀꢘeꢓꢙꢚ 0ꢆ
Rꢗꢡ0 ꢁꢝꢜ ꢟꢖꢓꢖe
ꢌ
ꢍ
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
Reꢚeꢘveꢙ
Reꢚeꢘveꢙ
Reꢚeꢘveꢙ
Reꢚeꢘveꢙ
Reꢚeꢘveꢙ
ꢄꢄꢁRꢑꢱ ꢄꢞꢞ ꢟꢖꢓꢖꢔꢚ
Reꢚeꢘveꢙ
Reꢚeꢘveꢙ
Reꢚeꢘveꢙ
ꢫꢬꢞꢎꢇꢊꢋ ꢒꢢꢘꢣꢝꢜꢭ FAULT1 ꢫꢢꢮ
ꢫꢬꢞꢎꢇꢊꢋ ꢒꢢꢘꢣꢝꢜꢭ FAULT0 ꢫꢢꢮ
FAULT1 ꢁꢝꢜ ꢟꢖꢓꢖe
FAULT0 ꢁꢝꢜ ꢟꢖꢓꢖe
ꢎꢇꢊꢋ ꢒ0ꢎ
ꢑꢖꢨeꢘ ꢞꢢꢷꢷꢔꢜꢝꢣꢓꢖꢝꢢꢜ ꢒꢓꢔꢕꢖ
ꢑꢖꢨeꢘ ꢱeꢷꢢꢘꢦ ꢢꢘ ꢫꢢꢭꢝꢣ ꢒꢓꢔꢕꢖ
Reꢚeꢘveꢙ
DESCRIPTION
MASKABLE GENERATES ALERT BIT CLEARABLE
ꢃeꢜeꢘꢓꢕ ꢒꢓꢔꢕꢖ ꢢꢘ ꢩꢓꢘꢜꢝꢜꢭ ꢄveꢜꢖ
ꢃeꢜeꢘꢓꢕ ꢡꢢꢜꢺꢱꢓꢚꢤꢓꢥꢕe ꢄveꢜꢖ
ꢅꢦꢜꢓꢷꢝꢣ
ꢠeꢚ
ꢡꢢ
ꢡꢢ
ꢡꢢ
ꢠeꢚ
ꢠeꢚ
ꢡꢢ
ꢠeꢚ
ꢠeꢚ
ꢡꢢ
ꢟꢖꢓꢖꢔꢚ ꢅeꢘꢝveꢙ ꢹꢘꢢꢷ ꢑꢖꢨeꢘ ꢰꢝꢖꢚ
ꢡꢢꢖ ꢅꢝꢘeꢣꢖꢕꢦ
ꢡꢢ
Figure 6. LTC7132 Status Register Summary
Rev 0
28
For more information www.analog.com
LTC7132
OPERATION
With some exceptions, the SMBALERT_MASK com-
mand can be used to prevent the LTC7132 from assert-
ing ALERT for bits in these registers on a bit-by-bit basis.
These mask settings are promoted to STATUS_WORD
and STATUS_BYTE in the same fashion as the status bits
themselves. For example, if ALERT is masked for all bits
in Channel 0 STATUS_VOUT, then ALERT is effectively
masked for the VOUT bit in STATUS_WORD for PAGE 0.
faults cleared when either RUN pin is toggled or, set bit 0
of MFR_CONFIG_ALL to a 1.
The status of all faults and warnings is summarized in the
STATUS_WORD and STATUS_BYTE commands.
Additional fault detection and handling capabilities are:
Power Good Pins
The PGOODn pins of the LTC7132 are connected to the
open drains of internal MOSFETs. The MOSFETs turn on
and pull the PGOODn pins low when the channel output
voltage is not within the channel’s UV and OV voltage
thresholds. During TON_DELAY and TON_RISE sequenc-
ing, the PGOODn pin is held low. The PGOODn pin is
also pulled low when the respective RUNn pin is low. The
PGOODn pin response is deglitched by an internal 60μs
digital filter. The PGOODn pin and PGOOD status may be
different at times due to communication latency of up to
10µs.
The BUSY bit in STATUS_BYTE also asserts ALERT low
and cannot be masked. This bit can be set as a result of
various internal interactions with PMBus communication.
This fault occurs when a command is received that cannot
be safely executed with one or both channels enabled. As
discussed in Application Information, BUSY faults can
be avoided by polling MFR_COMMON before executing
some commands.
If masked faults occur immediately after power up, ALERT
may still be pulled low because there has not been time
to retrieve all of the programmed masking information
from EEPROM.
CRC Protection
Status information contained in MFR_COMMON and
MFR_PADS can be used to further debug or clarify the
contents of STATUS_BYTE or STATUS_WORD as shown,
but the contents of these registers do not affect the state
of the ALERT pin and may not directly influence bits in
STATUS_BYTE or STATUS_WORD.
The integrity of the NVM memory is checked after a power
on reset. A CRC error will prevent the controller from leav-
ing the inactive state. If a CRC error occurs, the CML bit is
set in the STATUS_BYTE and STATUS_WORD commands,
the appropriate bit is set in the STATUS_MFR_SPECIFIC
command, and the ALERT pin will be pulled low. NVM
repair can be attempted by writing the desired configura-
tion to the controller and executing a STORE_USER_ALL
command followed by a CLEAR_FAULTS command.
Mapping Faults to FAULT Pins
Channel-to-channel fault (including channels from mul-
tiple LTC7132s) dependencies can be created by con-
necting FAULTn pins together. In the event of an internal
fault, one or more of the channels is configured to pull
the bussed FAULTn pins low. The other channels are then
configured to shut down when the FAULTn pins are pulled
low. For autonomous group retry, the faulted channel is
configured to let go of the FAULTn pin(s) after a retry
interval, assuming the original fault has cleared. All the
channels in the group then begin a soft-start sequence. If
the fault response is LATCH_OFF, the FAULTn pin remains
asserted low until either the RUN pin is toggled OFF/ON or
the part is commanded OFF/ON. The toggling of the RUN
either by the pin or OFF/ON command will clear faults
associated with the channel. If it is desired to have all
The LTC7132 manufacturing section of the NVM is mir-
rored. If both copies are corrupted, the “NVM CRC Fault”
in the STATUS_MFR_SPECIFIC command is set. If this
bit remains set after being cleared by issuing a CLEAR_
FAULTS or writing a 1 to this bit, an irrecoverable internal
fault has occurred. The user is cautioned to disable both
output power supply rails associated with this specific
part. There are no provisions for field repair of NVM faults
in the manufacturing section.
SERIAL INTERFACE
The LTC7132 serial interface is a PMBus compliant
slave device and can operate at any frequency between
Rev 0
29
For more information www.analog.com
LTC7132
OPERATION
10kHz and 400kHz. The address is configurable using
either the NVM or an external resistor divider. In addition
the LTC7132 always responds to the global broadcast
address of 0x5A (7 bit) or 0x5B (7 bit).
channel being acted upon. Device addressing can be dis-
abled by writing a value of 0x80 to the MFR_ADDRESS.
Rail addressing provides a means for the bus master to
simultaneously communicate with all channels connected
together to produce a single output voltage (PolyPhase).
While similar to global addressing, the rail address can
be dynamically assigned with the paged MFR_RAIL_
ADDRESS command, allowing for any logical grouping
of channels that might be required for reliable system
control. Reading from rail addresses is also strongly
discouraged.
The serial interface supports the following protocols
defined in the PMBus specifications: 1) send command,
2) write byte, 3) write word, 4) group, 5) read byte, 6) read
word and 7) read block. 8) write block. All read operations
will return a valid PEC if the PMBus master requests it. If
the PEC_REQUIRED bit is set in the MFR_CONFIG_ALL
command, the PMBus write operations will not be acted
upon until a valid PEC has been received by the LTC7132.
All four means of PMBus addressing require the user to
employ disciplined planning to avoid addressing con-
flicts. Communication to LTC7132 devices at global
and rail addresses should be limited to command write
operations.
Communication Protection
PEC write errors (if PEC_REQUIRED is active), attempts
to access unsupported commands, or writing invalid data
to supported commands will result in a CML fault. The
CML bit is set in the STATUS_BYTE and STATUS_WORD
commands, the appropriate bit is set in the STATUS_CML
command, and the ALERT pin is pulled low.
RESPONSES TO V
and I /I
FAULTS
OUT
IN OUT
V
OV and UV conditions are monitored by compara-
OUT
tors. The OV and UV limits are set in three ways.
n
DEVICE ADDRESSING
As a Percentage of the VOUT if Using the Resistor
Configuration Pins
The LTC7132 offers five different types of addressing over
the PMBus interface, specifically: 1) global, 2) device, 3)
rail addressing and 4) alert response address (ARA).
n
In NVM if Either Programmed at the Factory or Through
the GUI
n
Global addressing provides a means of the PMBus master
to address all LTC7132 devices on the bus. The LTC7132
global address is fixed 0x5A (7 bit) or 0xB4 (8 bit) and can-
not be disabled. Commands sent to the global address act
the same as if PAGE is set to a value of 0xFF. Commands
sent are written to both channels simultaneously. Global
command 0x5B (7 bit) or 0xB6 (8 bit) is paged and allows
channel specific command of all LTC7132 devices on the
bus. Other ADI device types may respond at one or both
of these global addresses. Reading from global addresses
is strongly discouraged.
By PMBus Command
The I and I
overcurrent monitors are performed by
ADC IrNeadingOsUaTnd calculations. Thus these values are
based on average currents and can have a time latency
of up to t
. The I
calculation accounts for the
CONVERT
OUT
DCR or sense resistor and their temperature coefficient.
The input current is equal to the voltage measured across
the R
resistor divided by the resistors value as set
IINSNS
with the MFR_IIN_CAL_GAIN command. If this calcu-
lated input current exceeds the IN_OC_WARN_LIMIT the
ALERT pin is pulled low and the IIN_OC_WARN bit is
asserted in the STATUS_INPUT command.
Device addressing provides the standard means of the
PMBus master communicating with a single instance of
an LTC7132. The value of the device address is set by a
combination of the ASEL0 and ASEL1 configuration pins
and the MFR_ ADDRESS command. When this address-
ing means is used, the PAGE command determines the
The digital processor within the LTC7132 provides the
ability to ignore the fault, shut down and latch off or shut
down and retry indefinitely (hiccup). The retry interval
is set in MFR_RETRY_ DELAY and can be from 120ms
Rev 0
30
For more information www.analog.com
LTC7132
OPERATION
to 83.88 seconds in 1ms increments. The shutdown for
OV/UV and OC can be done immediately or after a user
selectable deglitch time.
circuit operates by limiting the I maximum voltage. If
TH
DCR sensing is used, the ITH maximum voltage has a
temperature dependency directly proportional to the TC
of the DCR of the inductor. The LTC7132 automatically
monitors the external temperature sensors and modifies
Output Overvoltage Fault Response
the maximum allowed I to compensate for this term.
TH
A programmable overvoltage comparator (OV) guards
against transient overshoots as well as long-term over-
voltages at the output. In such cases, the top MOSFET is
turned off and the bottom MOSFET is turned on. However,
the reverse output current is monitored while device is in
OV fault. When it reaches the limit, both top and bottom
MOSFETs are turned off. The top and bottom MOSFETs will
keep their state until the overvoltage condition is cleared
regardless of the PMBus VOUT_OV_FAULT_RESPONSE
command byte value. This hardware level fault response
delay is typically 2μs from the overvoltage condition to BG
asserted high. Using the VOUT_OV_FAULT_RESPONSE
command, the user can select any of the following
behaviors:
The overcurrent fault processing circuitry can execute the
following behaviors:
n
Current Limit Indefinitely
n
Shut Down Immediately—Latch Off
n
Shut Down Immediately—Retry Indefinitely at the Time
Interval Specified in MFR_RETRY_DELAY.
The overcurrent responses can be deglitched in incre-
ments of (0-7) • 16ms. See Table 9.
RESPONSES TO TIMING FAULTS
TON_MAX_FAULT_LIMIT is the time allowed for V
to
OUT
n
OV Pull-Down Only (OV Cannot Be Ignored)
rise and settle at start-up. The TON_MAX_FAULT_LIMIT
condition is predicated upon detection of the VOUT_UV_
FAULT_LIMIT as the output is undergoing a SOFT_START
sequence. The TON_MAX_ FAULT_LIMIT time is started
after TON_DELAY has been reached and a SOFT_START
sequence is started. The resolution of the TON_MAX_
FAULT_LIMIT is 10μs. If the VOUT_UV_FAULT _LIMIT
is not reached within the TON_MAX_FAULT_LIMIT time,
the response of this fault is determined by the value of
the TON_MAX_FAULT_RESPONSE command value. This
response may be one of the following:
n
Shut Down (Stop Switching) Immediately—Latch Off
n
Shut Down Immediately—Retry Indefinitely at the Time
Interval Specified in MFR_RETRY_DELAY
Either the Latch Off or Retry fault responses can be
deglitched in increments of (0-7) • 10μs. See Table 7.
Output Undervoltage Response
The response to an undervoltage comparator output can
be the following:
n
Ignore
n
Ignore
n
Shut Down (Stop Switching) Immediately—Latch Off
n
Shut Down Immediately—Latch Off
n
Shut Down Immediately—Retry Indefinitely at the Time
Interval Specified in MFR_RETRY_DELAY.
n
Shut Down Immediately—Retry Indefinitely at the Time
Interval Specified in MFR_RETRY_DELAY.
This fault response is not deglitched. A value of 0 in
TON_MAX_FAULT_LIMIT means the fault is ignored. The
TON_MAX_FAULT_LIMIT should be set longer than the
TON_RISE time. It is recommended TON_MAX_FAULT_
LIMIT always be set to a non-zero value, otherwise the
output may never come up and no flag will be set to the
user. See Table 11.
The UV responses can be deglitched. See Table 8.
Peak Output Overcurrent Fault Response
Due to the current mode control algorithm, peak output
current across the inductor is always limited on a cycle-
by-cycle basis. The value of the peak current limit is speci-
fied in sense voltage in the EC table. The current limit
Rev 0
31
For more information www.analog.com
LTC7132
OPERATION
RESPONSES TO V OV FAULTS
RESPONSES TO INPUT OVERCURRENT AND OUTPUT
UNDERCURRENT FAULTS
IN
V overvoltage is measured with the ADC. The response
IN
is naturally deglitched by the 90ms typical response time
Input overcurrent and output undercurrent are measured
with the ADC. The fault responses are:
of the ADC. The fault responses are:
n
n
Ignore
Ignore
n
n
Shut Down Immediately—Latch Off
Shut Down Immediately—Latch Off
n
n
Shut Down Immediately—Retry Indefinitely at the Time
Interval Specified in MFR_RETRY_DELAY. See Table 11.
Shut Down Immediately—Retry Indefinitely at the Time
Interval Specified in MFR_RETRY_DELAY
See Table 11.
RESPONSES TO OT/UT FAULTS
RESPONSES TO EXTERNAL FAULTS
Internal Overtemperature Fault Response
When either FAULTn pin is pulled low, the OTHER bit is
set in the STATUS_WORD command, the appropriate bit
is set in the STATUS_MFR_SPECIFIC command, and the
ALERT pin is pulled low. Responses are not deglitched.
Each channel can be configured to ignore or shut down
then retry in response to its FAULTn pin going low by
modifying the MFR_FAULT_RESPONSE command. To
avoid the ALERT pin asserting low when FAULT is pulled
low, assert bit 1 of MFR_CHAN_CONFIG, or mask the
ALERT using the SMBALERT_MASK command.
An internal temperature sensor protects against NVM
damage. Above 85°C, no writes to NVM are recom-
mended. Above 130°C, the internal overtemperature warn
threshold is exceeded and the part disables the NVM and
does not re-enable until the temperature has dropped to
125°C. When the die temperature exceed 160°C the inter-
nal temperature fault response is enabled and the PWM
is disabled until the die temperature drops below 150°C.
Temperature is measured by the ADC. Internal tempera-
ture faults cannot be ignored. Internal temperature limits
cannot be adjusted by the user. See Table 10.
FAULT LOGGING
External Overtemperature and Undertemperature
Fault Response
The LTC7132 has fault logging capability. Data is logged
into memory in the order shown in Table 13. The data is
stored in a continuously updated buffer in RAM. When a
fault event occurs, the fault log buffer is copied from the
RAM buffer into NVM. Fault logging is allowed at tem-
peratures above 85°C; however, retention of 10 years is
not guaranteed. When the die temperature exceeds 130°C
the fault logging is delayed until the die temperature drops
below 125°C. The fault log data remains in NVM until a
MFR_FAULT _LOG_CLEAR command is issued. Issuing
this command re-enables the fault log feature. Before re-
enabling fault log, be sure no faults are present and a
CLEAR_FAULTS command has been issued.
Two external temperature sensors can be used to sense
the temperature of critical circuit elements like inductors
and power MOSFETs. The OT_FAULT_ RESPONSE and
UT_FAULT_ RESPOSE commands are used to determine
the appropriate response to an overtemperature and
under temperature condition, respectively. If no exter-
nal sense elements are used (not recommended) set the
UT_FAULT_RESPONSE to ignore and set the UT_FAULT_
LIMIT to –275°C. The fault responses are:
n
Ignore
n
Shut Down Immediately—Latch Off
When the LTC7132 powers-up or exits its reset state,
it checks the NVM for a valid fault log. If a valid fault
log exists in NVM, the “Valid Fault Log” bit in the
n
Shut Down Immediately—Retry Indefinitely at the Time
Interval Specified in MFR_RETRY_DELAY. See Table 9.
Rev 0
32
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LTC7132
OPERATION
STATUS_MFR_SPECIFIC command will be set and an
ALERT event will be generated. Also, fault logging will
be blocked until the LTC7132 has received a MFR_
FAULT_LOG_CLEAR command before fault logging will
be re-enabled.
differences in timing, DC parameters and protocol. The
PMBus/SMBus protocols are more robust than simple
I2C byte commands because PMBus/SMBus provide
timeouts to prevent persistent bus errors and optional
packet error checking (PEC) to ensure data integrity.
2
In general, a master device that can be configured for I C
The information is stored in EEPROM in the event of
any fault that disables the controller on either channel. A
FAULTn being externally pulled low will not trigger a fault
logging event.
communication can be used for PMBus communication
with little or no change to hardware or firmware. Repeat
2
start (restart) is not supported by all I C controllers but
is required for SMBus/PMBus reads. If a general purpose
2
I C controller is used, check that repeat start is supported.
BUS TIMEOUT PROTECTION
The LTC7132 supports the maximum SMBus clock speed
of 100kHz and is compatible with the higher speed PMBus
specification (between 100kHz and 400kHz) if MFR_
COMMON polling or clock stretching is enabled. For
robust communication and operation refer to the Note
section in the PMBus command summary. Clock stretch-
ing is enabled by asserting bit 1 of MFR_CONFIG_ALL.
The LTC7132 implements a timeout feature to avoid per-
sistent faults on the serial interface. The data packet timer
begins at the first START event before the device address
write byte. Data packet information must be completed
within 30ms or the LTC7132 will three-state the bus and
ignore the given data packet. If more time is required,
assert bit 3 of MFR_CONFIG_ALL to allow typical bus
timeouts of 255ms. Data packet information includes the
device address byte write, command byte, repeat start
event (if a read operation), device address byte read
(if a read operation), all data bytes and the PEC byte if
applicable.
For a description of the minor extensions and exceptions
PMBus makes to SMBus, refer to PMBus Specification
Part 1 Revision 1.2: Paragraph 5: Transport.
For a description of the differences between SMBus
and I2C, refer to System Management Bus (SMBus)
Specification Version 2.0: Appendix B—Differences
The LTC7132 allows longer PMBus timeouts for block
read data packets. This timeout is proportional to the
length of the block read. The additional block read time-
out applies primarily to the MFR_FAULT_LOG command.
The timeout period defaults to 32ms.
2
Between SMBus and I C.
PMBus SERIAL DIGITAL INTERFACE
The LTC7132 communicates with a host (master) using
the standard PMBus serial bus interface. The Timing
Diagram, Figure 7, shows the timing relationship of the
signals on the bus. The two bus lines, SDA and SCL, must
be high when the bus is not in use. External pull-up resis-
tors or current sources are required on these lines. The
LTC7132 is a slave device. The master can communicate
with the LTC7132 using the following formats:
The user is encouraged to use as high a clock rate as
possible to maintain efficient data packet transfer between
all devices sharing the serial bus interface. The LTC7132
supports the full PMBus frequency range from 10kHz to
400kHz.
2
SIMILARITY BETWEEN PMBus, SMBus AND I C
2-WIRE INTERFACE
n
Master Transmitter, Slave Receiver
Master Receiver, Slave Transmitter
The PMBus 2-wire interface is an incremental extension
n
2
of the SMBus. SMBus is built upon I C with some minor
Rev 0
33
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LTC7132
OPERATION
The following PMBus protocols are supported:
n
Master reads slave immediately after the first byte. At
the moment of the first acknowledgment (provided by
the slave receiver) the master transmitter becomes a
master receiver and the slave receiver becomes a slave
transmitter.
n
Write Byte, Write Word, Send Byte
n
Read Byte, Read Word, Block Read, Block Write
n
Alert Response Address
n
Combined format. During a change of direction within
a transfer, the master repeats both a start condition and
the slave address but with the R/W bit reversed. In this
case, the master receiver terminates the transfer by
generating a NACK on the last byte of the transfer and
a STOP condition.
Figures 8-25 illustrate the aforementioned PMBus proto-
cols. All transactions support PEC and GCP (group com-
mand protocol). The Block Read supports 255 bytes of
returned data. For this reason, the PMBus timeout may
be extended when reading the fault log.
Figure 8 is a key to the protocol diagrams in this section.
PEC is optional.
Refer to Figure 8 for a legend.
Handshaking features are included to ensure robust
system communication. Please refer to the PMBus
Communication and Command Processing subsection
of the Applications Information section for further details.
A value shown below a field in the following figures is
mandatory value for that field.
The data formats implemented by PMBus are:
n
Master transmitter transmits to slave receiver. The
transfer direction in this case is not changed.
ꢀꢁꢂ
ꢅ
ꢓ
ꢅ
ꢀꢊꢇꢁꢂꢈꢉ
ꢅ
ꢅ
ꢀꢍ
ꢅ
ꢆꢁꢇꢀꢁꢂꢉ
ꢓ
ꢅ
ꢔ
ꢅ
ꢅ
ꢔ
ꢅ
ꢎꢊꢏ
ꢄꢋꢌ
ꢀꢃꢄ
ꢅ
ꢅ
ꢅ
ꢀꢊꢇꢀꢈꢋꢉ
ꢆꢁꢇꢀꢈꢂꢉ
ꢀꢊꢇꢀꢈꢂꢉ
ꢅ
ꢅ
ꢆꢑꢕꢆ
ꢆꢁꢇꢁꢂꢈꢉ
ꢖꢗꢘꢙ ꢏ0ꢚ
ꢀꢈꢂRꢈ
ꢃꢋꢐꢁꢑꢈꢑꢋꢐ
Rꢒꢍꢒꢂꢈꢒꢁ ꢀꢈꢂRꢈ
ꢃꢋꢐꢁꢑꢈꢑꢋꢐ
ꢀꢈꢋꢍ
ꢀꢈꢂRꢈ
ꢃꢋꢐꢁꢑꢈꢑꢋꢐ ꢃꢋꢐꢁꢑꢈꢑꢋꢐ
Figure 7. Timing Diagram
Table 1. Abbreviations of Supported Data Formats
PMBus
SPECIFICATION
ADI
TERMINOLOGY
L11 Linear
REFERENCE TERMINOLOGY DEFINITION
EXAMPLE
N
Part II ¶7.1
Linear_5s_1s Floating point 16-bit data: value = Y • 2 , b[15:0] = 0x9807 = 10011_000_0000_0111
–13
where N = b[15:11] and Y = b[10:0], both value = 7 • 2 = 854E-6
two’s compliment binary integers.
–12
L16 Linear VOUT_MODE
CF DIRECT
Part II ¶8.2
Part II ¶7.2
Linear_16u
Varies
Floating point 16-bit data: value = Y • 2 , b[15:0] = 0x4C00 = 0100_1100_0000_0000
–12
where Y = b[15:0], an unsigned integer.
value = 19456 • 2 = 4.75
16-bit data with a custom format
defined in the detailed PMBus command
description.
Often an unsigned or two’s compliment
integer.
Reg register bits
Part II ¶10.3
Reg
Per-bit meaning defined in detailed PMBus PMBus STATUS_BYTE command.
command description.
ASC text characters
Part II ¶22.2.1
ASCII
ISO/IEC 8859-1 [A05]
LTC (0x4C5443)
Rev 0
34
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LTC7132
OPERATION
ꢅ
ꢅꢆꢇRꢆ ꢈꢉꢊꢋꢌꢆꢌꢉꢊ
ꢅꢍ
Rꢎꢏꢎꢇꢆꢎꢋ ꢅꢆꢇRꢆ ꢈꢉꢊꢋꢌꢆꢌꢉꢊ
Rꢐ Rꢎꢇꢋ ꢑꢒꢌꢆ ꢓꢇꢔꢕꢎ ꢉꢄ ꢁꢖ
ꢗꢍ ꢗRꢌꢆꢎ ꢑꢒꢌꢆ ꢓꢇꢔꢕꢎ ꢉꢄ 0ꢖ
ꢇ
ꢇꢈꢘꢊꢉꢗꢔꢎꢋꢙꢎ ꢑꢆꢚꢌꢅ ꢒꢌꢆ ꢏꢉꢅꢌꢆꢌꢉꢊ ꢛꢇꢜ ꢒꢎ 0
ꢄꢉR ꢇꢊ ꢇꢈꢘ ꢉR ꢁ ꢄꢉR ꢇ ꢊꢇꢈꢘꢖ
ꢏ
ꢅꢆꢉꢏ ꢈꢉꢊꢋꢌꢆꢌꢉꢊ
ꢏꢎꢈ ꢏꢇꢈꢘꢎꢆ ꢎRRꢉR ꢈꢉꢋꢎ
ꢛꢇꢅꢆꢎR ꢆꢉ ꢅꢔꢇꢓꢎ
ꢅꢔꢇꢓꢎ ꢆꢉ ꢛꢇꢅꢆꢎR
ꢝꢝꢝ
ꢈꢉꢊꢆꢌꢊꢕꢇꢆꢌꢉꢊ ꢉꢄ ꢏRꢉꢆꢉꢈꢉꢔ
ꢀꢁꢂꢃ ꢄ0ꢀ
Figure 8. PMBus Packet Protocol Diagram Element Key
ꢌ
ꢋ
ꢌ
ꢌ
ꢌ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢆꢇꢈꢉ
ꢂ
ꢊ
ꢋꢌꢍꢎ ꢏ0ꢐ
Figure 9. Quick Command Protocol
ꢎ
ꢍ
ꢎ
ꢎ
ꢓ
ꢎ
ꢎ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢊꢋ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢌ
ꢍꢎꢏꢐ ꢑ0ꢒ
Figure 10 . Send Byte Protocol
ꢎ
ꢍ
ꢎ
ꢎ
ꢒ
ꢎ
ꢒ
ꢎ
ꢎ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢋꢌ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢊꢄꢆ
ꢂ
ꢊ
ꢍꢎꢏꢐ ꢑꢎꢐ
Figure 11. Send Byte Protocol with PEC
ꢑ
ꢐ
ꢑ
ꢑ
ꢕ
ꢑ
ꢕ
ꢑ
ꢑ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢍꢎ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢅꢂꢊꢂ ꢋꢌꢊꢄ
ꢂ
ꢏ
ꢐꢑꢒꢓ ꢔꢑꢒ
Figure 12. Write Byte Protocol
ꢑ
ꢐ
ꢑ
ꢑ
ꢖ
ꢑ
ꢖ
ꢑ
ꢖ
ꢑ
ꢑ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢍꢎ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢅꢂꢊꢂ ꢋꢌꢊꢄ
ꢂ
ꢏꢄꢆ
ꢂ
ꢏ
ꢐꢑꢒꢓ ꢔꢑꢕ
Figure 13. Write Byte Protocol with PEC
ꢑ
ꢐ
ꢑ
ꢑ
ꢖ
ꢑ
ꢖ
ꢑ
ꢑ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢍꢎ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢅꢂꢊꢂ ꢋꢌꢊꢄ
ꢂ
ꢏ
ꢐꢑꢒꢓ ꢔꢑꢕ
Figure 14. Write Word Protocol
ꢑ
ꢐ
ꢑ
ꢑ
ꢖ
ꢑ
ꢖ
ꢑ
ꢖ
ꢑ
ꢑ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢍꢎ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢅꢂꢊꢂ ꢋꢌꢊꢄ
ꢂ
ꢏꢄꢆ
ꢂ
ꢏ
ꢐꢑꢒꢓ ꢔꢑꢕ
Figure 15. Write Word Protocol with PEC
Rev 0
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LTC7132
OPERATION
ꢎ
ꢍ
ꢎ
ꢎ
ꢒ
ꢎ
ꢎ
ꢍ
ꢎ
ꢎ
ꢒ
ꢎ
ꢎ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢊꢋ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢀꢋ ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢖ
ꢂ
ꢅꢂꢓꢂ ꢔꢕꢓꢄ
ꢂ
ꢌ
ꢍꢎꢏꢐ ꢑꢎꢍ
Figure 16. Read Byte Protocol
ꢎ
ꢍ
ꢎ
ꢎ
ꢒ
ꢎ
ꢎ
ꢍ
ꢎ
ꢎ
ꢒ
ꢎ
ꢎ
ꢎ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢊꢋ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢀꢋ ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢖ
ꢂ
ꢅꢂꢓꢂ ꢔꢕꢓꢄ
ꢂ
ꢌꢄꢆ
ꢂ
ꢌ
ꢍꢎꢏꢐ ꢑꢎꢒ
Figure 17. Read Byte Protocol with PEC
ꢎ
ꢍ
ꢎ
ꢎ
ꢓ
ꢎ
ꢎ
ꢍ
ꢎ
ꢎ
ꢓ
ꢎ
ꢓ
ꢎ
ꢎ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢊꢋ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢀꢋ ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢚ
ꢂ
ꢅꢂꢔꢂ ꢕꢖꢔꢄ ꢁꢇꢊ
ꢂ
ꢅꢂꢔꢂ ꢕꢖꢔꢄ ꢗꢘꢙꢗ
ꢂ
ꢌ
ꢍꢎꢏꢐ ꢑꢎꢒ
Figure 18. Read Word Protocol
ꢎ
ꢍ
ꢎ
ꢎ
ꢒ
ꢎ
ꢎ
ꢍ
ꢎ
ꢎ
ꢒ
ꢎ
ꢒ
ꢎ
ꢒ
ꢎ
ꢎ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢊꢋ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢀꢋ ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢙ
ꢂ
ꢅꢂꢓꢂ ꢔꢕꢓꢄ ꢁꢇꢊ
ꢂ
ꢅꢂꢓꢂ ꢔꢕꢓꢄ ꢖꢗꢘꢖ
ꢂ
ꢌꢄꢆ
ꢂ
ꢌ
ꢍꢎꢏꢐ ꢑꢐ0
Figure 19. Read Word Protocol with PEC
ꢎ
ꢌ
ꢎ
ꢎ
ꢍ
ꢎ
ꢎ
ꢌ
ꢎ
ꢎ
ꢍ
ꢎ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢊꢋ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢀꢋ ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢔ
ꢂ
ꢏꢐꢑꢄ ꢆꢇꢒꢉꢑ ꢓ ꢉ
ꢂ
ꢕ
ꢍ
ꢎ
ꢍ
ꢎ
ꢕ
ꢕ
ꢍ
ꢎ
ꢎ
ꢅꢂꢑꢂ ꢏꢐꢑꢄ ꢎ
ꢂ
ꢅꢂꢑꢂ ꢏꢐꢑꢄ ꢘ
ꢂ
ꢅꢂꢑꢂ ꢏꢐꢑꢄ ꢉ
ꢂ
ꢖ
ꢌꢎꢗꢘ ꢙꢘꢎ
Figure 20 . Block Read Protocol
ꢎ
ꢌ
ꢎ
ꢎ
ꢍ
ꢎ
ꢎ
ꢌ
ꢎ
ꢎ
ꢍ
ꢎ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢊꢋ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢀꢋ ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢔ
ꢂ
ꢏꢐꢑꢄ ꢆꢇꢒꢉꢑ ꢓ ꢉ
ꢂ
ꢕ
ꢍ
ꢎ
ꢍ
ꢎ
ꢕ
ꢕ
ꢍ
ꢎ
ꢍ
ꢎ
ꢎ
ꢅꢂꢑꢂ ꢏꢐꢑꢄ ꢎ
ꢂ
ꢅꢂꢑꢂ ꢏꢐꢑꢄ ꢖ
ꢂ
ꢅꢂꢑꢂ ꢏꢐꢑꢄ ꢉ
ꢂ
ꢗꢄꢆ
ꢂ
ꢗ
ꢌꢎꢘꢖ ꢙꢖꢖ
Figure 21. Block Read Protocol with PEC
Rev 0
36
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LTC7132
OPERATION
ꢓ
ꢑ
ꢓ
ꢓ
ꢒ
ꢓ
ꢒ
ꢓ
ꢒ
ꢓ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢏꢐ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢊꢋꢌꢄ ꢆꢇꢍꢉꢌ ꢎ ꢈ
ꢂ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢓ
ꢂ
ꢔ
ꢒ
ꢓ
ꢒ
ꢓ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢕ
ꢂ
ꢔ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢈ
ꢂ
ꢔ
ꢓ
ꢑ
ꢓ
ꢓ
ꢒ
ꢓ
ꢒ
ꢓ
ꢓ
ꢀꢐ ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢖ
ꢂ
ꢊꢋꢌꢄ ꢆꢇꢍꢉꢌ ꢎ ꢉ
ꢂ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢓ
ꢂ
ꢔ
ꢒ
ꢓ
ꢔ
ꢔ
ꢒ
ꢓ
ꢓ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢕ
ꢂ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢉ
ꢂ
ꢗ
ꢑꢓꢘꢕ ꢙꢕꢘ
Figure 22. Block Write – Block Read Process Call
ꢓ
ꢑ
ꢓ
ꢓ
ꢒ
ꢓ
ꢒ
ꢓ
ꢒ
ꢓ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢏꢐ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢊꢋꢌꢄ ꢆꢇꢍꢉꢌ ꢎ ꢈ
ꢂ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢓ
ꢂ
ꢔ
ꢒ
ꢓ
ꢒ
ꢓ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢕ
ꢂ
ꢔ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢈ
ꢂ
ꢔ
ꢓ
ꢑ
ꢓ
ꢓ
ꢒ
ꢓ
ꢒ
ꢓ
ꢓ
ꢀꢐ ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢖ
ꢂ
ꢊꢋꢌꢄ ꢆꢇꢍꢉꢌ ꢎ ꢉ
ꢂ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢓ
ꢂ
ꢔ
ꢒ
ꢓ
ꢔ
ꢔ
ꢒ
ꢓ
ꢒ
ꢓ
ꢓ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢕ
ꢂ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢉ
ꢂ
ꢗꢄꢆ
ꢂ
ꢗ
ꢑꢓꢘꢕ ꢙꢕꢚ
Figure 23. Block Write – Block Read Process Call with PEC
ꢋ
ꢊ
ꢋ
ꢋ
ꢐ
ꢋ
ꢋ
ꢀꢁꢂRꢃ Rꢂꢄꢅꢆꢇꢄꢂ
ꢀꢈꢈRꢂꢄꢄ
ꢄ
Rꢉ
ꢀ
ꢈꢂꢑꢒꢓꢂ ꢀꢈꢈRꢂꢄꢄ
ꢀ
ꢅ
ꢊꢋꢌꢍ ꢎꢍꢏ
Figure 24. Alert Response Address Protocol
ꢌ
ꢊ
ꢌ
ꢌ
ꢋ
ꢌ
ꢋ
ꢌ
ꢌ
ꢀꢁꢂRꢃ Rꢂꢄꢅꢆꢇꢄꢂ
ꢀꢈꢈRꢂꢄꢄ
ꢄ
Rꢉ
ꢀ
ꢈꢂꢍꢎꢏꢂ ꢀꢈꢈRꢂꢄꢄ
ꢀ
ꢅꢂꢏ
ꢀ
ꢅ
ꢊꢌꢐꢑ ꢒꢑꢓ
Figure 25. Alert Response Address Protocol with PEC
Rev 0
37
For more information www.analog.com
LTC7132
PMBus COMMAND SUMMARY
PMBus COMMANDS
table are implicitly not supported by the manufacturer.
Attempting to access non-supported or reserved com-
mands may result in a CML command fault event. All
output voltage settings and measurements are based on
The following tables list supported PMBus commands and
manufacturer specific commands. A complete description
of these commands can be found in the “PMBus Power
System Mgt Protocol Specification – Part II – Revision
1.2”. Users are encouraged to reference this specifica-
tion. Exceptions or manufacturer specific implementa-
tions are listed below in Table 2. Floating point values
listed in the “DEFAULT VALUE” column are either Linear
16-bit Signed (PMBus Section 8.3.1) or Linear_5s_11s
(PMBus Section 7.1) format, whichever is appropriate for
the command. All commands from 0xD0 through 0xFF not
listed in this table are implicitly reserved by the manufac-
turer. Users should avoid blind writes within this range
of commands to avoid undesired operation of the part.
All commands from 0x00 through 0xCF not listed in this
the VOUT_MODE setting of 0x14. This translates to an
–12
exponent of 2
.
If PMBus commands are received faster than they are
being processed, the part may become too busy to handle
new commands. In these circumstances the part follows
the protocols defined in the PMBus Specification v1.2,
Part II, Section 10.8.7, to communicate that it is busy.
The part includes handshaking features to eliminate busy
errors and simplify error handling software while ensur-
ing robust communication and system behavior. Please
refer to the subsection titled PMBus Communication and
Command Processing in the Applications Information
section for further details.
Table 2. Summary (Note: The Data Format abbreviations are detailed at the end of this table.)
CMD
DATA
PAGED FORMAT UNITS NVM
DEFAULT
VALUE PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGE
0x00 Provides integration with multi-page PMBus
devices.
R/W Byte
N
Y
Y
Reg
Reg
Reg
0x00
0x80
0x1E
NA
68
72
72
OPERATION
0x01 Operating mode control. On/off, margin high
and margin low.
R/W Byte
R/W Byte
Y
Y
ON_OFF_CONFIG
0x02 RUN pin and PMBus bus on/off command
configuration.
CLEAR_FAULTS
0x03 Clear any fault bits that have been set.
Send Byte
W Block
N
N
N
N
97
69
69
69
PAGE_PLUS_WRITE
PAGE_PLUS_READ
WRITE_PROTECT
0x05 Write a command directly to a specified page.
0x06 Read a command directly from a specified page. Block R/W
0x10 Level of protection provided by the device
against accidental changes.
R/W Byte
Reg
Reg
Y
0x00
STORE_USER_ALL
RESTORE_USER_ALL
CAPABILITY
0x15 Store user operating memory to EEPROM.
Send Byte
N
N
N
NA
NA
108
108
96
0x16 Restore user operating memory from EEPROM. Send Byte
0x19 Summary of PMBus optional communication
protocols supported by this device.
R Byte
0xB0
SMBALERT_MASK
VOUT_MODE
0x1B Mask ALERT activity
Block R/W
R Byte
Y
Y
Reg
Reg
Y
see CMD 97
–12
0x20 Output voltage format and exponent (2 ).
2–12
0x14
77
79
77
78
79
VOUT_COMMAND
VOUT_MAX
0x21 Nominal output voltage set point.
R/W Word
R/W Word
R/W Word
R/W Word
Y
Y
Y
Y
L16
L16
L16
L16
V
V
V
V
Y
Y
Y
Y
1.0
0x1000
0x24 Upper limit on the commanded output voltage
including VOUT_MARGIN_HI.
2.75
0x2C00
VOUT_MARGIN_HIGH
VOUT_MARGIN_LOW
0x25 Margin high output voltage set point. Must be
greater than VOUT_COMMAND.
1.05
0x10CD
0x26 Margin low output voltage set point. Must be
less than VOUT_COMMAND.
0.95
0x0F33
Rev 0
38
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LTC7132
PMBus COMMAND SUMMARY
CMD
DATA
PAGED FORMAT UNITS NVM
DEFAULT
VALUE PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
VOUT_TRANSITION_
RATE
0X27 Rate the output changes when VOUT
commanded to a new value.
R/W Word
Y
N
N
N
Y
L11
L11
L11
L11
L11
V/ms
kHz
V
Y
Y
Y
Y
Y
0.25
85
76
76
77
80
0xAA00
FREQUENCY_SWITCH
0x33 Switching frequency of the controller.
R/W Word
R/W Word
R/W Word
R/W Word
425k
0xFB52
VIN_ON
0x35 Input voltage at which the unit should start
power conversion.
6.5
0xCB40
VIN_OFF
0x36 Input voltage at which the unit should stop
power conversion.
V
6.0
0xCB00
IOUT_CAL_GAIN
0x38 The ratio of the voltage at the current sense
pins to the sensed current. For devices using a
fixed current sense resistor, it is the resistance
value in mΩ.
mΩ
0.32
0xAA8F
VOUT_OV_FAULT_LIMIT 0x40 Output overvoltage fault limit.
R/W Word
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
N
N
Y
L16
Reg
L16
L16
L16
Reg
L11
Reg
L11
L11
Reg
L11
L11
Reg
L11
Reg
L11
L11
L11
V
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
1.1
78
87
78
79
79
88
80
90
81
83
92
83
84
92
76
87
76
82
84
0x119A
VOUT_OV_FAULT_
RESPONSE
0x41 Action to be taken by the device when an output R/W Byte
overvoltage fault is detected.
0xB8
VOUT_OV_WARN_LIMIT 0x42 Output overvoltage warning limit.
VOUT_UV_WARN_LIMIT 0x43 Output undervoltage warning limit.
VOUT_UV_FAULT_LIMIT 0x44 Output undervoltage fault limit.
R/W Word
R/W Word
R/W Word
V
V
V
1.075
0x1133
0.925
0x0ECD
0.9
0x0E66
VOUT_UV_FAULT_
RESPONSE
0x45 Action to be taken by the device when an output R/W Byte
undervoltage fault is detected.
0xB8
IOUT_OC_FAULT_LIMIT
0x46 Output overcurrent fault limit.
R/W Word
A
45.0
0xE2D0
IOUT_OC_FAULT_
RESPONSE
0x47 Action to be taken by the device when an output R/W Byte
overcurrent fault is detected.
0x00
IOUT_OC_WARN_LIMIT
0x4A Output overcurrent warning limit.
R/W Word
R/W Word
R/W Byte
R/W Word
R/W Word
R/W Byte
R/W Word
R/W Byte
R/W Word
R/W Word
R/W Word
A
C
35.0
0xE230
OT_FAULT_LIMIT
0x4F External overtemperature fault limit.
100.0
0xEB20
OT_FAULT_RESPONSE
OT_WARN_LIMIT
0x50 Action to be taken by the device when an
external overtemperature fault is detected,
0xB8
0x51 External overtemperature warning limit.
C
C
85.0
0xEAA8
UT_FAULT_LIMIT
0x53 External undertemperature fault limit.
–40.0
0xE580
UT_FAULT_RESPONSE
VIN_OV_FAULT_LIMIT
0x54 Action to be taken by the device when an
external undertemperature fault is detected.
0xB8
0x55 Input supply overvoltage fault limit.
V
15.5
0xD3E0
VIN_OV_FAULT_
RESPONSE
0x56 Action to be taken by the device when an input
overvoltage fault is detected.
0x80
VIN_UV_WARN_LIMIT
IIN_OC_WARN_LIMIT
TON_DELAY
0x58 Input supply undervoltage warning limit.
V
A
6.3
0xCB26
0x5D Input supply overcurrent warning limit.
10.0
0xD280
0x60 Time from RUN and/or Operation on to output
rail turn-on.
ms
0.0
0x8000
Rev 0
39
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LTC7132
PMBus COMMAND SUMMARY
CMD
DATA
DEFAULT
VALUE PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
TON_RISE
0x61 Time from when the output starts to rise
until the output voltage reaches the VOUT
commanded value.
R/W Word
Y
L11
ms
Y
8.0
0xD200
84
TON_MAX_FAULT_LIMIT 0x62 Maximum time from the start of TON_RISE for R/W Word
VOUT to cross the VOUT_UV_FAULT_LIMIT.
Y
Y
Y
Y
Y
L11
Reg
L11
L11
L11
ms
Y
Y
Y
Y
Y
10.00
85
90
85
85
86
0xD280
TON_MAX_FAULT_
RESPONSE
0x63 Action to be taken by the device when a TON_
MAX_FAULT event is detected.
R/W Byte
0xB8
TOFF_DELAY
0x64 Time from RUN and/or Operation off to the start R/W Word
of TOFF_FALL ramp.
ms
ms
ms
0.0
0x8000
TOFF_FALL
0x65 Time from when the output starts to fall until
the output reaches zero volts.
R/W Word
8.00
0xD200
TOFF_MAX_WARN_LIMIT 0x66 Maximum allowed time, after TOFF_FALL
completed, for the unit to decay below 12.5%.
R/W Word
150.0
0xF258
STATUS_BYTE
STATUS_WORD
STATUS_VOUT
STATUS_IOUT
STATUS_INPUT
0x78 One byte summary of the unit’s fault condition. R/W Byte
0x79 Two byte summary of the unit’s fault condition. R/W Word
Y
Y
Y
Y
N
Y
Reg
Reg
Reg
Reg
Reg
Reg
NA
NA
NA
NA
NA
NA
98
99
0x7A Output voltage fault and warning status.
0x7B Output current fault and warning status.
0x7C Input supply fault and warning status.
R/W Byte
R/W Byte
R/W Byte
R/W Byte
99
100
100
101
STATUS_TEMPERATURE 0x7D External temperature fault and warning status
for READ_TEMPERATURE_1.
STATUS_CML
0x7E Communication and memory fault and warning R/W Byte
status.
N
Y
Reg
Reg
NA
NA
101
102
STATUS_MFR_SPECIFIC 0x80 Manufacturer specific fault and state
information.
R/W Byte
READ_VIN
READ_IIN
0x88 Measured input supply voltage.
0x89 Measured input supply current.
0x8B Measured output voltage.
0x8C Measured output current.
R Word
R Word
R Word
R Word
R Word
N
N
Y
Y
Y
L11
L11
L16
L11
L11
V
A
V
A
C
NA
NA
NA
NA
NA
104
104
104
105
105
READ_VOUT
READ_IOUT
READ_TEMPERATURE_1 0x8D External temperature sensor temperature. This
is the value used for all temperature related
processing, including IOUT_CAL_GAIN.
READ_TEMPERATURE_2 0x8E Internal die junction temperature. Does not
affect any other commands.
R Word
N
L11
C
NA
105
READ_FREQUENCY
READ_POUT
0x95 Measured PWM switching frequency.
0x96 Measured output power
R Word
R Word
R Word
R Byte
Y
Y
Y
N
L11
L11
L11
Reg
Hz
W
W
NA
N/A
105
105
105
96
READ_PIN
0x97 Calculated input power
N/A
PMBus_REVISION
0x98 PMBus revision supported by this device.
Current revision is 1.2.
0x22
MFR_ID
0x99 The manufacturer ID of the LTC7132 in ASCII.
0x9A Manufacturer part number in ASCII.
R String
R String
R Word
N
N
Y
ASC
ASC
L16
LTC
96
MFR_MODEL
MFR_VOUT_MAX
LTC7132 96
0xA5 Maximum allowed output voltage including
VOUT_OV_FAULT_LIMIT.
V
5.7
0x5B33
79
MFR_PIN_ACCURACY
0xAC Returns the accuracy of the READ_PIN
command
R Byte
N
%
5.0%
105
Rev 0
40
For more information www.analog.com
LTC7132
PMBus COMMAND SUMMARY
CMD
DATA
PAGED FORMAT UNITS NVM
DEFAULT
VALUE PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
USER_DATA_00
0xB0 OEM RESERVED. Typically used for part
serialization.
R/W Word
N
Reg
Y
NA
95
USER_DATA_01
USER_DATA_02
0xB1 Manufacturer reserved for LTpowerPlay.
R/W Word
R/W Word
Y
N
Reg
Reg
Y
Y
NA
NA
95
95
0xB2 OEM RESERVED. Typically used for part
serialization
USER_DATA_03
USER_DATA_04
MFR_INFO
0xB3 An NVM word available for the user.
0xB4 An NVM word available for the user.
0xB6 Manufacturer specific information
0xBD Contact factory.
R/W Word
R/W Word
R/W Word
Y
N
N
Reg
Reg
Reg
Y
Y
0x0000
0x0000
NA
95
95
103
112
MFR_EE_UNLOCK
MFR_EE_ERASE
0xBE Contact factory.
112
MFR_EE_DATA
0xBF Contact factory.
112
70
MFR_CHAN_CONFIG
MFR_CONFIG_ALL
0xD0 Configuration bits that are channel specific.
0xD1 General configuration bits.
R/W Byte
R/W Byte
R/W Word
Y
N
Y
Reg
Reg
Reg
Y
Y
Y
0x1D
0x21
71
MFR_FAULT_PROPAGATE 0xD2 Configuration that determines which faults are
propagated to the FAULT pin.
0x6993
93
MFR_PWM_COMP
MFR_PWM_MODE
0xD3 PWM loop compensation configuration
0xD4 Configuration for the PWM engine.
R/W Byte
R/W Byte
R/W Byte
Y
Y
Y
Reg
Reg
Reg
Y
Y
Y
0xAE
0xC7
0xC0
74
73
95
MFR_FAULT_RESPONSE 0xD5 Action to be taken by the device when the
FAULT pin is externally asserted low.
MFR_OT_FAULT_
RESPONSE
0xD6 Action to be taken by the device when an
internal overtemperature fault is detected.
R Byte
R Word
N
Y
N
Y
Y
Y
N
Y
Reg
L11
Reg
L11
L11
L16
L11
L11
0xC0
NA
91
105
106
86
MFR_IOUT_PEAK
0xD7 Report the maximum measured value of READ_
IOUT since last MFR_CLEAR_PEAKS.
A
MFR_ADC_CONTROL
MFR_RETRY_DELAY
MFR_RESTART_DELAY
MFR_VOUT_PEAK
MFR_VIN_PEAK
0xD8 ADC telemetry parameter selected for repeated
fast ADC read back
R/W Byte
R/W Word
R/W Word
R Word
0x00
0xDB Retry interval during FAULT retry mode.
ms
ms
V
Y
Y
350.0
0xFABC
0xDC Minimum time the RUN pin is held low by the
LTC7132.
500.0
0xFBE8
86
0xDD Maximum measured value of READ_VOUT
since last MFR_CLEAR_PEAKS.
NA
NA
NA
106
106
106
0xDE Maximum measured value of READ_VIN since
last MFR_CLEAR_PEAKS.
R Word
V
MFR_TEMPERATURE_1_ 0xDF Maximum measured value of external
PEAK
R Word
C
Temperature (READ_TEMPERATURE_1) since
last MFR_CLEAR_PEAKS.
MFR_READ_IIN_PEAK
0xE1 Maximum measured value of READ_IIN
command since last MFR_CLEAR_PEAKS
R Word
N
L11
A
A
NA
106
MFR_CLEAR_PEAKS
MFR_READ_ICHIP
MFR_PADS
0xE3 Clears all peak values.
Send Byte
R Word
N
N
N
N
N
NA
NA
98
106
102
70
0xE4 Measured supply current of the LTC7132
0xE5 Digital status of the I/O pads.
L11
Reg
Reg
Reg
R Word
NA
2
MFR_ADDRESS
MFR_SPECIAL_ID
0xE6 Sets the 7-bit I C address byte.
R/W Byte
R Word
Y
0x4F
0xE7 Manufacturer code representing the LTC7132
and revision
0x4C0X
0x4CEX
96
Rev 0
41
For more information www.analog.com
LTC7132
PMBus COMMAND SUMMARY
CMD
DATA
DEFAULT
VALUE PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
MFR_IIN_CAL_GAIN
0xE8 The resistance value of the input current sense R/W Word
element in mΩ.
N
N
N
L11
mΩ
Y
5.0
82
0xCA80
MFR_FAULT_LOG_STORE 0xEA Command a transfer of the fault log from RAM
to EEPROM.
Send Byte
NA
NA
109
112
MFR_FAULT_LOG_CLEAR 0xEC Initialize the EEPROM block reserved for fault
logging.
Send Byte
MFR_FAULT_LOG
MFR_COMMON
0xEE Fault log data bytes.
R Block
R Byte
N
N
Reg
Reg
Y
NA
NA
109
103
0xEF Manufacturer status bits that are common
across multiple ADI chips.
MFR_COMPARE_USER_ 0xF0 Compares current command contents with
ALL NVM.
Send Byte
R Word
N
N
N
Y
N
Y
Y
Y
NA
NA
108
106
75
MFR_TEMPERATURE_2_ 0xF4 Peak internal die temperature since last
L11
Reg
CF
C
PEAK
MFR_CLEAR_PEAKS.
MFR_PWM_CONFIG
0xF5 Set numerous parameters for the DC/DC
controller including phasing.
R/W Byte
R/W Word
R/W Word
R/W Word
R/W Word
R/W Byte
Y
Y
Y
Y
Y
Y
0x10
MFR_IOUT_CAL_GAIN_
TC
0xF6 Temperature coefficient of the current sensing
element.
ppm/
˚C
3900
0x0F3C
80
MFR_RVIN
0xF7 The resistance value of the VIN pin filter
element in mΩ.
L11
CF
mΩ
1000
0x03E8
77
MFR_TEMP_1_GAIN
MFR_TEMP_1_OFFSET
MFR_RAIL_ADDRESS
0xF8 Sets the slope of the external temperature
sensor.
1.0
0x4000
83
0xF9 Sets the offset of the external temperature
sensor with respect to –273.1°C
L11
Reg
CF
C
0.0
0x8000
83
0xFA Common address for PolyPhase outputs to
adjust common parameters.
0x80
70
MFR_REAL_TIME
MFR_RESET
0xFB 48-bit share-clock counter value.
R Block
N
N
NA
NA
107
72
0xFD Commanded reset without requiring a power
down.
Send Byte
Note 1: Commands indicated with Y in the NVM column indicate that these
commands are stored and restored using the STORE_USER_ALL and
RESTORE_USER_ALL commands, respectively.
Note 4: Some of the unpublished commands are read-only and will
generate a CML bit 6 fault if written.
Note 5: Writing to commands not published in this table is not permitted.
Note 2: Commands with a default value of NA indicate “not applicable”.
Commands with a default value of FS indicate “factory set on a per part
basis”.
Note 3: The LTC7132 contains additional commands not listed in this
table. Reading these commands is harmless to the operation of the IC;
however, the contents and meaning of these commands can change
without notice.
Note 6: The user should not assume compatibility of commands
between different parts based upon command names. Always refer to
the manufacturer’s data sheet for each part for a complete definition of a
command’s function.
ADI strives to keep command functionality compatible between all ADI
devices. Differences may occur to address specific product requirements.
Rev 0
42
For more information www.analog.com
LTC7132
PMBus COMMAND SUMMARY
*DATA FORMAT
L11 Linear_5s_11s
PMBus data field b[15:0]
N
Value = Y • 2
where N = b[15:11] is a 5-bit two’s complement integer and Y = b[10:0] is an 11-bit
two’s complement integer
Example:
For b[15:0] = 0x9807 = ‘b10011_000_0000_0111
–13
–6
Value = 7 • 2 = 854 • 10
From “PMBus Spec Part II: Paragraph 7.1”
L16 Linear_16u
PMBus data field b[15:0]
N
Value = Y • 2
where Y = b[15:0] is an unsigned integer and N = Vout_mode_parameter is a 5-bit two’s
complement exponent that is hardwired to –12 decimal
Example:
For b[15:0] = 0x9800 = ‘b1001_1000_0000_0000
–12
Value = 19456 • 2 = 4.75
From “PMBus Spec Part II: Paragraph 8.2”
Reg Register
PMBus data field b[15:0] or b[7:0].
Bit field meaning is defined in detailed PMBus Command Description.
I16 Integer Word
PMBus data field b[15:0]
Value = Y
where Y = b[15:0] is a 16 bit unsigned integer
Example:
For b[15:0] = 0x9807 = ‘b1001_1000_0000_0111
Value = 38919 (decimal)
CF Custom Format
ASC ASCII Format
Value is defined in detailed PMBus Command Description.
This is often an unsigned or two’s complement integer scaled by an MFR specific
constant.
A variable length string of text characters conforming to ISO/IEC 8859-1 standard.
Rev 0
43
For more information www.analog.com
LTC7132
APPLICATIONS INFORMATION
The Typical Application on the back page is a common
LTC7132 application circuit. The LTC7132 is mainly
designed for low DCR application via PMBus command
exceeding that current limit, an OC fault will be issued.
Each range in Figure 26 affects the loop gain, and sub-
sequently effects the loop stability, so setting range of
current limiting is a part of loop design.
MFR_PWM_MODE[2] = 1 applicable when 0 ≤ V
≤
OUT
3.5V, but it can be also configured to be regular DCR or
ꢆ00
regular resistor sensing by setting MFR_PWM_MODE[2]
ꢇ0
= 0 for 0≤ V
≤ 5.5V. The choice among them is largely
OUT
ꢈ0
a design trade-off between cost, power consumption and
accuracy. DCR sensing is becoming popular because it
saves expensive current sensing resistors and is more
power efficient, especially in high current applications.
Low DCR provides the most power efficient solution, and
best signal-to-noise ratio of the input sensing voltage.
The accuracy of the current reading and current limit
are typically limited by the accuracy of the DCR resis-
tor (accounted for in the IOUT_CAL_GAIN parameter of
the LTC7132). Thus current sensing resistors provide the
most accurate current sensing and limiting for the appli-
cation. Other external component selection is driven by
the load requirement, and begins with the selection of
ꢐꢓRꢕꢖꢗꢐꢕꢐꢘꢙꢚꢛꢊꢜꢝ0
ꢐꢓRꢕꢖꢗꢐꢕꢐꢘꢙꢚꢛꢔꢜꢝꢆ
Rꢞ ꢝ ꢏꢟꢙꢞR
ꢉ0
ꢊ0
ꢐꢓRꢕꢖꢗꢐꢕꢐꢘꢙꢚꢛꢊꢜꢝ0
ꢐꢓRꢕꢖꢗꢐꢕꢐꢘꢙꢚꢛꢔꢜꢝ0
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0
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Figure 26. VITH vs VILIMIT
The LTC7132 will account for the DCR of the inductor if
the device is configured for DCR sensing and automati-
cally update the current limit as the inductor temperature
changes. The temperature coefficient of the DCR is stored
in the MFR_IOUT_CAL_GAIN_TC register. The setting
MFR_PWM_MODE[2] = 1, MFR_PWM_MODE[7] = 0,
allows for the use of very low DCR inductors or sense
resistors, the peak output current is up to 16.5mV/DCR,
the application LTC7132 is mainly designed for. Keep in
mind this operation is based on a cycle-by-cycle basis and
is only a function of the peak inductor current. The aver-
age inductor current is monitored by the ADC converter
and can provide a warning if too much average output
current is detected. The overcurrent fault is detected when
R
(if R
is used) and inductor value. Then the
SENSE
SENSE
input and output capacitors are selected. To have a stable
loop performance and reliability, the loop compensation
parameters such as GM of error amplifier programmed
by MFR_PWM_ COMP[7:5] and RTH by MFR_PWM_
COMP[4:0] together with current limit range, set by bit[7]
of MFR_PWM_MODE and voltage range set by bit[1] of
MFR_ PWM_MODE have to be properly selected. All other
programmable parameters do not affect the loop gain,
allowing parameters to be modified without impacting
the transient response to load changes.
the I voltage hits the maximum value. The digital pro-
TH
CURRENT LIMIT PROGRAMMING
cessor within the LTC7132 provides the ability to either
ignore the fault, shut down and latch off or shut down and
retry indefinitely (hiccup). Refer to the overcurrent portion
of the Operation section for more detail.
The cycle-by-cycle current limit threshold voltage,
V
, across the I
+/I
– pins is proportional
SENSE SENSE
toILVIMITITH. The VITH limit can be programmed from 1.45
to 2.2V using the PMBUS command IOUT_OC_FAULT_
LIMIT. See Figure 26. The LTC7132 has four ranges of
current limit programming. Properly setting the value of
MFR_PWM_MODE[2] and MFR_PWM_MODE[7], and
IOUT_OC_FAULT_LIMIT, see the section of the PMBus
commands, the device can regulate output voltage with
the peak current under the value of IOUT_OC_FAULT_
LIMIT in normal operation. In case of output current
±
±
I
AND I
PINS
SENSE0
SENSE1
+
–
The I
and I
pins are the inputs to the current
SENSE
SENSE
comparator and the A/D. The common mode input voltage
range of the current comparators is 0V to 5.5V. Both the
SENSE pins are high impedance inputs with small input
currents typically less than 1µA. The high impedance
Rev 0
44
For more information www.analog.com
LTC7132
APPLICATIONS INFORMATION
inputs to the current comparators enable accurate DCR
sensing. Do not float these pins during normal operation.
The RC sense filter time constant must be set by the fol-
lowing equations:
Filter components connected to the I
traces should
RC =L/(5 •DCR) at MFR_PWM_MODE[2]=1 for low DCR
RC = L/DCR at MFR_PWM_MODE[2] = 0 for normal DCR
where:
SENSE
be placed close to the IC. The positive and negative traces
should be routed differentially and Kelvin connected to the
current sense element; see Figure 27. A non-Kelvin connec-
tion or improper placement can add parasitic inductance
and capacitance to the current sense element, degrading the
signal at the sense terminals and making the programmed
current limit perform poorly. In a PolyPhase system, poor
placement of the sensing element will result in sub-optimal
current sharing between power stages. If DCR sensing is
used (Figure 28a), sense resistor R1 should be placed close
to the inductor to prevent noise from coupling into sensi-
tive small-signal nodes. The capacitor C1 should be placed
close to the IC pins. Any impedance difference between the
V
: Maximum sense voltage for a given I
TH
SENSE(MAX)
voltage
I
: Maximum load current
MAX
∆I : Inductor ripple current
L
DCR: Inductor resistance
RC: Filter time constant
During normal DCR sensing, the voltage ripple across C1
is equal to the voltage ripple across the inductor DCR.
During low DCR sensing, the voltage ripple across C1 is
equal to the 5x the voltage ripple across the inductor DCR.
+
–
I
and I
signal paths can result in loss of accu-
SENSE
SENSE
racy in the current reading of the ADC. The current reading
accuracy can be improved by matching the impedance of
the two signal paths. To accomplish this add a series resis-
tor R3 between VOUT and ISENSE– equal to R1. A capacitor of
1µF or greater should be placed in parallel with this resistor.
To ensure the load current will be delivered over the full
operating temperature range, the temperature coefficient
of DCR resistance, approximately 3900ppm/˚C, should be
taken into consideration.
Typically, C is selected in the range of 0.047µF to 0.47µF.
This forces R1 to around 2kΩ at MFR_PWM_MODE[2]=0,
400Ω at MFR_PWM_MODE[2]=1 reducing error that
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might have been caused by the I
pins’ 1µA current
SENSE
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(R3 and C2 are for reducing sensing error caused by input
current through R1).
Figure 27. Sense Lines Placement with Inductor DCR
There will be some power loss in R1 that relates to the
duty cycle, and will be the most in continuous mode at
the maximum input voltage:
Inductor DCR Sensing
The DCR is the DC winding resistance of the inductor's
copper, which is often less than 1mΩ for high current
inductors. In high current and low output voltage applica-
tions, a conduction loss of a high DCR or a sense resistor
will cause a significant reduction in power efficiency. For a
specific output requirement, choose the inductor with the
DCR that satisfies the maximum desirable sense voltage,
and uses the relationship of the sense pin filters to output
inductor characteristics as depicted in the following:
V
IN(MAX) – VOUT •V
(
)
OUT
P
R1 =
LOSS ( )
R1
Ensure that R1 has a power rating higher than this value.
However, DCR sensing eliminates the conduction loss of
sense resistor; it will provide better efficiency at heavy
loads. To maintain a good signal-to-noise ratio for low cur-
rent sense signals, it is best to enable the LOW DCR sens-
ing network (MFR_PWM_MODE[2] = 1, RC = L/(5 • DCR).
VSENSE(MAX)
DCR=
ΔIL
IMAX
+
2
Rev 0
45
For more information www.analog.com
LTC7132
APPLICATIONS INFORMATION
For a DCR sensing application, the peak-to-peak ripple
voltage will be determined by the equation:
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
VOUT V – V
IN
OUT
ΔVSENSE
=
•
V
RC•fOSC
IN
LOW VALUE RESISTOR CURRENT SENSING
Low DCR sensing can be used at ∆V
as 2mV.
signal as low
SENSE
A typical sensing circuit using a discrete resistor is shown
in Figure 28b. RSENSE is chosen based on the required
output current.
INDUCTOR VALUE CALCULATION
The current comparator has a maximum threshold
V
determined by the I
setting. The input
Given the desired input and output voltages, the inductor
value and operating frequency, fOSC, directly determine
the inductor peak-to-peak ripple current:
SENSE(MAX)
LIMIT
common mode range of the current comparator is 0V to
5.5V. The current comparator threshold sets the peak of
the inductor current, yielding a maximum average output
VOUT V – V
(
)
current I
equal to the peak value less half the peak-
IN
OUT
MAX
∆IL =
to-peak ripple current ∆I . To calculate the sense resistor
V •fOSC •L
L
IN
value, use the equation:
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors, and output voltage
ripple. Thus, at a given frequency, the highest efficiency
operation is obtained with a small ripple current, which
requires a large inductor.
VSENSE(MAX)
RSENSE
=
ΔIL
2
IMAX
+
Due to possible PCB noise in the current sensing loop, the
AC current sensing ripple of ∆V = ∆I • R also
SENSE
L
SENSE
A reasonable starting point is to choose a ripple current
that is about 40% of IOUT(MAX). Note that the largest ripple
current occurs at the highest input voltage. To guarantee
that the ripple current does not exceed a specified maxi-
mum, the inductor should be chosen according to:
needs to be checked in the design to get a good signal-to-
noise ratio. In general, for a reasonably good PCB layout,
a 15mV minimum ∆V
voltage is recommended as a
SENSE
conservative number to start with for RSENSE applications.
For previous generation current mode controllers, the
maximum sense voltage was high enough (e.g., 75mV for
the LTC1628/LTC3728 family) that the voltage drop across
the parasitic inductance of the sense resistor represented
a relatively small error. In the newer and higher current
density solutions, the value of the sense resistor can be
less than 1mΩ and the peak sense voltage can be less than
20mV. Also, inductor ripple currents greater than 50%
with operation up to 750kHz are becoming more common.
Under these conditions, the voltage drop across the sense
resistor’s parasitic inductance is no longer negligible. A
typical sensing circuit using a discrete resistor is shown in
Figure 28b. In previous generations of controllers, a small
RC filter placed near the IC was commonly used to reduce
the effects of the capacitive and inductive noise coupled
in the sense traces on the PCB. A typical filter consists of
two series 100Ω resistors connected to a parallel 1000pF
VOUT V – V
(
)
IN
OUT
L≥
V •f •IRIPPLE
IN
OSC
INDUCTOR CORE SELECTION
Once the inductor value is determined, the type of induc-
tor must be selected. Core loss is independent of core
size for a fixed inductor value, but it is very dependent
on inductance. As the inductance increases, core losses
go down. Unfortunately, increased inductance requires
more turns of wire and therefore copper losses increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core materials saturate hard, which means that the induc-
tance collapses abruptly when the peak design current is
capacitor, resulting in a time constant of 200ns.
Rev 0
46
For more information www.analog.com
LTC7132
APPLICATIONS INFORMATION
If the RC time constant is chosen to be close to the para-
sitic inductance divided by the sense resistor (L/R), the
resultant waveform looks resistive, as shown in
Figure 29b. For applications using low maximum sense
voltages, check the sense resistor manufacturer’s data
sheet for information about parasitic inductance. In the
absence of data, measure the voltage drop directly across
the sense resistor to extract the magnitude of the ESL step
and use Equation 1 to determine the ESL. However, do not
overfilter the signal. Keep the RC time constant less than
or equal to the inductor time constant to maintain a suf-
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ficient ripple voltage on V
for optimal operation of
RSENSE
the current loop controller.
Figure 28a. Inductor DCR Current Sense Circuit
INTV
CC
SENSE RESISTOR
PLUS PARASITIC
INDUCTANCE
BOOST
SW
ꢆ
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L
R
S
ESL
ꢊ0ꢋꢆꢃꢄꢅꢆ
V
OUT
LTC7132
C • 2 ≤ ESL/R
F
RF
S
GND
+
POLE-ZERO
CANCELLATION
R
R
F
F
I
SENSE
C
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–
7132 F29b
I
SENSE
Figure 29a. Voltage Measured Directly Across RSENSE
FILTER COMPONENTS
PLACED NEAR SENSE PINS
Figure 28b. Resistor Current Sense Circuit
This same RC filter, with minor modifications, can be used
to extract the resistive component of the current sense
signal in the presence of parasitic inductance. For exam-
ple, Figure 29a illustrates the voltage waveform across a
2mΩ resistor with a PCB footprint of 2010. The waveform
is the superposition of a purely resistive component and a
purely inductive component. It was measured using two
scope probes and waveform math to obtain a differential
measurement. Based on additional measurements of the
inductor ripple current and the on-time, t , and off-time,
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Figure 29b. Voltage Measured After the RSENSE Filter
t
, of the top switch, the value of theOpNarasitic induc-
SLOPE COMPENSATION AND INDUCTOR PEAK
CURRENT
OFF
tance was determined to be 0.5nH using the equation:
Slope compensation provides stability in constant-fre-
quency current-mode architectures by preventing sub-
harmonic oscillations at high duty cycles. This is accom-
plished internally by adding a compensation ramp to the
inductor current signal. The LTC7132 uses a patented
(
)
VESL STEP tON •tOFF
ESL =
•
(1)
ΔIL
tON + tOFF
Rev 0
47
For more information www.analog.com
LTC7132
APPLICATIONS INFORMATION
current limit technique that counteracts the compensating
ramp. This allows the maximum inductor peak current to
remain unaffected throughout all duty cycles.
The LTC7132 PWM will always use discontinuous mode
during the TON_RISE operation. In discontinuous mode,
the bottom gate is turned off as soon as reverse current
is detected in the inductor. This will allow the regulator to
start up into a pre-biased load.
VARIABLE DELAY TIME, SOFT-START AND OUTPUT
VOLTAGE RAMPING
There is no traditional tracking feature in the LTC7132.
However, two outputs can be given the same TON_RISE
and TON_DELAY times to effectively ramp up at the same
time. If the RUN pin is released at the same time and both
LTC7132s use the same time base, the outputs will track
very closely. If the circuit is in a PolyPhase configuration,
all timing parameters must be the same.
The LTC7132 must enter the run state prior to soft-start.
The RUNn pin is released after the part initializes and VIN is
greater than the VIN_ON threshold. If multiple LTC7132s
are used in an application, they should be configured to
share the same RUNn pins. They all hold their respective
RUNn pins low until all devices initialize and V exceeds
IN
the VIN_ON threshold for all devices. The SHARE_CLK
pin assures all the devices connected to the signal use
the same time base.
The method of start-up sequencing described above is
time based. For concatenated events it is possible to con-
trol the RUNn pins based on the PGOODn pin of a different
controller. There is 60µs filtering to the PGOODn inside
the device. If unwanted transitions still occur on PGOODn,
place a capacitor to ground on the PGOODn pin to filter
the waveform. The RC time-constant of the filter should
be set sufficiently fast to assure no appreciable delay is
incurred. A value of 300μs to 500μs will provide some
additional filtering without significantly delaying the trig-
ger event.
After the RUNn pin releases, the controller waits for the
user-specified turn-on delay (TON_DELAY) prior to ini-
tiating an output voltage ramp. Multiple LTC7132s and
other ADI parts can be configured to start with variable
delay times. To work correctly, all devices use the same
timing clock (SHARE_CLK) and all devices must share
the RUNn pin. This allows the relative delay of all parts
to be synchronized. The actual variation in the delay will
be dependent on the highest clock rate of the devices
connected to the SHARE_CLK pin (all Analog Devices ICs
are configured to allow the fastest SHARE_CLK signal to
control the timing of all devices). The SHARE_CLK signal
can be 10% in frequency, thus the actual time delays will
have proportional variance.
DIGITAL SERVO MODE
For maximum accuracy in the regulated output voltage,
enable the digital servo loop by asserting bit 6 of the
MFR_PWM_MODE command. In digital servo mode, the
LTC7132 will adjust the regulated output voltage based
on the ADC voltage reading. Every 90ms the digital servo
loop will step the LSB of the DAC (nominally 1.375mV or
0.688mV depending on the voltage range bit) until the out-
put is at the correct ADC reading. At power-up this mode
engages after TON_MAX_FAULT_LIMIT unless the limit is
set to 0 (infinite). If the TON_MAX_FAULT_LIMIT is set to
0 (infinite), the servo begins after TON_RISE is complete
and VOUT has exceeded the VOUT_UV_FAULT_LIMIT.
This same point in time is when the output changes from
discontinuous to the programmed mode as indicated in
MFR_PWM_MODE bit 0. Refer to Figure 30 for details on
Soft-start is performed by actively regulating the load
voltage while digitally ramping the target voltage from
0.0V to the commanded voltage set point. The rise time
of the voltage ramp can be programmed using the TON_
RISE command to minimize inrush currents associated
with the start-up voltage ramp. The soft-start feature
is disabled by setting TON_RISE to any value less than
0.250ms. The LTC7132 will perform the necessary math
internally to assure the voltage ramp is controlled to the
desired slope. However, the voltage slope cannot be any
faster than the fundamental limits of the power stage. The
shorter TON_RISE time is set, the larger the discrete steps
in the TON_RISE ramp will appear. The number of steps
in the ramp is equal to TON_RISE/0.1ms.
the V
waveform under time-based sequencing. If the
OUT
TON_MAX_FAULT_LIMIT is set to a value greater than 0
Rev 0
48
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LTC7132
APPLICATIONS INFORMATION
and the TON_MAX_FAULT_RESPONSE is set to ignore
0x00, the servo begins:
a controlled ramp. The output will decay as a function
of the load. The output voltage will operate as shown
in Figure 31 so long as the part is in forced continu-
ous mode and the TOFF_FALL time is sufficiently slow
that the power stage can achieve the desired slope. The
TOFF_FALL time can only be met if the power stage and
controller can sink sufficient current to assure the output
is at zero volts by the end of the fall time interval. If the
TOFF_FALL time is set shorter than the time required to
discharge the load capacitance, the output will not reach
the desired zero volt state. At the end of TOFF_FALL, the
controller will cease to sink current and VOUT will decay
at the natural rate determined by the load impedance. If
the controller is in discontinuous mode, the controller will
not pull negative current and the output will be pulled low
by the load, not the power stage. The maximum fall time
is limited to 1.3 seconds. The shorter TOFF_FALL time is
set, the larger the discrete steps in the TOFF_FALL ramp
will appear. The number of steps in the ramp is equal to
TOFF_FALL/0.1ms.
1. After the TON_RISE sequence is complete
2. After the TON_MAX_FAULT_LIMIT time is reached; and
3. After the VOUT_UV_FAULT_LIMIT has been exceed or
the IOUT_OC_FAULT_LIMIT is no longer active.
If the TON_MAX_FAULT_LIMIT is set to a value greater
than 0 and the TON_MAX_FAULT_RESPONSE is not set
to ignore 0X00, the servo begins:
1. After the TON_RISE sequence is complete;
2. After the TON_MAX_FAULT_LIMIT time has expired
and both VOUT_UV_FAULT and IOUT_OC_FAULT are
not present.
The maximum rise time is limited to 1.3 seconds.
In a PolyPhase configuration it is recommended only one
of the control loops have the digital servo mode enabled.
This will assure the various loops do not work against each
other due to slight differences in the reference circuits.
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ꢑ00ꢒꢓ00ꢔꢕ
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Figure 31. TOFF_DELAY and TOFF_FALL
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INTV /EXTV POWER
CC
CC
Figure 30 . Timing Controlled VOUT Rise
The internal MOSFET drivers and most other internal cir-
cuitry are derived from the INTV pin. When the EXTV
CC
CC
SOFT OFF (SEQUENCED OFF)
pin is shorted to GND or tied to a voltage less than 4.7V,
or SV is lower than 7V, an internal 5.5V linear regula-
In addition to a controlled start-up, the LTC7132 also sup-
ports controlled turn-off. The TOFF_DELAY and TOFF_
FALL functions are shown in Figure 31. TOFF_FALL is
processed when the RUN pin goes low or if the part is
commanded off. If the part faults off or FAULTn is pulled
low externally and the part is programmed to respond
to this, the output will three-state rather than exhibiting
IN
tor supplies INTV power from V . If EXTV is taken
CC
IN
CC
above 4.7V and SV is higher than 7V, the internal 5.5V
IN
regulator is turned off and an internal switch is turned on
connecting EXTVCC to INTVCC. EXTVCC reduces power dis-
sipation from the internal low dropout 5.5V regulator, thus
improves the overall efficiency and thermal performance.
Rev 0
49
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LTC7132
APPLICATIONS INFORMATION
EXTV can be applied before V . The regulator can sup-
TOPSIDE MOSFET DRIVER SUPPLY (C , D )
B B
IN
ply aCpCeak current of 100mA. Both INTV and EXTV
CC
CC
External bootstrap capacitors, CB, connected to the
need to be bypassed to ground with a minimum of 1μF
ceramic capacitor or low ESR electrolytic capacitor. No
matter what type of bulk capacitor is used, an additional
0.1μF ceramic capacitor placed directly adjacent to the
BOOSTn pin supplies the gate drive voltages for the inter-
nal topside MOSFETs. Capacitor C in the Block Diagram
B
is charged through external diode D from INTV when
B
CC
the SWn pin is low. When one of the topside MOSFETs is
INTV and PGND pins is highly recommended. Good
CC
to be turned on, the driver places the C voltage across
B
bypassing is needed to supply the high transient currents
required by the MOSFET gate drivers.
the gate source of the desired MOSFET. This enhances the
MOSFET and turns on the topside switch. The switch node
Do not tie INTV on the LTC7132 to an external supply
voltage, SWn, rises to V and the BOOSTn pin follows.
CC
IN
because INTV will attempt to pull the external supply
With the internal topside MOSFET on, the boost voltage is
CC
high and hit current limit, significantly increasing the die
above the input supply: V
= V + V
. The value
IN
INTVCC
temperature.
of the boost capacitor, C B,OnOeSeTds to be 100 times that of
B
the total input capacitance of the topside MOSFET(s). The
reverse breakdown of the external Schottky diode must
For applications where VIN is less than 6V, tie the SVIN and
INTV pins together to the supply voltage through a 1Ω
CC
be greater than V
.
IN(MAX)
or 2.2Ω resistor as shown in Figure 32. To minimize the
voltage drop caused by the gate charge current a low ESR
capacitor must be connected to the SVIN/INTVCC pins.
This configuration will override the INTVCC linear regulator
and will prevent INTVCC from dropping too low. The UVLO
PWM jitter has been observed in some designs operating
at higher V /V ratios. This jitter does not substantially
IN OUT
affect the circuit accuracy. Referring to Figure 33, PWM
jitter can be removed by inserting a series resistor with a
value of 1Ω to 5Ω between the cathode of the diode and
the BOOSTn pin. A resistor case size of 0603 or larger is
recommended to reduce ESL and achieve the best results.
on INTV is set to approximately 4V.
CC
V
IN
PV
SV
IN0/1
5V
+
IN
C
IN
UNDERVOLTAGE LOCKOUT
LTC7132
R
The LTC7132 is initialized by an internal threshold-based
UVLO where V must be approximately 4V and INTV ,
VIN
1Ω
INTV
CC
IN
CC
C
PGND
INTVCC
4.7µF
V
, and V
must be within approximately 20% of
DD33
DD25
7132 F33
their regulated values. In addition, V
must be within
DD33
approximately 7% of the targeted value before the RUN
pin is released. After the part has initialized, an additional
Figure 32. Setup for a 5V Input
comparator monitors V . The VIN_ON threshold must be
IN
exceeded before the power sequencing can begin. When
V
PV
IN
C
IN0/1
+
V drops below the VIN_OFF threshold, the SHARE_CLK
SV
IN
IN
1Ω TO 5Ω
IN
BOOST
pin will be pulled low and V must increase above the
IN
C
B
0.1µF
D
B
LTC7132
VIN_ON threshold before the controller will restart. The
SW
INTV
normal start-up sequence will be allowed after the VIN_
CC
C
4.7µF
INTVCC
ON threshold is crossed. If FAULTB is held low when V
IN
PGND
is applied, ALERT will be asserted low even if the part is
7132 F34
programmed to not assert ALERT when FAULTB is held
2
Figure 33. Boost Circuit to Minimize PWM Jitter
low. If I C communication occurs before the LTC7132 is
out of reset and only a portion of the command is seen by
Rev 0
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LTC7132
APPLICATIONS INFORMATION
the part, this can be interpreted as a CML fault. If a CML
fault is detected, ALERT is asserted low.
The benefit of using a LTC7132 in 2-phase operation
can be calculated by using the equation above for the
higher power monolithic and then calculating the loss
that would have resulted if both channels switched on at
the same time. The total RMS power loss is lower when
both channels are operating due to the reduced overlap
of current pulses required through the input capacitor’s
ESR. This is why the input capacitor’s requirement cal-
culated above for the worst-case controller is adequate
for the dual controller design. Also, the input protection
fuse resistance, battery resistance, and PC board trace
resistance losses are also reduced due to the reduced
peak currents in a 2-phase system. The overall benefit of
a multiphase design will only be fully realized when the
source impedance of the power supply/battery is included
in the efficiency testing.
It is possible to program the contents of the NVM in the
application if the VDD33 supply is externally driven directly
to V
or through EXTV . This will activate the digital
DD33
CC
portion of the LTC7132 without engaging the high volt-
age sections. PMBus communications are valid in this
supply configuration. If V has not been applied to the
IN
LTC7132, bit 3 (NVM Not Initialized) in MFR_COMMON
will be asserted low. If this condition is detected, the part
will only respond to addresses 5A and 5B. To initialize
the part issue the following set of commands: global
address 0x5B command 0xBD data 0x2B followed by
global address 5B command 0xBD and data 0xC4. The
part will now respond to the correct address. Configure
the part as desired then issue a STORE_USER_ALL. When
V is applied a MFR_RESET command must be issued to
A small (0.1μF to 1μF) bypass capacitor between the chip
SVIN pin and ground, placed close to the LTC7132, is also
IN
allow the PWM to be enabled and valid ADC conversions
to be read.
suggested. A 2.2Ω to 10Ω resistor placed between C
IN
(C1) and the V pin provides further isolation between
IN
the two LTC7132s.
C AND C
SELECTION
IN
OUT
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
In continuous mode, the source current of the internal top
MOSFET is a square wave of duty cycle (V )/(V ). To
prevent large voltage transients, a low ESR capacitor sized
for the maximum RMS current of one channel must be
used. The maximum RMS capacitor current is given by:
OUT
IN
output ripple (∆V ) is approximated by:
OUT
ꢀ
RIPPLE ꢂ
ꢁ
ꢃ
ꢅ
ꢄ
1
ΔVOUT ≈I
ESR+
IMAX
8•f•COUT
ꢀ
ꢂ1/2
CIN RequiredIRMS
≈
V V – V
OUT)(
IN
OUT
(
)
ꢃ
ꢁ
V
IN
where f is the operating frequency, C
is the output
OUT
This formula has a maximum at VIN = 2VOUT, where
= I /2. This simple worst-case condition is com-
capacitance and I
is the ripple current in the induc-
RIPPLE
I
tor. The output ripple is highest at maximum input voltage
since I increases with input voltage.
RMS
OUT
monly used for design because even significant deviations
do not offer much relief. Note that capacitor manufactur-
ers’ ripple current ratings are often based on only 2000
hours of life. This makes it advisable to further derate
the capacitor, or to choose a capacitor rated at a higher
temperature than required. Several capacitors may be par-
alleled to meet size or height requirements in the design.
Due to the high operating frequency of the LTC7132,
RIPPLE
FAULT INDICATION
The LTC7132 FAULT pins are configurable to indicate a
variety of faults including OV, UV, OC, OT, timing faults,
and peak over current faults. In addition, the FAULT pins
can be pulled low by external sources indicating a fault in
ceramic capacitors can also be used for C . Always con-
sult the manufacturer if there is any question.
IN
Rev 0
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LTC7132
APPLICATIONS INFORMATION
some other portion of the system. The fault response is
configurable and allows the following options:
All the above pins have on-chip pull-down transistors that
can sink 3mA at 0.4V. The low threshold on the pins is
0.8V; thus, there is plenty of margin on the digital signals
with 3mA of current. For 3.3V pins, 3mA of current is
a 1.1k resistor. Unless there are transient speed issues
associated with the RC time constant of the resistor pull-
up and parasitic capacitance to ground, a 10k resistor or
larger is generally recommended.
n
Ignore
n
n
Shut Down Immediately—Latch Off
Shut Down Immediately—Retry Indefinitely at the
Time Interval Specified in MFR_RETRY_DELAY
Refer to the PMBus section of the data sheet and the
PMBus specification for more details.
For high speed signals such as the SDA, SCL and SYNC,
a lower value resistor may be required. The RC time con-
stant should be set to 1/3 to 1/5 the required rise time
to avoid timing issues. For a 100pF load and a 400kHz
PMBus communication rate, the rise time must be less
than 300ns. The resistor pull-up on the SDA and SCL pins
with the time constant set to 1/3 the rise time is:
The OV response is automatic. If an OV condition is
detected, SWn goes low.
Fault logging is available on the LTC7132. The fault log-
ging is configurable to automatically store data when a
fault occurs that causes the unit to fault off. The header
portion of the fault logging table contains peak values. It
is possible to read these values at any time. This data will
be useful while troubleshooting the fault.
tRISE
3•100pF
RPULLUP
=
=1k
The closest 1% resistor value is 1k. Be careful to minimize
parasitic capacitance on the SDA and SCL pins to avoid
communication problems. To estimate the loading capaci-
tance, monitor the signal in question and measure how
long it takes for the desired signal to reach approximately
63% of the output value. This is a one time constant. The
SYNC pin has an on-chip pull-down transistor with the
output held low for nominally 500ns. If the internal oscil-
lator is set for 500kHz and the load is 100pF and a 3x time
constant is required, the resistor calculation is as follows:
If the LTC7132 internal temperature is in excess of 85°C,
writes into the NVM (other than fault logging) are not
recommended. The data will still be held in RAM, unless
the 3.3V supply UVLO threshold is reached. If the die
temperature exceeds 130°C all NVM communication is
disabled until the die temperature drops below 120°C.
OPEN-DRAIN PINS
The LTC7132 has the following open-drain pins:
3.3V Pins
2µs–500ns
3•100pF
RPULLUP
=
=5k
1. FAULT
2. SYNC
The closest 1% resistor is 4.99k.
3. SHARE_CLK
4. PGOODn
If timing errors are occurring or if the SYNC frequency is
not as fast as desired, monitor the waveform and deter-
mine if the RC time constant is too long for the applica-
tion. If possible reduce the parasitic capacitance. If not
reduce the pull-up resistor sufficiently to assure proper
timing. The SHARE_CLK pull-up resistor has a similar
equation with a period of 10µs and a pull-down time of
1μs. The RC time constant should be approximately 3μs
or faster.
5V Pins (5V pins operate correctly when pulled to
3.3V.)
1. RUNn
2. ALERT
3. SCL
4. SDA
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LTC7132
APPLICATIONS INFORMATION
PHASE-LOCKED LOOP AND FREQUENCY
SYNCHRONIZATION
control signals and minimize crosstalk to the SYNC signal
to avoid this problem. Multiple LTC7132s are required
to share one SYNC pin in PolyPhase configurations.
For other configurations, connecting the SYNC pins to
form a single SYNC signal is optional. If the SYNC pin
is shared between LTC7132s, only one LTC7132 can
be programmed with a frequency output. All the other
LTC7132s should be programmed to disable the SYNC
output. However their frequency should be programmed
to the nominal desired value.
The LTC7132 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. The PLL is locked to the falling edge of
the SYNC pin. The phase relationship between the PWM
controller and the falling edge of SYNC is controlled by
the lower 3 bits of the MFR_PWM_ CONFIG command.
For PolyPhase applications, it is recommended that all
the phases be spaced evenly. Thus for a 2-phase system
the signals should be 180° out of phase and a 4-phase
system should be spaced 90°.
MINIMUM ON-TIME CONSIDERATIONS
Minimum on-time, t
, is the smallest time duration
The phase detector is an edge-sensitive digital type that
provides a known phase shift between the external and
internal oscillators. This type of phase detector does not
exhibit false lock to harmonics of the external clock.
ON(MIN)
that the LTC7132 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum limit and
care should be taken to ensure that:
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the internal
filter network. The PLL lock range is guaranteed between
200kHz and 1MHz. Nominal parts will have a range beyond
this; however, operation to a wider frequency range is not
guaranteed.
VOUT
tON(MIN)
<
V •f
IN
OSC
If the duty cycle falls below what can be accommodated
by the minimum on-time, the part will begin to skip cycles.
The output voltage will continue to be regulated, but the
ripple voltage and current will increase.
The PLL has a lock detection circuit. If the PLL should
lose lock during operation, bit 4 of the STATUS_MFR_
SPECIFIC command is asserted and the ALERT pin is
pulled low. The fault can be cleared by writing a 1 to the
bit. If the user does not wish to see the ALERT pin assert
if a PLL_FAULT occurs, the SMBALERT_MASK command
can be used to prevent the alert.
The minimum on-time for the LTC7132 is approximately
90ns. Reasonably good PCB layout, minimum 30% induc-
tor current ripple and at least 2mV for LOW DCR structure
or 10mV to 15mV for regular DCR ripple on the current
sense signal are required to avoid increasing the mini-
mum on-time. The minimum on-time can be affected by
PCB switching noise in the voltage and current loop. As
the peak current sense voltage decreases, the minimum
on-time gradually increases to 130ns. This is of particu-
lar concern in forced continuous applications with low
ripple current at light loads. If the duty cycle drops below
the minimum on-time limit in this situation, a significant
amount of cycle skipping can occur with correspondingly
larger current and voltage ripple.
If the SYNC signal is not clocking in the application, the
nominal programmed frequency will control the PWM
circuitry. However, if multiple parts share the SYNC pins
and the signal is not clocking, the parts will not be syn-
chronized and excess voltage ripple on the output may be
present. Bit 10 of MFR_PADS will be asserted low if this
condition exists.
If the PWM signal appears to be running at too high a
frequency, monitor the SYNC pin. Extra transitions on
the falling edge will result in the PLL trying to lock on to
noise versus the intended signal. Review routing of digital
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LTC7132
APPLICATIONS INFORMATION
EXTERNAL TEMPERATURE SENSE
dual diode network as shown in Figure 35. This second
measurement method is not generally as accurate as the
first, but it supports legacy power blocks or may prove
necessary if high noise environments prevent use of the
The LTC7132 is capable of measuring the power stage
temperature of each channel. Multiple methods using
silicon junction type remote sensors are supported. The
voltage produced by the remote sense circuit is digitized
by the internal ADC, and the computed temperature value
is returned by the paged READ_TEMPERATURE_1 telem-
etry command.
∆V approach with its lower signal levels.
BE
For either method, the slope of the external tempera-
ture sensor can be modified with the coefficient stored
in MFR_TEMP_1_GAIN. With the ∆VBE approach, typi-
cal PNPs require temperature slope adjustments slightly
less than 1. The MMBT3906 has a recommended value
in this command of approximately MFR_TEMP_1_GAIN
= 0.991 based on the ideality factor of 1.01. Simply invert
the ideality factor to calculate the MFR_TEMP_1_GAIN.
Different manufacturers and different lots may have dif-
ferent ideality factors. Consult with the manufacturer to
set this value. Bench characterization over temperature is
recommended when adjusting MFR_TEMP_1_GAIN for
the direct p-n junction measurement method.
The most accurate external temperature measurement
can be made using a diode-connected PNP transistor
such as the MMBT3906 as shown in Figure 34 with bit 5
of MFR_PWM_MODE should be set to 0 (∆V method)
BE
when using this sensor configuration. The transistor
should be placed in contact with or immediately adja-
cent to the power stage inductor. Its emitter should be
connected to the TSNSn pin while the base and collec-
tor terminals of the PNP transistor should be returned to
the LTC7132 GND paddle using a Kevin connection. For
best noise immunity, the connections should be routed
differentially and a 10nF capacitor should be placed in
parallel with the diode-connected PNP. Parasitic PCB trace
inductance between the capacitor and transistor should
be minimized. Avoid placing PCB vias between the tran-
sistor and capacitor.
The offset of the external temperature sense can be
adjusted by MFR_TEMP_1_OFFSET.
If an external temperature sense element is not used, the
TSNSn pin must be shorted to GND. The UT_FAULT_LIMIT
must be set to –275°C, and the UT_FAULT_RESPONSE
must be set to ignore. The user also needs to set the
IOUT_CAL_GAIN_TC to a value of 0.
ꢀꢁꢂꢁ
ꢈꢀꢉꢊꢋꢅꢌ
ꢋ0ꢍꢎ
To ensure proper use of these temperature adjustment
parameters, refer to the specific formulas given for the
two methods by the MFR_PWM_MODE command in the
later section covering PMBus command details.
ꢏꢂꢐ
ꢃꢃꢄꢀꢅꢆ0ꢇ
ꢏꢂꢐ
ꢊꢋꢅꢌ ꢎꢅꢑ
Figure 34. External ∆VBE Temperature Sense
INPUT CURRENT SENSE AMPLIFIER
ꢋꢌꢍꢎꢏ
ꢀꢁꢂꢁ
The LTC7132 input current sense amplifier can sense the
supply current into the VIN pin using an external resistor as
well as the power stage current using an external current
sense resistor shown in Figure 36. Unless care is taken to
mitigate the frequency noise caused by the discontinuous
input current, significant input current measurement error
may occur. The noise will be the greatest in high current
applications and at large step-down ratios. Careful layout
ꢃꢀꢄꢅꢆꢇꢈ
ꢆꢉꢊ
ꢆꢐꢇꢍꢑ ꢏꢀ ꢈꢍꢒꢄ
ꢓꢂꢔ
ꢓꢂꢔ
ꢅꢆꢇꢈ ꢊꢇꢕ
Figure 35. 2D+R Temperature Sense
The LTC7132 also supports direct junction voltage mea-
surements when bit 5 of MFR_PWM_MODE_LTC7132 is
set to 1. The factory defaults support a resistor trimmed
and filtering at the SV pin is recommended to minimize
IN
measurement error. The SV pin should be filtered with
IN
a resistor and a ceramic capacitor. The filter should be
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LTC7132
APPLICATIONS INFORMATION
located as close to the SV pin as possible. The supply
RCONFIG pins are only interrogated at initial power up
and during a reset, so modifying their values on the fly
while the part is powered will have no effect. However,
this does mean that RCONFIG pins on the same IC can
be shared with a single resistor divider if they require
identical programming. Resistors with a tolerance of 1%
or better must be used to assure proper operation. In the
IN
side of the SVIN pin filter should be Kelvin connected to the
supply side of the R
resistor. A 2Ω resistor should
IINSNS
be sufficient for most applications. The resistor will cause
an IR voltage drop from the supply to the SV pin due to
the current flowing into the SV pin. To compensate for
IN
IN
this voltage drop, the MFR_RVIN command value should
be set to the nominal resistor value. The LTC7132 will
multiply the MFR_READ_ICHIP measurement value by the
user defined MFR_RVIN value and add this voltage to the
following tables, R
is connected between V
and
TOP
DD25
the RCONFIG pin while R
pin and GND. Noisy clock signals should not be routed
is connected between the
BOT
measured voltage at the SV pin. Therefore
near these pins.
IN
READ_VIN=VSVIN_PIN+(MFR_READ_ICHIP•MFR_RVIN)
Voltage Selection
Therefore the READ_VIN command will return the value
When an output voltage is set using the VOUT_CFGn pins
(by Table 3) the following parameters are set as a percent-
age of the output voltage:
of the voltage at the supply side of the SV pin filter. If no
IN
SV filter element is used, set MFR_RVIN = 0.
IN
The capacitor C1 should be a low ESR ceramic capacitor.
n
VOUT_OV_FAULT_LIMIT.................................... +10%
It should be placed as close as possible to PV
to sup-
IN0/1
n
VOUT_OV_WARN_LIMIT................................... +7.5%
ply high frequency transient input current. This will help
prevent noise from the top gate MOSFET from feeding
into the input current sense amplifier inputs and supply.
n
VOUT_MAX....................................................... +7.5%
n
VOUT_MARGIN_HIGH..........................................+5%
n
VOUT_MARGIN_LOW...........................................–5%
n
If the input current sense amplifier is not used, short the
VOUT_UV_WARN_LIMIT.................................. –6.5%
+
–
n
SV , I , and I pins together.
VOUT_UV_FAULT_LIMIT...................................... –7%
IN IN
IN
R
Table 3. VOUT_CFGn Resistor Programming
INSNS
V
IN
C1
R
(kΩ)
R
(kΩ)
V (V)
ON/OFF
NVM
ON
TOP
BOTTOM
OUT
10µF
PV
0 or Open
10
Open
23.2
15.8
20.5
17.4
17.8
15
NVM
5.000
3.300
2.500
1.800
1.500
1.350
1.250
1.200
1.150
1.100
1.050
0.900
0.750
0.650
0.600
NVM
IN0/1
I
I
–
+
IN
IN
2Ω
LTC7132
10
ON
SV
IN
16.2
16.2
20
ON
1µF
7132 F37
ON
ON
Figure 36. Low Noise Input Current Sense Circuit
20
ON
20
12.7
11
ON
20
ON
EXTERNAL RESISTOR CONFIGURATION PINS
(RCONFIG)
24.9
24.9
24.9
24.9
24.9
30.1
30.1
Open
11.3
9.09
7.32
5.76
4.32
3.57
1.96
0
ON
ON
The LTC7132 is factory programmed to use the external
resistor configuration. This allows output voltage, PWM
frequency, PWM phasing, and the PMBus address to be
set by the user without programming the part through
the PMBus interface or purchasing custom programmed
parts. To use resistor programming, the RCONFIG pins
ON
ON
ON
ON
ON
OFF
require a resistor divider between V
and GND. The
DD25
Rev 0
55
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LTC7132
APPLICATIONS INFORMATION
Frequency Selection
Phase Selection
The PWM switching frequency is set according to Table 4.
The SYNC pins must be shared in PolyPhase configura-
tions where multiple LTC7132s are used to produce the
output. If the configuration is not PolyPhase, the SYNC
pins do not have to be shared. If the SYNC pins are shared
between LTC7132s only one SYNC pin should be enabled;
all other SYNC pins should be disabled. A pull-up resistor
The phase of the channels with respect to the falling edge
of SYNC is set using the values in Table 5.
Table 5. PHASE_CFG Resistor Programming
R
TOP
R
SYNC TO CH0 SYNC TO CH1
SYNC
BOTTOM
(kΩ)
0 or Open
10
(kΩ)
(DEGREES)
(DEGREES)
NVM
NVM
NVM
300
OUTPUT
Open
23.2
15.8
20.5
17.4
17.8
15
NVM
NVM
NVM
120
60
NVM
NVM
NVM
to V
is required on the SYNC pin.
DD33
Table 4. FREQ_CFG Resistor Programming
(kΩ) (kΩ)
10
16.2
16.2
20
R
TOP
R
FREQUENCY (kHz)
BOTTOM
240
0 or Open
10
Open
23.2
15.8
20.5
17.4
17.8
15
NVM
NVM
NVM
NVM
NVM
NVM
NVM
NVM
1000
750
120
0
240
20
120
DISABLED
10
20
12.7
11
0
240
16.2
16.2
20
20
90
270
24.9
24.9
24.9
24.9
24.9
30.1
30.1
Open
11.3
9.09
7.32
5.76
4.32
3.57
1.96
0
0
180
120
60
300
20
240
20
12.7
11
120
0
240
20
120
ENABLED
24.9
24.9
24.9
24.9
24.9
30.1
30.1
Open
11.3
9.09
7.32
5.76
4.32
3.57
1.96
0
0
240
650
90
270
575
0
180
500
For example in a 4-phase configuration clocked at 500kHz,
all of the LTC7132s must be set to the desired frequency
and phase and only one LTC7132 should be set to the
desired frequency with the SYNC pin enabled. All phasing
is with respect to the falling edge of SYNC.
425
350
250
External Clock
For LTC7132 Chip 1, set the frequency to 500kHz with 90°
and 270° phase shift with the SYNC pin enabled:
Frequency: R
= 24.9kΩ and R
= 5.76kΩ
TOP
BOT
Phase: R
= 30.1kΩ and R
= 1.96kΩ
TOP
BOT
For LTC7132 Chip 2, set the frequency to 500kHz with
0°and 180° phase shift and the SYNC pin disabled:
Frequency: 24.9kΩ and R
= 5.76kΩ
BOT
Phase: R
= 24.9kΩ and R
= 11.3kΩ
TOP
BOT
Rev 0
56
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LTC7132
APPLICATIONS INFORMATION
Address Selection Using RCONFIG
Table 6b1. LTC7132 MFR_ADDRESS Command Examples
Expressing Both 7- or 8-Bit Addressing
HEX DEVICE
The LTC7132 address is selected based on the program-
ming of the two configuration pins ASEL0 and ASEL1
according to Table 6. ASEL0 programs the bottom four
bits of the device address for the LTC7132, and ASEL1
programs the three most significant bits. Either portion of
the address can also be retrieved from the MFR_ADDRESS
value in EEPROM. If both pins are left open, the full 7-bit
MFR_ADDRESS value stored in EEPROM is used to deter-
mine the device address. The LTC7132 always responds
to 7-bit global addresses 0x5A and 0x5B. MFR_ADDRESS
should not be set to either of these values because these
are global addresses and all parts will respond to them.
ADDRESS
BIT BIT BIT BIT BIT BIT BIT BIT
DESCRIPTION 7 BIT 8 BIT
7
0
0
0
0
0
1
6
1
1
1
1
1
0
5
0
0
0
1
1
0
4
1
1
0
0
0
0
3
1
1
1
0
0
0
2
0
0
1
0
0
0
1
1
1
1
0
0
0
0
R/W
0
4
Rail
0x5A 0xB4
0x5B 0xB6
0x4F 0x9E
0x60 0xC0
0x61 0xC2
0
1
1
0
1
0
4
Global
0
Default
0
Example 1
Example 2
0
0
2,3,5
Disabled
0
Note 1: This table can be applied to the MFR_RAIL_ADDRESS command
as well as the MFR_ADDRESS command.
Note 2: A disabled value in one command does not disable the device, nor
does it disable the Global address.
Note 3: A disabled value in one command does not inhibit the device from
responding to device addresses specified in other commands.
Table 6. ASELn Resistor Programming
ASEL1
ASEL0
LTC7132 DEVICE
ADDRESS BITS[3:0]
Note 4: It is not recommended to write the value 0x00, 0x0C (7 bit), or
0x5A or 0x5B(7 bit) to the MFR_ADDRESS, or the MFR_RAIL_ADDRESS
commands.
LTC7132 DEVICE
ADDRESS
BITS[6:4]
Note 5: To disable the address enter 0x80 in the MFR_ADDRESS
command. The 0x80 is greater than the 7-bit address field, disabling the
address.
R
TOP
(kΩ)
R
(kΩ) BINARY
HEX
BINARY
HEX
BOTTOM
0 or Open
10
Open
EEPROM
23.2
15.8
20.5
17.4
17.8
15
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
10
EFFICIENCY CONSIDERATIONS
16.2
16.2
20
EEPROM
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as: %Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
20
20
20
12.7
11
24.9
24.9
24.9
24.9
24.9
30.1
30.1
Open
11.3
9.09
7.32
5.76
4.32
3.57
1.96
0
111
110
101
100
011
010
001
000
7
6
5
4
3
2
1
0
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC7132 circuits: 1) IC V current, 2) INTV
regulator current, 3) I R losses, 4) Topside MOSFET tran-
sition losses.
IN
CC
2
1. The VIN current is the DC supply current given in
the Electrical Characteristics table, which excludes
internal MOSFET driver and control currents. VIN
current typically results in a small (<0.1%) loss.
Rev 0
57
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LTC7132
APPLICATIONS INFORMATION
2. INTVCC current is the sum of the internal
MOSFET driver and control currents. The
internal MOSFET driver current results from
switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched
from low to high to low again, a packet of charge dQ
calculation. For applications where the LTC7132 is oper-
ated at high ambient temperature, high V , high switch-
IN
ing frequency and maximum load current, the hot spot
may migrate to the power MOSFETs which are located
farther away from the internal on-chip diode. Therefore,
the maximum output load current rating shall be derated
to prevent the internal MOSFETs from overheating.
moves from INTV to ground. The resulting dQ/dt is
CC
a current out of INTV that is typically much larger
CC
The junction to ambient thermal resistance of the part
will vary depending on the copper area and thickness
of the PCB board where the part is mounted, the heat
sink mounted on top of the part, as well as the amount
of forced air flow used to cool down the device. Figures
38–41 below show the output current derating with both
heat sink and airflow on the existing standard demo board.
than the control circuit current.
2
3. I R losses are predicted from the DC resistances of
the fuse (if used), internal MOSFETs, inductor, and
current sense resistor. In continuous mode, the
average output current flows through the inductor
and R
, but is “chopped” between the topside
SENSE
MOSFET and the synchronous (bottom) MOSFET.
ꢀꢁ
ꢀꢁ ꢂꢃꢄꢅ ꢆꢇꢀꢈ
4. Transition losses apply only to the topside internal
MOSFET(s), and become significant only when
operating at high input voltages (typically 15V or
greater). Transition losses can be estimated from:
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁ
ꢀ
ꢀ ꢁꢂ
ꢀ
ꢀ ꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢃꢃꢄ ꢀꢅꢆꢇ ꢈꢇꢄRꢀ
2
Transition Loss = (1.7) • V • I
• C
• f
IN
O(MAX)
RSS
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses during
the design phase. The internal battery and fuse resistance
ꢀꢁ ꢂꢃRꢄꢅꢁꢆ
ꢇ00ꢅꢄꢈ
ꢉ00ꢅꢄꢈ
0
0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ00
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃ ꢄꢂꢅ
losses can be minimized by making sure that C has ade-
IN
Figure 37. Temperature Derating Curve Based
on the DC2666A Demo Board
quate charge storage and very low ESR at the switching
frequency. A 25W supply will typically require a minimum
of 20μF to 40μF of capacitance having a maximum of
20mΩ to 50mΩ of ESR. The LTC7132 two-phase archi-
tecture typically halves this input capacitance require-
ment over competing solutions. Other losses including
Schottky conduction losses during dead time and induc-
tor core losses generally account for less than 2% total
additional loss.
ꢀꢁ
ꢀꢁꢂꢃ ꢃꢄꢅꢂ ꢆꢁꢇꢈ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁ
ꢀ
ꢀ ꢁꢂ
ꢀ
ꢀ ꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢃꢃꢄ ꢀꢅꢆꢇ ꢈꢇꢄRꢀ
ꢀꢁ ꢂꢃRꢄꢅꢁꢆ
ꢇ00ꢅꢄꢈ
THERMAL CONSIDERATIONS
ꢉ00ꢅꢄꢈ
0
0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ00
ꢀꢁꢂ
In LTC7132, the READ_TEMPERATURE_2 command
returns the internal die junction temperature of the part
using an on-chip diode with a delta VBE measurement and
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃ ꢄꢂꢅ
Figure 38. Temperature Derating Curve Based
on the DC2666A Demo Board
Rev 0
58
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LTC7132
APPLICATIONS INFORMATION
ꢀꢁ
ꢀꢁ ꢂꢃꢄꢅ ꢆꢇꢀꢈ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢂ
Rꢃꢄ
ꢁ
ꢐ
ꢑ
ꢀ
ꢀ ꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢃꢃꢄ ꢀꢅꢆꢇ ꢈꢇꢄRꢀ
ꢄꢅ
ꢀ
R
ꢏ
ꢌꢍ
ꢏ
ꢌꢍR
ꢌꢍ
ꢆꢇꢈꢉ ꢄꢊꢉ
ꢋ
ꢌꢍ
ꢋ
ꢌꢍꢎ
ꢀꢁ ꢂꢃRꢄꢅꢁꢆ
ꢇ00ꢅꢄꢈ
ꢉ00ꢅꢄꢈ
Figure 41. Programmable Loop Compensation
0
0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ00
ꢀꢁꢂ
ꢒꢋꢓꢃ ꢀꢀ ꢂꢔꢕꢓꢃꢁꢅꢄꢒꢀꢔꢁ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃ ꢄꢅ0
ꢑꢄꢀꢁ
Figure 39. Temperature Derating Curve Based
on the DC2666A Demo Board
ꢀꢁ
ꢀꢁꢂꢃ ꢃꢄꢅꢂ ꢆꢁꢇꢈ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁ
ꢀ ꢁꢂꢃꢄ
ꢀ ꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂRꢃꢄꢅꢃ ꢆ
ꢇ
ꢀꢁꢂꢃꢃꢃꢄ ꢀꢅꢆꢇ ꢈꢇꢄRꢀ
ꢈRꢃꢉꢊꢃꢁꢂꢋ
ꢌꢍꢎꢏ ꢈꢐꢎ
Figure 42. Error Amp gm Adjust
ꢆꢋꢒꢃ ꢀꢀ ꢂꢓꢔꢒꢃꢁꢅꢄꢆꢀꢓꢁ
ꢀꢁ ꢂꢃRꢄꢅꢁꢆ
ꢇ00ꢅꢄꢈ
ꢉ00ꢅꢄꢈ
ꢑꢄꢀꢁ
0
0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ00
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃ ꢄꢅꢁ
Figure 40 . Temperature Derating Curve Based
on the DC2666A Demo Board
ꢀꢁꢂRꢃꢄꢅꢃ R
ꢆꢇ
PROGRAMMABLE LOOP COMPENSATION
ꢈRꢃꢉꢊꢃꢁꢂꢋ
ꢌꢍꢎꢏ ꢈꢐꢐ
The LTC7132 offers programmable loop compensation
to optimize the transient response without any hardware
change. The error amplifier gain gm varies from 0.8mmho
Figure 43. RTH Adjust
Adjusting the R will change the pole and zero location,
TH
to 4.6mmho, and the compensation resistor R varies
TH
as shown in Figure 43. It is recommended that the user
determines the appropriate value for the gm and RTH using
the LTPowerCAD tool.
from 0kΩ to 62kΩ inside the controller. Two compensation
capacitors, C and C , are required in the design and
TH
THP
the typical ratio between C and C
is 10 in Figure 41.
TH
THP
By adjusting the g and R only, the LTC7132 can pro-
CHECKING TRANSIENT RESPONSE
m
TH
vide a flexible type II compensation network to optimize
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
amount equal to ∆ILOAD • (ESR), where ESR is the effective
the loop over a wide range of output capacitors. Adjusting
the g will change the gain of the compensation over the
m
whole frequency range without moving the pole and zero
shifts by an
OUT
location, as shown in Figure 42.
Rev 0
59
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LTC7132
APPLICATIONS INFORMATION
series resistance of COUT. ∆ILOAD also begins to charge or
the programmed output voltage. The initial output volt-
age step resulting from the step change in output current
may not be within the bandwidth of the feedback loop, so
this signal cannot be used to determine phase margin.
discharge C
generating the feedback error signal that
OUT
forces the regulator to adapt to the current change and
return V to its steady-state value. During this recov-
OUT
ery time V
can be monitored for excessive overshoot
This is why it is better to look at the I pin signal which
OUT
TH
or ringing, which would indicate a stability problem. The
is in the feedback loop and is the filtered and compen-
sated control loop response. The gain of the loop will be
increased by increasing RTH and the bandwidth of the loop
availability of the I pin not only allows optimization of
TH
control loop behavior but also provides a DC-coupled and
AC-filtered closed-loop response test point. The DC step,
rise time and settling at this test point truly reflects the
closed-loop response. Assuming a predominantly second
order system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining
will be increased by decreasing C . If R is increased
TH
TH
by the same factor that CTH is decreased, the zero fre-
quency will be kept the same, thereby keeping the phase
shift the same in the most critical frequency range of the
feedback loop. The gain of the loop will be proportional
to the transconductance of the error amplifier which is
set using bits[7:5] of the MFR_PWM_COMP command.
The output voltage settling behavior is related to the sta-
bility of the closed-loop system and will demonstrate the
actual overall supply performance. A second, more severe
transient is caused by switching in loads with large (>1μF)
supply bypass capacitors. The discharged bypass capaci-
the rise time at the pin. The I
external capacitor shown
THR
in the Typical Application circuit will provide an adequate
starting point for most applications. The programmable
parameters that affect loop gain are the voltage range,
bit[1] of the MFR_PWM_MODE command, the current
range, bit[2] and bit[7] of the MFR_PWM_MODE com-
mand, the g of the PWM channel amplifier bits [7:5] of
tors are effectively put in parallel with C , causing a
m
OUT
MFR_PWM_COMP, and the internal R compensation
rapid drop in V . No regulator can alter its delivery of
TH
OUT
resistor, bits[4:0] of MFR_PWM_COMP. Be sure to estab-
lish these settings prior to compensation calculation.
current quickly enough to prevent this sudden step change
in output voltage if the load switch resistance is low and
it is driven quickly. If the ratio of C
to C
is greater
LOAD
OUT
The ITH series internal RTH external CTH filter sets the
than 1:50, the switch rise time should be controlled so
that the load rise time is limited to approximately 25 •
dominant pole-zero loop compensation. The internal R
TH
value can be modified (from 0Ω to 62kΩ) using bits[4:0]
of the MFR_PWM_ COMP command. Adjust the value
C
. Thus a 10μF capacitor would require a 250μs rise
LOAD
time, limiting the charging current to about 200mA.
of R to optimize transient response once the final PCB
TH
layout is done and the particular C filter capacitor and
TH
PolyPhase Configuration
output capacitor type and value have been determined.
The output capacitors need to be selected because the
various types and values determine the loop gain and
phase. An output current pulse of 20% to 80% of full-
load current having a rise time of 1μs to 10μs will pro-
When configuring a PolyPhase rail with multiple LTC7132s,
the user must share the SYNC, I , SHARE_CLK, FAULT,
and ALERT pins of these parts.THBe sure to use pull-up
resistors on FAULT, SHARE_CLK and ALERT. One of the
part’s SYNC pins must be set to the desired switching fre-
quency, and all other FREQUENCY_SWITCH commands
must be set to External Clock. If an external oscillator
is provided, set the FREQUENCY_SWITCH command to
External Clock for all parts. The relative phasing of all
the channels should be spaced equally. The MFR_RAIL_
ADDRESS of all the devices should be set to the
same value.
duce output voltage and I pin waveforms that will give
TH
a sense of the overall loop stability without breaking the
feedback loop. Placing a power MOSFET in series with a
current sense resistor to ground directly across the output
capacitor and driving the gate with an appropriate signal
generator is a practical way to produce to a load step. The
MOSFET + R
will produce output currents approxi-
OUT SERIES SERIES
SERIES
mately equal to V /R
. R
values from 0.1Ω
to 2Ω are valid depending on the current limit settings and
Rev 0
60
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LTC7132
APPLICATIONS INFORMATION
When connecting a PolyPhase rail with LTC7132s, con-
on the “output side” of the LTC7132 and occupy
minimum PC trace area. If DCR sensing is used,
place the top resistor (Figure 25a, R1) close to the
switching node.
nect the VIN pins of the LTC7132s directly back to the
supply voltage through the V pin filter networks.
IN
PC BOARD LAYOUT CHECKLIST
PC BOARD LAYOUT DEBUGGING
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 44. Figure 45 illustrates the cur-
rent waveforms present in the various branches of a syn-
chronous regulator operating in continuous mode. Check
the following in your layout:
It is helpful to use a DC-50MHz current probe to moni-
tor the current in the inductor while testing the circuit.
Monitor the output switching node (SWn pin) to syn-
chronize the oscilloscope to the internal oscillator and
probe the actual output voltage as well. Check for proper
performance over the operating voltage and current range
expected in the application. The frequency of operation
should be maintained over the input voltage range down
to dropout and until the output load drops below the low
current operation threshold.
1. Are signal ground and power ground kept separate?
The ground return of CINTVCC must return to the
combined C
(–) terminals.
OUT
2. The I trace should be as short as possible.
TH
The duty cycle percentage should be maintained from
cycle to cycle in a well-designed, low noise PCB imple-
mentation. Variation in the duty cycle at a subharmonic
rate can suggest noise pickup at the current or volt-
age sensing inputs or inadequate loop compensation.
Overcompensation of the loop can be used to tame a
poor PC layout if regulator bandwidth optimization is not
required.
3. The loop formed by the top N-channel MOSFET,
Schottky diode and the CIN capacitor should have
short leads and PC trace lengths.
4. The output capacitor (–) terminals should be
connected as close as possible to the (–) terminals
of the input capacitor by placing the capacitors next to
each other and away from the Schottky loop described
in item 4.
Reduce VIN from its nominal level to verify operation
of the regulator in dropout. Check the operation of the
undervoltage lockout circuit by further lowering VIN while
monitoring the outputs to verify operation.
+
–
5. Are the ISENSE and ISENSE leads routed together
with minimum PC trace spacing? The filter capacitor
+
–
between I
and I
should be as close as
SENSE
SENSE
possible to the IC. Ensure accurate current sensing
with Kelvin connections at the sense resistor or
inductor, whichever is used for current sensing.
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOSTn and
SWn connections and the sensitive voltage and current
pins. The capacitor placed across the current sensing pins
needs to be placed immediately adjacent to the pins of
the IC. This capacitor helps to minimize the effects of dif-
ferential noise injection due to high frequency capacitive
coupling. If problems are encountered with high current
output loading at lower input voltages, look for induc-
6. Is the INTV decoupling capacitor connected close
CC
to the IC, between the INTV and the power ground
pins? This capacitor carrCieCs the MOSFET driver
current peaks. An additional 1µF ceramic capacitor
placed immediately next to the INTV and GND pins
CC
can help improve noise performance substantially.
7. Keep the switching nodes (SWn) and boost nodes
(BOOSTn) away from sensitive small-signal nodes,
especially from the voltage and current sensing
feedback pins. All of these nodes have very large and
fast moving signals and therefore should be kept
tive coupling between C , Schottky components to the
IN
sensitive current and voltage sensing traces. In addition,
investigate common ground path voltage pickup between
these components and the GND pin of the IC.
Rev 0
61
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LTC7132
APPLICATIONS INFORMATION
R
ꢎꢎꢉꢌꢉꢌ
ꢍ
ꢎꢉ
ꢇꢍ
ꢎꢉ
ꢏ
ꢑ
ꢎ
ꢎ
ꢁꢌꢉꢌ
ꢎꢉ
ꢎꢉ
ꢙꢄ
ꢀꢁꢂꢃꢄꢅꢆ
ꢑ
ꢎ
ꢎ
ꢌꢐꢉꢌꢐ
ꢀ
R
ꢂꢄ
ꢌꢐꢉꢌꢐ
R
ꢍꢎꢉ
ꢏ
ꢍ
ꢘꢔꢁ
ꢌꢖ
ꢌꢐꢉꢌꢐ
ꢌꢍ
ꢂ
ꢎꢉ
ꢗ
ꢂ
ꢌꢕꢉꢂ
ꢗꢘꢘꢌꢁ
ꢍꢎꢉ
Rꢔꢉ
ꢑ
ꢍ
ꢍ
ꢌꢐꢉꢌꢐ
ꢌꢐꢉꢌꢐ
ꢏ
ꢎ
ꢁꢓR
ꢎ
ꢎꢉꢁꢍ
ꢂꢂ
ꢁꢓ
ꢑ
ꢍ
ꢍ
ꢊꢊꢅꢅ
ꢊꢊꢆꢒ
ꢂ
ꢎꢉꢁꢍꢂꢂ
ꢇꢈꢉꢊꢋꢌꢈꢉꢊ
ꢃꢄꢅꢆ ꢚꢛꢒ
Figure 44. Recommended Printed Circuit Layout Diagram, Single Phase Shown
ꢃꢄꢁ
ꢀꢁ
R
ꢃꢅꢆꢃꢅꢁ
ꢇ
ꢈꢉꢊꢁ
ꢂꢁ
ꢋ
ꢈꢉꢊꢁ
R
ꢀꢁ
ꢇ
ꢌꢆ
R
ꢌꢆ
ꢋ
ꢌꢆ
ꢃꢄ0
ꢀ0
R
ꢃꢅꢆꢃꢅ0
ꢇ
ꢈꢉꢊ0
ꢂ0
ꢋ
ꢈꢉꢊ0
R
ꢀ0
ꢍꢈꢀꢂ ꢀꢌꢆꢅꢃ ꢌꢆꢂꢌꢋꢎꢊꢅ
ꢏꢌꢐꢏ ꢃꢄꢌꢊꢋꢏꢌꢆꢐ
ꢋꢉRRꢅꢆꢊꢑ ꢒꢅꢅꢓ ꢀꢌꢆꢅꢃ
ꢊꢈ ꢎ ꢔꢌꢆꢌꢔꢉꢔ ꢀꢅꢆꢐꢊꢏꢑ
ꢕꢁꢖꢗ ꢘꢙꢚ
Figure 45. Branch Current Waveforms
Rev 0
62
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LTC7132
APPLICATIONS INFORMATION
DESIGN EXAMPLE
peak to peak inductor current ripple will be 7.72A (38.6%)
for channel 0 and 7.2A (35.9%) for channel 1.
As a design example for a 2-channel medium current regu-
lator, assume V = 12V nominal, V = 20V maximum,
ꢀ
ꢃ
ꢅ
ꢄ
IN
OUT1
IN
V
f•L
VOUT
IN(NOM) ꢅ
OUT ꢂ
ΔIL(NOM)
= 1–
V
OUT0
=1.5V, V
= 1.05V, I = 20A and f = 425kHz.
MAX0,1
V
ꢂ
ꢁ
The regulated output is established by the VOUT_
COMMAND stored in NVM or placing the following resis-
The peak inductor current will be the maximum DC value
plus one-half the ripple current or 23.9A for channel 0
and 23.6A for channel 1. The minimum on time occurs
tor divider between V , the RCONFIG pin and SGND:
DD25
1. V
2. V
, R
= 20k, R
= 17.8k
OUT0_CFG TOP
BOTTOM
on channel 1 at the maximum V , and should not be less
IN
, R
= 24.9k, R
= 7.32k
OUT1_CFG TOP
BOTTOM
than 90ns:
The frequency and phase are set by NVM or by setting the
resistor divider between VDD25, FREQ_CFG and SGND and
DD25
VOUT
1.5V
tON(MIN)
=
=
=118ns
V
IN(MAX) •f 20V •425kHz
V
, PHASE_CFG and SGND.
The next design focuses on Channel1 only.
Frequency, R
= 24.9kΩ and R
= 4.32kΩ
TOP
BOTTOM
The Coiltronics/Eaton FP1007R3-R30-R 0.3μH (0.29mΩ
DCR at 20°C) is used for channel 1. So IOUT_CAL_GAIN
= 0.29mΩ.
Phase, R
= open and R
= 0Ω
TOP
BOTTOM
The address is set to XF where X is the MSB stored in
the NVM.
Based on the output current and inductor value, it is con-
sidered to be a perfect example of low DCR application.
The following parameters are set as a percentage of the
output voltage if the resistor configuration pins are used
to determined output voltage:
Set: MFR_PWM_MODE[2] = 1 (Ultralow DCR)
then choose C = 220nF,
n
VOUT_OV_FAULT_LIMIT.................................. +10%
n
VOUT_OV_WARN_LIMIT................................. +7.5%
L
0.30µH
n
VOUT_MAX...................................................... +7.5%
R1=
=
= 940.4�
DCR • C • 5 0.29m� • 220nF • 5
n
VOUT_MARGIN_HIGH...........................................5%
n
VOUT_MARGIN_LOW............................................5%
Choose R1 = 931Ω (standard value, 1% tolerance resistor).
n
VOUT_UV_WARN_LIMIT....................................6.5%
The maximum power loss in R1 is related to the duty
cycle, and will occur in continuous conduction mode at
the maximum input voltage:
n
VOUT_UV_FAULT_LIMIT.......................................7%
All other user defined parameters must be programmed
into the NVM. The GUI can be utilized to quickly set up
the part with the desired operating parameters.
V
IN(MAX) – VOUT •V
(
)
OUT
P
=
LOSSR1
R1
The inductance values are based on a 40% maximum rip-
ple current assumption (8A). The highest value of ripple
current occurs at the maximum input voltage:
20−1 •1.5
(
)
=
=20.4mW
931
ꢀ
ꢃ
ꢅ
ꢄ
VOUT
f•ΔI
VOUT
IN(MAX) ꢅ
The current limit will be set 30% higher than the peak
value to assure variation in components and noise in the
system do not limit the average current.
ꢂ
L=
1–
V
L(MAX) ꢂ
ꢁ
Channel 0 will require 0.41μH and channel 1 will require
0.28μH. Use a standard value of L = 0.4µH for channel 0
V
= (1 + 30%) • I
• R
ILIMIT
PEAK DCR(MAX)
= (1 + 30%) • 23.6A • 0.29mΩ = 8.9mV
and L = 0.3µH for channel 1. At the nominal V = 12V, the
IN
Rev 0
63
For more information www.analog.com
LTC7132
APPLICATIONS INFORMATION
Based on Figure 26, set MFR_PWM_MODE[1] = 1(low
sure a unique address for each chip can be decoded with
the ASEL0 and ASEL1 pins. Refer to Table 6. For maxi-
TOP BOTTOM
for any parameter that is set with resistors such as ASEL0
and ASEL1.
V
range), MFR_PWM_MODE[2] = 1, (ultralow DCR)
OUT
and MFR_PWM_MODE[7] = 0 (low current range) and
mum flexibility, allow board space for R
and R
IOUT_CAL_GAIN = 0.29mΩ in GUI.
Enter IOUT_OC_FAULT_LIMIT = 30.69A, the LTC7132
will automatically set the current limit to 29.62A, based
on the IOUT_FAULT_LIMIT table, (see PMBus command
for details).
2
CONNECTING THE USB TO I C/SMBus/PMBus
CONTROLLER TO THE LTC7132 IN SYSTEM
The ADI USB-to-I2C/SMBus/PMBus adapter (DC1613A or
equivalent) can be interfaced to the LTC7132 on the user’s
board for programming, telemetry and system debug.
The adapter, when used in conjunction with LTpowerPlay,
provides a powerful way to debug an entire power sys-
tem. Faults are quickly diagnosed using telemetry, fault
status commands and the fault log. The final configura-
tion can be quickly developed and stored to the LTC7132
EEPROM. Figure 46 illustrates the application schematic
for powering, programming and communication with one
or more LTC7132s via the ADI I2C/SMBus/PMBus adapter
regardless of whether or not system power is present. If
system power is not present the dongle will power the
ADDITIONAL DESIGN CHECKS
Tie FAULT0 and FAULT1 together and pull up to V
with
a 10k resistor. Tie RUN0 and RUN1 together anDdDp33ull up
to V
with a 10k resistor.
DD33
If there are other ADI PSM parts, connect the RUN pins
between chips and connect the FAULT pins between chips.
Be sure all PMBus pins have resistor pull-up to V
DD33
and connect these inputs across all ADI PSM parts in
the application.
Tie SHARE_CLK high with a 4.99k resistor to V
share between all ADI PSM parts in the application. Be
and
DD33
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ꢘꢑꢈꢂꢌꢒ ꢐꢑꢒ RꢒꢇꢁꢇꢐꢏR ꢃꢁꢀꢁꢃꢒR ꢏꢂ ꢐꢑꢒ ꢓꢋꢒꢐ ꢌꢈꢐꢒ
ꢙꢉꢄꢅ ꢋꢚꢙ
Figure 46. Controller Connection
Rev 0
64
For more information www.analog.com
LTC7132
APPLICATIONS INFORMATION
LTC7132 through the V
supply pin. To initialize the
IC configuration files that can be saved and reloaded at a
later time. LTpowerPlay provides unprecedented diagnos-
tic and debug features. It becomes a valuable diagnostic
tool during board bring-up to program or tweak the power
system or to diagnose power issues when bring up rails.
DD33
part when V is not applied and the V
pin is powered
IN
DD33
use global address 0x5B command 0xBD data 0x2B fol-
lowed by address 0x5B command 0xBD data 0xC4.The
LTC7132 can now communicate with, and the project file
can be updated. To write the updated project file to the
2
LTpowerPlay utilizes Analog Devices' USB-to-I C/SMBus/
NVM issue a STORE_USER _ALL command. When V is
PMBus adapter to communication with one of the many
potential targets including the DC2165A demo board, the
DC2666A socketed programming board, or a customer
target system. The software also provides an automatic
update feature to keep the revisions current with the latest
set of device drivers and documentation.
IN
applied, a MFR_RESET must be issued to allow the PWM
to be enabled and valid ADCs to be read.
Because of the adapter’s limited current sourcing capabil-
ity, only the LTC7132s, their associated pull-up resistors
and the I2C pull-up resistors should be powered from
the ORed 3.3V supply. In addition any device sharing
the I2C bus connections with the LTC7132 should not
have body diodes between the SDA/SCL pins and their
A great deal of context sensitive help is available with
LTpower Play along with several tutorial demos. Complete
information is available at:
respective V node because this will interfere with bus
DD
www.analog.com/en/design-center/ltpower-play
communication in the absence of system power. If V is
applied, the DC1613A will not supply the power toINthe
LTC7132s on the board. It is recommended the RUNn
pins be held low or no voltage configuration resistors
inserted to avoid providing power to the load until the
part is fully configured.
PMBus COMMUNICATION AND COMMAND
PROCESSING
The LTC7132 has a one deep buffer to hold the last data
written for each supported command prior to processing
as shown in Figure 48, Write Command Data Processing.
When the part receives a new command from the bus,
it copies the data into the Write Command Data Buffer,
indicates to the internal processor that this command data
needs to be fetched, and converts the command to its
internal format so that it can be executed. Two distinct
parallel blocks manage command buffering and command
processing (fetch, convert, and execute) to ensure the last
data written to any command is never lost. Command
data buffering handles incoming PMBus writes by stor-
ing the command data to the Write Command Data Buffer
and marking these commands for future processing. The
internal processor runs in parallel and handles the some-
times slower task of fetching, converting and executing
commands marked for processing. Some computation-
ally intensive commands (e.g., timing parameters, tem-
peratures, voltages and currents) have internal proces-
sor execution times that may be long relative to PMBus
timing. If the part is busy processing a command, and
new command(s) arrive, execution may be delayed or
processed in a different order than received. The part
The LTC7132 is fully isolated from the host PC’s ground
by the DC1613A.The 3.3V from the adapter and the
LTC7132 V
pin must be driven to each LTC7132 with
a separate PDDF3E3T. If both V and EXTV are not applied,
IN
CC
the VDD33 pins can be in parallel because the on-chip
LDO is off. The controller 3.3V current limit is 100mA but
typical V
currents are under 15mA. The V
does
DD33
DD33
back drive the INTV /EXTV pin. Normally this is not
CC
CC
an issue if V is open.
IN
LTpowerPlay: AN INTERACTIVE GUI FOR DIGITAL
POWER
LTpowerPlay (Figure 47) is a powerful Windows-based
development environment that supports Analog Devices
digital power system management ICs including the
LTC7132. The software supports a variety of differ-
ent tasks. LTpowerPlay can be used to evaluate Analog
Devices ICs by connecting to a demo board or the user
application. LTpowerPlay can also be used in an offline
mode (with no hardware present) in order to build multiple
Rev 0
65
For more information www.analog.com
LTC7132
APPLICATIONS INFORMATION
Figure 47. LTpowerPlay Screen Shot
ꢂꢄꢀ
ꢌRꢅꢇꢁ ꢂꢃꢄꢄꢈꢆꢀ
ꢀꢈꢇꢈ ꢍꢎꢏꢏꢁR
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ꢀꢁꢂꢃꢀꢁR
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ꢘ
0ꢑ00
0ꢑꢒꢓ
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ꢂꢄꢀꢋ
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ꢘ
ꢘ
ꢘ
ꢄꢏRꢙRꢁꢋꢁꢇ
ꢑꢓ
0ꢑꢏꢀ
ꢋ
R
ꢂꢈꢉꢂꢎꢉꢈꢇꢅꢃꢆꢋ
ꢊꢁꢆꢀꢅꢆꢐ
ꢔꢓꢕꢒ ꢏꢖꢗ
Figure 48. Write Command Data Processing
Rev 0
66
For more information www.analog.com
LTC7132
APPLICATIONS INFORMATION
// wait until chip is not busy
do
{
mfrCommonValue = PMBUS_READ_BYTE(0xEF);
partReady = (mfrCommonValue & 0x68) == 0x68;
}while(!partReady)
// now the part is ready to receive the next command
PMBUS_WRITE_WORD(0x21, 0x2000); //write VOUT_COMMAND to 2V
Figure 50 . Example of a Command Write of VOUT_COMMAND
indicates when internal calculations are in process via
bit 5 of MFR_COMMON (‘calculations not pending’).
When the part is busy calculating, bit 5 is cleared. When
this bit is set, the part is ready for another command.
An example polling loop is provided in Figure 50 which
ensures that commands are processed in order while sim-
plifying error handling routines.
PMBus read byte of the MFR_COMMON register until all
three bits are set. A command immediately following the
status bits being set will be accepted without NACKing or
generating a BUSY fault/ALERT notification. The part can
NACK commands for other reasons, however, as required
by the PMBus spec (for instance, an invalid command
or data). An example of a robust command write algo-
rithm for the VOUT_COMMAND register is provided in
Figure 50.
When the part receives a new command while it is busy,
it will communicate this condition using standard PMBus
protocol. Depending on part configuration it may either
NACK the command or return all ones (0xFF) for reads.
It may also generate a BUSY fault and ALERT notifica-
tion, or stretch the SCL clock low. For more information
refer to PMBus Specification v1.1, Part II, Section 10.8.7
and SMBus v2.0 section 4.3.3. Clock stretching can be
enabled by asserting bit 1 of MFR_CONFIG_ ALL. Clock
stretching will only occur if enabled and the bus com-
munication speed exceeds 100kHz.
It is recommended that all command writes (write byte,
write word, etc.) be preceded with a polling loop to avoid
the extra complexity of dealing with busy behavior and
unwanted ALERT notification. A simple way to achieve this
is to create a SAFE_WRITE_BYTE() and SAFE_WRITE_
WORD() subroutine. The above polling mechanism allows
your software to remain clean and simple while robustly
communicating with the part. For a detailed discussion
of these topics and other special cases please refer to the
application note section located at:
PMBus busy protocols are well accepted standards, but
can make writing system level software somewhat com-
plex. The part provides three ‘hand shaking’ status bits
which reduce complexity while enabling robust system
level communication.
www.analog.com/en/education.html
When communicating using bus speeds at or below
100kHz, the polling mechanism shown here provides a
simple solution that ensures robust communication with-
out clock stretching. At bus speeds in excess of 100kHz,
it is strongly recommended that the part be configured to
enable clock stretching. This requires a PMBus master that
supports clock stretching. System software that detects
and properly recovers from the standard PMBus NACK/
BUSY faults as described in the PMBus Specification v1.1,
Part II, Section 10.8.7 is required to communicate: the
LTC7132 is not recommended in applications with bus
speeds in excess of 400kHz.
The three hand shaking status bits are in the MFR_
COMMON register. When the part is busy executing an
internal operation, it will clear bit 6 of MFR_COMMON
(‘chip not busy’). When the part is busy specifically
because it is in a transitional V
state (margining hi/lo,
OUT
power off/on, moving to a new output voltage set point,
etc.) it will clear bit 4 of MFR_COMMON (‘output not in
transition’). When internal calculations are in process, the
part will clear bit 5 of MFR_COMMON (‘calculations not
pending’). These three status bits can be polled with a
Rev 0
67
For more information www.analog.com
LTC7132
PMBus COMMAND DETAILS
ADDRESSING AND WRITE PROTECT
CMD
DATA
DEFAULT
COMMAND NAME
PAGE
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM VALUE
0x00 Provides integration with multi-page PMBus devices.
R/W Byte
N
N
N
Reg
Reg
0x00
PAGE_PLUS_WRITE
PAGE_PLUS_READ
0x05 Write a supported command directly to a PWM channel. W Block
0x06 Read a supported command directly from a PWM
channel.
Block
R/W
WRITE_PROTECT
0x10 Level of protection provided by the device against
accidental changes.
R/W Byte
N
Y
0x00
2
MFR_ADDRESS
0xE6 Sets the 7-bit I C address byte.
R/W Byte
R/W Byte
N
Y
Reg
Reg
Y
Y
0x4F
0x80
MFR_RAIL_ADDRESS
0xFA Common address for PolyPhase outputs to adjust
common parameters.
PAGE
The PAGE command provides the ability to configure, control and monitor both PWM channels through only one physi-
cal address, either the MFR_ADDRESS or GLOBAL device address. Each PAGE contains the operating commands for
one PWM channel.
Pages 0x00 and 0x01 correspond to Channel 0 and Channel 1, respectively, in this device.
Setting PAGE to 0xFF applies any following paged commands to both outputs. With PAGE set to 0xFF the LTC7132
will respond to read commands as if PAGE were set to 0x00 (Channel 0 results).
This command has one data byte.
PAGE_PLUS_WRITE
The PAGE_PLUS_WRITE command provides a way to set the page within a device, send a command, and then send
the data for the command, all in one communication packet. Commands allowed by the present write protection level
may be sent with PAGE_PLUS_WRITE.
The value stored in the PAGE command is not affected by PAGE_PLUS_WRITE. If PAGE_PLUS_WRITE is used to send
a non-paged command, the Page Number byte is ignored.
This command uses Write Block protocol. An example of the PAGE_PLUS_WRITE command with PEC sending a com-
mand that has two data bytes is shown in Figure 50.
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ꢖ
ꢘ
ꢘ
ꢗ
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ꢗ
ꢘ
ꢗ
ꢘ
ꢗ
ꢘ
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ꢆꢂꢇꢄꢈꢆꢁꢉꢀ
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ꢎꢁꢋꢊꢏ ꢊꢋꢉꢍꢐ
ꢑꢒ ꢓꢔ
ꢆꢂꢇꢄ
ꢍꢉꢌꢎꢄR
ꢊꢋꢌꢌꢂꢍꢅ
ꢊꢋꢅꢄ
ꢀ
ꢕ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢙ
ꢗ
ꢘ
ꢗ
ꢘ
ꢗ
ꢘ
ꢘ
ꢁꢋꢕꢄR ꢅꢂꢐꢂ
ꢎꢚꢐꢄ
ꢉꢆꢆꢄR ꢅꢂꢐꢂ
ꢎꢚꢐꢄ
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ꢂ
ꢆꢄꢊ ꢎꢚꢐꢄ
ꢂ
ꢆ
ꢖꢘꢛꢜ ꢝꢞꢘ
Figure 50 . Example of PAGE_PLUS_WRITE
Rev 0
68
For more information www.analog.com
LTC7132
PMBus COMMAND DETAILS
PAGE_PLUS_READ
The PAGE_PLUS_READ command provides the ability to set the page within a device, send a command, and then read
the data returned by the command, all in one communication packet .
The value stored in the PAGE command is not affected by PAGE_PLUS_READ. If PAGE_PLUS_READ is used to access
data from a non-paged command, the Page Number byte is ignored.
This command uses the Process Call protocol. An example of the PAGE_PLUS_READ command with PEC is shown
in Figure 51.
ꢁ
ꢗ
ꢁ
ꢁ
ꢘ
ꢁ
ꢘ
ꢁ
ꢘ
ꢁ
ꢘ
ꢁ
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ꢄꢇꢇRꢆꢂꢂ
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ꢒꢓ ꢔꢕ
ꢀꢄꢈꢆ
ꢎꢊꢍꢏꢆR
ꢋꢌꢍꢍꢄꢎꢇ
ꢋꢌꢇꢆ
ꢂ
ꢖ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢙ
ꢁ
ꢗ
ꢁ
ꢁ
ꢘ
ꢁ
ꢘ
ꢁ
ꢘ
ꢁ
ꢘ
ꢁ
ꢁ
ꢂꢃꢄꢅꢆ
ꢄꢇꢇRꢆꢂꢂ
ꢏꢃꢌꢋꢐ ꢋꢌꢊꢎꢑ
ꢃꢌꢖꢆR ꢇꢄꢑꢄ
ꢏꢚꢑꢆ
ꢊꢀꢀꢆR ꢇꢄꢑꢄ
ꢏꢚꢑꢆ
ꢂꢛ
R
ꢄ
ꢄ
ꢄ
ꢄ
ꢀꢆꢋ ꢏꢚꢑꢆ
ꢎꢄ
ꢀ
ꢒꢓ ꢔꢕ
ꢗꢁꢜꢔ ꢝꢞꢔ
Figure 51. Example of PAGE_PLUS_READ
Note: PAGE_PLUS commands cannot be nested. A PAGE_PLUS command cannot be used to read or write another
PAGE_PLUS command. If this is attempted, the LTC7132 will NACK the entire PAGE_PLUS packet and issue a CML
fault for Invalid/Unsupported Data.
WRITE_PROTECT
The WRITE_PROTECT command is used to control writing to the LTC7132 device. This command does not indicate
the status of the WP pin which is defined in the MFR_COMMON command. The WP pin takes precedence over the
value of this command.
BYTE MEANING
0x80 Disable all writes except to the WRITE_PROTECT, PAGE, MFR_
EE_UNLOCK, and STORE_USER_ALL commands.
0x40 Disable all writes except to the WRITE_PROTECT, PAGE,
MFR_EE_UNLOCK, MFR_CLEAR_PEAKS, STORE_USER_ALL,
OPERATION and CLEAR_FAULTS command. Individual fault
bits can be cleared by writing a 1 to the respective bits in the
STATUS commands.
0x20 Disable all writes except to the WRITE_PROTECT, OPERATION,
MFR_EE_UNLOCK, MFR_CLEAR_PEAKS, CLEAR_FAULTS,
PAGE, ON_OFF_CONFIG, VOUT_COMMAND and STORE_USER_
ALL. Individual fault bits can be cleared by writing a 1 to the
respective bits in the STATUS commands.
0x10 Reserved, must be 0
0x08 Reserved, must be 0
0x04 Reserved, must be 0
0x02 Reserved, must be 0
0x01 Reserved, must be 0
Enable writes to all commands when WRITE_PROTECT is set to 0x00.
If WP pin is high, PAGE, OPERATION, MFR_CLEAR_PEAKS, MFR_EE_UNLOCK, WRITE_PROTECT and CLEAR_FAULTS
commands are supported. Individual fault bits can be cleared by writing a 1 to the respective bits in the STATUS commands.
Rev 0
69
For more information www.analog.com
LTC7132
PMBus COMMAND DETAILS
MFR_ADDRESS
The MFR_ADDRESS command byte sets the 7 bits of the PMBus slave address for this device.
Setting this command to a value of 0x80 disables device addressing. The GLOBAL device address, 0x5A and 0x5B,
cannot be deactivated. If RCONFIG is set to ignore, the ASEL0 and ASEL1 pins are still used to determine the LSB
and MSB, respectively, of the channel address. If the ASEL0 and ASEL1 pins are both open, the LTC7132 will use the
address value stored in NVM. If the ASEL0 pin is open, the LTC7132 will use the lower 4 bits of the MFR_ADDRESS
value stored in NVM to construct the effective address of the part. If the ASEL1 pin is open, the LTC7132 will use the
upper 4 bits of the MFR_ADDRESS value stored in NVM to construct the effective address of the part.
This command has one data byte.
MFR_RAIL_ADDRESS
The MFR_RAIL_ADDRESS command enables direct device address access to the PAGE activated channel. The value
of this command should be common to all devices attached to a single power supply rail.
The user should only perform command writes to this address. If a read is performed from this address and the rail
devices do not respond with EXACTLY the same value, the LTC7132 will detect bus contention and may set a CML
communications fault.
Setting this command to a value of 0x80 disables rail device addressing for the channel.
This command has one data byte.
GENERAL CONFIGURATION COMMANDS
DATA
DEFAULT
VALUE
COMMAND NAME
MFR_CHAN_CONFIG
MFR_CONFIG_ALL
CMD CODE DESCRIPTION
TYPE
Configuration bits that are channel specific. R/W Byte
General configuration bits. R/W Byte
PAGED FORMAT UNITS NVM
0xD0
0xD1
Y
N
Reg
Reg
Y
Y
0x10
0x21
MFR_CHAN_CONFIG
General purpose configuration command common to multiple ADI products.
BIT MEANING
7
6
5
4
3
2
1
Reserved
Reserved
Reserved
Disable RUN Low. When asserted the RUN pin is not pulsed low if commanded OFF.
Enable Short Cycle recognition if this bit is set to a 1.
SHARE_CLOCK control. If SHARE_CLOCK is held low, the output is disabled.
No FAULT ALERT, ALERT is not pulled low if FAULT is pulled low externally. Assert this bit if either POWER_GOOD or VOUT_UVUF are
propagated on FAULT.
0
Disables the V
decay value requirement for MFR_RETRY_TIME and t
processing. When this bit is set to a 0, the output must decay to
OUT
OFF(MIN)
less than 12.5% of the programmed value for any action that turns off the rail including a fault, an OFF/ON command, or a toggle of RUN from
high to low to high.
This command has one data byte.
Rev 0
70
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LTC7132
PMBus COMMAND DETAILS
A ShortCycle event occurs whenever the PWM channel is commanded back ON, or reactivated, after the part has been
commanded OFF and is processing either the TOFF_DELAY or the TOFF_FALL states. The PWM channel can be turned
ON and OFF through either the RUN pin and or the PMBus OPERATION command.
If the PWM channel is reactivated during the TOFF_DELAY, the part will perform the following:
1. Immediately tri-state the PWM channel output;
2. Start the retry delay timer as specified by the t
.
OFF(MIN)
3. After the t
value has expired, the PWM channel will proceed to the TON_DELAY state and the STATUS_
OFF(MIN)
MFR_SPECIFIC bit #1 will assert.
If the PWM channel is reactivated during the TOFF_FALL, the part will perform the following:
1. Stop ramping down the PWM channel output;
2. Immediately tri-state the PWM channel output;
3. Start the retry delay timer as specified by the t
.
OFF(MIN)
4. After the t
value has expired, the PWM channel will proceed to the TON_DELAY state and the STATUS_
OFF(MIN)
MFR_SPEFIFIC bit #1 will assert.
If the ShortCycle event occurs and the ShortCycle MFR_CHAN_CONFIG bit is not set, the PWM channel state machine
will complete its TOFF_DELAY and TOFF_FALL operations as previously commanded by the user.
MFR_CONFIG_ALL
General purpose configuration command common to multiple ADI products.
BIT MEANING
7
6
5
4
3
2
1
0
Enable Fault Logging
Ignore Resistor Configuration Pins
Mask PMBus, Part II, Section 10.9.1 Violations
Disable SYNC output
Enable 255ms PMBus timeout
PMBus command writes require a valid Packet Error Checking, PEC to be accepted.*
Enable the use of PMBus clock stretching
Execute CLEAR_FAULTS on rising edge of either RUN pin.
*PMBus command writes that have a valid PEC byte are always processed. PMBus command
writes that have an invalid PEC byte are not processed and set a CML status fault.
This command has one data byte.
ON/OFF/MARGIN
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
ON_OFF_CONFIG
OPERATION
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
0x02 RUN pin and PMBus bus on/off command configuration. R/W Byte
Y
Y
Reg
Reg
Y
Y
0x1E
0x80
0x01 Operating mode control. On/off, margin high and margin R/W Byte
low.
MFR_RESET
0xFD Commanded reset without requiring a power-down.
Send Byte
N
NA
Rev 0
71
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LTC7132
PMBus COMMAND DETAILS
ON_OFF_CONFIG
The ON_OFF_CONFIG command specifies the combination of RUNn pin input state and PMBus commands needed to
turn the PWM channel on and off.
Supported Values:
VALUE
0x1F
MEANING
OPERATION value and RUNn pin must both command the device to start/run. Device executes immediate off when commanded off.
OPERATION value and RUNn pin must both command the device to start/run. Device uses TOFF_ command values when commanded off.
RUNn pin control with immediate off when commanded off. OPERATION on/off control ignored.
RUNn pin control using TOFF_ command values when commanded off. OPERATION on/off control ignored.
0x1E
0x17
0x16
Programming an unsupported ON_OFF_CONFIG value will generate a CML fault and the command will be ignored.
This command has one data byte.
OPERATION
The OPERATION command is used to turn the unit on and off in conjunction with the input from the RUNn pins. It
is also used to cause the unit to set the output voltage to the upper or lower MARGIN VOLTAGEs. The unit stays in
the commanded operating mode until a subsequent OPERATION command or change in the state of the RUNn pin
instructs the device to change to another mode. If the part is stored in the MARGIN_LOW/HIGH state, the next RESET
or POWER_ON cycle will ramp to that state. If the OPERATION command is modified, for example ON is changed
to MARGIN_LOW, the output will move at a fixed slope set by the VOUT_TRANSITION_RATE. The default operation
command is sequence off. If V is applied to a part with factory default programming and the VOUT_CONFIG resistor
IN
configuration pins are not installed, the outputs will be commanded off.
The part defaults to the Sequence Off state.
This command has one data byte.
Supported Values:
VALUE
0xA8
MEANING
Margin high.
Margin low.
0x98
0x80
On (V
back to nominal even if bit 3 of ON_OFF_CONFIG is not set).
OUT
0x40*
0x00*
Soft off (with sequencing).
Immediate off (no sequencing).
*Device does not respond to these commands if bit 3 of ON_OFF_CONFIG is not set.
Programming an unsupported OPERATION value will generate a CML fault and the command will be ignored.
This command has one data byte.
MFR_RESET
This command provides a means to reset the LTC7132 from the serial bus. This forces the LTC7132 to turn off both
PWM channels, load the operating memory from internal EEPROM, clear all faults and then perform a soft-start of
both PWM channels, if enabled.
This write-only command has no data bytes.
Rev 0
72
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LTC7132
PMBus COMMAND DETAILS
PWM CONFIGURATION
DATA
DEFAULT
COMMAND NAME
MFR_PWM_COMP
MFR_PWM_MODE
MFR_PWM_CONFIG
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM VALUE
0xD3
0xD4
0xF5
PWM loop compensation configuration
R/W Byte
R/W Byte
R/W Byte
Y
Y
N
Reg
Reg
Reg
Y
Y
Y
0xAE
0xC7
0x10
Configuration for the PWM engine.
Set numerous parameters for the DC/DC controller
including phasing.
FREQUENCY_SWITCH
0x33
Switching frequency of the controller.
R/W
Word
N
L11
kHz
Y
425
0xFB52
MFR_PWM_MODE
The MFR_PWM_MODE command sets important PWM controls for each channel.
The MFR_PWM_MODE command allows the user to program the PWM controller to use discontinuous (pulse-skipping
mode), or forced continuous conduction mode.
BIT
7
0b
1b
6
MEANING
Use High Range of I
Low Current Range
High Current Range
Enable Servo Mode
LIMIT
5
External temperature sense:
0: ∆V measurement.
BE
1: Direct voltage measurement.
Reserved
[4:3]
2
Enable ultra-low DCR current sense
1
V
Range
OUT
1b
0b
The maximum output voltage is 2.75V
The maximum output voltage is 5.5V
Bit[0] Mode
0b
1b
Discontinuous
Forced Continuous
Bit [7] of this command determines if the part is in high range or low range of the IOUT_OC_FAULT_LIMIT command.
Changing this bit value changes the PWM loop gain and compensation. This bit value should not be changed when the
channel output is active. Writing this bit when the channel is active will generate a CML fault.
Bit [6] The LTC7132 will not servo while the part is OFF, ramping on or ramping off. When set to a one, the output servo
is enabled. The output set point DAC will be slowly adjusted to minimize the difference between the READ_VOUT_ADC
and the VOUT_COMMAND (or the appropriate margined value).
When Bit[5] is cleared, the LTC7132 computes temperature in °C from ∆V measured by the ADC at the TSNSn pin as
BE
T = (G • ∆V • q/(K • ln(16))) – 273.15 + O
BE
When Bit[5] is set, the LTC7132 computes temperature in °C from TSNSn voltage measured by the ADC as
T = (G • (1.35 – V
+ O)/4.3e-3) + 25
TSNSn
Rev 0
73
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LTC7132
PMBus COMMAND DETAILS
For both equations,
–14
G = MFR_TEMP_1_GAIN • 2 , and
O = MFR_TEMP_1_OFFSET
–23
K = 1.381 • 10 J/K
–19
q = 1.602 • 10
C
Bit[2] determines if the part uses ultralow DCR for sensing the output current. This is a very critical selection in terms
of overcurrent limit. It is highly recommend that Bit[2] should not be changed when device is in operation.
Bit[1] of this command determines if the part is in high range or low voltage range. Changing this bit value changes
the PWM loop gain and compensation. This bit value should not be changed when the channel output is active. Writing
this bit when the channel is active will generate a CML fault.
B
it[0] determines if the PWM mode of operation is discontinuous (pulse-skipping mode), or forced continuous con-
duction mode. Whenever the channel is ramping on, the PWM mode will be discontinuous, regardless of the value of
this bit. This command has one data byte.
MFR_PWM_COMP
The MFR_PWM_COMP command sets the g of the PWM channel error amplifiers and the value of the internal R
m
ITHn
compensation resistors. This command affects the loop gain of the PWM output which may require modifications to
the external compensation network.
BIT
MEANING
BIT [7:5]
000b
Error Amplifier GM Adjust (mS)
0.8
1.3
1.9
2.4
2.9
3.5
4.0
4.6
001b
010b
011b
100b
101b
110b
111b
BIT [4:0 ]
00000b
00001b
00010b
00011b
00100b
00101b
00110b
00111b
01000b
01001b
01010b
01011b
01100b
01101b
R
ITH
(kΩ)
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.5
3
3.5
4
4.5
Rev 0
74
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LTC7132
PMBus COMMAND DETAILS
01110b
01111b
10000b
10001b
10010b
10011b
10100b
10101b
10110b
10111b
11000b
11001b
11010b
11011b
11100b
11101b
11110b
11111b
5
5.5
6
7
8
9
11
13
15
17
20
24
28
32
38
46
54
62
This command has one data byte.
MFR_PWM_CONFIG
The MFR_PWM_CONFIG command sets the switching frequency phase offset with respect to the falling edge of the
SYNC signal. The part must be in the OFF state to process this command. Either the RUN pins must be low or the
channels must be commanded off. If either channel is in the RUN state and this command is written, the command
will be NACK’d and a BUSY fault will be asserted.
BIT
MEANING
7
Reserved
[6:5]
00b
01b
10b
11b
Input current sense gain.
2x gain. 0mV to 50mV range.
4x gain. 0mV to 20mV range.
8x gain. 0mV to 5mV range.
Reserved
4
Share Clock Enable : If this bit is 1, the
SHARE_CLK pin will not be released until
V
> VIN_ON. The SHARE_CLK pin will be
IN
pulled low when V < VIN_OFF. If this bit is 0, the
IN
SHARE_CLK pin will not be pulled low when VIN <
VIN_OFF except for the initial application of VIN.
BIT [2:0 ]
000b
001b
010b
011b
100b
101b
110b
CHANNEL 0 (DEGREES) CHANNEL 1 (DEGREES)
0
90
0
180
270
240
120
240
240
300
0
120
60
120
Rev 0
75
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LTC7132
PMBus COMMAND DETAILS
FREQUENCY_SWITCH
The FREQUENCY_SWITCH command sets all switching frequencies between 250kHz to 1MHz.
The part must be in the OFF state to process this command. The RUN pin must be low or both channels must be
commanded off. If the part is in the RUN state and this command is written, the command will be NACK'd and a BUSY
fault will be asserted. When the part is commanded off and the frequency is changed, a PLL_UNLOCK status may be
detected as the PLL locks onto the new frequency.
This command has two data bytes and is formatted in Linear_5s_11s format.
VOLTAGE
Input Voltage and Limits
DATA
PAGED FORMAT
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
UNITS
NVM
VIN_OV_FAULT_LIMIT
0x55
0x58
0x35
0x36
0xF7
Input supply overvoltage fault limit.
R/W
N
N
N
N
N
L11
L11
L11
L11
L11
V
Y
15.5
Word
0xD3E0
VIN_UV_WARN_LIMIT
VIN_ON
Input supply undervoltage warning limit.
R/W
Word
V
V
Y
Y
Y
Y
6.3
0xCB26
Input voltage at which the unit should start
power conversion.
R/W
Word
6.5
0xCB40
VIN_OFF
Input voltage at which the unit should stop
power conversion.
R/W
Word
V
6.0
0xCB00
MFR_RVIN
The resistance value of the V pin filter
R/W
Word
mΩ
1000
0x03E8
IN
element in milliohms
VIN_OV_FAULT_LIMIT
The VIN_OV_FAULT_LIMIT command sets the value of the input voltage measured by the ADC, in volts, that causes
an input overvoltage fault.
This command has two data bytes in Linear_5s_11s format.
VIN_UV_WARN_LIMIT
The VIN_UV_WARN_LIMIT command sets the value of input voltage measured by the ADC that causes an input under
voltage warning. This warning is disabled until the input exceeds the input startup threshold value set by the VIN_ON
command and the unit has been enabled. If the V Voltage drops below the VIN_OV_WARN_LIMIT the device:
-
IN
•
•
•
Sets the INPUT Bit Is the STATUS_WORD
Sets the V Undervoltage Warning Bit in the STATUS_INPUT Command
IN
Notifies the Host by Asserting ALERT, unless Masked
VIN_ON
The VIN_ON command sets the input voltage, in Volts, at which the unit starts power conversion.
This command has two data bytes and is formatted in Linear_5s_11s format.
Rev 0
76
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LTC7132
PMBus COMMAND DETAILS
VIN_OFF
The VIN_OFF command sets the input voltage, in Volts, at which the unit stops power conversion.
This command has two data bytes and is formatted in Linear_5s_11s format.
MFR_RVIN
The MFR_RVIN command is used to set the resistance value of the VIN pin filter element in milliohms. (See also
READ_VIN). Set MFR_RVIN equal to 0 if no filter element is used.
This command has two data bytes and is formatted in Linear_5s_11s format.
Output Voltage and Limits
CMD
DATA
DEFAULT
VALUE
2
0x14
2.75
0x2C00
1.1
0x119A
1.075
0x1133
1.05
0x10CD
1.0
0x1000
0.95
0x0F33
COMMAND NAME
CODE DESCRIPTION
TYPE
R Byte
PAGED FORMAT
UNITS
NVM
–12
–12
VOUT_MODE
0x20 Output voltage format and exponent (2 ).
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Reg
L16
L16
L16
L16
L16
L16
L16
L16
L16
VOUT_MAX
0x24 Upper limit on the output voltage the unit can
command regardless of any other commands.
R/W
Word
R/W
Word
R/W
Word
R/W
Word
R/W
Word
R/W
Word
R/W
Word
R/W
Word
V
V
V
V
V
V
V
V
V
Y
Y
Y
Y
Y
Y
Y
Y
VOUT_OV_FAULT_ LIMIT
VOUT_OV_WARN_ LIMIT
VOUT_MARGIN_HIGH
VOUT_COMMAND
0x40 Output overvoltage fault limit.
0x42 Output overvoltage warning limit.
0x25 Margin high output voltage set point. Must be
greater than VOUT_COMMAND.
0x21 Nominal output voltage set point.
VOUT_MARGIN_LOW
VOUT_UV_WARN_ LIMIT
VOUT_UV_FAULT_ LIMIT
MFR_VOUT_MAX
0x26 Margin low output voltage set point. Must be
less than VOUT_COMMAND.
0x43 Output undervoltage warning limit.
0x44 Output undervoltage fault limit.
0xA5 Maximum allowed output voltage.
0.925
0x0ECD
0.9
0x0E66
5.7
0x5B33
R Word
VOUT_MODE
The data byte for VOUT_MODE command, used for commanding and reading output voltage, consists of a 3-bit mode
(only linear format is supported) and a 5-bit parameter representing the exponent used in output voltage Read/Write
commands.
This read-only command has one data byte.
VOUT_MAX
The VOUT_MAX command sets an upper limit on any voltage, including VOUT_MARGIN_HIGH, the unit can com-
mand regardless of any other commands or combinations. The maximum allowed value of this command is 5.8V. The
maximum output voltage the LTC7132 can produce is 5.5V including VOUT_MARGIN_HIGH. However, the VOUT_
OV_FAULT_LIMIT can be commanded as high as 5.7V.
This command has two data bytes and is formatted in Linear_16u format.
Rev 0
77
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LTC7132
PMBus COMMAND DETAILS
VOUT_OV_FAULT_LIMIT
The VOUT_OV_FAULT_LIMIT command sets the value of the output voltage measured by the OV supervisor compara-
tor at the sense pins, in volts, which causes an output overvoltage fault.
If the VOUT_OV_FAULT_LIMIT is modified and the part is in the RUN state, allow 10ms after the command is modi-
fied to assure the new value is being honored. The part indicates if it is busy making a calculation. Monitor bits 5 and
6 of MFR_COMMON. Either bit is low if the part is busy. If this wait time is not honored and the VOUT_COMMAND
is modified above the old overvoltage limit, an OV condition might temporarily be detected resulting in undesirable
behavior and possible damage to the switcher.
If VOUT_OV_FAULT_RESPONSE is set to OV_PULLDOWN or 0x00, the FAULT pin will not assert if VOUT_OV_FAULT
is propagated. The LTC7132 will pull the TG low and assert the BG bit as soon as the overvoltage condition is detected.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_OV_WARN_LIMIT
The VOUT_OV_WARN_LIMIT command sets the value of the output voltage measured by the ADC at the sense pins,
in volts, which causes an output voltage high warning. The MFR_VOUT_PEAK value can be used to determine if this
limit has been exceeded.
In response to the VOUT_OV_WARN_LIMIT being exceeded, the device:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT Overvoltage Warning bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked
This condition is detected by the ADC so the response time may be up to t
This command has two data bytes and is formatted in Linear_16u format.
VOUT_MARGIN_HIGH
.
CONVERT
The VOUT_MARGIN_HIGH command loads the unit with the voltage to which the output is to be changed, in Volts,
when the OPERATION command is set to “Margin High”. The value should be greater than VOUT_COMMAND. The
maximum guaranteed value on VOUT_MARGIN_HIGH is 5.5V.
This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_
RATE will be used if this command is modified while the output is active and in a steady-state condition.
This command has two data bytes and is formatted in Linear_16u format.
Rev 0
78
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LTC7132
PMBus COMMAND DETAILS
VOUT_COMMAND
The VOUT_COMMAND consists of two bytes and is used to set the output voltage, in volts. The maximum guaranteed
value on VOUT is 5.5V.
This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_
RATE will be used if this command is modified while the output is active and in a steady-state condition.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_MARGIN_LOW
The VOUT_MARGIN_LOW command loads the unit with the voltage to which the output is to be changed, in volts,
when the OPERATION command is set to “Margin Low”. The value must be less than VOUT_COMMAND.
This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_
RATE will be used if this command is modified while the output is active and in a steady-state condition.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_UV_WARN_LIMIT
The VOUT_UV_ WARN_LIMIT command reads the value of the output voltage measured by the ADC at the sense pins,
in volts, which causes an output voltage low warning.
In response to the VOUT_UV_WARN_LIMIT being exceeded, the device:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT Undervoltage Warning bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked
This command has two data bytes and is formatted in Linear_16u format.
VOUT_UV_FAULT_LIMIT
The VOUT_UV_FAULT_LIMIT command reads the value of the output voltage measured by the UV supervisor com-
parator at the sense pins, in volts, which causes an output undervoltage fault.
This command has two data bytes and is formatted in Linear_16u format.
MFR_VOUT_MAX
The MFR_VOUT_MAX command is the maximum output voltage in volts for each channel, including VOUT_OV_FAULT_
LIMIT. If the output voltages are set to high range (Bit 1 of MFR_PWM_MODE set to a 0) MFR_VOUT_MAX is 5.5V. If
the output voltage is set to low range (Bit 1 of MFR_PWM_MODE set to a 1) the MFR_VOUT_MAX is 2.75V. Entering
a VOUT_COMMAND value greater than this will result in a CML fault and the output voltage setting will be clamped
to the maximum level. This will also result in Bit 3 VOUT_MAX_Warning in the STATUS_VOUT command being set.
This read only command has 2 data bytes and is formatted in Linear_16u format.
Rev 0
79
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LTC7132
PMBus COMMAND DETAILS
OUTPUT CURRENT AND LIMITS
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS
NVM
IOUT_CAL_GAIN
0x38
The ratio of the voltage at the current R/W Word
sense pins to the sensed current. For
devices using a fixed current sense
resistor, it is the resistance value in
mΩ.
Y
L11
mΩ
Y
0.32
0xAA8F
MFR_IOUT_CAL_GAIN_TC
IOUT_OC_FAULT_LIMIT
IOUT_OC_WARN_LIMIT
0xF6
0x46
0x4A
Temperature coefficient of the current R/W Word
sensing element.
Y
Y
Y
CF
Y
Y
Y
3900
0x0F3C
Output overcurrent fault limit.
R/W Word
L11
L11
A
A
45.0
0xE2D0
Output overcurrent warning limit.
R/W Word
34.0
0xE230
IOUT_CAL_GAIN
The IOUT_CAL_GAIN command is used to set the resistance value of the current sense resistor in milliohms. (see
also MFR_IOUT_CAL_GAIN_TC).
This command has two data bytes and is formatted in Linear_5s_11s format.
MFR_IOUT_CAL_GAIN_TC
The MFR_IOUT_CAL_GAIN_TC command allows the user to program the temperature coefficient of the IOUT_CAL_
GAIN sense resistor or inductor DCR in ppm/°C.
This command has two data bytes and is formatted in 16-bit 2’s complement integer ppm. N = –32768 to 32767 •
–6
10 . Nominal temperature is 27°C. The IOUT_CAL_GAIN is multiplied by:
[1.0 + MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERATURE_1-27)].
DCR sensing will have a typical value of 3900.
The IOUT_CAL_GAIN and MFR_IOUT_CAL_GAIN_TC impact all current parameters including: READ_IOUT,
MFR_IOUT_PEAK, IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT.
IOUT_OC_FAULT_LIMIT
The IOUT_OC_FAULT_LIMIT command sets the value of the peak output current limit, in Amperes. When the control-
ler is in current limit, the overcurrent detector will indicate an overcurrent fault condition. The following table lists the
+
–
progammable peak output current limit value in mV between I
and I
. The actual value of current limit is
SENSE
SENSE
+
–
(I
– I
)/IOUT_CAL_GAIN in Amperes.
SENSE
SENSE
Rev 0
80
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LTC7132
PMBus COMMAND DETAILS
MFR_PWM_MODE[2] = 1 (Sub-milli Ω DCR)
RC = L/(5 • DCR)
MFR_PWM_MODE[2] = 0 (Normal Value of DCR)
RC = L/(DCR)
MFR_PWM_MODE[7]=1
CODE High Current Range V
MFR_PWM_MODE[7]=0
MFR_PWM_MODE[7]=1
MFR_PWM_MODE[7]=0
(mV) Low Current Range V
(mV) High Current Range V
(mV) Low Current Range V
(mV)
ILIMIT
ILIMIT
ILIMIT
ILIMIT
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
15.45
16.59
17.73
18.86
20.42
21.14
22.27
23.41
24.55
25.68
26.82
27.95
29.5
8.59
9.22
38.64
41.48
44.32
47.16
51.04
52.84
55.68
58.52
61.36
64.20
67.05
69.89
74.5
21.46
23.04
24.62
26.20
28.36
29.36
30.93
32.51
34.09
35.67
37.25
38.83
41.38
41.98
43.56
45.14
9.85
10.48
11.34
11.74
12.37
13.01
13.64
14.27
14.90
15.53
16.5
30.23
31.36
32.50
16.79
17.42
18.06
75.57
78.41
81.25
Note: V
values used to calculate IOUT_OC_FAULT_LIMIT.
ILIMIT
Note: This is the peak of the current waveform. The READ_IOUT command returns the average current. The peak output current limits are adjusted with
temperature based on the MFR_IOUT_CAL_GAIN_TC using the equation:
Peak Current Limit = IOUT_CAL_GAIN • (1 + MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERTURE_1-27.0)).
The LTC7132 automatically converts currents to the appropriate internal bit value.
The IOUT range is set with bit 7 of the MFR_PWM_MODE command.
The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL.
If the IOUT_OC_FAULT_LIMIT is exceeded, the device:
• Sets the IOUT bit in the STATUS word
• Sets the IOUT Overcurrent fault bit in the STATUS_IOUT
• Notifies the host by asserting ALERT, unless masked
This command has two data bytes and is formatted in Linear_5s_11s format.
IOUT_OC_WARN_LIMIT
This command sets the value of the output current measured by the ADC that causes an output overcurrent warning
in Amperes. The READ_IOUT value will be used to determine if this limit has been exceeded.
In response to the IOUT_OC_WARN_LIMIT being exceeded, the device:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the IOUT bit in the STATUS_WORD
• Sets the IOUT Overcurrent Warning bit in the STATUS_IOUT command, and
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LTC7132
PMBus COMMAND DETAILS
• Notifies the host by asserting ALERT pin, unless masked
The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL.
This command has two data bytes and is formatted in Linear_5s_11s format
Input Current and Limits
CMD
DATA
FORMAT
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
UNITS
NVM
MFR_IIN_CAL_GAIN
0xE8 The resistance value of the input current sense
element in mΩ.
R/W Word
L11
mΩ
Y
5.000
0xCA80
MFR_IIN_CAL_GAIN
The MFR_IIN_CAL_GAIN command is used to set the resistance value of the input current sense resistor in milliohms.
(see also READ_IIN).
This command has two data bytes and is formatted in Linear_5s_11s format.
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
0x5D Input overcurrent warning
limit.
TYPE
PAGED
FORMAT
UNITS
NVM
IIN_OC_WARN_LIMIT
R/W Word
N
L11
A
Y
10.0
0xD280
IIN_OC_WARN_LIMIT
The IIN_OC_WARN_LIMIT command sets the value of the input current measured by the ADC, in amperes, that
causes a warning indicating the input current is high. The READ_IIN value will be used to determine if this limit has
been exceeded.
In response to the IIN_OC_WARN_LIMIT being exceeded, the device:
• Sets the OTHER bit in the STATUS_BYTE
• Sets the INPUT bit in the upper byte of the STATUS_WORD
• Sets the IIN Overcurrent Warning bit[1] in the STATUS_INPUT command, and
• Notifies the host by asserting ALERT pin
This command has two data bytes and is formatted in Linear_5s_11s format.
TEMPERATURE
External Temperature Calibration
DATA
DEFAULT
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM VALUE
MFR_TEMP_1_GAIN
0xF8
Sets the slope of the external temperature
sensor.
R/W Word
Y
Y
CF
Y
Y
1.0
0x4000
MFR_TEMP_1_OFFSET
0xF9
Sets the offset of the external temperature R/W Word
sensor.
L11
C
0.0
0x8000
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LTC7132
PMBus COMMAND DETAILS
MFR_TEMP_1_GAIN
The MFR_TEMP_1_GAIN command will modify the slope of the external temperature sensor to account for non-idealities
in the element and errors associated with the remote sensing of the temperature in the inductor.
This command has two data bytes and is formatted in 16-bit 2’s complement integer. The effective gain adjustment is
–14
N • 2 . The nominal value is 1.
MFR_TEMP_1_OFFSET
The MFR_TEMP_1_OFFSET command will modify the offset of the external temperature sensor to account for non-
idealities in the element and errors associated with the remote sensing of the temperature in the inductor.
This command has two data bytes and is formatted in Linear_5s_11s format.
External Temperature Limits
DATA
FORMAT
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED
UNITS
NVM
OT_FAULT_LIMIT
0x4F
0x51
0x53
External overtemperature fault limit.
R/W Word
Y
L11
L11
L11
C
Y
100.0
0xEB20
OT_WARN_LIMIT
UT_FAULT_LIMIT
External overtemperature warning
limit.
R/W Word
Y
Y
C
C
Y
Y
85.0
0xEAA8
External undertemperature fault limit. R/W Word
–40.0
0xE580
OT_FAULT_LIMIT
The OT_FAULT_LIMIT command sets the value of the external sense temperature measured by the ADC, in degrees
Celsius, which causes an overtemperature fault. The READ_TEMPERATURE_1 value will be used to determine if this
limit has been exceeded.
This command has two data bytes and is formatted in Linear_5s_11s format.
OT_WARN_LIMIT
The OT_WARN_LIMIT command sets the value of the external sense temperature measured by the ADC, in degrees
Celsius, which causes an overtemperature warning. The READ_TEMPERATURE_1 value will be used to determine if
this limit has been exceeded.
In response to the OT_WARN_LIMIT being exceeded, the device:
• Sets the TEMPERATURE bit in the STATUS_BYTE
• Sets the Overtemperature Warning bit in the STATUS_TEMPERATURE command, and
• Notifies the host by asserting ALERT pin, unless masked
This command has two data bytes and is formatted in Linear_5s_11s format.
Rev 0
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LTC7132
PMBus COMMAND DETAILS
UT_FAULT_LIMIT
The UT_FAULT_LIMITcommand sets the value of the external sense temperature measured by the ADC, in degrees Celsius,
which causes an undertemperature fault. The READ_TEMPERATURE_1 value will be used to determine if this limit has been
exceeded.
Note: If the temp sensors are not installed, the UT_FAULT_LIMIT can be set to –275°C and UT_FAULT_LIMIT response
set to ignore to avoid ALERT being asserted.
This command has two data bytes and is formatted in Linear_5s_11s format.
TIMING
Timing—On Sequence/Ramp
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS
NVM
TON_DELAY
0x60
Time from RUN and/or Operation on to
R/W Word
Y
L11
L11
ms
Y
0.0
output rail turn-on.
0x8000
TON_RISE
0x61
Time from when the output starts to
rise until the output voltage reaches the
VOUT commanded value.
Maximum time from the start of
TON_RISE for VOUT to cross the
VOUT_UV_FAULT_LIMIT.
R/W Word
R/W Word
R/W Word
Y
ms
Y
Y
Y
8.0
0xD200
TON_MAX_FAULT_LIMIT
VOUT_TRANSITION_RATE
TON_DELAY
0x62
0x27
Y
Y
L11
L11
ms
10.0
0xD280
Rate the output changes when VOUT
commanded to a new value.
V/ms
0.25
0xAA00
The TON_DELAY command sets the time, in milliseconds, from when a start condition is received until the output
voltage starts to rise. Values from 0ms to 83 seconds are valid. The resulting turn-on delay will have a typical delay of
270µs for TON_DELAY = 0 and an uncertainty of 50µs for all values of TON_DELAY.
This command has two data bytes and is formatted in Linear_5s_11s format.
TON_RISE
The TON_RISE command sets the time, in milliseconds, from the time the output starts to rise to the time the output
enters the regulation band. Values from 0 to 1.3 seconds are valid. The part will be in discontinuous mode during
TON_RISE events. If TON_RISE is less than 0.25ms, the LTC7132 digital slope will be bypassed and the output voltage
transition will only be controlled by the analog performance of the PWM switcher. The number of steps in TON_RISE
is equal to TON_RISE (in ms)/0.1ms with an uncertainty of 0.1ms.
This command has two data bytes and is formatted in Linear_5s_11s format.
Rev 0
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LTC7132
PMBus COMMAND DETAILS
TON_MAX_FAULT_LIMIT
The TON_MAX_FAULT_LIMIT command sets the value, in milliseconds, on how long the unit can attempt to power
up the output without reaching the output undervoltage fault limit.
A data value of 0ms means that there is no limit and that the unit can attempt to bring up the output voltage indefinitely.
The maximum limit is 83 seconds.
This command has two data bytes and is formatted in Linear_5s_11s format.
VOUT_TRANSITION_RATE
When a PMBus device receives either a VOUT_COMMAND or OPERATION (Margin High, Margin Low) that causes the
output voltage to change, this command set the rate in V/ms at which the output voltage changes. The commanded
rate of change does not apply when the unit is commanded on or off. The maximum allowed slope is 4V/ms.
This command has two data bytes and is formatted in Linear_5s_11s format.
Timing—Off Sequence/Ramp
DATA
FORMAT UNITS
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED
NVM
TOFF_DELAY
0x64
0x65
0x66
Time from RUN and/or Operation off to
the start of TOFF_FALL ramp.
Time from when the output starts to fall R/W Word
until the output reaches zero volts.
Maximum allowed time, after TOFF_FALL R/W Word
completed, for the unit to decay below
12.5%.
R/W Word
Y
L11
L11
L11
ms
ms
ms
Y
0.0
0x8000
TOFF_FALL
Y
Y
Y
Y
8.0
0xD200
150
0xF258
TOFF_MAX_WARN_LIMIT
TOFF_DELAY
The TOFF_DELAY command sets the time, in milliseconds, from when a stop condition is received until the output
voltage starts to fall. Values from 0 to 83 seconds are valid. The resulting turn off delay will have a typical delay of
270µs for TOFF_DELAY = 0 and an uncertainty of 50µs for all values of TOFF_DELAY. TOFF_DELAY is not applied
when a fault event occurs
This command has two data bytes and is formatted in Linear_5s_11s format.
TOFF_FALL
The TOFF_FALL command sets the time, in milliseconds, from the end of the turn-off delay time until the output volt-
age is commanded to zero. It is the ramp time of the V
set to high impedance state.
DAC. When the V
DAC is zero, the PWM output will be
OUT
OUT
The part will maintain the mode of operation programmed. For defined TOFF_FALL times, the user should set the part
to continuous conduction mode. Loading the max value indicates the part will ramp down at the slowest possible rate.
The minimum supported fall time is 0.25ms. A value less than 0.25ms will result in a 0.25ms ramp. The maximum
fall time is 1.3 seconds. The number of steps in TOFF_FALL is equal to TOFF_FALL (in ms)/0.1ms with an uncertainty
of 0.1ms.
In discontinuous conduction mode, the controller will not draw current from the load and the fall time will be set by
the output capacitance and load current.
This command has two data bytes and is formatted in Linear_5s_11s format.
Rev 0
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LTC7132
PMBus COMMAND DETAILS
TOFF_MAX_WARN_LIMIT
The TOFF_MAX_WARN_LIMIT command sets the value, in milliseconds, on how long the output voltage exceeds
12.5% of the programmed voltage before a warning is asserted. The output is considered off when the V
voltage
OUT
is less than 12.5% of the programmed VOUT_COMMAND value. The calculation begins after TOFF_FALL is complete.
A data value of 0ms means that there is no limit and that the output voltage exceeds 12.5% of the programmed voltage
indefinitely. Other than 0, values from 120ms to 524 seconds are valid.
This command has two data bytes and is formatted in Linear_5s_11s format.
Precondition for Restart
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
0xDC Minimum time the RUN pin is held
low by the LTC7132.
TYPE
PAGED
FORMAT
UNITS
NVM
MFR_RESTART_ DELAY
R/W Word
Y
L11
ms
Y
500
0xFBE8
MFR_RESTART_DELAY
This command specifies the minimum RUN off time in milliseconds. This device will pull the RUN pin low for this length
of time once a falling edge of RUN has been detected. The minimum recommended value is 136ms.
Note: The restart delay is different than the retry delay. The restart delay pulls RUN low for the specified time, after
which a standard start-up sequence is initiated. The minimum restart delay should be equal to TOFF_DELAY + TOFF_
FALL + 136ms. Valid values are from 136ms to 65.52 seconds in 16ms increments. To assure a minimum off time,
set the MFR_RESTART_DELAY 16ms longer than the desired time. The output rail can be off longer than the MFR_
RESTART_DELAY after the RUN pin is pulled high if the output decay bit 0 is enabled in MFR_CHAN_CONFIG and the
output takes a long time to decay below 12.5% of the programmed value.
This command has two data bytes and is formatted in Linear_5s_11s format.
FAULT RESPONSE
Fault Responses All Faults
DATA
FORMAT
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED
UNITS
NVM
MFR_RETRY_ DELAY
0xDB
Retry interval during FAULT retry R/W Word
mode.
Y
L11
ms
Y
350
0xFABC
MFR_RETRY_DELAY
This command sets the time in milliseconds between retries if the fault response is to retry the controller at specified
intervals. This command value is used for all fault responses that require retry. The retry time starts once the fault has
been detected by the offending channel. Valid values are from 120ms to 83.88 seconds in 10µs increments.
Note: The retry delay time is determined by the longer of the MFR_RETRY_DELAY command or the time required
for the regulated output to decay below 12.5% of the programmed value. If the natural decay time of the output is
too long, it is possible to remove the voltage requirement of the MFR_RETRY_DELAY command by asserting bit 0 of
MFR_CHAN_CONFIG.
This command has two data bytes and is formatted in Linear_5s_11s format.
Rev 0
86
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LTC7132
PMBus COMMAND DETAILS
Fault Responses Input Voltage
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS
NVM
VIN_OV_FAULT_RESPONSE
0x56
Action to be taken by the device when an R/W Byte
input supply overvoltage fault is detected.
Y
Reg
Y
0x80
VIN_OV_FAULT_RESPONSE
The VIN_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an input over-
voltage fault. The data byte is in the format given in Table 11.
The device also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Set the INPUT bit in the upper byte of the STATUS_WORD
• Sets the VIN Overvoltage Fault bit in the STATUS_INPUT command, and
• Notifies the host by asserting ALERT pin, unless masked
This command has one data byte.
Fault Responses Output Voltage
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS
NVM
VOUT_OV_FAULT_RESPONSE
0x41
0x45
0x63
Action to be taken by the device when an R/W Byte
output overvoltage fault is detected.
Y
Y
Y
Reg
Reg
Reg
Y
0xB8
0xB8
0xB8
VOUT_UV_FAULT_RESPONSE
Action to be taken by the device when an R/W Byte
output undervoltage fault is detected.
Y
Y
TON_MAX_FAULT_
RESPONSE
Action to be taken by the device when a
TON_MAX_FAULT event is detected.
R/W Byte
VOUT_OV_FAULT_RESPONSE
The VOUT_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an output
overvoltage fault. The data byte is in the format given in Table 7.
The device also:
• Sets the VOUT_OV bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT Overvoltage Fault bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked
The only values recognized for this command are:
0x00–Part performs OV pull down only, or OV_PULLDOWN.
0x80–The device shuts down (disables the output) and the unit does not attempt to retry. (PMBus, Part II, Section 10.7).
Rev 0
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PMBus COMMAND DETAILS
0xB8–The device shuts down (disables the output) and device attempts to retry continuously, without limitation, until
it is commanded OFF (by the RUN pin or OPERATION command or both), bias power is removed, or another fault
condition causes the unit to shut down.
0x4n The device shuts down and the unit does not attempt to retry. The output remains disabled until the part is com-
manded OFF then ON or the RUN pin is asserted low then high or RESET through the command or removal of VIN.
The OV fault must remain active for a period of n • 10µs, where n is a value from 0 to 7.
0x78+n The device shuts down and the unit attempts to retry continuously until either the fault condition is cleared
or the part is commanded OFF then ON or the RUN pin is asserted low then high or RESET through the command or
removal of VIN. The OV fault must remain active for a period of n • 10µs, where n is a value from 0 to 7.
Any other value will result in a CML fault and the write will be ignored.
This command has one data byte.
Table 7. VOUT_OV_FAULT_RESPONSE Data Byte Contents
BITS DESCRIPTION
VALUE MEANING
7:6 Response
00
Part performs OV pull down only or OV_PULLDOWN
(i.e., turns off the top MOSFET and turns on lower MOSFET while
is > VOUT_OV_FAULT).
For all values of bits [7:6], the LTC7132:
V
OUT
• Sets the corresponding fault bit in the status commands and
01
The PMBus device continues operation for the delay time specified
by bits [2:0] and the delay time unit specified for that particular
fault. If the fault condition is still present at the end of the delay
time, the unit responds as programmed in the Retry Setting
(bits [5:3]).
• Notifies the host by asserting ALERT pin, unless masked.
The fault bit, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command.
10
11
The device shuts down immediately (disables the output) and
responds according to the retry setting in bits [5:3].
• The output is commanded through the RUN pin, the OPERATION
command, or the combined action of the RUN pin and
OPERATION command, to turn off and then to turn back on, or
Not supported. Writing this value will generate a CML fault.
• Bias power is removed and reapplied to the LTC7132.
5:3 Retry Setting
000 The unit does not attempt to restart. The output remains disabled
until the fault is cleared until the device is commanded OFF bias
power is removed.
111 The PMBus device attempts to restart continuously, without
limitation, until it is commanded OFF (by the RUN pin or
OPERATION command or both), bias power is removed, or another
fault condition causes the unit to shut down without retry. Note: The
retry interval is set by the MFR_RETRY_DELAY command.
2:0 Delay Time
000-111 The delay time in 10µs increments. This delay time determines how
long the controller continues operating after a fault is detected. Only
valid for deglitched off state.
VOUT_UV_FAULT_RESPONSE
The VOUT_UV_FAULT_RESPONSE command instructs the device on what action to take in response to an output
undervoltage fault. The data byte is in the format given in Table 8.
The device also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT undervoltage fault bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked
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LTC7132
PMBus COMMAND DETAILS
The UV fault and warn are masked until the following criteria are achieved:
1) The TON_MAX_FAULT_LIMIT has been reached
2) The TON_DELAY sequence has completed
3) The TON_RISE sequence has completed
4) The VOUT_UV_FAULT_LIMIT threshold has been reached
5) The IOUT_OC_FAULT_LIMIT is not present
The UV fault and warn are masked whenever the channel is not active.
The UV fault and warn are masked during TON_RISE and TOFF_FALL sequencing.
This command has one data byte.
Table 8. VOUT_UV_FAULT_RESPONSE Data Byte Contents
BITS DESCRIPTION
VALUE MEANING
7:6
Response
00
The PMBus device continues operation without interruption.
(Ignores the fault functionally)
For all values of bits [7:6], the LTC7132:
• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin, unless masked.
01
The PMBus device continues operation for the delay time specified
by bits [2:0] and the delay time unit specified for that particular
fault. If the fault condition is still present at the end of the delay
time, the unit responds as programmed in the Retry Setting (bits
[5:3]).
The fault bit, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command.
10
11
The device shuts down (disables the output) and responds
according to the retry setting in bits [5:3].
• The output is commanded through the RUN pin, the OPERATION
command, or the combined action of the RUN pin and
OPERATION command, to turn off and then to turn back on, or
Not supported. Writing this value will generate a CML fault.
• The device receives a RESTORE_USER_ALL command.
• The device receives a MFR_RESET command.
• The device supply power is cycled.
Retry Setting
5:3
2:0
000 The unit does not attempt to restart. The output remains disabled
until the fault is cleared until the device is commanded OFF bias
power is removed.
111 The PMBus device attempts to restart continuously,
without limitation, until it is commanded OFF (by the RUN
pin or OPERATION command or both), bias power is
removed, or another fault condition causes the unit to shut
down without retry. Note: The retry interval is set by the
MFR_RETRY_DELAY command.
Delay Time
000- The delay time in 10µs increments. This delay time determines
111 how long the controller continues operating after a fault is
detected. Only valid for deglitched off state.
Rev 0
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LTC7132
PMBus COMMAND DETAILS
TON_MAX_FAULT_RESPONSE
The TON_MAX_FAULT_RESPONSE command instructs the device on what action to take in response to a TON_MAX
fault. The data byte is in the format given in Table 11.
The device also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the TON_MAX_FAULT bit in the STATUS_VOUT command, and
• Notifies the host by asserting ALERT pin, unless masked
A value of 0 disables the TON_MAX_FAULT_RESPONSE. It is not recommended to use 0.
Note: The PWM channel remains in discontinues mode until the TON_MAX_FAULT_LIMIT has been exceeded.
This command has one data byte.
Fault Responses Output Current
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
IOUT_OC_FAULT_RESPONSE
0x47
Action to be taken by the device when an R/W Byte
output overcurrent fault is detected.
Y
Reg
Y
0x00
IOUT_OC_FAULT_RESPONSE
The IOUT_OC_FAULT_RESPONSE command instructs the device on what action to take in response to an output
overcurrent fault. The data byte is in the format given in Table 9.
The device also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the IOUT_OC bit in the STATUS_BYTE
• Sets the IOUT bit in the STATUS_WORD
• Sets the IOUT Overcurrent Fault bit in the STATUS_IOUT command, and
• Notifies the host by asserting ALERT pin, unless masked
This command has one data byte.
Rev 0
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LTC7132
PMBus COMMAND DETAILS
Table 9. IOUT_OC_FAULT_RESPONSE Data Byte Contents
BITS DESCRIPTION
VALUE MEANING
7:6
Response
00
The LTC7132 continues to operate indefinitely while maintaining
the output current at the value set by IOUT_OC_FAULT_LIMIT
without regard to the output voltage (known as constant-
current or brick-wall limiting).
For all values of bits [7:6], the LTC7132:
• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin, unless masked.
01
10
Not supported.
The fault bit, once set, is cleared only when one or more of the
following events occurs:
The LTC7132 continues to operate, maintaining the output
current at the value set by IOUT_OC_FAULT_LIMIT without
regard to the output voltage, for the delay time set by bits [2:0].
If the device is still operating in current limit at the end of the
delay time, the device responds as programmed by the Retry
Setting in bits [5:3].
• The device receives a CLEAR_FAULTS command.
• The output is commanded through the RUN pin, the OPERATION
command, or the combined action of the RUN pin and
OPERATION command, to turn off and then to turn back on, or
11
The LTC7132 shuts down immediately and responds as
programmed by the Retry Setting in bits [5:3].
• The device receives a RESTORE_USER_ALL command.
• The device receives a MFR_RESET command.
• The device supply power is cycled.
Retry Setting
5:3
2:0
000
111
The unit does not attempt to restart. The output remains
disabled until the fault is cleared by cycling the RUN pin or
removing bias power.
The device attempts to restart continuously, without limitation,
until it is commanded OFF (by the RUN pin or OPERATION
command or both), bias power is removed, or another fault
condition causes the unit to shut down. Note: The retry interval
is set by the MFR_RETRY_DELAY command.
Delay Time
000-111 The number of delay time units in 16ms increments. This
delay time is used to determine the amount of time a unit is
to continue operating after a fault is detected before shutting
down. Only valid for deglitched off response.
Fault Responses IC Temperature
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS
NVM
MFR_OT_FAULT_RESPONSE
0xD6
Action to be taken by the device when an
internal overtemperature fault is detected.
R Byte
N
Reg
0xC0
MFR_OT_FAULT_RESPONSE
The MFR_OT_FAULT_RESPONSE command byte instructs the device on what action to take in response to an internal
overtemperature fault. The data byte is in the format given in Table 10.
The LTC7132 also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the MFR bit in the STATUS_WORD, and
• Sets the Overtemperature Fault bit in the STATUS_MFR_SPECIFIC command
• Notifies the host by asserting ALERT pin, unless masked
This command has one data byte.
Rev 0
91
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LTC7132
PMBus COMMAND DETAILS
Table 10 . Data Byte Contents MFR_OT_FAULT_RESPONSE
BITS DESCRIPTION
VALUE MEANING
7:6
Response
00
01
10
Not supported. Writing this value will generate a CML fault.
For all values of bits [7:6], the LTC7132:
• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin, unless masked.
Not supported. Writing this value will generate a CML fault
The device shuts down immediately (disables the output) and
responds according to the retry setting in bits [5:3].
11
The device’s output is disabled while the fault is present.
Operation resumes and the output is enabled when the fault
condition no longer exists.
The fault bit, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command.
• The output is commanded through the RUN pin, the OPERATION
command, or the combined action of the RUN pin and
OPERATION command, to turn off and then to turn back on, or
• Bias power is removed and reapplied to the LTC7132.
Retry Setting
5:3
2:0
000
The unit does not attempt to restart. The output remains
disabled until the fault is cleared.
001-111 Not supported. Writing this value will generate CML fault.
Delay Time
XXX
Not supported. Value ignored
Fault Responses External Temperature
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS
NVM
OT_FAULT_ RESPONSE
0x50
Action to be taken by the device when an
external overtemperature fault is detected,
R/W Byte
Y
Reg
Reg
Y
0xB8
UT_FAULT_ RESPONSE
0x54
Action to be taken by the device when an
external undertemperature fault is detected.
R/W Byte
Y
Y
0xB8
OT_FAULT_RESPONSE
The OT_FAULT_RESPONSE command instructs the device on what action to take in response to an external overtem-
perature fault on the external temp sensors. The data byte is in the format given in Table 11.
The device also:
• Sets the TEMPERATURE bit in the STATUS_BYTE
• Sets the Overtemperature Fault bit in the STATUS_TEMPERATURE command, and
• Notifies the host by asserting ALERT pin, unless masked
This command has one data byte.
UT_FAULT_RESPONSE
The UT_FAULT_RESPONSE command instructs the device on what action to take in response to an external under-
temperature fault on the external temp sensors. The data byte is in the format given in Table 11.
The device also:
• Sets the TEMPERATURE bit in the STATUS_BYTE
• Sets the Undertemperature Fault bit in the STATUS_TEMPERATURE command, and
• Notifies the host by asserting ALERT pin, unless masked
Rev 0
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LTC7132
PMBus COMMAND DETAILS
This condition is detected by the ADC so the response time may be up to t
.
CONVERT
This command has one data byte.
Table 11. Data Byte Contents: TON_MAX_FAULT_RESPONSE, VIN_OV_FAULT_RESPONSE,
OT_FAULT_RESPONSE, UT_FAULT_RESPONSE
BITS DESCRIPTION
VALUE MEANING
7:6
Response
00
01
10
The PMBus device continues operation without interruption.
Not supported. Writing this value will generate a CML fault.
For all values of bits [7:6], the LTC7132:
• Sets the corresponding fault bit in the status commands, and
• Notifies the host by asserting ALERT pin, unless masked.
The device shuts down immediately (disables the output) and
responds according to the retry setting in bits [5:3].
11
Not supported. Writing this value will generate a CML fault.
The fault bit, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command.
• The output is commanded through the RUN pin, the OPERATION
command, or the combined action of the RUN pin and
OPERATION command, to turn off and then to turn back on, or
• The device receives a RESTORE_USER_ALL command.
• The device receives a MFR_RESET command.
• The device supply power is cycled.
Retry Setting
5:3
2:0
000
111
The unit does not attempt to restart. The output remains
disabled until the fault is cleared until the device is commanded
OFF bias power is removed.
The PMBus device attempts to restart continuously, without
limitation, until it is commanded OFF (by the RUN pin or
OPERATION command or both), bias power is removed, or
another fault condition causes the unit to shut down without
retry. Note: The retry interval is set by the MFR_RETRY_DELAY
command.
Delay Time
XXX
Not supported. Values ignored
FAULT SHARING
Fault Sharing Propagation
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
0xD2 Configuration that determines which faults
are propagated to the FAULT pins.
TYPE
PAGED FORMAT UNITS
NVM
MFR_FAULT_
PROPAGATE
R/W Word
Y
Reg
Y
0x6993
MFR_FAULT_PROPAGATE
The MFR_FAULT_PROPAGATE command enables the faults that can cause the FAULTn pin to assert low. The com-
mand is formatted as shown in Table 12. Faults can only be propagated to the FAULTn pin if they are programmed to
respond to faults.
This command has two data bytes.
Rev 0
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LTC7132
PMBus COMMAND DETAILS
Table 12. FAULTn Propagate Fault Configuration
The FAULT0 and FAULT1 pins are designed to provide electrical notification of selected events to the user. Some of these events are common to both output
channels. Others are specific to an output channel. They can also be used to share faults between channels.
BIT(S)
SYMBOL
OPERATION
B[15]
VOUT disabled while not decayed.
This is used in a PolyPhase configuration when bit 0 of the MFR_CHAN_CONFIG_LTC7132 is a
zero. If the channel is turned off, by toggling the RUN pin or commanding the part OFF, and then
the RUN is reasserted or the part is commanded back on before the output has decayed, VOUT
will not restart until the 12.5% decay is honored. The FAULT pin is asserted during this condition
if bit 15 is asserted.
B[14]
b[13]
Mfr_fault_propagate_short_CMD_cycle 0: No action
1: Asserts low if commanded off then on before the output has sequenced off. Re-asserts high
after sequence off.
t
OFF(MIN)
Mfr_fault_propagate_ton_max_fault
0: No action if a TON_MAX_FAULT fault is asserted
1: Associated output will be asserted low if a TON_MAX_FAULT fault is asserted
FAULT0 is associated with page 0 TON_MAX_FAULT faults
FAULT1 is associated with page 1 TON_MAX_FAULT faults
b[12]
b[11]
Reserved
Mfr_fault0_propagate_int_ot,
Mfr_fault1_propagate_int_ot
Reserved
0: No action if the MFR_OT_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the MFR_OT_FAULT_LIMIT fault is asserted
b[10]
b[9]
Reserved
b[8]
Mfr_fault0_propagate_ut,
Mfr_fault1_propagate_ut
0: No action if the UT_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the UT_FAULT_LIMIT fault is asserted
FAULT0 is associated with page 0 UT faults
FAULT1 is associated with page 1 UT faults
b[7]
Mfr_fault0_propagate_ot,
Mfr_fault1_propagate_ot
0: No action if the OT_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the OT_FAULT_LIMIT fault is asserted
FAULT0 is associated with page 0 OT faults
FAULT1 is associated with page 1 OT faults
b[6]
b[5]
b[4]
Reserved
Reserved
Mfr_fault0_propagate_input_ov,
Mfr_fault1_propagate_input_ov
Reserved
0: No action if the VIN_OV_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the VIN_OV_FAULT_LIMIT fault is asserted
b[3]
b[2]
Mfr_fault0_propagate_iout_oc,
Mfr_fault1_propagate_iout_oc
0: No action if the IOUT_OC_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the IOUT_OC_FAULT_LIMIT fault is asserted
FAULT0 is associated with page 0 OC faults
FAULT1 is associated with page 1 OC faults
b[1]
b[0]
Mfr_fault0_propagate_vout_uv,
Mfr_fault1_propagate_vout_uv
0: No action if the VOUT_UV_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the VOUT_UV_FAULT_LIMIT fault is asserted
FAULT0 is associated with page 0 UV faults
FAULT1 is associated with page 1 UV faults
Mfr_fault0_propagate_vout_ov,
Mfr_fault1_propagate_vout_ov
0: No action if the VOUT_OV_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the VOUT_OV_FAULT_LIMIT fault is asserted
FAULT0 is associated with page 0 OV faults
FAULT1 is associated with page 1 OV faults
Rev 0
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LTC7132
PMBus COMMAND DETAILS
Fault Sharing Response
DATA
DEFAULT
COMMAND NAME
CMD CODE DESCRIPTION
0xD5 Action to be taken by the device when the
FAULT pin is asserted low.
TYPE
R/W Byte
PAGED FORMAT UNITS
Y
NVM
Y
VALUE
MFR_FAULT_RESPONSE
Reg
0xC0
MFR_FAULT_RESPONSE
The MFR_FAULT_RESPONSE command instructs the device on what action to take in response to the FAULTn pin
being pulled low by an external source.
Supported Values:
VALUE
0xC0
MEANING
FAULT_INHIBIT The LTC7132 will three-state the output in response to the FAULT pin pulled low.
FAULT_IGNORE The LTC7132 continues operation without interruption.
0x00
The device also:
•
•
•
Sets the MFR Bit in the STATUS_WORD.
Sets Bit 0 in the STATUS_MFR_SPECIFIC Command to Indicate FAULTn Is Being Pulled Low
Notifies the Host by Asserting ALERT, Unless Masked
This command has one data byte.
SCRATCHPAD
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS
NVM
USER_DATA_00
0xB0
OEM reserved. Typically used for part
serialization.
R/W Word
N
Reg
Y
NA
USER_DATA_01
USER_DATA_02
0xB1
0xB2
Manufacturer reserved for LTpowerPlay.
R/W Word
R/W Word
Y
N
Reg
Reg
Y
Y
NA
NA
OEM reserved. Typically used for part
serialization.
USER_DATA_03
USER_DATA_04
0xB3
0xB4
A NVM word available for the user.
A NVM word available for the user.
R/W Word
R/W Word
Y
N
Reg
Reg
Y
Y
0x0000
0x0000
USER_DATA_00 through USER_DATA_04
These commands are non-volatile memory locations for customer storage. The customer has the option to write any
value to the USER_DATA_nn at any time. However, the LTpowerPlay software and contract manufacturers use some of
these commands for inventory control. Modifying the reserved USER_DATA_nn commands may lead to undesirable
inventory control and incompatibility with these products.
These commands have 2 data bytes and are in register format.
Rev 0
95
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LTC7132
PMBus COMMAND DETAILS
IDENTIFICATION
DATA
FORMAT UNITS
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED
NVM
PMBus_REVISION
0x98
PMBus revision supported by this device.
R Byte
N
Reg
Reg
FS
0x22
Current revision is 1.2.
CAPABILITY
0x19
Summary of PMBus optional communication
protocols supported by this device.
R Byte
N
0xB0
MFR_ID
0x99
0x9A
0xE7
The manufacturer ID of the LTC7132 in ASCII.
Manufacturer part number in ASCII.
R String
R String
R Word
N
N
N
ASC
ASC
Reg
LTC
MFR_MODEL
MFR_SPECIAL_ID
LTC7132
0x4C0X
Manufacturer code representing the LTC7132.
PMBus_REVISION
The PMBUS_REVISION command indicates the revision of the PMBus to which the device is compliant. The LTC7132
is PMBus Version 1.2 compliant in both Part I and Part II.
This read-only command has one data byte.
CAPABILITY
This command provides a way for a host system to determine some key capabilities of a PMBus device.
The LTC7132 supports packet error checking, 400kHz bus speeds, and ALERT pin.
This read-only command has one data byte.
MFR_ID
The MFR_ID command indicates the manufacturer ID of the LTC7132 using ASCII characters.
This read-only command is in block format.
MFR_MODEL
The MFR_MODEL command indicates the manufacturer’s part number of the LTC7132 using ASCII characters.
This read-only command is in block format.
MFR_SPECIAL_ID
The 16-bit word representing the part name and revision. 0x4C denotes the part is an LTC7132, XX is adjustable by
the manufacturer.
This read-only command has two data bytes.
Rev 0
96
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LTC7132
PMBus COMMAND DETAILS
FAULT WARNING AND STATUS
DEFAULT
COMMAND NAME
CLEAR_FAULTS
SMBALERT_MASK
CMD CODE DESCRIPTION
TYPE
PAGED
N
Y
FORMAT UNITS
NVM
VALUE
0x03
0x1B
Clear any fault bits that have been set. Send Byte
Mask activity.
NA
See CMD
Details
Block R/W
Reg
Y
MFR_CLEAR_PEAKS
STATUS_BYTE
0xE3
0x78
Clears all peak values.
One byte summary of the unit’s fault
condition.
Two byte summary of the unit’s fault
condition.
Output voltage fault and warning
status.
Output current fault and warning
status.
Input supply fault and warning status.
External temperature fault and warning R/W Byte
status for READ_TEMPERATURE_1.
Send Byte
R/W Byte
Y
Y
NA
NA
Reg
Reg
Reg
Reg
STATUS_WORD
STATUS_VOUT
STATUS_IOUT
0x79
0x7A
0x7B
R/W Word
R/W Byte
R/W Byte
R/W Byte
Y
Y
Y
NA
NA
NA
STATUS_INPUT
STATUS_ TEMPERATURE
0x7C
0x7D
N
Y
Reg
Reg
NA
NA
STATUS_CML
0x7E
0x80
Communication and memory fault and R/W Byte
warning status.
N
Y
Reg
Reg
NA
NA
STATUS_MFR_ SPECIFIC
Manufacturer specific fault and state
information.
R/W Byte
MFR_PADS
MFR_COMMON
0xE5
0xEF
Digital status of the I/O pads.
Manufacturer status bits that are
common across multiple ADI chips.
R Word
R Byte
N
N
Reg
Reg
NA
NA
CLEAR_FAULTS
The CLEAR_FAULTS command is used to clear any fault bits that have been set. This command clears all bits in all
status commands simultaneously. At the same time, the device negates (clears, releases) its ALERT pin signal output
if the device is asserting the ALERT pin signal. If the fault is still present when the bit is cleared, the fault bit will remain
set and the host notified by asserting the ALERT pin low. CLEAR_FAULTS can take up to 10µs to process. If a fault
occurs within that time frame it may be cleared before the status register is set.
This write-only command has no data bytes.
The CLEAR_FAULTS does not cause a unit that has latched off for a fault condition to restart. Units that have shut
down for a fault condition are restarted when:
• The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin
and OPERATION command, to turn off and then to turn back on, or
• MFR_RESET command is issued.
• Bias power is removed and reapplied to the integrated circuit
SMBALERT_MASK
The SMBALERT_MASK command can be used to prevent a particular status bit or bits from asserting ALERT as they
are asserted.
Figure 52 shows an example of the Write Word format used to set an ALERT mask, in this case without PEC. The bits in
the mask byte align with bits in the specified status register. For example, if the STATUS_TEMPERATURE command code
is sent in the first data byte, and the mask byte contains 0x40, then a subsequent External Overtemperature Warning
Rev 0
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LTC7132
PMBus COMMAND DETAILS
would still set bit 6 of STATUS_TEMPERATURE but not assert ALERT. All other supported STATUS_TEMPERATURE
bits would continue to assert ALERT if set.
Figure 53 shows an example of the Block Write – Block Read Process Call protocol used to read back the present state
of any supported status register, again without PEC.
SMBALERT_MASK cannot be applied to STATUS_BYTE, STATUS_WORD, MFR_COMMON or MFR_PADS_LTC7132.
Factory default masking for applicable status registers is shown below. Providing an unsupported command code to
SMBALERT_MASK will generate a CML for Invalid/Unsupported Data.
SMBALERT_MASK Default Setting: (Refer Also to Figure 2)
STATUS RESISTER
ALERT Mask Value MASKED BITS
STATUS_VOUT
0x00
0x00
0x00
0x00
0x00
0x11
None
STATUS_IOUT
None
STATUS_TEMPERATURE
STATUS_CML
None
None
STATUS_INPUT
None
STATUS_MFR_SPECIFIC
Bit 4 (internal PLL unlocked), bit 0 (FAULT pulled low by external device)
ꢁ
ꢓ
ꢁ
ꢁ
ꢔ
ꢁ
ꢔ
ꢁ
ꢔ
ꢁ
ꢁ
ꢂꢃꢄꢅꢆ
ꢄꢇꢇRꢆꢂꢂ
ꢂꢈꢉꢄꢃꢆRꢊꢋꢈꢄꢂꢌ
ꢍꢎꢈꢈꢄꢏꢇ ꢍꢎꢇꢆ
ꢂꢊꢄꢊꢐꢂꢋꢑ
ꢍꢎꢈꢈꢄꢏꢇ ꢍꢎꢇꢆ
ꢂ
ꢒ
ꢄ
ꢄ
ꢄ
ꢈꢄꢂꢌ ꢉꢕꢊꢆ
ꢄ
ꢀ
ꢓꢁꢖꢗ ꢘꢙꢖ
Figure 52. Example of Writing SMBALERT_MASK
ꢑ
ꢔ
ꢑ
ꢑ
ꢕ
ꢑ
ꢕ
ꢑ
ꢕ
ꢑ
ꢀꢁꢂꢃꢄ
ꢂꢅꢅRꢄꢀꢀ
ꢀꢆꢇꢂꢁꢄRꢈꢉꢆꢂꢀꢊ
ꢋꢌꢆꢆꢂꢍꢅ ꢋꢌꢅꢄ
ꢇꢁꢌꢋꢊ ꢋꢌꢎꢍꢈ
ꢏꢐ ꢑꢒ
ꢀꢈꢂꢈꢎꢀꢉꢖ
ꢋꢌꢆꢆꢂꢍꢅ ꢋꢌꢅꢄ
ꢀ
ꢓ
ꢂ
ꢂ
ꢂ
ꢂ
ꢗ
ꢑ
ꢔ
ꢑ
ꢑ
ꢕ
ꢑ
ꢕ
ꢑ
ꢑ
ꢀꢁꢂꢃꢄ
ꢂꢅꢅRꢄꢀꢀ
ꢇꢁꢌꢋꢊ ꢋꢌꢎꢍꢈ
ꢏꢐ ꢑꢒ
ꢀꢘ
R
ꢂ
ꢂ
ꢆꢂꢀꢊ ꢇꢟꢈꢄ
ꢍꢂ
ꢙ
ꢔꢑꢚꢛ ꢜꢝꢞ
Figure 53. Example of Reading SMBALERT_MASK
MFR_CLEAR_PEAKS
The MFR_CLEAR_PEAKS command clears the MFR_*_PEAK data values. A MFR_RESET command will also clear the
MFR_*_PEAK data values.
This write-only command has no data bytes.
STATUS_BYTE
The STATUS_BYTE command returns one byte of information with a summary of the most critical faults. This is the
lower byte of the status word.
Rev 0
98
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LTC7132
PMBus COMMAND DETAILS
STATUS_BYTE Message Contents:
BIT
7*
6
STATUS BIT NAME
MEANING
BUSY
OFF
A fault was declared because the LTC7132 was unable to respond.
This bit is set if the channel is not providing power to its output, regardless of the reason, including simply not
being enabled.
5
4
VOUT_OV
IOUT_OC
VIN_UV
An output overvoltage fault has occurred.
An output overcurrent fault has occurred.
Not supported (LTC7132 returns 0).
3
2
TEMPERATURE
CML
A temperature fault or warning has occurred.
A communications, memory or logic fault has occurred.
1
0*
NONE OF THE ABOVE A fault Not listed in bits[7:1] has occurred.
*ALERT can be asserted if either of these bits is set. They may be cleared by writing a 1 to their bit position in the STATUS_BYTE, in lieu of a CLEAR_
FAULTS command.
This command has one data byte.
STATUS_WORD
The STATUS_WORD command returns a two-byte summary of the channel's fault condition. The low byte of the
STATUS_WORD is the same as the STATUS_BYTE command.
STATUS_WORD High Byte Message Contents:
BIT
15
14
13
12
11
10
9
STATUS BIT NAME
MEANING
V
An output voltage fault or warning has occurred.
An output current fault or warning has occurred.
An input voltage fault or warning has occurred.
A fault or warning specific to the LTC7132 has occurred.
The POWER_GOOD state is false if this bit is set.
Not supported (LTC7132 returns 0).
OUT
OUT
I
INPUT
MFR_SPECIFIC
POWER_GOOD#
FANS
OTHER
Not supported (LTC7132 returns 0).
8
UNKNOWN
Not supported (LTC7132 returns 0).
If any of the bits in the upper byte are set, NONE_OF_THE_ABOVE is asserted.
This command has two data bytes.
STATUS_VOUT
The STATUS_VOUT command returns one byte of V
status information.
OUT
STATUS_VOUT Message Contents:
BIT
7
MEANING
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
overvoltage fault.
overvoltage warning.
undervoltage warning.
undervoltage fault.
max warning.
6
5
4
3
2
TON max fault.
1
TOFF max fault.
0
Not supported (LTC7132 returns 0).
Rev 0
99
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LTC7132
PMBus COMMAND DETAILS
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear
status by means other than using the CLEAR_FAULTS command.
Any supported fault bit in this command will initiate an ALERT event.
This command has one data byte.
STATUS_IOUT
The STATUS_IOUT command returns one byte of I
status information.
OUT
STATUS_IOUT Message Contents:
BIT
7
MEANING
overcurrent fault.
I
OUT
6
Not supported (LTC7132 returns 0).
I overcurrent warning.
OUT
5
4:0
Not supported (LTC7132 returns 0).
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear
status by means other than using the CLEAR_FAULTS command.
Any supported fault bit in this command will initiate an ALERT event. This command has one data byte.
STATUS_INPUT
The STATUS_INPUT command returns one byte of V (VINSNS) status information.
IN
STATUS_INPUT Message Contents:
BIT
7
MEANING
overvoltage fault.
V
IN
6
Not supported (LTC7132 returns 0).
V undervoltage warning.
IN
5
4
Not supported (LTC7132 returns 0).
3
Unit off for insufficient V .
IN
2
Not supported (LTC7132 returns 0).
1
I overcurrent warning.
IN
0
Not supported (LTC7132 returns 0).
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear
status by means other than using the CLEAR_FAULTS command.
Any supported fault bit in this command will initiate an ALERT event. Bit 3 of this command is not latched and will not
generate an ALERT even if it is set. This command has one data byte.
Rev 0
100
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LTC7132
PMBus COMMAND DETAILS
STATUS_TEMPERATURE
The STATUS_TEMPERATURE commands returns one byte with status information on temperature. This is a paged
command and is related to the respective READ_TEMPERATURE_1 value.
STATUS_TEMPERATURE Message Contents:
BIT
7
MEANING
External overtemperature fault.
External overtemperature warning.
Not supported (LTC7132 returns 0).
External undertemperature fault.
Not supported (LTC7132 returns 0).
6
5
4
3:0
.
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear
status by means other than using the CLEAR_FAULTS command.
This command has one data byte.
STATUS_CML
The STATUS_CML command returns one byte of status information on received commands, internal memory and logic.
STATUS_CML Message Contents:
BIT
7
MEANING
Invalid or unsupported command received.
Invalid or unsupported data received.
Packet error check failed.
6
5
4
Memory fault detected.
3
Processor fault detected.
2
Reserved (LTC7132 returns 0).
Other communication fault.
Other memory or logic fault.
1
0
If either bit 3 or bit 4 of this command is set, a serious and significant internal error has been detected. Continued
operation of the part is not recommended if these bits are continuously set.
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear
status by means other than using the CLEAR_FAULTS command.
Any supported fault bit in this command will initiate an ALERT event.
This command has one data byte.
Rev 0
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LTC7132
PMBus COMMAND DETAILS
STATUS_MFR_SPECIFIC
The STATUS_MFR_SPECIFIC commands returns one byte with the manufacturer specific status information.
The format for this byte is:
BIT MEANING
7
6
5
4
3
2
1
0
Internal Temperature Fault Limit Exceeded.
Internal Temperature Warn Limit Exceeded.
Factory Trim Area NVM CRC Fault.
PLL is Unlocked
Fault Log Present
V
DD33
UV or OV Fault
ShortCycle Event Detected
FAULT Pin Asserted Low by External Device
If any of these bits are set, the MFR bit in the STATUS_WORD will be set, and ALERT may be asserted.
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear
status by means other than using the CLEAR_FAULTS command. However, the fault log present bit can only be cleared
by issuing the MFR_FAULT_LOG_CLEAR command.
Any supported fault bit in this command will initiate an ALERT event.
This command has one data byte.
MFR_PADS
This command provides the user a means of directly reading the digital status of the I/O pins of the device. The bit
assignments of this command are as follows:
BIT ASSIGNED DIGITAL PIN
15
14
V
V
OV Fault
UV Fault
DD33
DD33
13 Reserved
12 Reserved
11 ADC Values Invalid, Occurs During Start-Up. May Occur Briefly on Current Measurement Channels During Normal Operation
10 SYNC clocked by external device (when LTC7132 configured to drive SYNC pin)
9
8
7
6
5
4
3
2
1
0
Channel 1 Power Good
Channel 0 Power Good
LTC7132 Driving RUN1 Low
LTC7132 Driving RUN0 Low
RUN1 Pin State
RUN0 Pin State
LTC7132 Driving FAULT1 Low
LTC7132 Driving FAULT0 Low
FAULT1 Pin State
FAULT0 Pin State
A 1 indicates the condition is true.
This read-only command has two data bytes.
Rev 0
102
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LTC7132
PMBus COMMAND DETAILS
MFR_COMMON
The MFR_COMMON command contains bits that are common to all ADI digital power and telemetry products.
BIT
7
MEANING
Chip Not Driving ALERT Low
LTC7132 Not Busy
Calculations Not Pending
LTC7132 Outputs Not in Transition
NVM Initialized
6
5
4
3
2
Reserved
1
SHARE_CLK Timeout
WP Pin Status
0
This read-only command has one data byte.
MFR_INFO
The MFR_INFO command contains additional status bits that are LTC7132-specific and may be common to multiple
ADI PSM products.
MFR_INFO Data Contents:
BIT
15:5
4
MEANING
Reserved.
EEPROM ECC status.
0: Corrections made in the EEPROM user space.
1: No corrections made in the EEPROM user space.
Reserved
3:0
EEPROM ECC status is updated after each RESTORE_USER_ALL or RESET command, a power-on reset or an EEPROM
bulk read operation. This read-only command has two data bytes.
Rev 0
103
For more information www.analog.com
LTC7132
PMBus COMMAND DETAILS
TELEMETRY
CMD
DEFAULT
VALUE
COMMAND NAME
READ_VIN
READ_IIN
READ_VOUT
READ_IOUT
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS
NVM
0x88 Measured input supply voltage.
0x89 Measured input supply current.
0x8B Measured output voltage.
0x8C Measured output current.
0x8D External diode junction temperature. This
is the value used for all temperature related
processing, including IOUT_CAL_GAIN.
R Word
R Word
R Word
R Word
R Word
N
N
Y
Y
Y
L11
L11
L16
L11
L11
V
A
V
A
C
NA
NA
NA
NA
NA
READ_TEMPERATURE_1
READ_TEMPERATURE_2
0x8E Internal junction temperature. Does not affect
any other commands.
R Word
N
L11
C
NA
READ_FREQUENCY
READ_POUT
READ_PIN
MFR_PIN_ACCURACY
MFR_IOUT_PEAK
0x95 Measured PWM switching frequency.
0x96 Calculated output power.
0x97 Calculated input power.
0xAC Returns the accuracy of the READ_PIN command R Byte
0xD7 Report the maximum measured value of
READ_IOUT since last MFR_CLEAR_PEAKS.
0xDD Maximum measured value of READ_VOUT
since last MFR_CLEAR_PEAKS.
0xDE Maximum measured value of READ_VIN since
last MFR_CLEAR_PEAKS.
R Word
R Word
R Word
Y
Y
N
N
Y
L11
L11
L11
Hz
W
W
%
A
NA
NA
NA
5.0%
NA
R Word
R Word
R Word
R Word
L11
L16
L11
L11
MFR_VOUT_PEAK
MFR_VIN_PEAK
Y
N
Y
V
V
C
NA
NA
NA
MFR_TEMPERATURE_1_PEAK 0xDF Maximum measured value of external
Temperature (READ_TEMPERATURE_1) since
last MFR_CLEAR_PEAKS.
MFR_READ_IIN_PEAK
0xE1 Maximum measured value of READ_IIN
command since last MFR_CLEAR_PEAKS.
R Word
N
L11
A
NA
MFR_READ_ICHIP
0xE4 Measured current used by the LTC7132.
R Word
R Word
N
N
L11
L11
A
C
NA
NA
MFR_TEMPERATURE_2_PEAK 0xF4 Peak internal die temperature since last
MFR_CLEAR_PEAKS.
MFR_ADC_CONTROL
0xD8 ADC telemetry parameter selected for repeated R/W Byte
fast ADC read back.
N
N
N
Reg
NA
NA
MFR_REAL_TIME
0xFB 48-bit share-clock counter value
R Block
CF
READ_VIN
The READ_VIN command returns the measured V pin voltage, in volts added to READ_ICHIP • MFR_RVIN. This
IN
compensates for the IR voltage drop across the V filter element due to the supply current of the LTC7132.
IN
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_VOUT
The READ_VOUT command returns the measured output voltage by the VOUT_MODE command.
This read-only command has two data bytes and is formatted in Linear_16u format.
READ_IIN
The READ_IIN command returns the input current, in Amperes, as measured across the input current sense resistor
(see also MFR_IIN_CAL_GAIN).
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
Rev 0
104
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LTC7132
PMBus COMMAND DETAILS
READ_IOUT
The READ_IOUT command returns the average output current in amperes. The IOUT value is a function of:
a) the differential voltage measured across the I
b) the IOUT_CAL_GAIN value
pins
SENSE
c) the MFR_IOUT_CAL_GAIN_TC value, and
d) READ_TEMPERATURE_1 value
e) The MFR_TEMP_1_GAIN and the MFR_TEMP_1_OFFSET
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_TEMPERATURE_1
The READ_TEMPERATURE_1 command returns the temperature, in degrees Celsius, of the external sense element.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_TEMPERATURE_2
The READ_TEMPERATURE_2 command returns the LTC7132’s die temperature, in degrees Celsius, of the internal
sense element.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_FREQUENCY
The READ_FREQUENCY command is a reading of the PWM switching frequency in kHz.
This read-only command has 2 data bytes and is formatted in Linear_5s_11s format.
READ_POUT
The READ_POUT command is a reading of the DC/DC converter output power in Watts. POUT is calculated based on
the most recent correlated output voltage and current reading.
This read-only command has 2 data bytes and is formatted in Linear_5s_11s format.
READ_PIN
The READ_PIN command is a reading of the DC/DC converter input power in Watts. PIN is calculated based on the
most recent input voltage and current reading.
This read-only command has 2 data bytes and is formatted in Linear_5s_11s format.
MFR_PIN_ACCURACY
The MFR_PIN_ACCURACY command returns the accuracy, in percent, of the value returned by the READ_PIN command.
There is one data byte. The value is 0.1% per bit which gives a range of 0.0% to 25.5%.
This read-only command has one data byte and is formatted as an unsigned integer.
Rev 0
105
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LTC7132
PMBus COMMAND DETAILS
MFR_IOUT_PEAK
The MFR_IOUT_PEAK command reports the highest current, in amperes, reported by the READ_IOUT measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
MFR_VOUT_PEAK
The MFR_VOUT_PEAK command reports the highest voltage, in volts, reported by the READ_VOUT measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_16u format.
MFR_VIN_PEAK
The MFR_VIN_PEAK command reports the highest voltage, in volts, reported by the READ_VIN measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
MFR_TEMPERATURE_1_PEAK
The MFR_TEMPERATURE_1_PEAK command reports the highest temperature, in degrees Celsius, reported by the
READ_TEMPERATURE_1 measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
MFR_READ_IIN_PEAK
The MFR_READ_IIN_PEAK command reports the highest current, in Amperes, reported by the READ_IIN measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This command has two data bytes and is formatted in Linear_5s_11s format.
MFR_READ_ICHIP
The MFR_READ_ICHIP command returns the measured input current, in Amperes, used by the LTC7132.
This command has two data bytes and is formatted in Linear_5s_11s format.
MFR_TEMPERATURE_2_PEAK
The MFR_TEMPERATURE_2_PEAK command reports the highest temperature, in degrees Celsius, reported by the
READ_TEMPERATURE_2 measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
MFR_ADC_CONTROL
The MFR_ADC_CONTROL command determines the ADC read back selection. A default value of 0 in the command runs
the standard telemetry loop with all parameters updated in a round robin fashion with a typical latency of t
.
CONVERT
The user can command a non-zero value to monitored a single parameter with an approximate update rate of 8ms.
Rev 0
106
For more information www.analog.com
LTC7132
PMBus COMMAND DETAILS
This command has a latency of up to 2 ADC conversions or approximately 16ms (external temperature conversions
may have a latency of up to 3 ADC conversion or approximately 24ms). It is recommended the part remain in standard
telemetry mode except for special cases where fast ADC updates of a single parameter is required. The part should be
commanded to monitor the desired parameter for a limited period of time (less then 1 second) then set the command
back to standard round robin mode. If this command is set to any value except standard round robin telemetry (0) all
warnings and faults associated with telemetry other than the selected parameter are effectively disabled and voltage
servoing is disabled. When round robin is reasserted, all warnings and faults and servo mode are re-enabled.
COMMANDED VALUE
TELEMETRY COMMAND NAME
DESCRIPTION
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
Reserved
Reserved
Reserved
Channel 1 external temperature
Reserved
Channel 1 measured output current
Channel 1 measured output voltage
Channel 0 external temperature
Reserved
Channel 0 measured output current
Channel 0 measured output voltage
Internal junction temperature
Measured input supply current
Measured supply current of the LTC7132
Measured input supply voltage
Standard ADC Round Robin Telemetry
READ_TEMPERATURE_1
READ_IOUT
READ_VOUT
READ_TEMPERATURE_1
READ_IOUT
READ_VOUT
READ_TEMPERATURE_2
READ_IIN
MFR_READ_ICHIP
READ_VIN
If a reserved command value is entered, the telemetry will default to Internal IC Temperature and issue a CML fault. CML
faults will continue to be issued by the LTC7132 until a valid command value is entered. The accuracy of the measured
input supply voltage is only guaranteed if the MFR_ADC_CONTROL command is set to standard round robin telemetry.
This write-only command has 1 data byte and is formatted in register format.
MFR_REAL_TIME
The MFR_REAL_TIME command is the real-time clock value of the device with a resolution of 200µs. The value is
synchronous to the share-clock. The format of the PMBus block read is as follows:
Format of the MFR_REAL_TIME
BYTE
BIT
DESCRIPTION
0
1
2
3
4
5
6
Length of the block read (fixed at 6)
LSB of the 48-bit real-time clock value
[7:0]
[15:8]
[23:16]
[31:24]
[39:32]
[47:40]
MSB of the 48-bit real-time clock value
This read-only command is in block format. The length will be 6. The value of this command is typically updated
every 25ms.
Rev 0
107
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LTC7132
PMBus COMMAND DETAILS
NVM MEMORY COMMANDS
Store/Restore
CMD
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED
FORMAT
UNITS
NVM
STORE_USER_ALL
0x15
0x16
0xF0
Store user operating memory to
EEPROM.
Send Byte
N
NA
NA
NA
RESTORE_USER_ALL
Restore user operating memory from Send Byte
EEPROM.
N
N
MFR_COMPARE_USER_ALL
Compares current command contents Send Byte
with NVM.
STORE_USER_ALL
The STORE_USER_ALL command instructs the PMBus device to copy the non-volatile user contents of the Operating
Memory to the matching locations in the non-volatile User NVM memory.
Executing this command if the die temperature exceeds 85°C or is below 0°C is not recommended and the data reten-
tion of 10 years cannot be guaranteed. If the die temperature exceeds 130°C, the STORE_USER_ALL command is
disabled. The command is re-enabled when the IC temperature drops below 125°C.
Communication with the LTC7132 and programming of the NVM can be initiated when EXTV or VDD33 is available
CC
and VIN is not applied. To enable the part in this state, using global address 0x5B write MFR_EE_UNLOCK to 0x2B
followed by 0xC4. The LTC7132 will now communicate normally, and the project file can be updated. To write the
updated project file to the NVM issue a STORE_USER_ALL command. When VIN is applied, a MFR_RESET must be
issued to allow the PWM to be enabled and valid ADCs to be read.
This write-only command has no data bytes.
RESTORE_USER_ALL
The RESTORE_USER_ALL command instructs the LTC7132 to copy the contents of the non-volatile User memory to
the matching locations in the Operating Memory. The values in the Operating Memory are overwritten by the value
retrieved from the User commands. The LTC7132 ensures both channels are off, loads the operating memory from
the internal EEPROM, clears all faults, reads the resistor configuration pins, and then performs a soft-start of both
PWM channels if applicable.
STORE_USER_ALL, MFR_COMPARE_USER_ALL and RESTORE_USER_ALL commands are disabled if the die exceeds
130°C and are not re-enabled until the die temperature drops below 125°C.
This write-only command has no data bytes.
MFR_COMPARE_USER_ALL
The MFR_COMPARE_USER_ALL command instructs the PMBus device to compare current command contents with
what is stored in non-volatile memory. If the compare operation detects differences, a CML bit 0 fault will be generated.
This write-only command has no data bytes.
Rev 0
108
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LTC7132
PMBus COMMAND DETAILS
Fault Logging
DATA
PAGED FORMAT UNITS NVM
DEFAULT
VALUE
NA
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
MFR_FAULT_LOG
0xEE
0xEA
Fault log data bytes.
R Block
N
N
CF
Y
MFR_FAULT_LOG_ STORE
Command a transfer of the fault log from RAM Send Byte
to EEPROM.
NA
MFR_FAULT_LOG_CLEAR
0xEC
Initialize the EEPROM block reserved for fault
logging.
Send Byte
N
NA
MFR_FAULT_LOG
The MFR_FAULT_LOG command allows the user to read the contents of the FAULT_LOG after the first fault occur-
rence since the last MFR_FAULT_LOG_CLEAR command was written. The contents of this command are stored in
non-volatile memory, and are cleared by the MFR_FAULT_LOG_CLEAR command. The length and content of this
command are listed in Table 13. If the user accesses the MFR_FAULT_LOG command and no fault log is present, the
command will return a data length of 0. If a fault log is present, the MFR_FAULT_LOG will return a block of data 147
bytes long. If a fault occurs within the first second of applying power, some of the earlier pages in the fault log may
not contain valid data.
NOTE: The approximate transfer time for this command is 3.4ms using a 400kHz clock.
This read-only command is in block format.
MFR_FAULT_LOG_STORE
The MFR_FAULT_LOG_STORE command forces the fault log operation to be written to NVM just as if a fault event
occurred. This command will set bit 3 of the STATUS_MFR_SPECIFIC fault if bit 7 “Enable Fault Logging” is set in
the MFR_CONFIG_ALL command.
If the die temperature exceeds 130°C, the MFR_FAULT_LOG_STORE command is disabled until the IC temperature
drops below 125°C.
This write-only command has no data bytes.
Table 13. Fault Logging
This table outlines the format of the block data from a read block data of the MFR_FAULT_LOG command.
Data Format Definitions
LIN 11 = PMBus = Rev 1.2, Part 2, section 7.1
LIN 16 = PMBus Rev 1.2, Part 2, section 8. Mantissa portion only
BYTE = 8 bits interpreted per definition of this command
DATA
FORMAT BYTE NUM BLOCK READ COMMAND
DATA
BITS
Block Length
BYTE
147
The MFR_FAULT_LOG command is a fixed length of 147 bytes
The block length will be zero if a data log event has not been captured
HEADER INFORMATION
Fault Log Preface
[7:0]
[7:0]
[15:8]
[7:0]
[7:0]
ASC
Reg
Reg
0
1
2
3
4
Returns LTxx beginning at byte 0 if a partial or complete fault log exists.
Word xx is a factory identifier that may vary part to part.
Fault Source
Refer to Table 13a.
Rev 0
109
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LTC7132
PMBus COMMAND DETAILS
MFR_REAL_TIME
[7:0]
[15:8]
Reg
5
6
48 bit share-clock counter value when fault occurred (200µs resolution).
[23:16]
[31:24]
[39:32]
[47:40]
[15:8]
7
8
9
10
11
MFR_VOUT_PEAK (PAGE 0)
MFR_VOUT_PEAK (PAGE 1)
MFR_IOUT_PEAK (PAGE 0)
MFR_IOUT_PEAK (PAGE 1)
L16
L16
L11
L11
Peak READ_VOUT on Channel 0 since last power-on or CLEAR_PEAKS
command.
[7:0]
[15:8]
12
13
Peak READ_VOUT on Channel 1 since last power-on or CLEAR_PEAKS
command.
[7:0]
[15:8]
14
15
Peak READ_IOUT on Channel 0 since last power-on or CLEAR_PEAKS
command.
[7:0]
[15:8]
16
17
Peak READ_IOUT on Channel 1 since last power-on or CLEAR_PEAKS
command.
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
18
19
20
21
22
23
24
25
26
MFR_VIN_PEAK
L11
L11
L11
L11
Peak READ_VIN since last power-on or CLEAR_PEAKS command.
External temperature sensor 0 during last event.
READ_TEMPERATURE1 (PAGE 0)
READ_TEMPERATURE1 (PAGE 1)
READ_TEMPERATURE2
External temperature sensor 1 during last event.
LTC7132 die temperature sensor during last event.
CYCLICAL DATA
EVENT n
Event “n” represents one complete cycle of ADC reads through the MUX
at time of fault. Example: If the fault occurs when the ADC is processing
step 15, it will continue to take readings through step 25 and then store
the header and all 6 event pages to EEPROM
(Data at Which Fault Occurred; Most Recent Data)
READ_VOUT (PAGE 0)
READ_VOUT (PAGE 1)
READ_IOUT (PAGE 0)
READ_IOUT (PAGE 1)
READ_VIN
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
LIN 16
LIN 16
LIN 16
LIN 16
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
BYTE
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
READ_IIN
STATUS_VOUT (PAGE 0)
STATUS_VOUT (PAGE 1)
STATUS_WORD (PAGE 0)
BYTE
[15:8]
[7:0]
[15:8]
[7:0]
WORD
WORD
WORD
WORD
BYTE
STATUS_WORD (PAGE 1)
STATUS_MFR_SPECIFIC (PAGE 0)
STATUS_MFR_SPECIFIC (PAGE 1)
BYTE
Rev 0
110
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LTC7132
PMBus COMMAND DETAILS
EVENT n-1
(data measured before fault was detected)
READ_VOUT (PAGE 0)
READ_VOUT (PAGE 1)
READ_IOUT (PAGE 0)
READ_IOUT (PAGE 1)
READ_VIN
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
LIN 16
LIN 16
LIN 16
LIN 16
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
BYTE
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
READ_IIN
STATUS_VOUT (PAGE 0)
STATUS_VOUT (PAGE 1)
STATUS_WORD (PAGE 0)
BYTE
[15:8]
[7:0]
[15:8]
[7:0]
WORD
WORD
WORD
WORD
BYTE
STATUS_WORD (PAGE 1)
STATUS_MFR_SPECIFIC (PAGE 0)
STATUS_MFR_SPECIFIC (PAGE 1)
BYTE
*
*
*
EVENT n-5
(Oldest Recorded Data)
READ_VOUT (PAGE 0)
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
LIN 16
LIN 16
LIN 16
LIN 16
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
BYTE
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
READ_VOUT (PAGE 1)
READ_IOUT (PAGE 0)
READ_IOUT (PAGE 1)
READ_VIN
READ_IIN
STATUS_VOUT (PAGE 0)
STATUS_VOUT (PAGE 1)
STATUS_WORD (PAGE 0)
BYTE
[15:8]
[7:0]
[15:8]
[7:0]
WORD
WORD
WORD
WORD
BYTE
STATUS_WORD (PAGE 1)
STATUS_MFR_SPECIFIC (PAGE 0)
STATUS_MFR_SPECIFIC (PAGE 1)
BYTE
Rev 0
111
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LTC7132
PMBus COMMAND DETAILS
Table 13a. Explanation of Position_Fault Values
POSITION_FAULT VALUE
SOURCE OF FAULT LOG
0xFF
0x00
0x01
0x02
0x03
0x05
0x06
0x07
0x0A
MFR_FAULT_LOG_STORE
TON_MAX_FAULT
VOUT_OV_FAULT
VOUT_UV_FAULT
IOUT_OC_FAULT
TEMP_OT_FAULT
TEMP_UT_FAULT
VIN_OV_FAULT
MFR_TEMP_2_OT_FAULT
MFR_FAULT_LOG_CLEAR
The MFR_FAULT_LOG_CLEAR command will erase the fault log file stored values. It will also clear bit 3 in the
STATUS_MFR_SPECIFIC command. After a clear is issued, the status can take up to 8ms to clear.
This write-only command is send bytes.
Block Memory Write/Read
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
MFR_EE_UNLOCK
0xBD
0xBE
0xBF
Unlock user EEPROM for access by MFR_EE_ERASE
R/W Byte
N
N
N
Reg
Reg
Reg
NA
NA
NA
and MFR_EE_DATA commands.
MFR_EE_ERASE
MFR_EE_DATA
Initialize user EEPROM for bulk programming by
MFR_EE_DATA.
R/W Byte
Data transferred to and from EEPROM using
sequential PMBus word reads or writes. Supports bulk
programming.
R/W
Word
All the NVM commands are disabled if the die temperature exceeds 130°C. NVM commands are re-enabled when the
die temperature drops below 125°C.
MFR_EE_xxxx
The MFR_EE_xxxx commands facilitate bulk programming of the LTC7132 internal EEPROM. Contact the factory for
details.
Rev 0
112
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LTC7132
TYPICAL APPLICATIONS
1µF
1Ω
1%
2mΩ
V
IN
180µF
25V
×2
6V TO 14V
10µF
×2
10µF
×2
4.7µF
D2
ꢂ
ꢂ
D1
ꢀ
ꢀꢁ
ꢀ
ꢀꢁ
INTV
SV
IN
CC
PV
IN0
ꢀꢁ
ꢂꢃꢄ
L0
L1
ꢀꢁꢁꢂꢃ0
ꢂꢄ0
ꢅꢆꢆꢇꢈꢄ
ꢇꢉꢄ
0.51µH
0.51µH
0.1µF
0.1µF
4.99k
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
DCR = 0.29mΩ
V
DCR = 0.29mΩ
DD25
ꢂꢅꢆꢇ
LTC7132
24.9k
5.76k
ꢈꢉꢁꢁꢊ0
ꢈꢉꢁꢁꢊꢋ
ꢂꢊꢌ
24.9k
V
V
OUT0_CFG
OUT1_CFG
931Ω
1%
750Ω
1%
V
DD25
ꢂꢇꢍ
20k
ALERT
FAULT0
FAULT1
V
DD33
V
DD25
11k
24.9k
ꢂꢎꢌRꢏꢐꢇꢍꢑ
Rꢒꢆ0
FREQ_CFG
ASEL1
ASEL0
4.32k
4.32k
PHASE_CFG
Rꢒꢆꢋ
WP
EXTV
CC
I
+
–
I
+
SENSE0
SENSE1
470nF
220nF
I
I
V
–
+
SENSE0
SENSE1
SENSE1
V
V
OUT1
1.2V/10A
OUT0
V
V
+
SENSE0
0.9V/25A
100µF
×2
6.3V
330µF
×2
6.3V
330µF
×2
6.3V
100µF
×2
6.3V
V
–
–
SENSE1
SENSE0
TSNS1
TSNS0
10nF
10nF
I
I
TH1
TH0
150pF
150pF
I
I
THR1
THR0
ꢀꢀꢁꢂꢃꢄ0ꢅꢆꢇꢈꢃꢆR
ꢀꢀꢁꢂꢃꢄ0ꢅꢆꢇꢈꢃꢆR
2200pF
V
2200pF
ꢀ
ꢀꢁꢂꢃ ꢀꢁꢂ ꢀ
ꢀꢀꢁꢂ
ꢁꢁꢂꢂ
V
DD25
DD33
2.2µF
1µF
7132TA02
D1, D2: CMDSH3-TR
L0: VITEC 59PR9874N
L1: VITEC 59PR9876N
High Efficiency, Ultralow DCR Sense Dual-Output 0 .9V/25A and 1.2V/10 A, 425 kHz Buck Converter
Rev 0
113
For more information www.analog.com
LTC7132
TYPICAL APPLICATIONS
Rev 0
114
For more information www.analog.com
LTC7132
TYPICAL APPLICATIONS
1Ω
1%
1µF
2mΩ
2mΩ
V
IN
7V TO 14V
10µF
×2
180µF
×2
25V
10µF
×2
4.7µF
ꢂ
ꢂ
D2
D1
ꢀ
ꢀꢁ
ꢀ
ꢀꢁ
INTV
SV
IN
CC
ꢀꢁ
ꢂꢃ0
ꢀꢁ
ꢂꢃꢄ
L1
L2
ꢄꢅꢅꢆꢇ0
ꢆꢈ0
ꢅꢆꢆꢇꢈꢄ
ꢇꢉꢄ
1µH
1µH
0.1µF
0.1µF
4.99k
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
XAL1010-102ME
DCR = 1mΩ
XAL1010-102ME
DCR = 1mΩ
ꢆꢉꢃꢊ
V
DD25
LTC7132
ꢀꢋꢅꢅꢌ0
ꢀꢋꢅꢅꢌꢍ
ꢆꢌꢎ
909Ω
1%
16.2k
16.2k
30.1k
1.96k
ꢁꢆꢊꢈ0ꢋꢌꢍꢎ
ꢁꢆꢊꢈꢄꢋꢌꢍꢎ
ꢏꢇꢐꢑꢄ
909Ω
1%
ꢆꢊꢏ
ALERT
FAULT0
FAULT1
V
DD33
20.5k
17.4k
ꢏꢇꢐꢑ0
350kHz
ꢆꢐꢎRꢑꢒꢊꢏꢓ
Rꢔꢃ0
ꢍRꢐꢒꢋꢌꢍꢎ
ꢀꢓꢏꢇꢐꢋꢌꢍꢎ
Rꢔꢃꢍ
ꢐꢔꢈꢁ
ꢌꢌ
WP
I
+
–
I
+
SENSE0
SENSE1
220nF
220nF
I
I
V
–
+
SENSE0
SENSE1
SENSE1
V
V
OUT1
1.8V/15A
OUT0
V
V
+
SENSE0
2.5V/15A
330µF
×2
6.3V
100µF
×2
6.3V
100µF
×2
6.3V
330µF
×2
6.3V
V
–
–
SENSE1
SENSE0
TSNS1
TSNS0
10nF
10nF
I
I
TH1
TH0
150pF
150pF
I
I
THR1
THR0
ꢀꢀꢁꢂꢃꢄ0ꢅꢆꢇꢈꢃꢆR
ꢀꢀꢁꢂꢃꢄ0ꢅꢆꢇꢈꢃꢆR
1500pF
1500pF
ꢀ
ꢀꢁꢂꢃ ꢀꢁꢂꢃ
ꢀ
ꢀꢀꢁꢂ
ꢁꢁꢂꢂ
V
V
DD25
DD33
2.2µF
1µF
7132TA04
D1, D2, D3, D4: CMDSH3-TR
High Efficiency, 350 kHz, Dual-Output, 2.5V/15A and 1.8V/15A Buck Converter
Rev 0
115
For more information www.analog.com
LTC7132
TYPICAL APPLICATIONS
C3
1µF
1Ω
1%
2mΩ
2mΩ
V
IN
10V TO 14V
10µF
×2
180µF
10µF
4.7µF
×2
×2
25V
ꢂ
ꢂ
D2
D1
ꢀ
ꢀꢁ
ꢀ
ꢀꢁ
INTV
SV
IN
CC
ꢀꢁ
ꢂꢃ0
ꢀꢁ
ꢂꢃꢄ
L1
L2
1.5µH
ꢄꢅꢅꢆꢇ0
ꢆꢈ0
ꢅꢆꢆꢇꢈꢄ
ꢇꢉꢄ
1.5µH
0.1µF
4.99k
10k
0.1µF
XAL1010-152ME
DCR = 1.6mΩ
XAL1010-152ME
DCR = 1.6mΩ
ꢆꢉꢃꢊ
V
DD25
10k
LTC7132
ꢀꢋꢅꢅꢌ0
ꢀꢋꢅꢅꢌꢍ
ꢆꢌꢎ
4.32k
1%
30.1k
1.96k
24.9k
ꢁ
ꢁ
ꢆꢊꢈ0ꢋꢌꢍꢎ
ꢆꢊꢈꢄꢋꢌꢍꢎ
10k
10k
10k
10k
4.32k
1%
ꢆꢊꢏ
ꢍRꢏꢐꢋꢌꢍꢎ
ꢑꢇꢏꢒꢄ
ALERT
FAULT0
FAULT1
V
DD33
23.2k
4.32k
ꢑꢇꢏꢒ0
10k
10k
ꢆꢐꢎRꢑꢒꢊꢏꢓ
Rꢔꢃ0
ꢀꢓꢑꢇꢏꢋꢌꢍꢎ
5.5V
ꢏꢔꢈꢁ
ꢌꢌ
Rꢔꢃꢍ
WP
I
+
–
I
+
SENSE0
SENSE1
220nF
V
220nF
OUT1
I
I
V
–
+
5.0V/30A
SENSE0
SENSE1
SENSE1
V
V
+
SENSE0
330µF
×2
6.3V
100µF
×2
6.3V
100µF
330µF
×2
6.3V
×2
6.3V
V
–
–
SENSE1
SENSE0
TSNS1
TSNS0
10nF
I
10nF
I
TH1
TH0
330pF
I
I
THR1
THR0
ꢀꢀꢁꢂꢃꢄ0ꢅꢆꢇꢈꢃꢆR
ꢀꢀꢁꢂꢃꢄ0ꢅꢆꢇꢈꢃꢆR
3.3nF
ꢀ
ꢀꢁꢂꢃ ꢀꢁꢂꢃ
ꢀ
ꢀꢀꢁꢂ
ꢁꢁꢂꢂ
V
V
DD25
DD33
2.2µF
1µF
7132TA05
High Efficiency, Typical DCR Current Sense, 250 kHz, Dual Phase Single-Output, 5V/30 A Buck Converter
Rev 0
116
For more information www.analog.com
LTC7132
PACKAGE DESCRIPTION
ꢟ
ꢟ
ꢸ ꢸ ꢨ ꢨ ꢨ
ꢟ
ꢘ ꢇ ꢱ 0 0
ꢕ ꢇ ꢲ 0 0
ꢕ ꢇ 0 0 0
ꢆ ꢇ ꢕ 0 0
0 ꢇ ꢑ 0 0
0 ꢇ ꢑ 0 0
ꢆ ꢇ ꢕ 0 0
ꢕ ꢇ 0 0 0
ꢕ ꢇ ꢲ 0 0
ꢘ ꢇ ꢱ 0 0
0 ꢇ 0 0 0
ꢣ ꢣ ꢣ
ꢟ
Rev 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
117
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LTC7132
TYPICAL APPLICATION
Low DCR Sensing, 425kHz, Dual Phase Single-Output, 1V/40 A Buck Converter
C3
1µF
1Ω
1%
2mΩ
V
IN
6V TO 14V
10µF
×2
180µF
10µF
×2
×2
4.7µF
ꢂ
ꢂ
D2
D1
25V
ꢀ
ꢀꢁ
ꢀ
INTV
CC
ꢀꢁ
ꢂꢃ0
SV
IN
ꢀꢁ
ꢀꢁ
ꢂꢃꢄ
L1
L2
0.3µH
ꢄꢅꢅꢆꢇ0
ꢆꢈ0
ꢅꢆꢆꢇꢈꢄ
ꢇꢉꢄ
0.3µH
0.1µF
4.99k
0.1µF
PA3288.301HL
DCR = 0.29mΩ
PA3288.301HL
DCR = 0.29mΩ
ꢆꢉꢃꢊ
V
10k
DD25
LTC7132
ꢀꢋꢅꢅꢌ0
ꢀꢋꢅꢅꢌꢍ
ꢆꢌꢎ
931Ω
1%
931Ω
1%
24.9k
24.9k
4.32k
30.1k
ꢁ
ꢁ
ꢆꢊꢈ0ꢋꢌꢍꢎ
ꢆꢊꢈꢄꢋꢌꢍꢎ
10k
10k
10k
10k
ꢆꢊꢏ
ꢍRꢏꢐꢋꢌꢍꢎ
ꢀꢑꢒꢇꢏꢋꢌꢍꢎ
ꢏꢓꢈꢁ
7.32k
1.96k
V
ALERT
FAULT0
FAULT1
DD33
ꢌꢌ
ꢒꢇꢏꢔ0
ꢒꢇꢏꢔꢄ
10k
10k
ꢆꢐꢎRꢑꢒꢊꢏꢓ
Rꢔꢃ0
Rꢔꢃꢍ
WP
I
I
+
–
I
+
SENSE0
SENSE1
220nF
220nF
V
OUT
1V/40A
I
V
–
+
SENSE0
SENSE1
SENSE1
V
+
SENSE0
330µF
100µF
100µF
330µF
×2
×2
×2
×2
6.3V
6.3V
6.3V
6.3V
V
–
V
–
SENSE1
SENSE0
TSNS1
TSNS0
10nF
I
10nF
I
TH1
TH0
220pF
I
I
THR1
THR0
10pF
ꢀꢀꢁꢂꢃꢄ0ꢅꢆꢇꢈꢃꢆR
ꢀꢀꢁꢂꢃꢄ0ꢅꢆꢇꢈꢃꢆR
4.7nF
ꢀ
ꢀꢁꢂꢃ ꢀꢁꢂꢃ
ꢀ
ꢀꢀꢁꢂ
ꢁꢁꢂꢂ
V
V
DD33
DD25
1µF
2.2µF
7132 TA07
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
4.5V ≤ V ≤17V; 0.5V ≤ V
2
LTM4676A
LTM4675
LTM4677
LTC3874
Dual 13A or Single 26A Step-Down DC/DC µModule
Regulator with Digital Power System Management
( 0.5%) ≤ 5.5V, I C/PMBus Interface,
IN
OUT
16mm × 16mm × 5mm, BGA Package
2
Dual 9A or Single 18A μModule Regulator with Digital
Power System Management
4.5V ≤ V ≤17V; 0.5V ≤ V ( 0.5%) ≤ 5.5V, I C/PMBus Interface,
IN
OUT
11.9mm × 16mm × 5mm, BGA Package
2
Dual 18A or Single 36A µModule Regulator with Digital
Power System Management
4.5V ≤ V ≤ 16V; 0.5V ≤ V ( 0.5%) ≤ 1.8V, I C/PMBus Interface,
IN
OUT
16mm × 16mm × 5.01mm, BGA Package
Multiphase Step-Down Synchronous Slave Controller with 4.5V ≤ V ≤ 38V, V
up to 5.5V, Very High Output Current, Accurate
IN
OUT
Sub MilliOhm DCR Sensing
Current Sharing, Current Mode Applications
Dual Output Multiphase Step-Down DC/DC Controller with 4.5V ≤ V ≤ 24V, 0.5V ≤ V ( 0.5%) ≤ 5.5V, 70mS Start-Up, I C/
IN OUT0,1
2
LTC3887/
LTC3887-1
Digital Power System Management, 70mS Start-Up
PMBus Interface, –1 Version uses DrMOS or Power Blocks
2
LTC3882/
LTC3882-1
Dual Output Multiphase Step-Down DC/DC Voltage Mode
Controller with Digital Power System Management
3V ≤ V ≤ 38V, 0.5V ≤ V ≤ 5.25V, ( 0.5%) V Accuracy I C/
IN
OUT1,2
OUT
PMBus Interface, uses DrMOS or Power Blocks
2
LTC3886
LTC3815
60V Dual Output Step-Down Controller with Digital Power
System Management
4.5V ≤ V ≤ 60V, 0.5V ≤ V ( 0.5%) ≤ 13.8V, 70mS Start-Up, I C/
IN
OUT0,1
PMBus Interface, Input Current Sense
2.25V ≤ V ≤ 5.5V, 0.4V ≤ V ≤ 0.72V , Programmable V Range
OUT
6A Monolithic Synchronous DC/DC Step-Down Converter
with Digital Power System Management
IN
OUT
IN
25% with 0.1% Resolution, Up to 3MHz Operation with 13-Bit ADC
Licensed under U.S. Patent 7000125 and other related patents worldwide.
Rev 0
9/20
www.analog.com
ANALOG DEVICES, INC. 2019
118
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