LTC7802JUFDM-3.3 [ADI]
40V Low IQ, 3MHz Dual, 2-Phase Synchronous Step-Down Controller with Spread Spectrum;
| 型号： | LTC7802JUFDM-3.3 |
| 厂家： | 
ADI |
| 描述： | 40V Low IQ, 3MHz Dual, 2-Phase Synchronous Step-Down Controller with Spread Spectrum |
| 文件： | 总34页 (文件大小：1462K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC7802-3.3
40V Low I , 3MHz Dual, 2-Phase Synchronous
Q
Step-Down Controller with Spread Spectrum
FEATURES
DESCRIPTION
The LTC®7802-3.3 is a high performance dual step-down
synchronous DC/DC switching regulator controller that
drives all N-channel power MOSFET stages. Constant fre-
quency current mode architecture allows a phase-lockable
switching frequency of up to 3MHz. The LTC7802-3.3
operates from a wide 4.5V to 40V input supply range.
Power loss and supply noise are minimized by operating
the two controller output stages out-of-phase.
n
Wide Input Voltage Range: 4.5V to 40V
n
n
n
n
n
n
Wide Output Voltage Range: 0.8V to 99% • V
IN
Low Operating I : 12μA (14V to 3.3V, Channel 1 On)
Q
Fixed 3.3V Output Voltage on Channel 1
Spread Spectrum Operation
R
SENSE
or DCR Current Sensing
Out-of-Phase Controllers Reduce Required Input
Capacitance and Power Supply Induced Noise
Programmable Fixed Frequency (100kHz to 3MHz)
Phase-Lockable Frequency (100kHz to 3MHz)
Selectable Continuous, Pulse-Skipping, or Low
Ripple, Burst Mode® Operation at Light Loads
Very Low Dropout Operation: 99% Duty Cycle
Power Good Output Voltage Monitors
n
n
n
The very low no-load quiescent current extends operating
runtime in battery powered systems. OPTI-LOOP com-
pensation allows the transient response to be optimized
over a wide range of output capacitance and ESR values.
The LTC7802-3.3 features a precision 0.8V reference and
power good output indicators. The MODE pin selects
among Burst Mode operation, pulse-skipping mode, or
continuous inductor current mode at light loads.
n
n
n
n
n
n
Output Overvoltage Protection
Internal LDO Powers Gate Drive from V or EXTV
IN
CC
Low Shutdown I : 1.5μA
Q
The LTC7802-3.3 additionally features spread spectrum
operation which significantly reduces the peak radiated
and conducted noise on both the input and output sup-
plies, making it easier to comply with electromagnetic
interference (EMI) standards.
Side Wettable 4mm × 5mm QFN-28 Package
APPLICATIONS
n
Automotive and Transportation
n
Industrial
All registered trademarks and trademarks are the property of their respective owners.
n
Military / Avionics
TYPICAL APPLICATION
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Rev. 0
1
Document Feedback
For more information www.analog.com
LTC7802-3.3
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
Input Supply Voltage (V )......................... –0.3V to 40V
IN
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BOOST1, BOOST2...................................... –0.3V to 46V
Switch Voltage (SW1, SW2).......................... –5V to 40V
RUN1, RUN2 Voltages................................ –0.3V to 40V
EXTV Voltage ......................................... –0.3V to 30V
CC
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INTV Voltage ............................................ –0.3V to 6V
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(BOOST1–SW1), (BOOST2–SW2)................ –0.3V to 6V
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SENSE1 , SENSE1 Voltages...................... –0.3V to 40V
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SENSE2 , SENSE2 Voltages ..................... –0.3V to 40V
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TRACK/SS1, V
Voltages........................ –0.3V to 6V
OUT1
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TRACK/SS2, V Voltages.......................... –0.3V to 6V
FB2
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MODE, PGOOD1, PGOOD2 Voltages ............ –0.3V to 6V
PLLIN/SPREAD, FREQ Voltages................... –0.3V to 6V
ITH1, ITH2 Voltages ..................................... –0.3V to 2V
BG1, BG2, TG1, TG2...........................................(Note 9)
Operating Junction Temperature Range (Notes 2, 8)
LTC7802E-3.3, LTC7802I-3.3............. –40°C to 125°C
LTC7802J-3.3, LTC7802H-3.3 ........... –40°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
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ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC7802EUFDM-3.3#PBF
AUTOMOTIVE PRODUCTS**
LTC7802IUFDM-3.3#WPBF
LTC7802-3.3EUFDM#TRPBF
78023
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
LTC7802IUFDM-3.3#WTRPBF
78023
28-Lead (4mm × 5mm) Plastic QFN
28-Lead (4mm × 5mm) Plastic QFN
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
–40°C to 150°C
–40°C to 150°C
LTC7802JUFDM-3.3#WPBF LTC7802JUFDM-3.3#WTRPBF 78023
LTC7802HUFDM-3.3#WPBF LTC7802HUFDM-3.3#WTRPBF 78023
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
these models.
Rev. 0
2
For more information www.analog.com
LTC7802-3.3
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 12V, RUN1,2 > 1.25V, EXTVCC = 0V, unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Supply (V )
IN
V
Input Supply Operating Range
Current in Regulation
4.5
40
V
IN
I
V
IN
Front Page Circuit, 14V to 3.3V,
No Load, RUN2 = 0V
12
µA
VIN
Controller Operation
V
V
Channel 2 Output Voltage Operating Range
Channel 1 Regulated Output Voltage
0.8
3.25
0.788
40
V
V
V
OUT2
OUT1
(Note 4) V = 4.5V to 40V,
IN
l
l
ITH1 Voltage = 0.6V to 1.2V
3.3
3.35
0.812
V
Channel 2 Regulated Feedback Voltage
Feedback Current
(Note 4) V = 4.5V to 40V,
FB2
IN
ITH2 Voltage = 0.6V to 1.2V
0.800
Channel 1
Channel 2
1
5
µA
nA
50
13
Feedback Overvoltage Protection Threshold Measured at V
, V Relative to
OUT1 FB2
7
10
%
OUT1 FB2
Regulated V
, V
g
Transconductance Amplifier g
(Note 4) ITH1,2 = 1.2V, Sink/Source = 5μA
1.8
50
0
mmho
mV
mV
µA
m1,2
m
l
V
Maximum Current Sense Threshold
Matching Between Channels
V
V
V
V
= 2.9V, V = 0.7V, V – = 3.3V
SENSE1,2
45
55
3.5
1
SENSE(MAX)
OUT1
FB2
–
= 3.3V
= 3.3V
–3.5
SENSE1,2
SENSE1,2
+
+
+
I
I
I
SENSE1, 2 Pin Current
SENSE1,2
–
–
–
SENSE1 Pin Current
= 3.3V
= 3.3V
50
µA
SENSE1
SENSE1
–
–
–
–
SENSE2 Pin Current
V
V
2
µA
µA
SENSE2
SENSE2
SENSE2
> INTV + 0.5V
650
12.5
1.20
100
CC
Soft-Start Charge Current
RUN Pin ON Threshold
RUN Pin Hysteresis
V
V
= 0V
10
15
µA
V
TRACK/SS1,2
l
Rising
1.15
1.25
RUN1,2
mV
DC Supply Current (Note 5)
V
Shutdown Current
RUN1,2 = 0V
1.5
15
µA
µA
IN
–
V
IN
Sleep Mode Current
V
< 3.2V, EXTV = 0V
24
SENSE1
CC
Only Channel 2 On
Sleep Mode Current (Note 3)
Only Channel 1 On
V
V
Current, EXTV = 0V
5
1
9
4
10
18
µA
µA
µA
µA
IN
IN
CC
Current, EXTV ≥ 4.8V
CC
EXTV Current, EXTV ≥ 4.8V
5
CC
CC
–
SENSE1 Current
10
Sleep Mode Current (Note 3)
Both Channels On
EXTV ≥ 4.8V
CC
V
Current
1
7
12
4
14
22
µA
µA
µA
IN
EXTV Current
CC
–
SENSE1 Current
Pulse-Skipping or Forced Continuous Mode One Channel On
or EXTV Current (Notes 3, 5) Both Channels On
2
3
mA
mA
V
IN
CC
Rev. 0
3
For more information www.analog.com
LTC7802-3.3
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 12V, RUN1,2 > 1.25V, EXTVCC = 0V, unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Gate Drivers
TG or BG On-Resistance
Pull-Up
Pull-Down
2.0
1.0
Ω
Ω
TG or BG Transition Time
Rise Time
Fall Time
(Note 6)
LOAD
LOAD
C
C
= 3300pF
= 3300pF
25
15
ns
ns
TG Off to BG On Delay
Synchronous Switch-On Delay Time
C
LOAD
= 3300pF Each Driver
15
ns
BG Off to TG On Delay
Top Switch-On Delay Time
C
LOAD
= 3300pF Each Driver
15
ns
t
TG Minimum On-Time
(Note 7)
40
99
ns
%
ON(MIN)1,2
Maximum Duty Factor for TG
f
= 350kHz
98
OSC
INTV Low Dropout (LDO) Linear Regulator
CC
INTV Regulation Point
4.9
5.1
5.3
V
CC
INTV Load Regulation
I
I
= 0mA to 100mA, V ≥ 6V
1.2
1.2
2
2
%
%
CC
CC
CC
IN
= 0mA to 100mA, V
≥ 6V
EXTVCC
EXTV LDO Switchover Voltage
EXTV Rising
4.5
4.7
4.8
V
CC
CC
EXTV Switchover Hysteresis
250
mV
CC
l
l
UVLO
Undervoltage Lockout
INTV Rising
4.10
3.75
4.20
3.85
4.35
4.00
V
V
CC
INTV Falling
CC
Spread Spectrum Oscillator and Phase-Locked Loop
f
Low Fixed Frequency
High Fixed Frequency
Programmable Frequency
V
V
= 0V, PLLIN/SPREAD = 0V
320
2.0
350
380
2.5
kHz
OSC
FREQ
l
= INTV , PLLIN/SPREAD = 0V
2.25
MHz
FREQ
CC
R
R
R
= 374kΩ, PLLIN/SPREAD = 0V
= 75kΩ, PLLIN/SPREAD = 0V
= 12.1kΩ, PLLIN/SPREAD = 0V
100
500
3
kHz
kHz
MHz
FREQ
FREQ
FREQ
450
550
3
l
Synchronizable Frequency Range
PLLIN/SPREAD = External Clock
0.1
2.2
MHz
l
l
PLLIN Input High Level
PLLIN Input Low Level
V
V
0.5
Spread Spectrum Frequency Range
PLLIN/SPREAD = INTV
Minimum Frequency
Maximum Frequency
CC
(Relative to f
)
–12
15
%
%
OSC
PGOOD1 and PGOOD2 Outputs
PGOOD Voltage Low
PGOOD Leakage Current
PGOOD Trip Level
I
= 2mA
= 5V
0.2
0.4
1
V
PGOOD1,2
V
µA
PGOOD1,2
V
, V Rising
OUT1 FB2
7
10
2.5
13
%
%
V
, V Relative to Set Regulation Point Hysteresis
OUT1 FB2
V
, V Falling
–13
–10
2.5
–7
%
%
OUT1 FB2
Hysteresis
PGOOD Delay for Reporting a Fault
25
µs
Rev. 0
4
For more information www.analog.com
LTC7802-3.3
ELECTRICAL CHARACTERISTICS
–
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: When SENSE1 ≥ 3.2V or EXTV ≥ 4.8V, V supply current
CC IN
is transferred to these pins to reduce the total input supply quiescent
current. SENSE1 bias current is reflected to the channel 1 input supply by
–
the formula I
= I
– • V /(V • η), where η is the efficiency.
OUT1 IN1
VIN1
SENSE1
EXTV bias current is similarly reflected to the input supply when biased
by an output. Input supply current is minimized when EXTV is connected
to the lowest output-derived voltage greater than 4.8V.
Note 4: The LTC7802-3.3 is tested in a feedback loop that servos V
to a specified voltage and measures the resultant V
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications information.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 7: The minimum on-time condition is specified for an inductor
peak-to-peak ripple current >40% of I
Considerations in the Applications Information section).
CC
Note 2: The LTC7802-3.3 is tested under pulsed load conditions such
CC
that T ≈ T . The LTC7802E-3.3 is guaranteed to meet specifications
J
A
from 0°C to 85°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC7802I-3.3 is guaranteed over the –40°C to 125°C operating junction
temperature range, and the LTC7802J-3.30/LTC7802H-3.3 are guaranteed
over the –40°C to 150°C operating junction temperature range. High
junction temperatures degrade operating lifetimes; operating lifetime
is derated for junction temperatures greater than 125°C. Note that the
maximum ambient temperature consistent with these specifications is
determined by specific operating conditions in conjunction with board
layout, the rated package thermal impedance and other environmental
ITH1,2
, V
OUT1 FB2
.
(See Minimum On-Time
L(MAX)
Note 8: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
factors. The junction temperature (T , in °C) is calculated from the ambient
J
temperature (T , in °C) and power dissipation (P , in Watts) according
A
D
to the formula: T = T + (P • θ ), where θ (in °C/W) is the package
J
A
D
JA
JA
thermal impedance.
Note 9: Do not apply a voltage or current source to these pins. They must
be connected to capacitive loads only, otherwise permanent damage may
occur.
Rev. 0
5
For more information www.analog.com
LTC7802-3.3
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency and Power Loss
vs Load Current
Efficiency vs Load Current
Efficiency vs Input Voltage
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ꢀꢁꢂꢃRꢄ ꢅ ꢆꢁRꢆꢃꢁꢇ
0.000ꢀ 0.00ꢀ
0.0ꢀ
0.ꢀ ꢀ0
ꢀ
0.000ꢀ 0.00ꢀ
0.0ꢀ
0.ꢀ
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0
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ꢀꢁ0ꢂꢃꢃ ꢄ0ꢂ
ꢀꢁ0ꢂꢃꢃ ꢄ0ꢃ
Load Step Forced
Continuous Mode
Load Step Burst Mode Operation
Load Step Pulse-Skipping Mode
ꢀ
ꢀ
ꢁꢂꢃ
ꢁꢂꢃ
ꢀ
ꢁꢂꢃ
ꢄ00ꢅꢀꢆꢇꢈꢀ
ꢄ00ꢅꢀꢆꢇꢈꢀ
ꢄ00ꢅꢀꢆꢇꢈꢀ
ꢀꢁꢂꢃꢄꢅꢆR
ꢄꢃRRꢇꢁꢅ
ꢈꢉꢊꢂꢀꢋ
ꢀꢁꢂꢃꢄꢅꢆR
ꢄꢃRRꢇꢁꢅ
ꢈꢉꢊꢂꢀꢋ
ꢀꢁꢂꢃꢄꢅꢆR
ꢄꢃRRꢇꢁꢅ
ꢈꢉꢊꢂꢀꢋ
ꢀꢁꢂꢃ
ꢄꢅRRꢆꢇꢈ
ꢉꢂꢊꢃꢋꢌ
ꢀꢁꢂꢃ
ꢄꢅRRꢆꢇꢈ
ꢉꢂꢊꢃꢋꢌ
ꢀꢁꢂꢃ
ꢄꢅRRꢆꢇꢈ
ꢉꢂꢊꢃꢋꢌ
ꢀꢁ0ꢂꢃꢃ ꢄ0ꢅ
ꢀꢁ0ꢂꢃꢃ ꢄ0ꢅ
ꢀꢁ0ꢂꢃꢃ ꢄ0ꢅ
ꢀ0ꢁꢂꢃꢄꢅꢆ
ꢀ0ꢁꢂꢃꢄꢅꢆ
ꢀ0ꢁꢂꢃꢄꢅꢆ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁꢂ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁꢂ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ ꢁꢂ
ꢀ
ꢀ ꢁꢂ
ꢀ
ꢀ ꢁꢂ
ꢀ00ꢁꢂ ꢃꢄ ꢅꢂ ꢆꢄꢂꢇ ꢈꢃꢉꢊ
ꢀ00ꢁꢂ ꢃꢄ ꢅꢂ ꢆꢄꢂꢇ ꢈꢃꢉꢊ
ꢀ00ꢁꢂ ꢃꢄ ꢅꢂ ꢆꢄꢂꢇ ꢈꢃꢉꢊ
ꢀꢁꢂꢃRꢄ ꢅ ꢆꢁRꢆꢃꢁꢇ
ꢀꢁꢂꢃRꢄ ꢅ ꢆꢁRꢆꢃꢁꢇ
ꢀꢁꢂꢃRꢄ ꢅ ꢆꢁRꢆꢃꢁꢇ
Regulated Feedback Voltage
vs Temperature
Inductor Current at Light Load
Soft Start-Up
ꢀ.00
0.ꢀꢁ
0.ꢀ0
0.ꢀꢁ
0
ꢀꢁRꢂꢃꢄ
Rꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄꢁ
ꢀꢁꢂꢃꢄꢂꢅꢁꢅꢆ
ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢁ
ꢀꢁRꢂꢃ ꢄꢅꢆꢇ
ꢀꢁꢂRꢃꢄꢅꢀꢆ
ꢀꢁꢂꢃꢄꢅ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢁ
ꢀ0.ꢁꢂ
ꢀ0.ꢁ0
ꢀ0.ꢁꢂ
ꢀꢁ.00
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢃꢂꢄꢅ
ꢀꢁꢂꢃ
ꢀꢁ0ꢂꢃꢃ ꢄ0ꢁ
ꢀꢁ0ꢂꢃꢃ ꢄ0ꢀ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁ
ꢀ
ꢀ ꢁꢂ
ꢀꢁRꢂꢃꢄ ꢂꢁꢅꢆꢇꢅꢈꢁꢈꢉ ꢊꢁꢄꢃ
ꢀꢁ ꢂꢁꢃꢄ
ꢀꢁꢂꢃRꢄ ꢅ ꢆꢁRꢆꢃꢁꢇ
ꢀꢁꢁ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢂ ꢀꢁꢁ
ꢀꢁꢂꢃRꢄ ꢅ ꢆꢁRꢆꢃꢁꢇ
ꢀ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆ ꢀꢁ
ꢀꢁ0ꢂꢃ ꢄ0ꢅ
Rev. 0
6
For more information www.analog.com
LTC7802-3.3
TYPICAL PERFORMANCE CHARACTERISTICS
Current Sense Threshold vs ITH
Voltage
SENSE1,2– Input Current
vs VSENSE Voltage
SENSE1,2+ Input Current
vs VSENSE Voltage
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
0
ꢀ0
ꢀ0
ꢀ.0
0.ꢀ
ꢀꢁꢂꢃ ꢄ ꢅꢆꢇꢈ
ꢀꢀ
ꢀꢁꢂꢃ ꢄ ꢅꢆꢇꢈ
ꢀꢁꢂꢃꢄꢅꢃꢆꢇꢀꢀꢇꢈꢉ
ꢀꢁꢂꢃꢄ ꢅꢆꢇe ꢈꢉꢊRꢋꢌꢍꢈꢎ
ꢀꢁRꢂꢃꢄ ꢂꢁꢅꢆꢇꢅꢈꢁꢈꢉ
ꢀꢀ
0.ꢀ
ꢀ0
0.ꢀ
ꢀ0
0.ꢀ
ꢀ0
0.0
ꢀ0.ꢁ
ꢀ0.ꢁ
ꢀ0.ꢁ
ꢀ0.ꢁ
ꢀꢁ.0
0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
0
ꢀ
ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0
0
0.ꢀ 0.ꢀ 0.ꢀ 0.ꢀ ꢀ.0 ꢀ.ꢁ ꢀ.ꢁ
0
ꢀ
ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0
ꢀ
ꢀꢁꢂ ꢃꢄꢅꢁꢆꢇꢈ ꢉꢃꢊ
ꢀ
ꢀꢁꢂꢀꢁꢃ ꢀꢁꢂꢃꢄꢅꢆ ꢇꢀꢈ
ꢀꢁ0ꢂꢃꢃ ꢄꢅꢅ
ꢀꢁꢂꢀꢁ ꢀꢁꢂꢃꢄꢅꢆ ꢇꢀꢈ
ꢀꢁ0ꢂꢃꢃ ꢄꢅꢂ
ꢀꢁ0ꢂꢃꢃ ꢄꢅ0
SENSE1,2– Input Current
vs Temperature
SENSE1,2+ Input Current
vs Temperature
Foldback Current Limit
ꢀ.0
0.ꢀ
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
0
ꢀꢁꢂꢃ ꢄ ꢅꢆꢇꢈ
ꢀꢁꢂꢃ ꢄ ꢅꢆꢇꢈ
ꢀꢀ
ꢀꢀ
ꢀ
ꢀꢁꢂꢀꢁꢃ ꢀ ꢁꢂꢃꢄ ꢀ 0.ꢁꢂ
ꢀꢀ
0.ꢀ
ꢀ
ꢀꢁꢂꢀꢁ ꢀ ꢁꢂꢃ
0.ꢀ
0.ꢀ
ꢀ
ꢀꢁꢂꢀꢁ ꢀ ꢁ.ꢁꢂ
0.0
ꢀ
ꢀꢁꢂꢀꢁ ꢀ ꢁꢂ
ꢀ0.ꢁ
ꢀ0.ꢁ
ꢀ0.ꢁ
ꢀ0.ꢁ
ꢀꢁ.0
ꢀ
ꢀꢁꢂꢀꢁ ꢀ 0ꢁ
ꢀ
ꢀꢁꢂꢀꢁꢃ ꢀ ꢁ.ꢁꢂ
ꢀ
ꢀꢁꢂꢀꢁꢃ ꢀ ꢁꢂꢃꢄ ꢀ 0.ꢁꢂ
ꢀꢀ
ꢀꢁ00
ꢀꢁꢁ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢂ ꢀꢁꢁ
0
ꢀ00 ꢀ00 ꢀ00 ꢀ00 ꢀ00 ꢀ00 ꢀ00 ꢀ00
ꢀꢁꢁ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢂ ꢀꢁꢁ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢀꢀꢁ
ꢀꢁꢁꢂꢃꢄꢅꢆ ꢇꢈꢉꢊꢄꢋꢁ ꢌꢍꢇꢎ
ꢀ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆ ꢀꢁ
ꢀꢁ0ꢂꢃꢃ ꢄꢅꢆ
ꢀꢁ0ꢂꢃꢃ ꢄꢅꢃ
ꢀꢁ0ꢂꢃꢃ ꢄꢅꢆ
Maximum Current Sense
Oscillator Frequency
vs Temperature
RUN Pin Thresholds vs
Temperature
Threshold vs SENSE– Voltage
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ.ꢁꢁ
ꢀ.ꢁ0
ꢀ.ꢀꢁ
ꢀ.ꢀꢁ
ꢀ.ꢀꢁ
ꢀ.ꢀꢁ
ꢀ.ꢀ0
ꢀ.0ꢁ
ꢀ.0ꢁ
ꢀ0
ꢀ
R
R
R
ꢀ ꢁꢂꢃꢄ ꢅꢆ00ꢄꢇꢈꢉ
ꢀ ꢁꢂꢃ ꢄꢂ00ꢃꢅꢆꢇ
ꢀ ꢁꢂꢃ ꢄꢅꢆꢇꢈꢉ
ꢀRꢁꢂ
ꢀRꢁꢂ
ꢀRꢁꢂ
ꢀRꢁꢂ ꢃ ꢄꢅꢆ ꢇꢈꢉ0ꢊꢋꢌꢍ
ꢀRꢁꢂ ꢃꢄꢅꢆꢇ ꢀꢁ.ꢁꢂꢃꢄꢅꢆ
Rꢀꢁꢀꢂꢃ
ꢀ
ꢀꢀ
ꢀ
ꢀ
0
ꢀꢁꢂꢂꢃꢄꢅ
ꢀꢁ
ꢀꢁ
ꢀꢁ
0
ꢀ
ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0
ꢀꢁꢁ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢂ ꢀꢁꢁ
ꢀꢁꢁ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢂ ꢀꢁꢁ
ꢀ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢀꢀꢁ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢀꢀꢁ
ꢀꢁꢂꢀꢁ ꢀꢁꢂꢃꢄꢅꢆ ꢇꢀꢈ
ꢀꢁ0ꢂꢃꢃ ꢄꢅꢆ
ꢀꢁ0ꢂꢃꢃ ꢄꢅꢁ
ꢀꢁ0ꢂꢃꢃ ꢄꢅꢀ
Rev. 0
7
For more information www.analog.com
LTC7802-3.3
TYPICAL PERFORMANCE CHARACTERISTICS
EXTVCC Switchover and INTVCC
Voltage vs Temperature
INTVCC Undervoltage Lockout
Thresholds vs Temperature
INTVCC Load Regulation
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢀ
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢀ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢀ
ꢀ.ꢁ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂꢃ ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃ ꢀ ꢁꢂ
ꢀꢀ
ꢀꢀ
Rꢀꢁꢀꢂꢃ
ꢀꢁꢂꢃ ꢀ 0ꢁ
ꢀꢀ
ꢀꢁꢂꢃ ꢀ ꢁꢂ
ꢀꢀ
ꢀꢁꢂꢃ Rꢀꢁꢀꢂꢃ
ꢀꢀ
ꢀꢁꢂꢂꢃꢄꢅ
ꢀꢁꢂꢃ ꢀꢁꢂꢂꢃꢄꢅ
ꢀꢀ
0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀ00
ꢀꢁ0
ꢀ00
ꢀꢁꢁ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢂ ꢀꢁꢁ
ꢀꢁꢁ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢂ ꢀꢁꢁ
ꢀꢁꢂꢃ ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢊꢂꢋ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢀꢀꢁ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢀꢀꢁ
ꢀꢀ
ꢀꢁ0ꢂꢃꢃ ꢄꢅꢆ
ꢀꢁ0ꢂꢃꢃ ꢄꢂꢅ
ꢀꢁ0ꢂꢃꢃ ꢄꢂ0
Quiescent Current
vs Temperature
TRACK/SS Pull-Up Current
vs Temperature
Shutdown Current vs VIN Voltage
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀ.0
ꢀ.0
ꢀ.0
ꢀ.0
ꢀ.0
ꢀ.0
ꢀ.0
ꢀ.0
0
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢀ
ꢀ0
ꢀ
ꢀꢁꢂꢃ ꢄꢅꢆꢁꢁꢇꢂ ꢈ ꢀꢁ
ꢀꢁꢂꢂꢃ ꢄꢅꢆꢂ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁ
ꢀꢁꢁꢀꢀ
ꢀꢁꢂꢀꢀ
ꢀꢁꢂꢃ ꢀ 0ꢁ
ꢀꢀ
ꢀ
ꢀꢁꢂꢀꢁꢃ ꢀ 0ꢁ
ꢀꢁꢂꢃ ꢀ 0ꢁ
ꢀꢀ
ꢀ
ꢀꢁꢂꢀꢁꢃ ꢀ ꢁ.ꢁꢂ
ꢀꢁꢂꢃ ꢀ ꢁꢂ
ꢀꢁꢂꢀꢁꢃ ꢀ ꢁ.ꢁꢂ
ꢀꢀ
ꢀ
ꢀꢁꢀꢀ
ꢀꢁꢁꢀꢀ
0
ꢀꢁꢁ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ ꢀꢁ ꢀꢁꢂ ꢀꢁꢁ
0
ꢀ
ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0
ꢀꢁꢂꢃꢄꢅꢆ ꢇꢀꢈ
ꢀꢁꢁ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢂ ꢀꢁꢁ
ꢀ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢀꢀꢁ
ꢀ
ꢀꢁ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆ ꢀꢁ
ꢀꢁ0ꢂꢃꢃ ꢄꢂꢂ
ꢀꢁ0ꢂꢂꢃ ꢄꢃꢂ
ꢀꢁ0ꢂꢃꢃ ꢄꢂꢅ
Rev. 0
8
For more information www.analog.com
LTC7802-3.3
PIN FUNCTIONS
SENSE1+, SENSE2+ (Pins 1,8): The Positive (+) Input
EXTVCC (Pin 18): External Power Input to an Internal LDO
to the Differential Current Comparators. The ITH pin
Connected to INTV . This LDO supplies INTV power,
CC CC
–
voltage and controlled offsets between the SENSE and
bypassing the internal LDO powered from V whenever
IN
+
SENSE pins in conjunction with R
trip threshold.
set the current
EXTVCC is higher than 4.7V. See INTVCC Regulators in the
SENSE
Applications Information section. Do not exceed 30V on
this pin. Connect this pin to ground if the EXTV LDO
SENSE1–, SENSE2– (Pins 2,7): The Negative (–) Input
CC
is not used.
to the Differential Current Comparators. The SENSE2–
pin supplies current to its current comparator when it is
VIN (Pin 19): Main Bias Input Supply Pin. A bypass capac-
itor should be tied between this pin and GND.
–
greater than INTV . When SENSE1 is 3.2V or greater,
CC
it supplies the majority of the sleep mode quiescent cur-
rent instead of VIN, further reducing the input-referred
quiescent current.
PLLIN/SPREAD (Pin 25): External Synchronization Input
and Spread Spectrum Selection. When an external clock
is applied to this pin, the phase-locked loop will force the
rising TG1 signal to be synchronized with the rising edge
of the external clock. When an external clock is present, the
regulators operate in pulse-skipping mode if it is selected
by the MODE pin, or in forced continuous mode otherwise.
When not synchronizing to an external clock, tie this input
to INTVCC to enable spread spectrum dithering of the oscil-
lator or to ground to disable spread spectrum.
FREQ (Pin 3): Frequency Control Pin for the Internal
Oscillator. Connect to ground to set the switching fre-
quency to 350kHz. Connect to INTV to set the switching
CC
frequency to 2.25MHz. Frequencies between 100kHz and
3MHz can be programmed using a resistor between the
FREQ pin and ground. Minimize the capacitance on this pin.
MODE (Pin 4): Mode Select Input. This input, which acts
on both channels, determines how the LTC7802-3.3 oper-
ates at light loads. Pulling this pin to ground selects Burst
Mode operation. An internal 100k resistor to ground also
invokes Burst Mode operation when the pin is floating.
BG1, BG2 (Pins 20,16): High Current Gate Drives for
Bottom (Synchronous) N-Channel MOSFETs. Voltage
swing at these pins is from ground to INTV .
CC
BOOST1, BOOST2 (Pins 21,15): Bootstrapped Supplies to
the Top Side Floating Drivers. Connect capacitors between
the corresponding BOOST and SW pins for each channel.
Also connect Schottky diodes between the BOOST1 and
Tying this pin to INTV forces continuous inductor cur-
CC
rent operation. Tying this pin to INTV through a 100k
CC
resistor selects pulse-skipping operation.
RUN1, RUN2 (Pins 5,6): Run Control Inputs for Each
Controller. Forcing either of these pins below 1.1V disables
switching of the corresponding controller. Forcing both of
these pins below 0.7V shuts down the entire LTC7802-
3.3, reducing quiescent current to approximately 1.5µA.
INTV pins and the BOOST2 and INTV pins. Voltage
CC CC
swing at the BOOST pins is from INTV to (V + INTV ).
CC
IN
CC
SW1, SW2 (Pins 22,14): Switch Node Connections to
Inductors.
TG1, TG2 (Pins 23,13): High Current Gate Drives for Top
These pins can be tied to V for always-on operation. Do
IN
N Channel MOSFETs. These are the outputs of floating
not float the RUN pins.
drivers with a voltage swing of INTV superimposed on
CC
INTV (Pin 17): Output of the Internal 5.1V Low Dropout
CC
the switch node voltage SW.
Regulator. The driver and control circuits are powered by
this supply. Must be decoupled to ground with a minimum
of 4.7μF ceramic or tantalum capacitor.
PGOOD1, PGOOD2 (Pins 24,12): Open-Drain Power
Good Outputs. The VOUT1, VFB2 pins are monitored to
ensure that V
are in regulation. When V
is not
OUT1,2
OUT
Rev. 0
9
For more information www.analog.com
LTC7802-3.3
PIN FUNCTIONS
within 10% of its regulation point, the corresponding
PGOOD pin is pulled low.
with this control voltage. Place compensation compo-
nents between the ITH pins and ground.
VOUT1, VFB2 (Pins 28,9): Controller Feedback Inputs.
TRACK/SS1, TRACK/SS2 (Pins 26,11): External Tracking
and Soft-Start Input. The LTC7802-3.3 regulates the nega-
tive input of the Error Amplifier (EA–) voltage to the lesser
of 0.8V or the voltage on the TRACK/SS1,2 pin. Internal
12.5µA pull-up current sources are connected to these
pins. A capacitor to ground sets the start-up ramp time to
the final regulated output voltage. The ramp time is equal
to 0.65ms for every 10nF of capacitance. Alternatively,
a resistor divider on another voltage supply connected
to the TRACK/SS pins allows the LTC7802-3.3 output to
track the other supply during start-up.
Connect V
directly to the channel 1 output voltage.
OUT1
Connect an external resistor divider between the channel 2
output voltage and the VFB2 pin to set the regulated VOUT2
voltage. Tie VFB2 to INTVCC to configure the channels for a
2-phase 3.3V output, in which both channels share VOUT1
,
ITH1, and TRACK/SS1.
GND (Exposed Pad Pin 29): Ground. Connects to the
sources of the bottom N-Channel MOSFETs and the (–)
terminal(s) of decoupling capacitors. The exposed pad
must be soldered to PCB ground for rated electrical and
thermal performance.
ITH1, ITH2 (Pins 27,10): Error Amplifier Outputs and
Switching Regulator Compensation Points. Each associ-
ated channel’s current comparator trip point increases
Rev. 0
10
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LTC7802-3.3
FUNCTIONAL DIAGRAM
ꢅꢑꢔꢌꢈꢊꢘꢉꢕ ꢞꢍR ꢆꢕꢊꢍꢏꢅ ꢊꢍꢏꢉRꢍꢌꢌꢕR ꢊꢋꢘꢏꢏꢕꢌ
Rꢑꢏ
ꢈꢏꢉꢐ
ꢊꢊ
ꢅ
ꢐ
ꢄ
ꢈꢏ
ꢄꢍꢍꢆꢉ
ꢉꢎ
–
ꢘꢌꢌꢍꢞꢞ
+
ꢒ.ꢂꢐ
ꢊ
ꢄ
ꢉꢍꢔ
ꢄꢍꢉ
ꢊ
ꢈꢏ
ꢞRꢕꢚ
ꢆꢔRꢕꢘꢅ
ꢆꢔꢕꢊꢉRꢑꢙ
ꢍꢆꢊꢈꢌꢌꢘꢉꢍR
ꢘꢏꢅ ꢔꢌꢌ
ꢊꢌꢠꢂ
ꢊꢌꢠꢒ
ꢅRꢍꢔꢍꢑꢉ
ꢅꢕꢉꢕꢊꢉ
ꢆꢇꢈꢉꢊꢋ
ꢌꢍꢎꢈꢊ
ꢔꢌꢌꢈꢏꢡꢆꢔRꢕꢘꢅ
ꢆ
R
ꢉꢍꢔ ꢍꢏ
ꢆꢇ
ꢚ
ꢈꢏꢉꢐ
ꢊꢊ
ꢄꢎ
+
–
0.ꢜꢂꢛꢐ
ꢆꢌꢕꢕꢔ
ꢔꢎꢏꢅ
ꢙꢍꢅꢕ
ꢒ00ꢤ
ꢈꢊꢙꢔ
ꢈR
ꢖ
ꢗ
ꢗ
ꢖ
ꢗ ꢖ
R
ꢆꢕꢏꢆꢕ
ꢌ
ꢖꢗ
ꢐ
ꢍꢑꢉꢒꢓꢂ
ꢗ
ꢂꢟꢐ
ꢆꢕꢏꢆꢕ
ꢊ
ꢍꢑꢉ
ꢖ
ꢆꢕꢏꢆꢕ
ꢆꢌꢍꢔꢕ ꢊꢍꢙꢔ
R
ꢐ
ꢞꢄ
ꢞꢒ
ꢖ
ꢗ
ꢗ
ꢕꢘ
0.ꢁꢐ
ꢞꢕꢕꢅꢄꢘꢊꢠ ꢅꢈꢐꢈꢅꢕR ꢈꢙꢔꢌꢕꢙꢕꢏꢉꢕꢅ
ꢈꢏꢉꢕRꢏꢘꢌꢌꢣ ꢞꢍR ꢊꢋꢘꢏꢏꢕꢌ ꢒ
R
ꢞꢂ
R
ꢊ
ꢈꢉꢋ
ꢐ
ꢈꢏ
ꢈꢉꢋ
ꢊꢌꢘꢙꢔ
ꢒ.ꢜꢐ
ꢊ
ꢊꢂ
ꢊ
ꢊꢒ
ꢕꢝꢉꢐ
ꢊꢊ
ꢒꢂ.ꢛꢢꢘ
ꢉRꢘꢊꢠꢡꢆꢆ
ꢔꢎꢍꢍꢅ
+
–
–
0.ꢁꢁꢐ
0.ꢀꢂꢐ
0ꢐ
ꢊ
ꢆꢆ
ꢘꢌꢌꢍꢞꢞ
ꢜ.ꢀꢐ
+
–
ꢕꢏ
–
ꢕꢏ
ꢛ.ꢒꢐ
ꢛ.ꢒꢐ
–
+
+
+
ꢕꢝꢉꢐ ꢌꢅꢍ
ꢊꢊ
ꢐ
ꢌꢅꢍ
ꢄꢈꢘꢆ
ꢈꢏꢉꢐ
ꢊꢊ
ꢀꢁ0ꢂꢃꢃ ꢄꢅ
Rev. 0
11
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LTC7802-3.3
OPERATION (Refer to Functional Diagram)
Main Control Loop
Each top MOSFET driver is biased from the floating boot-
strap capacitor C , which normally recharges during each
cycle through anBexternal diode when the switch voltage
goes low.
The LTC7802-3.3 is a dual step-down (buck) synchro-
nous controller utilizing a constant frequency, peak cur-
rent mode architecture. The two controller channels oper-
ate 180° out of phase which reduces the required input
capacitance and power supply induced noise. During
normal operation, the external top MOSFET is turned on
when the clock for that channel sets the SR latch, causing
the inductor current to increase. The main switch is turned
off when the main current comparator, ICMP, resets the SR
latch. After the top MOSFET is turned off each cycle, the
bottom MOSFET is turned on which causes the inductor
current to decrease until either the inductor current starts
to reverse, as indicated by the current comparator IR, or
the beginning of the next clock cycle.
If the input voltage decreases to a voltage close to its
output, the loop may enter dropout and attempt to turn
on the top MOSFET continuously. The dropout detector
detects this and forces the top MOSFET off for a short
time every tenth cycle to allow C to recharge, resulting in
a 99% duty cycle at 350kHz opeBration and approximately
98% duty cycle at 2MHz operation.
Start-Up and Shutdown (RUN and TRACK/SS Pins)
The two channels of the LTC7802-3.3 can be indepen-
dently shut down using the RUN1 and RUN2 pins. Pulling
a RUN pin below 1.1V shuts down the main control loop
for that channel. Pulling both RUN pins below 0.7V dis-
ables both controllers and most internal circuits, including
The peak inductor current at which ICMP trips and resets
the latch is controlled by the voltage on the ITH pin, which
is the output of the error amplifier EA. The error ampli-
fier compares the output voltage feedback signal at the
the INTV LDOs. In this shutdown state, the LTC7802-
CC
3.3 draws only 1.5μA of quiescent current.
V
pin, (which is generated with a resistor divider con-
FB
nected across the output voltage, V , to ground) to the
OUT
The RUN pins may be externally pulled up or driven
directly by logic. Each pin can tolerate up to 40V (abso-
internal 0.8V reference voltage. When the load current
increases, it causes a slight decrease in VFB relative to
the reference,which causes the EA to increase the ITH
voltage until the average inductor current matches the
new load current.
lute maximum), so it can be conveniently tied to V in
IN
always-on applications where one or both controllers are
enabled continuously and never shut down. Additionally,
a resistive divider from V to a RUN pin can be used to
IN
set a precise input undervoltage lockout so that the power
Power and Bias Supplies (V , EXTV , and INTV )
IN
CC
CC
supply does not operate below a user adjustable level.
The INTVCC pin supplies power for the top and bottom
MOSFET drivers and most of the internal circuitry. LDOs
(low dropout linear regulators) are available from both the
The start-up of each channel’s output voltage V
is con-
OUT
trolled by the voltage on the corresponding TRACK/SS
pin. When the voltage on the TRACK/SS pin is less than
the 0.8V internal reference voltage, the LTC7802-3.3 regu-
V and EXTV pins to provide power to INTV , which
IN
CC
CC
has a regulation point of 5.1V. When the EXTV pin is
CC
lates the V voltage to the TRACK/SS pin voltage instead
FB
left open or tied to a voltage less than 4.7V, the V LDO
IN
of the 0.8V reference voltage. This allows the TRACK/SS
pin to be used as a soft-start which smoothly ramps the
output voltage on start-up, thereby limiting the input sup-
ply inrush current. An external capacitor from the TRACK/
SS pin to GND is charged by an internal 12.5μA pull-up
current, creating a voltage ramp on the TRACK/SS pin. As
supplies power to INTV . If EXTV is taken above 4.7V,
CC
CC
the V LDO is turned off and the EXTV LDO is turned
IN
CC
on. Once enabled, the EXTVCC LDO supplies power to
INTV . Using the EXTV pin allows the INTV power
CC
CC
CC
to be derived from a high efficiency external source such
as one of the LTC7802-3.3 switching regulator outputs.
Rev. 0
12
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LTC7802-3.3
OPERATION
the TRACK/SS voltage rises linearly from 0V to 0.8V (and
beyond), the output voltage VOUT rises smoothly from
zero to its final value.
–
quiescent current is supplied by the SENSE1 pin, which
further reduces the input-referred quiescent current by
the ratio of V /V
multiplied by the efficiency.
IN OUT
Alternatively, the TRACK/SS pins can be used to make the
start-up of VOUT track that of another supply. Typically
this requires connecting to the TRACK/SS pin through an
external resistor divider from the other supply to ground
(see the Applications Information section).
In sleep mode, the load current is supplied by the output
capacitor. As the output voltage decreases, the EA’s out-
put begins to rise. When the output voltage drops enough,
the ITH pin is reconnected to the output of the EA, the
sleep signal goes low, and the controller resumes normal
operation by turning on the top MOSFET on the next cycle
of the internal oscillator.
Light Load Operation: Burst Mode Operation, Pulse-
Skipping, or Forced Continuous Mode (MODE Pin)
When a controller is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The reverse
current comparator (IR) turns off the bottom MOSFET
just before the inductor current reaches zero, preventing
it from reversing and going negative. Thus, the controller
operates in discontinuous operation.
The LTC7802-3.3 can be set to enter high efficiency
Burst Mode operation, constant frequency pulse-skipping
mode or forced continuous conduction mode at low load
currents.
To select Burst Mode operation, tie the MODE pin to
ground. To select forced continuous operation, tie the
In forced continuous operation the inductor current is
allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined by
the voltage on the ITH pin, just as in normal operation.
In this mode, the efficiency at light loads is lower than
in Burst Mode operation. However, continuous operation
has the advantage of lower output voltage ripple and less
interference to audio circuitry. In forced continuous mode,
the output ripple is independent of load current.
MODE pin to INTV . To select pulse-skipping mode, tie
CC
the MODE pin to a DC voltage greater than 1.2V and less
than INTV – 1.3V. An internal 100k resistor to ground
invokes BCuCrst Mode operation when the MODE pin is
floating and pulse-skipping mode when the MODE pin is
tied to INTV through an external 100k resistor.
CC
When the controllers are enabled for Burst Mode opera-
tion, the minimum peak current in the inductor is set to
approximately 25% of its maximum value even though
the voltage on the ITH pin might indicate a lower value. If
the average inductor current is higher than the load cur-
rent, the error amplifier EA will decrease the voltage on
the ITH pin. When the ITH voltage drops below 0.425V,
the internal sleep signal goes high (enabling sleep mode)
and both external MOSFETs are turned off. The ITH pin is
then disconnected from the output of the EA and parked
at 0.45V.
When the MODE pin is connected for pulse-skipping
mode, the LTC7802-3.3 operates in PWM pulse-skipping
mode at light loads. In this mode, constant frequency
operation is maintained down to approximately 1% of
designed maximum output current. At very light loads, the
current comparator ICMP may remain tripped for several
cycles and force the top MOSFET to stay off for the same
number of cycles (i.e., skipping pulses). The inductor cur-
rent is not allowed to reverse (discontinuous operation).
This mode, like forced continuous operation, exhibits low
output ripple as well as low audio noise and reduced RF
interference as compared to Burst Mode operation. It pro-
vides higher low current efficiency than forced continuous
mode, but not nearly as high as Burst Mode operation.
In sleep mode, much of the internal circuitry is turned
off, reducing the quiescent current that the LTC7802-3.3
draws. If one channel is in sleep mode and the other chan-
nel is shut down, the LTC7802-3.3 draws only 15μA of
quiescent current. If both channels are in sleep mode, the
LTC7802-3.3 draws only 20μA of quiescent current. When
Unlike forced continuous mode and pulse-skipping mode,
Burst Mode cannot be synchronized to an external clock.
V
on channel 1 is 3.2V or higher, the majority of this
OUT
Rev. 0
13
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LTC7802-3.3
OPERATION
Therefore, if Burst Mode is selected and the switching
frequency is synchronized to an external clock applied to
the PLLIN/SPREAD pin, the LTC7802-3.3 switches from
Burst Mode to forced continuous mode.
approximately the frequency of the external clock. The
LTC7802-3.3’s PLL is guaranteed to lock to an external
clock source whose frequency is between 100kHz and
3MHz.
The PLLIN/SPREAD pin is TTL compatible with thresholds
of 1.6V (rising) and 1.1V (falling) and is guaranteed to
operate with a clock signal swing of 0.5V to 2.2V.
Frequency Selection, Spread Spectrum, and Phase-
Locked Loop (FREQ and PLLIN/SPREAD Pins)
The free running switching frequency of the LTC7802-
3.3 controllers is selected using the FREQ pin. Tying
FREQ to GND selects 350kHz while tying FREQ to INTV
selects 2.25MHz. Placing a resistor between FREQ and
GND allows the frequency to be programmed between
100kHz and 3MHz.
Output Overvoltage Protection
CC
Each channel has an overvoltage comparator that guards
against transient overshoots as well as other more serious
conditions that may overvoltage the output. When the
V
, V
OUT1 FB2
pin rises more than 10% above its regula-
Switching regulators can be particularly troublesome for
applications where electromagnetic interference (EMI) is
a concern. To improve EMI, the LTC7802-3.3 can oper-
ate in spread spectrum mode, which is enabled by tying
tion point, the top MOSFET is turned off and the bottom
MOSFET is turned on until the overvoltage condition is
cleared.
Foldback Current
the PLLIN/SPREAD pin to INTV . This feature varies the
CC
switching frequency within typical boundaries of –12% to
+15% of the frequency set by the FREQ pin.
When the output voltage falls to less than 50% of its
nominal level, foldback current limiting is activated, pro-
gressively lowering the peak current limit in proportion to
the severity of the overcurrent or short-circuit condition.
Foldback current limiting is disabled during the soft-start
A phase-locked loop (PLL) is available on the LTC7802-
3.3 to synchronize the internal oscillator to an external
clock source connected to the PLLIN/SPREAD pin. The
LTC7802-3.3’s PLL aligns the turn-on of controller 1’s
external top MOSFET to the rising edge of the synchroniz-
ing signal. Thus, the turn-on of controller 2’s external top
MOSFET is 180° out-of-phase to the rising edge of the
external clock source.
interval (as long as the V voltage is keeping up with the
FB
TRACK/SS1,2 voltage).
Power Good
Each channel has a PGOOD pin that is connected to an
open drain of an internal N-channel MOSFET. The MOSFET
The PLL frequency is prebiased to the free running fre-
quency set by the FREQ pin before the external clock is
applied. If prebiased near the external clock frequency,
the PLL only needs to make slight changes in order to
synchronize the rising edge of the external clock to the
rising edge of TG1. For more rapid lock-in to the external
clock, use the FREQ pin to set the internal oscillator to
turns on and pulls the PGOOD pin low when the V volt-
FB
age is not within 10% of the 0.8V reference. The PGOOD
pin is also pulled low when the RUN pin is low (shut
down). When the V voltage is within the 10% require-
FB
ment, the MOSFET is turned off and the pin is allowed to
be pulled up by an external resistor to a source no greater
than 6V, such as INTV .
CC
Rev. 0
14
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LTC7802-3.3
APPLICATIONS INFORMATION
The Typical Application on the first page is a basic
LTC7802-3.3 application circuit. External component
selection is largely driven by the load requirement and
begins with the selection of the inductor, current sense
components, operating frequency, and light load oper-
ating mode. The remaining power stage components,
consisting of the input and output capacitors, and power
MOSFETs can then be chosen. Next, feedback resistors
are selected to set the desired output voltage. Then, the
remaining external components are selected, such as for
soft-start, biasing, and loop compensation.
lower load currents, which can cause a dip in efficiency
in the upper range of low current operation.
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High efficiency regulators generally can-
not afford the core loss found in low cost powdered
iron cores, forcing the use of more expensive ferrite or
molypermalloy cores. Actual core loss is very dependent
on inductance value selected. As inductance increases,
core losses go down. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
Inductor Value Calculation
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because
of MOSFET switching and gate charge losses. In addi-
tion to this basic trade-off, the effect of inductor value
on ripple current and low current operation must also
be considered. The inductor value has a direct effect on
ripple current.
Ferrite designs have very low core loss and are preferred
for high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates hard, which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Current Sense Selection
The LTC7802-3.3 can be configured to use either DCR
(inductor resistance) sensing or low value resistor sens-
ing. The choice between the two current sensing schemes
is largely a design trade-off between cost, power con-
sumption and accuracy. DCR sensing has become popular
because it saves expensive current sensing resistors and
is more power efficient, particularly in higher current and
lower frequency applications. However, current sensing
resistors provide the most accurate current limits for the
controller. Other external component selection is driven
by the load requirement and begins with the selection of
The maximum average inductor current I
is equal
L(MAX)
to the maximum output current. The peak current is equal
to the average inductor current plus half of the inductor
ripple current, ΔI , which decreases with higher induc-
L
tance or higher frequency and increases with higher V :
IN
⎛
⎜
⎝
⎞
⎟
⎠
ꢂ
ꢆ
ꢇꢈꢉ
Δꢀ =
ꢆ
ꢂ−
ꢁ
ꢇꢈꢉ
ꢃꢄꢅꢃꢁꢅ
ꢆ
ꢀꢊ
Accepting larger values of ΔIL allows the use of low induc-
tances, but results in higher output voltage ripple and
greater core losses. A reasonable starting point for setting
ripple current is ΔIL = 0.3 • IL(MAX). The maximum ΔIL
occurs at the maximum input voltage.
R
SENSE
(if R
is used) and inductor value.
SENSE
+
–
The SENSE and SENSE pins are the inputs to the cur-
rent comparators. The common mode voltage range on
these pins is 0V to 40V (absolute maximum), enabling the
LTC7802-3.3 to regulate output voltages up to a maxi-
The inductor value also has secondary effects. The tran-
sition to Burst Mode operation begins when the average
inductor current required results in a peak current below
25% of the current limit determined by RSENSE. Lower
+
mum of 40V. The SENSE pin is high impedance, drawing
less than ≈1μA. This high impedance allows the current
comparators to be used in inductor DCR sensing. The
inductor values (higher ΔI ) will cause this to occur at
L
Rev. 0
15
For more information www.analog.com
LTC7802-3.3
APPLICATIONS INFORMATION
–
Using the maximum inductor current (I
) and ripple
impedance of the SENSE pin changes depending on the
L(MAX)
current (ΔI ) from the Inductor Value Calculation section,
common mode voltage. When less than INTV – 0.5V,
L
CC
the target sense resistor value is:
these pins are relatively high impedance, drawing ≈ 1μA.
When above INTV + 0.5V, a higher current (≈650μA)
CC
V
SENSE(MAX)
flows into each pin. Between INTV – 0.5V and INTV
R
≤
CC
CC
SENSE(EQUIV)
� I
L
+ 0.5V, the current transitions from the smaller current to
the higher current. Channel 1’s SENSE1– pin has an addi-
tional ≈ 50μA current when its voltage is above 3.2V to
I
+
L(MAX)
2
To ensure that the application will deliver full load cur-
rent over the full operating temperature range, choose
the minimum value for VSENSE(MAX) in the Electrical
Characteristics table.
bias internal circuitry from V
reducing the input-referred supply current.
instead of V , thereby
OUT1
IN
Filter components mutual to the sense lines should be
placed close to the LTC7802-3.3, and the sense lines
should run close together to a Kelvin connection under-
neath the current sense element (shown in Figure 1).
Sensing current elsewhere can effectively add parasitic
inductance and capacitance to the current sense ele-
ment, degrading the information at the sense terminals
and making the programmed current limit unpredictable.
If DCR sensing is used (Figure 2b), resistor R1 should be
placed close to the switching node, to prevent noise from
coupling into sensitive small signal nodes.
To avoid potential jitter or instability due to PCB noise cou-
pling into the current sense signal, the AC current sensing
ripple of ΔV
= Δ • R
should also be checked
SENSE
IL
SENSE
to ensure a good signal-to-noise ratio. In general, for a
reasonably good PCB layout, a target ΔV voltage of
SENSE
10mV to 20mV at nominal input voltage is recommended
for both R and DCR sensing applications.
SENSE
The parasitic inductance (ESL) of the sense resistor
introduces significant error in the current sense signal
for lower inductor value (<3μH) or higher current (>5A)
applications. This error is proportional to input voltage
and may degrade line regulation or cause loop instability.
An RC filter into the sense pins, as shown in Figure 2a, can
be used to compensate for this error. Set the RC filter time
ꢆꢇ ꢈꢉꢊꢈꢉ ꢄꢋꢌꢆꢉR
ꢊꢉꢍꢆ ꢆꢇ ꢆꢎꢉ ꢏꢇꢊꢆRꢇꢌꢌꢉR
ꢏꢑRRꢉꢊꢆ ꢄꢌꢇꢒ
constant R • C = ESL/R for optimal cancellation of
F
F
SENSE
ꢀꢁ0ꢂꢃꢃ ꢄ0ꢅ
the ESL. In general, select C to be in the range of 1nF to
F
ꢋꢊꢐꢑꢏꢆꢇR ꢇR R
ꢈꢉꢊꢈꢉ
10nF and calculate the corresponding R . Surface mount
F
Figure 1. Sense Lines Placement with Inductor or
Sense Resistor
sense resistors in low ESL wide footprint geometries are
recommended to minimize this error. If not specified on
the manufacturer’s data sheet, the ESL can be approxi-
mated as 0.4nH for a resistor with a 1206 footprint and
0.2nH for a 1225 footprint.
Low Value Resistor Current Sensing
A typical sensing circuit using a discrete resistor is shown
in Figure 2a. R
is chosen based on the required out-
SENSE
Inductor DCR Current Sensing
put current. Each controller’s current comparator has a
maximum threshold VSENSE(MAX) of 50mV. The current
comparator threshold voltage sets the peak inductor
current.
For applications requiring the highest possible efficiency
at high load currents, the LTC7802-3.3 is capable of sens-
ing the voltage drop across the inductor DCR, as shown in
Figure 2b. The DCR of the inductor represents the small
amount of DC winding resistance of the copper, which
can be less than 1mΩ for today’s low value, high current
Rev. 0
16
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LTC7802-3.3
APPLICATIONS INFORMATION
ꢀ
DCR of the inductor must be known. It can be measured
using a good RLC meter, but the DCR tolerance is not
always the same and varies with temperature; consult
the manufacturers’ data sheets for detailed information.
ꢀꢁꢂꢃꢄ
ꢀꢁ
ꢀꢁꢂꢀꢁ RꢁꢀꢃꢀꢄꢅR
ꢀꢁꢂꢃ ꢄꢅRꢅꢆꢁꢂꢁꢇ
ꢀꢁꢁꢂꢃ
ꢀꢁꢂꢃꢄꢅꢆꢁꢄꢇ
R
ꢀꢁꢂꢀꢁ
ꢀ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢂꢃꢄ0ꢅꢆꢇ.ꢇ
ꢀꢁ
ꢀ
ꢀꢁꢂꢃꢄꢅ
R ꢀꢁ ꢀ ꢁꢂꢃꢄR
ꢀꢁꢂꢀꢁ
Using the maximum inductor current (I
) and ripple
ꢀ
ꢀ
current (ΔI ) from the Inductor ValueL(CMaAlcXu) lation sec-
ꢀꢁꢂꢃꢄꢅꢃRꢁ
ꢀꢁꢂꢀꢃꢄꢄꢁꢅꢆꢇꢂ
L
R
tion, the target sense resistor value is calculated from the
nominal inductance, C1 value, and DCR:
ꢀ
ꢆ
ꢀꢁꢂꢀꢁꢃꢄꢅ
ꢀ
ꢀ
ꢆ
V
ꢀꢁꢂꢀꢁꢃꢄꢅ
SENSE(MAX)
ꢀꢁꢂꢃꢄ R ꢀꢁꢂ ꢃ ꢀꢁꢂR ꢃꢁꢀꢃꢁ ꢄꢅꢀꢃ
ꢀ
ꢀ
R
≤
SENSE(EQUIV)
ꢀꢁ0ꢂꢃꢃ ꢄ0ꢂꢅ
� I
L
I
+
L(MAX)
2
(2a) Using a Resistor to Sense Current
To ensure that the application will deliver full load cur-
rent over the full operating temperature range, choose
the minimum value for VSENSE(MAX) in the Electrical
Characteristics table.
ꢖ
ꢗꢐꢑꢒꢂ
ꢊꢋꢋꢌꢇ
ꢇꢍ
ꢗꢐꢕꢘꢈꢇꢋR
ꢕꢈR
ꢆꢇꢈꢀꢁ0ꢂꢉꢃ.ꢃ
ꢆ
Next, determine the DCR of the inductor. When provided,
use the manufacturer’s maximum value, usually given at
20°C. Increase this value to account for the temperature
coefficient of copper resistance, which is approximately
ꢖ
ꢌꢎ
ꢋꢘꢇꢑꢒꢂ
ꢊꢍ
Rꢑ
ꢓ
ꢌꢏꢐꢌꢏꢑꢒ ꢂ
0.4%/°C. A conservative value for T
is 100°C. To
L(MAX)
ꢈꢑꢙ
Rꢂ
scale the maximum inductor DCR to the desired sense
ꢔ
ꢌꢏꢐꢌꢏꢑꢒ ꢂ
resistor value, use the divider ratio:
ꢍꢐꢕ
ꢀꢁ0ꢂꢃꢃ ꢄ0ꢂꢅ
R
SENSE(EQUIV)
ꢜRꢑꢡꢡRꢂꢞ ꢢ ꢈꢑ ꢟ ꢆꢠꢕꢈR
R ꢟ ꢕꢈRꢜRꢂꢠꢜRꢑꢓRꢂꢞꢞ
ꢌꢏꢐꢌꢏꢜꢏꢝꢞ
R =
D
ꢙꢚꢆꢛꢈꢏ ꢈꢑ ꢐꢏꢛR ꢌꢏꢐꢌꢏ ꢚꢗꢐꢌ
DCR
at T
L(MAX)
MAX
(2b) Using the Inductor DCR to Sense Current
Figure 2. Current Sensing Methods
C1 is usually selected to be in the range of 0.1μF to 0.47μF.
This forces R1||R2 to around 2k, reducing error that might
+
have been caused by the SENSE pin’s ≈1μA current.
The target equivalent resistance R1||R2 is calculated from
the nominal inductance, C1 value, and DCR:
inductors. In a high current application requiring such
an inductor, power loss through a sense resistor would
cost several points of efficiency compared to inductor
DCR sensing.
L
R1 R2 =
(DCR at 20°C) • C1
If the external (R1||R2) • C1 time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across the external capacitor is equal to the drop across
the inductor DCR multiplied by R2/(R1+R2). R2 scales the
voltage across the sense terminals for applications where
the DCR is greater than the target sense resistor value.
To properly dimension the external filter components, the
The sense resistor values are:
R1 R2
R1• R
D
R1=
; R2 =
R
1� R
D
D
Rev. 0
17
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LTC7802-3.3
APPLICATIONS INFORMATION
The maximum power loss in R1 is related to duty cycle and
Tying the FREQ pin to ground selects 350kHz while tying
FREQ to INTVCC selects 2.25MHz. Placing a resistor
between FREQ and ground allows the frequency to be pro-
grammed anywhere between 100kHz and 3MHz. Choose a
FREQ pin resistor from Figure 3 or the following equation:
occurs in continuous mode at the maximum input voltage:
(V
� V
) • V
IN(MAX)
OUT OUT
P
R1=
LOSS
R1
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing
or sense resistors. Light load power loss can be mod-
estly higher with a DCR network than with a sense resis-
tor, due to the extra switching losses incurred through
R1. However, DCR sensing eliminates a sense resistor,
reduces conduction losses and provides higher efficiency
at heavy loads. Peak efficiency is about the same with
either method.
37MHz
R
(in kΩ) =
FREQ
f
OSC
ꢀ0ꢁ
ꢀꢁ
Setting the Operating Frequency
Selection of the operating frequency is a trade-off between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing gate charge and transition losses, but requires
larger inductance values and/or more output capacitance
to maintain low output ripple voltage.
ꢀ00ꢁ
ꢀ0ꢁ
ꢀ00ꢁ
ꢀRꢁꢂ ꢃꢄꢅ RꢁꢆꢄꢆꢇꢈR ꢉꢈꢊꢋꢌꢍ
ꢀ00ꢁ
ꢀꢁ0ꢂꢃꢃ ꢄ0ꢃꢅ
Figure 3. Relationship Between Oscillator Frequency and
Resistor Value at the FREQ Pin
To improve electromagnetic interference (EMI) perfor-
mance, spread spectrum mode can optionally be selected
by tying the PLLIN/SPREAD pin to INTV . When spread
spectrum is enabled, the switching frequency modulates
within −12% to +15% of the frequency selected by the
FREQ pin. Spread spectrum may be used in any operat-
ing mode selected by the MODE pin (Burst Mode, pulse-
skipping, or forced continuous mode).
In higher voltage applications transition losses contrib-
ute more significantly to power loss, and a good balance
between size and efficiency is generally achieved with a
switching frequency between 300kHz and 900kHz. Lower
voltage applications benefit from lower switching losses
and can therefore more readily operate at higher switch-
ing frequencies up to 3MHz if desired. The switching fre-
quency is set using the FREQ and PLLIN/SPREAD pins
as shown in Table 1
CC
A phase-locked loop (PLL) is also available on the
LTC7802-3.3 to synchronize the internal oscillator to an
external clock source connected to the PLLIN/SPREAD
pin. After the PLL locks, TG1 is synchronized to the ris-
ing edge of the external clock signal, and TG2 is 180°
out of phase from TG1. See the Phase-Locked Loop and
Frequency Synchronization section for details.
Table 1.
FREQ PIN
PLLIN/SPREAD PIN
FREQUENCY
350kHz
0V
0V
0V
0V
INTV
2.25MHz
CC
Resistor to GND
Any of the Above
100kHz to 3MHz
External Clock 100kHz Phase-Locked to
to 3MHz
External lock
Any of the Above
INTV
Spread Spectrum
Modulated
CC
Rev. 0
18
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LTC7802-3.3
APPLICATIONS INFORMATION
In pulse-skipping mode, constant frequency operation
is maintained down to approximately 1% of designed
maximum output current. At very light loads, the PWM
comparator may remain tripped for several cycles and
force the top MOSFET to stay off for the same number of
cycles (i.e., skipping pulses). The inductor current is not
allowed to reverse (discontinuous operation). This mode,
like forced continuous operation, exhibits low output rip-
ple as well as low audio noise and reduced RF interference
as compared to Burst Mode operation. It provides higher
light load efficiency than forced continuous mode, but not
nearly as high as Burst Mode operation. Consequently,
pulse-skipping mode represents a compromise between
light load efficiency, output ripple and EMI.
Selecting the Light-Load Operating Mode
The LTC7802-3.3 can be set to enter high efficiency Burst
Mode operation, constant frequency pulse-skipping mode
or forced continuous conduction mode at light load cur-
rents. To select Burst Mode operation, tie the MODE to
ground. To select forced continuous operation, tie the
MODE pin to INTVCC. To select pulse-skipping mode,
tie the MODE pin to INTVCC through a 100k resistor.
An internal 100k resistor from the MODE pin to ground
selects Burst Mode if the pin is floating. When synchro-
nized to an external clock through the PLLIN/SPREAD
pin, the LTC7802-3.3 operates in pulse-skipping mode
if it is selected, or in forced continuous mode otherwise.
Table 2. summarizes the use of the MODE pin to select
the light load operating mode.
In some applications, it may be desirable to change light
load operating mode based on the conditions present in
the system. For example, if a system is inactive, one might
select high efficiency Burst Mode operation by keeping the
MODE pin set to 0V. When the system wakes, one might
send an external clock to PLLIN/SPREAD, or tie MODE to
INTV to switch to low noise forced continuous mode.
SuchCCon-the-fly mode changes can allow an individual
application to benefit from the advantages of each light
load operating mode.
Table 2.
LIGHT-LOAD
OPERATING MODE
MODE WHEN
SYNCHRONIZED
MODE PIN
0V or Floating
Burst Mode
Forced Continuous
Pulse-Skipping
100k to INTV
Pulse-Skipping
Forced Continuous
CC
INTV
Forced Continuous
CC
In general, the requirements of each application will
dictate the appropriate choice for light-load operating
mode. In Burst Mode operation, the inductor current is
not allowed to reverse. The reverse current comparator
turns off the bottom MOSFET just before the inductor
current reaches zero, preventing it from reversing and
going negative. Thus, the regulator operates in discon-
tinuous operation. In addition, when the load current is
very light, the inductor current will begin bursting at fre-
quencies lower than the switching frequency and enter a
low current sleep mode when not switching. As a result,
Burst Mode operation has the highest possible efficiency
at light load.
Power MOSFET Selection
Two external power MOSFETs must be selected for each
controller in the LTC7802-3.3: one N-channel MOSFET
for the top (main) switch and one N-channel MOSFET
for the bottom (synchronous) switch. The peak-to-peak
gate drive levels are set by the INTV regulation point of
CC
5.1V. Consequently, logic level threshold MOSFETs must
be used in most applications. Pay close attention to the
BV
specification for the MOSFETs as well; many of the
logDicSSlevel MOSFETs are limited to 30V or less.
In forced continuous mode, the inductor current is
allowed to reverse at light loads and switches at the same
frequency regardless of load. In this mode, the efficiency
at light loads is considerably lower than in Burst Mode
operation. However, continuous operation has the advan-
tage of lower output voltage ripple and less interference
to audio circuitry. In forced continuous mode, the output
ripple is independent of load current.
Selection criteria for the power MOSFETs include the on
resistance RDS(ON), Miller capacitance CMILLER, input volt-
age, and maximum output current. Miller capacitance,
C
, can be approximated from the gate charge curve
MILLER
usually provided on the MOSFET manufacturers’ data
sheet. CMILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
flat divided by the specified change in V . This result is
DS
Rev. 0
19
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LTC7802-3.3
APPLICATIONS INFORMATION
then multiplied by the ratio of the application applied V
to the gate charge curve specified VDS. When the ICDisS
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
C and C
Selection
IN
OUT
The selection of C is simplified by the 2-phase archi-
IN
tecture and its impact on the worst-case RMS current
drawn through the input network (battery/fuse/capacitor).
It can be shown that the worst-case capacitor RMS cur-
rent occurs when only one controller is operating. The
ꢏ
ꢐꢊꢆ
ꢀꢁꢂꢃ ꢄꢅꢂꢆꢇꢈ ꢉꢊꢆꢋ ꢇꢋꢇꢌꢍ ꢎ
ꢏ
controller with the highest V
• I
product needs to
OUT OUT
ꢂꢃ
be used in the equation below to determine the maximum
RMS capacitor current requirement.
ꢏ
ꢑ ꢏ
ꢐꢊꢆ
ꢂꢃ
ꢄꢋꢃꢇꢈRꢐꢃꢐꢊꢄ ꢄꢅꢂꢆꢇꢈ ꢉꢊꢆꢋ ꢇꢋꢇꢌꢍ ꢎ
ꢏ
ꢂꢃ
Increasing the output current drawn from the other con-
troller will actually decrease the input RMS ripple current
from its maximum value. The out-of-phase technique typi-
cally reduces the input capacitor’s RMS ripple current by
a factor of 30% to 70% when compared to a single-phase
power supply solution.
The MOSFET power dissipations at maximum output cur-
rent are given by:
ꢊ
ꢅ
ꢆꢇꢈ
ꢀ
=
ꢃ
(
ꢋ+ δ R
+
(
)
)
ꢁꢂꢃꢄ
ꢁꢂꢉ
ꢌꢍꢎꢆꢄꢏ
ꢅ
ꢃꢄ
⎛
⎜
⎝
⎞
⎟
⎠
ꢃ
In continuous mode, the source current of the top
ꢁꢂꢉ
ꢊ
ꢎꢅ ꢏ
ꢎR ꢏꢎꢐ
ꢏ ꢓ
ꢃꢄ
ꢌR
ꢁꢃꢑꢑꢒR
MOSFET is a square wave of duty cycle V /V . To pre-
OUT IN
ꢊ
vent large voltage transients, a low ESR capacitor sized
for the maximum RMS current of one channel must be
used. At maximum load current IMAX, the maximum RMS
capacitor current is given by:
⎡
⎢
⎣
⎤
ꢋ
ꢋ
+
ꢎꢕꢏ
⎥
⎦
ꢅ
− ꢅ
ꢅ
ꢈꢔꢁꢃꢄ
ꢈꢔꢁꢃꢄ
ꢃꢄꢈꢅꢐꢐ
ꢊ
ꢅ − ꢅ
ꢃꢄ
ꢆꢇꢈ
ꢀ
=
ꢃ
ꢋ+ δ R
ꢌꢍꢎꢆꢄꢏ
(
)
(
)
ꢍꢖꢄꢐ
ꢁꢂꢉ
I
ꢅ
1/2
MAX
ꢃꢄ
�
�
C
Required I
�
V
V � V
IN
OUT
(
) (
)
�
�
IN
RMS
OUT
V
IN
where δ is the temperature dependency of R
(δ ≈
DS(ON)
This formula has a maximum at V = 2V , where I
RMS
IN
OUT
0.005/°C) and R is the effective driver resistance at the
DR
= I /2. This simple worst-case condition is commonly
OUT
MOSFET’s Miller threshold voltage (R ≈ 2Ω). V
is
the typical MOSFET minimum threshold voltage.THMIN
DR
used for design because even significant deviations do
not offer much relief. Note that capacitor manufacturers’
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the capaci-
tor, or to choose a capacitor rated at a higher temperature
than required. Several capacitors may be paralleled to
meet size or height requirements in the design. Due to
the high operating frequency of the LTC7802-3.3, ceramic
2
Both MOSFETs have I R losses while the main N-channel
equations include an additional term for transition losses,
which are highest at high input voltages. For V < 20V
IN
the high current efficiency generally improves with larger
MOSFETs, while for V > 20V the transition losses rap-
IN
idly increase to the point that the use of a higher R
DS(ON)
device with lower C
actually provides higher effi-
MILLER
capacitors can also be used for C . Always consult the
IN
ciency. The synchronous MOSFET losses are greatest at
high input voltage when the top switch duty factor is low
or during a short-circuit when the synchronous switch is
on close to 100% of the period.
manufacturer if there is any question.
The benefit of the LTC7802-3.3 2-phase operation can
be calculated by using this equation for the higher power
controller and then calculating the loss that would have
resulted if both controller channels switched on at the
same time. The total RMS power lost is lower when both
controllers are operating due to the reduced overlap of
Rev. 0
20
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LTC7802-3.3
APPLICATIONS INFORMATION
ꢊ
current pulses required through the input capacitor’s
ESR. This is why the input capacitor’s requirement cal-
culated above for the worst-case controller is adequate
for the dual controller design. Also, the input protection
fuse resistance, battery resistance, and PC board trace
resistance losses are also reduced due to the reduced
peak currents in a 2-phase system. The overall benefit of
a multiphase design will only be fully realized when the
source impedance of the power supply/battery is included
in the efficiency testing.
ꢍꢎꢇ
R
ꢋ
ꢈ
ꢄꢄ
ꢆꢇꢈꢀꢁ0ꢂꢉꢃ.ꢃ
ꢊ
ꢄꢋꢂ
R
ꢌ
ꢀꢁ0ꢂꢃꢃ ꢄ0ꢅ
Figure 4. Setting Channel 2 Output Voltage
Place resistors R and R very close to the V pin to
FB2
A
B
The drains of the top MOSFETs should be placed within
minimize PCB trace length and noise on the sensitive V
FB2
1cm of each other and share a common C (s). Separating
IN
node. Great care should be taken to route the V trace
FB2
the drains and C may produce undesirable resonances
IN
away from noise sources, such as the inductor or the
at V .
IN
SW trace. To improve frequency response, a feedforward
capacitor (C ) may be used.
A small (0.1μF to 1μF) bypass capacitor between the chip
FF
V pin and ground, placed close to the LTC7802-3.3, is
IN
RUN Pins and Undervoltage Lockout
also suggested. An optional 1Ω to 10Ω resistor placed
between CIN and the VIN pin provides further isolation
from a noisy input supply.
The two channels of the LTC7802-3.3 are enabled using
the RUN1, and RUN2 pins. The RUN pins have a rising
threshold of 1.2V with 100mV of hysteresis. Pulling a
RUN pin below 1.1V shuts down the main control loop
and resets the soft-start for that channel. Pulling both
RUN pins below 0.7V disables the controllers and most
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
output ripple (ΔV ) is approximated by:
OUT
internal circuits, including the INTV LDOs. In this state,
the LTC7802-3.3 draws only ≈1.5μA of quiescent current.
CC
⎛
⎞
ꢈ
Δꢀ
≈ Δꢄ ꢆꢇR +
⎜
ꢅ
⎟
ꢁꢂꢃ
ꢉꢊꢋ
⎝
⎠
ꢁꢂꢃ
The RUN pins are high impedance and must be externally
pulled up/down or driven directly by logic. Each RUN pin
can tolerate up to 40V (absolute maximum), so it can be
where f is the operating frequency, C
is the output
OUT
capacitance and ΔI is the ripple current in the inductor.
conveniently tied to V in always-on applications where
The output ripple iLs highest at maximum input voltage
IN
the controller is enabled continuously and never shut
since ΔI increases with input voltage.
down. Do not float the RUN pins.
L
The RUN pins can also be configured as precise under-
voltage lockouts (UVLOs) on the input supply with a resis-
Setting the Output Voltage
For channel 1, directly connect the LTC7802-3.3’s V
OUT1
tor divider from V to ground, as shown in Figure 5.
IN
pin to the output to regulate the output voltage to 3.3V.
For channel 2, the output voltage is set by an external
feedback resistor divider carefully placed across the out-
put, as shown in Figure 4. The regulated output voltage
is determined by:
The V UVLO thresholds can be computed as:
IN
⎛
R ⎞
ꢉ
ꢀꢁꢂꢃ Rꢄꢅꢄꢆꢇ ꢈ ꢉ.ꢊꢁ ꢉ+
⎜
⎟
R
⎝
⎛
⎠
ꢊ
R ⎞
ꢉ
ꢀꢁꢂꢃ ꢋꢌꢂꢂꢄꢆꢇ ꢈ ꢉ.ꢉꢁ ꢉ+
⎜
⎟
⎛
R ⎞
ꢇ
R
⎝
⎠
ꢀ
= 0.ꢅꢀ ꢆ+
ꢊ
⎜
⎟
ꢁꢂꢃꢄ
R
⎝
⎠
ꢈ
Rev. 0
21
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LTC7802-3.3
APPLICATIONS INFORMATION
Figure 7. During start-up V
will track V according to
X
ꢎ
OUT
ꢏꢍ
the ratio set by the resistor divider:
ꢆꢇꢂ ꢈꢉꢊꢀꢁ0ꢂꢋꢃ.ꢃ
Rꢌꢍ
Rꢆ
V
R
R
TRACKA
+ R
X
A
TRACKB
R + R
A B
=
•
Rꢂ
V
R
OUT
TRACKA
ꢀꢁ0ꢂꢃꢃ ꢄ0ꢅ
Set R
= R and R
X
= R for coincident track-
TRACKB B
TRACKA
A
Figure 5. Using the RUN Pins As a UVLD
ing (V
= V during start-up).
OUT
The current that flows through the R1-R2 divider directly
adds to the shutdown, sleep, and active current of the
LTC7802-3.3, and care should be taken to minimize the
impact of this current on the overall efficiency of the appli-
cation circuit. Resistor values in the MΩ range may be
required to keep the impact on quiescent shutdown and
sleep currents low.
ꢆ
ꢆ
ꢇꢈꢉꢊꢋꢌꢍRꢎ
ꢏꢐꢌꢈꢋꢑꢊꢆꢍꢎ
Soft-Start and Tracking (TRACK/SS Pins)
ꢀꢁ0ꢂꢃꢃ ꢄ0ꢀꢅ
ꢌꢓꢉꢍ
The start-up of each V
is controlled by the voltage on
OUT
(a) Coincident Tracking
the TRACK/SS pin (TRACK/SS1 for channel 1, TRACK/SS2
for channel 2). When the voltage on the TRACK/SS pin
is less than the internal 0.8V reference, the LTC7802-3.3
regulates the negative input of the Error Amplifier (EA–)
to the voltage on the TRACK/SS pin instead of the internal
reference. The TRACK/SS pin can be used to program
ꢆ
ꢆ
ꢇꢈꢉꢊꢋꢌꢍRꢎ
ꢏꢐꢌꢈꢋꢑꢊꢆꢍꢎ
an external soft-start function or to allow V
another supply during start-up.
to track
OUT
Soft-start is enabled by simply connecting a capacitor
from the TRACK/SS pin to ground. An internal 12.5μA cur-
rent source charges the capacitor, providing a linear ramp-
ing voltage at the TRACK/SS pin. The LTC7802-3.3 will
ꢀꢁ0ꢂꢃꢃ ꢄ0ꢀꢅ
ꢌꢓꢉꢍ
(b) Ratiometric Tracking
Figure 6. Two Different Modes of Output Voltage Tracking
regulate V
proportional to the voltage on the TRACK/
OUT
ꢉ
ꢑꢒꢅ
SS pin, allowing VOUT to rise smoothly from 0V to its final
regulated value. For a desired soft-start time, t , select a
SS
R
ꢊ
ꢋ
soft-start capacitor C = t • 15μF/sec.
SS
SS
ꢉ
ꢃꢊ
Alternatively, the TRACK/SS pins can be used to track two
or more supplies during start-up, as shown qualitatively
in Figure 6a and Figure 6b. To do this, a resistor divider
should be connected from the master supply (V ) to the
TRACK/SS pin of the slave supply (VOUT), as sXhown in
R
ꢉ
ꢓ
ꢄꢅꢆꢀꢁ0ꢇꢈꢂ.ꢂ
R
R
ꢅRꢋꢆꢌꢊ
ꢅRꢋꢆꢌꢋ
ꢅRꢋꢆꢌꢍꢎꢎꢏꢐꢇ
ꢀꢁ0ꢂꢂ ꢃ0ꢁ
Figure 7. Using the TRACK/SS Pin for Tracking
Rev. 0
22
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LTC7802-3.3
APPLICATIONS INFORMATION
Single Output 2-Phase Operation
equations given in Note 2 of the Electrical Characteristics.
For example, the LTC7802-3.3 INTV current is limited
CC
For high power 3.3V output applications, the two channels
can be operated in a 2-phase single output configuration.
The channels switch 180° out-of-phase, which reduces
the required output capacitance in addition to the required
input capacitance and power supply induced noise. To
configure the LTC7802-3.3for 2-phase operation, tie VFB2
to less than 35mA from a 36V supply when not using the
EXTV supply at a 70°C ambient temperature:
CC
T = 70°C + (35mA)(36V)(43°C/W) = 125°C
J
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked
while operating in continuous conduction mode (MODE
to INTV , ITH2 to ground, and RUN2 to RUN1.
CC
The RUN1, V , ITH1, TRACK/SS1 pins are then used
OUT1
= INTV ) at maximum V .
CC IN
to control both channels, but each channel uses its own
ICMP and IR comparators to monitor their respective
inductor currents. Figure 10 is a typical application con-
figured for single output 2-phase operation.
When the voltage applied to EXTVCC rises above 4.7V
(typical), the VIN LDO is turned off and the EXTVCC LDO is
enabled. The EXTV LDO remains on as long as the volt-
CC
age applied to EXTV remains above approximately 4.5V.
CC
The EXTV LDO attempts to regulate the INTV voltage
CC
CC
INTV Regulators
CC
to 5.1V, so while EXTV is less than 5.1V, the LDO is in
dropout and the INTV CC voltage is approximately equal
The LTC7802-3.3 features two separate internal low
dropout linear regulators (LDOs) that supply power at
the INTV pin from either the V pin or the EXTV pin
CC
to EXTV . When EXTV is greater than 5.1V (up to an
CC
CC
absolute maximum of 30V), INTV is regulated to 5.1V.
CC
IN
CC
CC
depending on the EXTVCC pin voltage. INTVCC powers the
MOSFET gate drivers and most of the internal circuitry.
The V LDO and the EXTV LDO each regulate INTV
Using the EXTVCC LDO allows the MOSFET driver and con-
trol power to be derived from one of the LTC7802-3.3’s
switching regulator outputs (4.8V ≤ V
≤ 30V) during
IN
CC
CC
OUT
to 5.1V and can provide a peak current of at least 100mA.
normal operation and from the V LDO when the output
IN
is out of regulation (e.g., start-up, short-circuit). If more
current is required through the EXTVCC LDO than is speci-
fied, an external Schottky diode can be added between the
The INTVCC pin must be bypassed to ground with a
minimum of 4.7μF ceramic capacitor, placed as close as
possible to the pin. An additional 1μF ceramic capacitor
EXTV and INTV pins. In this case, do not apply more
CC
CC
placed directly adjacent to the INTV and GND pins is
CC
than 6V to the EXTV pin.
CC
also highly recommended to supply the high frequency
transient currents required by the MOSFET gate drivers.
Significant efficiency and thermal gains can be realized
by powering INTV from an output, since the V cur-
CC
IN
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi-
mum junction temperature rating for the LTC7802-3.3 to
rent resulting from the driver and control currents will be
scaled by a factor of VOUT/(VIN • Efficiency). For 5V to 30V
regulator outputs, this means connecting the EXTV pin
CC
be exceeded. The INTV current, which is dominated by
CC
directly to V . Tying the EXTV pin to an 8.5V supply
OUT
CC
the gate charge current, may be supplied by either the V
IN
reduces the junction temperature in the previous example
LDO or the EXTVCC LDO. When the voltage on the EXTVCC
from 125°C to:
pin is less than 4.7V, the V LDO is enabled. Power dissi-
IN
pation for the IC in this case is equal to V • IINTV . The
T = 70°C + (35mA)(8.5V)(43°C/W) = 83°C
J
IN
CC
gate charge current is dependent on operating frequency
as discussed in the Efficiency Considerations section.
The junction temperature can be estimated by using the
However, for 3.3V and other low voltage outputs, addi-
tional circuitry is required to derive INTV power from
CC
the output.
Rev. 0
23
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LTC7802-3.3
APPLICATIONS INFORMATION
The following list summarizes the four possible connec-
The external diode DB can be a Schottky diode or sili-
con diode, but in either case it should have low leakage
and fast recovery. The reverse breakdown of the diode
tions for EXTV :
CC
1. EXTV grounded. This will cause INTV to be pow-
CC
CC
must be greater than V
. Pay close attention to the
IN(MAX)
ered from the internal VIN LDO resulting in an efficiency
reverse leakage at high temperatures where it generally
increases substantially.
penalty of up to 10% or more at high input voltages.
2. EXTV connected directly to one of the regulator out-
CC
A leaky diode not only increases the quiescent current
of the regulator, but it can create current path from the
BOOST pin to INTVCC. This will cause INTVCC to rise if
the diode leakage exceeds the current consumption on
puts. This is the normal connection for an application
with an output in the range of 5V to 30V and provides
the highest efficiency. If both outputs are in the 5V to
30V range, connect EXTVCC to the lesser of the two
outputs to maximize efficiency.
INTV , which is primarily a concern in Burst Mode opera-
CC
tion where the load on INTV can be very small. There
CC
3. EXTV connected to an external supply. If an external
is an internal voltage clamp on INTV that prevents the
CC
CC
supply is available, it may be used to power EXTV
INTV voltage from running away, but this clamp should
CC
be reCgCarded as a failsafe only.
provided that it is compatible with the MOSFET gate
drive requirements. This supply may be higher or lower
than V ; however, a lower EXTV voltage results in
Minimum On-Time Considerations
IN
CC
higher efficiency.
Minimum on-time t
is the smallest time duration
ON(MIN)
4. EXTVCC connected to an output-derived boost or charge
pump. For regulators where both outputs are below
5V, efficiency gains can still be realized by connect-
that the LTC7802-3.3 is capable of turning on the top
MOSFET. It is determined by internal timing delays and
the gate charge required to turn on the MOSFET. Low duty
cycle applications may approach this minimum on time
limit and care should be taken to ensure that:
ing EXTV to an output-derived voltage that has been
CC
boosted to greater than 4.8V.
VOUT
Topside MOSFET Driver Supply (C , D )
B
B
tON(MIN)
<
V •fOSC
IN
External bootstrap capacitors CB connected to the
BOOST pins supply the gate drive voltages for the top-
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase. The mini-
mum on-time for the LTC7802-3.3 is approximately 40ns.
However, as the peak sense voltage decreases the mini-
mum on-time gradually increases up to about 60ns. This
is of particular concern in forced continuous applications
with low ripple current at light loads. If the duty cycle
drops below the minimum on-time limit in this situation,
a significant amount of cycle skipping can occur with cor-
respondingly larger current and voltage ripple.
side MOSFETs. Capacitor C in the Functional Diagram is
B
charged though external diode D from INTV when the
B
CC
SW pin is low.
When one of the topside MOSFETs is to be turned on, the
driver places the C voltage across the gate-source of the
B
desired MOSFET. This enhances the MOSFET and turns on
the topside switch. The switch node voltage, SW, rises to
VIN and the BOOST pin follows. With the topside MOSFET
on, the boost voltage is above the input supply: V
=
BOOST
B
V + V
. The value of the boost capacitor C needs
IN
INTVCC
to be 100 times that of the total input capacitance of the
topside MOSFET(s). For a typical application, a value of
C = 0.1μF is generally sufficient.
B
Rev. 0
24
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LTC7802-3.3
APPLICATIONS INFORMATION
Fault Conditions: Current Limit and Foldback
When the internal die temperature exceeds 180°C, the
INTV LDO and gate drivers are disabled. When the die
CC
The LTC7802-3.3 includes current foldback to reduce the
load current when the output is shorted to ground. If the
output voltage falls below 50% of its regulation point, then
the maximum sense voltage is progressively lowered from
100% to 40% of its maximum value. Under short-circuit
conditions with very low duty cycles, the LTC7802-3.3 will
begin cycle skipping to limit the short circuit current. In
this situation the bottom MOSFET dissipates most of the
power but less than in normal operation. The short-circuit
ripple current is determined by the minimum on-time,
cools to 160°C, the LTC7802-3.3 enables the INTVCC LDO
and resumes operation beginning with a soft-start startup.
Long-term overstress (T > 125°C) should be avoided as
J
it can degrade the performance or shorten the life of the
part.
Phase-Locked Loop and Frequency Synchronization
The LTC7802-3.3 has an internal phase-locked loop (PLL)
which allows the turn-on of the top MOSFET of control-
ler 1 to be synchronized to the rising edge of an external
clock signal applied to the PLLIN/SPREAD pin. The turn
on of controller 2’s top MOSFET is thus 180° out of phase
with the external clock.
t
≈ 40ns, the input voltage and inductor value:
ON(MIN)
ΔI
L(SC)
= t
• V /L
ON(MIN) IN
The resulting average short-circuit current is:
= 40% • I − ΔI /2
I
SC
Rapid phase-locking can be achieved by using the FREQ
pin to set a free-running frequency near the desired
synchronization frequency. Before synchronization,
the PLL is prebiased to the frequency set by the FREQ
pin. Consequently, the PLL only needs to make minor
adjustments to achieve phase-lock and synchronization.
Although it is not required that the free-running frequency
be near the external clock frequency, doing so will pre-
vent the oscillator from passing through a large range of
frequencies as the PLL locks.
LIM(MAX)
L(SC)
Fault Conditions: Overvoltage Protection (Crowbar)
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
much higher than nominal levels. The crowbar causes
huge currents to flow that blow the fuse to protect against
a shorted top MOSFET if the short occurs while the con-
troller is operating.
If an output voltage rises 10% above the set regula-
tion point, the top MOSFET is turned off and the bottom
MOSFET is turned on until the overvoltage condition is
cleared. The bottom MOSFET remains on continuously
for as long as the overvoltage condition persists; if V
returns to a safe level, normal operation automaticOalUlyT
resumes.
When synchronized to an external clock, the LTC7802-3.3
operates in pulse-skipping mode if it is selected by the
MODE pin, or in forced continuous mode otherwise. The
LTC7802-3.3 is guaranteed to synchronize to an external
clock applied to the PLLIN/SPREAD pin that swings up
to at least 2.2V and down to 0.5V or less. Note that the
LTC7802-3.3 can only be synchronized to an external
clock frequency within the range of 100kHz to 3MHz.
A shorted top MOSFET will result in a high current con-
dition which will open the system fuse. The switching
regulator will regulate properly with a leaky top MOSFET
by altering the duty cycle to accommodate the leakage.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
Fault Conditions: Overtemperature Protection
At higher temperatures, or in cases where the internal
power dissipation causes excessive self-heating (such
as a short from INTV to ground) internal overtempera-
CC
ture shutdown circuitry will shut down the LTC7802-3.3.
Rev. 0
25
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LTC7802-3.3
APPLICATIONS INFORMATION
produce the most improvement. Percent efficiency can
be expressed as:
MOSFET can simply be summed with the resistances
2
of L, R
and ESR to obtain I R losses.
SENSE
%Efficiency = 100% – (L1 + L2 + L3 + ...)
For example, if each R
SENSE
= 30mΩ, R = 50mΩ,
DS(ON) L
R
= 10mΩ and ESR = 40mΩ (sum of both input
where L1, L2, etc. are the individual losses as a percent-
age of input power.
and output capacitance losses), then the total resis-
tance is 130mΩ. This results in losses ranging from
3% to 13% as the output current increases from 1A to
5A for a 5V output, or a 4% to 20% loss for a 3.3V out-
put. This percentage loss varies as the inverse square
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of
the losses in LTC7802-3.3 circuits: 1) IC VIN current,
2
2) INTV regulator current, 3) I R losses, 4) Topside
of V
for the same external components and output
CC
OUT
MOSFET transition losses.
power level. The combined effects of increasingly lower
output voltages and higher currents required by high
performance digital systems is not doubling but qua-
drupling the importance of loss terms in the switching
regulator system!
1. The VIN current is the DC supply current given in
the Electrical Characteristics table, which excludes
MOSFET driver and control currents. Other than at very
light loads in burst mode, V current typically results
IN
in a small (<0.1%) loss.
4. Transition losses apply only to the top MOSFETs and
become significant only when operating at higher
input voltages (typically 15V or greater). Transition
losses can be estimated from the equation for the
main switch power dissipation in the power MOSFET
Selection section.
2. INTV current is the sum of the MOSFET driver and
CC
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge, dQ, moves
from INTVCC to ground. The resulting dQ/dt is a current
Other hidden losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these system level losses during the
design phase. The internal battery and fuse resistance
out of INTV that is typically much larger than the
CC
control circuit current. In continuous mode, I
GATECHG
= f (Q Q ), where Q and Q are the gate charges
SW T +
B
T
B
of the top and bottom MOSFETs.
losses can be minimized by making sure that C has ade-
IN
Supplying INTVCC from an output-derived source
through EXTVCC will scale the VIN current required
quate charge storage and very low ESR at the switching
frequency. A 25W supply will typically require a minimum
of 20μF to 40μF of capacitance having a maximum of
20mΩ to 50mΩ of ESR. The LTC7802-3.3 2-phase archi-
tecture typically halves this input capacitance requirement
over competing solutions. Other losses including induc-
tor core losses generally account for less than 2% total
additional loss.
for the driver and control circuits by a factor of V
/
OUT
(V • Efficiency). For example, in a 20V to 5V applica-
IN
tion, 10mA of INTV current results in approximately
CC
2.5mA of VIN current. This reduces the mid-current
loss from 10% or more (if the driver was powered
directly from V ) to only a few percent.
IN
3. I2R losses are predicted from the DC resistances of the
input fuse (if used), MOSFET, inductor, current sense
resistor, and input and output capacitor ESR. In con-
tinuous mode the average output current flows through
L and RSENSE, but is chopped between the top and
bottom MOSFETs. If the two MOSFETs have approxi-
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
amount equal to ΔILOAD • (ESR), where ESR is the effective
shifts by an
OUT
mately the same R
, then the resistance of one
DS(ON)
Rev. 0
26
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LTC7802-3.3
APPLICATIONS INFORMATION
by increasing R and the bandwidth of the loop will be
series resistance of C . ΔI
also begins to charge or
C
OUT
generating tLhOeAfDeedback error signal that
increased by decreasing CC. If RC is increased by the same
factor that C is decreased, the zero frequency will be kept
the same, thCereby keeping the phase shift the same in the
most critical frequency range of the feedback loop. The
output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance.
discharge C
OUT
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recovery
time V
can be monitored for excessive overshoot or
OUT
ringing, which would indicate a stability problem.
OPTI-LOOP compensation allows the transient response
to be optimized over a wide range of output capaci-
tance and ESR values. The availability of the ITH pin not
only allows optimization of control loop behavior, but it
also provides a DC coupled and AC filtered closed loop
response test point. The DC step, rise time and settling
at this test point truly reflects the closed loop response.
Assuming a predominantly second order system, phase
margin and/or damping factor can be estimated using the
percentage of overshoot seen at this pin. The bandwidth
can also be estimated by examining the rise time at the
pin. The ITH external components shown in the Typical
Applications circuits provide an adequate starting point
for most applications.
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C , causing a rapid drop in V . No regulator can
OUT
alter itOsUdTelivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C
to C
is greater than 1:50, the switch rise time
LOAD
OUT
should be controlled so that the load rise time is limited
to approximately C • 25μs/μF. Thus a 10μF capacitor
LOAD
would require a 250μs rise time, limiting the charging
current to about 200mA.
The ITH series R -C filter sets the dominant pole-zero
C
C
Design Example
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their initial values) to optimize tran-
sient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1μs to 10μs will
produce output voltage and ITH pin waveforms that will
give a sense of the overall loop stability without breaking
the feedback loop.
As a design example, assume VIN(NOMINAL) = 12V, VIN(MAX)
= 22V, V
= 3.3V, I
= 20A, and f = 1MHz.
OUT
OUT SW
1. Set the operating frequency. The frequency is not one of
the internal preset values, so a resistor from the FREQ
pin to GND is required, with a value of:
ꢈꢉꢊꢋꢌ
R
ꢃꢄꢅ ꢆΩꢇ=
= ꢈꢉꢆΩ
ꢀRꢁꢂ
ꢍꢊꢋꢌ
2. Determine the inductor value. Initially select a value
based on an inductor ripple current of 30%. The induc-
tor value can then be calculated from the following
equation:
Placing a power MOSFET directly across the output
capacitor and driving the gate with an appropriate signal
generator is a practical way to produce a realistic load
step condition. The initial output voltage step resulting
from the step change in output current may not be within
the bandwidth of the feedback loop, so this signal can-
not be used to determine phase margin. This is why it is
better to look at the ITH pin signal which is in the feed-
back loop and is the filtered and compensated control
loop response. The gain of the loop will be increased
�
�
V
V
OUT
V
IN(NOM)
OUT
�
÷
L =
1–
= 0.4µH
�
�
÷
f
� I
(
)
L
SW
�
The highest value of ripple current occurs at the maxi-
mum input voltage. In this case the ripple at V = 22V
IN
is 35%
Rev. 0
27
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LTC7802-3.3
APPLICATIONS INFORMATION
3. Verify that the minimum on-time of 40ns is not violated.
divider current in the range of 10μA to 100μA or more
is acceptable. For a 50μA feedback divider current,
The minimum on-time occurs at V
:
IN(MAX)
R = 0.8V/50μA = 16kΩ. R can then be calculated
A
B
ꢇ
ꢁꢈꢉ
as R = R (3.3V/0.8V – 1) = 50kΩ. For channel 1, the
B
feedback Aresistor network is implemented internally.
ꢀ
=
= ꢏꢐ0ꢑꢒ
ꢁꢂꢃꢄꢅꢂꢆ
ꢇ
ꢃꢌ
ꢆ
ꢅꢂꢃꢄꢊꢋꢆ
ꢍꢎ
Directly connect the V
pin to the output.
OUT1
This is more than sufficient to satisfy the minimum on
time requirement. If the minimum on time is violated,
the LTC7802-3.3 skips pulses at high input voltage,
resulting in lower frequency operation and higher
inductor current ripple than desired. If undesirable, this
behavior can be avoided by decreasing the frequency
(with the inductor value accordingly adjusted) to avoid
operation near the minimum on-time.
6. Select the MOSFETs. The best way to evaluate MOSFET
performance in a particular application is to build and
test the circuit on the bench, facilitated by an LTC7802-
3.3 demo board. However, an educated guess about
the application is helpful to initially select MOSFETs.
Since this is a high current, low voltage application, I2R
losses will likely dominate over transition losses for the
top MOSFET. Therefore, choose a MOSFET with lower
4. Select the RSENSE resistor value. The peak inductor
current is the maximum DC output current plus half of
the inductor ripple current. Or 20A • (1+0.30/2) = 23A
in this case. The RSENSE resistor value can then be cal-
culated based on the minimum value for the maximum
current sense threshold (45mV):
R
as opposed to lower gate charge to minimize
DS(ON)
the combined loss terms. The bottom MOSFET does
not experience transition losses, and its power loss is
2
generally dominated by I R losses. For this reason,
the bottom MOSFET is typically chosen to be of lower
R
and subsequently higher gate charge than the
DS(ON)
top MOSFET.
45mV
R
�
� 2m�
Due to the high current in this application, two
MOSFETs may needed in parallel to more evenly bal-
SENSE
23A
ance the dissipated power and to lower the R
. Be
To allow for additional margin, a lower value R
DS(ON)
SENSE
sure to select logic-level threshold MOSFETs, since the
may be used (for example, 1.8mΩ); however, be sure
gate drive voltage is limited to 5.1V (INTV ). Minimize
that the inductor saturation current has sufficient mar-
CC
the inductance of the TG and BG gate drive traces and
their respective return paths to the controller IC (SW
and GND) by using wide traces and multiple parallel
vias.
gin above V
/R
, where the maximum
SENSE(MAX)
SENSE(MAX) SENSE
value of 55mV is used for V
.
For this low inductor value and high current applica-
tion, an RC filter into the SENSE pins should be used
to compensate for the parasitic inductance (ESL) of the
7. Select the input and output capacitors. C is chosen
IN
for an RMS current rating of at least 10A (I /2, with
sense resistor. Assuming an R
geometry of 1225
OUT
SENSE
margin) at temperature assuming only this channel
with a parasitic inductance of 0.2nH, the RC filter time
constant should be RC = ESL/R = 0.2nH/2mΩ =
is on. C
is chosen with an ESR of 3mΩ for low
OUT
SENSE
output ripple. Multiple capacitors connected in parallel
may be required to reduce the ESR to this level. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due
to ESR is approximately:
100ns, which may be implemented with 100Ω resis-
tor in series with the SENSE+ pin and 1nF capacitor
–
between SENSE+ and SENSE .
5. Select the feedback resistors. If very light load effi-
ciency is required, high value feedback resistors may
be used to minimize the current due to the feedback
divider. However, in most applications a feedback
V
= ESR • ΔI = 3mΩ • 6A = 18mV
L P-P
ORIPPLE
On the 3.3V output, this is equal to 0.55% of peak to
peak voltage ripple.
Rev. 0
28
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LTC7802-3.3
APPLICATIONS INFORMATION
8. Determine the bias supply components. Since the regu-
lated output is not greater than the EXTV switchover
threshold (4.7V), it cannot be used toCbCias INTVCC.
However, if another supply is available, for example
if the other channel is regulating to 5V, connect that
terminals. The area of the “hot loop” formed by the top
N-channel MOSFET, bottom N-channel MOSFET and the
high frequency (ceramic) input capacitors, as shown
in Figure 8, should be minimized with short leads, pla-
nar connections, and multiple paralleled vias where
needed. The output capacitor (–) terminals should be
connected as close as possible to the (–) terminals of
the input capacitor.
supply to EXTV to improve the efficiency.
CC
For a 6.5ms soft-start, select a 0.1μF capacitor for the
TRACK/SS pin. As a first pass estimate for the bias
components, select CINTVCC = 4.7μF, boost supply
3. Do the LTC7802-3.3 V
pin and V
pin’s resis-
FB2
OUT1
capacitor C = 0.1μF and low forward drop boost sup-
B
tive divider connect to the (+) terminals of C ? The
OUT
ply diode CMDSH-4E from Central Semiconductor.
resistive divider must be connected between the (+)
terminal of C
and signal ground. Place the divider
9. Determine and set application-specific parameters. Set
the MODE pin based on the trade-off of light load effi-
ciency and constant frequency operation. Set the PLLIN/
SPREAD pin based on whether a fixed, spread spec-
trum, or phase-locked frequency is desired. The RUN
pin can be used to control the minimum input voltage
OUT
close to the VFB2 pin to minimize noise coupling into the
sensitive V node. The feedback resistor connections
should notFbBe2 along the high current input feeds from
the input capacitor(s).
4. Are the SENSE– and SENSE+ leads routed together with
minimum PC trace spacing? Route these traces away
from the high frequency switching nodes, on an inner
for regulator operation or can be tied to V for always-
IN
on operation. Use ITH compensation components from
the typical applications as a first guess, check the tran-
sient response for stability, and modify as necessary.
+
layer if possible. The filter capacitor between SENSE
–
and SENSE should be as close as possible to the IC.
Ensure accurate current sensing with Kelvin connec-
tions at the sense resistor.
For more detailed layout guidance, see Analog Devices
Application Notes AN136 “PCB Layout Considerations
for Non-Isolated Switching Power Supplies” and
AN139 “Power Supply Layout and EMI”.
5. Is the INTV decoupling capacitor connected close
CC
to the IC, between the INTV and the power ground
CC
pin? This capacitor carries the MOSFET drivers’ cur-
rent peaks. An additional 1μF ceramic capacitor placed
immediately next to the INTV and GND pins can help
improve noise performanceCsCubstantially. The boost
diodes should have separate routes directly to the
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. Figure 8 illustrates the current waveforms present
in the various branches of the synchronous regulators
operating in the continuous mode. Check the following
in your layout:
INTV capacitor near the IC, not shared with any sig-
CC
nal connections to INTV .
CC
6. Keep the switching nodes (SW1, SW2), top gate nodes
(TG1, TG2), and boost nodes (BOOST1, BOOST2) away
from sensitive small-signal nodes, especially from the
other channel’s voltage and current sensing feedback
pins. All of these nodes have very large and fast-mov-
ing signals and therefore should be kept on the out-
put side of the LTC7802-3.3 and occupy minimum PC
trace area. Minimize the inductance of the TG and BG
gate drive traces and their respective return paths to
the controller IC (SW and GND) by using wide traces
and multiple parallel vias.
1. Are the top N-channel MOSFETs located within 1cm of
each other with a common drain connection at CIN?
Decoupling capacitors for the two channels should be
close to each other to avoid a large resonant loop.
2. Are the signal and power grounds kept separate?
The combined IC ground pin and the ground return
of CINTVCC must return to the combined COUT (–)
Rev. 0
29
For more information www.analog.com
LTC7802-3.3
APPLICATIONS INFORMATION
ꢂꢃꢁ
ꢀꢁ
R
ꢂꢄꢅꢂꢄꢁ
ꢆ
ꢇꢈꢉꢁ
ꢐꢇꢉ
ꢀꢇꢇꢓ
ꢊ
ꢇꢈꢉꢁ
R
ꢀꢁ
ꢆ
ꢋꢅ
R
ꢋꢅ
ꢊ
ꢋꢅ
ꢂꢃꢌ
ꢀꢌ
R
ꢂꢄꢅꢂꢄꢌ
ꢆ
ꢇꢈꢉꢌ
ꢐꢇꢉ
ꢀꢇꢇꢓ
ꢊ
ꢇꢈꢉꢌ
R
ꢀꢌ
ꢍꢇꢀꢎ ꢀꢋꢅꢄꢂ ꢋꢅꢎꢋꢊꢏꢉꢄ
ꢐꢋꢑꢐ ꢂꢃꢋꢉꢊꢐꢋꢅꢑ
ꢊꢈRRꢄꢅꢉ. ꢒꢄꢄꢓ ꢀꢋꢅꢄꢂ
ꢉꢇ ꢏ ꢔꢋꢅꢋꢔꢈꢔ ꢀꢄꢅꢑꢉꢐ.
ꢕꢖ0ꢌꢗꢗ ꢘ0ꢙ
Figure 8. Branch Current Waveforms
Rev. 0
30
For more information www.analog.com
LTC7802-3.3
APPLICATIONS INFORMATION
comparator trip point when the other channel is turning
on its top MOSFET. This occurs around 50% duty cycle
on either channel due to the phasing of the internal clocks
and may cause minor duty cycle jitter.
7. Use a modified star ground technique: a low impedance,
large copper area central grounding point on the same
side of the PC board as the input and output capacitors
with tie-ins for the bottom of the INTV decoupling
CC
capacitor, the bottom of the voltage feedback resistive
divider and the GND pin of the IC. For more detailed
layout guidance, see Analog Devices Application Notes
AN136 “PCB Layout Considerations for Non-Isolated
Switching Power Supplies” and AN139 “Power Supply
Layout and EMI”.
Reduce VIN from its nominal level to verify operation
of the regulator in dropout. Check the operation of the
undervoltage lockout circuit by further lowering VIN while
monitoring the outputs to verify operation. Investigate
whether any problems exist only at higher output cur-
rents or only at higher input voltages. If problems coincide
with high input voltages and low output currents, look for
capacitive coupling between the BOOST, SW, TG, and pos-
sibly BG connections and the sensitive voltage and current
pins. The capacitor placed across the current sensing pins
needs to be placed immediately adjacent to the pins of
the IC. This capacitor helps to minimize the effects of dif-
ferential noise injection due to high frequency capacitive
coupling. If problems are encountered with high current
output loading at lower input voltages, look for inductive
PC Board Layout Debugging
Start with one controller on at a time. It is helpful to use
a DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output volt-
age as well. Check for proper performance over the oper-
ating voltage and current range expected in the applica-
tion. The frequency of operation should be maintained
over the input voltage range down to dropout and until
the output load drops below the low current operation
threshold—typically 25% of the maximum designed cur-
rent level in Burst Mode operation.
coupling between C , the top MOSFET, and the bottom
IN
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
GND pin of the IC.
The duty cycle percentage should be maintained from
cycle to cycle in a well-designed, low noise PCB imple-
mentation. Variation in the duty cycle at a subharmonic
rate can suggest noise pickup at the current or volt-
age sensing inputs or inadequate loop compensation.
Overcompensation of the loop can be used to tame a
poor PC layout if regulator bandwidth optimization is not
required. Only after each controller is checked for its indi-
vidual performance should both controllers be turned on
at the same time. A particularly difficult region of opera-
tion is when one controller channel is nearing its current
An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
when the current sensing leads are hooked up backwards.
The output voltage under this improper hookup will still
be maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop
will be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
Rev. 0
31
For more information www.analog.com
LTC7802-3.3
TYPICAL APPLICATIONS
ꢀ
ꢁꢂ
ꢃ.ꢄꢀ ꢅꢆ ꢇꢈꢀ
ꢀꢁꢂꢃ
ꢄꢄ
ꢀꢁꢂꢃ
ꢄꢄ
ꢀꢁ
ꢀ0ꢁꢂ
ꢃꢄ
ꢀ00ꢁꢂ
ꢃꢄꢅ
Rꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢁꢂ
Rꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢁꢂꢃꢄ
ꢀꢁꢁꢂꢃꢄ
0.ꢀꢁꢂ
ꢀꢁꢂ 0.ꢃꢄꢅ
0.ꢀꢁꢂ
ꢀꢁꢂ ꢃ.ꢄꢅꢆ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ0ꢅꢆꢇ.ꢇ
20Ω
ꢄ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂꢀꢁꢃ
2mΩ
3mΩ
ꢀꢁꢂ
ꢀꢁꢂ
ꢄ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂꢀꢁꢃ
ꢀ
ꢁꢂꢃꢄ
ꢅ.ꢅꢀꢆ ꢄꢇꢈ
ꢀ
ꢀ
ꢁꢂꢃꢄ
ꢆ
ꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢄꢄ
ꢅꢀ ꢇ ꢈ0ꢉ
ꢀ
ꢀꢁꢂꢂꢃꢄ
ꢀꢁꢂꢂꢃꢄ
ꢁꢂꢃꢄ
ꢀ
ꢀꢁꢂꢃ
ꢁꢂꢃꢄ
ꢀ00ꢁꢂ
ꢃꢄ
ꢅꢅ0ꢆꢇ
ꢈ.ꢅꢉ
ꢀ00ꢁꢂ
ꢃꢄ
ꢅꢅ0ꢆꢇ
ꢈ.ꢅꢉ
ꢀ
ꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁ.ꢂꢃ
ꢀRꢁꢂꢃꢄꢅꢅꢆ
ꢀRꢁꢂꢃꢄꢅꢅꢆ
ꢀꢀꢁ
ꢀ.ꢁꢂ
0.ꢀꢁꢂ
0.ꢀꢁꢂ
ꢀ00ꢁꢂ
ꢀ.ꢀꢁꢂ
ꢀꢁꢁꢂꢃꢄꢅꢀRꢆꢇꢈ
ꢀRꢁꢂ
ꢀ00ꢁꢂ
ꢀ.ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢄꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀ.ꢁꢂꢃ
ꢀ
ꢃ ꢄꢅ0ꢆꢇꢈ
ꢁꢂ
ꢀꢁ0ꢂꢃꢃ ꢄ0ꢅꢆ
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢈRꢉꢊ ꢋꢆꢌꢍ ꢅꢌꢀꢋꢎꢏꢐꢆ
ꢀꢁꢂ ꢃꢄRꢅꢆ ꢇꢈꢈꢉꢊꢊ0ꢋ0
ꢀꢌꢂ ꢃꢄRꢅꢆ ꢇꢈꢈꢉꢁꢉꢁꢍ0
ꢎꢅꢏꢐꢁꢑꢌꢂ ꢒꢓꢔꢒꢓꢕꢏꢓ ꢖꢗꢘ0ꢊꢋꢓ0ꢈꢀꢗꢙ
ꢎꢖꢏꢅꢁꢑꢌꢂ ꢒꢓꢔꢒꢓꢕꢏꢓ ꢖꢗꢘ0ꢌꢌꢓ0ꢈꢀꢗꢙ
ꢅ
ꢅ
ꢄ ꢋꢑꢇꢅꢒꢇ ꢓꢔꢅꢆꢁ00ꢊꢕ
ꢍꢇ
ꢄ ꢖꢆꢌꢆꢈ ꢈꢗꢃ0ꢘꢔꢔꢙꢌ00ꢓꢉꢈꢆ0ꢁꢗ
ꢒꢑꢈꢁꢂꢃ
ꢚꢘ
ꢒꢑꢈꢃ
ꢛꢒꢊꢊꢒꢜꢋ ꢘ ꢜꢎꢆꢇ ꢘ ꢝ ꢗꢘ
ꢍꢇ
ꢍꢇ
No-Load Burst Mode Input
Current vs Input Voltage
Efficiency vs Load Current
Short-Circuit Response
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀ00
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁꢂꢃ ꢄꢃꢅꢆꢆꢇꢈꢉ ꢁꢆ
ꢀꢁꢂꢃꢄ ꢅꢆꢇe ꢈꢉꢊRꢋꢌꢍꢈꢎ
ꢀꢁꢂꢃ ꢄꢅꢆꢁꢁꢇꢂ ꢈ ꢀꢁ
ꢀꢁꢂꢃ ꢄꢅꢆꢁꢁꢇꢂ ꢈ ꢀꢁ
ꢀꢁꢂꢃ ꢄꢃꢅꢆꢆꢇꢈꢉ ꢁꢆ
ꢀ
ꢁꢂꢃꢄ
ꢅꢀꢆꢇꢈꢀ
ꢀꢁꢂꢃꢄꢅꢆR
ꢄꢃRRꢇꢁꢅ
ꢈꢉꢊꢂꢀꢋ
ꢀ
ꢀ ꢁꢂ
ꢀ
ꢀ ꢁ.ꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁRꢂꢃꢄ ꢂꢁꢅꢆꢇꢅꢈꢁꢈꢉ ꢊꢁꢄꢃ
ꢀꢁ
ꢀ
ꢀ ꢁꢂꢃ
ꢀ
ꢀ ꢁꢂꢃ
ꢀ ꢁꢂꢃ
ꢀ ꢁꢂꢃ
ꢀꢁ0ꢂꢃꢃ ꢄ0ꢅꢆ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ00ꢁꢂꢃꢄꢅꢆ
ꢀ
ꢀ ꢁꢂꢃ
ꢀ
ꢀ
ꢀ ꢁꢂꢃ
ꢀ
0
ꢀ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
0
ꢀ
ꢀ
ꢀ
ꢀꢁ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆ ꢇꢀꢈ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁ
ꢀꢁ0ꢂꢃꢃ ꢄ0ꢅꢆ
ꢀꢁ0ꢂꢃꢃ ꢄ0ꢅꢆ
Figure 9. High Efficiency Dual 3.3V, 5V Step-Down Regulator with Spread Spectrum
Rev. 0
32
For more information www.analog.com
LTC7802-3.3
PACKAGE DESCRIPTION
UFDM Package
28-Lead Plastic Side Wettable QFN (4mm × 5mm)
ꢂReꢨeꢩeꢪꢫe ꢓꢍꢒ ꢆꢐꢑ ꢬ 0ꢉꢭ0ꢡꢭꢁꢟꢡꢃ Rev ꢧꢈ
ꢗꢅꢋ ꢁ ꢋꢌꢍꢒꢛ
R ꢤ 0.ꢃ0 ꢌR 0.ꢕꢉ
× ꢀꢉ° ꢒꢛꢏꢔꢊꢇR
ꢃ.ꢉ0 Rꢇꢊ
R ꢤ 0.ꢁꢁꢉ
ꢍꢞꢗ
R ꢤ 0.0ꢉ
ꢍꢞꢗ
0.ꢠꢉ ±0.0ꢉ
ꢀ.00 ±0.ꢁ0
ꢂꢃ ꢄꢅꢆꢇꢄꢈ
ꢃꢠ
ꢃꢡ
0.ꢀ0 ±0.ꢁ0
ꢗꢅꢋ ꢁ
ꢍꢌꢗ ꢔꢏRꢙ
ꢂꢋꢌꢍꢇ ꢟꢈ
ꢁ
ꢃ
ꢉ.00 ±0.ꢁ0
ꢂꢃ ꢄꢅꢆꢇꢄꢈ
ꢕ.ꢉ0 Rꢇꢊ
ꢕ.ꢟꢉ ±0.ꢁ0
ꢃ.ꢟꢉ ±0.ꢁ0
ꢆꢇꢍꢏꢅꢓ ꢏ
ꢂꢚꢊꢆꢔꢃꢡꢈ ꢦꢊꢋ ꢁꢃꢁꢡ Rꢇꢢ ꢧ
0.ꢃꢉ ±0.0ꢉ
0.ꢃ00 Rꢇꢊ
0.ꢉ0 ꢘꢄꢒ
0.00 ꢥ 0.0ꢉ
ꢘꢌꢍꢍꢌꢔ ꢢꢅꢇꢐꢣꢇꢖꢗꢌꢄꢇꢆ ꢗꢏꢆ
ꢋꢌꢍꢇꢎ
ꢆꢇꢍꢏꢅꢓ ꢏ
ꢁ. ꢆRꢏꢐꢅꢋꢑ ꢋꢌꢍ ꢍꢌ ꢄꢒꢏꢓꢇ
ꢍꢇRꢔꢅꢋꢏꢓ ꢓꢇꢋꢑꢍꢛ
0.ꢀ0 0.ꢁ0
ꢃ. ꢏꢓꢓ ꢆꢅꢔꢇꢋꢄꢅꢌꢋꢄ ꢏRꢇ ꢅꢋ ꢔꢅꢓꢓꢅꢔꢇꢍꢇRꢄ
ꢕ. ꢆꢅꢔꢇꢋꢄꢅꢌꢋꢄ ꢌꢊ ꢇꢖꢗꢌꢄꢇꢆ ꢗꢏꢆ ꢌꢋ ꢘꢌꢍꢍꢌꢔ ꢌꢊ ꢗꢏꢒꢙꢏꢑꢇ ꢆꢌ ꢋꢌꢍ ꢅꢋꢒꢓꢚꢆꢇ
ꢔꢌꢓꢆ ꢊꢓꢏꢄꢛ. ꢔꢌꢓꢆ ꢊꢓꢏꢄꢛꢜ ꢅꢊ ꢗRꢇꢄꢇꢋꢍꢜ ꢄꢛꢏꢓꢓ ꢋꢌꢍ ꢇꢖꢒꢇꢇꢆ 0.ꢁꢉꢝꢝ ꢌꢋ ꢏꢋꢞ ꢄꢅꢆꢇ
ꢀ. ꢄꢛꢏꢆꢇꢆ ꢏRꢇꢏ ꢅꢄ ꢌꢋꢓꢞ ꢏ RꢇꢊꢇRꢇꢋꢒꢇ ꢊꢌR ꢗꢅꢋ ꢁ ꢓꢌꢒꢏꢍꢅꢌꢋ
ꢌꢋ ꢍꢛꢇ ꢍꢌꢗ ꢏꢋꢆ ꢘꢌꢍꢍꢌꢔ ꢌꢊ ꢗꢏꢒꢙꢏꢑꢇ
0.ꢃ0ꢕ Rꢇꢊ
ꢍꢇRꢔꢅꢋꢏꢓ ꢍꢛꢅꢒꢙꢋꢇꢄꢄ
0.ꢁ0 Rꢇꢊ
0.0ꢉ Rꢇꢊ
ꢗꢓꢏꢍꢇꢆ ꢏRꢇꢏ
0.ꢠ0 ±0.0ꢉ
ꢀ.ꢉ0 ±0.0ꢉ
ꢕ.ꢁ0 ±0.0ꢉ
ꢃ.ꢉ0 Rꢇꢊ
ꢃ.ꢟꢉ ±0.0ꢉ
ꢕ.ꢟꢉ ±0.0ꢉ
ꢗꢏꢒꢙꢏꢑꢇ ꢌꢚꢍꢓꢅꢋꢇ
0.ꢃꢉ ±0.0ꢉ
0.ꢉ0 ꢘꢄꢒ
ꢕ.ꢉ0 Rꢇꢊ
ꢀ.ꢁ0 ±0.0ꢉ
ꢉ.ꢉ0 ±0.0ꢉ
Rꢇꢒꢌꢔꢔꢇꢋꢆꢇꢆ ꢄꢌꢓꢆꢇR ꢗꢏꢆ ꢗꢅꢍꢒꢛ ꢏꢋꢆ ꢆꢅꢔꢇꢋꢄꢅꢌꢋꢄ
ꢏꢗꢗꢓꢞ ꢄꢌꢓꢆꢇR ꢔꢏꢄꢙ ꢍꢌ ꢏRꢇꢏꢄ ꢍꢛꢏꢍ ꢏRꢇ ꢋꢌꢍ ꢄꢌꢓꢆꢇRꢇꢆ
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
33
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LTC7802-3.3
TYPICAL APPLICATION
ꢀꢁꢂꢃ
ꢄꢄ
ꢀ
ꢁꢂ
ꢀ
ꢁꢂ
ꢀꢁ
ꢃ.ꢄꢀ ꢅꢆ ꢇꢈꢀ
ꢉꢊꢀ ꢂꢆꢋꢁꢂꢌꢍ
ꢀ
ꢀ
ꢁꢂ
ꢀ0ꢁꢂ
ꢀ00ꢁꢂ
ꢀꢁꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ 0.ꢁꢃꢄꢅ
Rꢀꢁꢂ
ꢀꢁꢂ
Rꢀꢁꢂ
0.ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂꢃ
ꢁꢂꢃ
ꢄꢄ
ꢀꢁꢂꢃꢄ0ꢅꢆꢇ.ꢇ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀRꢁꢂ
150Ω
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂꢃ
ꢄꢄ
3mΩ
ꢀꢁꢂ
ꢀ.ꢁꢂꢃ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀ
ꢁꢂꢃ
ꢀ
ꢁꢂꢃꢄ
ꢄ.ꢄꢀꢅ ꢆꢇꢈ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀ
ꢀ
ꢀ.ꢁꢂꢃ
ꢄꢅ
ꢁꢂꢃ
ꢄꢅ0ꢆꢇ
ꢄꢈ
3mΩ
ꢀꢁꢂ
150Ω
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂꢃ
ꢄꢄ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀRꢁꢂꢃꢄꢅꢅꢆ
ꢀ
ꢁꢂ
0.ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ 0.ꢃꢄꢅꢆ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀRꢁꢂꢃꢄꢅꢅꢆ
0.ꢀꢁꢂ
ꢀ
ꢃ ꢄ.ꢄꢅꢆꢇꢈ
ꢁꢂ
ꢀꢁ0ꢂꢃ
ꢀꢁꢂ
ꢀꢁꢁꢂꢃꢄꢅꢀRꢆꢇꢈ
ꢆꢉꢊꢋꢌꢍꢄꢎ ꢏꢐꢑꢏꢐꢒꢊꢐ ꢓꢁꢔ0ꢅꢕꢐ0ꢖꢗꢁꢘ
ꢆꢓꢊꢉꢌꢍꢄꢎ ꢏꢐꢑꢏꢐꢒꢊꢐ ꢓꢁꢔ0ꢄꢄꢐ0ꢖꢗꢁꢘ
ꢗꢌꢍꢄꢎ ꢔꢊꢏꢗꢔRꢙꢑꢉ ꢚꢙꢗꢅ0ꢛ0ꢜꢌꢘꢌꢆꢒ
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Figure 10. 2.25MHz 2-Phase Single Output 3.3V, 24A Step-Down Regulator
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
4.5V ≤ V ≤ 40V, V
LTC7802
40V Dual Low I , 3MHz 2-Phase Synchronous Step-Down
Controller with Spread Spectrum
Up to 40V, I = 12µA
OUT Q
Q
IN
Fixed Frequency 100kHz to 3MHz, 4mm X 5mm QFN-28
LTC7803
40V Low I , 100% Duty Cycle,
4.5V ≤ V ≤ 40V, V
Up to 40V, I = 12µA
Q
IN
OUT Q
Synchronous Step-Down Controller with Spread Spectrum
Fixed Frequency 100kHz to 3MHz, 3mm X 3mm QFN-16/
MSOP-16
LTC3807
38V Low I , Synchronous Step-Down Controller
4V ≤ V ≤ 38V, 0.8V ≤ V
≤ 24V, I = 50µA
Q
IN
OUT Q
with 24V Output Voltage Capability
PLL Fixed Frequency 50kHz to 900kHz, 3mm x 4mm QFN-20/
TSSOP-20
LTC3890/LTC3890-1
60V, Low I , Dual 2-Phase Synchronous
4V ≤ V ≤ 60V, 0.8V ≤ V
≤ 24V, I = 50µA
Q
IN
OUT Q
PLL Fixed Frequency 50kHz to 900kHz
LTC3890-2/LTC3890-3 Step-Down DC/DC Controller with 99% Duty Cycle
PLL Fixed Frequency 50kHz to 900kHz
LTC3892
LTC3850
LTC3855
60V Low I , Dual, 2-Phase Synchronous
4V ≤ V ≤ 60V, 0.8V ≤ V
≤ 24V, I = 29µA
Q
IN
OUT Q
Step-Down DC/DC Controller with Adjustable Gate drive Voltage PLL Fixed Frequency 50kHz to 900kHz,
Dual, 2-Phase Synchronous Step-Down DC/DC Controller
4V≤ V ≤ 24V, V
up to 5.5V
IN
OUT
PLL Fixed Frequency 250kHz to 750kHz
Dual, Multiphase, Synchronous Step-Down DC/DC Controller
with Diff Amp and DCR Temperature Compensation
4.5V≤ V ≤ 38V, 0.8V ≤ V
≤ 12V
IN
OUT
PLL Fixed Frequency 250kHz to 770kHz,
Excellent current Share
LTC3869/LTC3869-2
LTC3875
Dual Output, 2-Phase Synchronous Step-Down DC/DC
Controller, with Accurate Current Share
4V ≤ V ≤ 38V, V
up to 12.5V
IN
OUT
PLL Fixed 250kHz to 750kHz Frequency,
Dual, 2-Phase, Synchronous Controller with
Sub-Milliohm DCR Sensing and Temperature Compensation
4.75V ≤ V ≤ 38V; 0.6V ≤ V
≤ 3.5V/5V
IN
OUT
Excellent current Share
LTC3774
Dual, Mulitphase Curent Mode Synchronous Step-Down
DC/DC Controller for Sub-Milliohm DCR Sensing
Operates with DrMOS, Power Blocks or External
Drivers/MOSFETs, 4.5V≤ V ≤ 38V, 0.6V ≤ V
≤ 3.5V
OUT
IN
Rev. 0
09/20
www.analog.com
ANALOG DEVICES, INC. 2020
34
相关型号：
LTC7812HUH#PBF
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Linear
LTC7812HUH#TRPBF
LTC7812 - Low IQ, 38V Synchronous Boost+Buck Controller; Package: QFN; Pins: 32; Temperature Range: -40°C to 125°C
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LTC7812IUH#PBF
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Linear
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