LTC7819 [ADI]
40V Low IQ, Triple Output, 3-Phase Synchronous Step-Down Controller;
| 型号： | LTC7819 |
| 厂家： | 
ADI |
| 描述： | 40V Low IQ, Triple Output, 3-Phase Synchronous Step-Down Controller |
| 文件： | 总36页 (文件大小：1524K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC7819
40V Low I , Triple Output, 3-Phase
Q
Synchronous Step-Down Controller
FEATURES
DESCRIPTION
The LTC®7819 is a high performance triple step-down
synchronous DC/DC switching regulator controller that
n
Triple Buck Synchronous Controllers
n
Wide Input Voltage Range: 4.5V to 40V
n
Wide Output Voltage Range: 0.8V to 99% • V
drives all N-channel power MOSFET stages. Constant fre-
quency current mode architecture allows a phase-lockable
switching frequency of up to 3MHz. The LTC7819 oper-
ates from a wide 4.5V to 40V input supply range. Power
loss and supply noise are minimized by operating the
three controller output stages out-of-phase.
IN
n
n
n
n
n
Low Operating I : 14μA (14V to 3.3V, Channel 1 On)
Q
Spread Spectrum Operation
R
or DCR Current Sensing
SENSE
Integrated Bootstrap Supply Charge Pump (Channel 1)
PassThru™/100% Duty Cycle Capability
(Channel 1), 99% Duty Cycle (Channels 2 and 3)
Programmable Fixed Frequency (100kHz to 3MHz)
Phase-Lockable Frequency (100kHz to 3MHz)
Selectable Continuous, Pulse-Skipping, or Low
Ripple, Burst Mode® Operation at Light Loads
The very low no-load quiescent current extends oper-
ating runtime in battery powered systems. OPTI-LOOP
compensation allows the transient response to be opti-
mized over a wide range of output capacitance and ESR
values. The LTC7819 features a precision 0.8V reference
and power good output indicators. The MODE pin selects
among Burst Mode operation, pulse-skipping mode, or
continuous inductor current mode at light loads.
n
n
n
n
n
n
Low Shutdown I : 1.5μA
Q
Small 40-Lead 6mm × 6mm QFN Package
AEC-Q100 Qualified for Automotive Applications
The LTC7819 additionally features spread spectrum oper
-
APPLICATIONS
ation which significantly reduces the peak radiated and
conducted noise on both the input and output supplies,
making it easier to comply with electromagnetic interfer-
ence (EMI) standards.
n
Automotive and Transportation
n
Industrial
n
Military / Avionics
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
V
IN
4.5V TO 38V
V
RUN1 RUN2 RUN3
IN
100µF
TG1
BOOST1
TG2
BOOST2
0.1µF
0.1µF
0.22µH
0.22µH
2mΩ
2mΩ
V
OUT
5V, 50A
SW1
SW2
LTC7819
BG1
BG2
470µF
+
–
+
–
SENSE1
SENSE2
SENSE1
SENSE2
V
EXTV
FB1
CC
V
IN
BOOST1,2,3
VPRG1
FREQ
INTV
CC
INTV
CC
TG3
BOOST3
V
FB2
V
4.7µF
FB3
PLLIN/SPREAD
0.1µF
0.22µH
2mΩ
SW3
BG3
ITH1
TRACK/SS1
ITH2
+
ITH3
MODE
SENSE3
0.1µF
–
SENSE3
7819 TA01
GND
Rev. 0
1
Document Feedback
For more information www.analog.com
LTC7819
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
Input Supply Voltage (V )......................... –0.3V to 40V
IN
BOOST1, BOOST2, BOOST3....................... –0.3V to 46V
Switch Voltage (SW1, SW2, SW3)................ –5V to 40V
RUN1, RUN2, RUN3 Voltages..................... –0.3V to 40V
40 39 38 37 36 35 34 33 32 31
EXTV Voltage ......................................... –0.3V to 30V
CC
MODE
1
2
3
4
5
6
7
8
9
30
29
28
BOOST3
BG3
INTV Voltage ............................................ –0.3V to 6V
CC
TRACK/SS1
(BOOST1-SW1), (BOOST2-SW2),
–
SENSE1
SW1
(BOOST3-SW3)............................................ –0.3V to 6V
+
SENSE1
27 TG1
+
+
+
–
–
–
SENSE1 , SENSE1 Voltages...................... –0.3V to 40V
V
FB1
26 BOOST1
41
GND
SENSE2 , SENSE2 Voltages ..................... –0.3V to 40V
ITH1
PGOOD2
RUN3
25
24
23
BG1
SENSE3 , SENSE3 Voltages..................... –0.3V to 40V
V
IN
EXTV
TRACK/SS1, V Voltages .......................... –0.3V to 6V
CC
FB1
FB2
FB3
RUN2
22 INTV
21
CC
TRACK/SS2, V Voltages.......................... –0.3V to 6V
RUN1 10
BG2
TRACK/SS3, V Voltages.......................... –0.3V to 6V
11 12 13 14 15 16 17 18 19 20
ITH1, ITH2, ITH3 Voltages............................ –0.3V to 2V
MODE, PGOOD1, PGOOD2 Voltages ............ –0.3V to 6V
PGOOD3, VPRG1 Voltages........................... –0.3V to 6V
PLLIN/SPREAD, FREQ Voltages................... –0.3V to 6V
BG1, BG2, BG3, TG1, TG2, TG3..........................(Note 9)
Operating Junction Temperature Range (Notes 2, 8)
LTC7819R .......................................... –40°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
T
= 150°C, θ = 33°C/W
JA
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
JMAX
Maximum Junction Temperature (T ) ................... 150°C
J
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC7819RUJ#PBF
LTC7819RUJ#TRPBF
7819
40-Lead (6mm x 6mm) Plastic QFN
−40°C to 150°C
AUTOMOTIVE PRODUCTS**
LTC7819RUJ#WPBF
LTC7819RUJ#WTRPBF
7819
40-Lead (6mm x 6mm) Plastic QFN
−40°C to 150°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
these models.
Rev. 0
2
For more information www.analog.com
LTC7819
ELECTRICAL CHARACTERISTICS The ldenotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 12V, RUN1,2,3 > 1.25V, EXTVCC = 0V, unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Supply (V )
IN
V
Input Supply Operating Range
Current in Regulation
4.5
40
V
IN
I
V
Front Page Circuit, 14V to 3.3V,
No Load, RUN2, 3 = 0V
14
µA
VIN
IN
Controller Operation
V
V
Output Voltage Operating Range
0.8
40
V
OUT1,2,3
FB1,2,3
Regulated Adjustable Output Feedback Voltage (Note 4) V = 4.5V to 40V,
IN
l
ITH1,2,3 Voltage = 0.6V to 1.2V
0°C to 85°C
0.788
0.792
0.800
0.800
0.812
0.808
V
V
V
FB1
Regulated Fixed Output Feedback Voltage
(Note 4) V = 4.5V to 40V,
IN
ITH1 Voltage = 0.6V to 1.2V
VPRG1 =0V
l
l
3.23
4.9
3.3
5.0
3.37
5.1
V
V
VPRG1= INTV
CC
Feedback Current (Channels 2 & 3)
Feedback Current (Channel 1)
5
50
50
nA
VPRG1 = FLOAT
5
1
nA
µA
VPRG1 = 0V or INTV , in Regulation
CC
Feedback Overvoltage Protection Threshold
Measured at V
Relative to
7
10
13
%
FB1,2,3
FB1,2,3
Regulated V
g
Transconductance Amplifier g
(Note 4) ITH1,2,3 = 1.2V, Sink/Source = 5μA
1.8
50
0
mmho
mV
m1,2,3
m
–
l
V
Maximum Current Sense Threshold
Matching Between Channels
V
V
V
V
= 0.7V, V
= 3.3V
45
55
3.5
1
SENSE(MAX)
FB1,2,3
SENSE1,2,3
–
= 3.3V
–3.5
mV
SENSE1,2,3
+
+
+
I
I
SENSE1,2,3 Pin Current
= 3.3V
µA
SENSE1,2,3
SENSE1,2,3
–
–
–
SENSE1 Pin Current
≤ 2.7V
SENSE1
> INTV + 0.5V
2
µA
µA
µA
SENSE1
SENSE1
–
3.2V ≤ V
< INTV – 0.5V
50
CC
–
V
700
SENSE1
CC
–
–
–
–
I
SENSE2,3 Pin Current
V
V
= 3.3V
2
µA
µA
SENSE2,3
SENSE2,3
SENSE2,3
> INTV + 0.5V
650
12.5
1.20
100
CC
Soft-Start Charge Current
RUN Pin ON Threshold
RUN Pin Hysteresis
V
V
V
= 0V
10
15
µA
V
TRACK/SS1,2,3
l
Rising
1.15
1.25
RUN1,2,3
RUN1,2,3
Falling
mV
DC Supply Current (Note 5)
V
IN
V
IN
Shutdown Current
Sleep Mode Current
RUN1,2,3 = 0V
1.5
µA
–
V
< 3.2V, EXTV = 0V
CC
SENSE1
One Channel On
15
18
24
30
µA
µA
All Channels On
–
Sleep Mode Current (Note 3)
Only Channel 1 On
V
V
V
≥ 3.2V
SENSE1
IN
IN
Current, EXTV = 0V
5
1
9
4
10
18
µA
µA
µA
µA
CC
CC
Current, EXTV ≥ 4.8V
EXTV Current, EXTV ≥ 4.8V
5
CC
CC
–
SENSE1 Current
10
–
Sleep Mode Current (Note 3)
All Channels On
V
V
≥ 3.2V, EXTV ≥ 4.8V
SENSE1
IN
CC
Current
1
8
16
4
14
26
µA
µA
µA
EXTV Current
CC
–
SENSE1 Current
Pulse-Skipping or Forced Continuous Mode
IN
One Channel On
All Channels On
2
4
mA
mA
V
or EXTV Current (Note 3)
CC
Rev. 0
3
For more information www.analog.com
LTC7819
ELECTRICAL CHARACTERISTICS The ldenotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 12V, RUN1,2,3 > 1.25V, EXTVCC = 0V, unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Gate Drivers
TG or BG On-Resistance
Pull-Up
Pull-Down
2.0
1.0
Ω
Ω
TG or BG Transition Time
Rise Time
Fall Time
(Note 6)
LOAD
LOAD
C
C
= 3300pF
= 3300pF
25
15
ns
ns
TG Off to BG On Delay
C
= 3300pF Each Driver
15
15
40
ns
ns
ns
LOAD
Synchronous Switch-On Delay Time
BG Off to TG On Delay
Top Switch-On Delay Time
C
= 3300pF Each Driver
LOAD
t
TG Minimum On-Time
(Note 7)
ON(MIN)
Maximum Duty Factor for TG
Channel 1
100
99
%
%
Channels 2,3, f
= 350kHz
98
20
OSC
BOOST1 Charge Pump Available
Output Current
V
= 16V, V
= 12V, f = 350kHz,
OSC
50
µA
BOOST1
SW1
Forced Continuous Mode
INTV Low Dropout (LDO) Linear Regulator
CC
INTV Regulation Point
4.9
4.5
5.1
5.3
V
CC
INTV Load Regulation
I
I
= 0mA to 100mA, V ≥ 6V
1.2
1.2
2
2
%
%
CC
CC
CC
IN
= 0mA to 100mA, V
≥ 6V
EXTVCC
EXTV LDO Switchover Voltage
EXTV Rising
4.7
4.8
V
CC
CC
EXTV Switchover Hysteresis
250
mV
CC
l
l
UVLO
Undervoltage Lockout
INTV Rising
4.10
3.75
4.20
3.90
4.35
4.00
V
V
CC
INTV Falling
CC
Spread Spectrum Oscillator and Phase-Locked Loop
f
Low Fixed Frequency
High Fixed Frequency
Programmable Frequency
V
V
= 0V, PLLIN/SPREAD = 0V
330
2.0
380
430
2.5
kHz
OSC
FREQ
l
= INTV , PLLIN/SPREAD = 0V
2.25
MHz
FREQ
CC
R
R
R
= 374kΩ, PLLIN/SPREAD = 0V
= 75kΩ, PLLIN/SPREAD = 0V
= 12kΩ, PLLIN/SPREAD = 0V
100
500
3
kHz
kHz
MHz
FREQ
FREQ
FREQ
450
550
3
l
Synchronizable Frequency Range
PLLIN/SPREAD = External Clock
0.1
2.2
MHz
l
l
PLLIN Input High Level
PLLIN Input Low Level
V
V
0.5
Spread Spectrum Frequency Range
PLLIN/SPREAD = INTV
Minimum Frequency
Maximum Frequency
CC
(Relative to f
)
0
+20
%
%
OSC
PGOOD1,2,3 Outputs
PGOOD Voltage Low
PGOOD Leakage Current
PGOOD Trip Level
I
= 2mA
= 5V
0.2
0.4
1
V
PGOOD
V
V
µA
PGOOD
Rising
7
10
2.5
13
%
%
FB
V
Relative to Set Regulation Point
Hysteresis
FB
V
Falling
–13
–10
2.5
–7
%
%
FB
Hysteresis
PGOOD Delay for Reporting a Fault
25
µs
Rev. 0
4
For more information www.analog.com
LTC7819
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4: The LTC7819 is tested in a feedback loop that servos V
to a
ITH1,2,3
specified voltage and measures the resultant V . The specification at
FB1,2,3
85°C is not tested in production and is assured by design, characterization
and correlation to production testing at other temperatures.
Note 2: The LTC7819R is specified over the –40°C to 150°C operating
junction temperature range. High junction temperatures degrade operating
lifetimes. Note that the maximum ambient temperature consistent with
these specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal impedance
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications information.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 7: The minimum on-time condition is specified for an inductor
and other environmental factors. The junction temperature (T , in °C) is
J
peak-to-peak ripple current >40% of I
(See Minimum On-Time
L(MAX)
calculated from the ambient temperature (T , in °C) and power dissipation
A
Considerations in the Applications Information section).
(P , in Watts) according to the formula: T = T + (P • θ ), where θ (in
D
J
A
D
JA
JA
Note 8: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 9: Do not apply a voltage or current source to these pins. They must
be connected to capacitive loads only, otherwise permanent damage may
occur.
°C/W) is the package thermal impedance.
–
Note 3: When SENSE1 ≥ 3.2V or EXTV ≥ 4.8V, V supply current
CC
IN
is transferred to these pins to reduce the total input supply quiescent
–
current. SENSE1 bias current is reflected to the channel 1 input supply by
the formula I
= I
– • V /(V • η), where η is the efficiency.
SENSE1 OUT1 IN1
VIN1
EXTV bias current is similarly reflected to the input supply when biased
CC
by an output. To minimize input supply current, select channel 1 to be the
lowest output voltage greater than 3.2V and connect EXTV to the lowest
CC
output voltage greater than 4.8V
Rev. 0
5
For more information www.analog.com
LTC7819
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency and Power Loss
vs Output Current
Efficiency vs Output Current
Burst Mode Operation
Efficiency vs Input Voltage
100
90
80
70
60
50
40
30
20
10
0
100
10
100
90
80
70
60
50
40
30
20
10
0
100
95
90
85
80
75
70
65
60
BURST EFFICIENCY
V
IN
= 12V
V
OUT2
= 5V
PULSE-SKIPPING
EFFICIENCY
V
OUT1
= 3.3V
FCM EFFICIENCY
1
FCM LOSS
V
OUT3
= 1V
PULSE-SKIPPING
LOSS
0.1
0.01
0.001
BURST
LOSS
I
I
= 5A
LOAD1,2
LOAD3
V
V
V
= 5V
= 3.3V
= 1V
OUT2
OUT1
OUT3
= 15A
V
V
= 12V
= 5V
IN
OUT
FIGURE 9 CIRCUIT
PULSE–SKIPPING MODE
FIGURE 9 CIRCUIT
10 100
FIGURE 9 CIRCUIT
0.0001 0.001
0.01
0.1
1
10
0.0001 0.001 0.01
0.1
1
0
5
10 15 20 25 30 35 40
INPUT VOLTAGE (V)
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
7819 G01
7819 G02
7819 G03
Load Step
Burst Mode Operation
Load Step
Pulse-Skipping Mode
Load Step
Forced Continuous Mode
V
V
OUT
OUT
V
OUT
500mV/DIV
500mV/DIV
500mV/DIV
INDUCTOR
CURRENT
5A/DIV
INDUCTOR
CURRENT
5A/DIV
INDUCTOR
CURRENT
5A/DIV
LOAD
CURRENT
5A/DIV
LOAD
CURRENT
5A/DIV
LOAD
CURRENT
5A/DIV
7819 G06
7819 G04
7819 G05
40µs/DIV
40µs/DIV
40µs/DIV
V
V
= 12V
= 5V
V
V
= 12V
= 5V
V
V
= 12V
= 5V
OUT
IN
OUT
IN
OUT
IN
500mA TO 8A LOAD STEP
FIGURE 9 CIRCUIT
500mA TO 8A LOAD STEP
FIGURE 9 CIRCUIT
500mA TO 8A LOAD STEP
FIGURE 9 CIRCUIT
Regulated Feedback Voltage
vs Temperature
Inductor Current at Light Load
Soft Start-Up
808
806
804
802
800
798
796
794
792
FORCED
CONTINUOUS
MODE
RUN1,2,3
5V/DIV
V
OUT2
1V/DIV
BURST MODE
OPERATION
2A/DIV
V
OUT1
1V/DIV
PULSE
SKIPPING
MODE
V
OUT3
1V/DIV
7819 G08
7819 G07
1ms/DIV
4µs/DIV
V
V
= 12V
OUT
NO LOAD
IN
V
= 12V
IN
= 5V
FORCED CONTINUOUS MODE
FIGURE 9 CIRCUIT
–55 –25
5
35
65
95 125 155
FIGURE 9 CIRCUIT
TEMPERATURE (°C)
7819 G09
Rev. 0
6
For more information www.analog.com
LTC7819
TYPICAL PERFORMANCE CHARACTERISTICS
Maximum Current Sense
Current Sense Threshold vs ITH
Voltage
SENSE1,2,3– Input Current
vs VSENSE Voltage
Threshold vs SENSE Common
Mode Voltage
70
60
50
40
30
20
10
0
50
40
900
800
700
600
500
400
300
200
100
0
PULSE-SKIPPING
BURST MODE
FORCED CONTINUOUS
–
SENSE1 CURRENT
30
20
–
–
SENSE2 OR SENSE3 CURRENT
10
0
–10
–20
–30
MODE = INTV
CC
0
5
10 15 20 25 30 35 40
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4
0
5
10 15 20 25 30 35 40
SENSE VOLTAGE (V)
ITH VOLTAGE (V)
SENSE VOLTAGE (V)
7819 G12
7819 G10
7819 G11
SENSE1,2,3– Input Current
vs Temperature
SENSE1,2,3+ Input Current
vs Temperature
Foldback Current Limit
1.0
0.8
70
60
50
40
30
20
10
0
900
800
700
600
500
400
300
200
100
0
MODE = INTV
MODE = INTV
CC
CC
SENSE = INTV + 0.5V
CC
0.6
SENSE = 3.3V
0.4
SENSE = 12V
0.2
0.0
SENSE = 1V
–0.2
–0.4
–0.6
–0.8
–1.0
SENSE = 0V
–
SENSE1 = INTV – 0.5V
CC
–
–
SENSE2 ,SENSE3 = INTV – 0.5V
CC
–100
–55 –25
5
35
65
95 125 155
0
100 200 300 400 500 600 700 800
–55 –25
5
35
65
95 125 155
TEMPERATURE (°C)
FEEDBACK VOLTAGE (mV)
TEMPERATURE (°C)
7819 G15
7819 G13
7819 G14
Oscillator Frequency
vs Temperature
RUN Pin Thresholds vs
Temperature
Output Voltage Noise Spectrum
6
5
0
1.26
1.24
1.22
1.20
1.18
1.16
1.14
1.12
1.10
1.08
1.06
FIGURE 9 CIRCUIT
–10 RBW = 510Hz, PEAK-HOLD
R
R
R
= 374k (100kHz)
= 75k (500kHz)
= 12k (3MHz)
RISING
FALLING
FREQ
FREQ
FREQ
4
–20
–30
–40
–50
–60
–70
–80
–90
–100
PLLIN/SPREAD = GND
PLLIN/SPREAD = INTV
CC
FREQ = GND (380kHz)
FREQ = INTV (2.25MHz)
3
CC
2
1
0
–1
–2
–3
–4
–55 –25
5
35
65
95 125 155
200
400
600
800 1000 1200 1400
–55 –25
5
35
65
95 125 155
TEMPERATURE (°C)
FREQUENCY (kHz)
TEMPERATURE (°C)
7819 G16
7819 G17
7819 G18
Rev. 0
7
For more information www.analog.com
LTC7819
TYPICAL PERFORMANCE CHARACTERISTICS
EXTVCC Switchover and INTVCC
Voltage vs Temperature
INTVCC Undervoltage Lockout
Thresholds vs Temperature
INTVCC Voltage vs Current
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
V
= 12V
IN
INTV VOLTAGE
CC
EXTV = 0V
CC
UVLO RISING
EXTV = 6V
CC
EXTV = 5V
CC
EXTV RISING
CC
UVLO FALLING
EXTV FALLING
CC
–55 –25
5
35 65 95 125 155
–55 –25
5
35 65 95 125 155
0
50
100 150 200 250 300
TEMPERATURE (°C)
TEMPERATURE (°C)
INTV LOAD CURRENT (mA)
CC
7819 G20
7819 G21
7819 G19
V
IN Quiescent Pin Current
TRACK/SS Pull-Up Current
vs Temperature
vs Temperature
Shutdown Current vs VIN Voltage
40
35
30
25
20
15
10
5
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
14.0
13.5
13.0
12.5
12.0
11.5
11.0
ALL CHANNELS ON
SLEEP MODE
150°C
–55°C
25°C
V
IN
= 12V
–
EXTV = 0V, SENSE1 = 0V
CC
–
EXTV = 0V, SENSE1 = 3.3V
CC
–
EXTV = 12V, SENSE1 = 3.3V
CC
0
–55 –25
5
35 65 95 125 155
0
5
10 15 20 25 30 35 40
INPUT VOLTAGE (V)
–55 –25
5
35 65 95 125 155
TEMPERATURE (°C)
V
IN
TEMPERATURE (°C)
7819 G22
7819 G23
7819 G24
BOOST1 Charge Pump Output
Current vs SW1 Voltage
BOOST1 Charge Pump Output
Current vs Frequency
BOOST1-SW1 Charge Pump
Voltage vs BOOST1 Current
100
7
6
5
4
3
2
1
0
100
90
80
70
60
50
40
30
20
10
0
BOOST1–SW1 = 4V
FREQ = 0V
BOOST1 = 16V
90 SW1 = 12V
FREQ = GND
SW1 = 12V
150°C
–55°C
25°C
80
70
60
50
40
30
20
10
0
150°C
–55°C
25°C
150°C
–55°C
25°C
0
500 1000 1500 2000 2500 3000
0
15
30
45
60
75
90
0
5
10 15 20 25 30 35
FREQUENCY (kHz)
BOOST1 CURRENT (µA)
SW1 VOLTAGE (V)
7819 G26
7819 G27
7819 G25
Rev. 0
8
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LTC7819
PIN FUNCTIONS
MODE (Pin 1): Mode Select Input. This input, which acts
on all three channels, determines how the LTC7819 oper-
ates at light loads. Pulling this pin to ground selects Burst
Mode operation. An internal 100k resistor to ground also
invokes Burst Mode operation when the pin is floating.
VIN (Pin 24): Main Bias Input Supply Pin. A bypass capac-
itor should be tied between this pin and ground.
PLLIN/SPREAD (Pin 34): External Synchronization Input
and Spread Spectrum Selection. When an external clock
is applied to this pin, the phase-locked loop will force
the rising TG1 signal to be synchronized with the ris-
ing edge of the external clock. When an external clock is
present, the regulators operate in pulse-skipping mode if
it is selected by the MODE pin, or in forced continuous
mode otherwise. When not synchronizing to an external
Tying this pin to INTV forces continuous inductor cur-
CC
rent operation. Tying this pin to INTV through a 100k
CC
resistor selects pulse-skipping operation.
PGOOD1, PGOOD2, PGOOD3 (Pins 17, 7, 33): Open-
Drain Power Good Outputs. The VFB pin of each channel
is monitored to ensure that V
is in regulation. When a
clock, tie this input to INTV to enable spread spectrum
OUT
CC
channel’s V
is not within 10% of its regulation point,
dithering of the oscillator or to ground to disable spread
OUT
the corresponding PGOOD pin is pulled low.
spectrum.
RUN1, RUN2, RUN3 (Pins 10, 9, 8): Run Control Inputs
for Each Controller. Forcing any of these pins below
1.1V disables switching of the corresponding control-
ler. Forcing all of these pins below 0.7V shuts down the
entire LTC7819, reducing the quiescent current to approx-
FREQ (Pin 40): Frequency Control Pin for the Internal
Oscillator. Connect to ground to set the switching fre-
quency to 380KHz. Connect to INTV to set the switch-
CC
ing frequency to 2.25MHz. Frequencies between 100kHz
and 3MHz can be programmed using a resistor between
the FREQ pin and ground. Minimize the capacitance on
this pin.
imately 1.5µA. These pins can be tied to V for always-on
IN
operation.
VPRG1 (Pin 16): Channel 1 Voltage Programming Pin.
This pin sets channel 1 to adjustable output voltage or to
a fixed output voltage. Floating this pin allows the channel
1 output to be programmed through the VFB1 pin using
external resistors, regulating VFB1 to the 0.8V reference.
BG1, BG2, BG3 (Pins 25, 21, 29): High Current Gate
Drives for Bottom N-Channel MOSFETs. Voltage swing at
these pins is from ground to INTV .
CC
BOOST1, BOOST2, BOOST3 (Pins 26, 20, 30):
Bootstrapped Supplies to the Top Side Floating Drivers.
Connect capacitors between the corresponding BOOST
and SW pins for each channel. Also connect Schottky
diodes between the BOOST and INTVCC pins Voltage
Connecting this pin to GND or INTV programs the out-
CC
put voltage to 3.3V or 5V (respectively), with VFB1 directly
connected to the output.
INTV (Pin 22): Output of the Internal 5.1V Low Dropout
swing at the BOOST pins is from INTV to (V +INTV ).
CC
CC IN CC
Regulator. The driver and control circuits are powered by
this supply. Must be decoupled to ground with a minimum
of 4.7μF ceramic or tantalum capacitor.
SW1, SW2, SW3 (Pins 28, 19, 31): Switch Node
Connections to Inductors.
TG1, TG2, TG3 (Pins 27, 18, 32): High Current Gate
Drives for Top N-Channel MOSFETs. These are the out-
EXTVCC (Pin 23): External Power Input to an Internal LDO
Connected to INTV . This LDO supplies INTV power,
CC
CC
puts of floating drivers with a voltage swing of INTV
superimposed on the switch node voltage SW.
CC
bypassing the internal LDO powered from V whenever
IN
EXTVCC is higher than 4.7V. See INTVCC Regulators in the
TRACK/SS1, TRACK/SS2, TRACK/SS3 (Pins 2, 15, 35):
Applications Information section. Do not exceed 30V on
External Tracking and Soft-Start Input. The LTC7819 regu-
this pin. Connect this pin to ground if the EXTV LDO
CC
−
lates the negative input of the Error Amplifier (EA ) volt-
is not used.
age to the lesser of 0.8V or the voltage on the TRACK/
Rev. 0
9
For more information www.analog.com
LTC7819
PIN FUNCTIONS
application, where the associated channel is a slave to
SS1,2,3 pin. Internal 12.5µA pull-up current sources are
connected to these pins. A capacitor to ground sets the
startup ramp time to the final regulated output voltage.
The ramp time is equal to 0.65ms for every 10nF of capac-
itance. Alternatively, a resistor divider on another volt-
age supply connected to the TRACK/SS pins allows the
LTC7819 output to track the other supply during startup.
Channel 1, sharing V , ITH1, and TRACK/SS1. Tie both
FB1
V
and V to INTV to configure the LTC7819 for a
FB2
FB3 CC
three-phase single output application, in which all three
channels share V , ITH1, and TRACK/SS1.
FB1
SENSE1+, SENSE2+, SENSE3+ (Pins 4, 12, 38): The
Positive (+) Input to the Differential Current Comparators.
The ITH pin voltage and controlled offsets between the
ITH1, ITH2, ITH3 (Pins 6, 14, 36): Error Amplifier Outputs
and Regulator Compensation Points. Each associated
channel’s current comparator trip point increases with
this control voltage. Place compensation components
between the ITH pins and ground.
−
+
SENSE and SENSE pins in conjunction with R
the current trip threshold.
set
SENSE
SENSE1−, SENSE2−, SENSE3− (Pins 3, 11, 39): The
Negative (−) Input to the Differential Current Comparators.
−
When SENSE1 is 3.2V or greater, it supplies the major-
VFB1 (Pin 5): Channel 1 Controller Feedback Input. When
ity of the sleep mode quiescent current instead of VIN,
further reducing the input-referred quiescent current. The
VPRG1 is floating, connect an external resistor divider
between the output voltage and the V
pin to set the
FB1
−
SENSE pins supply current to the current comparators
regulated voltage. When VPRG1 is connected to ground
or INTV , tie V directly to the output.
when they are greater than INTV .
CC
CC
FB1
GND (Exposed Pad Pin 41): Ground. Connects to the
sources of bottom N-channel MOSFETs and the (−)
terminal(s) of decoupling capacitors. The exposed pad
must be soldered to PCB ground for rated electrical and
thermal performance.
VFB2, VFB3 (Pins 13, 37): Channel 2, 3 Controller
Feedback Inputs. Connect an external resistor divider
between the output voltage and the VFB pin to set the
regulated output voltage. Tie either VFB2 or VFB3 to INTVCC
to configure that channel for a two-phase single output
Rev. 0
10
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LTC7819
FUNCTIONAL DIAGRAM
CHANNEL 1
INTV
CC
RUN1
D
B1
V
IN
CHARGE
BOOST1
TG1
C
PUMP
B1
C
IN1
TOP
ALLOFF
1.2V
L1
R
SENSE1
SW1
CLK1
V
OUT1
FREQ
S
SPREAD
SPECTRUM
OSCILLATOR
AND PLL
TOP ON
SWITCH
LOGIC
Q
INTV
OV
CC
CLK2
C
OUT1
R
PLLIN/SPREAD
CLK3
BOT
BG1
0.425V
GND
SLEEP
MODE
ICMP
IR
100k
V
IN
2mV
SENSE1+
EXTV
CC
SENSE1-
SLOPE COMP
4.7V
R
R1
B1
V
V
OUT1
FB1
VPRG1
V
OUT1
FLOAT
ADJUSTABLE
3.3V FIXED
5V FIXED
EN
EN
EA
0.8V
5.1V
5.1V
GND
R2
R
A1
INTV
VPRG1
CC
V
LDO
IN
EXTV LDO
CC
R
C1
INTV
CC
ITH1
0.88V
PGOOD1
C
G1
C
C1
TRACK/SS1
12.5µA
C
SS1
ITH
CLAMP
1.4V
0.72V
ALLOFF
CHANNELS 2 AND 3
INTV
CC
V
IN
RUN
D
B
BOOST
TG
C
IN
ALLOFF
C
B
1.2V
TOP
DROPOUT
DETECT
L
R
SENSE
SW
SWITCH
LOGIC
CLK
S
V
OUT
TOP ON
Q
OV
INTV
CC
R
C
OUT
BOT
BG
0.425V
GND
SLEEP
MODE
ICMP
IR
2mV
SENSE+
SENSE-
SLOPE COMP
RB
V
FB
V
OUT
EA
0.8V
RA
0.88V
PGOOD
V
FB
R
C
ITH
C
G
C
C
12.5µA
0.72V
TRACK/SS
ITH
CLAMP
1.4V
ALLOFF
C
SS
7819 BD
Rev. 0
11
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LTC7819
OPERATION (Refer to Functional Diagram)
Main Control Loop
Each top MOSFET driver is biased from the floating bootstrap
capacitor C , which normally recharges during each cycle
B
The LTC7819 is a triple step-down (buck) synchronous
controller utilizing a constant frequency, peak current
mode architecture. The three controller channels oper-
ate 120° out of phase which reduces the required input
capacitance and power supply induced noise. During nor-
mal operation, the external top MOSFET is turned on when
the clock for that channel sets the SR latch, causing the
inductor current to increase. The main switch is turned off
when the main current comparator, ICMP, resets the SR
latch. After the top MOSFET is turned off each cycle, the
bottom MOSFET is turned on which causes the inductor
current to decrease until either the inductor current starts
to reverse, as indicated by the current comparator IR, or
the beginning of the next clock cycle.
through an external diode when the switch voltage goes low.
If the input voltage decreases to a voltage close to the
regulation point, the bottom MOSFET on-time may be too
short to recharge the bootstrap capacitor. The LTC7819
detects this and extends the bottom MOSFET on-time
every tenth cycle to charge the bootstrap capacitor. If
the input voltage drops below the regulation point, the
loop may enter dropout and attempt to turn on the top
MOSFET continuously. For Channel 1, an internal charge
pump charges C , which enables the top MOSFET to be
B
turned on continuously. For Channels 2 and 3, the top
MOSFET is forced off for a short time every tenth cycle
to allow C to recharge, resulting in a 99% duty cycle at
B
380kHz operation and approximately 98% duty cycle at
The peak inductor current at which ICMP trips and resets
the latch is controlled by the voltage on the ITH pin, which
is the output of the error amplifier EA. The error ampli-
fier compares the output voltage feedback signal at the
2MHz operation.
Start-Up and Shutdown (RUN and TRACK/SS Pins)
The three channels of the LTC7819 can be independently
shut down using the RUN1, RUN2, and RUN3 pins. Pulling
a RUN pin below 1.1V shuts down the main control loop
for that channel. Pulling all three RUN pins below 0.7V
disables the controllers and most internal circuits, includ-
ing the INTVCC LDOs. In this shutdown state, the LTC7819
draws only 1.5μA of quiescent current.
V
pin, (which is generated with a resistor divider con-
FB
nected across the output voltage, V , to ground) to the
OUT
internal 0.8V reference voltage. When the load current
increases, it causes a slight decrease in VFB relative to
the reference,which causes the EA to increase the ITH
voltage until the average inductor current matches the
new load current.
The RUN pins may be externally pulled up or driven
directly by logic. Each pin can tolerate up to 40V (abso-
Power and Bias Supplies (V , EXTV , and INTV )
IN
CC
CC
The INTVCC pin supplies power for the top and bottom
MOSFET drivers and most of the internal circuitry. LDOs
(low dropout linear regulators) are available from both the
V and EXTV pins to provide power to INTV , which
lute maximum), so it can be conveniently tied to V in
IN
always-on applications where one or more controllers are
enabled continuously and never shut down. Additionally,
a resistive divider from V to a RUN pin can be used to
IN
CC
CC
IN
has a regulation point of 5.1V. When the EXTV pin is
set a precise input undervoltage lockout so that the power
CC
left open or tied to a voltage less than 4.7V, the V LDO
supply does not operate below a user adjustable level.
IN
supplies power to INTV . If EXTV is taken above 4.7V
CC
CC
The start-up of each channel’s output voltage V
is con-
OUT
(typical), the VIN LDO is turned off and the EXTVCC LDO is
turned on. Once enabled, the EXTVCC LDO supplies power
to INTVCC. Using the EXTVCC pin allows the INTVCC power
to be derived from a high efficiency external source such
as one of the LTC7819 switching regulator outputs.
trolled by the voltage on the corresponding TRACK/SS
pin. When the voltage on the TRACK/SS pin is less than
the 0.8V internal reference voltage, the LTC7819 regulates
the V voltage to the TRACK/SS pin voltage instead of
FB
the 0.8V reference voltage. This allows the TRACK/SS pin
to be used as a soft-start which smoothly ramps the out-
put voltage on start-up, thereby limiting the input supply
Rev. 0
12
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LTC7819
OPERATION
–
inrush current. An external capacitor from the TRACK/
SS pin to GND is charged by an internal 12.5μA pull-up
current, creating a voltage ramp on the TRACK/SS pin. As
the TRACK/SS voltage rises linearly from 0V to 0.8V (and
beyond), the output voltage VOUT rises smoothly from
zero to its final value.
quiescent current is supplied by the SENSE1 pin, which
further reduces the input-referred quiescent current by
the ratio of V /V
multiplied by the efficiency.
IN OUT
In sleep mode, the load current is supplied by the output
capacitor. As the output voltage decreases, the EA’s out-
put begins to rise. When the output voltage drops enough,
the ITH pin is reconnected to the output of the EA, the
sleep signal goes low, and the controller resumes normal
operation by turning on the top MOSFET on the next cycle
of the internal oscillator.
Alternatively, the TRACK/SS pins can be used to make the
start-up of VOUT track that of another supply. Typically
this requires connecting to the TRACK/SS pin through an
external resistor divider from the other supply to ground
(see the Applications Information section).
When a controller is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The reverse
current comparator (IR) turns off the bottom MOSFET
just before the inductor current reaches zero, preventing
it from reversing and going negative. Thus, the controller
operates in discontinuous operation.
Light Load Operation: Burst Mode Operation, Pulse-
Skipping, or Forced Continuous Mode (MODE Pin)
The LTC7819 can be set to enter high efficiency Burst Mode
operation, constant frequency pulse-skipping mode or forced
continuous conduction mode at low load currents.
In forced continuous operation the inductor current is
allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined by
the voltage on the ITH pin, just as in normal operation.
In this mode, the efficiency at light loads is lower than
in Burst Mode operation. However, continuous operation
has the advantage of lower output voltage ripple and less
interference to audio circuitry. In forced continuous mode,
the output ripple is independent of load current.
To select Burst Mode operation, tie the MODE pin to
ground. To select forced continuous operation, tie the
MODE pin to INTV . To select pulse-skipping mode, tie
CC
the MODE pin to a DC voltage greater than 1.2V and less
than INTV – 1.3V. An internal 100k resistor to ground
invokes BCuCrst Mode operation when the MODE pin is
floating and pulse-skipping mode when the MODE pin is
tied to INTV through an external 100k resistor.
CC
When the controllers are enabled for Burst Mode opera-
tion, the minimum peak current in the inductor is set to
approximately 25% of its maximum value even though the
voltage on the ITH pin might indicate a lower value. If the
average inductor current is higher than the load current,
the error amplifier EA will decrease the voltage on the ITH
pin. When the ITH voltage drops below 0.425V, the internal
sleep signal goes high (enabling sleep mode) and both
external MOSFETs are turned off. The ITH pin is then dis-
connected from the output of the EA and parked at 0.45V.
When the MODE pin is connected for pulse-skipping
mode, the LTC7819 operates in PWM pulse-skipping
mode at light loads. In this mode, constant frequency
operation is maintained down to approximately 1% of
designed maximum output current. At very light loads, the
current comparator ICMP may remain tripped for several
cycles and force the top MOSFET to stay off for the same
number of cycles (i.e., skipping pulses). The inductor cur-
rent is not allowed to reverse (discontinuous operation).
This mode, like forced continuous operation, exhibits low
output ripple as well as low audio noise and reduced RF
interference as compared to Burst Mode operation. It pro-
vides higher low current efficiency than forced continuous
mode, but not nearly as high as Burst Mode operation.
In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current that the LTC7819 draws.
If one channel is in sleep mode and the other channels
are shut down, the LTC7819 draws only 15μA of quies-
cent current. If all three channels are in sleep mode, the
LTC7819 draws only 18μA of quiescent current. When
Unlike forced continuous mode and pulse-skipping mode,
Burst Mode cannot be synchronized to an external clock.
V
on channel 1 is 3.2V or higher, the majority of this
OUT
Rev. 0
13
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LTC7819
OPERATION
Therefore, if Burst Mode is selected and the switching
frequency is synchronized to an external clock applied to
the PLLIN/SPREAD pin, the LTC7819 switches from Burst
Mode to forced continuous mode.
clock, use the FREQ pin to set the internal oscillator to
approximately the frequency of the external clock. The
LTC7819’s PLL is guaranteed to lock to an external clock
source whose frequency is between 100kHz and 3MHz.
The PLLIN/SPREAD pin is TTL compatible with thresholds
of 1.6V (rising) and 1.1V (falling) and is guaranteed to
operate with a clock signal swing of 0.5V to 2.2V.
Frequency Selection, Spread Spectrum, and Phase-
Locked Loop (FREQ and PLLIN/SPREAD Pins)
The free running switching frequency of the LTC7819
controllers is selected using the FREQ pin. Tying FREQ to
GND selects 380kHz while tying FREQ to INTV selects
2.25MHz. Placing a resistor between FREQ CaCnd GND
allows the frequency to be programmed between 100kHz
and 3MHz.
Output Overvoltage Protection
Each channel has an overvoltage comparator that guards
against transient overshoots as well as other more seri-
ous conditions that may overvoltage the output. When
the VFB1,2,3 pin rises more than 10% above its regula-
tion point, the top MOSFET is turned off and the bottom
MOSFET is turned on until the overvoltage condition is
cleared.
Switching regulators can be particularly troublesome for
applications where electromagnetic interference (EMI) is
a concern. To improve EMI, the LTC7819 can operate in
spread spectrum mode, which is enabled by tying the
PLLIN/SPREAD pin to INTVCC. This feature varies the
switching frequency 0% to 20% higher than the frequency
set by the FREQ pin.
Foldback Current
When the output voltage falls to less than 50% of its
nominal level, foldback current limiting is activated, pro-
gressively lowering the peak current limit in proportion to
the severity of the overcurrent or short-circuit condition.
Foldback current limiting is disabled during the soft-start
A phase-locked loop (PLL) is available on the LTC7819
to synchronize the internal oscillator to an external
clock source connected to the PLLIN/SPREAD pin. The
LTC7819’s PLL aligns the turn-on of controller 1’s external
top MOSFET to the rising edge of the synchronizing signal.
Thus, the turn-on of controller 2’s top MOSFET is 120° out-
of-phase to the rising edge of the external clock source,
and the turn-on of controller 3’s top MOSFET is 240° out-
of-phase to the rising edge of the external clock source.
interval (as long as the V voltage is keeping up with the
FB
TRACK/SS1,2,3 voltage).
Power Good
Each channel has a PGOOD pin that is connected to an
open drain of an internal N-channel MOSFET. The MOSFET
turns on and pulls the PGOOD pin low when the V volt-
FB
The PLL frequency is prebiased to the free running fre-
quency set by the FREQ pin before the external clock is
applied. If prebiased near the external clock frequency,
the PLL only needs to make slight changes in order to
synchronize the rising edge of the external clock to the
rising edge of TG1. For more rapid lock-in to the external
age is not within 10% of its regulation point. The PGOOD
pin is also pulled low when the RUN pin is low (shut
down). When the V voltage is within the 10% require-
FB
ment, the MOSFET is turned off and the pin is allowed to
be pulled up by an external resistor to a source no greater
than 6V, such as INTV .
CC
Rev. 0
14
For more information www.analog.com
LTC7819
APPLICATIONS INFORMATION
The Typical Application on the first page is a basic
LTC7819 application circuit. External component selection
is largely driven by the load requirement and begins with
the selection of the inductor, current sense components,
operating frequency, and light load operating mode. The
remaining power stage components, consisting of the
input and output capacitors, and power MOSFETs can
then be chosen. Next, feedback resistors are selected
to set the desired output voltage. Then, the remaining
external components are selected, such as for soft-start,
biasing, and loop compensation.
The inductor value also has secondary effects. The tran-
sition to Burst Mode operation begins when the average
inductor current required results in a peak current below
25% of the current limit determined by RSENSE. Lower
inductor values (higher ΔI ) will cause this to occur at
L
lower load currents, which can cause a dip in efficiency
in the upper range of low current operation.
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High efficiency regulators generally can-
not afford the core loss found in low cost powdered
iron cores, forcing the use of more expensive ferrite or
molypermalloy cores. Actual core loss is very dependent
on inductance value selected. As inductance increases,
core losses go down. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
Inductor Value Calculation
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because
of MOSFET switching and gate charge losses. In addi-
tion to this basic trade-off, the effect of inductor value
on ripple current and low current operation must also
be considered. The inductor value has a direct effect on
ripple current.
Ferrite designs have very low core loss and are preferred
for high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates hard, which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
The maximum average inductor current I
is equal
L(MAX)
to the maximum output current. The peak current is equal
to the average inductor current plus half of the inductor
Current Sense Selection
ripple current, ΔI , which decreases with higher induc-
L
tance or higher frequency and increases with higher V :
IN
The LTC7819 can be configured to use either DCR (induc-
tor resistance) sensing or low value resistor sensing.
The choice between the two current sensing schemes
is largely a design trade-off between cost, power con-
sumption and accuracy. DCR sensing has become popular
because it saves expensive current sensing resistors and
is more power efficient, particularly in higher current and
lower frequency applications. However, current sensing
resistors provide the most accurate current limits for the
controller. Other external component selection is driven
by the load requirement and begins with the selection of
⎛
⎜
⎝
⎞
⎟
⎠
1
V
OUT
ΔI =
V
1−
L
OUT
(f)(L)
V
IN
Accepting larger values of ΔIL allows the use of low induc-
tances, but results in higher output voltage ripple and
greater core losses. A reasonable starting point for setting
ripple current is ΔIL = 0.3 • IL(MAX). The maximum ΔIL
occurs at the maximum input voltage.
R
SENSE
(if R
is used) and inductor value.
SENSE
Rev. 0
15
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LTC7819
APPLICATIONS INFORMATION
+
–
The SENSE and SENSE pins are the inputs to the cur-
rent comparators. The common mode voltage range on
these pins is 0V to 40V (absolute maximum), enabling
the LTC7819 to regulate output voltages up to a maxi-
Low Value Resistor Current Sensing
A typical sensing circuit using a discrete resistor is shown
in Figure 2a. R
is chosen based on the required out-
SENSE
put current. Each controller’s current comparator has a
maximum threshold VSENSE(MAX) of 50mV. The current
comparator threshold voltage sets the peak inductor
current.
+
mum of 40V. The SENSE pin is high impedance, drawing
less than ≈1μA. This high impedance allows the current
comparators to be used in inductor DCR sensing. The
–
impedance of the SENSE pin changes depending on the
Using the maximum inductor current (I
) and ripple
common mode voltage. When less than INTV – 0.5V,
L(MAX)
CC
current (ΔI ) from the Inductor Value Calculation section,
these pins are relatively high impedance, drawing ≈ 1μA.
L
the target sense resistor value is:
When above INTV + 0.5V, a higher current (≈650μA)
CC
flows into each pin. Between INTV – 0.5V and INTV
CC
CC
VSENSE(MAX)
RSENSE
≤
+ 0.5V, the current transitions from the smaller current to
the higher current. Channel 1’s SENSE1– pin has an addi-
tional ≈ 50μA current when its voltage is above 3.2V to
ΔIL
IL(MAX)
+
2
bias internal circuitry from V
instead of V , thereby
OUT1
IN
To ensure that the application will deliver full load cur-
rent over the full operating temperature range, choose
the minimum value for VSENSE(MAX) in the Electrical
Characteristics table.
reducing the input-referred supply current.
Filter components mutual to the sense lines should be
placed close to the LTC7819, and the sense lines should
run close together to a Kelvin connection underneath the
current sense element (shown in Figure 1). Sensing cur-
rent elsewhere can effectively add parasitic inductance
and capacitance to the current sense element, degrading
the information at the sense terminals and making the
programmed current limit unpredictable. If DCR sensing
is used (Figure 2b), resistor R1 should be placed close to
the switching node, to prevent noise from coupling into
sensitive small signal nodes.
To avoid potential jitter or instability due to PCB noise cou-
pling into the current sense signal, the AC current sensing
ripple of ΔV
= ΔI • R
should also be checked
SENSE
L
SENSE
to ensure a good signal-to-noise ratio. In general, for a
reasonably good PCB layout, a target ΔV voltage of
SENSE
10mV to 20mV at nominal input voltage is recommended
for both R and DCR sensing applications.
SENSE
The parasitic inductance (ESL) of the sense resistor
introduces significant error in the current sense signal
for lower inductor value (<3uH) or higher current (>5A)
applications. This error is proportional to input voltage
and may degrade line regulation or cause loop instability.
An RC filter into the sense pins, as shown in Figure 2a, can
be used to compensate for this error. Set the RC filter time
TO SENSE FILTER
NEXT TO THE CONTROLLER
CURRENT FLOW
constant R • C = ESL/R for optimal cancellation of
F
F
SENSE
7802 F01
INDUCTOR OR R
SENSE
the ESL. In general, select C to be in the range of 1nF to
F
10nF and calculate the corresponding R Surface mount
Figure 1. Sense Lines Placement with Inductor or
Sense Resistor
F.
sense resistors in low ESL wide footprint geometries are
recommended to minimize this error. If not specified on
the manufacturer’s data sheet, the ESL can be approxi-
mated as 0.4nH for a resistor with a 1206 footprint and
0.2nH for a 1225 footprint.
Rev. 0
16
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LTC7819
Inductor DCR Current Sensing
Next, determine the DCR of the inductor. When provided,
use the manufacturer’s maximum value, usually given at
20°C. Increase this value to account for the temperature
coefficient of copper resistance, which is approximately
For applications requiring the highest possible efficiency
at high load currents, the LTC7819 is capable of sensing
the voltage drop across the inductor DCR, as shown in
Figure 2b. The DCR of the inductor represents the small
amount of DC winding resistance of the copper, which
can be less than 1mΩ for today’s low value, high current
inductors. In a high current application requiring such
an inductor, power loss through a sense resistor would
cost several points of efficiency compared to inductor
DCR sensing.
0.4%/°C. A conservative value for T
is 100°C. To
L(MAX)
scale the maximum inductor DCR to the desired sense
resistor value, use the divider ratio:
R
SENSE(EQUIV)
R =
D
DCR
at T
L(MAX)
MAX
C1 is usually selected to be in the range of 0.1μF to 0.47μF.
This forces R1||R2 to around 2k, reducing error that might
If the external (R1||R2) • C1 time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across the external capacitor is equal to the drop across
the inductor DCR multiplied by R2/(R1+R2). R2 scales the
voltage across the sense terminals for applications where
the DCR is greater than the target sense resistor value.
To properly dimension the external filter components, the
DCR of the inductor must be known. It can be measured
using a good RLC meter, but the DCR tolerance is not
always the same and varies with temperature; consult
the manufacturers’ data sheets for detailed information.
+
have been caused by the SENSE pin’s ≈1μA current.
The target equivalent resistance R1||R2 is calculated from
the nominal inductance, C1 value, and DCR:
L
R1!R2 =
(DCR at 20°C)•C1
The sense resistor values are:
R1!R2
RD
R1•RD
1−RD
R1=
; R2 =
Using the maximum inductor current (I
) and ripple
L(MAX)
The maximum power loss in R1 is related to duty cycle
and occurs in continuous mode at the maximum input
voltage:
current (ΔI ) from the Inductor Value Calculation section,
L
the target sense resistor value is:
VSENSE(MAX)
RSENSE(EQUIV)
=
(VIN(MAX) − VOUT)• VOUT
ΔIL
PLOSS R1=
ILMAX
+
R1
2
To ensure that the application will deliver full load cur-
rent over the full operating temperature range, choose
the minimum value for VSENSE(MAX) in the Electrical
Characteristics table.
Rev. 0
17
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LTC7819
APPLICATIONS INFORMATION
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing
or sense resistors. Light load power loss can be mod-
estly higher with a DCR network than with a sense resis-
tor, due to the extra switching losses incurred through
R1. However, DCR sensing eliminates a sense resistor,
reduces conduction losses and provides higher efficiency
at heavy loads. Peak efficiency is about the same with
either method.
V
IN
TG
BOOST
SW
SENSE RESISTOR
WITH PARASITIC
INDUCTANCE
R
L
ESL
R *C = ESL/R
SENSE
SENSE
V
OUT
LTC7819
F
F
POLE-ZERO
CANCELLATION
BG
R
F
+
SENSE
C
F
–
SENSE
PLACE R AND C NEAR SENSE PINS
F
F
7819 F02a
Setting the Operating Frequency
(2a) Using a Resistor to Sense Current
Selection of the operating frequency is a trade-off between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing gate charge and transition losses, but requires
larger inductance values and/or more output capacitance
to maintain low output ripple voltage.
V
IN
BOOST
TG
INDUCTOR
DCR
LTC7819
L
V
OUT
SW
BG
R1
In higher voltage applications transition losses contrib-
ute more significantly to power loss, and a good balance
between size and efficiency is generally achieved with a
switching frequency between 300kHz and 900kHz. Lower
voltage applications benefit from lower switching losses
and can therefore more readily operate at higher switch-
ing frequencies up to 3MHz if desired. The switching fre-
quency is set using the FREQ and PLLIN/SPREAD pins
as shown in Table 1.
+
SENSE
C1*
R2
–
SENSE
GND
7819 F02b
(R1||R2) • C1 = L/DCR
R = DCR(R2/(R1+R2))
SENSE(EQ)
*PLACE C1 NEAR SENSE PINS
(2b) Using the Inductor DCR to Sense Current
Figure 2. Current Sensing Methods
Rev. 0
18
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LTC7819
APPLICATIONS INFORMATION
Table 1.
10M
FREQ PIN
PLLIN/SPREAD PIN
FREQUENCY
380kHz
0V
0V
0V
0V
INTV
2.25MHz
CC
Resistor to GND
Any of the Above
100kHz to 3MHz
1M
External Clock 100kHz Phase-Locked to
to 3MHz
External lock
Any of the Above
INTV
Spread Spectrum f
CC
OSC
Modulated 0% to 20%
100k
Tying the FREQ pin to ground selects 380kHz while tying
FREQ to INTVCC selects 2.25MHz. Placing a resistor
between FREQ and ground allows the frequency to be pro-
grammed anywhere between 100kHz and 3MHz. Choose a
FREQ pin resistor from Figure 3 or the following equation:
10k
100k
500k
FREQ PIN RESISTOR (Ohms)
7819 F03
Figure 3. Relationship Between Oscillator Frequency and
Resistor Value at the FREQ Pin
Selecting the Light-Load Operating Mode
37MHz
R
(in kΩ) =
FREQ
The LTC7819 can be set to enter high efficiency Burst
Mode operation, constant frequency pulse-skipping mode
or forced continuous conduction mode at light load cur-
rents. To select Burst Mode operation, tie the MODE to
ground. To select forced continuous operation, tie the
f
OSC
To improve electromagnetic interference (EMI) perfor-
mance, spread spectrum mode can optionally be selected
by tying the PLLIN/SPREAD pin to INTV . When spread
spectrum is enabled, the switching frequency modulates
0% to 20% above the frequency selected by the FREQ
pin. Spread spectrum may be used in any operating mode
selected by the MODE pin (Burst Mode, pulse-skipping,
or forced continuous mode).
CC
MODE pin to INTV . To select pulse-skipping mode, tie
CC
the MODE pin to INTVCC through a 100k resistor. An inter-
nal 100k resistor from the MODE pin to ground selects
Burst Mode if the pin is floating. When synchronized to
an external clock through the PLLIN/SPREAD pin, the
LTC7819 operates in pulse-skipping mode if it is selected,
or in forced continuous mode otherwise. Table 2 sum-
marizes the use of the MODE pin to select the light load
operating mode.
A phase-locked loop (PLL) is also available on the
LTC7819 to synchronize the internal oscillator to an exter-
nal clock source connected to the PLLIN/SPREAD pin.
After the PLL locks, TG1 is synchronized to the rising
edge of the external clock signal, TG2 is 120º out of phase
from TG1, and TG3 is 240º out of phase from TG1. See
the Phase-Locked Loop and Frequency Synchronization
section for details.
Table 2.
LIGHT-LOAD
OPERATING MODE
MODE WHEN
SYNCHRONIZED
MODE PIN
0V or Floating
Burst Mode
Forced Continuous
Pulse-Skipping
100k to INTV
Pulse-Skipping
Forced Continuous
CC
INTV
Forced Continuous
CC
Rev. 0
19
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LTC7819
APPLICATIONS INFORMATION
MODE pin set to 0V. When the system wakes, one might
send an external clock to PLLIN/SPREAD, or tie MODE to
INTV to switch to low noise forced continuous mode.
SuchCCon-the-fly mode changes can allow an individual
application to benefit from the advantages of each light
load operating mode.
In general, the requirements of each application will
dictate the appropriate choice for light-load operating
mode. In Burst Mode operation, the inductor current is
not allowed to reverse. The reverse current comparator
turns off the bottom MOSFET just before the inductor
current reaches zero, preventing it from reversing and
going negative. Thus, the regulator operates in discon-
tinuous operation. In addition, when the load current is
very light, the inductor current will begin bursting at fre-
quencies lower than the switching frequency and enter a
low current sleep mode when not switching. As a result,
Burst Mode operation has the highest possible efficiency
at light load.
Power MOSFET Selection
Two external power MOSFETs must be selected for each
controller in the LTC7819: one N-channel MOSFET for
the top (main) switch and one N-channel MOSFET for
the bottom (synchronous) switch. The peak-to-peak
gate drive levels are set by the INTV regulation point of
CC
5.1V. Consequently, logic level threshold MOSFETs must
be used in most applications. Pay close attention to the
logDicSSlevel MOSFETs are limited to 30V or less.
In forced continuous mode, the inductor current is
allowed to reverse at light loads and switches at the same
frequency regardless of load. In this mode, the efficiency
at light loads is considerably lower than in Burst Mode
operation. However, continuous operation has the advan-
tage of lower output voltage ripple and less interference
to audio circuitry. In forced continuous mode, the output
ripple is independent of load current.
BV
specification for the MOSFETs as well; many of the
Selection criteria for the power MOSFETs include the on
resistance RDS(ON), Miller capacitance CMILLER, input volt-
age, and maximum output current. Miller capacitance,
C , can be approximated from the gate charge curve
MILLER
usually provided on the MOSFET manufacturers’ data
sheet. CMILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
In pulse-skipping mode, constant frequency operation
is maintained down to approximately 1% of designed
maximum output current. At very light loads, the PWM
comparator may remain tripped for several cycles and
force the top MOSFET to stay off for the same number of
cycles (i.e., skipping pulses). The inductor current is not
allowed to reverse (discontinuous operation). This mode,
like forced continuous operation, exhibits low output rip-
ple as well as low audio noise and reduced RF interference
as compared to Burst Mode operation. It provides higher
light load efficiency than forced continuous mode, but not
nearly as high as Burst Mode operation. Consequently,
pulse-skipping mode represents a compromise between
light load efficiency, output ripple and EMI.
flat divided by the specified change in V . This result is
DS
then multiplied by the ratio of the application applied V
to the gate charge curve specified VDS. When the ICDisS
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
V
OUT
MAIN SWITCH DUTY CYCLE =
V
IN
V
– V
OUT
IN
SYNCHRONOUS SWITCH DUTY CYCLE =
V
IN
In some applications, it may be desirable to change light
load operating mode based on the conditions present in
the system. For example, if a system is inactive, one might
select high efficiency Burst Mode operation by keeping the
Rev. 0
20
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LTC7819
APPLICATIONS INFORMATION
The MOSFET power dissipations at maximum output cur-
rent are given by:
a factor of 30% to 70% when compared to a single-phase
power supply solution.
VOUT
In continuous mode, the source current of the top
2
PMAIN
=
I
1+ δ R
+
(
)
(
)
MAX
DS(ON)
MOSFET is a square wave of duty cycle V /V . To pre-
OUT IN
V
IN
vent large voltage transients, a low ESR capacitor sized
for the maximum RMS current of one channel must be
used. At maximum load current IMAX, the maximum RMS
capacitor current is given by:
I
⎛
⎞
(V )2
(R )(CMILLER)•
MAX
⎜
⎟
⎠
IN
DR
⎝
2
⎡
⎢
⎤
1
1
+
(f)
⎥
IMAX
V
⎣ INTVCC − VTHMIN VTHMIN
1/2
⎦
⎡
⎤
CIN Required IRMS
≈
V V − V
OUT)(
IN
OUT
(
)
⎦
⎣
V
V − V
2
IN
IN
OUT
PSYNC
=
I
1+ δ R
( )
DS(ON)
(
)
MAX
V
IN
This formula has a maximum at V = 2V , where I
RMS
IN
OUT
= I /2. This simple worst-case condition is commonly
OUT
where δ is the temperature dependency of R
(δ ≈
DS(ON)
used for design because even significant deviations do
not offer much relief. Note that capacitor manufacturers’
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the capaci-
tor, or to choose a capacitor rated at a higher temperature
than required. Several capacitors may be paralleled to
meet size or height requirements in the design. Due to
the high operating frequency of the LTC7819, ceramic
0.005/°C) and R is the effective driver resistance at the
DR
MOSFET’s Miller threshold voltage (R ≈ 2Ω). V
is
the typical MOSFET minimum threshold voltage.THMIN
DR
2
Both MOSFETs have I R losses while the main N-channel
equations include an additional term for transition losses,
which are highest at high input voltages. For V < 20V
IN
the high current efficiency generally improves with larger
MOSFETs, while for V > 20V the transition losses rap-
IN
capacitors can also be used for C . Always consult the
IN
idly increase to the point that the use of a higher R
DS(ON)
manufacturer if there is any question.
device with lower C
actually provides higher effi-
MILLER
The benefit of the LTC7819 3-phase operation can be
calculated by using this equation for the higher power
controller and then calculating the loss that would have
resulted if all three controller channels switched on at the
same time. The total RMS power lost is lower when all
three controllers are operating due to the reduced overlap
of current pulses required through the input capacitor’s
ESR. This is why the input capacitor’s requirement cal-
culated above for the worst-case controller is adequate
for the triple controller design. Also, the input protection
fuse resistance, battery resistance, and PC board trace
resistance losses are also reduced due to the reduced
peak currents in a 3-phase system. The overall benefit of
a multiphase design will only be fully realized when the
source impedance of the power supply/battery is included
in the efficiency testing.
ciency. The synchronous MOSFET losses are greatest at
high input voltage when the top switch duty factor is low
or during a short-circuit when the synchronous switch is
on close to 100% of the period.
C and C
IN
Selection
OUT
The selection of C is simplified by the 3-phase archi-
IN
tecture and its impact on the worst-case RMS current
drawn through the input network (battery/fuse/capacitor).
It can be shown that the worst-case capacitor RMS cur-
rent occurs when only one controller is operating. The
controller with the highest V
• I
product needs to
OUT OUT
be used in the equation below to determine the maximum
RMS capacitor current requirement.
Increasing the output current drawn from the other con-
troller will actually decrease the input RMS ripple current
from its maximum value. The out-of-phase technique typi-
cally reduces the input capacitor’s RMS ripple current by
The drains of the top MOSFETs should be placed within 1cm
of each other and share a common C (s). Separating the
IN
drains and C may produce undesirable resonances at V .
IN
IN
Rev. 0
21
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LTC7819
APPLICATIONS INFORMATION
Channel 1 can be programmed to a fixed 5V or 3.3V out-
put through control of the VPRG1 pin, which optionally
A small (0.1μF to 1μF) bypass capacitor between the
chip V pin and ground, placed close to the LTC7819, is
IN
connects an internal divider to the V pin. Tying VPRG1
also suggested. An optional 1Ω to 10Ω resistor placed
between CIN and the VIN pin provides further isolation
from a noisy input supply.
FB1
to INTV or GND programs V
to 5V or 3.3V, respec-
to adjustable output
CC
OUT1
OUT1
tively. Floating VPRG1 sets V
mode using external resistors. When channel 1 is con-
figured for a fixed output voltage setting, directly connect
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
V
to the output V
.
FB1
OUT1
For applications with multiple output voltage levels, select
output ripple (ΔV ) is approximated by:
OUT
channel 1 to be the lowest output voltage that is greater
–
⎛
⎞
1
than 3.2V. When the SENSE1 pin (connected to V
)
OUT1
ΔV
≈ ΔI ESR +
⎜
L
⎟
OUT
is above 3.2V, it biases some internal circuitry instead of
V , thereby increasing light load Burst Mode efficiency.
8fC
⎝
⎠
OUT
IN
Similarly, connect EXTV to the lowest output voltage that
CC
where f is the operating frequency, C
is the output
OUT
is greater than the 4.8V maximum EXTV rising switch-
CC
capacitance and ΔI is the ripple current in the inductor.
The output ripple iLs highest at maximum input voltage
over threshold. EXTVCC then supplies the high current gate
drivers and relieves additional quiescent current from V ,
IN
since ΔI increases with input voltage.
L
further reducing the V pin current to ≈1μA in sleep.
IN
Setting the Output Voltage
RUN Pins and Undervoltage Lockout
The LTC7819 output voltages are each set by an external
feedback resistor divider carefully placed across the out-
put, as shown in Figure 4. The regulated output voltage
is determined by:
The three channels of the LTC7819 are enabled using the
RUN1, RUN2, and RUN3 pins. The RUN pins have a ris-
ing threshold of 1.2V with 100mV of hysteresis. Pulling
a RUN pin below 1.1V shuts down the main control loop
and resets the soft-start for that channel. Pulling all three
RUN pins below 0.7V disables the controllers and most
⎛
R ⎞
B
V
= 0.8V 1+
⎜
⎟
OUT
R
⎝
⎠
A
internal circuits, including the INTV LDOs. In this state,
CC
the LTC7819 draws only ≈1.5μA of quiescent current.
Place resistors R and R very close to the V pin to
A
B
FB
The RUN pins are high impedance and must be externally
pulled up/down or driven directly by logic. Each RUN pin
can tolerate up to 40V (absolute maximum), so it can be
minimize PCB trace length and noise on the sensitive V
FB
node. Great care should be taken to route the V trace
FB
away from noise sources, such as the inductor or the
conveniently tied to V in always-on applications where
IN
V
OUT
one or more controllers are enabled continuously and
never shut down. Do not float the RUN pins.
R
B
R
A
C
FF
1/3 LTC7819
The RUN pins can also be configured as precise under-
voltage lockouts (UVLOs) on the input supply with a resis-
V
FB
tor divider from V to ground, as shown in Figure 5.
IN
V
IN
7819 F04
1/3 LTC7819
RUN
R1
Figure 4. Setting Output Voltage
R2
SW trace. To improve frequency response, a feedforward
7819 F05
capacitor (C ) may be used.
FF
Figure 5. Using the RUN Pins As a UVLD
Rev. 0
22
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LTC7819
APPLICATIONS INFORMATION
The V UVLO thresholds can be computed as:
IN
V
R
R
+R
TRACKA TRACKB
X
A
=
•
V
R
R +R
A B
⎛
R ⎞
OUT
TRACKA
1
UVLO RISING = 1.2V 1+
⎜
⎟
R
⎝
⎛
⎠
2
Set R
= R and R
= V during start-up).
= R for coincident track-
TRACKB B
TRACKA
ing (V
A
R ⎞
1
OUT
X
UVLO FALLING = 1.1V 1+
⎜
⎟
R
⎝
⎠
2
The current that flows through the R1-R2 divider directly
adds to the shutdown, sleep, and active current of the
LTC7819, and care should be taken to minimize the impact
of this current on the overall efficiency of the application
circuit. Resistor values in the MΩ range may be required
to keep the impact on quiescent shutdown and sleep cur-
rents low.
V
V
X(MASTER)
OUT(SLAVE)
7819 F06a
TIME
Soft-Start and Tracking (TRACK/SS Pins)
Figure 6a. Coincident Tracking
The start-up of each V
is controlled by the voltage on
OUT
the TRACK/SS pin (TRACK/SS1 for channel 1, TRACK/
SS2 for channel 2, TRACK/SS3 for channel 3). When the
voltage on the TRACK/SS pin is less than the internal 0.8V
V
V
X(MASTER)
reference, the LTC7819 regulates the V pin voltage to
FB
OUT(SLAVE)
the voltage on the TRACK/SS pin instead of the internal
reference. The TRACK/SS pin can be used to program
an external soft-start function or to allow V
another supply during start-up.
to track
OUT
7819 F06b
TIME
Soft-start is enabled by simply connecting a capacitor
from the TRACK/SS pin to ground. An internal 12.5μA
current source charges the capacitor, providing a linear
ramping voltage at the TRACK/SS pin. The LTC7819 will
Figure 6b. Ratiometric Tracking
Figure 6. Two Different Modes of Output Voltage Tracking
regulate its feedback voltage (and hence V ) accord-
OUT
V
OUT
ing to the voltage on the TRACK/SS pin, allowing V
OUT
to rise smoothly from 0V to its final regulated value. For
a desired soft-start time, t , select a soft-start capacitor
R
B
A
SS
V
FB
C
= t • 15μF/sec.
SS
SS
R
V
X
Alternatively, the TRACK/SS pins can be used to track two
or more supplies during start-up, as shown qualitatively
in Figure 6a and Figure 6b. To do this, a resistor divider
should be connected from the master supply (V ) to the
TRACK/SS pin of the slave supply (VOUT), as sXhown in
LTC7819
R
R
TRACKB
TRACKA
TRACK/SS
Figure 7. During start-up V
will track V according to
OUT
X
7819 F07
the ratio set by the resistor divider:
Figure 7. Using the TRACK/SS Pin for Tracking
Rev. 0
23
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LTC7819
APPLICATIONS INFORMATION
Single Output Multi-Phase Operation
maximum junction temperature rating for the LTC7819 to
be exceeded. The INTV current, which is dominated by
CC
For high power applications, two or more channels can
be operated in a multi-phase single output configuration.
The channels switch 120° out-of-phase, which reduces
the required output capacitance in addition to the required
input capacitance and power supply induced noise.
Channel 1 is always the master channel in a multi-phase
application. Channels 2 or 3 are designated as slave chan-
the gate charge current, may be supplied by either the V
IN
LDO or the EXTVCC LDO. When the voltage on the EXTVCC
pin is less than 4.8V, the V LDO is enabled. Power dissi-
IN
pation for the IC in this case is equal to V • IINTV . The
IN
CC
gate charge current is dependent on operating frequency
as discussed in the Efficiency Considerations section. The
junction temperature can be estimated by using the equa-
tions given in Note 2 of the Electrical Characteristics. For
nels that follow channel 1 if their respective V pins are
FB
tied to INTV .
CC
example, the LTC7819 INTV current is limited to less
CC
To configure for single output 3-phase operation, tie both
VFB2 and VFB3 to INTVCC, ITH2 and ITH3 to ground, and
RUN2 and RUN3 to RUN1. The RUN1, VFB1, ITH1, and
TRACK/SS1 pins then control all three channels, but each
channel uses its own ICMP and IR comparators to moni-
tor their respective inductor currents. Figure 10 is a typical
application configured for single output 3-phase operation.
than 46mA from a 36V supply when not using the EXTV
CC
supply at a 70°C ambient temperature:
T = 70°C + (46mA)(36V)(33°C/W) = 125°C
J
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked
while operating in continuous conduction mode (MODE
= INTV ) at maximum V .
CC
IN
Similarly, to configure two channels for single output
2-phase with the third channel as a separate independent
When the voltage applied to EXTVCC rises above 4.8V, the
VIN LDO is turned off and the EXTVCC LDO is enabled. The
output, tie either V
or V to INTV . That channel
FB3 CC
FB2
will then follow channel 1 as described above, and should
have its ITH pin tied to ground and its RUN pin tied to
RUN1. The third channel can be used as an independent
single-phase output.
EXTV LDO remains on as long as the voltage applied to
CC
EXTV remains above approximately 4.5V. The EXTV
CC
CC
LDO attempts to regulate the INTV voltage to 5.1V, so
CC
while EXTV is less than 5.1V, the LDO is in dropout
CC
and the INTVCC voltage is approximately equal to EXTVCC.
When EXTVCC is greater than 5.1V (up to an absolute
maximum of 30V), INTVCC is regulated to 5.1V. Using
INTV Regulators
CC
The LTC7819 features two separate internal low dropout
the EXTV LDO allows the MOSFET driver and control
CC
linear regulators (LDOs) that supply power at the INTV
CC
power to be derived from one of the LTC7819’s switch-
pin from either the V pin or the EXTV pin depending
IN
CC
ing regulator outputs (4.8V ≤ V
≤ 30V) during normal
OUT
on the EXTV pin voltage. INTV powers the MOSFET
gate driversCaCnd most of the intCeCrnal circuitry. The V
operation and from the V LDO when the output is out
IN
IN
of regulation (e.g., start-up, short-circuit). If more current
LDO and the EXTV LDO each regulate INTV to 5.1V
CC
CC
is required through the EXTV LDO than is specified, an
CC
and can provide a peak current of at least 100mA.
external Schottky diode can be added between the EXTV
CC
The INTVCC pin must be bypassed to ground with a
minimum of 4.7μF ceramic capacitor, placed as close as
possible to the pin. An additional 1μF ceramic capacitor
and INTV pins. In this case, do not apply more than 6V
CC
to the EXTV pin.
CC
Significant efficiency and thermal gains can be realized
placed directly adjacent to the INTV and GND pins is
CC
by powering INTV from an output, since the V cur-
CC
IN
also highly recommended to supply the high frequency
rent resulting from the driver and control currents will be
scaled by a factor of VOUT/(VIN • Efficiency). For 5V to 30V
transient currents required by the MOSFET gate drivers.
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the
regulator outputs, this means connecting the EXTV pin
CC
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24
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LTC7819
APPLICATIONS INFORMATION
directly to V . Tying the EXTV pin to an 8.5V supply
reduces the junction temperature in the previous example
from 125°C to:
VIN and the BOOST pin follows. With the topside MOSFET
OUT
CC
on, the boost voltage is above the input supply: V
=
BOOST
V + V
. The value of the boost capacitor C needs
IN
INTVCC
B
to be 100 times that of the total input capacitance of the
T = 70°C + (46mA)(8.5V)(33°C/W) = 83°C
J
topside MOSFET(s). For a typical application, a value of
However, for 3.3V and other low voltage outputs, addi-
C = 0.1μF is generally sufficient.
B
tional circuitry is required to derive INTV power from
CC
The external diode DB can be a Schottky diode or sili-
con diode, but in either case it should have low leakage
and fast recovery. The reverse breakdown of the diode
the output.
The following list summarizes the four possible connec-
tions for EXTV :
must be greater than V . Pay close attention to the
IN(MAX)
CC
reverse leakage at high temperatures where it generally
increases substantially.
1. EXTV grounded. This will cause INTV to be pow-
CC
CC
ered from the internal VIN LDO resulting in an efficiency
penalty of up to 10% or more at high input voltages.
A leaky diode not only increases the quiescent current
of the regulator, but it can create current path from the
BOOST pin to INTVCC. This will cause INTVCC to rise if
the diode leakage exceeds the current consumption on
2. EXTV connected directly to one of the regulator out-
CC
puts. This is the normal connection for an application
with an output in the range of 5V to 30V and provides
the highest efficiency. If more than one output is in the
INTV , which is primarily a concern in Burst Mode opera-
CC
tion where the load on INTV can be very small. There
CC
5V to 30V range, connect EXTV to the lesser output
CC
is an internal voltage clamp on INTV that prevents the
CC
to maximize efficiency.
INTV voltage from running away, but this clamp should
be reCgCarded as a failsafe only.
3. EXTV connected to an external supply. If an external
CC
supply is available, it may be used to power EXTV
CC
The topside MOSFET driver for the channel 1 includes
an internal charge pump that delivers current to the
bootstrap capacitor from the BOOST1 pin. This charge
current maintains the bias voltage required to keep the
top MOSFET on continuously during dropout conditions.
Curves displaying the available charge pump current
under different operating conditions can be found in the
Typical Performance Characteristics section.
provided that it is compatible with the MOSFET gate
drive requirements. This supply may be higher or lower
than V ; however, a lower EXTV voltage results in
IN
CC
higher efficiency.
4. EXTVCC connected to an output-derived boost or charge
pump. For regulators where all three outputs are below
5V, efficiency gains can still be realized by connect-
ing EXTV to an output-derived voltage that has been
CC
Minimum On-Time Considerations
boosted to greater than 4.8V.
Minimum on-time t
is the smallest time duration
ON(MIN)
Topside MOSFET Driver Supply (C , D )
B
B
that the LTC7819 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the MOSFET. Low duty cycle
applications may approach this minimum on time limit
and care should be taken to ensure that:
External bootstrap capacitors CB connected to the
BOOST pins supply the gate drive voltages for the top-
side MOSFETs. Capacitor C in the Functional Diagram is
B
charged though external diode D from INTV when the
B
CC
SW pin is low.
V
OUT
t
<
ON(MIN)
When one of the topside MOSFETs is to be turned on, the
V • f
OSC
IN
driver places the C voltage across the gate-source of the
B
desired MOSFET. This enhances the MOSFET and turns on
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
the topside switch. The switch node voltage, SW, rises to
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25
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cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase. The
minimum on-time the LTC7819 is approximately 40ns.
However, as the peak sense voltage decreases the mini-
mum on-time gradually increases up to about 60ns. This
is of particular concern in forced continuous applications
with low ripple current at light loads. If the duty cycle
drops below the minimum on-time limit in this situation,
a significant amount of cycle skipping can occur with cor-
respondingly larger current and voltage ripple.
A shorted top MOSFET will result in a high current con-
dition which will open the system fuse. The switching
regulator will regulate properly with a leaky top MOSFET
by altering the duty cycle to accommodate the leakage.
Fault Conditions: Overtemperature Protection
At higher temperatures, or in cases where the internal
power dissipation causes excessive self-heating (such as
a short from INTV to ground) internal overtemperature
shutdown circuitrCyCwill shut down the LTC7819. When
the internal die temperature exceeds 180°C, the INTV
CC
Fault Conditions: Current Limit and Foldback
LDO and gate drivers are disabled. When the die cools
to 160°C, the LTC7819 enables the INTVCC LDO and
resumes operation beginning with a soft-start startup.
Long-term overstress (TJ > 125°C) should be avoided
as it can degrade the performance or shorten the life of
the part.
The LTC7819 includes current foldback to reduce the load
current when the output is shorted to ground. If the output
voltage falls below 50% of its regulation point, then the
maximum sense voltage is progressively lowered from
100% to 40% of its maximum value. Under short-circuit
conditions with very low duty cycles, the LTC7819 will
begin cycle skipping to limit the short circuit current. In
this situation the bottom MOSFET dissipates most of the
power but less than in normal operation. The short-circuit
ripple current is determined by the minimum on-time,
Phase-Locked Loop and Frequency Synchronization
The LTC7819 has an internal phase-locked loop (PLL)
which allows the turn-on of the top MOSFET of control-
ler 1 to be synchronized to the rising edge of an external
clock signal applied to the PLLIN/SPREAD pin. The turn
on of controller 2’s and controller 3’s top MOSFETs are
then 120º and 240º out of phase with the external clock,
repectively.
t
≈ 40ns, the input voltage and inductor value:
ON(MIN)
ΔI
L(SC)
= t
• V /L
ON(MIN) IN
The resulting average short-circuit current is:
= 40% • I − ΔI /2
I
SC
LIM(MAX)
L(SC)
Rapid phase-locking can be achieved by using the FREQ
pin to set a free-running frequency near the desired
synchronization frequency. Before synchronization,
the PLL is prebiased to the frequency set by the FREQ
pin. Consequently, the PLL only needs to make minor
adjustments to achieve phase-lock and synchronization.
Although it is not required that the free-running frequency
be near the external clock frequency, doing so will pre-
vent the oscillator from passing through a large range of
frequencies as the PLL locks.
Fault Conditions: Overvoltage Protection (Crowbar)
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
much higher than nominal levels. The crowbar causes
huge currents to flow that blow the fuse to protect against
a shorted top MOSFET if the short occurs while the con-
troller is operating.
If an output voltage rises 10% above the set regulation
point, the top MOSFET is turned off and the bottom MOSFET
is turned on until the overvoltage condition is cleared. The
bottom MOSFET remains on continuously for as long as
the overvoltage condition persists; if VOUT returns to a safe
level, normal operation automatically resumes.
When synchronized to an external clock, the LTC7819
operates in pulse-skipping mode if it is selected by the
MODE pin, or in forced continuous mode otherwise. The
LTC7819 is guaranteed to synchronize to an external
clock applied to the PLLIN/SPREAD pin that swings up
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LTC7819
APPLICATIONS INFORMATION
to at least 2.2V and down to 0.5V or less. Note that the
LTC7819 can only be synchronized to an external clock
frequency within the range of 100kHz to 3MHz.
loss from 10% or more (if the driver was powered
directly from V ) to only a few percent.
IN
3. I2R losses are predicted from the DC resistances of the
input fuse (if used), MOSFET, inductor, current sense
resistor, and input and output capacitor ESR. In con-
tinuous mode the average output current flows through
L and RSENSE, but is chopped between the top and
bottom MOSFETs. If the two MOSFETs have approxi-
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
mately the same R
, then the resistance of one
DS(ON)
MOSFET can simply be summed with the resistances
2
of L, R
and ESR to obtain I R losses.
SENSE
%Efficiency = 100% – (L1 + L2 + L3 + ...)
For example, if each R
SENSE
= 30mΩ, R = 50mΩ,
L
DS(ON)
R
= 10mΩ and ESR = 40mΩ (sum of both input
where L1, L2, etc. are the individual losses as a percent-
age of input power.
and output capacitance losses), then the total resis-
tance is 130mΩ. This results in losses ranging from
3% to 13% as the output current increases from 1A to
5A for a 5V output, or a 4% to 20% loss for a 3.3V out-
put. This percentage loss varies as the inverse square
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC7819 circuits: 1) IC V current, 2) INTV
IN
CC
2
regulator current, 3) I R losses, 4) Topside MOSFET tran-
sition losses.
of V
for the same external components and output
OUT
power level. The combined effects of increasingly lower
output voltages and higher currents required by high
performance digital systems is not doubling but qua-
drupling the importance of loss terms in the switching
regulator system!
1. The VIN current is the DC supply current given in
the Electrical Characteristics table, which excludes
MOSFET driver and control currents. Other than at very
light loads in burst mode, V current typically results
IN
in a small (<0.1%) loss.
4. Transition losses apply only to the top MOSFETs and
become significant only when operating at higher input
voltages (typically 15V or greater). Transition losses
can be estimated from the equation for the main switch
power dissipation in the Power MOSFET Selection
section.
2. INTV current is the sum of the MOSFET driver and
CC
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge, dQ, moves
from INTVCC to ground. The resulting dQ/dt is a current
Other hidden losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these system level losses during the
design phase. The internal battery and fuse resistance
losses can be minimized by making sure that CIN has
adequate charge storage and very low ESR at the switch-
ing frequency. A 25W supply will typically require a mini-
mum of 20μF to 40μF of capacitance having a maximum
of 20mΩ to 50mΩ of ESR. The LTC7819 3-phase archi-
tecture typically halves this input capacitance requirement
over competing solutions. Other losses including inductor
out of INTV that is typically much larger than the
CC
control circuit current. In continuous mode, I
GATECHG
= f (Q Q ), where Q and Q are the gate charges
SW T +
B
T
B
of the top and bottom MOSFETs.
Supplying INTVCC from an output-derived source
through EXTVCC will scale the VIN current required
for the driver and control circuits by a factor of V
/
OUT
(V • Efficiency). For example, in a 20V to 5V applica-
IN
tion, 10mA of INTV current results in approximately
CC
2.5mA of VIN current. This reduces the mid-current
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LTC7819
APPLICATIONS INFORMATION
core losses generally account for less than 2% total addi-
tional loss.
Placing a power MOSFET directly across the output
capacitor and driving the gate with an appropriate signal
generator is a practical way to produce a realistic load
step condition. The initial output voltage step resulting
from the step change in output current may not be within
the bandwidth of the feedback loop, so this signal can-
not be used to determine phase margin. This is why it is
better to look at the ITH pin signal which is in the feed-
back loop and is the filtered and compensated control
loop response. The gain of the loop will be increased
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
shifts by an
OUT
amount equal to ΔILOAD • (ESR), where ESR is the effective
series resistance of C . ΔI
also begins to charge or
OUT
generating tLhOeAfDeedback error signal that
by increasing R and the bandwidth of the loop will be
C
discharge C
OUT
increased by decreasing CC. If RC is increased by the same
factor that C is decreased, the zero frequency will be kept
the same, thCereby keeping the phase shift the same in the
most critical frequency range of the feedback loop. The
output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance.
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recovery
time V
can be monitored for excessive overshoot or
OUT
ringing, which would indicate a stability problem.
OPTI-LOOP compensation allows the transient response
to be optimized over a wide range of output capaci-
tance and ESR values. The availability of the ITH pin not
only allows optimization of control loop behavior, but it
also provides a DC coupled and AC filtered closed loop
response test point. The DC step, rise time and settling
at this test point truly reflects the closed loop response.
Assuming a predominantly second order system, phase
margin and/or damping factor can be estimated using the
percentage of overshoot seen at this pin. The bandwidth
can also be estimated by examining the rise time at the
pin. The ITH external components shown in the Typical
Applications circuits provide an adequate starting point
for most applications.
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C , causing a rapid drop in V . No regulator can
OUT
alter itOsUdTelivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C
to C
is greater than 1:50, the switch rise time
LOAD
OUT
should be controlled so that the load rise time is limited
to approximately C • 25μs/μF. Thus a 10μF capacitor
LOAD
would require a 250μs rise time, limiting the charging
current to about 200mA.
The ITH series R -C filter sets the dominant pole-zero
C
C
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their initial values) to optimize tran-
sient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1μs to 10μs will
produce output voltage and ITH pin waveforms that will
give a sense of the overall loop stability without breaking
the feedback loop.
Design Example
As a design example, assume VIN(NOMINAL) = 12V, VIN(MAX)
= 22V, V
= 3.3V, I
= 20A, and f = 1MHz.
OUT
OUT SW
1. Set the operating frequency. The frequency is not one of
the internal preset values, so a resistor from the FREQ
pin to GND is required, with a value of:
37MHz
R
(in kΩ)=
= 37kΩ
FREQ
1MHz
2. Determine the inductor value. Initially select a value
based on an inductor ripple current of 30%. The
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inductor value can then be calculated from the follow-
ing equation:
For this low inductor value and high current applica-
tion, an RC filter into the sense pins should be used to
compensate for the parasitic inductance (ESL) of the
⎛
⎞
VOUT
fSW ΔI
VOUT
sense resistor. Assuming an R
geometry of 1225
⎜
⎟
SENSE
L=
1–
=0.4µH
⎜
⎟
V
(
)
with a parasitic inductance of 0.2nH, the RC filter time
L
IN(NOM)
⎝
⎠
constant should be RC = ESL/R = 0.2nH / 2mΩ
SENSE
The highest value of ripple current occurs at the maxi-
= 100ns, which may be implemented with 100Ω resis-
tor in series with the SENSE+ pin and 1nF capacitor
mum input voltage. In this case the ripple at V = 22V
IN
+
−
is 35%
between SENSE and SENSE .
3. Verify that the minimum on-time of 40ns is not violated.
5. Select the feedback resistors. If very light load effi-
ciency is required, high value feedback resistors may
be used to minimize the current due to the feedback
divider. However, in most applications a feedback
divider current in the range of 10μA to 100μA or more
is acceptable. For a 50μA feedback divider current,
The minimum on-time occurs at V
:
IN(MAX)
V
OUT
t
=
= 150ns
ON(MIN)
V
(f
)
IN(MAX)
SW
This is more than sufficient to satisfy the minimum on
time requirement. If the minimum on time is violated,
the LTC7819 skips pulses at high input voltage, result-
ing in lower frequency operation and higher inductor
current ripple than desired. If undesirable, this behavior
can be avoided by decreasing the frequency (with the
inductor value accordingly adjusted) to avoid operation
near the minimum on-time.
R = 0.8V/50μA = 16kΩ. R can then be calculated as
A
B
R = R (3.3V/0.8V – 1) = 50kΩ. Alternatively, if chan-
B
A
nel 1 is configured as this output then the fixed out-
put voltage setting can be used. For a 3.3V output, tie
VPRG1 to ground and directly connect V to V
.
OUT1
FB1
6. Select the MOSFETs. The best way to evaluate MOSFET
performance in a particular application is to build and
test the circuit on the bench, facilitated by an LTC7819
demo board. However, an educated guess about the
application is helpful to initially select MOSFETs. Since
this is a high current, low voltage application, I2R
losses will likely dominate over transition losses for the
top MOSFET. Therefore, choose a MOSFET with lower
4. Select the RSENSE resistor value. The peak inductor
current is the maximum DC output current plus half of
the inductor ripple current. Or 20A • (1+0.30/2) = 23A
in this case. The RSENSE resistor value can then be cal-
culated based on the minimum value for the maximum
current sense threshold (45mV):
R
as opposed to lower gate charge to minimize
DS(ON)
45mV
23A
the combined loss terms. The bottom MOSFET does
not experience transition losses, and its power loss is
RSENSE
≤
≅2mΩ
2
generally dominated by I R losses. For this reason,
To allow for additional margin, a lower value R
SENSE
the bottom MOSFET is typically chosen to be of lower
may be used (for example, 1.8mΩ); however, be sure
R
and subsequently higher gate charge than the
DS(ON)
top MOSFET.
that the inductor saturation current has sufficient mar-
gin above V
/R
, where the maximum
SENSE(MAX)
SENSE(MAX) SENSE
value of 55mV is used for V
Due to the high current in this application, two
MOSFETs may be needed in parallel to more evenly
.
balance the dissipated power and to lower the RDS(ON)
Be sure to select logic-level threshold MOSFETs, since
the gate drive voltage is limited to 5.1V (INTV ).
.
CC
Rev. 0
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7. Select the input and output capacitors. C is chosen
1. Are the top N-channel MOSFETs located within 1cm of
each other with a common drain connection at CIN?
Decoupling capacitors for the three channels should
be close to each other to avoid a large resonant loop.
IN
for an RMS current rating of at least 10A (I /2, with
OUT
margin) at temperature assuming only this channel
is on. C
is chosen with an ESR of 3mΩ for low
OUT
output ripple. Multiple capacitors connected in parallel
may be required to reduce the ESR to this level. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due
to ESR is approximately:
2. Are the signal and power grounds kept separate?
The combined IC ground pin and the ground return
of C
must return to the combined C
(–) ter-
INTVCC
OUT
minals. The area of the “hot loop” formed by the top
N-channel MOSFET, bottom N-channel MOSFET and the
high-frequency (ceramic) input capacitors, as shown
in Figure 8, should be minimized with short leads, pla-
nar connections, and multiple paralleled vias where
needed. The output capacitor (–) terminals should be
connected as close as possible to the (–) terminals of
the input capacitor.
V
= ESR • ΔI = 3mΩ • 6A = 18mV
L P-P
ORIPPLE
On the 3.3V output, this is equal to 0.55% of peak to
peak voltage ripple.
8. Determine the bias supply components. Since the regu-
lated output is not greater than the EXTV switchover
threshold (4.8V), it cannot be used toCbCias INTVCC.
However, if another supply is available, for example
if the other channel is regulating to 5V, connect that
3. Do the LTC7819 V pins’ resistive dividers connect to
FB
the (+) terminals of C ? The resistive divider must
OUT
be connected between the (+) terminal of COUT and
supply to EXTV to improve the efficiency.
CC
signal ground. Place the divider close to the V pin to
minimize noise coupling into the sensitive VFB node.
For a 6.5ms soft-start, select a 0.1μF capacitor for the
TRACK/SS pin. As a first pass estimate for the bias
components, select CINTVCC = 4.7μF, boost supply
FB
The feedback resistor connections should not be along
the high current input feeds from the input capacitor(s).
capacitor C = 0.1μF and low forward drop boost sup-
B
4. Are the SENSE– and SENSE+ leads routed together with
minimum PC trace spacing? Route these traces away
from the high frequency switching nodes, on an inner
ply diode CMDSH-4E from Central Semiconductor.
9. Determine and set application-specific parameters.
Set the MODE pin based on the trade-off of light load
efficiency and constant frequency operation. Set the
PLLIN/SPREAD pin based on whether a fixed, spread
spectrum, or phase-locked frequency is desired. The
RUN pin can be used to control the minimum input
voltage for regulator operation or can be tied to VIN
for always-on operation. Use ITH compensation com-
ponents from the typical applications as a first guess,
check the transient response for stability, and modify
as necessary.
+
layer if possible. The filter capacitor between SENSE
–
and SENSE should be as close as possible to the IC.
Ensure accurate current sensing with Kelvin connec-
tions at the sense resistor.
5. Is the INTV decoupling capacitor connected close
CC
to the IC, between the INTV and the power ground
CC
plane? This capacitor carries the MOSFET drivers’
current peaks. An additional 1μF ceramic capacitor
placed immediately next to the INTV and GND pins
CC
can help improve noise performance substantially. The
boost diodes should have separate routes directly to
PC Board Layout Checklist
the INTV capacitor near the IC, not shared with any
CC
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. Figure 8 illustrates the current waveforms present
in the various branches of the synchronous regulators
operating in the continuous mode. Check the following
in your layout:
signal connections to INTV .
CC
6. Keep the switching nodes (SW1, SW2, SW3), top gate
nodes (TG1, TG2, TG3), and boost nodes (BOOST1,
BOOST2, BOOST3) away from sensitive small-signal
nodes, especially from the other channels’ voltage and
Rev. 0
30
For more information www.analog.com
LTC7819
APPLICATIONS INFORMATION
current sensing feedback pins. All of these nodes have
very large and fast-moving signals and therefore should
be kept on the output side of the LTC7819 and occupy
minimum PC trace area. Minimize the inductance of the
TG and BG gate drive traces and their respective return
paths to the controller IC (SW and GND) by using wide
traces and multiple parallel vias.
not required. Only after each controller is checked for
its individual performance should multiple controllers be
turned on at the same time. A particularly difficult region
of operation is when one controller channel is nearing
its current comparator trip point when another channel
is turning on its top MOSFET. This occurs around 33%
and 67% duty cycle on any channel due to the phasing of
the internal clocks and may cause minor duty cycle jitter.
7. Use a modified star ground technique: a low imped-
ance, large copper area central grounding point on the
same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTVCC
decoupling capacitor, the bottom of the voltage feed-
back resistive divider and the GND pin of the IC.
Reduce VIN from its nominal level to verify operation
of the regulator in dropout. Check the operation of the
undervoltage lockout circuit by further lowering VIN while
monitoring the outputs to verify operation. Investigate
whether any problems exist only at higher output cur-
rents or only at higher input voltages. If problems coincide
with high input voltages and low output currents, look for
capacitive coupling between the BOOST, SW, TG, and pos-
sibly BG connections and the sensitive voltage and current
pins. The capacitor placed across the current sensing pins
needs to be placed immediately adjacent to the pins of
the IC. This capacitor helps to minimize the effects of dif-
ferential noise injection due to high frequency capacitive
coupling. If problems are encountered with high current
output loading at lower input voltages, look for inductive
For more detailed layout guidance, see Analog Devices
Application Notes AN136 “PCB Layout Considerations
for Non-Isolated Switching Power Supplies” and AN139
“Power Supply Layout and EMI”.
PC Board Layout Debugging
Start with one controller on at a time. It is helpful to use
a DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output volt-
age as well. Check for proper performance over the oper-
ating voltage and current range expected in the applica-
tion. The frequency of operation should be maintained
over the input voltage range down to dropout and until
the output load drops below the low current operation
coupling between C , the top MOSFET, and the bottom
IN
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
GND pin of the IC.
An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
when the current sensing leads are hooked up backwards.
The output voltage under this improper hookup will still
be maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop
will be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
threshold—typically 25% of the maximum designed cur-
rent level in Burst Mode operation.
The duty cycle percentage should be maintained from
cycle to cycle in a well-designed, low noise PCB imple-
mentation. Variation in the duty cycle at a subharmonic
rate can suggest noise pickup at the current or volt-
age sensing inputs or inadequate loop compensation.
Overcompensation of the loop can be used to tame a
poor PC layout if regulator bandwidth optimization is
the current sensing resistor
—don’t worry, the regulator
will still maintain control of the output voltage.
Rev. 0
31
For more information www.analog.com
LTC7819
APPLICATIONS INFORMATION
SW1
L1
R
SENSE1
V
OUT1
C
OUT1
R
L1
HOT
LOOP
V
IN
R
IN
C
IN
SW2
L2
R
SENSE2
V
OUT2
C
OUT2
R
L2
HOT
LOOP
BOLD LINES INDICATE
HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.
7819 F09
Figure 8. Branch Current Waveforms for Bucks
Rev. 0
32
For more information www.analog.com
LTC7819
TYPICAL APPLICATIONS
V
IN
4.5V TO 38V
10µF
50V
×4
INTV
INTV
CC
CC
V
RUN1 RUN2 RUN3
IN
D1
D2
MTOP1
TG1
BOOST1
TG2
BOOST2
MTOP2
L2
L1
1µH
0.1µF
0.1µF
LTC7819
1.8µH
2mΩ
3mΩ
V
V
OUT1
OUT2
SW1
SW2
3.3V, 10A
5V, 10A
+
MBOT1
100Ω
BG1
BG2
MBOT2
C
+
1nF
OUT1
1nF
100µF
×2
C
OUT2
330μF
6.3V
100µF
×2
330μF
6.3V
+
–
+
–
SENSE1
SENSE2
SENSE1
SENSE2
V
EXTV
FB1
CC
INTV
INTV
CC
CC
105k
TRACK/SS1
TRACK/SS2
TRACK/SS3
V
FB2
INTV
CC
4.7µF
V
20k
IN
0.1µF
D3
0.1µF
0.1µF
TG3
BOOST3
MTOP3
FREQ
L3
0.1µF
0.16µH
V
OUT3
ITH1
SW3
1V, 25A
ITH2
1.5k
ITH3
BG3
MBOT3
+
10.7k
0.1μF
C
100µF
×4
OUT3
PGOOD1
PGOOD2
PGOOD3
PLLIN/SPREAD
VPRG1
MODE
9.3k
470μF
2.5V
6.98k
4.84k
+
–
47pF
SENSE3
47pF
47pF
SENSE3
V
FB3
3.3nF
2.2nF
6.8nF
GND
28k
7819 F09
f
= 380kHz
SW
MTOP1,2,3: BSC059N04LS6
MBOT1,2,3: BSC022N04LS6
D1,2,3: BAS140
COUT1,2: KEMET T520V337M006ATE015
COUT3: KEMET T528Z477M2R5ATE005
L1: COILCRAFT XAL7070-102MEB
L2: COILCRAFT XAL7070-182MEB
L3: COILCRAFT XAL7070-161MEB
Figure 9. High Efficiency Triple Output 3.3V/10A, 5V/10A, 1V/25A Regulator
Rev. 0
33
For more information www.analog.com
LTC7819
TYPICAL APPLICATIONS
INTV
INTV
INTV
CC
V
V
V
IN
D1
TG1
MTOP1
V
V
BOOST1
IN
IN
L1
1µH
RUN1
RUN2
RUN3
4.5V TO 38V
10µF
X5R
50V
×4
0.1µF
2mΩ
C
IN
SW1
100μF
63V
100Ω
1nF
BG1
MBOT1
LTC7819
+
–
SENSE1
SENSE1
CC
IN
TG2
BOOST2
MTOP2
L2
1µH
0.1µF
2mΩ
V
OUT
SW2
5V, 50A
100µF
X5R
6.3V
×3
100Ω
1nF
INTV
INTV
BG2
MBOT2
C
CC
CC
OUT
330µF
6.3V
PLLIN/SPREAD
VPRG1
4.7µF
V
V
+
–
FB2
FB3
SENSE2
SENSE2
CC
IN
D3
TG3
MTOP3
PGOOD1
PGOOD2
PGOOD3
TRACK/SS3
TRACK/SS2
TRACK/SS1
ITH1
BOOST3
L3
0.1µF
1µH
2mΩ
SW3
L1,2,3: COILCRAFT XAL1580-102ME
MTOP1,2,3: INFINEON BSC059N04LS
MBOT1,2,3: INFINEON BSC022N04LS6
D1,2,3: CENTRAL SEMI CMDSH-4E
100Ω
1nF
BG3
MBOT3
FREQ
ITH2
+
–
3.65k
SENSE3
C
C
: SUNCON 63HVPF100M
IN
0.1µF
SENSE3
: KEMET T520D337M006ATE018
ITH3
47pF
OUT
V
FB1
EXTV
CC
MODE
7819 F10
1.5nF
GND
f
= 380kHz
SW
Efficiency vs Load Current
Load Step Transient Response
Efficiency vs Input Voltage
100
90
80
70
60
50
40
30
20
10
0
100
V
= 12V
IN
V
OUT
500mV/DIV
95
90
85
80
75
70
INDUCTOR L1
CURRENT
10A/DIV
Burst Mode
OPERATION
PULSE
SKIPPING
INDUCTOR L2
CURRENT
10A/DIV
FORCED
CONTINUOUS
INDUCTOR L3
CURRENT
10A/DIV
7819 F10c
I
I
I
= 2A
= 5A
= 20A
LOAD
LOAD
LOAD
20µs/DIV
5A to 30A LOAD STEP
V
IN
= 12V
0.001
0.01
0.1
1
10
100
0
5
10 15 20 25 30 35 40
LOAD CURRENT (A)
INPUT VOLTAGE (V)
7819 F10b
7819 F10d
Figure 10. High Efficiency 380kHz 3-Phase 5V/50A Regulator
Rev. 0
34
For more information www.analog.com
LTC7819
PACKAGE DESCRIPTION
UJ Package
40-Lead Plastic QFN (6mm × 6mm)
(Reference LTC DWG # 05-08-ꢀ728 Rev Ø)
0.70 0.05
6.50 0.05
5.ꢀ0 0.05
4.42 0.05
4.50 0.05
(4 SIDES)
4.42 0.05
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.75 0.05
R = 0.ꢀꢀ5
TYP
6.00 0.ꢀ0
(4 SIDES)
R = 0.ꢀ0
TYP
39 40
0.40 0.ꢀ0
PIN ꢀ TOP MARK
(SEE NOTE 6)
ꢀ
2
PIN ꢀ NOTCH
R = 0.45 OR
0.35 × 45°
CHAMFER
4.42 0.ꢀ0
4.50 REF
(4-SIDES)
4.42 0.ꢀ0
(UJ40) QFN REV Ø 0406
0.200 REF
0.25 0.05
0.50 BSC
0.00 – 0.05
NOTE:
BOTTOM VIEW—EXPOSED PAD
ꢀ. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION ON THE TOP AND BOTTOM OF PACKAGE
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
35
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LTC7819
TYPICAL APPLICATION
High Efficiency 2.25MHz 12V/8A and 2-Phase 3.3V/30A Regulator
V
IN
16V TO 38V
INTV
INTV
CC
CC
V
RUN1 RUN2 RUN3
C
IN
INB
C
INA
68µF
10µF
D2
D1
×3
MTOP1
×2
MTOP2
TG2
BOOST2
TG1
BOOST1
L1
L2
0.1µF
0.1µF
0.16µH
0.47µH
4mΩ
2mΩ
V
OUT2
SW2
SW1
LTC7819
12V, 8A
MBOT2
MBOT1
BG2
BG1
100Ω
1nF
50Ω
10µF
X7R
×2
100µF
25V
1nF
+
–
+
SENSE2
SENSE1
220k
–
SENSE2
SENSE1
*
V
OUT1
3.3V, 30A
EXTV
V
FB1
CC
INTV
V
CC
FB2
V
IN
C
15.7k
4.7µF
X7R
×6
OUT1
470µF
4V
D3
INTV
CC
INTV
FB3
FREQ
CC
V
MTOP3
×2
0.1µF
×3
4.7µF
TG3
BOOST3
L3
PGOOD1,2,3
TRACK/SS3
ITH1
0.1µF
0.16µH
*OUTPUT CURRENT CAPABILITY
AT HIGH INPUT VOLTAGES MAY BE
LIMITED BY THE THERMAL
CHARACTERISTICS OF THE
OVERALL SYSTEM AND PRINTED
CIRCUIT BOARD DESIGN
2mΩ
SW3
ITH2
MBOT3
BG3
100Ω
1nF
TRACK/SS1
TRACK/SS2
ITH3
3.57k
2k
+
100pF
47pF
PLLIN/SPREAD
VPRG1
MODE
SENSE3
–
0.1µF
SENSE3
0.1µF
GND
3.3nF
470pF
MTOP1,2,3: INFINEON BSC059N04LS6 L1,L3: COILCRAFT XAL5030-161ME
7819 TA02
MBOT1,3: INFINEON BSC022N04LS6
MBOT2: INFINEON BSC059N04LS6
D1,2,3: CENTRAL SEMI CMDSH-4E
L2: COILCRAFT XEL4030V-471
: KEMET T520D477M004ATE012
C
OUT1
f
= 2.25MHz
SW
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTC3853
LTC7805
LTC7802
LTC7806
LTC7811
LTC7818
LTC7817
LTC7803
LTC7804
LTC3899
LTC3890
Triple Output, Multiphase Synchronous Step-Down
Controller
4.5V ≤ V ≤ 24V, 0.8V ≤ V
≤ 13.5V, PLL Fixed Operating Frequency
IN
OUT
100kHz to 750kHz
40V Low I , Dual, 2-Phase 100% Duty Cycle Synchronous
4.5V ≤ V ≤ 40V, 0.8V ≤ V
≤ 40V, I = 14µA, PLL Fixed Operating
Q
Q
IN
OUT
Step-Down Controller
Frequency 100kHz to 3MHz
40V Low I , Dual, 2-Phase Synchronous Step-Down
4.5V ≤ V ≤ 40V, 0.8V ≤ V
≤ 0.99V , I = 14µA, PLL Fixed Operating
IN Q
Q
IN
OUT
Controller
Frequency 100kHz to 3MHz
40V, Low I , 3MHz, 2-Phase Synchronous Boost Controller 4.5V (Down to 1V after Start-Up) ≤ V ≤ 40V, V
Up to 40V, I = 18µA,
Q
Q
IN
OUT
PLL Fixed Frequency 100kHz to 3MHz, Side-Wettable 4mm × 5mm QFN-28
40V, Low I , 3MHz, Triple Output Buck/Buck/Boost
4.5V ≤ V ≤ 40V, I = 14µA, Boost V Limited by Ext Components, Buck
Q
IN
Q
OUT
Controller
V
s Up to 40V, PLL Fixed Frequency 100kHz to 3MHz
OUT
40V, Low I , 3MHz, Triple Output Buck/Buck/Boost
4.5V ≤ V ≤ 40V, I = 14µA, 100% Duty Cycle Capable Boost, Buck and
Q
IN
OUT
Q
Synchronous Controller with Spread Spectrum
Boost V
Up to 40V, PLL Fixed Frequency 100kHz to 3MHz
40V Low I , 3MHz Triple Output Buck/Buck/Boost
4.5V (Down to 1V after Start-Up) ≤ V ≤ 40V, I = 14µA, Buck V
Range: 0.8V to 40V, Boost V
Q
IN
Q
OUT
Synchronous Controller
Up to 40V
OUT
40V Low I , 3MHz 100% Duty Cycle Synchronous Step-
4.5V ≤ V ≤ 40V, 0.8V ≤ V
≤ 40V, I = 12µA, PLL Fixed Operating
Q
IN
OUT Q
Down Controller
Frequency 100kHz to 3MHz, 3mm × 3mm QFN/MSOP-16
40V Low I 3MHz Synchronous Boost Controller 100% Duty 4.5V (Down to 1V after Start-Up) ≤ V ≤ 40V, V
Up to 40V, I = 14µA,
Q
IN
OUT
Q
Cycle Capable
PLL Fixed Frequency 100kHz to 3MHHz, 3mm × 3mm QFN-16, MSOP-16E
60V Low I , Triple Output, Buck/Buck/Boost Synchronous
4.5V (Down to 2.2V after Start-Up) ≤ V ≤ 60V, I = 28µA, Buck and Boost
Q
IN
Q
Controller PLL Fixed Operating Frequency 50kHz to 900kHz
V
Up to 60V
OUT
60V Low I , Dual 2-Phase Synchronous Step-Down
4.5V ≤ V ≤ 60V, 0.8V ≤ V
≤ 24V, I = 50µA, PLL Fixed Frequency
OUT Q
Q
IN
Controller
50kHz to 900kHz
Rev. 0
10/21
www.analog.com
ANALOG DEVICES, INC. 2021
36
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