LTC7872_技术文档

LTC7872

Quad-Phase, Synchronous

Bidirectional Buck or Boost Controller

FEATURES

DESCRIPTION

The LTC^®7872 is a high performance bidirectional buck or

n

Unique Architecture Allows Dynamic Regulation of

Input Voltage, Output Voltage or Current

boost switching regulator controller that operates in either

buck or boost mode on demand. It regulates in buck mode

n

Operates with External Gate Drivers and MOSFETs

from V

-to-V

and boost mode from V

-to-V

LOW

HIGH

LOW

depending on a control signal, making it ideal for 48V/^H1^I2^GV^H

automotive dual battery systems. An accurate current pro-

gramming loop regulates the maximum current that can

be delivered in either direction. The LTC7872 allows both

batteries to supply energy to the load simultaneously by

driving energy from either battery to the other.

V

Voltages Up to 100V; V

Voltages Up to 60V

HIGH

LOW

Synchronous Rectification: Up to 98% Efficiency

ADI-Proprietary Advanced Current Mode Control

1% Voltage Regulation Accuracy Overtemperature

Accurate, Programmable Inductor Current

Monitoring and Bidirectional Regulation

SPI Compliant Serial Interface

n

Operation Status and Fault Report

Its proprietary constant frequency current mode archi-

tecture enhances the signal-to-noise ratio enabling low

noise operation and provides excellent current match-

ing between phases. Additional features include an SPI-

compliant serial interface, discontinuous or continuous

mode of operation, OV/UV monitors, independent loop

compensation for buck and boost operation, accurate

inductor current monitoring and overcurrent protection.

n

Programmable V

, V

Margining

HIGH LOW

n

Phase-Lockable Frequency: 60kHz to 750kHz

Optional Spread Spectrum Modulation

Multiphase/Multi-ICs Operation Up to 24 Phases

Selectable CCM/DCM/Burst Mode Operation

Thermally Enhanced 48-Lead LQFP Package

AEC-Q100 Qualification in Progress

The LTC7872 is available in a 48-lead 7mm × 7mm

LXE package.

APPLICATIONS

n

Automotive 48V/12V Dual Battery Systems

All registered trademarks and trademarks are the property of their respective owners.

n

Backup Power Systems

TYPICAL APPLICATION

Boost-to-Buck Transition

High Voltage Bidirectional Controller with Programming and Monitoring Functions

V

HIGH

30V TO

70V

ꢀꢁꢂꢃ

2.2µF

×12

VFB

OV

LOW

CC

3.01M 2.2Ω

ꢄꢅꢆꢇꢈꢅ

10k

210k

ꢀ

ꢁꢂꢃ

EXTV

10k

OV

UV

HIGH

499k

ꢄꢀꢅꢆꢇꢀ

+

V

HIGH

33µF

×12

ꢀ

ꢁ

VFB

90.9k

110k

ꢂꢃꢄꢅꢀꢆ

V

HIGH

48.7k

1µF

1mΩ

1.5k

6.8µH

16.9k

12.7k 10k

47pF

V

ꢀ

1^L2^OV^W/120A

ꢁꢂꢃꢁ

PWM1

DRIVER

LTC7060

22µF

×4

ꢄꢀꢅꢆꢂꢀ

1nF

0.1µF

ꢀ

ꢁꢂ

ꢃ00ꢀꢄꢅꢆꢀ

+

LTC7872

100µF

×4

0.1µF

0.33µF

499Ω 499Ω

1.69k

ꢀꢁꢀꢂ ꢃꢄ0ꢅꢆ

+

–

ITH

IMON

SS

SNSA1

SNSD1

SNS1

HIGH

LOW

ꢀ0ꢁꢂꢃꢄꢅꢆ

PINS NOT USED

IN THIS CIRCUIT:

CLKOUT

DRVSET

MODE

(PHASE 2 TO PHASE 3)

SETCUR

DRVCC

V5

V

HIGH

45.3k

ILIM

RUN

51k

100pF

0.1µF

4.7µF

1mΩ

1.5k

6.8µH

16.9k

PWMEN

FAULT

PWM4

DRIVER

LTC7060

PGOOD

37.4k

4.7µF

FREQ

SGND

0.1µF

BUCK BOOST

BUCK

SCLK

SDI

SDO

CSB

1.69k

+

SNSA4

SPI

INTERFACE

NOTE: SDO REQUIRES PULL-UP

SNSD4

–

SNS4

7872 TA01a

Rev. 0

1

Document Feedback

For more information www.analog.com

LTC7872

TABLE OF CONTENTS

Features............................................................................................................................ 1

Applications ....................................................................................................................... 1

Typical Application ............................................................................................................... 1

Description......................................................................................................................... 1

Absolute Maximum Ratings..................................................................................................... 3

Order Information................................................................................................................. 3

Pin Configuration ................................................................................................................. 3

Electrical Characteristics........................................................................................................ 4

Typical Performance Characteristics .......................................................................................... 8

Pin Functions.....................................................................................................................10

Block Diagram....................................................................................................................12

Operation..........................................................................................................................13

Applications Information .......................................................................................................20

Serial Port............................................................................................................................................................. 31

Serial Port Register Details................................................................................................................................... 35

Typical Applications.............................................................................................................46

Package Description ............................................................................................................47

Typical Application ..............................................................................................................48

Related Parts.....................................................................................................................48

Rev. 0

2

For more information www.analog.com

LTC7872

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Note 1)

ꢑꢎꢝ ꢊꢐꢗꢏ

V

..................................................... –0.3V to 100V

HIGH

Current Sense Voltages

+

–

(SNSD , SNSA , SNS Phase 1 to 4) ... –0.3V to 60V

(SNSA – SNS ) ................................. –0.3V to 0.3V

(SNSD – SNS ) ................................. –0.3V to 0.3V

EXTV .................................................... –0.3V to 60V

ꢉꢉ

ꢀ

ꢁ

ꢂꢅ ꢊ

ꢒꢐꢓꢒ

ꢂꢄ ꢔꢘ

CC

ꢊꢋꢌ

ꢐꢑꢒ

ꢍꢎꢏ

ꢉꢓꢔꢕ

ꢒꢐꢓꢒ

ꢊꢄ

DRV ....................................................... –0.3V to 11V

CC

ꢂ

ꢂꢃ ꢕRꢊ

ꢘꢘ

ꢃ

ꢂꢂ ꢉꢓꢔꢕ

RUN, OV

UV

OV

.................... –0.3V to 6V

HIGH,

LOW

ꢐꢑꢒ

ꢊꢋꢌ

ꢄ

ꢂꢁ ꢕRꢊꢉꢗꢑ

ꢂꢀ ꢗꢡꢑꢊ

ꢂ0 ꢉꢘꢍꢞ

ꢁꢈ ꢉꢕꢐ

ꢅ

ꢃꢈ

ꢓꢔꢕ

V5 .............................................................. –0.3V to 6V

SCLK, SDI, SDO, CSB.................................. –0.3V to 6V

PWM1, PWM2, PWM3, PWM4, PWMEN.... –0.3V to V5

ꢘꢘ

ꢆ

ꢐꢖꢎꢔ

ꢉꢗꢑꢘꢙR

ꢇ

ꢈ

ꢁꢇ ꢉꢕꢎ

ꢁꢆ ꢘꢉꢌ

ꢎꢊ

ꢙꢊ

ꢎꢊ

ꢀ0

ꢀꢀ

ꢀꢁ

ꢒꢐꢓꢒ

ꢍꢎꢏ

ꢁꢅ ꢝꢏꢖꢃ

ꢁꢄ FAULT

ITH

, ITH

, VFB

............ –0.3V to V5

HIGH

LOW

HIGH

LOW

FAULT, SETCUR, DRVSET, PGOOD.............. –0.3V to V5

IMON, ILIM, SS, BUCK, MODE.................... –0.3V to V5

FREQ, SYNC, CLKOUT................................. –0.3V to V5

Operating Junction Temperature Range

(Notes 2, 3)....................................... –40°C to 150°C

Storage Temperature Range ................. –65°C to 150°C

ꢍꢡꢗ ꢝꢚꢘꢞꢚꢓꢗ

ꢃꢇꢢꢍꢗꢚꢕ ꢣꢆꢤꢤ × ꢆꢤꢤꢥ ꢝꢍꢚꢉꢑꢐꢘ ꢍꢟꢋꢝ

ꢑ

ꢧ ꢀꢄ0ꢨꢘꢩ θ ꢧ ꢂꢅꢨꢘꢪꢏ

ꢦꢚ

ꢗꢡꢝꢎꢉꢗꢕ ꢝꢚꢕ ꢣꢝꢐꢔ ꢃꢈꢥ ꢐꢉ ꢉꢓꢔꢕꢩ ꢖꢙꢉꢑ ꢌꢗ ꢉꢎꢍꢕꢗRꢗꢕ ꢑꢎ ꢝꢘꢌ

ꢦꢖꢚꢡ

DRV /EXTV Peak Current

CC

(Guaranteed by Design) ...................................150mA

ORDER INFORMATION

LEAD FREE FINISH

PART MARKING*

PACKAGE DESCRIPTION*

TEMPERATURE RANGE

–40°C to 125°C

LTC7872ELXE#PBF

LTC7872 LXE

48-Lead (7mm × 7mm) Plastic LXE

AUTOMOTIVE PRODUCTS**

LTC7872ILXE#WPBF

LTC7872JLXE#WPBF

LTC7872HLXE#WPBF

LTC7872 LXE

48-Lead (7mm × 7mm) Plastic LXE

–40°C to 125°C

–40°C to 150°C

Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

This product is available in 160-piece trays.

**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These

models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your

local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for

these models.

Rev. 0

3

For more information www.analog.com

LTC7872

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C, V_HIGH= 48V, V_RUN= 5V unless otherwise noted. (Note 2)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Main Control Loops

V

Supply Voltage Range

Regulated Feedback Voltage

EA Feedback Current

6

100

60

V

HIGH

LOW

HIGH

LOW

HIGH

V

> 6V

1.2

LOW

HIGH

l

(Note 4); ITH

(Note 4)

Voltage = 1.5V

Voltage = 0.5V

1.188

1.200

–10

1.212

–40

V

LOW

V

HIGH

nA

%

EA Feedback Current

(Note 4)

–10

–40

Reference Voltage Line Regulation

(Note 4); V

= 7V to 80V

0.02

0.2

HIGH

V

/V

Voltage Load Regulation Measured in Servo Loop, ∆ITH Voltage = 1.0V to 1.5V

Measured in Servo Loop, ∆ITH Voltage = 1.0V to 0.5V

0.01

–0.01

0.2

–0.2

%

HIGH LOW

g

Buck Mode Transconductance

Amplifier g

(Note 4) ITH

(Note 5)

= 1.5V, Sink/Source 5µA

2

1

mmho

m–buck

LOW

m–buck

Boost Mode Transconductance

Amplifier g

= 0.5V, Sink/Source 5µA

mmho

m–boost

HIGH

m–boost

I

V

DC Supply Current

HIGH

9

30

20

15

mA

µA

Q

Shutdown Mode, V

Supply Current

V

= 0V; V

= 48V

= 12V

HIGH

LOW

RUN

HIGH

LOW

= 0V; V

UVLO

DRV Undervoltage Lockout

DRV Ramping Down, V

= V

V5

= Float

= 0V

6.9

4.8

3.9

7.2

5.0

4.1

7.5

5.2

4.3

V

CC

DRVSET

Threshold

DRV Ramping Down, V

CC

DRV Ramping Down, V

CC

DRV Undervoltage Hysteresis

V

= Float, V

= 0V

0.8

0.5

V

CC

DRVSET

V5

V5 Undervoltage Lockout Threshold

V5 Undervoltage Hysteresis

V5 Ramping Down, V

= Float, V

= 0V

4.2

3.9

4.4

4.1

4.6

4.3

V

DRVSET

V5

V

= Float, V

= 0V

0.2

0.5

V

DRVSET

V5

RUN Pin On Threshold

V

Rising

1.1

1.22

80

2

1.35

1.2

V

mV

µA

RUN

RUN Pin On Hysteresis

RUN Pin Source Current

RUN Pin Hysteresis Current

Soft-Start Charging Current

BUCK Pin Input Threshold

l

V

< 1.1V

0.6

2

RUN

> 1.3V

6

µA

I

= 1.2V

SS

0.8

1.0

µA

SS

V

Rising

Falling

2.2

1.7

V

BUCK

BUCK Pin Pull-Up Resistance

Maximum Duty Cycle

BUCK Pin to V5

200

kΩ

Buck Mode

Boost Mode

96

98

92

%

Current Monitoring and Regulation Functions

+

I

+

SNSA Pins Input Current

0.05

1

µA

mA

kΩ

µA

%

SNSA

SNSD

+

SNSD Pins Input Current

–

SNS Pins Input Current

SNS

ILIM Pin Input Resistance

SETCUR Pin Sourcing Current

IMON Error at Max Current

100

16.0

l

I

MFR_IDAC_SETCUR = 0x00

= Float, R = 3mΩ

15.0

17.0

10

SETCUR

V

ILIM

SENSE

I

Zero Current Voltage

1.240

1.250

1.260

V

MON

Rev. 0

4

For more information www.analog.com

LTC7872

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C, V_HIGH= 48V, V_RUN= 5V unless otherwise noted. (Note 2)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Current Sense Pin Voltage

V

= 0V, 1/4 V

40

20

V/V

ILIM

V5

+

–

(V

– V

) to IMON Gain

= Float, 3/4 V , V

V5 V5

SNSD

SNS

Total DC Sense Signal Gain

DCR Configuration

Configuration

5

4

V/V

R

SENSE

l

V

Maximum Current Sense Threshold

(Buck and Boost Mode)

V

= 0V

6.5

10.0

20.0

30.0

40.0

50.0

13.5

23.0

33.0

44.0

56.0

mV

SENSE(MAX)

ILIM

(DCR

= 1/4 V

17.0

27.0

36.0

44.0

V5

Configuration)

= Float

= 3/4 V

V5

= V

V5

l

V

Maximum Current Sense Threshold

(Buck and Boost Mode)

V

= 0V

8.1

12.5

25.0

37.5

50.0

62.5

16.9

28.8

41.3

55.0

70.0

mV

SENSE(MAX)

SENSE

ILIM

(R

= 1/4 V

= Float

= 3/4 V

21.2

33.7

45.0

55.0

V5

Configuration)

V5

= V

V5

l

V

Overcurrent Fault Threshold,

V

= 0V

31.0

43.0

54.0

65.0

76.0

37.5

50.0

62.5

75.0

87.5

44.0

57.0

71.0

85.0

99.0

mV

OCFT

ILIM

+

–

V

– V

= 1/4 V

= Float

= 3/4 V

SNSD

SNS

V5

= V

V5

l

Negative Overcurrent Fault Threshold,

V

= 0V

–45.0

–58.0

–72.0

–86.0

–100.0

–37.5

–50.0

–62.5

–75.0

–87.5

–30.0

–42.0

–53.0

–64.0

–75.0

mV

NOCFT

ILIM

+

–

V

– V

= 1/4 V

= Float

= 3/4 V

SNSD

SNS

V5

= V

V5

Overcurrent Fault Threshold

V

= 0V

25

31

mV

ILIM

+

–

Hysteresis, |V

– V

|

= 1/4 V , Float, 3/4 V , V

V5 V5 V5

SNSD

SNS

DRV and V5 Linear Regulators

CC

V

DRV Regulation Voltage

12V < V

< 60V, V

= V

V5

= Float

= 0V

9.5

7.6

4.8

10

8

5

10.5

8.4

5.2

V

DRVCC

CC

EXTVCC

DRVSET

DRV Load Regulation

I

= 0mA to 100mA, V = 14V

EXTVCC

1.6

3.0

%

CC

DRVCC

EXTV Switchover Voltage

EXTV Ramping Positive, V

= V

V5

= Float

= 0V

10.7

8.5

6.9

V

CC

DRVSET

EXTV Ramping Positive, V

CC

EXTV Ramping Positive, V

CC

EXTV Hysteresis

12

5.0

0.5

%

V

CC

V5

V5 Regulation Voltage

V5 Load Regulation

6V < V

< 10V

4.8

5.2

1

DRVCC

I

= 0mA to 20mA

%

V5

Current DACs (IDAC)

V

/V

IDAC Accuracy

MFR_IDAC_V

= 0x40 or 0x7F

–1

–64

0

1

%

µA

HIGH LOW

LOW/HIGH

/V

IDAC Program Range

63

31

HIGH LOW

SETCUR IDAC Program Range

LSB

V

/V IDAC LSB

1

µA

HIGH LOW

SETCUR IDAC LSB

Oscillator and Phase-Locked Loop

l

I

FREQ Pin Output Current

Nominal Frequency

19

230

55

20

250

70

21

270

85

µA

kHz

FREQ

V

SYNC

V

SYNC

V

SYNC

= 0V, R

= 51.1k

FREQ

f

Low Fixed Frequency

High Fixed Frequency

= 0V, R

= 27.4k

= 105k

LOW

640

710

780

HIGH

Rev. 0

5

For more information www.analog.com

LTC7872

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C, V_HIGH= 48V, V_RUN= 5V unless otherwise noted. (Note 2)

SYMBOL

PARAMETER

CONDITIONS

MIN

60

TYP

MAX

750

12

UNITS

kHz

l

Synchronizable Frequency

SYNC = External Clock

Spread Spectrum Frequency

Modulation Range

V

= 5V, R

= 51.1k, MFR_SSFM = 0x00

–12

%

SYNC

FREQ

θ – θ

Phase 2 Relative to Phase 1

Phase 3 Relative to Phase 1

Phase 4 Relative to Phase 1

CLKOUT Phase to Phase 1

Clock Output High Voltage

Clock Output Low Voltage

SYNC Pin Input Threshold

180

90

Deg

V

2

1

θ – θ

3

1

θ – θ

4

270

45

θ

– θ

1

CLKOUT

I

= 0.5mA

V5 – 0.2

2

V5

LOAD

= –0.5mA

0.2

1.1

V

SYNC Pin Rising

SYNC Pin Falling

V

SYNC Pin Input Resistance

100

0.1

kΩ

Power Good and FAULT

PGOOD Voltage Low

PGOOD Leakage Current

PGOOD Trip Level, VFB

I

= 2mA

= 5V

0.3

1

V

PGOOD

V

µA

PGOOD

/VFB

VFB

/VFB

Ramping Negative

Ramping Positive

–10

10

%

HIGH

LOW

HIGH

LOW

With Respect to the Regulated Voltage VFB

PGOOD Delay

PGOOD Pin High to Low

40

µs

V

FAULT Voltage Low

FAULT Voltage Leakage Current

FAULT Delay

I

= 2mA

= 5V

0.1

0.3

1

FAULT

V

µA

µs

V

FAULT

FAULT Pin High to Low

120

1.2

5

V

OV Comparator Threshold

OV Comparator Hysteresis

OV Comparator Threshold

OV Comparator Hysteresis

UV Comparator Threshold

UV Comparator Hysteresis

1.15

1.25

LOW

HIGH

V

> 1.2V

< 1.2V

µA

V

OVLOW

OVHIGH

UVHIGH

1.2

5

µA

V

1.2

5

µA

PWM Outputs

l

PWM Output High Voltage

PWM Output Low Voltage

I

= 0.5mA

V5 – 0.5

V

LOAD

= –0.5mA

0.5

5

PWM Output Current in Hi-Z State

µA

DIGITAL I/O: CSB, SCLK, SDI, SDO

V

Digital Input Low Voltage

Digital Input High Voltage

Digital Output Voltage Low

CSB Pin Pull-Up Resistor

SCLK Pin Pull-Down Resistor

SDI Pin Pull-Down Resistor

Pins CSB, SCLK, SDI

Pin SDO, Sinking 1mA

0.5

0.3

V

IL

1.8

IH

OL

V

R

300

kΩ

CSB

SCLK

SDI

Rev. 0

6

For more information www.analog.com

LTC7872

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C, V_HIGH= 48V, V_RUN= 5V unless otherwise noted. (Note 2)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

SPI Interface Timing Characteristics (Refer to Timing Diagram in Figure 9 and 10)

t

f

SCLK High Time

45

40

60

40

20

90

45

5

ns

CKH

CSB Setup Time

CSS

CSB High Time

ns

CSH

CS

SDI to SCLK Setup Time

SDI to SCLK Hold Time

SCLK to SDO Time

SCLK Duty Cycle

ns

CH

ns

DO

50

55

%

C%

Maximum SCLK Frequency

MHz

SCLK(MAX)

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

junction temperature degrades operating lifetimes; operating lifetime

is derated for junction temperatures greater than 125°C. Note that the

maximum ambient temperature consistent with these specifications is

determined by specific operating conditions in conjunction with board

layout, the rated package thermal impedance and other environmental

factors.

Note 2: The LTC7872 is tested under pulsed load conditions such that

T ≈ T . The LTC7872E is guaranteed to meet performance specifications

J

A

from 0°C to 85°C junction temperature. Specifications over the –40°C

to 125°C operating junction temperature range are assured by design,

characterization and correlation with statistical process controls. The

LTC7872I is guaranteed over the –40°C to 125°C operating junction

temperature range. The LTC7872J is guaranteed over the –40°C to 150°C

operating junction temperature range. The LTC7872H is guaranteed

over the full –40°C to 150°C operating junction temperature range. High

Note 3: T is calculated from the ambient temperature T and power

J A

dissipation P according to the following formula:

D

T = T + (P • 36°C/W)

J

A

D

Note 4: The LTC7872 is tested in a feedback loop that servos V

ITHHIGH

and V

to a specified voltage and measures the resultant VFB

, respectively.

,

ITHLOW

HIGH

VFB

LOW

Note 5: Dynamic supply current may be higher due to the loading current

at DRV linear regulator.

CC

Rev. 0

7

For more information www.analog.com

LTC7872

T_A= 25°C, unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

Efficiency Buck Mode

Power Loss Buck Mode

Efficiency Boost Mode

ꢀ0

0

ꢀ00

ꢀꢁ

ꢀ0

ꢀꢁ

ꢀ0

ꢀꢁ

ꢀ0

ꢀꢁ

ꢀ0

ꢀ00

ꢀ

ꢀ ꢁꢂꢃ

ꢀꢁꢂꢀ

ꢀꢁꢂ

ꢀ

ꢀ ꢁꢂꢃ

ꢀꢁ

ꢀ0

ꢀꢁ

ꢀ0

ꢀꢁ

ꢀꢁꢂꢃRꢄ ꢅꢆ ꢇꢁRꢇꢃꢁꢈ

ꢀ0

ꢀ

ꢀ ꢁꢂꢃ

ꢀ

ꢀ ꢁꢂꢃ

ꢀꢁꢂꢀ

ꢀꢁꢂ

ꢀꢁꢂꢀ

ꢀꢁꢂ

ꢀꢁ

ꢀ ꢁꢂꢃ

ꢀꢁꢂꢃRꢄ ꢅꢆ ꢇꢁRꢇꢃꢁꢈ

ꢀ0

ꢀ

ꢀ0

ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ

ꢀ00 ꢀ00

ꢀ

ꢀ0

ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ

ꢀ00 ꢀ00

0.ꢀ

ꢀ

ꢀ0

ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ

ꢀꢁꢀꢂ ꢃ0ꢂ

ꢀꢁꢀꢂ ꢃ0ꢄ

SS Pin Pull-Up Current

vs Temperature

RUN Pin Threshold

Power Loss Boost Mode

vs Temperature

ꢀ0

0

ꢀ.0

ꢀ.ꢁ

0.ꢀ

0

ꢀ.ꢁ

ꢀ.ꢀ

ꢀ.0

0.ꢀ

ꢀ

ꢀ ꢁꢂꢃ

ꢀꢁꢂꢀ

ꢀꢁꢂ

ꢀꢁ

ꢀꢁꢁ

ꢀ

ꢀ ꢁꢂꢃ

ꢀꢁꢂꢃRꢄ ꢅꢆ ꢇꢁRꢇꢃꢁꢈ

0.ꢀ

ꢀ

ꢀ0

ꢀꢁꢂ ꢀꢁ0

ꢀ

ꢀ0 ꢀꢀ ꢀ0 ꢀ0ꢁ ꢀꢁ0 ꢀꢁꢁ

ꢀꢁꢂ ꢀꢁ0

ꢀ

ꢀ0 ꢀꢀ ꢀ0 ꢀ0ꢁ ꢀꢁ0 ꢀꢁꢁ

ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ

ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ

ꢀꢁꢀꢂ ꢃ0ꢄ

Regulated Feedback Voltage

vs Temperature

Oscillator Frequency

vs Temperature

Undervoltage Lockout

Threshold (V5) vs Temperature

ꢀ.ꢁ0ꢂ

ꢀ.ꢁ0ꢁ

ꢀ.ꢁ00

ꢀ.ꢀꢁꢂ

ꢀ.0

ꢀ.ꢁ

ꢀ.ꢀ

ꢀ.ꢁ

ꢀ.0

ꢀ00

ꢀꢁ0

ꢀꢀ0

ꢀ00

ꢀꢁꢂꢃꢄꢅ

ꢀꢁꢂꢃꢄꢅꢃ

Rꢀꢁꢀꢂꢃ

ꢀꢁꢂ ꢀꢁ0

ꢀ

ꢀ0 ꢀꢀ ꢀ0 ꢀ0ꢁ ꢀꢁ0 ꢀꢁꢁ

ꢀꢁꢂ ꢀꢁ0

ꢀ

ꢀ0 ꢀꢀ ꢀ0 ꢀ0ꢁ ꢀꢁ0 ꢀꢁꢁ

ꢀꢁꢂ ꢀꢁ0

ꢀ

ꢀ0 ꢀꢀ ꢀ0 ꢀ0ꢁ ꢀꢁ0 ꢀꢁꢁ

ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ

ꢀꢁꢀꢂ ꢃ0ꢀ

ꢀꢁꢀꢂ ꢃ0ꢄ

ꢀꢁꢀꢂ ꢃ0ꢁ

Rev. 0

8

For more information www.analog.com

LTC7872

T_A= 25°C, unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

FREQ Pin Source Current

vs Temperature

Quiescent Current vs Temperature

Shutdown Current vs Temperature

ꢀꢁ.0

ꢀꢀ.0

ꢀ0.0

ꢀ.0

ꢀ0.0

ꢀꢁ.ꢂ

ꢀꢁ.0

ꢀ0.ꢁ

ꢀ0.0

ꢀꢁ.ꢂ

ꢀꢁ.0

ꢀꢁ.ꢂ

ꢀ

ꢀ ꢁꢂꢃ

ꢀꢁꢂꢀ

ꢀ

ꢀ ꢁꢂꢃ

ꢀꢁꢂꢀ

ꢀ.0

ꢀꢁꢂ ꢀꢁ0

ꢀ

ꢀ0 ꢀꢀ ꢀ0 ꢀ0ꢁ ꢀꢁ0 ꢀꢁꢁ

ꢀꢁꢂ ꢀꢁ0

ꢀ

ꢀ0 ꢀꢀ ꢀ0 ꢀ0ꢁ ꢀꢁ0 ꢀꢁꢁ

ꢀꢁꢂ ꢀꢁ0

ꢀ

ꢀ0 ꢀꢀ ꢀ0 ꢀ0ꢁ ꢀꢁ0 ꢀꢁꢁ

ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ

ꢀꢁꢀꢂ ꢃꢄ0

ꢀꢁꢀꢂ ꢃꢄꢄ

ꢀꢁꢀꢂ ꢃꢄꢂ

Current Sense Threshold

vs ITH Voltage (DCR) as a

Function of ILIM

Maximum Current Sense

SETCUR Pin Source Current

vs Temperature

Threshold vs Feedback Voltage—

BUCK (DCR) as a Function of ILIM

ꢀꢁ.0

ꢀꢁ.ꢂ

ꢀꢁ.ꢁ

ꢀꢁ.ꢂ

ꢀꢁ.0

ꢀꢁ.ꢂ

ꢀꢁ.0

ꢀ0

0

ꢀꢁꢂ

ꢀꢁꢂ ꢃꢄ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂ ꢃꢄ

ꢀꢁ

ꢀꢁꢂ ꢃꢄ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂ ꢃꢄ

ꢀꢁ

ꢀ0

0

ꢀꢁ0

ꢀꢁꢂ ꢀꢁ0

ꢀ

ꢀ0 ꢀꢀ ꢀ0 ꢀ0ꢁ ꢀꢁ0 ꢀꢁꢁ

0

0.ꢀ

ꢀ

ꢀ.ꢁ

ꢀ

0

0.ꢀ

ꢀ.0

ꢀ.ꢁ

ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ

ꢀꢁꢂ ꢃꢄꢅꢁꢆꢇꢈ ꢉꢃꢊ

ꢀꢁꢁꢂꢃꢄꢅꢆ ꢇꢈꢉꢊꢄꢋꢁ ꢌꢇꢍ

ꢀꢁꢀꢂ ꢃꢄꢅ

Current Sense Threshold

vs ITH Voltage—(R_SENSE) as

a Function of ILIM

Maximum Current Sense Threshold

vs Feedback Voltage—BUCK

(R_SENSE) as a Function of ILIM

Overcurrent Fault Threshold

vs Temperature as a Function

of ILIM

ꢀ0

0

ꢀ00

ꢀ0

0

ꢀꢁꢂ

ꢀꢁꢂ ꢃꢄ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂ ꢃꢄ

ꢀꢁ

ꢀꢁꢂ ꢃꢄ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂ ꢃꢄ

ꢀꢁ

ꢀ0

ꢀꢁ0

ꢀꢁꢂ

ꢀꢁꢂ ꢃꢄ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂ ꢃꢄ

ꢀꢁ

0

0.ꢀ

ꢀ

ꢀ.ꢁ

ꢀ

0

0.ꢀ

ꢀ.0

ꢀ.ꢁ

ꢀꢁꢂ ꢀꢁ0

ꢀ

ꢀ0 ꢀꢀ ꢀ0 ꢀ0ꢁ ꢀꢁ0 ꢀꢁꢁ

ꢀꢁꢂ ꢃꢄꢅꢁꢆꢇꢈ ꢉꢃꢊ

ꢀꢁꢁꢂꢃꢄꢅꢆ ꢇꢈꢉꢊꢄꢋꢁ ꢌꢇꢍ

ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ

ꢀꢁꢀꢂ ꢃꢄꢅ

ꢀꢁꢀꢂ ꢃꢄꢀ

ꢀꢁꢀꢂ ꢃꢄꢁ

Rev. 0

9

For more information www.analog.com

LTC7872

PIN FUNCTIONS

SS (Pin 1): Soft-Start Input. The voltage ramp rate at this

pin sets the voltage ramp rate of the regulated voltage. A

capacitor to ground accomplishes soft-start. This pin has

a 1µA pull-up current.

OV

(Pin 12): V

Overvoltage Threshold Set Pin. A

LOW

resistor divider from V

is needed to set this thresh-

old. When the voltage on this pin rises past the 1.2V trip

point, a 5μA current is sourced out of the pin to provide

externally adjustable hysteresis.

SNSA1⁺/SNSA2⁺/SNSA3⁺/SNSA4⁺(Pins 13, 18, 43, 48):

AC Positive Current Sense Comparator Inputs. These

inputs amplify the AC portion of the current signal to the

IC’s current comparator.

VFB

(Pin 2): V

Voltage Sensing Error Amplifier

LOW

Inverting Input.

ITH_HIGH/ITH_LOW(Pins 5 and 3): Current Control Threshold

and Error Amplifier Compensation Point. The current com-

parator’s threshold varies with the ITH control voltage.

SNS1^–/SNS2^–/SNS3^–/SNS4^–(Pins 14, 17, 44, 47):

Negative Current Sense Comparator Inputs. The nega-

tive input of the current comparator is normally connected

SGND (Pins 4, 33, Exposed Pad): Ground. Must be

soldered to PCB ground for rated thermal performance.

Connect this pin closely to negative terminal of V

,

HIGH

to the V

.

LOW

DRV_CC, V5 bypass capacitors. All small signal components

and compensation components should connect here.

SNSD1⁺/SNSD2⁺/SNSD3⁺/SNSD4⁺(Pins 15, 16, 45,

46): DC Positive Current Sense Comparator Inputs. These

inputs amplify the DC portion of the current signal to the

IC’s current comparators and current sense amplifiers.

VFB

(Pin 6): V

Voltage Sensing Error Amplifier

HIGH

Noninverting Input.

V5 (Pin 7): Internal 5V Regulator Output. The control

circuits are powered from this voltage. Bypass this pin

to SGND with a minimum of 4.7µF low ESR tantalum or

ceramic capacitor.

RUN (Pin 19): Enable Control Input. A voltage above

1.22V turns on the IC. There is a 2µA pull-up current on

this pin. Once the RUN pin rises above the 1.22V thresh-

old, the pull-up current increases to 6µA.

IMON (Pin 8): Current Monitor Pin. The voltage on this pin

is directly proportional to the average inductor currents

of all 4 channels. 1.25V on this pin indicates zero average

inductor current per phase.

PWMEN (Pin 20): Enable Pin for External Gate Drivers.

Open drain logic that is pulled to ground when the

LTC7872 shut downs the external gate drivers. When this

pin is low, all the PWM pin outputs are high impedance.

SETCUR (Pin 9): This pin sets the maximum average

inductor current in buck or boost mode. This pin sources

16μA current and it is programmable by the SPI interface.

PWM1, PWM2, PWM3, PWM4 (Pins 21, 23, 24, 26):

(Top) Gate Signal Output. This signal goes to the PWM

or top gate input of the external gate driver or integrated

driver MOSFET. This is a three-state compatible output.

OV

(Pin 10): V

Overvoltage Threshold Set Pin. A

HIGH

resistor divider from V

is needed to set this thresh-

HIGH

PGOOD (Pin 22): Power Good Indictor Output for the

old. When the voltage on this pin rises past the 1.2V trip

point, a 5μA current is sourced out of the pin to provide

externally adjustable hysteresis.

Regulated V

/V

. Open drain logic out that is pulled

HIGH LOW

to ground when the regulated V

/V

exceeds 10%

regulation window, after the i^Hn^It^Ge^Hrna^Ll^O4^W0µS power bad

mask timer expires.

UV

(Pin 11): V

Undervoltage Threshold Set Pin.

HIGH

A resistor divider from V

is needed to set this thresh-

FAULT (Pin 25): Fault Indicator Output. Open-drain output

that pulls to ground during a fault condition.

old. When the voltage on this pin falls below the 1.2V

trip point, a 5μA current is sunk in to the pin to provide

externally adjustable hysteresis.

Rev. 0

10

For more information www.analog.com

LTC7872

PIN FUNCTIONS

CSB, SDO, SDI, SCLK (Pins 27, 28, 29, 30): 4-Wire Serial

Peripheral Interface (SPI). Active low chip select (CSB),

serial clock (SCLK) and serial data in (SDI) are digital

Inputs. Serial data out (SDO) is an open-drain NMOS out-

put pin. SDO requires an external pull-up resistor. Refer

to the Serial Port section for more details.

CLKOUT (Pin 38): Clock Output Pin. Use this pin to syn-

chronize multiple LTC7872 ICs. Signal swing is from V5

to ground.

MODE (Pin 39): Mode Set Pin. Tying this pin to SGND

enables forced continuous mode in buck or boost modes.

Floating this pin results in burst mode in buck mode and

discontinuous mode in boost mode. Tying this pin to V5

enables discontinuous mode in buck or boost modes. The

input impedance of this pin is 90kΩ.

EXTV_CC(Pin 31): External Power Input to an Internal LDO

Connected to DRV . This LDO supplies DRV power,

CC

bypassing the internal LDO powered from V

, when-

HIGH

ever EXTV is higher than its switchover threshold. Do

CC

SYNC (Pin 40): Switching Frequency Synchronization

or Spread Spectrum Set Pin. Applying an external clock

between 60kHz to 750kHz to this pin causes the switch-

ing frequency to synchronize to the clock signal. If SYNC

is low, a resistor from the FREQ pin to SGND sets the

switching frequency. Tying this pin to V5 allows switching

frequency spread spectrum. This pin has a 100kΩ internal

resistor to ground.

not exceed 60V on this pin.

DRVSET (Pin 32): The voltage setting on this pin pro-

grams the DRV output voltage. There are two internal

CC

resistors, 200kΩ and 160kΩ, connecting this pin to the

V5 and SGND, respectively.

DRV (Pin 34): Gate Driver Current Supply LDO Output.

CC

The voltage on this pin can be set to 5V, 8V, or 10V by

the DRVSET pin. Bypass this pin to ground plane with a

minimum of 4.7μF low ESR tantalum or ceramic capacitor.

FREQ (Pin 41): Frequency Set Pin. A resistor between

this pin and SGND sets the switching frequency. This pin

sources 20µA current.

NC (Pin 35): No Connect Pin.

BUCK (Pin 42): The voltage on this pin determines if the

V_HIGH(Pin 36): Main V_HIGHSupply. Bypass this pin to

ground with a capacitor (0.1μF to 1μF).

IC is regulating the V

or V

voltage/current. Float

LOW

HIGH

or tie this pin to V5 for buck mode operation. Ground this

pin for boost mode operation.

ILIM (Pin 37): Current Comparator Sense Voltage Limit

Selection Pin. The input impedance of this pin is 100kΩ.

Rev. 0

11

For more information www.analog.com

LTC7872

Functional Diagram Shows Two Channels Only.

BLOCK DIAGRAM

ꢅ

ꢖꢐꢗꢖ

ꢇꢈꢉꢊ

ꢉꢘꢇ ꢘꢉꢔꢊ ꢘꢏꢐ ꢘꢏꢕ

ꢅ

ꢕꢅ

ꢖꢐꢗꢖ

ꢈꢅ

ꢖꢐꢗꢖ

ꢇꢕꢕꢘꢛꢋꢌꢍ

ꢇꢈꢉꢊꢋꢌꢍ

ꢅ

Rꢌꢝ

ꢌꢞꢛꢅ

ꢉꢉ

ꢅꢚ

ꢘꢑꢐ ꢐꢍꢛꢌRꢝꢙꢉꢌ

ꢅꢝꢇ

ꢔꢕꢒ

ꢖꢐꢗꢖ

ꢐꢏꢙꢉ

ꢘꢌꢛꢉꢈR

ꢅ ꢋꢕꢅ

ꢖꢐꢗꢖ

ꢅ

ꢔꢕꢒ

ꢉꢕꢍꢛRꢕꢔ

ꢔꢕꢗꢐꢉ

ꢅ ꢋꢈꢅ

ꢖꢐꢗꢖ

ꢁ

ꢀ

ꢅ

ꢋꢕꢅ

Rꢌꢝ

ꢔꢕꢒ

ꢅ

ꢖꢐꢗꢖ

ꢕꢅ

ꢔꢕꢒ

ꢓꢕꢏꢌ

ꢅ

ꢔꢕꢒ

ꢀ

ꢁ

ꢑꢒꢓꢂ

ꢔꢕꢗꢐꢉ ꢂ

ꢏRꢐꢅꢌR

ꢅ

Rꢌꢝ

ꢔꢕꢒ

ꢇꢈꢉꢊꢋꢌꢍ

ꢅꢝꢇ

ꢔꢕꢒ

ꢑꢒꢓꢌꢍ

ꢀ

ꢁ

ꢌꢙꢋꢅ

ꢘꢘ

ꢂ.ꢄꢅ

ꢔꢕꢒ

ꢐRꢌꢅꢂꢟꢄ

ꢀ

ꢅꢚ

ꢘꢍꢘꢏꢂ

ꢁ

ꢀ

ꢁ

ꢅꢝꢔꢏ

ꢐꢛꢖ

ꢘꢍꢘꢙꢂ

ꢘꢍꢘꢂ

ꢔꢕꢒ

ꢉꢔꢊ

ꢑꢒꢓꢄ

ꢔꢕꢗꢐꢉ ꢄ

ꢏRꢐꢅꢌR

ꢀ

ꢐꢉꢓꢑꢂꢟꢄ

ꢘꢌꢛꢉꢈR

ꢁ

ꢀ

ꢘꢍꢘꢏꢄ

ꢂ.ꢄꢚꢅ ꢀ ꢘꢌꢛꢉꢈR

ꢂ.ꢄꢚꢅ ꢁ ꢘꢌꢛꢉꢈR

ꢜ

ꢀ

ꢁ

ꢘꢍꢘꢙꢄ

ꢘꢍꢘꢄ

ꢀ

ꢐꢉꢓꢑꢂ

ꢐꢉꢓꢑꢄ

ꢘꢍꢘꢙꢂ

ꢀ

ꢁ

ꢐꢓꢕꢍ

ꢀ

ꢘꢍꢘꢏꢂ

ꢀ

ꢁ

ꢘꢍꢘꢂ

ꢀ

ꢘꢍꢘꢙꢄ

ꢀ

ꢁ

ꢀ

ꢅ

ꢖꢐꢗꢖ

ꢘꢍꢘꢏꢄ

ꢀ

ꢁ

ꢘꢍꢘꢄ

ꢅꢝꢇ

ꢖꢐꢗꢖ

ꢘꢘ

ꢀ

ꢌꢙꢋꢅ

ꢖꢐꢗꢖ

ꢇꢈꢉꢊꢋꢌꢍ

ꢂ.ꢃꢄꢅ

ꢂ.0ꢆꢅ

ꢀ

ꢁ

ꢂ.ꢄꢅ

ꢁ

ꢑꢗꢕꢕꢏ

ꢅꢝꢇ

ꢔꢕꢒ

ꢇꢕꢕꢘꢛꢋꢌꢍ

ꢐꢛꢖ

ꢖꢐꢗꢖ

ꢀ

ꢁ

FAULT

ꢘꢠꢍꢉ

ꢑꢖꢙꢘꢌ

ꢏꢌꢛꢌꢉꢛꢕR

ꢅ

ꢋꢕꢅ

ꢋꢈꢅ

ꢔꢕꢒ

ꢖꢐꢗꢖ

ꢅ

ꢖꢐꢗꢖ

ꢂ00ꢤ

ꢄ0ꢣꢙ

ꢐꢍꢛꢌRꢍꢙꢔ

ꢔꢏꢕ Rꢌꢗ

ꢂꢣꢙ

ꢉꢔꢊ

ꢝRꢌꢡ

ꢉꢔꢊꢕꢈꢛ

ꢌꢞꢛꢅ

ꢉꢉ

ꢑꢔꢔꢢꢕꢘꢉ

ꢚꢅ ꢔꢏꢕ

ꢅꢚ ꢘꢗꢍꢏ

ꢉꢉ

ꢔꢏꢕ Rꢌꢗ

ꢏRꢅꢘꢌꢛ ꢌꢞꢛꢅ

ꢏRꢅ

ꢘꢘ

ꢉꢉ

ꢎꢆꢎꢄ ꢇꢏ

Rev. 0

12

For more information www.analog.com

LTC7872

OPERATION

Main Control Loop

Current Sensing with Low DCR or R

SENSE

The LTC7872 is a bidirectional, constant-frequency, cur-

rent mode buck or boost switching regulator controller

with four channels operating equally out of phase. The

The LTC7872 employs a unique architecture to enhance

the signal-to-noise ratio with low current sense offsets.

This enables it to operate with a small current sense signal

from a very low value inductor DCR to improve power

efficiency, and reduce jitter due to switching noise which

could corrupt the signal. Each channel has two positive

current sense pins, SNSD⁺and SNSA⁺, which share

LTC7872 is capable of delivering power from V

to

HIGH

. When power

, the LTC7872 operates

V

as well as from V

back to V

LOW

to V

HIGH

is delivered from V

HIGH

as a peak-current mode constant-frequency buck regula-

tor; and when power delivery is reversed, it operates as a

valley current mode constant-frequency boost regulator.

Four control loops, two for current and two for voltage,

allow control of voltage or bidirectional current on either

V_HIGHor V_LOW. The LTC7872 uses an ADI proprietary cur-

rent sensing, current mode architecture. During normal

buck mode operation, the top MOSFET is turned on every

cycle when the oscillator sets the RS latch, and turned off

–

the negative current sense pin SNS . These sense pins

acquire signals and process them internally to provide

the response equivalent to a DCR sense signal that has

a 14dB (5 times) signal-to-noise ratio. Accordingly, the

current limit threshold is still a function of the inductor

peak-current and its DCR value and can be accurately set

from 10mV to 50mV in 10mV steps with the ILIM pin.

DRV /EXTV /V5 Power

when the main current comparator, I

, resets the RS

CMP

CC

CMP

latch. The peak inductor current at which I

resets the

Power for the external top and bottom MOSFET drivers

is derived from the DRV pin. The DRV voltage can

RS latch is controlled by the voltage on the ITH pin, which

is the output of the error amplifier, EA. The error amplifier

receives the feedback signal and compares it to the inter-

nal 1.2V reference. When the load current increases, it

causes a slight change in the feedback pin voltage relative

to the 1.2V reference, which in turn causes the ITH voltage

to change until the inductor’s average current equals the

new load current. After the top MOSFET has turned off,

the bottom synchronous MOSFET is turned on until the

beginning of the next cycle.

CC

be set to 5V, 8V, or 10V using the DRVSET pin. When

the EXTV pin is left open or tied to a voltage less than

CC

the switchover voltage programmed by the DRVSET pin,

an internal linear regulator supplies DRV power from

CC

V

. When EXTV is taken above the switchover volt-

HIGH

CC

age, the internal regulator between V

and DRV is

CC

HIGH

turned off, and a second internal regulator is turned on

between EXTV and DRV . Each top MOSFET driver is

biased from a^Cf^Cloating bootstrap capacitor, which nor-

mally recharges during each off cycle through an external

diode when the top MOSFET turns off. If the input volt-

age, V_HIGH, decreases to a voltage close to V_LOW, the

loop may enter dropout and attempt to turn on the top

MOSFET continuously. The dropout detector detects this

and forces the top MOSFET off for about one-twelfth of

the clock period plus 160ns every fifth cycle to allow the

bootstrap capacitor to recharge.

CC

In either buck or boost mode, the two current control

loops always monitor the maximum average inductor cur-

rent. When it increases above the thresholds, the current

loops will take over the ITH pin control from the voltage

loop. As a result, the maximum average inductor current

is limited.

The main control loop is shut down by pulling the RUN pin

low. Releasing the RUN pin allows an internal 2μA current

source to pull it up. When the RUN pin reaches 1.22V,

the IC is powered up and the pull-up current increases to

6μA. When the RUN pin is low, all functions are kept in a

controlled shutdown state.

Most of the internal circuitry is powered from the V5

rail that is generated by an internal linear regulator from

DRV_CC. The V5 pin needs to be bypassed with a minimum

4.7μF external capacitor to SGND. This pin provides a 5V

output that can supply up to 20mA of current. See the

Applications Information section for more details.

Rev. 0

13

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LTC7872

OPERATION

Soft-Start (Buck Mode)

pin to be used to program a soft-start by connecting an

external capacitor from the SS pin to SGND. An internal

1μA pull-up current charges this capacitor, creating a volt-

age ramp on the SS pin. As the SS voltage rises linearly

from 0V to 1.2V (and beyond), the V_LOWvoltage rises

smoothly from zero to its final value. When the RUN pin

is pulled low to disable the controller, or when V5 drops

below its undervoltage lockout threshold, the SS pin is

pulled low by an internal MOSFET. When in undervolt-

age lockout, the controller is disabled and the external

MOSFETs are held off. External circuitry can be added to

discharge the soft-start capacitor during fault conditions

to ensure a soft-start when the faults are cleared.

By default, the start-up of the V

voltage is normally

LOW

controlled by an internal soft-start ramp. The internal soft-

start ramp represents a noninverting input to the error

amplifier. The VFB

pin is regulated to the lowest of the

LOW

error amplifier’s three noninverting inputs (the internal

soft-start ramp, the SS pin or the internal 1.2V reference).

As the ramp voltage rises from 0V to 1.2V over approxi-

mately 1ms, the V_LOWvoltage rises smoothly from its

prebiased value to its final set value. Certain applications

can require the start-up of the converter into a non-zero

load voltage, where residual charge is stored on the V

capacitor at the onset of converter switching. In order to

LOW

prevent the V

from discharging under these condi-

tions, the top^LOan^Wd bottom MOSFETs are disabled until

Frequency Selection, Spread Spectrum, and Phase-

Locked Loop (FREQ and SYNC Pins)

soft-start is greater than VFB

.

LOW

The selection of switching frequency is a trade-off between

efficiency and component size. Low frequency opera-

tion increases efficiency by reducing MOSFET switching

losses, but requires larger inductance and/or capacitance

to maintain low output ripple voltage.

Soft-Start (Boost Mode)

The same internal soft-start capacitor and external soft-

start capacitor are also active if the controller starts with

boost mode of operation. The error amplifier for boost

mode also tries to regulate to the lowest reference during

start-up. However, the topology of the boost converter

limits the effectiveness of this soft-start mechanism until

the boost output voltage reaches its input voltage level.

Therefore, it is recommended that the controller starts in

buck mode of operation.

If the SYNC pin is tied to SGND, the FREQ pin can be

used to program the controller’s operating frequency

from 67kHz to 725kHz. There is a precision 20μA current

flowing out of the FREQ pin so that the user can program

the controller’s switching frequency with a single resis-

tor to SGND. A curve is provided later in the Applications

Information section showing the relationship between

the voltage on the FREQ pin and switching frequency

(Figure 7).

Shutdown and Start-Up (RUN and SS Pins)

The LTC7872 can be shut down using the RUN pin.

Pulling the RUN pin below 1.22V shuts down the main

control loop for the controller and most internal circuits,

including the DRV_CCand V5 regulators. Releasing the

RUN pin allows an internal 2μA current to pull up the

pin and enable the controller. Alternatively, the RUN pin

may be externally pulled up or driven directly by logic. Be

careful not to exceed the absolute maximum rating of 6V

on this pin. The start-up of the controller’s V

is controlled by the voltage on the SS pin. When the volt-

age on the SS pin is less than the 1.2V internal reference,

the LTC7872 regulates the VFB

voltage instead of the 1.2V reference. This allows the SS

Switching regulators can be particularly troublesome for

applications when electromagnetic interface (EMI) is a

concern. To improve EMI, the LTC7872 can operate in

spread spectrum mode, which is enabled by tying the

SYNC pin to V5. This feature varies the switching fre-

quency at low frequency rate (switching frequency/512,

by default) with a triangular frequency modulation of

12%. For example, if the LTC7872’s frequency is pro-

grammed to switch at 200kHz, enabling spread spectrum

will modulate the frequency between 176kHz and 224kHz

at a 0.4kHz rate. These spread spectrum parameters are

programmed by the MFR_SSFM register.

voltage

LOW

voltage to the SS pin

LOW

Rev. 0

14

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LTC7872

OPERATION

A phase-locked loop (PLL) is available on the LTC7872

to synchronize the internal oscillator to an external clock

source that is connected to the SYNC pin. The PLL loop

filter network is integrated inside the LTC7872. The phase

locked loop is capable of locking to any frequency within

the range of 60kHz to 750kHz. The frequency setting

resistor should always be present to set the controller’s

initial switching frequency before locking to the external

clock. The controller operates in the user selected mode

when it is synchronized.

d. During a startup sequence until the SS pin charges up

past 1.2V.

e. When any channel is in overcurrent fault status.

f. When the IC is over temperature.

The OV_LOWand OV_HIGHthresholds are set using an exter-

nal resistor divider off V_LOWand V_HIGH, respectively.

When the voltage at the pin exceeds the comparator

threshold of 1.2V, a 5μA hysteresis current is sourced

out of the respective pin and the FAULT signal goes low

after a 120μs delay. The UV_HIGHthreshold is also set using

Undervoltage Lockout

an external resistor divider off V

. When the voltage

HIGH

The LTC7872 has two functions that help protect the con-

troller in case of undervoltage conditions. Two precision

UVLO comparators constantly monitor the V5 and DRV_CC

voltages to ensure that adequate voltages are present. The

at the pin falls below the comparator threshold of 1.2V, a

5μA hysteresis current is sunk into the UV

pin and the

FAULT signal goes low after a 120μs delay^H. ^IT^Gh^He amount of

hysteresis can be adjusted by changing the total imped-

ance of the resistor divider, while the resistor ratio sets

the UV/OV trip point.

switching action is stopped when V5 or DRV is below

CC

the undervoltage lockout threshold. To prevent oscillation

when there is a disturbance on the V5 or DRV , the UVLO

CC

Besides flagging the FAULT pin, the UV/OV compara-

tors also affect the operation of the controller, as shown

in Table 1. When the OV_LOWcomparator crosses its

1.2V threshold:

comparators have precision hysteresis.

Another way to detect an undervoltage condition is to

monitor the V_HIGHsupply. Because the RUN pin has a

precision turn-on reference of 1.22V, one can use a resis-

a. In buck mode, the controller stops switching.

b. In boost mode, the controller continues to switch.

tor divider to V

to turn on the IC when V

is high

HIGH

enough. An extra 4μA of current flows out of the RUN pin

once the RUN pin voltage passes 1.22V. The RUN com-

parator itself has about 80mV of hysteresis. Additional

hysteresis for the RUN comparator can be programmed

by adjusting the values of the resistive divider. For accu-

rate V_HIGHundervoltage detection, V_HIGHneeds to be

higher than 5V.

c. ITH and SS are unaffected in both buck and boost

modes. Whenever a fault is detected, discharge the

SS pin as needed externally.

When the OV

of 1.2V:

comparator crosses its 1st threshold

HIGH

a. The controller stops switching in both buck and

boost modes.

Fault Flag (FAULT, OV

, OV

and UV

Pins)

HIGH

LOW

HIGH

The FAULT pin is connected to the open-drain of an inter-

nal N-channel MOSFET. It can be pulled high with an exter-

nal resistor connected to a voltage up to 6V, such as V5

or an external bias voltage. The FAULT pin is pulled low

when at least one of the following conditions is met:

b. ITH and SS are unaffected in both buck and boost

modes. Whenever a fault is detected, discharge the

SS pin as needed externally.

When the OV

of 2.4V:

comparator crosses its 2nd threshold

HIGH

a. The RUN pin is below its turn on threshold.

a. The controller stops switching in both buck and

boost modes.

b. When V5 or DRV is below its UVLO threshold.

CC

c. Any of the three OV/UV comparators has been tripped.

Rev. 0

15

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LTC7872

OPERATION

b. Both ITH and IMON pins are driven into high imped-

ance. This feature allows the users to isolate one

LTC7872 from a multiphase system in case a fault is

detected on one particular IC.

where:

V_ZEROis the IMON voltage when average output current

is zero; V = 1.25V typically

ZERO

K = 40 if the ILIM voltage is 0V or 1/4 V

V5

c. The SS pin is unaffected.

K = 20 if the ILIM voltage is float, 3/4 V or V

V5

When the UV

comparator crosses its 1.2V threshold:

HIGH

I

is the total average inductor current including

L(ALL)

all four channels

a. In buck mode, the controller stops switching after a

120μs delay, and the SS pin pulls to SGND.

R

SENSE

is the current sensing resistor value.

b. In boost mode, the controller continues to switch. The

SS pin is unaffected.

An external voltage can be applied to the SETCUR pin

to regulate the maximum average inductor current. The

SETCUR pin voltage should be set as:

c. ITH is unaffected in both buck and boost modes.

Table 1. OV/UV Faults

K •I

•R

SENSE

(

)

L MAX

FAULT

MODE SWITCHING ITH PINS

Buck Stops No Effect No Effect

Boost Continues No Effect No Effect

IMON

SS

V

=

SETCUR

4

No Effect

OV

1.2V

LOW

Threshold

where:

I

Buck

Boost

Buck

Boost

Buck

Stops

No Effect No Effect

OV 1.2V

HIGH

is the maximum total average inductor current

Threshold

L(MAX)

including all four channels

Hi-Z

OV 2.4V

HIGH

Threshold

The SETCURP and SETCURN are internally generated

voltages based on the SETCUR pin:

No Effect No Effect Pulls to SGND

No Effect

UV 1.2V

HIGH

Threshold

Boost Continues No Effect No Effect

SETCURP = 1.25V + V

SETCUR

SETCURN = |1.25V – V

|

SETCUR

Current Monitoring and Regulation

(IMON, SETCUR Pins)

SETCURP, SETCURN, and IMON are the three inputs to

the current regulation loop error amplifier with SETCURP

and SETCURN acting as the reference. When the IMON pin

voltage approaches SETCURP or SETCURN, the ITH pin

control is taken over by the current loop error amplifier

from the voltage loop error amplifier.

The inductor current can be sensed using either its DCR or

a R

resistor. The current monitoring pin, IMON, out-

put^Ss^Ea^NSv^Eoltage that is proportional to the average induc-

tor current of the four channels sensed by the LTC7872.

The operational range of IMON is 0.4V to 2.5V. When the

average inductor current is zero, the IMON pin voltage

rests at 1.25V. As the inductor current increases in buck

mode, the IMON voltage proportionally increases; As the

inductor current increases in boost mode, the IMON volt-

age proportionally decreases. Use the following equation

to calculate the voltages on IMON:

In either buck or boost mode, both the maximum positive

average current and the maximum negative average cur-

rent are regulated. There is a 16µA current flowing out of

the SETCUR pin so that a single resistor to SGND can set

both the positive average current loop and negative aver-

age current loop. The sourcing current from the SETCUR

pin is programmable through the SPI interface. For bat-

tery charging applications, SETCUR can be programmed

dynamically on-the-fly to set the charging currents to the

batteries in either buck or boost mode. SETCUR can be

used at start-up to limit the in-rush current in both buck

K •I

•R

(

)

SENSE

L ALL

V

= V

+

; Buck Mode

; Boost Mode

IMON

ZERO

4

)

K •I

•R

(

SENSE

L ALL

= V

–

4

mode and boost mode.

Rev. 0

16

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LTC7872

OPERATION

To defeat the average current programming operation,

tie the SETCUR pin to V5 or voltage higher than 1.25V.

immediately when the regulated VFB

/VFB

volt-

HIGH

LOW

age is within 10% of the reference window. However,

there is an internal 40µs power bad mask when regulated

Buck and Boost Modes (BUCK Pin)

VFB

/VFB

voltage goes out of the 10% window.

LOW

HIGH

The PGOOD pin is allowed to be pulled up by an external

resistor to sources of up to 6V.

The LTC7872 can be dynamically and seamlessly switched

from buck mode to boost mode and vice versa via the

BUCK pin. Tie this pin to V5 to select buck mode and

to ground to select boost mode operation. This pin has

an internal pull up resistor that defaults to buck mode if

left floating. There are two separate error amplifiers for

Programmable V , V

HIGH LOW

Margining

As shown in the Figure 1, the LTC7872 has a SPI con-

trolled 7-bit D/A converter current source. Through the

SPI interface, the LTC7872 receives a 7-bit DAC code and

converts this value to a bidirectional analog output cur-

V

or V

regulation. Having two error amplifiers

HIGH

LOW

allows fine tuning of the loop compensation for the buck

and boost modes independently to optimize transient

response. When buck mode is selected, the correspond-

rent. The current is connected to the VFB

pin in buck

LOW

mode or the VFB

pin in boost mode. By connecting

HIGH

ing error amplifier is enabled, and ITH

voltage con-

the DAC current to the feedback node of a voltage regula-

LOW

trols the peak inductor current. The other error amplifier

is disabled and ITH is parked at its zero current level.

tor, in buck mode, V

voltage is programmed with the

LOW

equation:

HIGH

In boost mode, ITH_HIGHis enabled while ITH_LOWis parked

at its zero current level. During a buck to boost or a boost

to buck transition, the internal soft-start is reset. Resetting

soft-start and parking the ITH pin at the zero current level

ensures a smooth transition to the newly selected mode.

Refer to Table 2 for a summary.

V

= 1.2V • (1 + R /R ) – I

• R

LOW

B

A

DAC B

In boost mode, V_HIGHvoltage is programmed with

the equation:

V

HIGH

= 1.2V • (1 + R /R ) – I

• R

D

C

DAC

D

There are two different registers for V

and V

pro-

gramming, MFR_IDAC_VLOW and MFR_IDAC^H_^IV^GH^HIGH.

The current DAC selects the register value based on the

buck or boost mode. The current DAC’s LSB is 1µA. The

MSB determines the current direction. When MSB is 0,

LOW

To further minimize any transients, SETCUR can be pro-

grammed to zero current level before switching between

boost and buck modes.

Table 2. ITH PIN Parking Conditions

Mode When Parked Comments

IDAC is sourcing current (reducing V

is positive current flowing out of the^Lf^Oe^Wedbac^Hk^IGp^Hin. When

MSB is 1, IDAC is sinking current (increasing V

HIGH

back pin.

or V

), which

Normal

Buck

Boost

Buck

OV

2.4V Threshold Overrides Park

HIGH

Operation

or

LOW

ITH

HIGH

Prebiased

Turn-on

V

), which is negative current flowing into the feed-

HIGH

Prebiased OV

Turn-on

2.4V Threshold and OV

LOW

HIGH

Override Park

ꢒ

ꢓꢐꢔ

ꢕꢍꢖꢕ

ITH

LOW

Normal

Operation

Boost

OV

HIGH

2.4V Threshold Overrides Park

ꢌꢐꢐꢑꢄ ꢏꢐꢅꢂ

ꢍ

ꢌꢁꢀꢎ ꢏꢐꢅꢂ

R

ꢅ

ꢀ

ꢌ

ꢀꢁRRꢂꢃꢄ ꢅꢆꢀ

ꢒꢊꢌ

ꢕꢍꢖꢕ

ꢓꢐꢔ

R

ꢍ

R

ꢆ

Power Good (PGOOD Pin)

ꢅꢆꢀ

ꢇꢈꢇꢉ ꢊ0ꢋ

When the regulated VFB

/VFB

voltage is not within

LOW

10% of the 1.2V reference vol^Hta^IGg^He, the PGOOD pin is

pulled low. The PGOOD pin is also pulled low when the

RUN pin is below 1.2V or when the LTC7872 is in the

soft-start or UVLO. The PGOOD pin will flag power good

Figure 1. Current DAC for V_LOW/V_HIGHProgramming

Rev. 0

17

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LTC7872

OPERATION

Buck Mode Light Load Current Operation (DCM/CCM/

Burst Mode Operation)

At very light loads, the current comparator, I

, may

CMP

remain tripped for several cycles and force the external top

MOSFET to stay off for the same number of cycles (i.e.,

skipping-pulses). The inductor current is not allowed to

reverse (discontinuous operation). This mode, like forced

continuous operation, exhibits low output ripple as well

as low audio noise and reduced RF interference. It pro-

vides higher low current efficiency than forced continuous

mode, but not nearly as high as Burst Mode operation.

In buck mode, the LTC7872 can be enabled to enter dis-

continuous conduction mode (DCM), forced continuous

conduction mode (CCM), or Burst Mode operation. To

select forced continuous operation, tie the MODE pin

to SGND. To select discontinuous conduction mode of

operation, tie the MODE pin to V5. To select Burst Mode

operation, float the MODE pin.

In forced continuous operation, the inductor current is

allowed to reverse at light loads or under large transient

conditions. The peak inductor current is determined by

the voltage on the ITH_LOWpin, just as in normal operation.

In this mode, the efficiency at light loads is lower than

in DCM operation. However, continuous mode has the

advantages of lower output ripple and less interference

with audio circuitry.

Boost Mode Light Load Current Operation (DCM/CCM)

In boost mode, the LTC7872 can be enabled to enter

constant-frequency discontinuous conduction mode or

forced continuous conduction mode. To select forced con-

tinuous operation, tie the MODE pin to SGND. To select

discontinuous conduction mode of operation, tie the

MODE pin to V5 or float it. In forced continuous operation,

the inductor current is allowed to reverse at light loads

or under large transient conditions. The inductor current

valley is determined by the voltage on the ITH_HIGHpin,

just as in normal operation. In this mode, the efficiency

at light loads is lower. However, continuous mode has the

advantage of lower output ripple.

When the LTC7872 is enabled for Burst Mode operation,

the peak current in the inductor is set to approximately

one-third of the maximum sense voltage even though the

voltage on the ITH

pin indicates a lower value. If the

LOW

average inductor current is higher than the load current,

the error amplifier, EA, will decrease the voltage on the

When the MODE pin is connected to V5 or floated, the

LTC7872 operates in discontinuous conduction mode at

light loads. At very light loads, the current comparator,

I_CMP, may remain tripped for several cycles and force

the external top MOSFET to stay off for the same number

of cycles (i.e., skipping-pulses). The inductor current is

not allowed to reverse (discontinuous operation). This

mode, like forced continuous operation, exhibits low

output ripple as well as low audio noise and reduced RF

interference. It provides higher low current efficiency than

forced continuous mode.

ITH

pin. When the ITH

voltage drops below 1.1V,

LOW

the internal sleep signal goes high (enabling sleep mode)

and both external MOSFETs are turned off.

In sleep mode, the load current is supplied by the output

capacitor. As the output voltage decreases, the EA’s out-

put begins to rise. When the output voltage drops enough,

the sleep signal goes low, and the controller resumes nor

-

mal operation by turning on the top external MOSFET on

the next cycle of the internal oscillator. When a controller

is enabled for Burst Mode operation, the inductor cur-

rent is not allowed to reverse. The reverse current com-

The LTC7872 operation mode is summarized in Table 3.

Table 3. Operation Mode

parator (I ) turns off the bottom external MOSFET just

REV

before the inductor current reaches zero, preventing it

from reversing and going negative. Thus, the controller

operates in discontinuous conduction mode.

MODE Pin

0V

Buck Operation Mode

CCM

Boost Operation Mode

CCM

DCM

Float

Burst Mode Operation

DCM

When the MODE pin is connected to V5, the LTC7872

operates in discontinuous conduction mode at light loads.

V

V5

Rev. 0

18

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LTC7872

OPERATION

Overcurrent Fault Monitor (OCFT and NOCFT)

The LTC7872’s PWMEN pin is used to communicate the

controller’s status with the external MOSFET drivers or

other LTC7872s. When the LTC7872 releases the PWMEN

pin but finds it is still pulled down externally, the LTC7872

will keep all the PWM pins in Hi-Z status.

Besides the peak/valley current comparator and the maxi-

mum average current regulation loops, the LTC7872 has

an additional overcurrent fault comparator to monitor the

voltage difference between the SNSD⁺and SNS^–pins.

+

–

If one channel’s (V

– V

) is larger than over-

SNSD

SNS

Multiphase Operation

current fault threshold (OCFT) or less than the negative

overcurrent threshold (NOCFT) as shown in the Table 4,

all four channels stop switching and all PWM pins are

Hi-Z. The OCFT and NOCFT status can be obtained

through the SPI interface by the MFR_OC_FAULT and

MFR_NOC_FAULT registers.

For output loads that demand high current, multiple

LTC7872s can be daisy chained to run out of phase to

provide more output current without increasing input and

output voltage ripple. The SYNC pin allows the LTC7872

to synchronize to the CLKOUT signal of another LTC7872.

The CLKOUT signal can be connected to the SYNC pin of

the following LTC7872 stage to line up both the frequency

and the phase of the entire system. When paralleling mul-

tiple ICs, please be aware of the input impedance of pins

connected to the same node.

+

–

Table 4. OCFT and NOCFT Threshold (V

SNSD

– V

)

SNS

ILIM Pin

Voltage

OCFT

Threshold

NOCFT

Threshold

–37.5mV

–50mV

Hysteresis

25mV

0V

37.5mV

50mV

1/4 V

31mV

V5

Float

3/4 V

62.5mV

75mV

–62.5mV

–75mV

31mV

Thermal Shutdown

31mV

V5

The LTC7872 has a temperature sensor integrated on

the IC, to sense the die temperature. When the die tem-

perature exceeds 180°C, all switching actions stop, and

all PWM pins become Hi-Z, thus turning off all external

MOSFETs. At the same time, all the channels are discon-

V

87.5mV

–87.5mV

31mV

V5

PWM and PWMEN Pins

The PWM pins are three-state compatible outputs,

designed to drive power stages such as power blocks,

DrMOS, and drivers with MOSFETs, none of which repre-

sents a heavy capacitive load. An external resistor divider

may be used to set the PWM voltage to mid-rail while the

PWM is in the high impedance state.

nected from the IMON pins, and the SS and ITH_HIGH

/

ITH pins continue to function normally, so as not to

LOW

interfere with other LTC7872 chips that may reference the

common pins. When the temperature drops 15°C below

the trip threshold, normal operation resumes.

The PWMEN pin is an open-drain output pin. It should

be pulled up by an external resistor to V5 when the

controller starts switching. During any fault status, the

LTC7872 pulls down the PWMEN pin to disable the exter-

nal MOSFET driver.

Rev. 0

19

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LTC7872

APPLICATIONS INFORMATION

The Typical Application on the first page of this data sheet

is a basic LTC7872 application circuit. In general, external

component selection is driven by the load requirements,

+

–

SNSD , SNSA and SNS Pins

+

–

The SNSA and SNS pins are the inputs to the current

comparators, while the SNSD⁺and SNS^–pins are the input

of an internal DC amplifier. The operating input voltage

range is 0V to 60V for all three sense pins. All the positive

sense pins that are connected to the current comparator

or the amplifier are high impedance with input bias cur-

and begins with the DCR or R

and inductor value.

SENSE

Next, power MOSFETs are selected. Finally, V_HIGHand

V

LOW

capacitors are selected.

Slope Compensation and Inductor Peak Current

–

rents of less than 1μA. The SNS pin is not a high imped-

Slope compensation provides stability in constant fre-

quency architectures by preventing subharmonic oscilla-

tions at high duty cycles. It is accomplished internally by

adding a compensating ramp to the inductor current sig-

nal at duty cycles in excess of 40%. Normally, this results

in a reduction of maximum inductor peak current for duty

cycles > 40%. However, the LTC7872 uses a scheme that

counteracts this compensating ramp, which allows the

maximum inductor peak current to remain unaffected

throughout all duty cycles.

ance pin. For V

voltages greater than V5, the current

LOW

comparators derive their bias currents directly from the

–

SNS pins. The SNS pins should be connected directly

to V . Care must be taken not to float these pins during

LOW

normal operation. Filter components, especially capaci-

tors, must be placed close to the LTC7872, and the sense

lines should run close together to a Kelvin connection

underneath the current sense element (Figure 2). Because

the LTC7872 is designed to be used with a very low value

sensing element to sense inductor current, without proper

care, the parasitic resistance, capacitance and inductance

will degrade the current sense signal integrity, making

the programmed current limit unpredictable. As shown in

Figure 3, resistor R1 is placed close to the output induc-

tor and capacitors C1 and C2 are close to the IC pins to

prevent noise coupling to the sense signal.

Current Limit Programming

The ILIM pin is a 5-level logic input which sets the maxi-

mum current limit of the controller. Table 5 shows the five

ILIM settings. Please note that these settings represent

the peak inductor current setting. Because of the inductor

ripple current, the average output current is lower than

the peak current. Setting ILIM using a resistor divider

from V5 to SGND will allow the maximum current sense

threshold setting to not change when the 5V LDO is in

dropout at start-up. Please note that the ILIM pin has an

internal 200k pull down resistor to SGND and a 200k pull

up resistor to V5.

ꢃꢁ ꢄꢅꢆꢄꢅ ꢇꢈꢉꢃꢅR ꢉꢁꢀꢊꢃꢅꢋ

ꢆꢅꢌꢃ ꢃꢁ ꢃꢍꢅ ꢀꢁꢆꢃRꢁꢉꢉꢅR

ꢀ

ꢁꢂꢃ

ꢎꢏꢎꢐ ꢇ0ꢐ

Figure 2. Sense Lines Placement with Sense Resistor

Inductor DCR Sensing

Table 5. ILIM Settings

Maximum Current Sense Threshold

The LTC7872 is specifically designed for high load current

applications requiring the highest possible efficiency; it is

capable of sensing the signal of an inductor DCR in the

milliohm range (Figure 3). The DCR is the DC winding

resistance of the inductor’s copper, which is often several

mΩ for high current inductors. In high current applica-

ILIM Pin Voltage

DCR Sensing

10mV

R

SENSE

0V

12.5mV

25mV

1/4 V

20mV

V5

Float

30mV

37.5mV

50mV

3/4 V

40mV

V5

tions, the conduction loss of a high DCR or a sense resis

-

V

50mV

62.5mV

V5

tor will cause a significant reduction in power efficiency.

+

The SNSA pin connects to the filter that has a R1 • C1

time constant one-fifth of the L/DCR of the inductor. The

+

SNSD pin is connected to the second filter with the time

Rev. 0

20

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LTC7872

APPLICATIONS INFORMATION

constant matched to L/DCR of the inductor. For a specific

output requirement, choose the inductor with the DCR

that satisfies the maximum desired sense voltage, and

uses the relationship of the sense pin filters to output

inductor characteristics as depicted below.

provides better efficiency at heavy loads. To maintain a

good signal-to-noise ratio for the current sense signal,

+

–

use a minimum of 10mV between SNSA and SNS pins

or the equivalent of 2mV ripple on the current sense signal

for duty cycles less than 40%. The actual ripple voltage

+

–

across SNSA and SNS pins will be determined by the

following equation:

V

SENSE(MAX)

DCR =

∆I

L

I

+

MAX

V

– V

LOW

HIGH

LOW

OSC

2

∆V

=

•

SENSE

V

R1• C1• f

HIGH

L

= 5 • R1• C1= R2 • C2

DCR

ꢋ

ꢍ

ꢉꢊꢉ

ꢀꢁꢂꢃꢄꢃꢅ

ꢂꢅ

where:

ꢂꢈ

ꢉꢊꢉꢌ

Rꢅ

V

is the maximum sense voltage for a given

SENSE(MAX)

ILIM threshold

Rꢈ

ꢉꢏ

ꢉꢊꢉꢎ

ꢀ

ꢃꢄꢃꢅ ꢆ0ꢇ

ꢐ

ꢀꢑꢏ

ꢍ

∆I is the Inductor ripple current

L

L and DCR are the output inductor characteristics

+

Figure 3. Inductor DCR Sensing

R1 • C1 is the filter time constant of the SNSA pin

+

R2 • C2 is the filter time constant of the SNSD pin

Sensing Using an R

Resistor

SENSE

To ensure that the load current will be delivered over the

full operating temperature range, the temperature coef-

ficient of DCR resistance, approximately 0.4%/°C, should

be taken into account.

The LTC7872 can be used with an external R

resis-

SENSE

tor to sense current accurately. The external components

required to accomplish this are shown in Figure 4. The

SNSD⁺pin senses directly across the R_Sresistor through

R3 and C3 network. The R1, R2, and C1 network provide

Typically, C1 and C2 are selected in the range of 0.047μF

to 0.47μF. If C1 and C2 are chosen to be 0.1μF, and an

inductor of 10μH with 2mΩ DCR is selected, R1 and R2

will be 10k and 49.9k, respectively. The bias current at

+

the current signal path to the SNSA pin. Internally the

signals from the AC and DC paths are combined for accu-

rate current sensing and low jitter performance. Resistor

R2 is used to divide down the DC component of the signal

+

SNSD and SNSA is less than 1μA, and it introduces a

small error to the sense signal.

+

seen by SNSA due to the DCR of the inductor. As a rule

of thumb, R2 needs to be 10 times smaller than R1 so

the DCR value can be safely ignored.

There will be some power loss in R1 that relates to the

duty cycle, and will be the most in continuous mode at

Rꢏ

the maximum V

voltage:

HIGH

ꢌ

ꢉꢊꢉꢋ

ꢀꢁꢂꢃꢄꢃꢅ

ꢂꢅ

ꢂꢈ

V

– V

• V

LOW

(

)

HIGH(MAX)

LOW

ꢍ

ꢉꢊꢉ

P

R =

( )

LOSS

Rꢅ

R

Rꢈ

ꢌ

ꢉꢊꢉꢎ

ꢀ

R

ꢉ

ꢃꢄꢃꢅ ꢆ0ꢇ

Ensure that R1 has a power rating higher than this value.

Care has to be taken for voltage coefficients of these resis-

tors at high V_HIGHvoltages. Multiple resistors can be used

in series to minimize this effect. However, DCR sensing

eliminates the conduction loss of a sense resistor; it also

ꢉꢐ

ꢑ

ꢀꢒꢐ

ꢌ

Figure 4. R_SENSEResistor Sensing

Rev. 0

21

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LTC7872

APPLICATIONS INFORMATION

The R1 • C1 time constant should be selected such that:

Upon removal of the short, V

soft starts using the

internal soft-start, thus reduc^Lin^Og^Woutput overshoot. In

the absence of this feature, the output capacitors would

have been charged at current limit, and in applications

with minimal output capacitance this may have resulted

in output overshoot. Current limit foldback is not disabled

during an overcurrent recovery. The load must drop below

the folded back current limit threshold in order to restart

from a hard short.

L

= 4 •R1•C1 for R1= 10 •R2

R

S

The R3 • C2 time constant should be selected such that:

R1•R2

R3 •C2 =

•C1

R1

+

R2

If a 6.8μH inductor and a 1mΩ sense resistor are selected

and C1 and C2 are chosen to be 0.1µF, then the values for

R1, R2 and R3 will be 16.9k, 1.69k and 1.5k, respectively

when the nearest standard value is chosen.

In both buck and boost modes of operation, forcing a

voltage on the SETCUR pin regulates the average current.

Zero average inductor current can be obtained by forcing

0V on SETCUR.

Pre-Biased Output Start-Up

The LTC7872 has additional overcurrent fault compara-

tors to monitor the current of each channel. If there is

any catastrophic failure in the system which causes one

or more channel’s inductor current to be higher than the

overcurrent fault threshold, all the channels will be shut

down and both the PWMEN and the FAULT pins will be

pulled down to SGND.

There may be situations that require the power supply to

start up with a prebias on the V

output capacitors. In

LOW

this case, it is desirable to start up without discharging

that output prebias. The LTC7872 can safely power up

into a prebiased output without discharging it.

The LTC7872 accomplishes this by disabling both the

top and bottom MOSFETs until the SS pin voltage and the

Another way to protect against overcurrent is to moni-

tor the IMON pin voltage. If the IMON voltage indicates

excessive current, an external circuit can be used to shut

down the system.

internal soft-start voltage are above the VFB

pin volt-

LOW

age. When VFB

is higher than SS or the internal soft-

LOW

start voltage, the error amp output is parked at its zero

current level. Disabling both top and bottom MOSFETs

prevents the prebiased output voltage from being dis-

charged. When SS and the internal soft-start both cross

1.32V or VFB_LOW, whichever is lower, both top and bottom

MOSFETs are enabled.

Inductor Value Calculation

Given the desired input and output voltages, the inductor

value and operating frequency, f_OSC, directly determine

the inductor’s peak-to-peak ripple current:

Overcurrent Fault Protection

⎛

⎞

V

V_HIGH

V_HIGH– V

LOW

I_RIPPLE

=

⎜

⎟

f_OSC•L

⎝

⎠

In the buck mode, when the output of the power supply

is loaded beyond its preset current limit, the regulated

output voltage will collapse depending on the load. The

Lower ripple current reduces core losses in the inductor,

ESR losses in the output capacitors, and output voltage

ripple. Thus, highest efficiency operation is obtained at

low frequency with a small ripple current. Achieving this,

however, requires a large inductor.

V

rail may be shorted to ground through a very low

LOW

impedance path or it may be a resistive short, in which

case the output will collapse partially, until the load cur-

rent equals the preset current limit. The controller will

continue to source current into the short. The amount of

current sourced depends on the ILIM pin setting and the

A reasonable starting point is to choose a ripple current

that is about 40% of the maximum inductor current. Note

that the largest ripple current occurs at the highest V

voltage. To guarantee that ripple current does not exceed

VFB

voltage as shown in the Current Foldback graph

LOW

HIGH

in the Typical Performance Characteristics section.

Rev. 0

22

For more information www.analog.com

LTC7872

APPLICATIONS INFORMATION

a specified maximum, the inductor should be chosen

according to:

The peak-to-peak MOSFET gate drive levels are set by

the internal DRV_CCregulator voltage. Pay close atten-

tion to the BV

specification for the MOSFETs as well.

DSS

V

– V

V

LOW

HIGH

LOW

L ≥

•

Selection criteria for the power MOSFETs include the on-

resistance R , input capacitance, input voltage and

f

•I

V

HIGH

RIPPLE

OSC

DS(ON)

maximum output current. MOSFET input capacitance is

a combination of several components but can be taken

from the typical gate charge curve included on most data

sheets (Figure 5). The curve is generated by forcing a

constant input current into the gate of a common source,

current source loaded stage and then plotting the gate

voltage versus time.

Inductor Core Selection

Once the inductance value is determined, the type of

inductor must be selected. Core loss is independent of

core size for a fixed inductor value, but it is very depen-

dent on inductance selected. As inductance increases,

core losses go down. Unfortunately, increased inductance

requires more turns of wire and therefore copper losses

will increase.

ꢂ

ꢅꢆ

ꢍꢅꢎꢎꢏR ꢏꢊꢊꢏꢐꢑ

ꢂ

Ferrite designs have very low core loss and are preferred

at high switching frequencies, so design goals can con-

centrate on copper loss and preventing saturation. Ferrite

core material saturates “hard,” which means that induc-

tance collapses abruptly when the peak design current is

exceeded. This results in an abrupt increase in inductor

ripple current and consequent output voltage ripple. Do

not allow the core to saturate!

ꢌꢄ

ꢓ

ꢔ

ꢀ

ꢁ ^ꢂ

ꢃꢄ

ꢀ

ꢒ

ꢅꢆ

ꢂ

ꢌꢄ

ꢁ

ꢐ

ꢕ ꢖꢒ ꢁ ꢒ ꢙꢚꢂ

ꢗ ꢘ ꢃꢄ

ꢍꢅꢎꢎꢏR

ꢇꢈꢇꢉ ꢊ0ꢋ

Figure 5. Gate Charge Characteristic

The initial slope is the effect of the gate-to-source and the

gate-to-drain capacitance. The flat portion of the curve is

the result of the Miller multiplication effect of the drain-

to-gate capacitance as the drain drops the voltage across

the current source load. The upper sloping line is due to

the drain-to-gate accumulation capacitance and the gate-

to-source capacitance. The Miller charge (the increase

in coulombs on the horizontal axis from a to b while the

Power MOSFET and Schottky Diode (Optional)

Selection

At least two external power MOSFETs need to be selected:

One N-channel MOSFET for the top switch and one or

more N-channel MOSFET(s) for the bottom switch. The

number, type and on-resistance of all MOSFETs selected

take into account the voltage step-down ratio as well

as the actual position (top or bottom) in which the

MOSFET will be used. A much smaller and much lower

input capacitance MOSFET should be used for the top

curve is flat) is specified for a given V drain voltage,

DS

but can be adjusted for different V voltages by multi-

DS

plying the ratio of the application V to the curve speci-

DS

fied V values. A way to estimate the C

term is to

DS

MILLER

take the change in gate charge from points a and b on a

MOSFET in applications that have an V

that is less

LOW

manufacturer’s data sheet and divide by the stated V

than one-third of V

LOW

. In applications where V

>>

DS

HIGH

voltage specified. C

is the most important selec-

V

, the top MOSFETs’ on-resistance is normally less

MILLER

tion criteria for determining the transition loss term in

important for overall efficiency than its input capacitance

at operating frequencies above 300kHz. MOSFET man-

ufacturers have designed special purpose devices that

provide reasonably low on-resistance with significantly

reduced input capacitance for the top switch application

in switching regulators.

the top MOSFET but is not directly specified on MOSFET

data sheets. C

and C are specified sometimes but

OS

RSS

definitions of these parameters are not included. When

Rev. 0

23

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LTC7872

APPLICATIONS INFORMATION

the controller is operating in continuous mode the duty

cycles for the top and bottom MOSFETs are given by:

An optional Schottky diode across the bottom MOSFET

conducts during the dead time between the conduction

of the two large power MOSFETs in buck mode. This pre-

vents the body diode of the bottom MOSFET from turning

on, storing charge during the dead time and requiring

a reverse-recovery period which could cost as much as

several percent in efficiency. A 2A to 8A Schottky is gen-

erally a good compromise for both regions of operation

due to the relatively small average current. Larger diodes

result in additional transition loss due to their larger

junction capacitance.

V

V_HIGH

LOW

TopSwitchDuty Cycle =

⎛

⎞

⎟

⎠

V_HIGH– V

LOW

BottomSwitchDuty Cycle =

⎜

V_HIGH

⎝

The power dissipation for the top and bottom MOSFETs

at maximum output current are given by:

2

V_LOW

V_HIGH

P_TOP

=

I

(

1+δ R

+

(

)

MAX

DS(ON)

C

and MOSFETs Selection (on V

and V

)

HIGH

LOW

In continuous mode, the source current of the top

MOSFET is a square wave of duty cycle (V )/(V ).

To prevent large voltage transients, a low ESR capaci-

tor sized for the maximum RMS current of one channel

must be used. In the following discussion, it is assumed

I

⎛

⎞

2

MAX

V

R

C

•

(

_DR)(

)

(

)

MILLER

HIGH

⎜

⎟

LOW

HIGH

2

⎝

⎠

⎡

⎤

⎥

⎦

1

+

•f

⎢

DRV – V_TH(MIN)V_{TH(MIN) ⎥}

⎢

⎣

CC

that C is C

, C

is C

, V is V

, and V

is

IN

HIGH

IN

OUT

V_LOW. The maximu^Om^UTRMS^Lc^Oa^Wpacitor cu^Hrr^IGe^Hnt is given by:

2

V_HIGH– V_LOW

V_HIGH

P_BOT

=

I

(

1+δ R

( )

DS(ON)

)

MAX

1/2

I_MAX

⎡

⎤

)

⎦

C_INRequired I_RMS

≈

V

_OUT)(

V – V

IN

OUT

(

⎣

V

IN

I

= Maximum Inductor Current.

MAX

where δ is the temperature dependency of R

, R

This formula has a maximum at V_IN= 2V_OUT, where

= I /2. This simple worst-case condition is com-

monly used for design because even significant deviations

do not offer much relief. Note that capacitor manufacturers’

ripple current ratings are often based on only 2000 hours

of use.

DS(ON) DR

is the effective top driver resistance; V_HIGHis the drain

potential and the change in drain potential in the particular

application. V_TH(MIN)is the data sheet specified typical

gate threshold voltage specified in the power MOSFET

I

RMS

OUT

data sheet at the specified drain current. C

is the

MILLER

calculated capacitance using the gate charge curve from

the MOSFET data sheet and the technique described

above.

Both MOSFETs have I²R losses while the topside

N-channel equation includes an additional term for tran-

sition losses, which peak at the highest input voltage.

This makes it advisable to further derate the capacitor, or

to choose a capacitor rated at a higher temperature than

required. Several capacitors may be paralleled to meet size

or height requirements in the design. Ceramic capacitors

can also be used for C . Always consult the manufacturer

IN

if there is any question.

The bottom MOSFET losses are greatest at high V

HIGH

Ceramic capacitors are becoming very popular for small

designs but several cautions should be observed. X7R, X5R

and Y5V are examples of a few of the ceramic materials

used as the dielectric layer, and these different dielectrics

have very different effect on the capacitance value due to

the voltage and temperature conditions applied. Physically,

if the capacitance value changes due to applied voltage

change, there is a concomitant piezo effect which results

Rev. 0

voltage when the top switch duty factor is low or during

a V

short-circuit when the bottom switch is on close

LOW

to 100% of the period.

The term (1 + δ) is generally given for a MOSFET in the

form of a normalized R

vs temperature curve, but

DS(ON)

δ = 0.005/°C can be used as an approximation for low

voltage MOSFETs.

24

For more information www.analog.com

LTC7872

APPLICATIONS INFORMATION

in radiating sound! A load that draws varying current at an

audible rate may cause an attendant varying input voltage

on a ceramic capacitor, resulting in an audible signal. A

secondary issue relates to the energy flowing back into

a ceramic capacitor whose capacitance value is being

reduced by the increasing charge. The voltage can increase

at a considerably higher rate than the constant current

being supplied because the capacitance value is decreasing

as the voltage is increasing! Nevertheless, ceramic capaci-

tors, when properly selected and used, can provide the

lowest overall loss due to their extremely low ESR.

significantly different from that of an ideal capacitor and

therefore requires accurate modeling or bench evalua-

tion during design. Manufacturers such as Nichicon,

Nippon Chemi-Con and Sanyo should be considered for

high performance through-hole capacitors. The OS-CON

semiconductor dielectric capacitors available from Sanyo

and the Panasonic SP surface mount types have a good

(ESR)(size) product.

Once the ESR requirement for C_OUThas been met, the

RMS current rating generally far exceeds the I

requirement. Ceramic capacitors from A^RV^IX^PP,^LET⁽a^Pi^–y^Po⁾

Yuden, Murata and TDK offer high capacitance value

and very low ESR, especially applicable for low output

voltage applications.

A small (0.1μF to 1μF) capacitor, C_IN, placed close to

the LTC7872 between the V pin and ground, bypasses

IN

switching noise to ground. A 2.2Ω to 10Ω resistor, placed

between C_INand V_HIGHpins decouples the V_HIGHpin from

switching noise.

In surface mount applications, multiple capacitors may

have to be paralleled to meet the ESR or RMS current

handling requirements of the application. Aluminum elec-

trolytic and dry tantalum capacitors are both available in

surface mount configurations. New special polymer sur-

face mount capacitors offer very low ESR also but have

much lower capacitive density per unit volume. In the

case of tantalum, it is critical that the capacitors are surge

tested for use in switching power supplies. Several excel-

lent choices are the AVX TPS, AVX TPSV, the KEMET T510

series of surface mount tantalums or the Panasonic SP

series of surface mount special polymer capacitors avail-

able in case heights ranging from 2mm to 4mm. Other

capacitor types include Sanyo POSCAP, Sanyo OS-CON,

Nichicon PL series and Sprague 595D series. Consult the

manufacturers for other specific recommendations.

The selection of C

at V

is driven by the required

OUT

effective series resistance (ESR). Typically once the ESR

requirement is satisfied the capacitance is adequate for

filtering. The steady-state output ripple (∆V ) is deter-

OUT

mined by:

⎛

⎜

⎝

⎞

1

ΔV_OUT≈ ΔI_RIPPLEESR+

⎟

8fC_OUT

⎠

where f = operating frequency, C

= output capacitance

and ∆I

= ripple current in^Oth^Ue^Tinductor. The output

RIPPLE

ripple is highest at maximum input voltage since ∆I_RIPPLE

increases with input voltage (V_HIGH). The output ripple will

be less than 50mV at maximum V with ∆I

IOUT(MAX)

= 0.4

IN

RIPPLE

assuming:

C

Capacitor Selection for Boost Operation

HIGH

C

OUT

required ESR < N • R

SENSE

Contributions of ESR (equivalent series resistance), ESL

(equivalent series inductance) and the bulk capacitance

must be considered when choosing the correct combina-

tion of output capacitors for a boost converter application.

and

1

C

>

OUT

8f R

(

)

(

)

SENSE

The choice of component(s) begins with the maximum

acceptable ripple voltage (expressed as a percentage of

the output voltage), and how this ripple should be divided

between the ESR step and the charging/discharging ∆V.

For the purpose of simplicity we will choose 2% for the

maximum output ripple, to be divided equally between the

ESR step and the charging/discharging ∆V. This percentage

Rev. 0

The emergence of very low ESR capacitors in small,

surface mount packages makes very small physical

implementations possible. The ability to externally com-

pensate the switching regulator loop using the ITH pin

allows a much wider selection of output capacitor types.

The impedance characteristic of each capacitor type is

25

For more information www.analog.com

LTC7872

APPLICATIONS INFORMATION

ripple will change, depending on the requirements of the

application, and the equations provided below can easily

be modified.

The output ripple current is divided between the various

capacitors connected in parallel at the output voltage.

Although ceramic capacitors are generally known for low

ESR (especially X5R and X7R), these capacitors suffer

from a relatively high voltage coefficient. Therefore, it is

not safe to assume that the entire ripple current flows in

the ceramic capacitor. Aluminum electrolytic capacitors

are generally chosen because of their high bulk capaci-

tance, but they have a relatively high ESR. As a result,

some amount of ripple current will flow in this capacitor.

If the ripple current flowing into a capacitor exceeds its

RMS rating, the capacitor will heat up, reducing its effec-

tive capacitance and adversely affecting its reliability. After

the output capacitor configuration has been determined

using the equations provided, measure the individual

capacitor case temperatures in order to verify good ther-

mal performance.

One of the key benefits of multiphase operation is a reduc-

tion in the peak current supplied to the output capacitor

by the boost diodes. As a result, the ESR requirement

of the capacitor is relaxed. For a 1% contribution to the

total ripple voltage, the ESR of the output capacitor can

be determined using the following equation:

0.01• V

OUT

ESR

>

COUT

I

(

)

D PEAK

where:

I_{O MAX}

1–D_MAX

1

n

χ

(

)

⎛

⎝

⎞

⎠

I_{D PEAK}₎= • 1+

•

(

2

The factor n represents the number of phases and the

Setting Output Voltage

χ

factor represents the percentage inductor ripple current.

The LTC7872 output voltage is set by two external feed-

back resistive dividers carefully placed across V_HIGHto

For the bulk capacitance, which we assume contributes

1% to the total output ripple, the minimum required

capacitance is approximately:

ground and V

to ground, as shown in Figure 6. The

LOW

regulated output voltage is determined by:

I

(

)

O MAX

C

≥

⎛

⎜

⎝

⎞

⎛

⎞

R_B

R_A

R_D

R_C

OUT

0.01•n • V

• f

V

= 1.2V • 1+

and V_HIGH= 1.2V • 1+

OUT

LOW

⎜

⎟

⎝

⎠

For many designs it will be necessary to use one type of

capacitor to obtain the required ESR, and another type to

satisfy the bulk capacitance. For example, using a low ESR

ceramic capacitor can minimize the ESR step, while an

electrolytic capacitor can be used to supply the required

bulk C.

To improve the frequency response, a feed forward capac-

itor, C /C , may be used. Great care should be taken

FF1 FF2

to route the feedback line away from noise sources, such

as the inductor or the SW line.

ꢀ

ꢁꢂꢃꢁ

R

ꢈꢍꢎ

R

The voltage rating of the output capacitor must be greater

than the maximum output voltage, with sufficient derating

to account for the maximum capacitor temperature.

ꢅ

ꢆꢆꢏ

ꢆꢆꢇ

ꢄ

ꢌ

ꢈꢉꢅꢊꢋꢊꢇ

ꢀꢆꢌ

ꢈꢍꢎ

ꢁꢂꢃꢁ

R

ꢅ

ꢐ

Because the ripple current in the output capacitor is a

square wave, the ripple current requirements for this

capacitor depend on the duty cycle, the number of phases

and the maximum output current. In order to choose a

ripple current rating for the output capacitor, first establish

the duty cycle range, based on the output voltage and

range of input voltage.

ꢊꢋꢊꢇ ꢆ0ꢑ

Figure 6. Setting Output Voltage

Rev. 0

26

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LTC7872

APPLICATIONS INFORMATION

External Soft-Start

of 4.7μF ceramic capacitor or low ESR electrolytic capaci-

tor. No matter what type of bulk capacitor is used, an addi-

tional 0.1μF ceramic capacitor placed directly adjacent to

the V5 and SGND pins is highly recommended.

The LTC7872 has the ability to soft-start by itself using

the internal soft-start or at a slower rate with an external

capacitor on the SS pin. The controller is in the shutdown

state if its RUN pin voltage is below 1.14V and its SS pin

is actively pulled to ground in this shutdown state. If the

RUN pin voltage is above 1.22V, the controller powers

Fault Conditions: Current Limit and Current Foldback

In buck mode, the LTC7872 includes current foldback to

help limit power dissipation when the V

is shorted to

up. Once V5 and DRV pass the UVLO thresholds and

LOW

CC

ground. If the V

falls below 33% of its nominal output

power on reset delay expires, a soft-start current of 1μA

then starts to charge the SS soft-start capacitor. Note that

LOW

level, then the maximum sense voltage is progressively

lowered from its maximum programmed value to one-third

of the maximum value. Foldback current limiting is disabled

during soft-start. Under short-circuit conditions with very

low duty cycles, the LTC7872 will begin cycle skipping in

order to limit the short-circuit current. In this situation the

bottom MOSFET will be dissipating most of the power but

less than in normal operation. The short circuit ripple cur-

soft-start is achieved not by limiting the maximum V

LOW

output current of the controller but by controlling the out-

put ramp voltage according to the ramp rate on the SS

pin. Current foldback is disabled during this phase. The

soft-start range is defined to be the voltage range from

0V to 1.2V on the SS pin. The total soft-start time can be

calculated as:

rent is determined by the minimum on-time t

of the

ON(MIN)

voltage and inductor value:

C

SS

LTC7872, the V

t

= 1.2 •

HIGH

SOFTSTART

1µA

V

HIGH

L

∆I

= t

)

•

)

(

ON MIN

L SC

The Internal LDOs

The LTC7872 features three internal PMOS LDOs. Two

The resulting short circuit current is:

provide power to DRV from either the V

or V

1

CC

LOW

supply, and the third provides the V5 rail ^Hfr^IGo^Hm DRV .

⎛

⎞

V_{SENSE MAX}

R_SENSE

1

⁾– ∆I

2

(

3

I_SC

=

( )

DRV powers the external top and bottom gate dr^Civ^Ce

⎜

L SC ⎟

⎝

⎠

CC

circuits, and V5 powers the LTC7872’s internal circuitry.

After a short, make sure that the load current takes the

folded back current limit into account.

There are two DRV_CCLDOs—one that converts DRV_CC

from V

LOW

(LDO1) and another that converts DRV from

CC

(^HL^ID^GO^H2), thus allowing the part to start up with just

Phase-Locked Loop and Frequency Synchronization

V

one of the two rails present! Only one of those LDOs is

active at any given time. If V is higher than the EXTV

The LTC7872 has a phase-locked loop (PLL) comprised

of an internal voltage-controlled oscillator (VCO) and a

phase detector. This allows the turn-on of the top MOSFET

to be locked to the rising edge of an external clock signal

applied to the SYNC pin. The phase detector is an edge

sensitive digital type that provides zero degrees phase

shift between the external and internal oscillators. This

type of phase detector does not exhibit false lock to har-

monics of the external clock.

LOW

CC

switchover threshold, LDO2 is active; if it is below the swi-

tchover threshold, LDO1 is active. The DRV pin regula-

CC

tion voltage is determined by the state of the DRVSET pin.

The DRVSET pin uses a 3-level logic. When DRVSET is

either grounded, floated or tied to V5, the typical value for

the DRV voltage will be 5V, 8V and 10V, respectively.

CC

Please note that the DRVSET pin has an internal 160kΩ pull

down resistor to SGND and a 200kΩ pull up resistor to V5.

The output of the phase detector is a pair of comple-

mentary current sources that charge or discharge the

internal filter network. There is a precision 20μA current

The V5 LDO regulates the voltage at the V5 pin to 5V when

DRV is at least 6V. The LDO can supply a peak current of

20m^CA^Cand must be bypassed to ground with a minimum

Rev. 0

27

For more information www.analog.com

LTC7872

APPLICATIONS INFORMATION

flowing out of the FREQ pin. This allows the user to use

a single resistor to SGND to set the switching frequency

when no external clock is applied to the SYNC pin. The

internal switch between the FREQ pin and the integrated

PLL filter network is on, allowing the filter network to be

pre-charged at the same voltage as of the FREQ pin. The

relationship between the voltage on the FREQ pin and

operating frequency is shown in Figure 7 and specified in

the Electrical Characteristics table. If an external clock is

detected on the SYNC pin, the internal switch mentioned

above turns off and isolates the influence of the FREQ

pin. Note that the LTC7872 can only be synchronized to

an external clock whose frequency is within range of the

LTC7872’s internal VCO. A simplified block diagram is

shown in Figure 8.

If the external clock frequency is greater than the inter-

nal oscillator’s frequency, f , then current is sourced

OSC

continuously from the phase detector output, pulling up

the filter network. When the external clock frequency is

less than f_OSC, current is sunk continuously, pulling down

the filter network. If the external and internal frequencies

are the same but exhibit a phase difference, the current

sources turn on for an amount of time corresponding to

the phase difference. The voltage on the filter network is

adjusted until the phase and frequency of the internal and

external oscillators are identical. At the stable operating

point, the phase detector output is high impedance and

the filter capacitor holds the voltage.

Typically, the external clock (on the SYNC pin) input high

threshold is 2V, while the input low threshold is 1.1V. The

LTC7872 switching frequency is determined by:

ꢀ000

ꢀ00

0

Frequency = V

• 414kHz/V – 163.5kHz

FREQ

where, V

Or,

= I

(from spec table) • R

FREQ

Frequency = R

• 8.28kHz/kΩ– 163.5kHz

FREQ

This assumes a perfect 20μA I

.

FREQ

Shared Pin Connections in Multichip Applications

0

0.ꢀ

ꢀ

ꢀ.ꢁ

ꢀ

ꢀ.ꢁ

ꢀ

When multiple LTC7872 ICs are used together in high cur-

rent applications, the customer may or may not connect

certain pins together, balancing better communication

between the ICs versus avoiding a single point failure.

ꢀ

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ꢀꢁꢀꢂ ꢃ0ꢀ

Figure 7. Relationship Between Oscillator Frequency

and Voltage at the FREQ Pin

The CLKOUT pin allows multiple LTC7872s to be daisy

chained together. The clock output signal on the CLKOUT

pin can be used to synchronize additional ICs in a multi-

phase power supply solution feeding a single high current

output, or even several outputs from the same input supply.

ꢓ.ꢔꢒ ꢕꢒ

R

ꢋRꢉꢌ

ꢓ0ꢖꢄ

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The SS and PWMEN pins should be tied together to enable

every LTC7872 IC to start up together. Not connecting

them together may result in some phases sourcing a lot

of current and others sinking current.

ꢒꢏꢑ

ꢗꢘꢗꢓ ꢋ0ꢘ

The IMON pins may or may not be tied together, depend-

ing on whether the customer wants to monitor the

average current per IC or the total average current in

the application.

Figure 8. Phase-Locked Loop Block Diagram

Rev. 0

28

For more information www.analog.com

LTC7872

APPLICATIONS INFORMATION

The ILIM, SETCUR, FREQ, MODE, BUCK, and DRVSET

pins may or may not be tied together based on conve-

nience. When tying these pins together, please be aware

of the pull-up/down currents/resistors on these pins! Any

external resistor or resistor divider network must take

those into account. For example, each FREQ pin sources

20μA. When two LTC7872 ICs have their FREQ pins tied

together, that is 40μA.

If the duty cycle falls below what can be accommodated by

the minimum on-time, the controller will begin to skip cycles.

The output voltage and current will continue to be regulated,

but the voltage ripple and current ripple will increase. The

minimum on-time for the LTC7872 is approximately 150ns,

with good PCB layout, minimum 30% inductor current rip-

ple and at least 2mV ripple on the current sense signal or

+

–

equivalent 10mV between SNSA and SNS pins.

The OV_LOW, OV_HIGHand UV_HIGHpins of multiple LTC7872s

must be tied together. This enables the entire system to

react to an OV/UV condition appropriately. The resistor

divider used on these pins must be scaled based on the

number of LTC7872s paralleled, as these pins have 5μA

hysteresis currents that turn on and off.

The minimum on-time can be affected by PCB switch-

ing noise in the voltage and current loop. As the peak

sense voltage decreases, the minimum on-time gradu-

ally increases. This is of particular concern in forced

continuous applications with low ripple current at light

loads. If the duty cycle drops below the minimum on-

time limit in this situation, a significant amount of cycle

skipping can occur with correspondingly larger current

and voltage ripple.

The ITH_LOWand ITH_HIGHpins of multiple LTC7872s

should be tied together. Tying the ITH

pins together

LOW

and the ITH_HIGHpins together gives the best current shar-

ing between phases. Each error amplifier’s compensation

network must be placed local to the specific IC to mini-

mize jitter and stability issues.

Efficiency Considerations

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can

be expressed as:

The RUN pins must be tied together – this is very critical

for boost mode operation. In boost mode, when multiple

LTC7872 have their RUN pins connected together, care

must be taken to ensure that the logic signal on the RUN

pin is a clean fast rising/falling signal so all ICs are enabled

at the same instant. If a resistor divider is used on the

RUN pin, then the part must be started up in buck mode.

%Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percent-

age of input power.

Using a resistor divider on the RUN pin off V

, set for

HIGH

a start-up voltage higher than the UV_HIGHset point, allows

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of

the losses in LTC7872 circuits: 1) IC V_HIGHcurrent, 2)

MOSFET driver current, 3) I²R losses, 4) top MOSFET

transition losses.

the part to soft start cleanly after a UV

fault is cleared.

HIGH

Minimum On-Time Considerations

Minimum on-time, t , is the smallest time duration

ON(MIN)

that the LTC7872 is capable of turning on the top MOSFET.

It is determined by internal timing delays, power stage

timing delays and the gate charge required to turn on the

top MOSFET. Low duty cycle applications may approach

this minimum on-time limit and care should be taken to

ensure that:

1. The V

current is the DC supply current given in the

Electr^Hic^Ia^Gl^HCharacteristics table. V

current typically

HIGH

results in a small (<0.1%) loss.

2. The MOSFET driver current results from switching the

gate capacitance of the power MOSFETs. Each time

a MOSFET gate is switched from low to high to low

V

LOW

t

<

ON(MIN)

again, a packet of charge d moves from the driver

Q

V

f

( )

HIGH

supply to ground. The resulting d_Q/d_tis a current

Rev. 0

29

For more information www.analog.com

LTC7872

APPLICATIONS INFORMATION

out of the driver supply that is typically much larger

than the control circuit current. In continuous mode,

Checking Transient Response

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

I

= f(Q + Q ), where Q and Q are the gate

T B T B

GATECHG

charges of the top and bottom MOSFETs.

2

3. I R losses are predicted from the DC resistances of

load current. When a load step occurs, V

shifts by an

LOW

the fuse (if used), MOSFETs, inductor and current

sense resistor. In continuous mode, the average output

current flows through L and R_SENSE, but is chopped

between the top MOSFET and the bottom MOSFET.

If the two MOSFETs have approximately the same

amount equal to ∆I

• ESR, where ESR is the effective

LOAD

series resistance of C_OUTat V_LOW. ∆I_LOADalso begins to

charge or discharge C generating the feedback error sig-

OUT

nal that forces the regulator to adapt to the current change

and return V_LOWto its steady-state value. During this recov-

R

, then the resistance of one MOSFET can sim-

ery time V

can be monitored for excessive overshoot

DS(ON)

ply be summed with the resistances of L and R_SENSEto

or ringing,^Lw^OWhich would indicate a stability problem. The

availability of the ITH pin not only allows optimization of

control loop behavior but also provides a DC-coupled and

AC-filtered closed-loop response test point. The DC step,

rise time and settling at this test point truly reflects the

closed-loop response. Assuming a predominantly second

order system, phase margin and/or damping factor can be

estimated using the percentage of overshoot seen at this

pin. The bandwidth can also be estimated by examining the

rise time at the pin. The ITH external components shown in

the Typical Application circuit will provide an adequate start-

ing point for most applications. The ITH series RC-CC filter

sets the dominant pole-zero loop compensation. The values

can be modified slightly (from 0.5 to 2 times their suggested

values) to optimize transient response once the final PC

layout is done and the particular output capacitor type and

value have been determined. The output capacitors need to

be selected because the various types and values determine

the loop gain and phase. An output current pulse of 20% to

80% of full-load current having a rise time of 1μs to 10μs

will produce output voltage and ITH pin waveforms that will

give a sense of the overall loop stability without breaking

the feedback loop. Placing a power MOSFET directly across

the output capacitor and driving the gate with an appropri-

ate signal generator is a practical way to produce a realistic

load step condition. The initial output voltage step resulting

from the step change in output current may not be within

the bandwidth of the feedback loop, so this signal cannot be

used to determine phase margin. This is why it is better to

look at the ITH pin signal which is in the feedback loop and

is the filtered and compensated control loop response. The

gain of the loop will be increased by increasing RC and the

obtain I²R losses. For example, if each R_DS(ON)=10mΩ,

R = 10mΩ, R

L

= 5mΩ, then the total resistance

SENSE

is 25mΩ. This results in losses ranging from 0.6% to

3% as the output current increases from 3A to 15A for

a 12V output in buck mode.

Efficiency varies as the inverse square of V

for the

LOW

same external components and output power level. The

combined effects of increasingly lower output voltages

and higher currents required by high performance digi-

tal systems is not doubling but quadrupling the impor-

tance of loss terms in the switching regulator system!

4. Transition losses apply only to the top MOSFET(s), and

become significant only when operating at high V

HIGH

voltages (typically 15V or greater). Transition losses

can be estimated from:

2

Transition Loss = (1.7) V

• I

• C

• f

HIGH

O(MAX)

RSS

I

= Maximum Load on V

LOW

O(MAX)

Other hidden losses such as copper trace and internal

battery resistances can account for an additional 5% to

10% efficiency degradation in portable systems. It is very

important to include these system level losses during the

design phase. The internal battery and fuse resistance

losses can be minimized by making sure that C

has

HIGH

adequate charge storage and very low ESR at the switch-

ing frequency. Other losses including Schottky conduc-

tion losses during dead time and inductor core losses

generally account for less than 2% total additional loss.

Rev. 0

30

For more information www.analog.com

LTC7872

APPLICATIONS INFORMATION

bandwidth of the loop will be increased by decreasing CC.

If RC is increased by the same factor that CC is decreased,

the zero frequency will be kept the same, thereby keeping

the phase shift the same in the most critical frequency range

of the feedback loop. The output voltage settling behavior

is related to the stability of the closed-loop system and will

demonstrate the actual overall supply performance. A sec-

ond, more severe transient is caused by switching in loads

with large (>1μF) supply bypass capacitors. The discharged

Communication Sequence

The serial bus is comprised of CSB, SCLK, SDI and SDO.

Data transfers to the part are accomplished by the serial

bus master device first taking CSB low to enable the

LTC7872’s port. Input data applied on SDI is clocked on

the rising edge of SCLK, with all transfers MSB first. The

communication burst is terminated by the serial bus mas-

ter returning CSB high. See Figure 9 for details.

Data is read from the part during a communication burst

using SDO. Readback may be multidrop (more than one

LTC7872 connected in parallel on the serial bus), as SDO

is high impedance (Hi-Z) when CSB = 1, or when data is

not being read from the part. If the LTC7872 is not used

in a multidrop configuration, or if the serial port mas-

ter is not capable of setting the SDO line level between

read sequences, it is recommended to attach a resistor

between SDO and V5 to ensure the line returns to V5 dur-

ing Hi-Z states. The resistor value should be large enough

to ensure that the SDO output current does not exceed

10mA. See Figure 10 for details.

bypass capacitors are effectively put in parallel with C

,

LOW

causing a rapid drop in V_LOW. No regulator can alter its

delivery of current quickly enough to prevent this sudden

step change in output voltage if the load switch resistance

is low and it is driven quickly. If the ratio of C

to C

is

LOAD

OUT

greater than 1:50, the switch rise time should be controlled

so that the load rise time is limited to approximately 25 •

C

. Thus a 10μF capacitor would require a 250μs rise

LOAD

time, limiting the charging current to about 200mA.

SERIAL PORT

The SPI-compatible serial port provides control and moni

toring functionality.

-

ꢀꢁꢂꢃꢄRꢅꢆꢂꢇ

ꢊ

ꢆꢂꢂ

ꢊ

ꢆꢉꢈ

ꢆꢉꢋ

ꢆꢂꢋ

ꢀꢁꢂꢃꢄRꢅꢂꢆꢈꢉ

ꢊ

ꢆꢋ

ꢆꢂ

ꢀꢁꢂꢃꢄRꢅꢂꢌꢒ

ꢌꢁꢃꢁ

ꢍꢎꢍꢏ ꢐ0ꢑ

Figure 9. Serial Port Write Timing Diagram

ꢀꢁꢂꢃꢄRꢅꢆꢂꢇ

ꢀꢁꢂꢃꢄRꢅꢂꢆꢈꢉ

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ꢋꢃꢑ ꢆꢈꢎꢆꢉ

ꢒ

ꢍꢎ

ꢒ

ꢍꢎ

ꢍꢁꢃꢁ

ꢊꢋꢊꢌ ꢏꢐ0

Figure 10. Serial Port Read Timing Diagram

Rev. 0

31

For more information www.analog.com

LTC7872

APPLICATIONS INFORMATION

Single Byte Transfers

to the part. The second byte, is data from/to the specified

register address. The third byte, is the PEC (packet error

code) byte. See Figure 11 for an example of a detailed

write sequence, and Figure 12 for a read sequence. All

bytes shift with MSB first.

The serial port is arranged as a simple memory map, with

status and control available in 5 read/write and 6 read only

byte-wide registers. All data bursts are comprised of at

least three bytes. The 7 most significant bits (MSB) of the

first byte are the register address, with an LSB of 1 indi-

cating a read from the part, and LSB of 0 indicating a write

Figure 13 shows an example of two write communica-

tion bursts. The first byte of the first burst sent from the

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ꢀꢁꢂꢃꢄRꢅꢂꢆꢇꢈ

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ꢀ ꢁꢂꢃꢄ ꢅꢆ ꢇꢈꢉ

ꢀꢁꢂꢃꢄRꢅꢂꢆꢇ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀ0 0 ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀ0 ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀ0

0 ꢀ ꢁRꢂꢃꢄ

7872 F11

ꢀꢁꢂꢃꢄꢃꢅꢆꢇꢈꢉ

Figure 11. Serial Port Write Sequence

ꢀꢁꢂꢃꢄRꢅꢆꢂꢇ

ꢀꢁꢂꢃꢄRꢅꢂꢆꢇꢈ

ꢀꢁ ꢂꢃꢄꢂꢅꢆ

ꢀꢁꢂꢃꢄ RꢅꢆꢃꢇꢄꢅR ꢈꢉꢉRꢅꢇꢇ

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ꢀ ꢁꢂꢃꢄ ꢅꢆ ꢇꢈꢉ

ꢀ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀ0 ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀ0

ꢀꢁꢂꢃꢄꢃꢅꢆꢇꢈꢉ

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Figure 12. Serial Port Read Sequence

ꢀꢁꢂꢃꢄRꢅꢆꢂꢇ

ꢀꢁꢂꢃꢄRꢅꢂꢈꢉ

ꢁꢈꢈR0ꢓꢔR

ꢈꢁꢃꢁ0

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ꢁꢈꢈRꢐꢓꢔR

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Figure 13. Two Write Communication Bursts

Rev. 0

32

For more information www.analog.com

LTC7872

APPLICATIONS INFORMATION

serial bus master on SDI contains the destination register

address (ADDR0) and a following 0 indicating a write.

The next byte is the DATA0 intended for the register at

address ADDR0. The third byte is the PEC0. CSB is then

taken high to terminate the transfer. The first byte of the

second burst contains the destination register address

(ADDR1) and a following 0 indicating a write. The next

byte on SDI is the DATA1 intended for the register at

address ADDR1. The third byte is the PEC1. CSB is then

taken high to terminate the transfer. Note that the written

data is transferred to the internal register at the falling

edge of the 24th clock cycle (parallel load) in each burst

after the PEC is checked as valid.

3. Update the 8-bit PEC as PEC[7] = PEC[6],

PEC[6] = PEC[5],……PEC[3] = PEC[2], PEC[2] = IN2,

PEC[1] = IN1, PEC[0] = IN0.

4. Go back to step 2 until all data are shifted. The 8-bit

result is the final PEC byte.

An example to calculate the PEC is listed in Table 6 and

Figure 14. The PEC of the 1 byte data 0x01 is computed

as 0xC7 after the last bit of the byte clocked in.

For the serial port write sequence, the master calculates

the PEC byte for the address byte and data byte it sends

out. The master latches the PEC byte it calculates at the

15th clock falling edge and attaches the calculated PEC

byte following the data byte it shifts out. The LTC7872

also calculates PEC byte for the address byte and data

byte it receives. The LTC7872 latches the PEC byte it cal-

culates at the 16th clock rising edge and compares it with

the PEC byte following the data byte. The data is regarded

as valid only if the PEC bytes match.

PEC Byte

The PEC byte a cyclic redundancy check (CRC) value cal-

culated for all the bits in a register group in the order they

are passed, using the initial PEC value of 01000001 (0x41)

and the following characteristic polynomial:

8

2

For the serial port read sequence, the LTC7872 calculates

PEC byte for the received address byte and data byte it

sends out. The LTC7872 latches the PEC byte at the 15th

clock falling edge and attaches the calculated PEC byte

following the data byte it shifts out. The master calculates

PEC byte for the address byte it sends and data byte it

receives. The master latches the PEC byte at the 16th

clock rising edge and compares it with the PEC byte fol-

lowing the data byte it receivers. The data is regarded as

valid only if the PEC bytes match.

x + x + x + 1

To calculate the 8-bit PEC value, a simple procedure can

be established:

1. Initialize the PEC to 0100 0001.

2. For each bit DIN coming into the register group, set

IN0 = DIN XOR PEC[7], then IN1=PEC[0] XOR IN0,

IN2 = PEC[1] XOR IN0.

Table 6. Procedure to Calculate PEC Byte

CLOCK

CYCLE

DIN

IN0

IN1

IN2

0

PEC[7]

PEC[6]

PEC[5]

PEC[4]

PEC[3]

PEC[2]

PEC[1]

PEC[0]

0

1

2

3

4

5

6

7

8

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Rev. 0

33

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LTC7872

APPLICATIONS INFORMATION

Rev. 0

34

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LTC7872

APPLICATIONS INFORMATION

Multidrop Configuration

Several LTC7872s may share the serial bus. In this multidrop configuration, SCLK, SDI, and SDO are common between

all parts. The serial bus master must use a separate CSB for each LTC7872 and ensure that only one device has CSB

asserted at any time during the serial port read sequence. It is recommended to attach a high value resistor to SDO to

ensure the line returns to a known level during Hi-Z states.

Serial Port Register Definition

Table 7. Register Summary

Register

Address

(7 bits)

DEFAULT

VALUE

Register NAME

MFR_FAULT

Description

TYPE

R

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

One byte summary of the unit’s fault condition.

One byte summary of the unit’s overcurrent fault condition.

One byte summary of the unit’s negative overcurrent fault condition.

One byte summary of the unit’s operation status.

One byte summary of the unit’s configuration

[3] = Communication Fault, [1] = Sticky Bit, [0] = Write Protection

MFR_OC_FAULT

MFR_NOC_FAULT

MFR_STATUS

R

MFR_CONFIG1

MFR_CONFIG2

MFR_CHIP_CTRL

MFR_IDAC_VLOW

MFR_IDAC_VHIGH

MFR_IDAC_SETCUR

MFR_SSFM

R

R/W

0x00

Adjust the IDAC_VLOW to program V

voltage.

LOW

Adjust the IDAC_VHIGH to program V

HIGH

Adjust the IDAC_SETCUR to program SETCUR pin’s sourcing current.

Adjust the spread spectrum frequency modulation parameters.

RESERVED

0x0C

0x0D

0x0E

0x0F

SERIAL PORT REGISTER DETAILS

MFR_FAULT

The MFR_FAULT returns a one-byte summary of the most critical faults.

MFR_FAULT Register Contents:

BIT

7

NAME

VALUE MEANING

Reserved

6

VLOW_OV

VHIGH_OV

VHIGH_UV

DRVCC_UV

V5_UV

1

The OV

The UV

pin is higher than 1.2V threshold.

pin is less than 1.2V threshold.

LOW

HIGH

5

4

3

The DRV pin is undervoltage.

CC

2

The V5 pin is undervoltage.

1

VREF_BAD

OVER_TEMP

The internal reference self-check fails.

An over temperature fault has occurred.

0

Rev. 0

35

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LTC7872

APPLICATIONS INFORMATION

MFR_OC_FAULT

The MFR_OC_FAULT returns a one-byte summary of overcurrent fault condition. When the voltage difference between

+

–

SNSD and SNS pins is larger than the overcurrent fault threshold programmed by the ILIM pin, the corresponding

register bit will become 1.

MFR_OC_FAULT Register Contents:

BIT

7:6

5

NAME

VALUE MEANING

Reserved

OC_FAULT_4

OC_FAULT_3

1

Channel 4 overcurrent fault has occurred.

4

Channel 3 overcurrent fault has occurred.

Reserved

3

2

Reserved

1

OC_FAULT_2

OC_FAULT_1

1

Channel 2 overcurrent fault has occurred.

Channel 1 overcurrent fault has occurred.

0

MFR_NOC_FAULT

The MFR_NOC_FAULT returns a one-byte summary of negative overcurrent fault condition. When the voltage difference

+

–

between SNSD and SNS pins is less than the negative overcurrent fault threshold programmed by the ILIM pin, the

corresponding register bit will become 1.

MFR_NOC_FAULT Register Contents:

BIT

7:6

5

NAME

VALUE MEANING

Reserved

NOC_FAULT_4

NOC_FAULT_3

1

Channel 4 negative overcurrent fault has occurred.

4

Channel 3 negative overcurrent fault has occurred.

Reserved

3

2

Reserved

1

NOC_FAULT_2

NOC_FAULT_1

1

Channel 2 negative overcurrent fault has occurred.

Channel 1 negative overcurrent fault has occurred.

0

MFR_STATUS

The MFR_STATUS returns a one-byte summary of the operation status. The content of the MFR_STATUS register is

read only.

MFR_STATUS Register Contents:

BIT

7:3

2

NAME

VALUE MEANING

Reserved

SS_DONE

1

The soft-start is finished.

The maximum current programmed by the ILIM pin is reached.

The regulated V /V is within 10% regulation windows.

1

MAX_CURRENT

PGOOD

0

LOW HIGH

Rev. 0

36

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LTC7872

APPLICATIONS INFORMATION

MFR_CONFIG1

The MFR_CONFIG1 returns a one-byte summary of the

configuration of the controller programmed by the pins.

The content of the MFR_CONFIG1 register is read only.

MFR_CONFIG1 Register Contents:

BIT

7:6

5

NAME

VALUE MEANING

Reserved

SERCUR_WARNING

DRVCC_SET[1:0]

1

The SETCUR pin is programmed to be above 1.25V.

4:3

00

01

10

The DRV is programmed to 5V.

CC

The DRV is programmed to 8V.

CC

The DRV is programmed to 10V.

CC

2:0

ILIM_SET[2:0]

000

001

010

011

100

The maximum current sense threshold is programmed to 10mV.

The maximum current sense threshold is programmed to 20mV.

The maximum current sense threshold is programmed to 30mV.

The maximum current sense threshold is programmed to 40mV.

The maximum current sense threshold is programmed to 50mV.

MFR_CONFIG2

The MFR_CONFIG2 returns a one-byte summary of the

configuration of the controller programmed by the pins.

The content of the MFR_CONFIG2 register is read only.

MFR_CONFIG2 Register Contents:

BIT

7:5

4

NAME

VALUE MEANING

Reserved

BURST

DCM

1

The controller is in burst mode operation.

3

The controller is in DCM.

2

HIZ

The controller is in Hi-Z mode.

The controller is in spread spectrum mode.

1

SPRD

0

BUCK_BOOST

0

1

The controller is in boost mode.

The controller is in buck mode.

MFR_CHIP_CTRL

The MFR_CHIP_CTRL is for general chip control.

MFR_CHIP_CTRL Message Contents:

BIT

7:3

2

NAME

VALUE MEANING

Reserved

CML

RESET

WP

1

A communication fault related to PEC during writing registers has occurred. Write 1 to this bit will clear the CML.

Sticky bit, reset all R/W registers.

1

0

1

Write allowed for all three IDAC registers, and MFR_SSFM register.

Write inhibited for all three IDAC registers, and MFR_SSFM register.

Rev. 0

37

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LTC7872

APPLICATIONS INFORMATION

MFR_IDAC_VLOW

The MFR_IDAC_VLOW stores the current DAC value to program the V

voltage by injecting the current DAC output

LOW

to the VFB

pin. It is formatted as a 7-bit two’s complement value. Setting BIT[6] = 0 means sourcing current from

LOW

the VFB

pin; and BIT[6] = 1 means sinking current. The detail is listed in Table 8. The DAC current is only injected

LOW

to the VFB

pin in buck mode. Sinking current will cause V

to rise. The default value for this register is 0x00.

LOW

Writes to this register are inhibited when the WP, BIT[0] in MFR_CHIP_CTRL, is set high.

MFR_IDAC_VLOW Message Contents:

BIT

7

VALUE

MEANING

Reserved

6

0

1

0µA

–64µA

5

4

3

2

1

0

1

0µA

32µA

0

1

0µA

16µA

0

1

0µA

8µA

0

1

0µA

4µA

0

1

0µA

2µA

0

1

0µA

1µA

MFR_IDAC_VHIGH

The MFR_IDAC_VHIGH stores the current DAC value to program the V

voltage by injecting the current DAC output

HIGH

to the VFB

pin. It is formatted as a 7-bit two’s complement value. Setting BIT[6] = 0 means sourcing current from

HIGH

the VFB

pin; and BIT[6] = 1 means sinking current. The detail is listed in Table 8. The DAC current is only injected

HIGH

to the VFB

pin in boost mode. Sinking current will cause V

to rise in boost mode. The default value for this

HIGH

register is 0x00. Writes to this register are inhibited when the WP, BIT[0] in MFR_CHIP_CTRL, is set high.

MFR_IDAC_VHIGH Message Contents:

BIT

7

VALUE

MEANING

Reserved

6

0

1

0µA

–64µA

5

4

3

2

1

0

1

0µA

32µA

0

1

0µA

16µA

0

1

0µA

8µA

0

1

0µA

4µA

0

1

0µA

2µA

0

1

0µA

1µA

Rev. 0

38

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LTC7872

APPLICATIONS INFORMATION

MFR_IDAC_SETCUR

The MFR_IDAC_SETCUR stores the current DAC value to program the sourcing current of the SETCUR pin. It is for-

matted as a 5-bit two’s complement value. The default value for this register is 0x00 and the SETCUR pin originally

sources 16µA. This register can program the SETCUR pin sourcing current from 0 to 31µA as shown in the Table 9.

Writes to this register are inhibited when the WP, BIT[0] in MFR_CHIP_CTRL, is set high.

MFR_IDAC_SETCUR Message Contents:

BIT

7:5

4

VALUE

MEANING

RESERVED

0

1

16µA

0µA

3

2

1

0

1

0µA

8µA

0

1

0µA

4µA

0

1

0µA

2µA

0

1

0µA

1µA

MFR_SSFM

The MFR_SSFM is for spread spectrum frequency modulation control. The default value for this register is 0x00. Writes

to this register are inhibited when the WP, BIT[0] in MFR_CHIP_CTRL, is set high.

MFR_SSFM Message Contents:

BIT

7:5

4:3

NAME

VALUE MEANING

Reserved

Frequency Spread

Range

00

01

12%

15%

10

10%

11

8%

2:0

Modulation Signal

Frequency

000

001

010

011

100

101

110

111

Controller Switching Frequency/512

Controller Switching Frequency/1024

Controller Switching Frequency/2048

Controller Switching Frequency/4096

Controller Switching Frequency/256

Controller Switching Frequency/128

Controller Switching Frequency/64

Controller Switching Frequency/512

Rev. 0

39

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LTC7872

APPLICATIONS INFORMATION

Table 8. VFB_LOW/VFB_HIGHPIN Current and Corresponding DAC Codes

MFR_IDAC_V /MFR_IDAC_V

LOW HIGH

LOW

HIGH

[6]

1

[5]

0

[4]

0

1

[3]

[2]

0

1

0

1

0

1

0

1

[1]

[0]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

I

(µA)

[6]

1

[5]

1

[4]

0

1

[3]

[2]

0

1

0

1

0

1

0

1

[1]

[0]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

I

(µA)

VFBLOW/VFBHIGH

0

–64

0

–32

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

–63

–62

–61

–60

–59

–58

–57

–56

–55

–54

–53

–52

–51

–50

–49

–48

–47

–46

–45

–44

–43

–42

–41

–40

–39

–38

–37

–36

–35

–34

–33

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

–31

–30

–29

–28

–27

–26

–25

–24

–23

–22

–21

–20

–19

–18

–17

–16

–15

–14

–13

–12

–11

–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

Rev. 0

40

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LTC7872

APPLICATIONS INFORMATION

Table 8. VFB_LOW/VFB_HIGHPIN Current and Corresponding DAC Codes

MFR_IDAC_V

/MFR_IDAC_V

MFR_IDAC_V /MFR_IDAC_V

LOW HIGH

LOW

HIGH

[6]

0

[5]

0

[4]

0

1

[3]

[2]

0

1

0

1

0

1

0

1

[1]

[0]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

I

(µA)

[6]

0

[5]

1

[4]

0

1

[3]

[2]

0

1

0

1

0

1

0

1

[1]

[0]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

I

(µA)

VFBLOW/VFBHIGH

0

32

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Rev. 0

41

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LTC7872

APPLICATIONS INFORMATION

Table 9. SETCUR Pin Current and Corresponding DAC Codes

MFR_IDAC_SETCUR[4:0]

Table 9. SETCUR Pin Current and Corresponding DAC Codes

MFR_IDAC_SETCUR[4:0]

[4]

1

[3]

0

1

[2]

0

1

0

1

[1]

0

1

0

1

0

1

0

1

[0]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

I

(µA)

[4]

0

[3]

0

1

[2]

0

1

0

1

[1]

0

1

0

1

0

1

0

1

[0]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

I

(µA)

SETCUR

0

16

1

2

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

3

4

5

6

7

8

9

10

11

12

13

14

15

Rev. 0

42

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LTC7872

APPLICATIONS INFORMATION

PC Board Layout Checklist

6. Keep the switching nodes away from sensitive small-

+

–

signal nodes (SNSD , SNSA , SNS , V ). Ideally the

FB

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the IC. These items are also illustrated graphically in the

layout diagram of Figure 15. Check the following in the

PC layout:

switch nodes printed circuit traces should be routed

away and separated from the IC and especially the

quiet side of the IC. Separate the high dV/dt traces

from sensitive small-signal nodes with ground traces

or ground planes.

1. The DRV bypass capacitor should be placed imme-

CC

7. Use a low impedance source such as a logic gate to

drive the SYNC pin and keep the PCB trace as short

as possible.

diately adjacent to the IC between the DRV pin and

CC

the GND plane. A 1μF ceramic capacitor of the X7R or

X5R type is small enough to fit very close to the IC. An

additional 4.7μF to 10μF of ceramic, tantalum or other

very low ESR capacitance is recommended in order to

keep the internal IC supply quiet.

8. The ceramic capacitors between each ITH pin and sig-

nal ground should be placed as close as possible to

the IC. Figure 15 illustrates all branch currents in a

switching regulator. It becomes very clear after study-

ing the current waveforms why it is critical to keep

the high switching current paths to a small physical

size. High electric and magnetic fields will radiate from

these loops just as radio stations transmit signals. The

2. The V5 bypass capacitor should be placed immediately

adjacent to the IC between the V5 and the SGND pins.

A 4.7μF to 10μF capacitor of ceramic, tantalum or other

very low ESR capacitance is recommended.

3. Place the feedback divider between the + and– terminals

C

ground should return to the negative terminal of

and not share a common ground path with any

LOW

HIGH

of C

/C

. Route VFB

/VFB

with minimum

HIGH

PC t^Lr^Oac^We s^Hp^Ia^Gc^Hing from the^LI^OC^Wto the feedback dividers.

switched current paths. The left half of the circuit gives

rise to the noise generated by a switching regulator.

The ground terminations of the bottom MOSFET and

Schottky diode should return to the bottom plate(s) of

+

–

4. Are the SNSA , SNSD and SNS printed circuit traces

routed together with minimum PC trace spacing? The

filter capacitors between SNSA^+,SNSD⁺and SNS^–

should be as close as possible to the pins of the IC.

the V

capacitor(s) with a short isolated PC trace

HIGH

since very high switched currents are present. External

OPTI-LOOP^®compensation allows overcompensation

for PC layouts which are not optimized, but this is not

the recommended design procedure.

5. Do the (+) plates of C

decoupling cap connect to

the drain of the topsi^Hd^Ie^GHMOSFET as closely as pos-

sible? This capacitor provides the pulsed current to

the MOSFET.

ꢅꢊ

ꢄ

ꢅꢆꢇ

ꢁꢂꢃꢁ

ꢋꢇꢌ

R

ꢋꢍꢎꢋꢍ

R

ꢁꢂꢃꢁ

ꢀ

R

ꢅꢆꢇ

ꢈ

ꢉꢊ

ꢈ

ꢅꢆꢇ

ꢋꢇꢊ

ꢁꢂꢃꢁ

ꢏꢐꢏꢌ ꢑꢊꢒ

ꢓꢆꢅꢉ ꢅꢂꢎꢍꢋ ꢂꢎꢉꢂꢈꢔꢕꢍ ꢁꢂꢃꢁꢖ ꢋꢇꢂꢕꢈꢁꢂꢎꢃ ꢈꢗRRꢍꢎꢕꢋ. ꢘꢍꢍꢙ ꢅꢂꢎꢍꢋ ꢕꢆ ꢔ ꢚꢂꢎꢂꢚꢗꢚ ꢅꢍꢎꢃꢕꢁ

Figure 15. Branch Current Waveforms (Buck Mode Shown)

Rev. 0

43

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LTC7872

APPLICATIONS INFORMATION

Special Layout Consideration

(30A/phase), and f = 150kHz. The regulated output voltage

is determined by:

Exceeding Absolute Max ratings on the EXTV pin can

CC

result in damage to the controller. As the EXTV pin is

V = 1.2V • (1 + R /R ).

LOW B A

CC

normally connected to V

, it is recommended to put

LOW

Using a 10k 1% resistor from the VFB

node to ground,

the top feedback resistor is (to the n^Le^Oa^Wrest 1% standard

a Schottky diode with an appropriately high voltage rat-

ing between the V and the EXTV pins as shown in

LOW

CC

value) 90.9k. The frequency is set by selecting the R

FREQ

Figure 16(a). Choose the right Schottky diode with the

forward voltage less than 0.5V at the maximum EXTV

pin current.

to be 37.4kΩ. The inductance values are based on a 35%

maximum ripple current assumption (10.5A for each

phase). The highest value of ripple current occurs at the

CC

Another method to protect on the EXTV pin is to use a

maximum V

voltage:

CC

HIGH

Schottky diode to clamp the EXTV pin to reduce volt-

CC

V_LOW

f•∆I

V_LOW

⎛

⎞

age spiking below ground. The Schottky diode should be

placed close to the controller IC, with the cathode con-

nected to the EXTV_CCpin and the anode connected to

ground as shown in the Figure 16(b). Choose a minimum

1Ω R_FLTRand keep the maximum voltage drop across the

L =

• 1–

⎜

⎟

V_{HIGH MAX}

⎝

⎠

(

)

(

)

L MAX

Each phase will require 6.1μH. The Sagami CVE2622C-

6R8M, 6.8μH, 1.8mΩ DCR inductor is chosen. At the

nominal V

voltage (48V), the ripple current will be:

HIGH

R

FLTR

less than 0.5V.

V_LOW

f•L

V_LOW

⎛

⎞

∆I

=

• 1–

(

)

L NOM

⎜

⎟

ꢀꢁꢂꢃꢄꢃꢅ

V_{HIGH NOM}

⎝

⎠

(

)

ꢀ

ꢀꢁꢂꢃ

ꢀꢁꢂ

ꢀꢀ

Each phase will have 8.8A (29.3%) ripple. The peak induc-

tor current will be the maximum DC value plus one-half the

ripple current, or 34.4A. The minimum on-time occurs at

1μF

the maximum V

, and should not be less than 150ns:

HIGH

(a)

V_LOW

12V

T_{ON MIN}

=

)

=

=1.33µs

(

V_{HIGH MAX}₎•f 60V •150kHz

(

ꢀꢁꢂꢃꢄꢃꢅ

R

ꢀꢁꢂR

With V

= 3/4 V , the equivalent R

resistor value

ꢀ

ꢀꢁꢂꢃ

ꢀꢀ

ILIM

can be calculated^Vb⁵y using the mini^Sm^ENu^Sm^Evalue for the

ꢀꢁꢂ

1μF

maximum current sense threshold (45mV):

ꢀꢁꢀꢂ ꢃꢄꢅ

V_{SENSE MIN}

(

)

R_{SENSE EQUIV}

=

)

(

∆I_{L NOM}

I_{LOAD MAX}

(

)

(

)

+

#OF PHASES

2

(b)

The equivalent required R

value is 1.31mΩ. Choose

SENSE

Figure 16. Methods to Protect the EXTV_CCPin

R_S= 1mΩ to allow some design margin. As shown in

Figure 17, set R2 to be below 1/10th of the R1. Therefore,

Design Example

+

the DC component of the SNSA filter is small enough to

be omitted. R1 • C1 should have a bandwidth that is four

As a design example for a four-phase single output

times as high as the L/R .

high current regulator, assume V

= 48V (nominal),

S

HIGH

V_HIGH= 60V (maximum), V_LOW= 12V, I_VLOW(MAX)= 120A

Rev. 0

44

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LTC7872

APPLICATIONS INFORMATION

Typically, C1 is selected in the range of 0.047μF to 0.47μF.

48V –12V

48V

⎧

⎪

⎨

⎪

⎩

⎫

⎪

•15A²

If C1 is chosen to be 0.1μF, R1 and R2 will be 16.9kΩ

P_SYNC

=

•2

+

⎬

and 1.69kΩ respectively. The bias current at SNSD and

⎪

⎭

+

(

)

SNSA is about 50nA, and it causes some small error to

• (1+0.005• 75°C–25°C )•5.2mΩ

[

]

the current sense signal. If C2 is also chosen to be 0.1μF,

R3 will be 1.5kΩ.

{

}

= 1.1W •2

R3

1.5k

= 2.2W

+

SNSD

C2

LTC7872

C

is chosen for an equivalent RMS current rating of

0.1µF

HIGH

at least 20A. C

–

SNS

is chosen with an equivalent ESR of

C1

0.1µF

LOW

R1

R2

1.69k

16.9k

10mΩ for low output ripple. The V

output ripple in

L

R

S

1mΩ

+

LOW

SNSA

6.8µH

continuous mode will be highest at the maximum V

7872 F17

SW

V

LOW

HIGH

+

voltage. The V_LOWoutput voltage ripple due to ESR

is approximately:

V

= R • ∆I = 0.01Ω • 8.8A = 88mV

ESR L

LOWRIPPLE

Figure 17. R_SENSEResistor Sensing in Design Example

Further reductions in V

output voltage ripple can be

LOW

made by placing ceramic capacitors across C

.

The power dissipation on the top MOSFET can be eas-

LOW

ily estimated. Set the gate drive voltage (DRV ) to be

CC

If the output load is a battery, the voltage loop is first set

for the desired output voltage and then the charge current

can be regulated using the current regulation loop—via

the SETCUR and IMON pins. Selecting a maximum charge

current of 80A, the desired SETCUR pin voltage is calcu-

lated using:

10V. Choosing two Infineon BSC117N08NS5 MOSFETs

results in:

R

V

= 11.7mΩ (max),

DS(ON)

MILLER

= 5V, C

≅ 19pF.

MILLER

At typical V

voltage with T (estimated) = 75°C:

J

HIGH

K •I_{L MAX}₎•R

(

SENSE

12V

48V

⎧

⎫

⎪

V_SETCUR

=

•15A²

4

⎪

20•80A •1mΩ

=

(

)

• (1+0.005• 75°C–25°C )•11.7mΩ

[

]

4

⎪

= 400mV

P_MAIN

=

•2

⎨

⎪

⎬

⎪

15A

2

+48V²•

•4Ω•19pF

The SETCUR pin can be driven by an ADC’s output to

400mV for the best accuracy. If one is not available, the

16μA current sourced out of the SETCUR pin can be used

to set the voltage with a resistor from SETCUR to ground,

calculated using:

1

⎞

⎛

•

+

•150k

⎟

⎜

⎝

⎠

⎪

⎩

⎪

⎭

10−5 5

{

}

= 823mW+79mW •2

400mV

16µA

=1804mW

R_SETCUR

=

= 25k

Two Infineon BSC052N08NS5 MOSFETs, R_DS(ON)

=

A 1% or more accurate 30.1k resistor can be chosen to

allow some design margin. The 16μA current out of the

SETCUR pin can be programmed by the SPI interface so

the maximum charge current can be changed on-the-fly.

5.2mΩ, C = 370pF are chosen for the bottom MOSFET.

OSS

The resulting power loss is:

Rev. 0

45

For more information www.analog.com

LTC7872

TYPICAL APPLICATIONS

Rev. 0

46

For more information www.analog.com

LTC7872

PACKAGE DESCRIPTION

LXE Package

48-Lead Plastic Exposed Pad LQFP (7mm × 7mm)

ꢢReꢩeꢪeꢫꢬe ꢀꢜꢗ ꢋꢤꢘ ꢭ0ꢐꢧ0ꢄꢧꢈꢄꢏꢔ Rev ꢋꢣ

ꢎ.ꢈꢐ ꢍ ꢎ.ꢔꢐ

ꢐ.ꢐ0 Rꢂꢆ

ꢃꢄ

ꢈ

ꢏꢎ

ꢏꢉ

0.ꢐ0 ꢕꢖꢗ

ꢗ0.ꢏ0

ꢐ.ꢐ0 Rꢂꢆ

ꢎ.ꢈꢐ ꢍ ꢎ.ꢔꢐ

0.ꢔ0 ꢍ 0.ꢏ0

ꢏ.ꢉ0 0.0ꢐ

e ꢏ

ꢈꢔ

ꢔꢐ

ꢔꢃ

ꢇꢒꢗꢟꢒꢘꢂ ꢛꢙꢜꢀꢞꢚꢂ

ꢈꢏ

ꢗꢛꢑꢇꢛꢚꢂꢚꢜ

ꢇꢞꢚ ꢯꢒꢈꢰ

ꢈ.ꢏ0 ꢑꢞꢚ

ꢜRꢒꢥ ꢇꢞꢚ ꢈ

ꢕꢂꢊꢂꢀ

Rꢂꢗꢛꢑꢑꢂꢚꢋꢂꢋ ꢖꢛꢀꢋꢂR ꢇꢒꢋ ꢀꢒꢥꢛꢙꢜ

ꢒꢇꢇꢀꢥ ꢖꢛꢀꢋꢂR ꢑꢒꢖꢟ ꢜꢛ ꢒRꢂꢒꢖ ꢜꢠꢒꢜ ꢒRꢂ ꢚꢛꢜ ꢖꢛꢀꢋꢂRꢂꢋ

ꢇꢒꢗꢟꢒꢘꢂ ꢞꢚ ꢜRꢒꢥ ꢀꢛꢒꢋꢞꢚꢘ ꢛRꢞꢂꢚꢜꢒꢜꢞꢛꢚ

ꢓ.00 ꢕꢖꢗ

ꢎ.00 ꢕꢖꢗ

ꢏ.ꢉ0 0.ꢈ0

ꢃꢄ

ꢏꢎ

ꢃꢄ

ꢖꢂꢂ ꢚꢛꢜꢂꢝ ꢏ

ꢈ

ꢏꢉ

ꢈ

ꢗ0.ꢏ0

ꢓ.00 ꢕꢖꢗ

ꢎ.00 ꢕꢖꢗ

ꢏ.ꢉ0 0.ꢈ0

ꢒ

ꢔꢐ

ꢈꢔ

ꢔꢐ

ꢗ0.ꢏ0 ꢍ 0.ꢐ0

ꢔꢃ

ꢈꢏ

ꢔꢃ

ꢕꢛꢜꢜꢛꢑ ꢛꢆ ꢇꢒꢗꢟꢒꢘꢂꢨꢂꢁꢇꢛꢖꢂꢋ ꢇꢒꢋ ꢢꢖꢠꢒꢋꢂꢋ ꢒRꢂꢒꢣ

ꢈ.ꢉ0

ꢈꢈꢌ ꢍ ꢈꢏꢌ

ꢈ.ꢏꢐ ꢍ ꢈ.ꢃꢐ ꢑꢒꢁ

R0.0ꢄ ꢍ 0.ꢔ0

ꢘꢒꢙꢘꢂ ꢇꢀꢒꢚꢂ

0.ꢔꢐ

0ꢌ ꢍ ꢎꢌ

ꢀꢁꢂꢃꢄ ꢀꢅꢆꢇ 0ꢃꢈꢉ Rꢂꢊ ꢋ

ꢈꢈꢌ ꢍ ꢈꢏꢌ

ꢈ.00 Rꢂꢆ

0.ꢐ0

ꢕꢖꢗ

0.0ꢓ ꢍ 0.ꢔ0

0.ꢈꢎ ꢍ 0.ꢔꢎ

ꢖꢞꢋꢂ ꢊꢞꢂꢤ

0.0ꢐ ꢍ 0.ꢈꢐ

0.ꢃꢐ ꢍ 0.ꢎꢐ

ꢖꢂꢗꢜꢞꢛꢚ ꢒ ꢍ ꢒ

ꢚꢛꢜꢂꢝ

ꢈ. ꢋꢞꢑꢂꢚꢖꢞꢛꢚꢖ ꢒRꢂ ꢞꢚ ꢑꢞꢀꢀꢞꢑꢂꢜꢂRꢖ

ꢏ. ꢇꢞꢚꢧꢈ ꢞꢚꢋꢂꢚꢜꢞꢆꢞꢂR ꢞꢖ ꢒ ꢑꢛꢀꢋꢂꢋ ꢞꢚꢋꢂꢚꢜꢒꢜꢞꢛꢚꢦ 0.ꢐ0ꢡꢡ ꢋꢞꢒꢑꢂꢜꢂR

ꢃ. ꢋRꢒꢤꢞꢚꢘ ꢞꢖ ꢚꢛꢜ ꢜꢛ ꢖꢗꢒꢀꢂ

ꢔ. ꢋꢞꢑꢂꢚꢖꢞꢛꢚꢖ ꢛꢆ ꢇꢒꢗꢟꢒꢘꢂ ꢋꢛ ꢚꢛꢜ ꢞꢚꢗꢀꢙꢋꢂ ꢑꢛꢀꢋ ꢆꢀꢒꢖꢠ. ꢑꢛꢀꢋ ꢆꢀꢒꢖꢠ

ꢖꢠꢒꢀꢀ ꢚꢛꢜ ꢂꢁꢗꢂꢂꢋ 0.ꢔꢐꢡꢡ ꢢꢈ0 ꢑꢞꢀꢖꢣ ꢕꢂꢜꢤꢂꢂꢚ ꢜꢠꢂ ꢀꢂꢒꢋꢖ ꢒꢚꢋ ꢛꢚ ꢒꢚꢥ

ꢖꢞꢋꢂ ꢛꢆ ꢂꢁꢇꢛꢖꢂꢋ ꢇꢒꢋꢦ ꢑꢒꢁ 0.ꢐ0ꢡꢡ ꢢꢔ0 ꢑꢞꢀꢖꢣ ꢒꢜ ꢗꢛRꢚꢂR ꢛꢆ ꢂꢁꢇꢛꢖꢂꢋ

ꢇꢒꢋꢦ ꢞꢆ ꢇRꢂꢖꢂꢚꢜ

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications

47

subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

For more information www.analog.com

LTC7872

TYPICAL APPLICATION

High Efficiency 4-Phase 24V/60A Bidirectional Supply

V

5

10k

30.1k

V

36V TO ^H7^I0^GV^H

2.2µF

×12

ILIM

VFB

OV

EXTV

LOW

3.01M 2.2Ω

10k

267k

10k

OV

UV

VFB

CC

HIGH

499k

ZHCS400

2mΩ

+

V

HIGH

1µF

33µF

×12

191k

210k

V

48.7k

1µF

HIGH

15µH

12.7k 10k

47pF

V

2^L4^OV^W/60A

PWM1

DRIVER

LTC7060

22µF

×4

18.7k

1.69k

0.1µF

1nF

0.1µF

+

LTC7872

33µF

×4

0.1µF

0.33µF

499Ω 499Ω

1.87k

+

–

ITH

IMON

SS

SNSA1

SNSD1

SNS1

HIGH

LOW

PINS NOT USED

IN THIS CIRCUIT:

CLKOUT

(PHASE 2 TO PHASE 3)

DRVSET

SETCUR

DRVCC

V5

MODE

V

HIGH

45.3k

V

5

RUN

FAULT

51k

100pF

0.1µF

4.7µF

2mΩ

15µH

18.7k

PWMEN

PGOOD

PWM4

DRIVER

LTC7060

37.4k

FREQ

SGND

1.69k

0.1µF

V

5

BUCK BOOST

BUCK

SCLK

SDI

SDO

CSB

1.87k

1k

+

SNSA4

SPI

INTERFACE

+

SNSD4

–

SNS4

7872 TA03

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LTC7871

Six-Phase, Synchronous Bidirectional Buck or Boost Up to 100V for V

, Up to 60V V , PLL Fixed Frequency 60kHz to 750kHz,

HIGH LOW

Controller

64-Lead LQFP

LTC7060

LT8228

100V Half Bridge Gate Driver with Floating Grounds Up to 100V Supply Voltage, 6V ≤ V ≤ 14V, Adaptive Shoot-Through

CC

and Programmable Dead-Time

Protection, 2mm × 3mm LFCSP and 12-Lead MSOP

Bidirectional Buck or Boost Controller with Fault

Protection

Up to 100V for V , and V , Ideal for 48V/12V Automotive Battery

HIGH LOW

Applications

LT8708/LT8708-1 80V Synchronous 4-Switch Buck-Boost DC/DC

Controller with Flexible Bidirectional Capability

2.8V ≤ V ≤ 80V, 1.3V ≤ V

≤ 80V, PLL Fixed Frequency 100kHz to 400kHz,

IN

OUT

5mm × 8mm QFN-40

LTC3871

LTC4449

LTC3779

LTC7813

LTC3899

LTM^®8056

LTC7103

Bidirectional PolyPhase Synchronous Buck or

Boost Controller

Up to 100V V

, Up to 30V V

, PLL Fixed Frequency 60kHz to 460kHz,

LOW

HIGH

48-Lead LQFP

High Speed Synchronous N-Channel MOSFET Driver Up to 38V Supply Voltage, 4V ≤ V ≤ 6.5V, Adaptive Shoot-Through

CC

Protection, 2mm × 3mm DFN-8

150V V and V

Synchronous 4-Switch

4.5V ≤ V ≤ 150V, 1.2V ≤ V

≤ 150V, PLL Fixed Frequency 50kHz to

IN

OUT

IN

OUT

Buck-Boost Controller

600kHz, FE38 TSSOP

60V Low I Synchronous Boost+Buck Controller,

4.5V (Down to 2.2V After Start-Up) ≤ V ≤ 60V, Boost V

Up to 60V, 0.8V ≤

Q

IN

OUT

Low EMI and Low Input/Output Ripple

Buck V ≤ 60V, I = 29µA, 5mm × 5mm QFN-32 Package

OUT Q

60V, Triple Output, Buck/Buck/Boost Synchronous

4.5V (Down to 2.2V after Start-Up) ≤ V ≤ 60V, V

Range: 0.8V to 60V, Boost V

Up to 60V, Buck V

OUT OUT

IN

Controller with 29µA Burst Mode I

Up to 60V

OUT

Q

58V , Buck-Boost µModule Regulator, Adjustable

5V ≤ V ≤ 58V, 1.2V ≤ V

≤ 48V, 15mm × 15mm × 4.92mm BGA Package

OUT

IN

Input and Output Current Limiting

105V, 2.3A, Low EMI Synchronous

Step-Down Regulator

4.4V ≤ V ≤ 105V, 1V ≤ V

≤ V , I = 2µA, Fixed Frequency 200kHz,

OUT IN Q

IN

5mm × 6mm QFN Package

Rev. 0

03/21

www.analog.com

48

 ANALOG DEVICES, INC. 2021

For more information www.analog.com


型号：	LTC7872
厂家：	ADI
描述：	Quad-Phase, Synchronous Bidirectional Buck or Boost Controller
文件：	总48页 (文件大小：2318K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC7872 [ADI]

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