LTM4671_技术文档

LTM4671

Quad DC/DC µModule Regulator with

Configurable Dual 12A, Dual 5A Output Array

FEATURES

DESCRIPTION

Quad Output Step-Down µModule^®Regulator with

Dual 12A and Dual 5A Output

n

ꢁhe LꢁM^®467± is a quad DC/DC step-down µModule

(micromodule) regulator offering dual ±2A and dual ꢀA

output. Included in the package are the switching control-

lers, power FEꢁs, inductors and support components.

Operating over an input voltage range of 3.±V to 20V, the

LꢁM467± supports an output voltage range of 0.6V to

3.3V for two ±2A channels and 0.6V to ꢀ.ꢀV for two ꢀA

channels, each set by a single external resistor. Only bulk

input and output capacitors are needed.

n

Wide Input Voltage Range: 3.1V to 20V

Dual 12A DC Output from 0.6V to 3.3V

Dual 5A DC Output from 0.6V to 5.5V

Up to 7W Power Dissipation (T = 60°C, 200LFM,

A

No Heat Sink)

n

±±.ꢀ5 ꢁotal Output Voltage Regulation

Dual Differential Sensing Amplifier

Current Mode Control, Fast ꢁransient Response

Parallelable for Higher Output Current

Selectable Burst Mode^®Operation

Output Voltage ꢁracking

Internal ꢁemperature Sensing Diode Output

External Frequency Synchronization

Overvoltage, Current and ꢁemperature Protection

9.ꢀmm × ±6mm × 4.72mm BGA Package

Fault protection features include overvoltage, overcurrent

and overtemperature protection. ꢁhe LꢁM467± is offered

in 9.ꢀmm × ±6mm × 4.72mm BGA package.

Configurable Output Array*

±2A

ꢀA

±2A

24A

±0A

24A

ꢀA

±0A

ꢀA

* Note 4

APPLICATIONS

All registered trademarks and trademarks are the property of their respective owners.

n

Multirail Point-of-Load Regulation

n

FPGAs, DSPs and ASICs Applications

TYPICAL APPLICATION

4V to 20V Input, 12A, 12A, 5A, 5A DC/DC Step-Down µModule Regulator

12V_INEfficiency vs Load Current

ꢀꢁꢁ

ꢀꢁ

V

OUT0

V

IN

OUT0

+

C

OUT0

C

22µF

×2

VOSNS0

5V TO 20V

1.2V/12A

IN

SV

IN0

IN3

–

100µF ×4

60.4k

19.1k

13.3k

FB0

RUN0

RUN1

RUN2

RUN3

V

OUT1

+

OUT1

VOSNS1

2.5V/5A

C

47µF

OUT1

FB1

COMP0a

COMP0b

LTM4671

V

OUT2

V

OUT2

+

COMP1

COMP2

VOSNS2

3.3V/5A

C

47µF

OUT2

ꢀ

ꢄ ꢅ.ꢆ

ꢄ ꢅ.ꢇ

ꢄ ꢇ.ꢈ

ꢄ ꢉ.ꢉ

FB2

ꢁꢂꢃ

COMP3a

COMP3b

V

OUT3

V

OUT3

+

C

VOSNS3

OUT3

TRACK/SS0

TRACK/SS1

TRACK/SS2

TRACK/SS3

1.0V/12A

–

100µF ×4

0.1μF

90.9k

ꢀ

ꢀꢁ

FB3

0.1μF

ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ

0.1μF

ꢀꢁꢂꢃ ꢄꢅꢆꢃꢇ

TMON GND

0.1μF

4671 TA01a

Rev. B

1

Document Feedback

For more information www.analog.com

LTM4671

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Note 1)

(See Pin Functions, Component BGA Pinout ꢁable)

V , SV , SV ........................................ –0.3V to 22V

IN

IN0

, V

IN3

ꢇꢈꢉ ꢊꢋꢌꢍ

V

............................................. –0.3V to 3.6V

OUꢁ0 OUꢁ3

ꢮ

ꢪ

ꢇꢧꢌꢙꢧꢌꢐ ꢇꢧꢌꢙꢧꢌꢐ

, V

................................................ –0.3V to 6V

ꢜ

B

ꢛ

ꢚ

ꢌ

OUꢁ± OUꢁ2

INꢁV , INꢁV

, INꢁV , ................... –0.3V to 3.6V

CC0

CC±2

CC3

FREQ0, FREQ±2, FREQ3,........................... –0.3V to 3.6V

FB0, FB±, FB2, FB3,................................... –0.3V to 3.6V

COMP0a, COMP0b, COMP3a, COMP3b,

COMP±, COMP2,................................... –0.3V to 3.6V

RUN0, RUN±, RUN2, RUN3........................ –0.3V to 22V

ꢁRACK/SS0, ꢁRACK/SS±, ꢁRACK/SS2,

ꢊ

ꢈꢘꢇꢐ

ꢊ

ꢋꢙ

ꢋꢙꢇꢊ

ꢉꢕꢑꢈꢚꢌꢐ

ꢧꢊ

ꢛꢒꢓꢈꢘꢇꢐ ꢉꢖꢈꢈꢚꢐ

ꢖꢙꢚ

ꢛꢛꢐ

ꢋꢙꢐ

ꢮ

ꢊꢈꢧꢙꢧꢐ ꢇRꢜꢛꢓꢦꢧꢧꢐ ꢗRꢌꢫꢐ Rꢘꢙꢐ

ꢗ

ꢁRACK/SS3, ......................................... –0.3V to 3.6V

PGOOD0, PGOOD±, PGOOD2, PGOOD3,... –0.3V to 3.6V

ꢑꢈꢚꢌꢦ

ꢖꢙꢚ

ꢪ

ꢗBꢐ

ꢖꢙꢚ ꢛꢒꢓꢋꢙꢐ

ꢊꢈꢧꢙꢧꢐ

ꢇRꢜꢛꢓꢦꢧꢧꢀ

ꢖ

ꢕ

ꢔ

+

–

+

VOSNS0 , VOSNS0 , VOSNS3 ,

ꢉꢖꢈꢈꢚꢀ

ꢗBꢀ

ꢛꢈꢑꢉꢐꢬ ꢛꢈꢑꢉꢐꢭ

–

VOSNS3 ,............................................. –0.3V to 3.6V

ꢊ

ꢈꢘꢇꢀ

ꢖꢙꢚ

Rꢘꢙꢀ

ꢇꢑꢈꢙ

ꢛꢈꢑꢉꢀ

ꢊꢈꢧꢙꢧꢀ

VOSNS±, VOSNS2........................................ –0.3V to 6V

ꢊ

ꢋꢙ

+

–

+

ꢁSENSE0 , ꢁSENSE0 , ꢁSENSE3 ,

ꢋꢙꢇꢊ

ꢗRꢌꢫꢀꢁ

ꢊꢈꢧꢙꢧꢁ

ꢖꢙꢚ

ꢛꢛꢀꢁ

ꢓ

ꢒ

ꢖꢙꢚ

–

ꢁSENSE3 ............................................. –0.3V to 0.8V

ꢑꢈꢚꢌꢦ

Rꢘꢙꢁ ꢛꢒꢓꢋꢙꢀꢁ

ꢖꢙꢚ

ꢁMON ....................................................... –0.3V to 3.6V

MODE/CLKIN0, CLKOUꢁ0, MODE/CLKIN3,

CLKOUꢁ3, MODE/CLKIN±2 ................... –0.3V to 3.6V

Operating Junction ꢁemperature (Note 2) –40°C to ±2ꢀ°C

Storage ꢁemperature Range .................. –ꢀꢀ°C to ±2ꢀ°C

Peak Solder Reflow Body ꢁemperature................. 24ꢀ°C

ꢊ

ꢋꢙ

ꢊ

ꢈꢘꢇꢁ

ꢉꢖꢈꢈꢚꢁ

ꢛꢈꢑꢉꢁ

ꢗBꢁ

ꢑ

ꢙ

ꢉ

R

ꢇ

ꢇRꢜꢛꢓꢦ

ꢪ

ꢧꢧꢁ ꢛꢈꢑꢉꢂꢭ ꢛꢈꢑꢉꢂꢬ

ꢗBꢂ ꢊꢈꢧꢙꢧꢂ

ꢇRꢜꢛꢓꢦ

ꢖꢙꢚ

ꢮ

ꢛꢒꢓꢈꢘꢇꢂ Rꢘꢙꢂ

ꢗRꢌꢫꢂ

ꢑꢈꢚꢌꢦ

ꢧꢧꢂ ꢊꢈꢧꢙꢧꢂ ꢖꢙꢚ

ꢋꢙꢇꢊ

ꢛꢛꢂ

ꢧꢊ

ꢉꢕꢑꢈꢚꢌꢂ ꢉꢖꢈꢈꢚꢂ ꢛꢒꢓꢋꢙꢂ

ꢋꢙꢂ

ꢊ

ꢋꢙ

ꢖꢙꢚ

ꢊ

ꢈꢘꢇꢂ

ꢘ

ꢊ

ꢍ

ꢖꢙꢚ

ꢪ

ꢮ

ꢖꢙꢚ

ꢇꢧꢌꢙꢧꢌꢂ ꢇꢧꢌꢙꢧꢌꢂ

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢆ

ꢎ

ꢏ

ꢀꢐ

ꢀꢀ

Bꢖꢜ ꢉꢜꢛꢓꢜꢖꢌ

ꢁꢐꢏꢝꢒꢌꢜꢚ ꢞꢏ.ꢄꢟꢟ ꢠ ꢀꢅꢟꢟ ꢠ ꢃ.ꢆꢁꢟꢟꢡ

ꢇ

ꢣ ꢀꢁꢄꢤꢛꢥ θ

ꢣ ꢀꢁ.ꢎꢤꢛꢦꢍꢥ θ ꢣ ꢀ.ꢄꢤꢛꢦꢍꢥ θ ꢣ ꢀꢁꢤꢛꢦꢍ

ꢔꢑꢜꢢ

ꢔꢛꢇꢈꢉ

ꢔꢛBꢈꢇꢇꢈꢑ ꢔꢜ

θ ꢊꢜꢒꢘꢌꢧ ꢚꢌꢇꢌRꢑꢋꢙꢌꢚ ꢉꢌR ꢔꢌꢧꢚꢄꢀꢝꢀꢁ

ꢍꢌꢋꢖꢕꢇꢨ ꢀ.ꢏꢃꢩ

Rev. B

2

For more information www.analog.com

LTM4671

ORDER INFORMATION

PART MARKING*

DEVICE FINISH CODE

LꢁM467±Y

PACKAGE

TYPE

MSL

TEMPERATURE RANGE

(SEE NOTE 2)

PART NUMBER

LꢁM467±EY#PBF

LꢁM467±IY#PBF

PAD OR BALL FINISH

RATING

SAC30ꢀ (RoHS)

e±

BGA

3

–40°C to ±2ꢀ°C

• Device temperature grade is indicated by a label on the shipping container.

• Pad or ball finish code is per IPC/JEDEC J-SꢁD-609.

• BGA Package and ꢁray Drawings

• ꢁhis product is not recommended for second side reflow.

ꢁhis product is moisture sensitive. For more information, go

to Recommended BGA PCB Assembly and Manufacturing

Procedures.

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified internal

operating temperature range. Specified as each individual output channel. T_A= 25°C (Note 2), SV_IN= V_IN= 12V, unless otherwise

noted. Per the typical application in Figure 30.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

Switching Regulator Section: (12A Channels)

l

V

Input DC Voltage

3.±

2.9

0.6

20

V

IN

Input DC Voltage After Start-Up

Output Voltage Range

IN(AFꢁER SꢁARꢁ-UP)

OUꢁ(RANGE)

OUꢁ(DC)

3.3

Output Voltage, ꢁotal Variation with

Line and Load

C

= 22µF, C

= ±00µF Ceramic

±.482 ±.ꢀ0 ±.ꢀ±8

IN

FB

OUꢁ

R

= 40.2k, Continuous Current Mode

SV = V = 3.±V to 20V, I = 0A to ±2A

OUꢁ

IN

I

Input Supply Bias Current

SV = V = ±2V, V = ±.ꢀV, Continuous Current Mode

OUꢁ

7ꢀ

70

mA

µA

Q(VIN)

IN

SV = V = ±2V, RUN = 0, Shutdown

IN

I

Input Supply Current

SV = V = ±2V, V

= ±.ꢀV, I = ±2A

OUꢁ

±.6

A

S(VIN)

IN

OUꢁ

Output Continuous Current Range

Line Regulation Accuracy

Load Regulation Accuracy

SV = V = ±2V, V

= ±.ꢀV (Note 4)

0

±2

OUꢁ(DC)

IN

OUꢁ

IN

l

∆V

/V

V

= ±.ꢀV, V = 3.±V to 20V, I = 0A

OUꢁ

0.00± 0.0ꢀ

5/V

OUꢁ(LINE) OUꢁ

IN

∆V

/V

= ±.ꢀV, I

= 0A to ±2A

0.2

0.ꢀ

5

OUꢁ(LOAD) OUꢁ

OUꢁ

V

Output Ripple Voltage

ꢁurn-On Overshoot

I

= 0A, C = ±00µF Ceramic

OUꢁ

6

mV

ms

mV

µs

OUꢁ(AC)

OUꢁ

IN

SV = V = ±2V, V

= ±.ꢀV

IN

OUꢁ

∆V

I

= 0A, C = ±00µF Ceramic,

OUꢁ

±ꢀ

±

OUꢁ(SꢁARꢁ)

OUꢁLS

OUꢁ

SV = V = ±2V, V = ±.ꢀV

OUꢁ

IN

t

ꢁurn-On ꢁime

ꢁRACK/SS = 0.0±µF,

SV = V = ±2V, V

SꢁARꢁ

= ±.ꢀV, C

= 3× ±00µF Ceramic

OUꢁ

IN

OUꢁ

∆V

Peak Deviation for Dynamic Load

Load: 05 to 2ꢀ5 to 05 of Full Load

SV = V = ±2V, V = ±.ꢀV, C

±ꢀ0

ꢀ0

IN

OUꢁ

t

Settling ꢁime for Dynamic Load Step Load: 05 to 2ꢀ5 to 05 of Full Load

SV = V = ±2V, V = ±.ꢀV, C

SEꢁꢁLE

IN

OUꢁ

I

Output Current Limit

Voltage at V Pin

SV = V = ±2V, V

= ±.ꢀV

±4

A

V

OUꢁPK

IN

OUꢁ

l

V

I

= 0A, V = ±.ꢀV

OUꢁ

0.ꢀ94

0.6

0.606

±ꢀ0

FB

OUꢁ

I

Current at V Pin

(Note 6)

nA

kΩ

FB

R

Resistor Between V

and V Pins

60.0ꢀ 60.40 60.7ꢀ

FB(ꢁOP)

OUꢁ

FB

Rev. B

3

For more information www.analog.com

LTM4671

The l denotes the specifications which apply over the specified internal

ELECTRICAL CHARACTERISTICS

operating temperature range. Specified as each individual output channel. T_A= 25°C (Note 2), SV_IN= V_IN= 12V, unless otherwise

noted. Per the typical application in Figure 30.

SYMBOL

PARAMETER

CONDITIONS

Rising

MIN

TYP

MAX UNITS

V

RUN

RUN Pin ON ꢁhreshold

V

±.±0

±.20

±ꢀ0

±.30

V

mV

RUN

Hysteresis

UVLO

Undervoltage Lockout

INꢁV Falling

2.4

2.ꢀꢀ

0.4

2.7

V

CC

Hysteresis

I

t

ꢁrack Pin Soft-Start Pull-Up Current ꢁRACK/SS = 0V

6

µA

ns

ꢁRACK/SS

ON(MIN)

OFF(MIN)

Minimum On-ꢁime

Minimum Off-ꢁime

PGOOD ꢁrip Level

(Note ꢀ)

2ꢀ

80

V

FB

With Respect to Set Output

PGOOD

V

Ramping Negative

Ramping Positive

–±0

6

–8

8

–6

±0

5

FB

V

R

PGOOD Pull-Down Resistance

±mA Load

8

±ꢀ

Ω

V

PGOOD

INꢁV

Internal V Voltage

3.2

±

3.3

600

3.4

CC

FREQ

Default Switching Frequency

kHz

CLKIN_H

CLKIN_H Input High ꢁhreshold

CLKIN_H Input Low ꢁhreshold

V

0.3

Switching Regulator Section: (5A Channels)

l

V

Input DC Voltage

3.±

2.9

0.6

20

V

IN

Input DC Voltage After Start-Up

Output Voltage Range

IN(AFꢁER SꢁARꢁ-UP)

OUꢁ(RANGE)

OUꢁ(DC)

ꢀ.ꢀ

Output Voltage, ꢁotal Variation with

Line and Load

C

= 22µF, C

= ±00µF Ceramic

±.477 ±.ꢀ0 ±.ꢀ23

IN

OUꢁ

R

= 40.2k, Continuous Current Mode

FB

IN

V

= 3.±V to 20V, I

= 0A to ꢀA

OUꢁ

I

)

Input Supply Bias Current

V

IN

V

IN

V

IN

= ±2V, V = ±.ꢀV, Continuous Current Mode

OUꢁ

±8

82

7ꢀ

mA

µA

Q(VIN

= ±2V, V

= ±.ꢀV, Burst Mode Operation (I

= 0.ꢀA

OUꢁ

= ±2V, RUN = 0V, Shutdown

I

Input Supply Current

V

= ±2V, V

= ±.ꢀV, I = ꢀA

OUꢁ

0.7

A

S(VIN)

IN

OUꢁ

Output Continuous Current Range

Line Regulation Accuracy

Load Regulation Accuracy

Output Ripple Voltage

= ±.ꢀV (Note 4)

0

ꢀ

OUꢁ(DC)

IN

l

∆V

/V

= ±.ꢀV, V = 3.±V to 20V, I = 0A

OUꢁ

0.00± 0.0ꢀ

5/V

5

OUꢁ(LINE) OUꢁ

OUꢁ

IN

/V

= ±.ꢀV, I

= 0A to ꢀA

0.2

8

0.ꢀ

OUꢁ(LOAD) OUꢁ

OUꢁ

V

I

= 0A, C

= ±00µF Ceramic

= ±.ꢀV

mV

OUꢁ(AC)

OUꢁ

V

IN

= ±2V, V

OUꢁ

∆V

ꢁurn-On Overshoot

I

= 0A, C

= ±00µF Ceramic,

= ±.ꢀV

±ꢀ

ꢀ

mV

ms

mV

µs

OUꢁ(SꢁARꢁ)

OUꢁLS

OUꢁ

IN

OUꢁ

V

= ±2V, V

OUꢁ

t

ꢁurn-On ꢁime

ꢁRACK/SS = 0.0±µF,

= ±2V, V = ±.ꢀV, C = ±00µF Ceramic

OUꢁ

SꢁARꢁ

V

IN

OUꢁ

∆V

Peak Deviation for Dynamic Load

Load: 05 to 2ꢀ5 to 05 of Full Load

= ±2V, V = ±.ꢀV, C = ±00µF Ceramic

30

70

V

IN

OUꢁ

t

I

Settling ꢁime for Dynamic Load Step Load: 05 to 2ꢀ5 to 05 of Full Load

SEꢁꢁLE

V

= ±2V, V

= ±.ꢀV, C = ±00µF Ceramic

OUꢁ

IN

OUꢁ

Output Current Limit

Voltage at V Pin

V

= ±2V, V

= ±.ꢀV

6

A

V

OUꢁPK

IN

l

V

I

= 0A, V

= ±.ꢀV

0.ꢀ92

0.6

0.608

±30

FB

OUꢁ

I

Current at V Pin

(Note 6)

nA

kΩ

FB

R

Resistor Between V

and V Pins

60.0ꢀ 60.40 60.7ꢀ

FB(ꢁOP)

RUN

OUꢁ

FB

V

RUN Pin ON ꢁhreshold

V

Rising

±.±ꢀ

±.2ꢀ

200

±.3ꢀ

V

mV

RUN

Hysteresis

Rev. B

4

For more information www.analog.com

LTM4671

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified internal

operating temperature range. Specified as each individual output channel. T_A= 25°C (Note 2), SV_IN= V_IN= 12V, unless otherwise

noted. Per the typical application in Figure 30.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

UVLO

Undervoltage Lockout

INꢁV Falling

2.2

2.4

0.ꢀ

2.6

V

CC

Hysteresis

I

t

ꢁrack Pin Soft-Start Pull-Up Current ꢁRACK/SS = 0V

±.4

20

4ꢀ

µA

ns

ꢁRACK/SS

ON(MIN)

OFF(MIN)

Minimum On-ꢁime

Minimum Off-ꢁime

PGOOD ꢁrip Level

(Note ꢀ)

V

FB

with Respect to Set Output

PGOOD

V

Ramping Negative

Ramping Positive

–±0

ꢀ

–8

8

–ꢀ

±0

5

FB

V

R

PGOOD Pull-Down Resistance

±0mA Load

2ꢀ

3.3

±

Ω

V

PGOOD

INꢁV

Internal V Voltage

3.±

±

3.ꢀ

0.3

CC

FREQ

Default Switching Frequency

MHz

MODE/CLKIN_L

MODE/CLKIN_L High ꢁhreshold

MODE/CLKIN_L Low ꢁhreshold

V

ꢁMON±2

ꢁemperature Monitor

ꢁemperature Monitor Slop

ꢁ = 2ꢀ°C

A

±.ꢀ

200

V

°C/V

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 3: ꢁhe minimum on-time is tested at wafer sort.

Note 4: See output current derating curves for different V , V

Note 5: Guaranteed by design.

and ꢁ .

IN OUꢁ

A

Note 6: ±005 tested at wafer level.

Note 2: ꢁhe LꢁM467± is tested under pulsed load conditions such

that ꢁ ≈ ꢁ . ꢁhe LꢁM467±E is guaranteed to meet performance

J

A

specifications over the 0°C to ±2ꢀ°C internal operating temperature

range. Specifications over the full –40°C to ±2ꢀ°C internal operating

temperature range are assured by design, characterization and correlation

with statistical process controls. ꢁhe LꢁM467±I is guaranteed to meet

specifications over the full –40°C to ±2ꢀ°C internal operating temperature

range. Note that the maximum ambient temperature consistent with

these specifications is determined by specific operating conditions in

conjunction with board layout, the rated package thermal resistance and

other environmental factors.

Rev. B

5

For more information www.analog.com

LTM4671

TYPICAL PERFORMANCE CHARACTERISTICS

Dual 12A Channels

Efficiency vs Load Current

from 3.3V_IN

Efficiency vs Load Current

from 5V_IN

Efficiency vs Load Current

from 12V_IN

ꢀꢁꢁ

ꢀꢁ

ꢀꢁꢁ

ꢀꢁ

ꢀꢁꢁ

ꢀꢁ

ꢀ

ꢄ ꢅ.ꢆꢀ

ꢄ ꢅ.ꢅꢀ

ꢀ

ꢄ ꢅ.ꢆꢀ

ꢄ ꢅ.ꢅꢀ

ꢁꢂꢃ

ꢀ

ꢄ ꢅ.ꢆꢀ

ꢁꢂꢃ

ꢀ

ꢁꢂꢃ

ꢀ

ꢁꢂꢃ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ

ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ

ꢀꢁꢂꢃ ꢄꢅꢆ

ꢀꢁꢂꢃ ꢄꢅꢃ

1.0V Output Transient Response

1.2V Output Transient Response

1.5V Output Transient Response

V

OUT

(AC-COUPLED)

50mV/DIV

OUT

(AC-COUPLED)

50mV/DIV

(AC-COUPLED)

50mV/DIV

LOAD STEP

2A/DIV

LOAD STEP

2A/DIV

LOAD STEP

2A/DIV

4671 G05

4671 G04

4671 G06

50μs/DIV

V

C

= 12V, V

OUT

= 1.2V, f = 600kHz

SW

V

C

= 12V, V

OUT

= 1V, f = 600kHz

SW

V

C

= 12V, V

OUT

EXT COMP, C = 2200pF, R = 5k, C = 33pF

TH FF

= 1.5V, f = 600kHz

SW

IN

OUT

= 3× 100μF CERAMIC CAPACITORS

IN

OUT

= 3× 100μF CERAMIC CAPACITORS

IN

= 3× 100μF CERAMIC CAPACITORS

EXT COMP, C = 2200pF, R = 5k, C = 33pF

TH

FF

TH

FF

TH

3A (25%) LOAD STEP, 1A/μs

1.8V Output Transient Response

2.5V Output Transient Response

3.3V Output Transient Response

V

OUT

(AC-COUPLED)

100mV/DIV

(AC-COUPLED)

50mV/DIV

(AC-COUPLED)

50mV/DIV

LOAD STEP

2A/DIV

LOAD STEP

2A/DIV

LOAD STEP

2A/DIV

4671 G09

4671 G08

4671 G07

50μs/DIV

V

C

= 12V, V

OUT

= 3.3V, f = 600kHz

SW

V

C

= 12V, V

OUT

= 2.5V, f = 600kHz

SW

V

C

= 12V, V

OUT

= 1.8V, f = 600kHz

SW

IN

OUT

= 3× 100μF CERAMIC CAPACITORS

IN

OUT

= 3× 100μF CERAMIC CAPACITORS

EXT COMP, C = 2200pF, R = 5k, C = 33pF

TH

FF

TH

FF

TH

FF

3A (25%) LOAD STEP, 1A/μs

Rev. B

6

For more information www.analog.com

LTM4671

TYPICAL PERFORMANCE CHARACTERISTICS

Dual 12A Channels

Start-Up Waveform with No Load

Current Applied

Start-Up Waveform with 12A Load

Current Applied

Short-Circuit Waveform with No

Load Current Exist

RUN

10V/DIV

RUN

10V/DIV

L

IN

PGOOD

5V/DIV

PGOOD

5V/DIV

500mA/DIV

L

IN

200mA/DIV

IN

200mA/DIV

V

OUT

500mV/DIV

V

OUT

1V/DIV

OUT

1V/DIV

4671 G10

4671 G11

2ms/DIV

4671 G12

50μs/DIV

V

C

= 12V, V

OUT

= 1V, f = 600kHz

SW

V

C

= 12V, V = 1V, f = 600kHz

OUT

IN

SW

= 1× 330μF POSCAP,

V

C

= 12V, V

OUT

2× 100μF CERAMIC CAPACITORS

= 1V, f = 600kHz

OUT SW

= 1× 330μF POSCAP,

IN

OUT

= 1× 330μF POSCAP,

2× 100μF CERAMIC CAPACITORS

C

= 0.1μF

C

= 0.1μF

SS

Short-Circuit Waveform with 12A

Load Current Exist

Output Ripple

Start Into Pre-Biased Output

RUN

10V/DIV

PGOOD

5V/DIV

L

IN

500mA/DIV

V

OUT

(AC-COUPLED)

10mV/DIV

V

OUT

1V/DIV

V

OUT

500mV/DIV

L

IN

100mA/DIV

4671 G15

2ms/DIV

4671 G14

4671 G13

1μs/DIV

= 1V, f = 600kHz

50μs/DIV

V

C

= 12V, V

OUT

= 1.5V, f = 600kHz

IN

OUT SW

V

C

= 12V, V

OUT

V

C

= 12V, V

OUT

2× 100μF CERAMIC CAPACITORS

= 1V, f = 600kHz

OUT SW

IN

SW

IN

= 1× 330μF POSCAP +

= 3× 100μF CERAMIC CAPACITORS

= 1× 330μF POSCAP,

2× 100μF CERAMIC CAPACITORS

V

= PREBIASED TO 0.9V

OUT

Dual 5A Channels

Efficiency vs Load Current

from 3.3V_IN

Efficiency vs Load Current

from 5V_IN

Efficiency vs Load Current

from 12V_IN

ꢀꢁꢁ

ꢀꢁ

ꢀꢁꢁ

ꢀꢁ

ꢀꢁꢁ

ꢀꢁ

ꢀ

ꢁꢂꢃ

ꢀ

ꢁꢂꢃ

ꢀ

ꢁꢂꢃ

ꢀ

ꢁꢂꢃ

ꢀ

ꢁꢂꢃ

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ꢁꢂꢃ

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ꢄ ꢆ.ꢇꢀ

ꢄ ꢈ.ꢉꢀ

ꢄ ꢈ.ꢇꢀ

ꢄ ꢈ.ꢆꢀ

ꢄ ꢈ.ꢊꢀ

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ꢁꢂꢃ

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ꢁꢂꢃ

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ꢄ ꢅ.ꢆꢀ

ꢄ ꢇ.ꢈꢀ

ꢄ ꢇ.ꢆꢀ

ꢄ ꢇ.ꢅꢀ

ꢄ ꢇ.ꢉꢀ

ꢀ

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ꢄ ꢅ.ꢆꢀ

ꢄ ꢇ.ꢇꢀ

ꢄ ꢈ.ꢅꢀ

ꢄ ꢉ.ꢊꢀ

ꢀ

ꢁꢂꢃ

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ꢄ ꢉ.ꢅꢀ

ꢄ ꢉ.ꢈꢀ

ꢄ ꢉ.ꢆꢀ

ꢀ

ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ

ꢀꢁꢂꢃ ꢄꢃꢅ

ꢀꢁꢂꢃ ꢄꢃꢂ

ꢀꢁꢂꢃ ꢄꢃꢁ

Rev. B

7

For more information www.analog.com

LTM4671

TYPICAL PERFORMANCE CHARACTERISTICS

1.0V Output Transient Response

1.2V Output Transient Response

1.5V Output Transient Response

V

OUT

(AC-COUPLED)

50mV/DIV

OUT

(AC-COUPLED)

50mV/DIV

(AC-COUPLED)

50mV/DIV

LOAD STEP

500mA/DIV

LOAD STEP

500mA/DIV

LOAD STEP

500mA/DIV

4671 G21

4671 G19

4671 G20

50μs/DIV

V

C

= 12V, V

OUT

= 100pF

= 1.5V, f = 1MHz

SW

V

C

= 12V, V

OUT

= 100pF

= 1V, f = 1MHz

SW

V

C

= 12V, V

OUT

= 100pF

FF

= 1.2V, f = 1MHz

SW

IN

OUT

= 2× 47μF + 10μF CERAMIC CAPACITORS

IN

= 2× 47μF + 10μF CERAMIC CAPACITORS

FF

1.25A (25%) LOAD STEP, 1A/μs

1.8V Output Transient Response

2.5V Output Transient Response

3.3V Output Transient Response

V

OUT

(AC-COUPLED)

100mV/DIV

(AC-COUPLED)

50mV/DIV

(AC-COUPLED)

50mV/DIV

LOAD STEP

500A/DIV

LOAD STEP

500mA/DIV

LOAD STEP

500A/DIV

4671 G24

4671 G22

4671 G23

50μs/DIV

V

C

= 12V, V

OUT

= 100pF

= 3.3V, f = 1MHz

SW

V

C

= 12V, V

OUT

= 100pF

= 1.8V, f = 1MHz

SW

V

C

= 12V, V

OUT

= 100pF

FF

= 2.5V, f = 1MHz

SW

IN

OUT

= 2× 47μF + 10μF CERAMIC CAPACITORS

IN

OUT

= 2× 47μF + 10μF CERAMIC CAPACITORS

FF

1.25A (25%) LOAD STEP, 1A/μs

Start-Up Waveform with No Load

Current Applied

Start-Up Waveform with 5A Load

Current Applied

5V Output Transient Response

RUN

10V/DIV

RUN

10V/DIV

V

OUT

PGOOD

5V/DIV

PGOOD

5V/DIV

(AC-COUPLED)

100mV/DIV

V

OUT

V

OUT

1V/DIV

LOAD STEP

500A/DIV

L

IN

200mA/DIV

4671 G26

4671 G27

4671 G25

20ms/DIV

50μs/DIV

V

C

= 12V, V

OUT

= 100pF, C = 0.1μF

FF

SS

= 1V, f = 1MHz

SW

V

C

= 12V, V

OUT

= 100pF, C = 0.1μF

SS

= 1V, f = 1MHz

SW

V

C

= 12V, V

OUT

= 100pF

= 1.8V, f = 1MHz

SW

IN

OUT

= 2× 47μF + 10μF CERAMIC CAPACITORS

IN

OUT

= 2× 47μF + 10μF CERAMIC CAPACITORS

IN

= 2× 47μF + 10μF CERAMIC CAPACITORS

FF

1.25A (25%) LOAD STEP, 1A/μs

Rev. B

8

For more information www.analog.com

LTM4671

TYPICAL PERFORMANCE CHARACTERISTICS

Short-Circuit Waveform with No

Load Current Exist

Short-Circuit Waveform with 5A

Load Current Exist

L

IN

500mA/DIV

L

IN

500mA/DIV

V

OUT

V

OUT

500mV/DIV

4671 G28

4671 G29

50μs/DIV

V

C

= 12V, V

OUT

= 100pF

= 1V, f = 1MHz

OUT SW

V

C

= 12V, V

OUT

= 100pF

= 1V, f = 1MHz

OUT SW

IN

= 2× 47μF + 10μF CERAMIC CAPACITORS

FF

Output Ripple

Start Into Pre-Biased Output

RUN

10V/DIV

PGOOD

5V/DIV

L

IN

V

OUT

5mV/DIV

2V/DIV

L

IN

100mA/DIV

4671 G31

4671 G30

2ms/DIV

500ns/DIV

= 1V, f = 1MHz

V

C

= 12V, V

OUT

= 3.3V, f = 1MHz

OUT SW

V

C

= 12V, V

OUT

= 100pF

IN

OUT

SW

= 2× 47μF + 10μF CERAMIC CAPACITORS

= 100pF, V PREBIASED 2V

OUT

FF

Rev. B

9

For more information www.analog.com

LTM4671

PIN FUNCTIONS

PACKAGE ROW AND COLUMN LABELING MAY VARY

RUN0 (F11), RUN3 (P7): Run Control Input of Each 12A

Switching Mode Regulator Channel. Enable regulator

operation by tying the specific RUN pin above 1.2V. Tying

it below 1.1V shuts down the specific regulator channel.

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE

LAYOUT CAREFULLY.

V (D7-D11, E8, H6, J5-J6, L5-L6, M6, R10, T7-T11):

IN

Power Input. Pins connect to the drain of the internal top

COMP0a (H10), COMP3a (N9): Current Control Thresh-

old and Error Amplifier Compensation Point of Each 12A

Switching Mode Regulator Channel. The internal current

comparatorthresholdislinearlyproportionaltothisvoltage.

Tie the COMPa pins from different channels together for

parallel operation. The device is internally compensated.

Connect to COMP0b or COMP3b, respectively, to use the

internal compensation. Or connect to a Type-II C-R-C

network to use customized compensation.

MOSFET and Signal V to the internal 3.3V regulator for

IN

the control circuitry for each switching mode regulator

channel.ApplyinputvoltagesbetweenthesepinsandGND

pins. Recommend placing input decoupling capacitance

directly between each of V pins and GND pins.

IN

GND (A4-A5, A8-A11, B4-B11, C4-C11, D4-D6, E3-E5,

F1-F7, G1-G6, G10, H5, H7, J7, J9, K1-K7, K11, L7,

L11, M5, M7, M10, N1-N6, P1-P5, P11, R3-R5, T4-T6,

U4-U11, V4-V11, W4-W5, W8-W11):PowerGroundPins

for Both Input and Output Returns. Use large PCB copper

areas to connect all GND together.

COMP0b (H11), COMP3b (N8): Internal Loop Compen-

sation Network for Each 12A Switching Mode Regulator

Channel. Connect to COMP0a or COMP3a, respectively, to

use the internal compensation in majority of applications.

PINS FOR DUAL 12A CHANNELS:

FB0 (G9), FB3 (N10): The Negative Input of the Error

V

OUT0

(A1-A3, B1-B3, C1-C3, D1-D3, E1-E2), V

OUT3

AmplifierforEach12ASwitchingModeRegulatorChannel.

+

(R1-R2, T1-T3, U1-U3, V1-V3, W1-W3): Power Output

Pins of Each 12A Switching Mode Regulator Channel.

Apply output load between these pins and GND pins. Rec-

ommend placing output decoupling capacitance directly

between these pins and GND pins. See the Applications

Information section for paralleling outputs.

This pin is internally connected to VOSNS0 or VOSNS3 ,

respectively, with a 60.4kΩ precision resistor. Output

voltages can be programmed with an additional resistor

–

between FB and VOSNS pins. In PolyPhase^®operation,

tying the FB pins together allows for parallel operation.

See the Applications Information section for details.

PGOOD0 (E11), PGOOD3 (R7): Output Power Good with

Open-Drain Logic of Each 12A Switching Mode Regulator

Channel. PGOOD is pulled to ground when the voltage on

theFBpinisnotwithin±10%oftheinternal0.6Vreference.

TRACK/SS0 (F9), TRACK/SS3 (P9): Output Tracking and

Soft-Start Pin of Each 12A Switching Mode Regulator

Channel. Allows the user to control the rise time of the

output voltage. Putting a voltage below 0.6V on this pin

bypasses the internal reference input to the error ampli-

fier, instead it servos the FB pin to the TRACK voltage.

Above 0.6V, the tracking function stops and the internal

reference resumes control of the error amplifier. There’s

INTV

(E7), INTV

(R11): Internal 3.3V Regulator

CC0

CC3

Output of Each 12A Switching Mode Regulator Channel.

The internal power drivers and control circuits are pow-

ered from this voltage. Decouple each pin to GND with a

minimum of 2.2µF local low ESR ceramic capacitor.

an internal 6µA pull-up current from INTV on this pin,

CC

so putting a capacitor here provides soft-start function.

See the Applications Information section for details.

Rev. B

10

For more information www.analog.com

LTM4671

PIN FUNCTIONS

+

FREQ0(F10),FREQ3(P8):SwitchingFrequencyProgram

Pin of Each 12A Switching Mode Regulator Channel. Fre-

quencyissetinternallyto600kHz. Anexternalresistorcan

be placed from this pin to GND to increase frequency, or

TSENSE0 (A7), TSENSE3 (W6): Temperature Monitor

of Each 12A Switching Mode Regulator Channel. An in-

ternal diode connected PNP transistor is placed between

+

–

TSENSE and TSENSE pins. See the Applications Infor-

mation section.

from this pin to INTV to reduce frequency. See the Ap-

CC

plications Information section for frequency adjustment.

–

TSENSE0 (A6), TSENSE3 (W7):LowSideoftheInternal

+

VOSNS0 (G8), VOSNS3 (N11): Positive Input to the Dif-

ferential Remote Sense Amplifier of Each 12A Switching

Mode Regulator Channel. Internally, this pin is connected

Temperature Monitor.

SV (E9), SV (R9): Signal V . Filtered input voltage

IN0

IN3

IN

to the on-chip 3.3V regulator. Tie this pin to the V pin in

IN

to V with a 60.4k 0.5% precision resistor. See the Ap-

plications Information section for details.

FB

most applications or connect SV to an external voltage

IN

supplyofatleast4VwhichmustalsobegreaterthanV

.

OUT

–

VOSNS0 (F8), VOSNS3 (P10): Negative Input to the

Differential Remote Sense Amplifier of Each 12A Switch-

ing Mode Regulator Channel. Connect an external resistor

PINS FOR DUAL 5A CHANNELS:

–

V

OUT1

(H1-H4, J1-J4), V

(L1-L4, M1-M4): Power

OUT2

between FB and VOSNS pin to set the output voltage of

OutputPinsofEach5ASwitchingModeRegulatorChannel.

Apply output load between these pins and GND pins. Rec-

ommend placing output decoupling capacitance directly

between these pins and GND pins. See the Applications

Information section for paralleling outputs.

the specific channel. See the Applications Information

section for details.

MODE/CLKIN0 (G11), MODE/CLKIN3 (R8): Discontinu-

ous Mode Select Pin and External Synchronization Input

to Phase Detector of Each 12A Switching Mode Regula-

tor Channel. Tie MODE/CLKIN to GND for discontinuous

mode of operation. Floating MODE/CLKIN or tying it to

a voltage above 1V will select forced continuous mode.

Furthermore,connectingMODE/CLKINtoanexternalclock

willsynchronizethesystemclocktotheexternalclockand

puts the part in forced continuous mode. See Applications

Information section for details.

PGOOD1 (H8), PGOOD2 (M8): Output Power Good with

Open-Drain Logic of Each 5A Switching Mode Regulator

Channel. PGOOD is pulled to ground when the voltage on

theFBpinisnotwithin±10%oftheinternal0.6Vreference.

INTV

(K9): Internal 3.3V RegulatorOutputfor Both 5A

CC12

Switching Mode Regulator Channels. The internal power

drivers and control circuits are powered from this voltage.

Decouple each pin to GND with a minimum of 2.2µF local

low ESR ceramic capacitor.

CLKOUT0 (E10), CLKOUT3 (P6): Output Clock Signal for

PolyPhaseOperationofEach12ASwitchingModeRegula-

tor Channel. The phase of CLKOUT with respect to CLKIN

is determined by the state of the respective PHMODE pin.

CLKOUT’s peak-to-peak amplitude is INTV to GND. See

Applications Information section for details.

RUN1 (J8), RUN2 (L8): Run Control Input of Each 5A

Switching Mode Regulator Channel. Enable regulator

operation by tying the specific RUN pin above 1.2V. Tying

it below 1.1V shuts down the specific regulator channel.

CC

PHMODE0 (E6), PHMODE3 (R6): Control Input to the

Phase Selector of Each 12A Switching Mode Regulator

Channel. Determines the phase relationship between in-

COMP1 (J11), COMP2 (M11): Current Control Threshold

andErrorAmplifierCompensationPointofEach5ASwitch-

ingModeRegulatorChannel.Theinternalcurrentcompara-

torthresholdislinearlyproportionaltothisvoltage. Tiethe

COMP pins from different channels together for parallel

operation. These channels are internally compensated.

ternal oscillator and CLKOUT. Tie it to INTV for 2-phase

CC

operation, tie it to SGND for 3-phase operation, and float-

ing for 4-phase operation. See Applications Information

section for details.

Rev. B

11

For more information www.analog.com

LTM4671

PIN FUNCTIONS

VOSNS1 (J10), VOSNS2 (L10): Output Voltage Sense Pin

FB1 (H9), FB2 (M9): The Negative Input of the Error

Amplifier for Each 5A Switching Mode Regulator Channel.

This pin is internally connected to VOSNS1 or VOSNS2,

respectively, with a 60.4kΩ precision resistor. Output

voltages can be programmed with an additional resistor

between FB and GND pins. In PolyPhase operation, tying

the FB pins together allows for parallel operation. See the

Applications Information section for details.

of Each 5A Switching Mode Regulator Channel. Internally,

this pin is connected to V with a 60.4k 0.5% precision

FB

resistor. See the Applications Information section for

details. It is very important to connect these pins to the

V

since this is the feedback path, and cannot be left

OUT

open. See the Applications Information section for details.

MODE/CLKIN12 (L9): Mode Select and External Synchro-

nization Input Pin for Both 5A Switching Mode Regulator

Channels.TiethispintoGNDtoforcecontinuoussynchro-

TRACK/SS1 (G7), TRACK/SS2 (N7): Output Tracking

and Soft-Start Pin of Each 5A Switching Mode Regulator

Channel. Allows the user to control the rise time of the

output voltage. Putting a voltage below 0.6V on this pin

bypassestheinternalreferenceinputtotheerroramplifier,

instead it servos the FB pin to the TRACK voltage. Above

0.6V,thetrackingfunctionstopsandtheinternalreference

resumes control of the error amplifier. There’s an internal

nous operation. Floating this pin or tying it to INTV

CC12

enables high efficiency Burst Mode operation at light

loads. When driving this pin with an external clock, the

phase-locked loop will force the channel 1 turn on signal

to be synchronized with the rising edge of the CLKIN12

signal. channel 2 will also be synchronized with the rising

edge of the CLKIN12 signal with a 180° phase shift. See

Applications Information section for details.

1.4µA pull-up current from INTV on this pin, so putting

CC

a capacitor here provides soft-start function. See the Ap-

plications Information section for details.

TMON(K8):TemperatureMonitorfor5AOutputChannels.

Avoltageproportionaltothemeasuredon-dietemperature

will appear at this pin. The voltage-to-temperature scaling

factoris200°K/V.SeetheApplicationsInformationsection

for detailed information on the TMON function. Tie this pin

FREQ12(K10):SwitchingFrequencyProgramPinforBoth

5A Switching Mode Regulator Channels. Frequency is

set internally to 1MHz. An external resistor can be placed

from this pin to GND to increase frequency, or from this

to INTV

to disable the temperature monitor circuit.

pin to INTV to reduce frequency. See the Applications

CC12

CC

Information section for frequency adjustment.

Rev. B

12

For more information www.analog.com

LTM4671

BLOCK DIAGRAM

ꢋꢃꢌꢉꢍꢀꢁꢂꢎꢊꢆ

ꢓꢆꢆꢙ

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ꢒ

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ꢒ

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ꢃꢄꢅꢆ

ꢒ

ꢃꢄꢅꢓ

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ꢕRꢉꢜꢆ

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ꢋꢃꢌꢉꢍꢀꢁꢂꢎꢊꢗ

ꢆ.ꢗꢗꢔꢘ

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ꢟ

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ꢇꢃꢈꢉR ꢀꢃꢊꢅRꢃꢁ

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Rꢄꢊꢗ

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ꢕꢎꢁꢅꢉR

ꢎꢊꢅꢉRꢊꢏꢁ ꢀꢃꢋꢇ

ꢀꢁꢂꢃꢄꢅꢗ

ꢒꢃꢐꢊꢐꢖ

ꢕRꢉꢜꢗ

ꢕBꢖ

ꢖꢛꢚꢙ

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ꢀꢀꢓꢖ

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ꢒ

ꢎꢊ

ꢋꢃꢌꢉꢍꢀꢁꢂꢎꢊꢓꢖ

ꢅRꢏꢀꢂꢍꢐꢐꢓ

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ꢓꢔꢘ

ꢒ

ꢆ.ꢓꢔꢕ

ꢃꢄꢅꢓ

ꢒ

ꢃꢄꢅꢓ

ꢖ.ꢢꢒ

ꢅRꢏꢀꢂꢍꢐꢐꢖ

Rꢄꢊꢓ

ꢢꢏ

ꢓꢔꢕ

ꢚꢛꢔꢕ

ꢞꢊꢌ

ꢇꢃꢈꢉR ꢀꢃꢊꢅRꢃꢁ

Rꢄꢊꢖ

ꢀꢃꢋꢇꢓ

ꢎꢊꢅꢉRꢊꢏꢁ ꢀꢃꢋꢇ

ꢆ.ꢖꢖꢔꢕ

ꢓꢔꢕ

ꢀꢃꢋꢇꢖ

ꢎꢊꢅꢉRꢊꢏꢁ ꢀꢃꢋꢇ

ꢕRꢉꢜꢓꢖ

ꢓꢔꢘ

ꢒ

ꢗ.ꢗꢒ

ꢢꢏ

ꢃꢄꢅꢖ

ꢒ

ꢃꢄꢅꢖ

ꢚꢛꢔꢕ

ꢞꢊꢌ

ꢗꢖꢚꢙ

Figure 1. Simplified LTM4671 Block Diagram

Rev. B

13

For more information www.analog.com

LTM4671

DECOUPLING REQUIREMENTS

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

C

External Input Capacitor Requirement

44

66

µF

IN

(V = 3.1V to 20V, V

= 1.5V)

IN

OUT

, C

External Output Capacitor Requirement

(V = 3.1V to 20V, V = 1.5V)

I

= 12A

= 5A

100

22

200

47

µF

OUT0 OUT3

OUT

IN

OUT

, C

External Output Capacitor Requirement

(V = 3.1V to 20V, V = 1.5V)

OUT1 OUT2

OUT

IN

OUT

OPERATION

The LTM4671 is a quad output standalone non-isolated

switch mode DC/DC power supply. It has built-in four

separate regulator channels which can deliver 12A, 12A,

5A, 5A continuous output current with few external input

and output capacitors. Two 12A regulator provides pre-

cisely regulated output voltage programmable from 0.6V

to 3.3V via a single external resistor over 3.1V to 20V

input voltage range while the other two 5A regulator can

support output voltage from 0.6V to 5.5V. Dual true dif-

ferentialremotesensingamplifiersareincludedinthehigh

current channels to get accurate regulation at load point.

The typical application schematic is shown in Figure 30.

employ a 2+1+1 or 2+2 channels parallel operation which

is more than flexible in a multirail POL application like

FPGA.Furthermore,theLTM4671hasCLKINandCLKOUT

pins for frequency synchronization or PolyPhase multiple

devices which allow up to 8 phases of 12A or 5A channels

can be cascaded to run simultaneously.

Currentmodecontrolalsoprovidescycle-by-cyclefastcur-

rentmonitoring.Aninternalovervoltageandundervoltage

comparators pull the open-drain PGOOD output low if the

output feedback voltage exits a ±10% window around the

regulationpoint.Furthermore,inanovervoltagecondition,

internal top FET is turned off and bottom FET is turned on

and held on until the overvoltage condition clears.

The LTM4671 has integrated four separate constant on-

time valley current mode regulators, power MOSFETs,

inductors, and other supporting discrete components.

For switching noise-sensitive applications, the switching

frequency can be adjusted by external resistors and the

µModule can be externally synchronized to a clock. See

the Applications Information section.

Pulling the RUN pin below 0.6V forces the controller into

its shutdown state, turning off both power MOSFETs and

mostoftheinternalcontrolcircuitry.Atlightloadcurrents,

Burst Mode operation can be enabled to achieve higher

efficiency compared to continuous mode for the dual 5A

channels by setting MODE/PLLIN pin floating or tying

With current mode control and internal feedback loop

compensation,theLTM4671modulehassufficientstabil-

ity margins and good transient performance with a wide

range of output capacitors, even with all ceramic output

capacitors. For Dual 12A output rails, an optional Type II

C-R-C external compensation network is allowed to cus-

tomize the stability and transient performance.

to INTV . The TRACK/SS pin is used for power supply

CC

trackingandsoft-startprogramming.SeetheApplications

Information section.

Three different temperature sensing pins are included in-

side the module to monitor the temperature of the module

for different channels. See the Applications Information

section for details.

Current mode control provides the flexibility of paralleling

any of the separate regulator channels with accurate cur-

rent sharing. With a build in clock interleaving between

each two regulator channels, the LTM4671 could easily

Rev. B

14

For more information www.analog.com

LTM4671

APPLICATIONS INFORMATION

For parallel operation of N-channels, tie the V , the FB

ThetypicalLTM4671applicationcircuitisshowninFigure

30. External component selection is primarily determined

by the input voltage, the output voltage and the maxi-

mum load current. Refer to Table 3 for specific external

capacitor requirements for a particular application.

OUT

–

pins and VOSNS pins together but only hooking up one

+

VOSNS (VOSNS) pin to the V

so that all the parallel-

OUT

ing channels can share the same error amplifier and same

top 60.4k feedback resistor. See PolyPhase Operation for

details.

V TO V

STEP-DOWN RATIOS

IN

OUT

Table 1. V_FBResistor Table vs Various Output Voltages

There are restrictions in the maximum V and V

step-

IN

OUT

V

(V)

OUT

0.6

1.0

1.2

1.5

1.8

2.5

3.3

5.0

down ratio that can be achieved for a given input voltage

due to the minimum off-time and minimum on-time limits

of each regulator. The minimum off-time limit imposes a

maximum duty cycle which can be calculated as:

R

(k)

OPEN 90.9 60.4 40.2 30.1 19.1 13.3 8.25

FB

INPUT DECOUPLING CAPACITORS

The LTM4671 module should be connected to a low AC-

impedance DC source. For each 12A regulator channel,

one piece 22µF input ceramic capacitor is required, for

each 5A regulator channel, one piece 10µF input ceramic

capacitor is required for RMS ripple current decoupling.

Bulk input capacitor is only needed when the input source

impedanceiscompromisedbylonginductiveleads,traces

ornotenoughsourcecapacitance.Thebulkcapacitorcanbe

an electrolytic aluminum capacitor and polymer capacitor.

D

= 1– t

• f

(MAX)

OFF(MIN) SW

where t

is the minimum off-time, 80ns typical for

OFF(MIN)

LTM4671, andf istheswitchingfrequency. Conversely,

SW

theminimumon-timelimitimposesaminimumdutycycle

of the converter which can be calculated as:

D

= t

• f

(MIN)

ON(MIN) SW

where T

is the minimum on-time, 25ns typical

ON(MIN)

Without considering the inductor current ripple, the RMS

current of the input capacitor can be estimated as:

for LTM4671. In the rare cases where the minimum duty

cycle is surpassed, the output voltage will still remain in

regulation, buttheswitchingfrequencywilldecreasefrom

its programmed value. These constraints are shown in

I

OUT(MAX)

I

=

• D • (1– D)

CIN(RMS)

η%

the Typical Performance Characteristic curve labeled “V

IN

to V

Step-Down Ratio.” Note that additional thermal

whereη%istheestimatedefficiencyofthepowermodule.

OUT

derating may be applied. See the Thermal Considerations

and Output Current Derating section in this data sheet.

OUTPUT DECOUPLING CAPACITORS

Withanoptimizedhighfrequency, highbandwidthdesign,

only single piece of low ESR output ceramic capacitor is

required for each regulator channel to achieve low output

voltagerippleandverygoodtransientresponse.Additional

output filtering may be required by the system designer,

if further reduction of output ripples or dynamic transient

spikesisrequired.Table3showsamatrixofdifferentoutput

voltages and output capacitors to minimize the voltage

droop and overshoot during a 25% load step transient.

Multiphase operation will reduce effective output ripple as

a function of the number of phases. Application Note 77

discusses this noise reduction versus output ripple cur-

rent cancellation, but the output capacitance will be more

OUTPUT VOLTAGE PROGRAMMING

ThePWMcontrollerhasaninternal0.6Vreferencevoltage.

For the 12A channels (CH0, CH3), a 60.4k 0.5% internal

+

feedbackresistorconnectseachregulatorchannelVOSNS

and FB pin together. Adding a resistor R from FB pin to

FB

–

VOSNS programs the output voltage.

For the 5A channels (CH1, CH2), a 60.4k 0.5% internal

feedbackresistorconnectseachregulatorchannelVOSNS

and FB pin together. Adding a resistor R from FB pin to

GND programs the output voltage:

FB

60.4k + R_FB

V_OUT= 0.6V •

R_FB

Rev. B

15

For more information www.analog.com

LTM4671

APPLICATIONS INFORMATION

a function of stability and transient response. The Analog

DevicesLTpowerCAD^®DesignToolisavailabletodownload

online for output ripple, stability and transient response

analysis and calculating the output ripple reduction as

the number of phases implemented increases by N times.

reversal comparator (I ) detects the negative inductor

REV

current and shuts off the bottom power MOSFET, resulting

in discontinuous operation and increased efficiency. Both

power MOSFETs will remain off until the ITH voltage rises

abovethezerocurrentleveltoinitiateanothercycle.During

this time, the output capacitor supplies the load current

and the part is placed into a low current sleep mode.

FORCED CONTINUOUS CURRENT MODE (CCM)

In applications where fixed frequency operation is more

critical than low current efficiency, and where the lowest

outputrippleisdesired,forcedcontinuousoperationshould

beused.Inthismode,inductorcurrentisallowedtoreverse

during low output loads, the COMP voltage is in control

of the current comparator threshold throughout, and the

top MOSFET always turns on with each oscillator pulse.

OPERATING FREQUENCY

The operating frequency of the LTM4671 is optimized

to achieve the compact package size and the minimum

output ripple voltage while still keeping high efficiency.

The default operating frequency is internally set to 600kHz

for 12A channels and 1MHz for 5A channels. In most ap-

plications, no additional frequency adjusting is required.

For the 12A channels (CH0, CH3), CCM can be enabled

by tying the MODE/CLKIN0 or MODE/CLKIN3 pin to the

Forthe12Achannels(CH0,CH3),ifanoperatingfrequency

other than 600kHz is required by the application, the op-

erating frequency can be increased by adding a resistor,

respective INTV or simply floating it.

CC

For the 5A channels (CH1, CH2), CCM can be enabled by

tying the MODE/CLKIN12 pin to GND.

R

, between the FREQ0 or FREQ3 pins and SGND. The

FSET

operating frequency can be calculated as:

During start-up, forced continuous mode is disabled and

inductor current is prevented from reversing until the

LTM4671’s output voltage is in regulation.

11

1.6e

f Hz =

(

)

274k||R

Ω

( )

FSET

The programmable operating frequency range is from

400kHz to 3MHz.

DISCONTINUOUS MODE/BURST MODE OPERATION

Inapplicationswherehighefficiencyatintermediatecurrent

is desired, discontinuous mode or Burst Mode operation

can be achieved.

For the 5A channels (CH1, CH2), If an operating frequency

other than 1MHz is required by the application, the op-

erating frequency can be increased by adding a resistor,

For the 12A channels (CH0, CH3), discontinuous mode

(DCM) can be achieved by tying the MODE/CLKIN0 or

MODE/CLKIN3 pin to GND. In discontinuous mode, the

reversecurrentcomparatorwillsensetheinductorcurrent

and turn of bottom MOSFET when the inductor current

drops to zero and becomes negative. Both power MOS-

FETs will remain off with the output capacitor supplying

the load current until the COMP voltage rises above its

zero current threshold to initiate the next switching cycle.

R

, between the FREQ12 pin and SGND. The operating

FSET

frequency can be calculated as:

11

3.2e

f Hz =

(

)

324k||R

Ω

( )

FSET

The programmable operating frequency range is from

400kHz to 3MHz.

AlsotheµModulecanbeexternallysynchronizedtoaclock

at ±30% around set operating frequency.

For the 5A channels (CH1, CH2), Burst Mode operation

can be achieved by tying MODE/CLKIN12 pin to INTV

CC12

or simply floating. In Burst Mode operation, a current

Rev. B

16

For more information www.analog.com

LTM4671

APPLICATIONS INFORMATION

FREQUENCY SYNCHRONIZATION AND CLOCK IN

ꢇꢈꢉꢊꢋꢌꢍꢎꢏꢐꢅ

ꢑꢒꢇꢈꢉꢊꢅ

The power module has a phase-locked loop comprised

of an internal voltage controlled oscillator and a phase

detector. This allows all internal top MOSFET turn-on to

be locked to the rising edge of the same external clock.

The external clock frequency range must be within ±30%

around the set frequency.

ꢏꢐꢔꢕ

ꢌꢌꢅ

ꢌꢒꢅ

ꢖꢅꢗꢘ

ꢕ

ꢈꢓꢔꢅ

ꢕ

ꢈꢓꢔꢚ

ꢕ

ꢈꢓꢔꢃ

ꢕ

ꢈꢓꢔꢆ

ꢌꢍꢎꢈꢓꢔꢅ

ꢃꢙꢅꢗ

ꢆꢀꢜ

ꢇꢈꢉꢊꢋꢌꢍꢎꢏꢐꢚ

ꢑꢒꢇꢈꢉꢊꢚ

ꢌꢒꢚ

ꢖꢃꢙꢅꢗꢘ

ꢄꢍꢈꢜꢔ

A pulse detection circuit is used to detect a clock on the

MODE/CLKIN0 pin for CH0 (12A) channel, MODE/CLKIN3

pinforCH3(12A)channelandMODE/CLKIN12pinforboth

CH1andCH25Achannelstoturnonthephase-lockedloop.

ꢌꢍꢎꢈꢓꢔꢚ

ꢛꢅꢗ

ꢇꢈꢉꢊꢋꢌꢍꢎꢏꢐꢃꢆ

ꢌꢒꢃ

ꢖꢆꢂꢅꢗꢘ

The pulse width of the clock has to be at least 400ns.

The clock high level must be above 1V and clock low

level below 0.3V. During the start-up of the regulator, the

phase-locked loop function is disabled. When the module

is driven with an external clock, forced continuous mode

(CCM) is automatically enabled.

ꢃꢙꢅꢗ

ꢃꢅꢜ

ꢌꢒꢆ

ꢖꢛꢅꢗꢘ

ꢍꢔꢇꢀꢁꢂꢃ

ꢀꢁꢂꢃ ꢄꢅꢆ

MULTICHANNEL PARALLEL OPERATION

Figure 2. 2 + 2 Parallel Concept Schematic

For the application that demand more than 12A of output

current, the LTM4671 multiple regulator channels can be

easilyparalleledtorunoutofphasetoprovidemoreoutput

currentwithoutincreasinginputandoutputvoltageripples.

pacitors. The RMS input ripple current is reduced by, and

the effective ripple frequency is multiplied by, the number

of phases used (assuming that the input voltage is greater

thanthenumberofphasesusedtimestheoutputvoltage).

Theoutputrippleamplitudeisalsoreducedbythenumber

of phases used when all of the outputs are tied together

to achieve a single high output current design.

For the 12A channels (CH0, CH3), each channel has its

own MODE/CLKIN and CLKOUT pin. The CLKOUT signal

canbeconnectedtotheCLKINpinofthefollowingstageto

line up both frequency and the phase of the entire system.

TyingthePHMODEpintoINTV , SGNDorfloatingthepin

CC

The LTM4671 device is an inherently current mode con-

trolled device, so parallel modules will have very good

current sharing. This will balance the thermals on the

design. Please tie RUN, TRACK/SS, FB and COMP pins

of each paralleling channel together. Figure 31 shows an

example of parallel operation and pin connection.

generates a phase difference between the clock applied on

the MODE/CLKIN pin and CLKOUT of 180° degrees, 120°

degrees, or 90° degrees respectively, which corresponds

to 2-phase, 3-phase, or 4-phase operation.

For the 5A channels (CH1, CH2), a preset built-in 180°

phase different between channel 1 and channel 2. MODE/

CLKIN12 allows both channels to be synchronized to

an external clock or the CLKOUT signal from any of the

12A channels.

INPUT RMS RIPPLE CURRENT CANCELLATION

Application Note 77 provides a detailed explanation of

multiphase operation. The input RMS ripple current

cancellation mathematical derivations are presented, and

a graph is displayed representing the RMS ripple current

reduction as a function of the number of interleaved

Figure 2 shows a 2 + 2 and a 4-channels parallel concept

schematic for clock phasing.

A multiphase power supply significantly reduces the

amount of ripple current in both the input and output ca-

phases. Figure 3 shows this graph.

Rev. B

17

For more information www.analog.com

LTM4671

APPLICATIONS INFORMATION

ꢀ.ꢅꢀ

ꢆꢝꢜꢞꢏꢛꢙ

ꢉꢝꢜꢞꢏꢛꢙ

ꢀ.ꢂꢂ

ꢈꢝꢜꢞꢏꢛꢙ

ꢄꢝꢜꢞꢏꢛꢙ

ꢅꢝꢜꢞꢏꢛꢙ

ꢀ.ꢂꢀ

ꢀ.ꢄꢂ

ꢀ.ꢄꢀ

ꢀ.ꢈꢂ

ꢀ.ꢈꢀ

ꢀ.ꢉꢂ

ꢀ.ꢉꢀ

ꢀ.ꢆꢂ

ꢀ.ꢆꢀ

ꢀ.ꢀꢂ

ꢀ

ꢀ.ꢆ ꢀ.ꢆꢂ ꢀ.ꢉ ꢀ.ꢉꢂ ꢀ.ꢈ ꢀ.ꢈꢂ ꢀ.ꢄ ꢀ.ꢄꢂ ꢀ.ꢂ ꢀ.ꢂꢂ ꢀ.ꢅ ꢀ.ꢅꢂ ꢀ.ꢁ ꢀ.ꢁꢂ ꢀ.ꢃ ꢀ.ꢃꢂ ꢀ.ꢊ

ꢋꢌꢍꢎ ꢇꢏꢐꢍꢑR ꢒꢓ ꢔꢓ

ꢗ

ꢑꢌꢍ ꢕꢖ

Figure 3. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle

SOFT-START AND OUTPUT VOLTAGE TRACKING

Figure 4 and Figure 5 show an example waveform and

schematic of a ratiometric tracking where the slave

The TRACK/SS pin provides a means to either soft-start

of each regulator channel or track it to a different power

supply. A capacitor on the TRACK/SS pin will program the

ramp rate of the output voltage. An internal soft-start cur-

rent source will charge up the external soft-start capacitor

regulator’s (V

, V

and V

) output slew rate is

OUT2 OUT3

proportional to the master’s (V

OUT0

).

OUT1

ꢍ

ꢑ ꢒ.ꢒꢍ

ꢊꢋꢆꢃ

ꢊꢋꢆꢓ

ꢊꢋꢆꢒ

ꢊꢋꢆꢅ

towards INTV voltage. When the TRACK/SS voltage is

CC

below 0.6V, it will take over the internal 0.6V reference

voltage to control the output voltage. The total soft-start

time can be calculated as:

ꢑ ꢓ.ꢔꢍ

ꢑ ꢃ.ꢓꢍ

ꢑ ꢃ.ꢅꢍ

C_SS

t_SS= 0.6 •

I_SS

where C is the capacitance on the TRACK/SS pin and

SS

the I is the soft-start current which equals 6µA for the

SS

12A output channels (CH0, CH3) and 1.4µA for the 5A

ꢀꢁꢂꢃ ꢄꢅꢀ

ꢆꢇꢈꢉ

Figure 4. Output Ratiometric Tracking Waveform

output channels (CH1, CH2).

Outputvoltagetrackingcanalsobeprogrammedexternally

using the TRACK/SS pin of each regulator channel. The

output can be tracked up and down with another regulator.

Rev. B

18

For more information www.analog.com

LTM4671

APPLICATIONS INFORMATION

ꢇ

ꢈꢉ

ꢀꢇ ꢌꢋ ꢖꢅꢇ

ꢎꢒꢃ

ꢎꢒꢖ

ꢎꢒꢔ

ꢎꢒꢅ

ꢀꢁꢂꢃ ꢄꢅꢆ

ꢎ

ꢑꢑ

R

ꢄBꢗꢑꢚꢙꢅ

ꢛꢅ.ꢁꢕ

ꢄBꢗꢑꢚꢙꢖ

ꢄBꢗꢑꢚꢙꢔ

ꢅ.ꢃꢓꢄ

ꢃꢛ.ꢃꢕ

ꢁꢅ.ꢀꢕ

R

ꢄBꢃ

ꢃꢔ.ꢔꢕ

R

ꢌRꢗꢌꢋꢘꢙꢖ

ꢁꢅ.ꢀꢕ

ꢌRꢗBꢋꢌꢙꢖ

ꢃꢔ.ꢔꢕ

R

ꢌRꢗꢌꢋꢘꢙꢔ

ꢁꢅ.ꢀꢕ

ꢌRꢗBꢋꢌꢙꢔ

ꢃꢔ.ꢔꢕ

R

ꢌRꢗꢌꢋꢘꢙꢅ

ꢁꢅ.ꢀꢕ

ꢌRꢗBꢋꢌꢙꢅ

ꢃꢔ.ꢔꢕ

Figure 5. Output Ratiometric Tracking Schematic

Since the slave regulator’s TRACK/SS is connected to

the master’s output through a R /R resistor

divider and its voltage used to regulate the slave output

voltage when TRACK/SS voltage is below 0.6V, the slave

outputvoltageandthemasteroutputvoltageshouldsatisfy

the following equation during the start-up.

Forexample,V

=3.3V,MR=3.3V/msandV

=

OUT(MA)

1.0V,SR=1.0V/msasV

OUT(SL)

fromtheequation,

TR(TOP) TR(BOT)

andV

OUT1

TR(TOP)0

OUT0

= 60.4k and R

we could solve out that R

=

TR(BOT)0

13.3k is a good combination. Follow the same equation,

we can get the same R /R resistor divider

TR(TOP) TR(BOT)

OUT3.

value for V

and V

OUT2

R_FB(SL)

R_TR(BOT)

The TRACK pins will have the 1.5µA current source on

when a resistive divider is used to implement tracking on

that specific channel. This will impose an offset on the

TRACK pin input. Smaller value resistors with the same

ratios as the resistor values calculated from the above

equation can be used. For example, where the 60.4k is

used then a 6.04k can be used to reduce the TRACK pin

offset to a negligible value.

V_OUT(SL)

•

= V_OUT(MA)•

R_FB(SL)+ 60.4k

R

_TR(TOP)+ R_TR(BOT)

The R

is the feedback resistor and the RTR

is the resistor divider on the TRACK/SS pin of

the slave regulator, as shown in Figure 5.

/

(TOP)

FB(SL)

RTR

(BOT)

Following the upper equation, the master’s output slew

rate (MR) and the slave’s output slew rate (SR) in Volts/

Time is determined by:

The coincident output tracking can be recognized as a

special ratiometric output tracking which the master’s

output slew rate (MR) is the same as the slave’s output

slew rate (SR), see Figure 6.

R

FB(SL)

R

+ 60.4k

MR

SR

FB(SL)

=

R

TR(BOT)

R

+ R

TR(BOT)

TR(TOP)

Rev. B

19

For more information www.analog.com

LTM4671

APPLICATIONS INFORMATION

reduction, an additional 10pF to 15pF phase boost cap is

required between V

and FB pins.

ꢍ

ꢑ ꢒ.ꢒꢍ

ꢑ ꢓ.ꢔꢍ

ꢑ ꢃ.ꢓꢍ

ꢑ ꢃ.ꢅꢍ

ꢊꢋꢆꢃ

ꢊꢋꢆꢓ

ꢊꢋꢆꢒ

ꢊꢋꢆꢅ

OUT

For specific optimized requirement for the dual 12A chan-

nels, disconnect COMPb from COMPa and apply a Type II

C-R-C compensation network from COMPa to SGND to

achieve external compensation.

The LTpowerCAD design tool is available to download

online to perform specific control loop optimization and

analyzethecontrolstabilityandloadtransientperformance.

ꢀꢁꢂꢃ ꢄꢅꢁ

ꢆꢇꢈꢉ

Figure 6. Output Coincident Tracking Waveform

RUN ENABLE

Pulling the RUN pin of each regulator channel to ground

forcestheregulatorintoitsshutdownstate,turningoffboth

power MOSFETs and most of its internal control circuitry.

Bringing the RUN pin above 0.7V turns on the internal

reference only, while still keeping the power MOSFETs

off. Further increasing the RUN pin voltage above 1.2V

will turn on the entire regulator channel.

R_FB(SL)

R_TR(BOT)

=

R

_FB(SL)+ 60.4k

R

_TR(TOP)+ R_TR(BOT)

From the equation, we could easily find out that, in the

coincident tracking, the slave regulator’s TRACK/SS pin

resistor divider is always the same as its feedback divider.

For example, R

= 60.4k and R

= 60.4k

TR(BOT)3

TR(TOP)3

TEMPERATURE MONITORING

The 12A Channels (CH0, CH3):

is a good combination for coincident tracking for

= 3.3V and V =1.2V application.

V

OUT(MA)

OUT(SL)

Measuring the absolute temperature of a diode is pos-

sible due to the relationship between current, voltage

and temperature described by the classic diode equation:

POWER GOOD

The PGOOD pins are open-drain pins that can be used to

monitor valid output voltage regulation. This pin monitors

a ±10% window around the regulation point. A resistor

can be pulled up to a particular supply voltage for moni-

toring. To prevent unwanted PGOOD glitches during tran-

⎛

⎞

V

D

I = I •e

D

S

⎜

⎟

η• V

⎝

⎠

T

sients or dynamic V

changes, the LTM4671’s PGOOD

or

OUT

falling edge includes a blanking delay of approximately

I

52 switching cycles.

D

V = η • V •In

D

T

I

S

STABILITY COMPENSATION

where I is the diode current, V is the diode voltage, η

D

The LTM4671 module internal compensation loop of each

regulator channel is designed and optimized for low ESR

ceramic output capacitors only application (COMPb tied

to COMPa for 12A channels). Table 3 is provided for most

application requirements using the optimized internal

compensation. In case of all ceramic output capacitors

is required for output ripples or dynamic transient spike

is the ideality factor (typically close to 1.0) and I (satu-

S

ration current) is a process dependent parameter. V can

T

be broken out to:

k • T

V =

T

q

Rev. B

20

For more information www.analog.com

LTM4671

APPLICATIONS INFORMATION

where T is the diode junction temperature in Kelvin, q is

the electron charge and k is Boltzmann’s constant. V is

ꢌ.ꢕ

ꢌ.ꢖ

ꢌ.ꢘ

ꢌ.ꢋ

ꢌ.ꢗ

ꢌ.ꢎ

T

approximately 26mV at room temperature (298K) and

scales linearly with Kelvin temperature. It is this linear

temperature relationship that makes diodes suitable tem-

perature sensors. The I term in the previous equation is

S

the extrapolated current through a diode junction when

the diode has zero volts across the terminals. The I term

S

varies from process to process, varies with temperature,

and by definition must always be less than I . Combining

D

ꢊꢋꢌ ꢊꢍꢋ

ꢌ

ꢍꢋ

ꢋꢌ

ꢖꢋ ꢙꢌꢌ ꢙꢍꢋ

all of the constants into one term:

ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ

ꢗꢘꢖꢙ ꢚꢌꢖ

η•k

K =

D

Figure 7. Diode Voltage V_Dvs Temperature T(°C)

q

−5

where K = 8.62 , and knowing ln(I /I ) is always posi-

D

D S

yields

∆V = K’ • T(KELVIN)

tive because I is always greater than I , leaves us with

the equation that:

D

S

D

Solving for temperature:

I

D

V = T KELVIN •K •In

(

)

D

∆V

I

D

S

T(KELVIN)=

(°CELSIUS)= T(KELVIN)– 273.15

K'

D

where V appears to increase with temperature. It is com-

D

mon knowledge that a silicon diode biased with a current

source has an approximate –2mV/°C temperature rela-

tionship (Figure 7), which is at odds with the equation. In

where

300°K = 27°C

means that is we take the difference in voltage across the

diode measured at two currents with a ratio of 10, the

resulting voltage is 198μV per Kelvin of the junction with

a zero intercept at 0 Kelvin.

fact, the I term increases with temperature, reducing the

S

ln(I /I ) absolute value yielding an approximate –2mV/°C

D S

composite diode voltage slope.

To obtain a linear voltage proportional to temperature

+

The diode connected NPN transistor across the T

SENSEn

we cancel the I variable in the natural logarithm term to

S

−

and pin and T

pins can be used to monitor the

SENSEn

remove the I dependency from the equation 1. This is

S

internal temperature of the LTM4671 channel 0 and 3.

accomplished by measuring the diode voltage at two cur-

rents I , and I , where I = 10 • I ) and subtracting we get:

1

2

1

2

The 5A Channels (CH1, CH2):

I

2

1

The LTM4671 produces a voltage at the TMON pin

proportional to the measured junction temperature. The

junction temperature-to-voltage scaling factor is 200°K/V.

Thus,toobtainthejunctiontemperatureindegreesKelvin,

simply multiply the voltage provided at the TMON pin by

the scaling factor. To obtain the junction temperature in

degrees Celsius, subtract 273 from the value obtained in

degrees Kelvin.

∆V = T(KELVIN)•K •IN – T(KELVIN)•K •IN

D

I

S

Combining like terms, then simplifying the natural log

terms yields:

∆V = T(KELVIN) • K • lN(10)

D

and redefining constant

198µV

K' = K •IN(10) =

D

K

Rev. B

21

For more information www.analog.com

LTM4671

APPLICATIONS INFORMATION

ꢀ.ꢁ

ꢀ.ꢀ

1. θ , the thermal resistance from junction to ambi-

JA

ent, is the natural convection junction-to-ambient

air thermal resistance measured in a one cubic foot

sealed enclosure. This environment is sometimes

referred to as “still air” although natural convection

causes the air to move. This value is determined with

the part mounted to a JESD51-9 defined test board,

which does not reflect an actual application or viable

operating condition.

2. θ

, the thermal resistance from junction to

JCbottom

ꢀꢁꢂ ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ

ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ

ambient,isthenaturalconvectionjunction-to-ambient

air thermal resistance measured in a one cubic foot

sealed enclosure. This environment is sometimes

referred to as “still air” although natural convection

causes the air to move. This value is determined with

the part mounted to a JESD51-9 defined test board,

which does not reflect an actual application or viable

operating condition.

ꢀꢁꢂꢃ ꢄꢅꢆ

Figure 8. TMON Voltage

Thermal Considerations and Output Current Derating

The thermal resistances reported in the Pin Configuration

section of the data sheet are consistent with those param-

eters defined by JESD51-9 and are intended for use with

finite element analysis (FEA) software modeling tools that

leveragetheoutcomeofthermalmodeling,simulation,and

correlationtohardwareevaluationperformedonaµModule

package mounted to a hardware test board—also defined

by JESD51-9 (“Test Boards for Area Array Surface Mount

Package Thermal Measurements”). The motivation for

providingthesethermalcoefficientsinfoundinJESD51-12

(“Guidelines for Reporting and Using Electronic Package

Thermal Information”).

4. θ

, the thermal resistance from junction to top of

JCtop

the product case, is determined with nearly all of the

componentpowerdissipationflowingthroughthetop

of the package. As the electrical connections of the

typical µModule are on the bottom of the package, it

is rare for an application to operate such that most of

the heat flows from the junction to the top of the part.

As in the case of θ

, this value may be useful

JCbottom

for comparing packages but the test conditions don’t

generally match the user’s application.

Many designers may opt to use laboratory equipment

and a test vehicle such as the demo board to anticipate

the µModule regulator’s thermal performance in their

applicationatvariouselectricalandenvironmentaloperat-

ing conditions to compliment any FEA activities. Without

FEA software, the thermal resistances reported in the

Pin Configuration section are in-and-of themselves not

relevant to providing guidance of thermal performance;

instead, the derating curves provided in the data sheet

can be used in a manner that yields insight and guidance

pertainingtoone’sapplication-usage, andcanbeadapted

tocorrelatethermalperformancetoone’sownapplication.

5. θ , the thermal resistance from junction to the

JB

printed circuit board, is the junction-to-board thermal

resistance where almost all of the heat flows through

the bottom of the µModule and into the board, and

is really the sum of the θ

and the thermal re-

JCbottom

sistance of the bottom of the part through the solder

joints and through a portion of the board. The board

temperature is measured a specified distance from

the package, using a two sided, two layer board. This

board is described in JESD51-9.

The Pin Configuration section typically gives four thermal

coefficients explicitly defined in JESD51-12; these coef-

ficients are quoted or paraphrased below.

Rev. B

22

For more information www.analog.com

LTM4671

APPLICATIONS INFORMATION

resistance values supplied in this data sheet: (1) Initially,

FEA software is used to accurately build the mechanical

geometry of the µModule and the specified PCB with all of

thecorrectmaterialcoefficientsalongwithaccuratepower

losssourcedefinitions;(2)thismodelsimulatesasoftware-

defined JEDEC environment consistent with JSED 51-9 to

predict power loss heat flow and temperature readings

at different interfaces that enable the calculation of the

JEDEC-defined thermal resistance values; (3) the model

and FEA software is used to evaluate the µModule with

heat sink and airflow; (4) having solved for and analyzed

these thermal resistance values and simulated various

operating conditions in the software model, a thorough

laboratory evaluation replicates the simulated conditions

with thermocouples within a controlled-environment

chamber while operating the device at the same power

loss as that which was simulated. An outcome of this

process and due-diligence yields a set of derating curves

provided in other sections of this data sheet. After these

laboratory tests have been performed and correlated to

A graphical representation of the aforementioned ther-

mal resistances is given in Figure 9; blue resistances are

contained within the μModule regulator, whereas green

resistances are external to the µModule.

As a practical matter, it should be clear to the reader that

no individual or sub-group of the four thermal resistance

parameters defined by JESD51-12 or provided in the Pin

Configuration section replicates or conveys normal op-

erating conditions of a μModule. For example, in normal

board-mounted applications, never does 100% of the

device’s total power loss (heat) thermally conduct exclu-

sivelythroughthetoporexclusivelythroughbottomofthe

µModule—asthestandarddefinesforθ

andθ

,

JCtop

JCbottom

respectively.Inpractice,powerlossisthermallydissipated

in bothdirectionsawayfromthepackage—granted, in the

absence of a heat sink and airflow, a majority of the heat

flow is into the board.

Within a SIP (system-in-package) module, be aware there

are multiple power devices and components dissipating

power, with a consequence that the thermal resistances

relative to different junctions of components or die are not

exactly linear with respect to total package power loss. To

reconcile this complication without sacrificing modeling

simplicity—but also, not ignoring practical realities—an

approach has been taken using FEA software modeling

along with laboratory testing in a controlled-environment

chamber to reasonably define and correlate the thermal

the µModule model, then the θ and θ are summed

JB

BA

together to correlate quite well with the µModule model

withnoairfloworheatsinkinginaproperlydefinechamber.

This θ + θ value is shown in the Pin Configuration

JB

BA

section and should accurately equal the θ value because

JA

approximately 100% of power loss flows from the junc-

tion through the board into ambient with no airflow or top

mounted heat sink.

ꢒꢓꢔꢑꢕꢐꢖꢔꢗꢕꢖꢗꢘꢈBꢐꢎꢔꢕ Rꢎꢙꢐꢙꢕꢘꢔꢑꢎ ꢚꢒꢎꢙꢍꢝꢃꢗꢆ ꢍꢎꢄꢐꢔꢎꢍ BꢖꢘRꢍꢜ

ꢒꢓꢔꢑꢕꢐꢖꢔꢗꢕꢖꢗꢑꢘꢙꢎ ꢚꢕꢖꢛꢜ

Rꢎꢙꢐꢙꢕꢘꢔꢑꢎ

ꢑꢘꢙꢎ ꢚꢕꢖꢛꢜꢗꢕꢖꢗꢘꢈBꢐꢎꢔꢕ

Rꢎꢙꢐꢙꢕꢘꢔꢑꢎ

ꢒꢓꢔꢑꢕꢐꢖꢔꢗꢕꢖꢗBꢖꢘRꢍ Rꢎꢙꢐꢙꢕꢘꢔꢑꢎ

ꢒꢓꢔꢑꢕꢐꢖꢔ

ꢘꢈBꢐꢎꢔꢕ

ꢒꢓꢔꢑꢕꢐꢖꢔꢗꢕꢖꢗꢑꢘꢙꢎ

ꢚBꢖꢕꢕꢖꢈꢜ Rꢎꢙꢐꢙꢕꢘꢔꢑꢎ

ꢑꢘꢙꢎ ꢚBꢖꢕꢕꢖꢈꢜꢗꢕꢖꢗBꢖꢘRꢍ

Rꢎꢙꢐꢙꢕꢘꢔꢑꢎ

BꢖꢘRꢍꢗꢕꢖꢗꢘꢈBꢐꢎꢔꢕ

Rꢎꢙꢐꢙꢕꢘꢔꢑꢎ

ꢀꢁꢂꢃ ꢄꢅꢆ

ꢇꢈꢉꢊꢋꢌe ꢍꢎꢏꢐꢑꢎ

Figure 9. Graphical Representation of JESD51-12 Thermal Coefficients

Rev. B

23

For more information www.analog.com

LTM4671

APPLICATIONS INFORMATION

The 1V to 5V power loss curves in Figure 10 to Figure

16 can be used in coordination with the load current

derating curves in Figure 17 to Figure 26 for calculating

junctiontemperatureof120°Cminustheambientoperating

temperaturespecifieshowmuchmoduletemperaturerise

can be allowed. The printed circuit board for this test is a

1.6mm thick six layers board with two ounce copper for

the two outer layers and one ounce copper for the four

inner layers. The PCB dimensions are 121mm × 112mm.

an approximate θ thermal resistance for the LTM4671

JA

with various heat sinking and airflow conditions. The

power loss curves are taken at room temperature and

are increased with a multiplicative factor according to

the junction temperature. This approximate factor is 1.3

considering internal junction temperature hitting 120°C at

the point of derating starts. The derating curves are taken

withthreedifferentoutputpowercombinations,lowpower

Figure 27 and Figure 28 display the maximum power loss

allowance curves vs ambient temperature with various

heat sinking and airflow conditions. This data was derived

from the thermal derating curves in Figure 17 to Figure 26

with the junction temperature measured at 120°C. This

maximumpowerlosslimitationservesasaguidelinewhen

designing multiple output rails with different voltages and

currents by calculating the total power loss. For example,

to determine the maximum ambient temperature when

(V

= V

OUT0

high power (V

= 1V, V

OUT3

= V

OUT1

= 3.3V, V

= 1.5V), medium

OUT0

power (V

OUT3

OUT1

= 1.8V, V

OUT2

= V

= 3.3V) and

OUT2

= V

= 5V).

OUT0

OUT3

OUT1

OUT2

Output current starting at 100% of the full load current

(I = I = 12A, I = I = 5A) and the ambient

OUT0 OUT3

OUT1 OUT2

V = 12V, V

= 1V at 10A, V

OUT3

= 1.8V at 3A, V

IN

OUT0

OUT1 OUT2

= 1.5V at 10A, without a heat sink

temperature starting at 30°C. These are chosen to include

the lower and higher output voltage ranges for correlating

the thermal resistance. Thermal models are derived from

several temperature measurements in a controlled tem-

perature chamber along with thermal modeling analysis.

The junction temperatures are monitored while ambient

temperature is increased with and without airflow. The

power loss increase with ambient temperature change

is factored into the derating curves. The junctions are

maintained at 120°C maximum while lowering output cur-

rent or power with increasing ambient temperature. The

decreasedoutputcurrentwilldecreasetheinternalmodule

loss as ambient temperature is increased. The monitored

= 3.3V at 2A, V

and any airflow, simply add up the total power loss for

each channel read from Figure 10 to Figure 16 which in

this example equals 4.8W (1.6W + 0.7W + 0.6W + 1.9W),

then multiply by the 1.3 coefficient for 120°C junction

temperature and compare the total power loss number,

6.3W with Figure 27. Figure 27 indicates with a 6.3W total

power loss, the maximum ambient temperature for this

application is around 66°C. Also from Figure 27, it is easy

to determine with a 6.3W total power loss, the maximum

ambient temperature is around 73°C with 200LFM airflow

and 77°C with 400LFM airflow.

Rev. B

24

For more information www.analog.com

LTM4671

APPLICATIONS INFORMATION

ꢀ

ꢀ.ꢁ

ꢀ.ꢀ

ꢀ

ꢀ.ꢁ

ꢀ.ꢀ

ꢀ

ꢀ.ꢁ

ꢀ.ꢀ

ꢀ

ꢀꢁ ꢄ ꢅꢆꢇꢄ ꢅꢆꢈ

ꢂꢃ

ꢀꢁꢂ ꢅ ꢆꢇꢀꢅ ꢆꢇꢁ

ꢃꢄ

ꢀꢁ ꢄ ꢅꢆꢇꢄ ꢅꢆꢈ

ꢂꢃ

ꢀꢁꢂ ꢅ ꢆꢇꢈꢅ ꢆꢇꢉ

ꢃꢄ

ꢀ.ꢁ

ꢀ

ꢀ.ꢁ

ꢀ

ꢀ.ꢁ

ꢀ

ꢀ.ꢁ

ꢀ

ꢀ.ꢁ

ꢀ

ꢀ.ꢁ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ

ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ

ꢀꢁꢂꢃ ꢄꢃꢅ

ꢀꢁꢂꢃ ꢄꢃꢃ

ꢀꢁꢂꢃ ꢄꢃꢅ

Figure 10. 1V Output Power Loss

Figure 11. 1.2VOutputPower Loss

Figure 12. 1.5V Output Power Loss

ꢀ

ꢀ.ꢁ

ꢀ.ꢀ

ꢀ

ꢀ.ꢁ

ꢀ

ꢀ.ꢁ

ꢀ

ꢀ.ꢁ

ꢀ.ꢀ

ꢀ.ꢁ

ꢀ

ꢀ.ꢁ

ꢀ.ꢀ

ꢀ.ꢁ

ꢀ

ꢀꢁ ꢄ ꢅꢆꢇꢄ ꢅꢆꢈ

ꢂꢃ

ꢀꢁ ꢄ ꢅꢆꢇꢄ ꢅꢆꢈ

ꢂꢃ

ꢀꢁ ꢄ ꢅꢆꢇꢄ ꢅꢆꢈ

ꢂꢃ

ꢀꢁꢂ ꢅ ꢆꢇꢀꢅ ꢆꢇꢁ

ꢃꢄ

ꢀꢁꢂ ꢅ ꢆꢇꢀꢅ ꢆꢇꢁ

ꢃꢄ

ꢀꢁ ꢄ ꢅꢆꢇꢄ ꢅꢆꢈ

ꢂꢃ

ꢀꢁꢂ ꢅ ꢆꢇꢈꢅ ꢆꢇꢉ

ꢃꢄ

ꢂꢃ

ꢀꢁ ꢄ ꢅꢆꢇꢄ ꢅꢆꢈ

ꢂꢃ

ꢀꢁꢂ ꢅ ꢆꢇꢈꢅ ꢆꢇꢉ

ꢃꢄ

ꢀꢁꢂ ꢅ ꢆꢇꢈꢅ ꢆꢇꢉ

ꢃꢄ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ

ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ

ꢀꢁꢂꢃ ꢄꢃꢅ

ꢀꢁꢂꢃ ꢄꢃꢀ

ꢀꢁꢂꢃ ꢄꢃꢅ

Figure 13. 5V Output Power Loss

Figure 14. 2.5V Output Power Loss

Figure 15. 3.3V Output Power Loss

ꢀ.ꢁ

ꢀ.ꢀ

ꢀ.ꢁ

ꢀ

ꢀꢁꢂ

ꢀꢁꢁ

ꢀꢁ

ꢀ

ꢀꢁꢂ

ꢀꢁꢁ

ꢀꢁ

ꢀ

ꢀꢁꢂ ꢅ ꢆꢇꢀꢅ ꢆꢇꢁ

ꢃꢄ

ꢀꢁꢂꢃ

ꢀꢁꢁꢂꢃꢄ

ꢀꢁꢂꢃ

ꢀꢁꢁꢂꢃꢄ

ꢀ

ꢀꢁ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢀꢁ ꢀꢁꢂ

ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ

ꢀꢁBꢂꢃꢄꢅ ꢅꢃꢁꢆꢃRꢀꢅꢇRꢃ ꢈꢉꢊꢋ

ꢀꢁꢂꢃ ꢄꢃꢁ

ꢀꢁꢂꢃ ꢄꢃꢂ

ꢀꢁꢂꢃ ꢄꢃꢅ

Figure 16. 5V Output Power Loss

Figure 17. 5V_INDerating Curve,

No Heat Sink CH0 and CH3

Paralleled to 1V/24A CH1 and

CH2 Paralleled to 1.5V/10A

Figure 18. 5V_INDerating Curve,

with Heat Sink CH0 and CH3

Paralleled to 1V/24A CH1 and CH2

Paralleled to 1.5V/10A

Rev. B

25

For more information www.analog.com

LTM4671

APPLICATIONS INFORMATION

ꢀꢁꢂ

ꢀꢁꢁ

ꢀꢁ

ꢀ

ꢀꢁꢁ

ꢀꢁ

ꢀꢁꢂꢃ

ꢀꢁꢁꢂꢃꢄ

ꢀꢁ

ꢀꢁꢂꢃ

ꢀꢁꢁꢂꢃꢄ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢀꢁ ꢀꢁꢂ

ꢀꢁBꢂꢃꢄꢅ ꢅꢃꢁꢆꢃRꢀꢅꢇRꢃ ꢈꢉꢊꢋ

ꢀꢁꢂꢃ ꢄꢃꢅ

ꢀꢁꢂꢃ ꢄꢅꢆ

Figure 19. 12V_INDerating Curve, No Heat

Sink CH0 and CH3 Paralleled to 1V/24A

CH1 and CH2 Paralleled to 1.5V/10A

Figure 20. 12V_INDerating Curve, with Heat

Sink CH0 and CH3 Paralleled to 1V/24A

CH1 and CH2 Paralleled to 1.5V/10A

ꢀꢁꢂ

ꢀꢁꢁ

ꢀꢁ

ꢀ

ꢀꢁꢂ

ꢀꢁꢁ

ꢀꢁ

ꢀ

ꢀꢁꢂꢃ

ꢀꢁꢁꢂꢃꢄ

ꢀꢁꢂꢃ

ꢀꢁꢁꢂꢃꢄ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢀꢁ ꢀꢁꢂ

ꢀꢁBꢂꢃꢄꢅ ꢅꢃꢁꢆꢃRꢀꢅꢇRꢃ ꢈꢉꢊꢋ

ꢀꢁꢂꢃ ꢄꢅꢃ

ꢀꢁꢂꢃ ꢄꢅꢅ

Figure 21. 5V_INDerating Curve, No Heat

Sink CH0 and CH3 Paralleled to 1.8V/24A

CH1 and CH2 Paralleled to 3.3V/10A

Figure 22. 5V_INDerating Curve, with Heat

Sink CH0 and CH3 Paralleled to 1.8V/24A

CH1 and CH2 Paralleled to 3.3V/10A

ꢀꢁꢂ

ꢀꢁꢁ

ꢀꢁ

ꢀ

ꢀꢁꢂ

ꢀꢁꢁ

ꢀꢁ

ꢀ

ꢀꢁꢂꢃ

ꢀꢁꢁꢂꢃꢄ

ꢀꢁꢂꢃ

ꢀꢁꢁꢂꢃꢄ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢀꢁ ꢀꢁꢂ

ꢀꢁBꢂꢃꢄꢅ ꢅꢃꢁꢆꢃRꢀꢅꢇRꢃ ꢈꢉꢊꢋ

ꢀꢁꢂꢃ ꢄꢅꢆ

ꢀꢁꢂꢃ ꢄꢅꢀ

Figure 23. 12V_INDerating Curve, No Heat

Sink CH0 and CH3 Paralleled to 1.8V/24A

CH1 and CH2 Paralleled to 3.3V/10A

Figure 24. 12V_INDerating Curve, with Heat

Sink CH0 and CH3 Paralleled to 1.8V/24A

CH1 and CH2 Paralleled to 3.3V/10A

Rev. B

26

For more information www.analog.com

LTM4671

APPLICATIONS INFORMATION

ꢀꢁꢂ

ꢀꢁꢁ

ꢀꢁ

ꢀ

ꢀꢁꢁ

ꢀꢁ

ꢀꢁꢂꢃ

ꢀꢁꢁꢂꢃꢄ

ꢀꢁ

ꢀꢁꢂꢃ

ꢀꢁꢁꢂꢃꢄ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢀꢁ ꢀꢁꢂ

ꢀꢁBꢂꢃꢄꢅ ꢅꢃꢁꢆꢃRꢀꢅꢇRꢃ ꢈꢉꢊꢋ

ꢀꢁꢂꢃ ꢄꢅꢆ

ꢀꢁꢂꢃ ꢄꢅꢁ

Figure 25. 12V_INDerating Curve, No Heat

Sink CH0 and CH3 Paralleled to 3.3V/24A

CH1 and CH2 Paralleled to 5V/10A

Figure 26. 12V_INDerating Curve, with Heat

Sink CH0 and CH3 Paralleled to 3.3V/24A

CH1 and CH2 Paralleled to 5V/10A

ꢀꢁ

ꢀꢀ

ꢀꢁ

ꢀ

ꢀꢁ

ꢀꢀ

ꢀꢁ

ꢀ

ꢀꢁꢂꢃ

ꢀꢁꢁꢂꢃꢄ

ꢀ

ꢀꢁꢂꢃ

ꢀꢁꢁꢂꢃꢄ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢀꢁ ꢀꢁꢂ

ꢀꢁBꢂꢃꢄꢅ ꢅꢃꢁꢆꢃRꢀꢅꢇRꢃ ꢈꢉꢊꢋ

ꢀꢁꢂꢃ ꢄꢅꢆ

ꢀꢁꢂꢃ ꢄꢅꢂ

Figure 27. Power Loss Allowance vs

Ambient Temperature No Heat Sink

Figure 28. Power Loss Allowance vs

Ambient Temperature with Heat Sink

Rev. B

27

For more information www.analog.com

LTM4671

APPLICATIONS INFORMATION

Table 2. Different Output, Junction-to-Ambient Thermal Resistance (θ_JA)

DERATING CURVE

Figure 27

V

(V)

POWER LOSS CURVE

Figure 10 to Figure 16

AIRFLOW (LFM)

HEAT SINK

None

θ

JA(°C/W)

IN

5, 12

0

8.5

Figure 27

200

400

0

None

7

Figure 27

None

6.5

8

Figure 28

BGA Heat Sink

Figure 28

200

400

6

Figure 28

5.5

Table 3. Output Voltage Response vs Component Matrix (Refer to Figure 30) 0A to 4A Load Step Typical Measured Values

C_IN(CERAMIC)

C_OUT(CERAMIC)

C_OUT(BULK)

VENDORS VALUE

PART NUMBER

VENDORS

VALUE

PART NUMBER

VENDORS VALUE

PART NUMBER

Murata

22μF, 25V, X5R, 1206 GRT31CR61E226ME01L Murata

22μF, 25V, X5R, 1210 GRM32ER61E226KE15K Murata

47μF, 6.3V, X5R, 0805 GRM21BR60J476ME15K Panasonic 680μF, 6.3V, 25mΩ 6TPE330ML

100μF, 6.3V, X5R, 1210 GRM32ER60J107ME20L

Taiyo Yuden 22μF, 25V, X5R, 1206 TMK316BBJ226ML-T

Taiyo Yuden 47μF, 6.3V, X5R, 0805 JMK212BBJ476MG-T

Taiyo Yuden 100μF, 6.3V, X5R, 1210 JMK325BJ107MM-T

CH0 and CH3 Transient Response

C

OUT2

P-P

LOAD

STEP

(A)

LOAD STEP

SLEW RATE

(A/μs)

IN

OUT1

V

(CERAMIC) C * (CERAMIC) (BULK)

C

R

C

V

DERIVATION RECOVERY

R

OUT

IN

TH

FF

IN

FB

(V)

(μF)

(BULK)

100

(μF)

100 × 3

100

(μF)

(pF)

1500

1000

1500

1000

1500

1000

1500

1000

(kΩ)

5

8

(pF)

(V)

(mV)

79.7

76.3

83.7

80

TIME (μs)

(k)

1

22 × 2

NA

33

5, 12

30

40

30

40

50

3

10

90.9

60.4

40.2

30.1

19.1

13.3

1

330

NA

33

1.2

1.5

1.8

2.5

3.3

100 × 3

100

5

8

330

NA

33

100 × 3

100

5

8

90.4

89.7

103.8

99.1

147.3

203

330

NA

33

100 × 3

100

5

8

330

NA

100

8

100

8

CH1 and CH2 Transient Response

C

OUT2

P-P

LOAD

STEP

(A)

LOAD STEP

SLEW RATE

(A/μs)

IN

OUT1

V

(CERAMIC) C * (CERAMIC) (BULK)

C

R

C

V

DERIVATION RECOVERY

R

OUT

IN

TH

(pF)

TH

FF

IN

FB

(V)

(μF)

22

(BULK)

(μF)

NA

(kΩ)

(pF)

100

(V)

5, 12

12

(mV)

56.9

57.8

62.3

67.6

85.7

115

167

TIME (μs)

(k)

1

100

47 × 2

Internal Internal

50

60

70

1.25

10

90.9

60.4

40.2

30.1

19.1

13.3

8.25

1.2

100

1.5

1.8

100

2.5

3.3

100

5

100

12

*Optional

Rev. B

28

For more information www.analog.com

LTM4671

APPLICATIONS INFORMATION

SAFETY CONSIDERATIONS

•

Place a dedicated power ground layer underneath

the unit.

The LTM4671 modules do not provide galvanic isolation

from VIN to VOUT. There is no internal fuse. If required,

a slow blow fuse with a rating twice the maximum input

current needs to be provided to protect each unit from

catastrophic failure. The device does support thermal

shutdown and over current protection.

Tominimizetheviaconductionlossandreducemodule

thermal stress, use multiple vias for interconnection

between top layer and other power layers.

•

Do not put via directly on the pad, unless they are

capped or plated over.

Use a separated SGND ground copper area for com-

ponents connected to signal pins. Connect the SGND

to GND underneath the unit.

LAYOUT CHECKLIST/EXAMPLE

The high integration of LTM4671 makes the PCB board

layout very simple and easy. However, to optimize its

electrical and thermal performance, some layout con-

siderations are still necessary.

•

Forparallelmodules,tietheV ,V ,andCOMPpins

OUT FB

together. Useaninternallayertocloselyconnectthese

pins together. The TRACK pin can be tied a common

capacitor for regulator soft-start.

•

Use large PCB copper areas for high current paths,

including V , GND, V and V . It helps to

IN

OUT1

OUT2

•

Bringouttestpointsonthesignalpinsformonitoring.

minimizethePCBconductionlossandthermalstress.

Figure29givesagoodexampleoftherecommendedlayout.

•

Place high frequency ceramic input and output

capacitors next to the V , PGND and V

pins to

IN

OUT

minimize high frequency noise.

ꢊ

ꢌꢍꢎꢅ

ꢊ

ꢌꢍꢎꢃ

ꢇꢈꢉ

ꢊ

ꢌꢍꢎꢏ

ꢌꢍꢎꢐ

ꢇꢈꢉ

ꢊ

ꢋꢈ

ꢀꢁꢂꢃ ꢄꢅꢆ

Figure 29. Recommended PCB Layout

Rev. B

29

For more information www.analog.com

LTM4671

TYPICAL APPLICATIONS

V

OUT0

V

IN1

IN

OUT0

+

C

OUT0

C

VOSNS0

5V TO 20V

0.8V/12A

IN

SV

IN0

IN3

–

100µF ×4

22µF

182k

30.1k

13.3k

×4

FB0

RUN0

RUN1

RUN2

RUN3

V

OUT1

+

OUT1

VOSNS1

1.8V/5A

C

OUT1

FB1

47µF ×2

COMP0a

COMP0b

V

OUT2

V

OUT2

+

COMP1

COMP2

VOSNS2

3.3V/5A

C

LTM4671

OUT2

FB2

47µF ×2

COMP3a

COMP3b

V

OUT3

V

OUT3

+

C

VOSNS3

OUT3

TRACK/SS0

TRACK/SS1

TRACK/SS2

TRACK/SS3

1.0V/12A

–

100µF ×4

0.1μF

90.9k

FB3

0.1μF

PGOOD0

PGOOD1

PGOOD2

PGOOD3

4671 F30

Figure 30. 5V to 20V Input, Quad Output Design

Rev. B

30

For more information www.analog.com

LTM4671

TYPICAL APPLICATIONS

INTV

CC0

V

OUT0

IN1

OUT0

OUT3

IN

C

22µF

×4

5V TO 20V

1.0V/24A

IN

SV

IN0

IN3

C

+

OUT0

VOSNS0

VOSNS3

100µF ×6

RUN0

RUN1

RUN2

RUN3

–

VOSNS0

VOSNS3

COMP0a

COMP0b

90.0k

FB0

FB3

COMP1

COMP2

LTM4671

V

OUT1

OUT2

COMP3a

COMP3b

3.3V/10A

C

OUT1

+

TRACK/SS0

TRACK/SS1

TRACK/SS2

TRACK/SS3

VOSNS1

VOSNS2

47µF ×4

0.1μF

FB1

FB2

13.3k

0.1μF

PGOOD0

PGOOD1

PGOOD2

PGOOD3

4671 F31

400k

90°

INTV

CC0

CH0

180°

0°

CH1

180°

CH2

CH3

180°

90°

Phase Shift

Phase

270°

Figure 31. Parallel Operation with 1MHz Clock and Interleaved Phases

Rev. B

31

For more information www.analog.com

LTM4671

TYPICAL APPLICATIONS

ꢊ

ꢁꢂꢃꢐ

ꢊ

ꢔꢕꢋ

ꢔꢕ

ꢁꢂꢃꢐ

ꢢ

ꢀ

ꢁꢂꢃꢐ

ꢀ

ꢄꢄꢇꢈ

ꢉꢅ

ꢊꢁꢖꢕꢖꢐ

ꢒ.ꢒꢊ

ꢐ.ꢤꢊꢌꢋꢄꢎ

ꢔꢕ

ꢖꢊ

ꢔꢕꢐ

ꢔꢕꢒ

ꢣ

ꢋꢐꢐꢇꢈ ꢉꢅ

ꢋꢤꢄꢑ

ꢒꢐ.ꢋꢑ

ꢏꢐ.ꢅꢑ

ꢈBꢐ

Rꢂꢕꢐ

Rꢂꢕꢋ

Rꢂꢕꢄ

Rꢂꢕꢒ

ꢊ

ꢁꢂꢃꢋ

ꢋ.ꢤꢊꢌꢍꢎ

ꢊ

ꢁꢂꢃꢋ

ꢢ

ꢊꢁꢖꢕꢖꢋ

ꢀ

ꢁꢂꢃꢋ

ꢈBꢋ

ꢅꢆꢇꢈ ꢉꢄ

ꢀꢁꢗꢘꢐꢙ

ꢀꢁꢗꢘꢐꢚ

ꢊ

ꢠꢃꢗꢅꢏꢆꢋ

ꢁꢂꢃꢄ

ꢊ

ꢁꢂꢃꢄ

ꢢ

ꢀꢁꢗꢘꢋ

ꢀꢁꢗꢘꢄ

ꢊꢁꢖꢕꢖꢄ

ꢋ.ꢄꢊꢌꢍꢎ

ꢀ

ꢁꢂꢃꢄ

ꢈBꢄ

ꢅꢆꢇꢈ ꢉꢄ

ꢀꢁꢗꢘꢒꢙ

ꢀꢁꢗꢘꢒꢚ

ꢊ

ꢁꢂꢃꢒ

ꢊ

ꢁꢂꢃꢒ

ꢢ

ꢀ

ꢊꢁꢖꢕꢖꢒ

ꢁꢂꢃꢒ

ꢘꢛꢁꢁꢜꢐ

ꢘꢛꢁꢁꢜꢋ

ꢘꢛꢁꢁꢜꢄ

ꢘꢛꢁꢁꢜꢒ

ꢋ.ꢐꢊꢌꢋꢄꢎ

ꢣ

ꢋꢐꢐꢇꢈ ꢉꢅ

ꢓꢐ.ꢓꢑ

ꢏꢐ.ꢅꢑ

ꢒꢐ.ꢋꢑ

ꢈBꢒ

ꢃRꢎꢀꢡꢌꢖꢖꢐ

ꢃRꢎꢀꢡꢌꢖꢖꢋ

ꢐ.ꢋꢇꢈ

ꢏꢐ.ꢅꢑ ꢏꢐ.ꢅꢑ

ꢒꢐ.ꢋꢑ ꢒꢐ.ꢋꢑ

ꢃRꢎꢀꢡꢌꢖꢖꢄ

ꢃRꢎꢀꢡꢌꢖꢖꢒ

ꢅꢏꢆꢋ ꢈꢒꢄ

Figure 32. 3.3V_IN, 1.8V, 1.2V, 1V, 0.8V with Ratiometric Tracking

Rev. B

32

For more information www.analog.com

LTM4671

COMPONENT BGA PINOUT

PIN ID

A1

A2

A3

A4

A5

A6

A7

A8

FUNCTION

PIN ID

B1

B2

B3

B4

B5

B6

B7

B8

FUNCTION

PIN ID

C1

C2

C3

C4

C5

C6

C7

C8

C9

FUNCTION

PIN ID

D1

D2

D3

D4

D5

D6

D7

D8

D9

FUNCTION

PIN ID

E1

E2

E3

E4

E5

E6

E7

E8

E9

FUNCTION

V

OUT0

V

OUT0

V

OUT0

V

OUT0

V

OUT0

V

OUT0

V

OUT0

GND

PHMODE0

INTV

CC0

V

IN

SV

IN0

CLKOUT0

PGOOD0

GND

TSENSE0

GND

–

+

V

IN

V

IN

V

IN

V

IN

V

IN

A9

A10

A11

GND

B9

B10

B11

C10

C11

D10

D11

E10

E11

PIN ID

F1

F2

F3

F4

FUNCTION

GND

PIN ID

G1

G2

G3

G4

FUNCTION

GND

PIN ID

H1

H2

H3

H4

FUNCTION

PIN ID

J1

J2

J3

J4

FUNCTION

PIN ID

K1

K2

K3

K4

FUNCTION

GND

V

OUT1

V

OUT1

V

OUT1

V

OUT1

V

OUT1

V

OUT1

V

OUT1

V

OUT1

GND

F5

F6

GND

G5

G6

GND

H5

H6

GND

J5

J6

V

K5

K6

GND

IN

V

IN

F7

F8

F9

F10

F11

GND

VOSNS0

TRACK/SS0

FREQ0

RUN0

G7

G8

G9

G10

G11

TRACK/SS1

V0SNS0

FB0

GND

MODE/CLKIN0

H7

H8

H9

H10

H11

GND

PGOOD1

FB1

COMP0a

COMP0b

J7

J8

J9

J10

J11

GND

RUN1

GND

VOSNS1

COMP1

K7

K8

K9

K10

K11

GND

TMON

INTV

CC12

FREQ12

GND

–

+

PIN ID

L1

L2

L3

L4

FUNCTION

PIN ID

M1

M2

M3

M4

FUNCTION

PIN ID

N1

N2

N3

N4

FUNCTION

GND

PIN ID

P1

P2

P3

P4

FUNCTION

GND

PIN ID

R1

R2

R3

R4

FUNCTION

V

OUT2

V

OUT2

V

OUT2

V

OUT2

V

OUT2

OUT3

GND

OUT3

GND

L5

L6

L7

L8

L9

V

M5

M6

M7

M8

M9

GND

N5

N6

N7

N8

N9

GND

TRACK/SS2

COMP3b

COMP3a

FB3

P5

P6

P7

P8

P9

GND

CLKOUT3

RUN3

FREQ3

TRACK/SS3

V0SNS3

R5

R6

R7

R8

R9

GND

IN

V

PHMODE3

PGOOD3

MODE/CLKIN3

IN

GND

RUN2

MODE/CLKIN12

GND

PGOOD2

FB2

GND

COMP2

SV

IN3

+

–

L10

L11

V0SNS2

GND

M10

M11

N10

N11

P10

P11

R10

R11

V

IN

+

V0SNS3

GND

INTV

CC3

PIN ID

T1

T2

FUNCTION

PIN ID

U1

U2

FUNCTION

PIN ID

V1

V2

FUNCTION

PIN ID

W1

W2

FUNCTION

V

OUT3

V

OUT3

V

OUT3

V

OUT3

V

OUT3

V

OUT3

V

OUT3

V

OUT3

V

OUT3

V

OUT3

T3

U3

V3

W3

T4

T5

T6

T7

T8

T9

T10

T11

GND

U4

U5

U6

U7

U8

U9

U10

U11

GND

V4

V5

V6

V7

V8

V9

V10

V11

GND

W4

W5

W6

W7

W8

W9

W10

W11

GND

TSENSE3

GND

+

–

V

IN

V

IN

V

IN

V

IN

V

IN

Rev. B

33

For more information www.analog.com

LTM4671

PACKAGE DESCRIPTION

BGA Package

209-Lead (16mm × 9.50mm × 4.72mm)

ꢢReꢣeꢤeꢥꢦe ꢇꢃꢏ ꢎꢀꢋꢧ ꢗꢕꢨꢗꢙꢨꢑꢕꢖꢑ Rev Bꢩ

ꢡꢍꢍ ꢅꢛꢃꢍꢡ

ꢚ

ꢎꢍꢃꢐꢜꢇ ꢐ

ꢐ

ꢒ×

ꢶꢶꢶ ꢬ

ꢍ

ꢟ

ꢐꢒ

ꢠ

ꢡꢍꢍ ꢅꢛꢃꢍꢡ

ꢓ

ꢑꢑ ꢑꢗ

ꢘ

ꢙ

ꢚ

ꢖ

ꢕ

ꢔ

ꢓ

ꢒ

ꢑ

ꢄꢜꢅ ꢑ

ꢐ

B

ꢏ

ꢎ

ꢍ

ꢐꢑ

ꢄꢜꢅ ꢝꢐꢑꢞ

ꢏꢛRꢅꢍR

ꢦꢦꢦ

ꢬ

ꢔ

ꢮ

ꢮꢑ

ꢆꢛꢇꢎ

ꢏꢐꢄ

ꢌ

ꢡꢂBꢡꢃRꢐꢃꢍ

ꢊꢑ

ꢋ

ꢊ

ꢉ

ꢊꢒ

ꢎꢍꢃꢐꢜꢇ B

ꢎ

ꢌ

ꢈ

ꢇ

ꢆ

ꢅ

ꢄ

R

ꢃ

e

ꢭꢮ ꢢꢒꢗꢘ ꢄꢇꢐꢏꢍꢡꢩ

ꢯꢯꢯ

eee

ꢆ

ꢬ

ꢠ ꢟ

ꢂ

ꢁ

ꢀ

ꢎꢍꢃꢐꢜꢇ ꢐ

ꢒ×

ꢶꢶꢶ ꢬ

e

ꢮ

ꢄꢐꢏꢈꢐꢋꢍ ꢃꢛꢄ ꢁꢜꢍꢀ

ꢋ

ꢎꢍꢃꢐꢜꢇ B

ꢄꢐꢏꢈꢐꢋꢍ ꢡꢜꢎꢍ ꢁꢜꢍꢀ

ꢄꢐꢏꢈꢐꢋꢍ Bꢛꢃꢃꢛꢆ ꢁꢜꢍꢀ

ꢅꢛꢃꢍꢡꢪ

ꢚ.ꢒꢗ

ꢖ.ꢔꢗ

ꢕ.ꢖꢗ

ꢔ.ꢙꢗ

ꢔ.ꢗꢗ

ꢓ.ꢒꢗ

ꢒ.ꢔꢗ

ꢑ.ꢖꢗ

ꢗ.ꢙꢗ

ꢗ.ꢗꢗ

ꢗ.ꢙꢗ

ꢑ.ꢖꢗ

ꢒ.ꢔꢗ

ꢓ.ꢒꢗ

ꢔ.ꢗꢗ

ꢔ.ꢙꢗ

ꢕ.ꢖꢗ

ꢖ.ꢔꢗ

ꢚ.ꢒꢗ

ꢑ. ꢎꢜꢆꢍꢅꢡꢜꢛꢅꢜꢅꢋ ꢐꢅꢎ ꢃꢛꢇꢍRꢐꢅꢏꢜꢅꢋ ꢄꢍR ꢐꢡꢆꢍ ꢟꢑꢔ.ꢕꢆꢨꢑꢘꢘꢔ

ꢗ.ꢔꢗ ꢗ.ꢗꢒꢕ ꢭ ꢒꢗꢘꢵ

DIMENSIONS

ꢒ. ꢐꢇꢇ ꢎꢜꢆꢍꢅꢡꢜꢛꢅꢡ ꢐRꢍ ꢜꢅ ꢆꢜꢇꢇꢜꢆꢍꢃꢍRꢡ

SYMBOL

ꢐ

ꢐꢑ

ꢐꢒ

ꢮ

ꢮꢑ

ꢎ

ꢍ

e

ꢌ

ꢋ

ꢊꢑ

ꢊꢒ

ꢶꢶꢶ

ꢮꢮꢮ

ꢦꢦꢦ

ꢯꢯꢯ

eee

MIN

ꢔ.ꢕꢓ

ꢗ.ꢓꢗ

ꢔ.ꢒꢓ

ꢗ.ꢔꢕ

ꢗ.ꢓꢚ

NOM

ꢔ.ꢚꢒ

ꢗ.ꢔꢗ

ꢔ.ꢓꢒ

ꢗ.ꢕꢗ

ꢗ.ꢔꢗ

ꢑꢖ.ꢗꢗ

ꢘ.ꢕꢗ

ꢗ.ꢙꢗ

ꢑꢔ.ꢔꢗ

ꢙ.ꢗꢗ

ꢗ.ꢓꢒ

ꢔ.ꢗꢗ

MAX

NOTES

ꢓ

ꢔ

Bꢐꢇꢇ ꢎꢍꢡꢜꢋꢅꢐꢃꢜꢛꢅ ꢄꢍR ꢉꢍꢄꢘꢕ

ꢔ.ꢘꢑ

ꢗ.ꢕꢗ

ꢔ.ꢔꢑ

ꢗ.ꢕꢕ

ꢗ.ꢔꢓ

Bꢐꢇꢇ ꢊꢃ

ꢎꢍꢃꢐꢜꢇꢡ ꢛꢌ ꢄꢜꢅ ꢧꢑ ꢜꢎꢍꢅꢃꢜꢌꢜꢍR ꢐRꢍ ꢛꢄꢃꢜꢛꢅꢐꢇꢫ

Bꢂꢃ ꢆꢂꢡꢃ Bꢍ ꢇꢛꢏꢐꢃꢍꢎ ꢀꢜꢃꢊꢜꢅ ꢃꢊꢍ ꢬꢛꢅꢍ ꢜꢅꢎꢜꢏꢐꢃꢍꢎ.

ꢃꢊꢍ ꢄꢜꢅ ꢧꢑ ꢜꢎꢍꢅꢃꢜꢌꢜꢍR ꢆꢐꢟ Bꢍ ꢍꢜꢃꢊꢍR ꢐ ꢆꢛꢇꢎ ꢛR

ꢆꢐRꢈꢍꢎ ꢌꢍꢐꢃꢂRꢍ

Bꢐꢇꢇ ꢎꢜꢆꢍꢅꢡꢜꢛꢅ

ꢄꢐꢎ ꢎꢜꢆꢍꢅꢡꢜꢛꢅ

ꢕ. ꢄRꢜꢆꢐRꢟ ꢎꢐꢃꢂꢆ ꢨꢬꢨ ꢜꢡ ꢡꢍꢐꢃꢜꢅꢋ ꢄꢇꢐꢅꢍ

ꢖ

ꢄꢐꢏꢈꢐꢋꢍ Rꢛꢀ ꢐꢅꢎ ꢏꢛꢇꢂꢆꢅ ꢇꢐBꢍꢇꢜꢅꢋ ꢆꢐꢟ ꢁꢐRꢟ

ꢐꢆꢛꢅꢋ ꢰꢆꢱꢯꢲꢳe ꢄRꢛꢎꢂꢏꢃꢡ. Rꢍꢁꢜꢍꢀ ꢍꢐꢏꢊ ꢄꢐꢏꢈꢐꢋꢍ

ꢇꢐꢟꢛꢂꢃ ꢏꢐRꢍꢌꢂꢇꢇꢟ

!

ꢡꢂBꢡꢃRꢐꢃꢍ ꢃꢊꢈ

ꢆꢛꢇꢎ ꢏꢐꢄ ꢊꢃ

ꢗ.ꢑꢕ

ꢗ.ꢒꢗ

ꢗ.ꢑꢕ

ꢗ.ꢗꢙ

ꢇꢃꢆꢠꢠꢠꢠ

ꢰꢆꢱꢯꢲꢳe

ꢏꢛꢆꢄꢛꢅꢍꢅꢃ

ꢄꢜꢅ ꢝꢐꢑꢞ

ꢃꢛꢃꢐꢇ ꢅꢂꢆBꢍR ꢛꢌ Bꢐꢇꢇꢡꢪ ꢒꢗꢘ

ꢃRꢐꢟ ꢄꢜꢅ ꢑ

Bꢍꢁꢍꢇ

ꢄꢐꢏꢈꢐꢋꢍ ꢜꢅ ꢃRꢐꢟ ꢇꢛꢐꢎꢜꢅꢋ ꢛRꢜꢍꢅꢃꢐꢃꢜꢛꢅ

Bꢋꢐ ꢒꢗꢘ ꢗꢒꢑꢙ Rꢍꢁ B

ꢡꢂꢋꢋꢍꢡꢃꢍꢎ ꢄꢏB ꢇꢐꢟꢛꢂꢃ

ꢃꢛꢄ ꢁꢜꢍꢀ

Rev. B

34

For more information www.analog.com

LTM4671

REVISION HISTORY

REV

DATE

DESCRIPTION

PAGE NUMBER

A

08/19 Corrected value of Start-Up Waveform graphs from 2ms/DIV to 20ms/DIV

8

B

01/20 Added text and formula to set operating frequency

Added Temperature Monitering section

16

20, 21, 22

3, 4

Changed MAX Value of Line Regulation Accuracy to 0.05%

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications

35

subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

For more information www.analog.com

LTM4671

PACKAGE PHOTO

DESIGN RESOURCES

SUBJECT

DESCRIPTION

µModule Design and Manufacturing Resources

Design:

Manufacturing:

• Selector Guides

• Quick Start Guide

• Demo Boards and Gerber Files

• Free Simulation Tools

• PCB Design, Assembly and Manufacturing Guidelines

• Package and Board Level Reliability

µModule Regulator Products Search

1. Sort table of products by parameters and download the result as a spread sheet.

2. Search using the Quick Power Search parametric table.

Digital Power System Management

Analog Devices’ family of digital power supply management ICs are highly integrated solutions that

offer essential functions, including power supply monitoring, supervision, margining and sequencing,

and feature EEPROM for storing user configurations and fault logging.

RELATED PARTS

PART NUMBER DESCRIPTION

COMMENTS

LTM4644

LTM4633

Quad 4A Step-Down µModule Regulator

Triple 3A Step-Down µModule Regulator

4.5V ≤ V ≤ 14V, 0.6V ≤ V

≤ 5.5V, 9mm × 15mm × 5.01mm BGA

IN

OUT

4.7V ≤ V ≤ 16V, 0.8V ≤ V

and V

≤ 1.8V, 0.8V ≤ V

≤ 5.5V,

IN

OUT1

OUT2

OUT3

15mm × 15mm × 5.01mm BGA

LTM4622

Ultrathin, Dual 2.5A or Single 5A Step-Down µModule Regulator 3.6V ≤ V ≤ 20V, 0.6V ≤ V

≤ 5.5V, 6.25mm × 6.25mm × 1.82mm

IN

OUT

LGA, 6.25mm x 6.25mm × 2.42mm BGA

LTM4646

LTM4662

LTM4650A

Dual 10A or Single 20A Step-Down µModule Regulator

Dual 15A or Single 30A Step-Down µModule Regulator

Dual 25A or Single 50A Step-Down µModule Regulator

4.5V ≤ V ≤ 20V, 0.6V ≤ V

≤ 5.5V, 11.25mm × 15mm × 5.01mm BGA

≤ 5.5V, 11.25mm × 15mm × 5.74mm BGA

OUT

IN

OUT

4.5V ≤ V ≤ 20V, 0.6V ≤ V

IN

4.5V ≤ V ≤ 16V, 0.6V ≤ V

≤ 5.5V, 16mm × 16mm × 4.41mm LGA,

IN

OUT

16mm × 16mm × 5.01mm BGA

LTM4626

LTM4638

12A µModule Regulator

15A µModule Regulator

3.1V ≤ V ≤ 20V, 0.6V ≤ V

≤ 5.5V, 6.25mm × 6.25mm × 3.87mm BGA

≤ 5.5V, 6.25mm × 6.25mm × 5.02mm BGA

IN

OUT

3.1V ≤ V ≤ 20V, 0.6V ≤ V

IN

Rev. B

01/20

www.analog.com

36

For more information www.analog.com


型号：	LTM4671
厂家：	ADI
描述：	Quad DC/DC Î¼Module Regulator with Configurable Dual 12A, Dual 5A Output Array
文件：	总36页 (文件大小：1920K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTM4671 [ADI]

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