LTM4691 [ADI]
20VIN, Dual 5A or Single 10A Step-Down DC/DC μModule Regulator;
| 型号： | LTM4691 |
| 厂家： | 
ADI |
| 描述： | 20VIN, Dual 5A or Single 10A Step-Down DC/DC μModule Regulator |
| 文件： | 总24页 (文件大小：1814K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTM4705
20V , Dual 5A or Single 10A Step-Down
IN
DC/DC µModule Regulator
FEATURES
DESCRIPTION
2
The LTM®4705 is a complete dual 5A step-down switch-
ing mode µModule® (micromodule) regulator in a tiny
6.25mm × 7.5mm × 3.22mm BGA package. Included in
the package are the switching controller, power MOSFETs,
inductor and support components. Operating over an
input voltage range of 3.1V to 20V, the LTM4705 sup-
ports an output voltage range of 0.6V to 5.5V, set by a
single external resistor. Its high efficiency design delivers
dual 5A continuous output current. Only a few ceramic
input and output capacitors are needed.
n
Complete Solution in <1cm (Single-Sided PCB) or
2
0.5cm (Dual-Sided PCB)
Wide Input Voltage Range: 3.1V to 20V
0.6V to 5.5V Output Voltage
n
n
n
n
Dual 5A or Single 10A Output Current
1.5ꢀ Maximum Total Output Voltage Regulation
Error Over Load, Line and Temperature
Current Mode Control, Fast Transient Response
External Frequency Synchronization
Multiphase Parallelable with Current Sharing
Output Voltage Tracking and Soft-Start Capability
Selectable Burst Mode® Operation
n
n
n
n
n
n
n
n
The LTM4705 supports selectable Burst Mode operation
and output voltage tracking for supply rail sequencing.
Its high switching frequency and current mode control
enable a very fast transient response to line and load
changes without sacrificing stability.
Overvoltage Input and Overtemperature Protection
Power Good Indicators
6.25mm × 7.5mm × 3.22mm BGA package
Fault protection features include input overvoltage, output
overcurrent and overtemperature protection.
APPLICATIONS
n
General Purpose Point-of-Load Conversion
The LTM4705 is available with RoHS compliant
terminal finish.
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Telecom, Networking and Industrial Equipment
Medical Diagnostic Equipment
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All registered trademarks and trademarks are the property of their respective owners.
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Test and Debug Systems
TYPICAL APPLICATION
2.5V and 1.8V Dual Output DC/DC Step-Down µModule Regulator
12V Input, Efficiency vs Load Current
100
PGOOD1
PGOOD2
95
90
85
80
75
70
65
60
V
OUT1
V
V
V
OUT1
IN1
2.5V, 5A
V
IN
100µF
IN2
3.1V TO 20V
LTM4705
22µF
RUN1
RUN2
V
OUT2
V
OUT2
1.8V, 5A
100µF
INTV
COMP1
COMP2
CC
SYNC/MODE
TRACK/SS1
TRACK/SS2
FB1
FB2
V
V
= 2.5V
= 1.8V
OUT
OUT
19.1k
30.1k
FREQ
GND
0
1
2
3
4
5
4705 TA01a
LOAD CURRENT (A)
4705 TA01b
Rev. 0
1
Document Feedback
For more information www.analog.com
LTM4705
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
V
V
, V ................................................... –0.3V to 22V
OUT1 OUT2
RUN1, RUN2 .............................................. –0.3V to 22V
IN1 IN2
1
2
3
4
5
6
7
, V
, PGOOD1, PGOOD2................ –0.3V to 6V
FB2 COMP2 RUN2 FREQ RUN1 COMP1 FB1
A
B
C
D
E
F
SYNC/MODE
TRACK/SS1
TRACK/SS2
PGOOD2
INTV
CC
PGOOD1
INTV , TRACK/SS1, TRACK/SS2............ –0.3V to 3.6V
SYNC/MODE, COMP1, COMP2,
FB1, FB2,...............................................–0.3V to INTV
Operating Junction Temperature Range
(Note 2).................................................. –40°C to 125°C
Storage Temperature Range .................. –55°C to 125°C
Peak Solder Reflow Body Temperature.................260°C
CC
GND
SGND
GND
CC
V
IN2
V
IN1
GND
G
H
J
V
OUT2
V
OUT1
BGA PACKAGE
63-PIN (6.25mm × 7.5mm × 3.22mm)
T
= 125°C, θ
JCtop
= 22°C/W, θ
= 4°C/W,
JMAX
JCbottom
= 17°C/W, WEIGHT = 0.46g
θ
JA
ORDER INFORMATION
PART MARKING*
PACKAGE
TYPE
MSL
TEMPERATURE RANGE
(SEE NOTE 2)
PART NUMBER
LTM4705EY#PBF
LTM4705IY#PBF
PAD OR BALL FINISH
DEVICE
FINISH CODE
RATING
LTM4705Y
LTM4705Y
Au (RoHS)
e1
BGA
3
–40°C to 125°C
• Contact the factory for parts specified with wider operating temperature
ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures
• LGA and BGA Package and Tray Drawings
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range (Note 2), otherwise specifications are at TA = 25°C (Note 2), VIN1 = VIN2 = 12V, unless otherwise noted per the
typical application shown in Figure 23.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Switching Regulator Section: Per Channel
l
l
l
l
V
V
V
V
Input DC Voltage
Input DC Voltage
Output Voltage Range
3.1
1.5
20
20
V
V
V
V
IN1
3.1V < V < 20V
IN2
IN1
0.6
5.5
OUT(RANGE)
OUT(DC)
Output Voltage, Total Variation with
Line and Load
C
= 22µF, C
CC IN1
= 0A to 5A
= 100µF Ceramic, R = 40.2k, MODE =
IN2
1.477
1.5
1.523
IN
OUT
FB
INTV , V = V = 3.1V to 20V,
I
OUT
V
RUN Pin On Threshold
RUN Threshold Rising
RUN Threshold Falling
1.16
0.96
1.27
1
1.35
1.06
V
V
RUN
I
Input Supply Bias Current
V
V
= V = 12V, V = 1.5V, MODE = GND
OUT
15
79
75
mA
mA
µA
Q(VIN)
IN1
IN1
IN2
= V = 12V, V
= 1.5V, MODE = INTV , I
= 0.5A
IN2
OUT
CC OUT
Shutdown, RUN1 = RUN2 = 0
Rev. 0
2
For more information www.analog.com
LTM4705
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range (Note 2), otherwise specifications are at TA = 25°C (Note 2), VIN1 = VIN2 = 12V, unless otherwise noted per the
typical application shown in Figure 23.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
A
I
I
Input Supply Current
V
IN1
V
IN1
V
OUT
= V = 12V, V
= 1.5V, I = 5A
OUT
0.74
S(VIN)
IN2
OUT
l
l
Output Continuous Current Range
Line Regulation Accuracy
= V = 12V, V
= 1.5V (Note 3)
0
5
A
OUT(DC)
IN2
OUT
ΔV
OUT
/
= 1.5V, V = V = 3.1V to 20V, I = 0A
OUT
0.01
0.2
8
0.1
ꢀ/V
OUT(Line)
IN1
IN2
V
l
ΔV
OUT
/
Load Regulation Accuracy
Output Ripple Voltage
Turn-On Overshoot
V
= 1.5V, I
= 0A to 5A
0.8
ꢀ
mV
mV
ms
mV
µs
OUT(Load)
OUT
OUT
OUT
V
V
I
= 0A, C
= 100µF Ceramic, V = V = 12V, V
IN1 IN2
OUT(AC)
OUT
OUT
= 1.5V
ΔV
OUT(START)
I
= 0A, C
= 100µF Ceramic, V = V = 12V, V
15
5
OUT
OUT
IN1
IN2
OUT
= 1.5V
= 100µF Ceramic, No Load, TRACK/SS = 0.01µF, V
IN
t
Turn-On Time
C
OUT
= 12V, V
START
= 1.5V
OUT
ΔV
Peak Deviation for Dynamic Load
Load: 0ꢀ to 25ꢀ to 0ꢀ of Full Load, C
= 100µF
= 100µF
30
70
OUTLS
OUT
OUT
Ceramic, V = 12V, V
= 1.5V
IN
OUT
t
Settling Time for Dynamic Load Step Load: 0ꢀ to 25ꢀ to 0ꢀ of Full Load, C
Ceramic, V = 12V, V = 1.5V
SETTLE
IN
OUT
I
Output Current Limit
Voltage at V Pin
V
= 12V, V
= 1.5V
6
A
V
OUTPK
IN
OUT
OUT
l
V
I
= 0A, V
= 1.5V
0.592
0.6
0.608
30
FB
FB
OUT
I
Current at V Pin
(Note 4)
nA
kΩ
FB
FB
R
Resistor Between V
and V Pins
60
60.4
60.8
2.6
FBHI
OUT
FB
UVLO
V
Undervoltage Lockout
V
Falling
2.2
2.4
0.5
V
V
IN
IN
Hysteresis
I
t
t
t
Track Pin Soft-Start Pull-Up Current TRACK/SS = 0V
1.4
1000
30
µA
µs
ns
ns
TRACK/SS
ss
Internal Soft-Start Time
Minimum On-Time
Minimum Off-Time
PGOOD Trip Level
10ꢀ to 90ꢀ Rise Time (Note 4)
(Note 4)
(Note 4)
ON(MIN)
OFF(MIN)
100
V
V
FB
with Respect to Set Output
FB
FB
PGOOD
V
V
Ramping Negative
Ramping Positive
–10
3.1
–8
8
–5
10
ꢀ
ꢀ
R
PGOOD Pull-Down Resistance
10mA Load
= V = 3.6V to 20V
25
3.3
1.3
Ω
V
PGOOD
INTVCC
INTVCC
V
Internal V Voltage
V
3.5
CC
IN1
IN2
V
INTV Load Regulation
I
= 0mA to 50mA
CC
ꢀ
CC
Load Reg
FREQ
Default Switching Frequency
1
MHz
V
SYNC/MODE High Threshold
SYNC/MODE Low Threshold
MODE V
MODE V
1
V
V
SYNC/MODE
IH
IL
0.3
I
SYNC/MODE Input Current
MODE = 0V
MODE = INTV
1.5
–1.5
µA
µA
MODE
CC
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
ambient temperature consistent with these specifications is determined by
specific operating conditions in conjunction with board layout, the rated
package thermal resistance and other environmental factors.
Note 3: See output current derating curves for different V , V
and T .
A
IN OUT
Note 2: The LTM4705 is tested under pulsed load conditions such that T ≈
J
Note 4: 100ꢀ tested at wafer level.
T . The LTM4705E is guaranteed to meet performance specifications over
A
Note 5: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
the 0°C to 125°C internal operating temperature range. Specifications over
the full –40°C to 125°C internal operating temperature range are assured
by design, characterization and correlation with statistical process controls.
The LTM4705I is guaranteed to meet specifications over the full –40°C
to 125°C internal operating temperature range. Note that the maximum
Rev. 0
3
For more information www.analog.com
LTM4705
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Load Current
from 5VIN
Efficiency vs Load Current
from 12VIN
Burst Mode Efficiency, 12VIN,
1.5VOUT
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
100
90
80
70
60
50
40
30
20
10
0
1.0V
1.2V
1.5V
1.8V
2.5V
3.3V
5.0V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
1.0V
1.2V
1.5V
1.8V
2.5V
3.3V
OUT
OUT
OUT
OUT
OUT
OUT
Burst Mode OPERATION
CCM
0
1
2
3
4
5
0
1
2
3
4
5
0.01
0.1
1
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (mA)
4705 G01
4705 G03
4705 G02
1.0V Output Transient Response
1.2V Output Transient Response
1.5V Output Transient Response
V
V
V
OUT
OUT
OUT
(AC-COUPLED)
50mV/DIV
(AC-COUPLED)
50mV/DIV
(AC-COUPLED)
50mV/DIV
LOAD STEP
500mA/DIV
LOAD STEP
500mA/DIV
LOAD STEP
500mA/DIV
4705 G06
4705 G04
4705 G05
50μs/DIV
50μs/DIV
50μs/DIV
V
C
C
= 12V, V
OUT
= 100pF
= 1.5V, f = 1MHz
SW
V
C
C
= 12V, V
OUT
OUT
= 100pF
= 1V, f = 1MHz
SW
V
C
C
= 12V, V
OUT
OUT
= 100pF
FF
= 1.2V, f = 1MHz
SW
IN
OUT
= 2× 47μF + 10μF CERAMIC CAPACITORS
IN
IN
= 2× 47μF + 10μF CERAMIC CAPACITORS
= 2× 47μF + 10μF CERAMIC CAPACITORS
FF
FF
1.25A (25%) LOAD STEP, 1A/μs
1.25A (25%) LOAD STEP, 1A/μs
1.25A (25%) LOAD STEP, 1A/μs
1.8V Output Transient Response
2.5V Output Transient Response
3.3V Output Transient Response
V
V
V
OUT
OUT
OUT
(AC-COUPLED)
100mV/DIV
(AC-COUPLED)
50mV/DIV
(AC-COUPLED)
50mV/DIV
LOAD STEP
500mA/DIV
LOAD STEP
500mA/DIV
LOAD STEP
500mA/DIV
4705 G09
4705 G07
4705 G08
50μs/DIV
50μs/DIV
50μs/DIV
V
C
C
= 12V, V
OUT
= 100pF
= 3.3V, f = 1MHz
SW
V
C
C
= 12V, V
OUT
OUT
= 100pF
= 1.8V, f = 1MHz
SW
V
C
C
= 12V, V
OUT
= 100pF
FF
= 2.5V, f = 1MHz
SW
IN
OUT
= 2× 47μF + 10μF CERAMIC CAPACITORS
IN
IN
OUT
= 2× 47μF + 10μF CERAMIC CAPACITORS
= 2× 47μF + 10μF CERAMIC CAPACITORS
FF
FF
1.25A (25%) LOAD STEP, 1A/μs
1.25A (25%) LOAD STEP, 1A/μs
1.25A (25%) LOAD STEP, 1A/μs
Rev. 0
4
For more information www.analog.com
LTM4705
TYPICAL PERFORMANCE CHARACTERISTICS
5V Output Transient Response
Short-Circuit with No Load Current
Short-Circuit with 5A Load Current
I
IN
V
OUT
I
IN
500mA/DIV
(AC-COUPLED)
100mV/DIV
500mA/DIV
LOAD STEP
500mA/DIV
V
OUT
V
OUT
500mV/DIV
500mV/DIV
4705 G10
50μs/DIV
4705 G11
4705 G12
20µs/DIV
V
C
C
= 12V, V
OUT
OUT
= 100pF
= 5V, f = 1MHz
50µs/DIV
IN
SW
= 2× 47μF + 10μF CERAMIC CAPACITORS
V
C
C
= 12V, V
OUT
= 100pF
= 1.0V, f = 1MHz
OUT SW
V
C
C
= 12V, V
OUT
= 100pF
= 1V, f = 1MHz
OUT SW
IN
IN
FF
= 2× 47µF + 10µF CERAMIC CAPACITORS
= 2× 47µF + 10µF CERAMIC CAPACITORS
1.25A (25%) LOAD STEP, 1A/μs
FF
FF
Steady-State Output Voltage Ripple
Start-Up into Pre-Biased Output
RUN
10V/DIV
V
OUT
PGOOD
5V/DIV
(AC-COUPLED)
5mV/DIV
V
OUT
2V/DIV
I
IN
500mV/DIV
4705 G13
500ns/DIV
= 1V, f = 1MHz
4705 G14
20ms/DIV
V
C
C
= 12V, V
OUT
OUT
= 100pF
IN
SW
V
C
C
= 12V, V
OUT
= 100pF
= 3.3V, f = 1MHz,
OUT SW
= 2× 47µF + 10µF CERAMIC CAPACITORS
IN
= 2× 47µF + 10µF CERAMIC CAPACITORS
FF
FF
Start-Up with No Load Current
Start-Up with 5A Load Current
RUN
10V/DIV
RUN
10V/DIV
PGOOD
5V/DIV
PGOOD
5V/DIV
V
V
OUT
OUT
1V/DIV
1V/DIV
I
I
IN
IN
500mV/DIV
500mV/DIV
4705 G15
4705 G16
20ms/DIV
20ms/DIV
V
C
C
= 12V, V
OUT
= 100pF
= 1V, f = 1MHz,
V
C
C
= 12V, V
OUT
= 100pF
FF
= 1V, f = 1MHz,
OUT SW
IN
OUT
SW
IN
= 2× 47µF + 10µF CERAMIC CAPACITORS
= 2× 47µF + 10µF CERAMIC CAPACITORS
FF
Rev. 0
5
For more information www.analog.com
LTM4705
PIN FUNCTIONS
PACKAGE ROW AND COLUMN LABELING MAY VARY
SYNC/MODE (B5): Mode Select and External
Synchronization Input. Tie this pin to ground to force
continuous synchronous operation at all output loads.
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
FREQ (A4): Frequency is set internally to 1MHz. An exter-
nal resistor can be placed from this pin to GND to increase
frequency, or from this pin to INTVCC to reduce frequency.
See the Applications Information section for frequency
adjustment.
Floating this pin or tying it to INTV enables high effi-
CC
ciency Burst Mode operation at light loads. Drive this
pin with a clock to synchronize the LTM4705 switching
frequency. An internal phase-locked loop will force the
bottom power N-channel MOSFET’s turn on signal to be
synchronized with the rising edge of the clock signal.
When this pin is driven with a clock, forced continuous
mode is automatically selected.
RUN1 (A5), RUN2 (A3): Run Control Input of Each
Switching Mode Regulator Channel. Enables chip opera-
tion by tying RUN above 1.27V. Tying this pin below 1V
shuts down the specific regulator channel. Do not float
this pin.
PGOOD1 (B6), PGOOD2 (B2): Output Power Good with
Open-Drain Logic of Each Switching Mode Regulator
Channel. PGOOD is pulled to ground when the voltage
on the FB pin is not within 8ꢀ (typical) of the internal
0.6V reference.
COMP1 (A6), COMP2 (A2): Current Control Threshold
and Error Amplifier Compensation Point of each Switching
Mode Regulator Channel. The current comparator’s trip
threshold is linearly proportional to this voltage, whose
normal range is from 0.3V to 1.8V. Tie the COMP pins
together for parallel operation. The device is internally
compensated.
TRACK/SS1 (B7), TRACK/SS2 (B1): Output Tracking and
Soft-Start Pin of Each Switching Mode Regulator Channel.
It allows the user to control the rise time of the output
voltage. Putting a voltage below 0.6V on this pin bypasses
the internal reference input to the error amplifier, instead
it servos the FB pin to the TRACK voltage. Above 0.6V,
the tracking function stops and the internal reference
resumes control of the error amplifier. There’s an internal
FB1 (A7), FB2 (A1): The Negative Input of the Error
Amplifier for Each Switching Mode Regulator Channel.
Internally, this pin is connected to VOUT with a 60.4k preci-
sion resistor. Different output voltages can be programmed
with an additional resistor between FB and GND pins. In
PolyPhase operation, tying the FB pins together allows
for parallel operation. See the Applications Information
section for details.
1.4µA pull-up current from INTV on this pin, so putting
CC
a capacitor here provides soft-start function.
SGND (C4): Signal Ground Connection. Tie to GND with
minimum distance. Connect COMP component, MODE,
TRACK/SS component, FB resistor to this pin as needed.
GND (B3, C2, C3, C5, C6, D4, E1, E4, E7, F1 - F7, G1
- G7, H4, J4): Power Ground Pins for Both Input and
Output Returns.
V
(C7, D5 - D7, E5 - E6), V (C1, D1 - D3, E2 - E3):
IN2
IN1
Power Input Pins. Apply input voltage between these pins
and GND pins. Recommend placing input decoupling
capacitance directly between BOTH V and V pins
INTVCC (B4): Internal 3.3V Regulator Output of the
Switching Mode Regulator Channel. The internal power
drivers and control circuits are powered from this voltage.
This pin is internally decoupled to GND with a 2.2µF low
ESR ceramic capacitor. No additional external decoupling
capacitor is needed.
IN1
IN2
and GND pins. Please note the module internal control cir-
cuitry is running off V . Channel 2 will not work without
IN1
a voltage higher than 3.1V present at V
.
IN1
V
OUT1
(H5 - H7, J5 - J7), V
(H1 - H3, J1 - J3): Power
OUT2
Output Pins of Each Switching Mode Regulator. Apply out-
put load between these pins and GND pins. Recommend
placing output decoupling capacitance directly between
these pins and GND pins.
Rev. 0
6
For more information www.analog.com
LTM4705
BLOCK DIAGRAM
V
OUT1
V
OUT2
60.4k
60.4k
10k
10k
PGOOD1
PGOOD2
FB1
INTV
INTV
CC
60.4k
FB2
INTV
CC
40.2k
CC
V
IN1
V
IN
2.2µF
3.1V TO 20V
0.1µF
22µF
SYNC/MODE
TRACK/SS1
1µH
V
1.2V
5A
V
OUT1
OUT1
0.1µF
0.1µF
100µF
TRACK/SS2
RUN1
GND
RUN2
V
IN2
0.1µF
22µF
COMP1
POWER CONTROL
INTERNAL
COMP
1µH
V
1.5V
5A
V
OUT2
OUT2
GND
COMP2
FREQ
100µF
INTERNAL
COMP
324k
4705 F01
Figure 1. Simplified LTM4705 Block Diagram
DECOUPLING REQUIREMENTS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
C
IN
External Input Capacitor Requirement
IN
I
= 5A
10
22
µF
OUT
(V = 3.1V to 20V, V
= 1.5V)
OUT
C
External Output Capacitor Requirement
(V = 3.1V to 20V, V = 1.5V)
I
= 5A
47
100
µF
OUT
OUT
IN
OUT
Rev. 0
7
For more information www.analog.com
LTM4705
OPERATION
The LTM4705 is a dual output standalone nonisolated
switch mode DC/DC power supply. It can deliver two 5A
DC outputs with few external input and output ceramic
capacitors. This module provides dual precisely regulated
output voltages programmable via two external resistors
from 0.6V to 5.5V over 3.1V to 20V input voltage range.
Both channels share the same clock and run 180° out
of phase. The typical application schematic is shown
in Figure 23.
wide range of output capacitors, even with all ceramic
output capacitors.
Current mode control provides cycle-by-cycle fast current
limiting. An internal overvoltage and undervoltage com-
parators pull the open-drain PGOOD output low if the out-
put feedback voltage exits a 8ꢀ window around the regu-
lation point. Furthermore, the input overvoltage protection
will be activated by shutting down both power MOSFETs
when V rises above 22.5V to protect internal devices.
IN
The LTM4705 contains an integrated controlled on-time
valley current mode regulator, power MOSFETs, inductor
and other supporting discrete components. The default
switching frequency is 1MHz. For output voltages between
2.5V and 5V, an external resistor is required between
FREQ and GND pins to set the operating frequency to
higher frequency to optimize inductor current ripple. For
switching noise-sensitive applications, the µModule can
be externally synchronized to a clock. See the Applications
Information section.
Multiphase operation can be easily employed by con-
necting the SYNC pin to an external oscillator. Multiple
LTM4705s can be paralleled to run simultaneously with
good current sharing guaranteed by the current mode
control loop.
Pulling the RUN pin below 1V forces the controller into
its shutdown state, turning off both power MOSFETs and
most of the internal control circuitry. At light load currents,
burst mode operation can be enabled to achieve higher
efficiency compared to continuous current mode (CCM)
With current mode control and internal feedback loop
compensation, the LTM4705 module has sufficient sta-
bility margins and good transient performance with a
by setting MODE pin to INTV . The TRACK/SS pin is used
CC
for power supply tracking and soft-start programming.
See the Applications Information section.
APPLICATIONS INFORMATION
The typical LTM4705 application circuit is shown in
Figure 23. External component selection is primarily deter-
mined by the input voltage, the output voltage and the
maximum load current. Refer to Table 8 for specific exter-
nal capacitor requirements for a particular application.
the minimum on-time limit imposes a minimum duty cycle
of the converter which can be calculated by Equation 2.
D
MIN
= t
• f
(2)
is the minimum on-time, 30ns typical for
ON(MIN) SW
where t
ON(MIN)
LTM4705. In the rare cases where the minimum duty
cycle is surpassed, the output voltage will still remain
in regulation, but the switching frequency will decrease
from its programmed value. Note that additional thermal
derating may be applied. See the Thermal Considerations
and Output Current Derating section in this data sheet.
V to V
Step-Down Ratios
IN
OUT
There are restrictions in the maximum VIN and VOUT step
down ratio that can be achieved for a given input voltage due
to the minimum off-time and minimum on-time limits of the
regulator. The minimum off-time limit imposes a maximum
duty cycle which can be calculated by Equation 1.
Output Voltage Programming
D
MAX
= 1 – t
• f
(1)
OFF(MIN) SW
The PWM controller has an internal 0.6V reference volt-
age. As shown in the Block Diagram, a 60.4k 0.5ꢀ internal
where tOFF(MIN) is the minimum off-time, 100ns typical for
LTM4705, and fSW is the switching frequency. Conversely
feedback resistor connects V
and FB pins together.
OUT
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Adding a resistor R from FB pin to GND programs the
step transient. Multiphase operation will reduce effec-
tive output ripple as a function of the number of phases.
Application Note 77 discusses this noise reduction versus
output ripple current cancellation, but the output capaci-
tance will be more a function of stability and transient
response. The Analog Devices LTpowerCAD® Design Tool
is available to download online for output ripple, stability
and transient response analysis and calculating the output
ripple reduction as the number of phases implemented
increases by N times.
FB
output voltage (Equation 3).
0.6V
VOUT – 0.6V
RFB
=
• 60.4k
(3)
Table 1. VFB Resistor Table vs Various Output Voltages
(V) 0.6 1.0 1.2 1.5 1.8 2.5 3.3
OPEN 90.9 60.4 40.2 30.1 19.1 13.3
V
OUT
5.0
8.25
R
(k)
FB
For parallel operation of N-channels LTM4705, Equation 4
can be used to solve for R :
FB
Burst Mode Operation
0.6V
VOUT – 0.6V
60.4k
N
In applications where high efficiency at intermediate cur-
rent is preferred over lower output voltage ripple, Burst
Mode operation could be used by connecting SYNC/
RFB
=
•
(4)
MODE pin to INTV to improve light load efficiency. In
Input Decoupling Capacitors
CC
Burst Mode operation, a current reversal comparator
The LTM4705 module should be connected to a low
AC-impedance DC source. For each regulator channel,
one piece 10µF input ceramic capacitor is required for
RMS ripple current decoupling. A bulk input capacitor is
only needed when the input source impedance is com-
promised by long inductive leads, traces or not enough
source capacitance. The bulk capacitor can be an electro-
lytic aluminum capacitor and/or polymer capacitor.
(I ) detects the negative inductor current and shuts off
REV
the bottom power MOSFET, resulting in discontinuous
operation and increased efficiency. Both power MOSFETs
will remain off and the output capacitor will supply the
load current until the COMP voltage rises above the zero
current level to initiate another cycle.
Forced Continuous Current Mode (CCM) Operation
Without considering the inductor current ripple, for each
output, the RMS current of the input capacitor can be
estimated using Equation 5.
In applications where fixed frequency operation is more
critical than low current efficiency, and where the low-
est output ripple is desired, forced continuous opera-
tion should be used. Forced continuous operation can
be enabled by tying the SYNC/MODE pin to GND. In this
mode, inductor current is allowed to reverse during low
output loads, the COMP voltage is in control of the cur-
rent comparator threshold throughout. During start-up,
forced continuous mode is disabled and inductor current
is prevented from reversing until the LTM4705’s output
voltage is in regulation.
IOUT(MAX)
ICIN(RMS)
=
• D• 1–D
(5)
(
)
η%
where is the estimated efficiency of the power module.
Output Decoupling Capacitors
With an optimized high frequency, high bandwidth design,
only a single piece of 47µF low ESR output ceramic capac-
itor is required for each LTM4705 output to achieve low
output voltage ripple and very good transient response.
Additional output filtering may be required by the system
designer, if further reduction of output ripples or dynamic
transient spikes is required. Table 8 shows a matrix of dif-
ferent output voltages and output capacitors to minimize
the voltage droop and overshoot during a 2.5A (50%) load
Operating Frequency
The operating frequency of the LTM4705 is optimized
to achieve the compact package size and the minimum
output ripple voltage while still keeping high efficiency.
The default operating frequency is internally set to 1MHz.
In most applications, no additional frequency adjusting
is required.
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If any operating frequency other than 1MHz is required by
can be paralleled to run out of phase to provide more
output current without increasing input and output volt-
age ripples.
application, the operating frequency can be increased by
adding a resistor, R , between the FREQ pin and GND,
FSET
as shown in Figure 26. The operating frequency can be
calculated by Equation 6.
A multiphase power supply significantly reduces the
amount of ripple current in both the input and output
capacitors. The RMS input ripple current is reduced by,
and the effective ripple frequency is multiplied by, the
number of phases used (assuming that the input volt-
age is greater than the number of phases used times
the output voltage). The output ripple amplitude is also
reduced by the number of phases used when all of the
outputs are tied together to achieve a single high output
current design.
3.2e11
f Hz =
( )
(6)
324k ||R
Ω
FSET ( )
To reduce switching current ripple, 1.5MHz to 2.5MHz
operating frequency can be used for 2.5V to 5V output
with R
to GND.
FSET
Table 2.
0.6V TO
1.8V
V
f
2.5V
3.3V
2MHz
324kΩ
5V
OUT
The two switching mode regulator channels inside the
LTM4705 are internally set to operate 180° out of phase.
Multiple LTM4705s could easily operate 90 degrees,
60 degrees or 45 degrees shift which corresponds to
4-phase, 6-phase or 8-phase operation by letting SYNC/
MODE of the LTM4705 synchronize to an external multi-
phase oscillator like LTC6902. Figure 2 shows a 4-phase
design example for clock phasing.
1MHz
Open
1.5MHz
649kΩ
2.5MHz
215kΩ
SW
R
FSET
The operating frequency can also be decreased by adding
a resistor between the FREQ pin and INTV , calculated as:
CC
5.67e11
f Hz = 1MHz –
( )
(7)
R
Ω
FSET ( )
33.2k
The programmable operating frequency range is from
800kHz to 3MHz.
0°
+
3.3V INTV
V
SET
SYNC/MODE
SYNC/MODE
V
V
CC
OUT1
180°
PH
MOD
OUT2
Frequency Synchronization
LTC6902
90°
0°
V
V
OUT1
DIV
OUT1
OUT2
The power module has a phase-locked loop comprised of
an internal voltage controlled oscillator and a phase detec-
tor. This allows the internal bottom MOSFET turn-on to
be locked to the rising edge of the external clock. A pulse
detection circuit is used to detect a clock on the SYNC/
MODE pin to turn on the phase locked loop. The pulse
width of the clock has to be at least 100ns. The clock high
level must be above 1V and clock low level below 0.3V.
The presence of an external clock will place both regulator
channels into forced continuous mode operation. During
the start-up of the regulator, the phase-locked loop func-
tion is disabled.
90°
270°
GND
OUT2
4705 F02
Figure 2. Example of Clock Phasing for 4-Phase
Operation with LTC6902
The LTM4705 is an inherently current mode controlled
device, so parallel modules will have very good current
sharing. This will balance the thermals on the design.
Please tie RUN, TRACK/SS, FB and COMP pin of each
paralleling channel together. Figure 24 shows an example
of parallel operation and pin connection.
INPUT RMS Ripple Current Cancellation
Multiphase Operation
Application Note 77 provides a detailed explanation of
multiphase operation. The input RMS ripple current can-
cellation mathematical derivations are presented, and
For output loads that demand more than 5A of current,
two outputs in the LTM4705 or even multiple LTM4705s
Rev. 0
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APPLICATIONS INFORMATION
a graph is displayed representing the RMS ripple cur-
rent reduction as a function of the number of interleaved
phases. Figure 3 shows this graph.
Output voltage tracking can also be programmed
externally using the TRACK/SS pin. The output can be
tracked up and down with another regulator. Figure 4 and
Figure 5 show an example waveform and schematic of a
Ratiometric tracking where the slave regulator’s output
slew rate is proportional to the master’s.
Soft-Start and Output Voltage Tracking
The TRACK/SS pin provides a means to either soft-start
the regulator or track it to a different power supply. A
capacitor on the TRACK/SS pin will program the ramp rate
of the output voltage. An internal 1.4µA current source
will charge up the external soft-start capacitor towards
Since the slave regulator’s TRACK/SS is connected to
the master’s output through a R
/R
resistor
TR(TOP) TR(BOT)
divider and its voltage used to regulate the slave output
voltage when TRACK/SS voltage is below 0.6V, the slave
output voltage and the master output voltage should sat-
isfy Equation 9 during the start-up.
INTV voltage. When the TRACK/SS voltage is below
CC
0.6V, it will take over the internal 0.6V reference voltage
to control the output voltage. The total soft-start time can
be calculated by Equation 8.
RFB(SL)
VOUT(SL)
•
=
RFB(SL) +60.4k
RTR(TOP)
CSS
1.4µA
(9)
tSS = 0.6 •
(8)
VOUT(MA)
•
RTR(TOP) +RTR(BOT)
where CSS is the capacitance on the TRACK/SS pin.
Current foldback and force continuous mode are disabled
during the soft-start process.
The RFB(SL) is the feedback resistor and the RTR(TOP)
TR(BOT)
the slave regulator, as shown in Figure 5.
/
R
is the resistor divider on the TRACK/SS pin of
0.60
1-PHASE
2-PHASE
0.55
3-PHASE
4-PHASE
6-PHASE
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY FACTOR (V /V
)
4705 F03
OUT IN
Figure 3. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle
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The TRACK pins will have the 1.5µA current source on
when a resistive divider is used to implement tracking on
that specific channel. This will impose an offset on the
TRACK pin input. Smaller value resistors with the same
ratios as the resistor values calculated from the above
equation can be used. For example, where the 60.4k is
used then a 6.04k can be used to reduce the TRACK pin
offset to a negligible value.
MASTER OUTPUT
SLAVE OUTPUT
The Coincident output tracking can be recognized as a
special Ratiometric output tracking which the master’s
output slew rate (MR) is the same as the slave’s output
slew rate (SR), as waveform shown in Figure 6.
TIME
4705 F04
Figure 4. Output Ratiometric Tracking Waveform
Following Equation 9, the master’s output slew rate (MR)
and the slave’s output slew rate (SR) in Volts/Time is
determined by Equation 10.
MASTER OUTPUT
SLAVE OUTPUT
RFB(SL)
RFB(SL) +60.4k
RTR(BOT)
MR
SR
(10)
=
RTR(TOP) +RTR(BOT)
For example, VOUT(MA) = 1.5V, MR = 1.5V/1ms and
= 1.2V, SR = 1.2V/1ms as shown in Figure 5.
TIME
V
OUT(SL)
4705 F06
From the equation, we could solve out that R
=
TR(TOP)
Figure 6. Output Coincident Tracking Waveform
60.4k and R
= 40.2k is a good combination for the
TR(BOT)
Ratiometric tracking.
From Equation 10, we could easily find out that, in the
Coincident tracking, the slave regulator’s TRACK/SS pin
resistor divider is always the same as its feedback divider
(Equation 11).
PGOOD1
PGOOD2
V
V
OUT1
V
OUT1
IN1
1.5V, 5A
V
IN
100µF
V
IN2
3.1V TO 20V
RFB(SL)
RTR(BOT)
22µF
25V
LTM4705
RUN1
RUN2
(11)
=
V
OUT2
V
RFB(SL) +60.4k RTR(TOP) +RTR(BOT)
OUT2
1.2V, 5A
100µF
INTV
COMP1
COMP2
CC
For example, R
= 60.4k and R
= 60.4k is a
SYNC/MODE
TRACK/SS1
TRACK/SS2
TR(TOP)
TR(BOT)
good combination for Coincident tracking for V
=
FB1
FB2
OUT(MA)
60.4k
V
OUT1
1.5V and V
= 1.2V application.
OUT(SL)
0.1µF
40.2k
60.4k
FREQ
GND
40.2k
Power Good
4705 F05
The PGOOD pins are open drain pins that can be used to
monitor valid output voltage regulation. This pin monitors
a 8% window around the regulation point. A resistor can
be pulled up to a particular supply voltage for monitoring.
To prevent unwanted PGOOD glitches during transients
Figure 5. Example Schematic of Ratiometric
Output Voltage Tracking
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APPLICATIONS INFORMATION
or dynamic V
changes, the LTM4705’s PGOOD falling
monitors each VIN pin for an overvoltage condition. When
IN
OUT
edge includes a blanking delay of approximately 40μs.
V rises above 22.5V, the regulator suspends operation
by shutting off both power MOSFETs on the correspond-
Stability compensation
ing channel. Once V drops below 21.5V, the regulator
IN
immediately resumes normal operation. The regulator
executes its soft-start function when exiting an overvolt-
age condition.
The LTM4705 module internal compensation loop is
designed and optimized for low ESR ceramic output
capacitors only applications. Please note that for appli-
cations that need to achieve high bandwidth control loop
compensation with enough phase margin, a feed forward
capacitor between 33pF – 100pF is recommended from
Thermal Considerations and Output Current Derating
The thermal resistances reported in the Pin Configuration
section of the data sheet are consistent with those param-
eters defined by JESD51-9 and are intended for use with
finite element analysis (FEA) software modeling tools that
leverage the outcome of thermal modeling, simulation,
and correlation to hardware evaluation performed on a
µModule package mounted to a hardware test board—
also defined by JESD51-9 (“Test Boards for Area Array
Surface Mount Package Thermal Measurements”). The
motivation for providing these thermal coefficients in
found in JESD51-12 (“Guidelines for Reporting and Using
Electronic Package Thermal Information”).
V
to V pin. Table 8 is provided for most application
OUT
FB
requirements. The LTpowerCAD Design Tool is available
to download online for control loop optimization.
RUN Enable
Pulling the RUN pin to ground forces the LTM4705 into
its shutdown state, turning off both power MOSFETs and
most of its internal control circuitry. Tying the RUN pin
voltage above 1.27V will turn on the entire chip.
Pre-Biased Output Start-Up
Many designers may opt to use laboratory equipment and
a test vehicle such as the demo board to anticipate the
µModule regulator’s thermal performance in their appli-
cation at various electrical and environmental operating
conditions to compliment any FEA activities. Without
FEA software, the thermal resistances reported in the
Pin Configuration section are in and of themselves not
relevant to providing guidance of thermal performance;
instead, the derating curves provided in the data sheet can
be used in a manner that yields insight and guidance per-
taining to one’s application usage, and can be adapted to
correlate thermal performance to one’s own application.
There may be situations that require the power supply to
start up with a pre-bias on the output capacitors. In this
case, it is desirable to start up without discharging that
output pre-bias. The LTM4705 can safely power up into
a pre-biased output without discharging it.
The LTM4705 accomplishes this by forcing discontinu-
ous mode (DCM) operation until the TRACK/SS pin volt-
age reaches 0.6V reference voltage. This will prevent the
bottom MOSFET from turning on during the pre-biased
output start-up which would discharge the output.
Overtemperature Protection
The Pin Configuration section typically gives four thermal
coefficients explicitly defined in JESD 51-12; these coef-
ficients are quoted or paraphrased below:
The internal overtemperature protection monitors the
junction temperature of the module. If the junction
temperature reaches approximately 160°C, both power
switches will be turned off until the temperature drops
about 15°C cooler.
1. θ , the thermal resistance from junction to ambient,
JA
is the natural convection junction-to-ambient air ther-
mal resistance measured in a one cubic foot sealed
enclosure. This environment is sometimes referred to
as “still air” although natural convection causes the
air to move. This value is determined with the part
Input Overvoltage Protection
In order to protect the internal power MOSFET devices
against transient voltage spikes, the LTM4705 constantly
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mounted to a JESD 51-9 defined test board, which
does not reflect an actual application or viable operat-
ing condition.
operating conditions of a μModule. For example, in nor-
mal board mounted applications, never does 100% of
the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bottom
2. θ
, the thermal resistance from junction to the
JCbottom
of the µModule—as the standard defines for θ
and
JCtop
bottom of the product case, is determined with all
of the component power dissipation flowing through
the bottom of the package. In the typical μModule
regulator, the bulk of the heat flows out the bottom
of the package, but there is always heat flow out into
the ambient environment. As a result, this thermal
resistance value may be useful for comparing pack-
ages but the test conditions don’t generally match the
user’s application.
θ
, respectively. In practice, power loss is ther-
JCbottom
mally dissipated in both directions away from the pack-
age—granted, in the absence of a heat sink and airflow,
a majority of the heat flow is into the board.
Within a SIP (system-in-package) module, be aware there
are multiple power devices and components dissipating
power, with a consequence that the thermal resistances
relative to different junctions of components or die are not
exactly linear with respect to total package power loss. To
reconcile this complication without sacrificing modeling
simplicity—but also, not ignoring practical realities—an
approach has been taken using FEA software modeling
along with laboratory testing in a controlled environment
chamber to reasonably define and correlate the thermal
resistance values supplied in this data sheet: (1) Initially,
FEA software is used to accurately build the mechanical
geometry of the µModule and the specified PCB with all
of the correct material coefficients along with accurate
power loss source definitions; (2) this model simulates
a software-defined JEDEC environment consistent with
JSED51-9 to predict power loss heat flow and tempera-
ture readings at different interfaces that enable the cal-
culation of the JEDEC-defined thermal resistance values;
(3) the model and FEA software is used to evaluate the
µModule with heat sink and airflow; (4) having solved for
and analyzed these thermal resistance values and simu-
lated various operating conditions in the software model,
a thorough laboratory evaluation replicates the simulated
conditions with thermocouples within a controlled-envi-
ronment chamber while operating the device at the same
power loss as that which was simulated. An outcome of
this process and due-diligence yields a set of derating
curves provided in other sections of this data sheet. After
these laboratory test have been performed and correlated
3. θ
, the thermal resistance from junction to top of
JCtop
the product case, is determined with nearly all of the
component power dissipation flowing through the top
of the package. As the electrical connections of the
typical µModule are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
As in the case of θ
, this value may be useful
JCbottom
for comparing packages but the test conditions don’t
generally match the user’s application.
4. θJB, the thermal resistance from junction to the
printed circuit board, is the junction-to-board thermal
resistance where almost all of the heat flows through
the bottom of the µModule and into the board, and
is really the sum of the θJCbottom and the thermal
resistance of the bottom of the part through the solder
joints and through a portion of the board. The board
temperature is measured a specified distance from
the package, using a two sided, two layer board. This
board is described in JESD 51-9.
A graphical representation of the aforementioned ther-
mal resistances is given in Figure 7; blue resistances are
contained within the μModule regulator, whereas green
resistances are external to the µModule.
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD 51-12 or provided in the
Pin Configuration section replicates or conveys normal
to the µModule model, then the θ and θ are summed
JB
BA
together to correlate quite well with the µModule model
with no airflow or heat sinking in a properly define cham-
ber. This θ + θ value is shown in the Pin Configuration
JB
BA
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µModule DEVICE
θ
θ
JUNCTION-TO-AMBIENT RESISTANCE
JA
θ
JUNCTION-TO-CASE
CASE (TOP)-TO-AMBIENT
JCtop
(TOP) RESISTANCE
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION
AMBIENT
JB
θ
JCbot
JUNCTION-TO-CASE
CASE (BOTTOM)-TO-BOARD
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
(BOTTOM) RESISTANCE
4705 F07
Figure 7. Graphical Representation of JESD51-12 Thermal Coefficients
section and should accurately equal the θ value because
approximately 100% of power loss flowJsAfrom the junc-
tion through the board into ambient with no airflow or top
mounted heat sink.
is increased. The monitored junction temperature of
120°C minus the ambient operating temperature speci-
fies how much module temperature rise can be allowed.
As an example in Figure 15 the load current is derated
to ~4A at ~110°C with no air or heat sink and the power
loss for the 5V to 1.5V at 10A output is about 0.6W. The
0.6W loss is calculated with the ~0.5W room temperature
loss from the 5V to 1.5V power loss curve at 10A, and
the 1.2 multiplying factor at 110°C ambient. If the 110°C
ambient temperature is subtracted from the 120°C junc-
tion temperature, then the difference of 10°C divided by
The 1.0V, 1.5V, 2.5V, 3.3V and 5V power loss curves in
Figure 8 to Figure 12 can be used in coordination with
the load current derating curves in Figure 13 to Figure 21
for calculating an approximate θ thermal resistance for
JA
the LTM4705 with no heat sinking and various airflow
conditions. The power loss curves are taken at room tem-
perature, and are increased with multiplicative factors of
1.35 assuming junction temperature at 120°C. The derat-
ing curves are plotted with the output current starting at
10A and the ambient temperature at 40°C. These output
voltages are chosen to include the lower and higher out-
put voltage ranges for correlating the thermal resistance.
Thermal models are derived from several temperature
measurements in a controlled temperature chamber along
with thermal modeling analysis. The junction temperatures
are monitored while ambient temperature is increased
with and without airflow. The power loss increase with
ambient temperature change is factored into the derating
curves. The junctions are maintained at 120°C maximum
while lowering output current or power with increasing
ambient temperature. The decreased output current will
decrease the internal module loss as ambient temperature
0.6W equals a 16.7°C/W θ thermal resistance. Table 3
JA
specifies a 17°C/W value which is very close. Table 3 to
Table 7 provide equivalent thermal resistances for 1.0V,
1.5V, 2.5V, 3.3V and 5V outputs with and without airflow.
The derived thermal resistances in Table 3 to Table 7 for
the various conditions can be multiplied by the calcu-
lated power loss as a function of ambient temperature to
derive temperature rise above ambient, thus maximum
junction temperature. Room temperature power loss
can be derived from the efficiency curves in the Typical
Performance Characteristics section and adjusted with
the above ambient temperature multiplicative factors. The
printed circuit board is a 1.6mm thick four layer board
with two ounce copper for the two outer layers and one
ounce copper for the two inner layers. The PCB dimen-
sions are 95mm × 76mm.
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15
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3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5V
5V
IN
5V
IN
IN
IN
IN
12V
12V
12V
IN
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
4705 F09
4705 F10
4705 F08
Figure 8. 1.0V Output Power Loss
Figure 9. 1.5V Output Power Loss
Figure 10. 2.5V Output Power Loss
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
12
10
8
5V
12V
IN
IN
IN
12V
6
4
2
0LFM
200LFM
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
40 50 60
70
80 90 100 110 120
LOAD CURRENT (A)
LOAD CURRENT (A)
AMBIENT TEMPERATURE (˚C)
4705 F11
4705 F12
4705 F13
Figure 11. 3.3V Output Power Loss
Figure 12. 5V Output Power Loss
Figure 13. 5V to 1.0V Derating
Curve, No Heat Sink
12
10
8
12
10
8
12
10
8
6
6
6
4
4
4
2
2
2
0LFM
0LFM
0LFM
200LFM
200LFM
200LFM
0
0
0
40 50 60
80 90 100 110 120
40 50 60
80 90 100 110 120
70
70
40 50 60
80 90 100 110 120
70
AMBIENT TEMPERATURE (˚C)
AMBIENT TEMPERATURE (˚C)
AMBIENT TEMPERATURE (˚C)
4705 F15
4705 F16
4705 F14
Figure 14. 12V to 1.0V Derating
Curve, No Heat Sink
Figure 15. 5V to 1.5V Derating
Curve, No Heat Sink
Figure 16. 12V to 1.5V Derating
Curve, No Heat Sink
Rev. 0
16
For more information www.analog.com
LTM4705
APPLICATIONS INFORMATION
12
10
8
12
10
8
12
10
8
6
6
6
4
4
4
2
2
2
0LFM
0LFM
0LFM
200LFM
200LFM
200LFM
0
0
0
40 50 60
80 90 100 110 120
70
40 50 60
80 90 100 110 120
40 50 60
80 90 100 110 120
70
70
AMBIENT TEMPERATURE (˚C)
AMBIENT TEMPERATURE (˚C)
AMBIENT TEMPERATURE (˚C)
4705 F17
4705 F18
4705 F19
Figure 17. 5V to 2.5V Derating
Curve, No Heat Sink
Figure 18. 12V to 2.5V Derating
Curve, No Heat Sink
Figure 19. 5V to 3.3V Derating
Curve, No Heat Sink
12
10
8
12
10
8
6
6
4
4
2
2
0LFM
0LFM
200LFM
200LFM
0
0
40 50 60
80 90 100 110 120
40 50 60
80 90 100 110 120
70
70
AMBIENT TEMPERATURE (˚C)
AMBIENT TEMPERATURE (˚C)
4705 F20
4705 F21
Figure 20. 12V to 3.3V Derating
Curve, No Heat Sink
Figure 21. 12V to 5V Derating
Curve, No Heat Sink
Table 3. 1V Output
DERATING CURVE
Figure 13, Figure 14
Figure 13, Figure 14
V
(V)
POWER LOSS CURVE
Figure 8
AIR FLOW (LFM)
HEAT SINK
None
θ
θ
IN
JA(°C/W)
5, 12
5, 12
0
17
Figure 8
200
None
14
Table 4. 1.5V Output
DERATING CURVE
V
(V)
POWER LOSS CURVE
Figure 9
AIR FLOW (LFM)
HEAT SINK
None
IN
JA(°C/W)
Figure 15, Figure 16
Figure 15, Figure 16
5, 12
0
17
5, 12
Figure 9
200
None
14
Rev. 0
17
For more information www.analog.com
LTM4705
APPLICATIONS INFORMATION
Table 5. 2.5V Output
DERATING CURVE
Figure 17, Figure 18
Figure 17, Figure 18
V
(V)
POWER LOSS CURVE
Figure 10
AIR FLOW (LFM)
HEAT SINK
None
θ
θ
θ
IN
JA(°C/W)
5, 12
5, 12
0
17
Figure 10
200
None
14
Table 6. 3.3V Output
DERATING CURVE
V
(V)
POWER LOSS CURVE
Figure 11
AIR FLOW (LFM)
HEAT SINK
None
IN
JA(°C/W)
Figure 19, Figure 20
Figure 19, Figure 20
5, 12
0
17
5, 12
Figure 11
200
None
14
Table 7. 5V Output
DERATING CURVE
Figure 21
V
(V)
POWER LOSS CURVE
Figure 12
AIR FLOW (LFM)
HEAT SINK
None
IN
JA(°C/W)
12
12
0
17
Figure 21
Figure 12
200
None
14
Table 8. Output Voltage Response for Each Regulator Channel vs Component Matrix (Refer to Figure 23)
1.25A Load Step Typical Measured Values
C
C
P-P
DERIVATION
(mV)
RECOVERY
TIME
LOAD STEP
LOAD STEP SLEW RATE
IN
OUT1
(CERAMIC)
(μF)
(CERAMIC)
(μF)
V
R
FB
IN
V
OUT
(V)
C
(pF)
FF
(V)
(μS)
(A)
2.5
2.5
2.5
2.5
2.5
2.5
2.5
(A/μS)
(kΩ)
90.9
60.4
40.2
30.1
19.1
13.3
8.25
1
22
22
22
22
22
22
22
100
100
100
100
100
100
100
100
5, 12
5, 12
5, 12
5, 12
5, 12
5, 12
12
60
60
50
50
50
50
50
50
50
10
1.2
100
100
100
100
100
100
10
1.5
1.8
2.5
3.3
5
60
10
60
10
68
10
90
10
133
10
Rev. 0
18
For more information www.analog.com
LTM4705
APPLICATIONS INFORMATION
Safety Considerations
• Place a dedicated power ground layer underneath
the unit.
The LTM4705 modules do not provide galvanic isolation
from V to V . There is no internal fuse. If required,
• To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
IN
OUT
a slow blow fuse with a rating twice the maximum input
current needs to be provided to protect each unit from
catastrophic failure. The device does support thermal
shutdown and overcurrent protection.
• Do not put via directly on the pad, unless they are
capped or plated over.
Layout Checklist/Example
• Use a separated SGND ground copper area for com-
ponents connected to signal pins. Connect the SGND
to GND underneath the unit.
The high integration of LTM4705 makes the PCB board
layout very simple and easy. However, to optimize its
electrical and thermal performance, some layout consid-
erations are still necessary.
• For parallel modules, tie the V , V , and COMP pins
together. Use an internal layerOtUoTcloFsBely connect these
pins together. The TRACK pin can be tied a common
capacitor for regulator soft-start.
• Use large PCB copper areas for high current paths,
including V , GND, V
and V
. It helps to mini-
IN
OUT1
OUT2
mize the PCB conduction loss and thermal stress.
• Bring out test points on the signal pins for monitoring.
Figure22givesagoodexampleoftherecommendedlayout.
• Place high frequency ceramic input and output capaci-
tors next to the V , GND and V
pins to minimize
IN
OUT
high frequency noise.
V
IN1
GND
V
V
OUT1
GND
OUT2
V
IN2
4705 F22
Figure 22. Recommended PCB Layout
Rev. 0
19
For more information www.analog.com
LTM4705
TYPICAL APPLICATIONS
PGOOD1
PGOOD2
V
V
V
V
V
OUT1
OUT1
IN1
1V, 5A
V
IN
100µF
100µF
IN2
3.1V TO 20V
22µF
100pF
LTM4705
RUN1
RUN2
INTV
FB1
V
OUT2
CC
OUT2
1.5V, 5A
SYNC/MODE
TRACK/SS1
TRACK/SS2
COMP1
COMP2
FB2
100pF
0.1µF
0.1µF
40.2k
90.9k
FREQ
GND
4705 F23
Figure 23. 3.1VIN to 20VIN, 1V and 1.5V Output at 5A Design
PGOOD
PGOOD1
PGOOD2
V
OUT
V
V
V
V
OUT1
IN1
1.2V, 10A
V
200µF
IN
IN2
3.1V TO 20V
LTM4705
OUT2
44µF
RUN1
RUN2
COMP1
INTV
CC
SYNC/MODE
TRACK/SS1
TRACK/SS2
COMP2
FB1
0.1µF
FB2
30.2k
FREQ
GND
4705 F24
Figure 24. 3.1VIN to 20VIN, 1.2V Two Phase in Parallel 10A Design
Rev. 0
20
For more information www.analog.com
LTM4705
TYPICAL APPLICATIONS
PGOOD1
PGOOD2
V
V
V
V
V
OUT1
OUT1
IN1
3.3V, 5A
V
IN
100µF
100µF
IN2
8V TO 20V
44µF
100pF
LTM4705
RUN1
RUN2
INTV
FB1
V
OUT2
CC
OUT2
5V, 5A
SYNC/MODE
TRACK/SS1
TRACK/SS2
COMP1
COMP2
FB2
100pF
0.1µF
0.1µF
8.25k
13.3k
FREQ
GND
4705 F25
324k
Figure 25. 8VIN to 20VIN, 3.3V and 5V Output at 5A with 2MHz Switching Frequency
PGOOD1
PGOOD2
V
OUT1
V
V
V
V
OUT1
IN1
1.5V, 5A
V
IN
100µF
IN2
3.3V
LTM4705
44µF
RUN1
RUN2
V
OUT2
OUT2
1.2V, 5A
100µF
INTV
COMP1
COMP2
CC
SYNC/MODE
TRACK/SS1
TRACK/SS2
FB1
FB2
60.4k
V
OUT1
40.2k
60.4k
FREQ
0.1µF
GND
4705 F26
60.4k
Figure 26. 3.3VIN, 1.5V and 1.2V Output at 5A Design with Output Coincident Tracking
Rev. 0
21
For more information www.analog.com
LTM4705
PACKAGE DESCRIPTION
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
LTM4705 Component BGA Pinout
PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
A1
B1
C1
D1
E1
F1
FB2
A2
B2
C2
D2
E2
F2
COMP2
PGOOD2
GND
A3
B3
C3
D3
E3
F3
RUN2
GND
GND
A4
B4
C4
D4
E4
F4
FREQ
INTV
A5
B5
C5
D5
E5
F5
RUN1
SYNC/MODE
GND
A6
B6
C6
D6
E6
F6
COMP1
PGOOD1
GND
A7
B7
C7
D7
E7
F7
FB1
TRACK/SS2
TRACK/SS1
CC
V
IN2
V
IN2
SGND
GND
GND
GND
GND
GND
GND
V
IN1
V
IN1
V
IN2
V
IN2
V
IN2
V
IN2
V
IN1
V
IN1
V
IN1
V
IN1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
G1
H1
J1
G2
H2
J2
G3
H3
J3
G4
H4
J4
G5
H5
J5
G6
H6
J6
G7
H7
J7
V
V
V
V
V
V
OUT2
OUT2
OUT2
OUT2
OUT2
OUT2
OUT1
OUT1
OUT1
OUT1
OUT1
OUT1
V
V
V
V
V
V
Rev. 0
22
For more information www.analog.com
LTM4705
PACKAGE DESCRIPTION
Z
/ / b b b
Z
2 . 4 0
1 . 6 0
0 . 8 0
0 . 0 0 0
0 . 8 0
1 . 6 0
2 . 4 0
a a a
Z
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
23
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LTM4705
PACKAGE PHOTO
DESIGN RESOURCES
SUBJECT
DESCRIPTION
µModule Design and Manufacturing Resources
Design:
• Selector Guides
Manufacturing:
• Quick Start Guide
• Demo Boards and Gerber Files
• Free Simulation Tools
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
µModule Regulator Products Search
1. Sort table of products by parameters and download the result as a spread sheet.
2. Search using the Quick Power Search parametric table.
Digital Power System Management
Analog Devices’ family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
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Dual 10A or Single 20A µModule Regulator
Dual 15A or Single 30A µModule Regulator
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≤ 5.5V; 11.25mm × 15mm × 5.01mm BGA
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IN
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4.5V ≤ V ≤ 20V; 0.6V ≤ V
IN
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Rev. 0
10/21
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24
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