LTM8083IY [ADI]
36V, 1.5A Buck-Boost μModule Regulator;
| 型号： | LTM8083IY |
| 厂家： | 
ADI |
| 描述： | 36V, 1.5A Buck-Boost μModule Regulator |
| 文件： | 总24页 (文件大小：2630K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTM8083
36V, 1.5A Buck-Boost
µModule Regulator
FEATURES
DESCRIPTION
The LTM®8083 is a 36VIN, Buck-Boost µModule® Regulator.
Included in the package are the switching controller, power
switches, inductor, and support components. All that is
needed to complete the design is resistors for setting the
output voltage and operating frequency, and input and
output capacitors. Operating over an input voltage range
from 3V to 36V, the LTM8083 can regulate output volt-
ages between 1V and 36V with seamless low-noise tran-
sitions between operation regions, as well as controlling
both input and output average currents through external
sense resistors.
n
Complete Buck-Boost Switch Mode Power Supply
n
Wide Input Voltage Range: 3V to 36V
n
Wide Output Voltage Range: 1V to 36V
n
12V/0.8A Output at 6V
IN
IN
IN
n
n
n
12V/1.5A Output at 12V
12V/1.5A Output at 36V
Integrated Three-Terminal Capacitors and Spread
Spectrum for Excellent EMI Performance
Compliant with CISPR25 Class 5 Limits (Refer to
Figure 25)
n
n
300kHz to 2MHz Fixed Switching Frequency with
External Frequency Synchronization
Adjustable Output Current Limit
Output Current Monitoring
RoHS Compliant Package
6.25mm × 6.25mm × 2.22mm BGA Package
The low profile package enables utilization of unused
space on the bottom of PC boards for high density point
of load regulation. The LTM8083 is packaged in ther-
mally enhanced, compact over-molded Ball Grid Array
(BGA) packages suitable for automated assembly by
standard surface mount equipment. The LTM8083 is
RoHS compliant.
n
n
n
n
APPLICATIONS
n
All registered trademarks and trademarks are the property of their respective owners.
Battery-Operated Devices
n
Test and Measurement Equipment
n
Industrial Control
n
Solar Powered Voltage Regulator
n
Solar Powered Battery Charging
TYPICAL APPLICATION
12VOUT from 3-36VIN Buck-Boost Regulator
Efficiency at 12V Output
ꢏ00
ꢀꢁꢂꢃ0ꢃꢄ
ꢀ
ꢀ
ꢁꢂꢃ
ꢁꢂ
ꢀ
ꢀ
ꢄꢅꢀ
ꢁꢂ
ꢁꢂꢃ
ꢐꢑ
ꢃꢀ ꢄꢅ ꢃꢆꢀ
ꢀꢁ
ꢀꢁꢂ
ꢀ0ꢁꢂ
ꢂꢃ
ꢀꢀ0ꢁ
ꢐ0
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂ
ꢀ0ꢁꢂ
ꢀꢁ
ꢒꢑ
ꢒ0
ꢀ0ꢁ
ꢀꢁꢀꢂ
ꢘ
ꢘ
ꢘ
ꢘ
ꢙ ꢖꢘ
Rꢀ
ꢌꢇ
ꢌꢇ
ꢌꢇ
ꢌꢇ
ꢀꢁꢂ ꢀꢁꢂꢃ ꢀꢁꢂꢀ ꢀꢁꢀꢂ
ꢙ ꢏꢗꢘ
ꢙ ꢗꢚꢘ
ꢙ ꢔꢖꢘ
ꢓꢑ
ꢓ0
ꢀ0.ꢁꢂ
ꢃꢄꢅꢆ
ꢀ0ꢀꢁ ꢂꢃ0ꢄ
0
0.ꢔ
0.ꢖ
0.ꢐ
ꢏ.ꢗ
ꢏ.ꢑ
ꢀꢁꢂꢃ ꢂꢄꢅ ꢆꢃꢇꢈꢉ
ꢊꢅRꢋꢌ ꢁꢃꢍꢄꢂꢌ ꢁꢂꢅꢎ ꢌ ꢃꢃꢌ ꢎ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢊꢊ
ꢊ
ꢒ0ꢒꢔ ꢈꢂ0ꢏꢕ
Rev. 0
1
Document Feedback
For more information www.analog.com
LTM8083
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
ꢒꢣꢃ ꢤꢥꢆꢜ
V , SV , EN/UVLO, .................................................40V
IN
OUT
IN
ꢒꢩꢒꢎ ꢣꢤꢊꢣ ꢄꢒRꢊ ꢁꢦꢋ
ꢩꢤ ꢆꢦꢛꢨꢤꢊꢣ ꢥꢦꢒꢤ ꢥꢩꢔꢣꢦ
Rꢒ
ꢬꢀ
ꢒꢩꢒꢗ
V
, ISP, ISN ...........................................................40V
ꢢ
ꢍ
ꢏ
ꢇ
ꢚ
ꢎ
ꢗ
OVLO, CTRL, FB, SYNC, INTV .................................5V
CC
ꢤ
ꢄ
ꢩꢩ
ꢩꢪꢦꢄ
ꢥꢦ
ꢄꢄ
ISP-ISN............................................................–1V to 1V
Operating Junction Temperature Range
(Notes 2, 3)............................................ –40°C to 125°C
Storage Temperature Range .................. –55°C to 150°C
Solder Temperature ..............................................260°C
ꢀꢂꢦꢅ ꢗ
ꢀꢂꢦꢅ ꢎ
ꢤ
ꢣꢨꢒ
ꢤ
ꢥꢦ
ꢥꢩꢦ
ꢥꢩꢃ
ꢀꢂꢦꢅ 0
ꢁꢦꢋ
ꢂ
ꢀ
ꢄ
ꢋ
ꢆ
ꢬ
ꢁ
ꢀꢁꢂ ꢃꢂꢄꢅꢂꢁꢆ
ꢇꢈꢉꢊꢆꢂꢋ ꢌꢍ.ꢎꢏꢐꢐ × ꢍ.ꢎꢏꢐꢐ × ꢎ.ꢎꢎꢐꢐꢑ
ꢒ
ꢓꢄꢝꢞꢟ
ꢖ ꢗꢎꢏꢘꢄꢙ θ ꢖ ꢎꢚꢘꢄꢛꢜꢙ
ꢓꢂ
ꢓꢔꢂꢕ
θ
ꢖ ꢎꢗ.ꢠꢘꢄꢛꢜꢙ θ
ꢖ ꢢ.ꢍꢘꢄꢛꢜ
ꢓꢄꢡꢞꢝꢝꢞꢐ
ꢦꢣꢒꢆꢧ
ꢗꢑ θ ꢤꢂꢊꢨꢆꢩ ꢂRꢆ ꢋꢆꢒꢆRꢔꢥꢦꢆꢋ ꢀꢪ ꢩꢥꢔꢨꢊꢂꢒꢥꢣꢦ ꢃꢆR ꢓꢆꢩꢋꢏꢗ ꢄꢣꢦꢋꢥꢒꢥꢣꢦꢩ.
ꢎꢑ θ ꢤꢂꢊꢨꢆ ꢥꢩ ꢣꢀꢒꢂꢥꢦꢆꢋ ꢜꢥꢒꢫ ꢋꢆꢔꢣ ꢀꢣꢂRꢋ.
ꢓꢂ
ꢚꢑ RꢆꢬꢆR ꢒꢣ ꢃꢂꢁꢆ ꢗꢍ ꢬꢣR ꢊꢂꢀ ꢔꢆꢂꢩꢨRꢆꢔꢆꢦꢒ ꢂꢦꢋ ꢋꢆRꢂꢒꢥꢦꢁ ꢥꢦꢬꢣRꢔꢂꢒꢥꢣꢦ.
ꢇꢑ ꢜꢆꢥꢁꢫꢒ ꢖ ꢎꢚꢗꢐꢭ
ORDER INFORMATION
PART MARKING*
PACKAGE
TYPE
MSL
PART NUMBER
LTM8083EY#PBF
LTM8083IY#PBF
PAD OR BALL FINISH
DEVICE
FINISH CODE
RATING
TEMPERATURE RANGE
SAC305 (RoHS)
8083
1
BGA
3
–40°C to 125°C
• Contact the factory for parts specified with wider operating temperature
ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures
*The temperature grade is identified by a label on the shipping container.
• LGA and BGA Package and Tray Drawings
Rev. 0
2
For more information www.analog.com
LTM8083
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = SVIN = 12V, VEN/UVLO = 1.5V, unless otherwise noted.
PARAMETER
CONDITIONS
= SV
MIN
TYP
MAX
UNITS
l
Minimum Input Voltage
Output DC Voltage
V
3
V
IN
IN
R
FBtop
R
FBtop
R
FBtop
= 113kΩ, R
= 113kΩ, R
= 113kΩ, R
open
= 10kΩ
= 3.24kΩ
1
12
36
V
V
V
FBbottom
FBbottom
FBbottom
Output DC Current
V
V
V
= 6V, V
= 12V
OUT
0.8
1.5
1.5
A
A
A
IN
IN
IN
= 12V, V
= 12V
OUT
= 36V, V
= 12V
OUT
Quiescent Current into V
EN/UVLO = 0V (Shutdown)
EN/UVLO = 1.5V, V = 12V, I
0.9
2.6
µA
mA
IN
= 0A
OUT
OUT
l
l
Output Voltage Line Regulation
Output Voltage Load Regulation
Output Voltage Ripple
3V < V < 36V, V
= 12V, I = 0.1A
OUT
0.02
0.5
10
0.15
1.5
%/V
%
IN
OUT
V
V
= 12V, 0.0A < I
< 1.5A (Note 4)
OUT
OUT
OUT
= 12V, I
= 0A
mV
OUT
Switching Frequency
RT = 178kΩ
RT = 14.3kΩ
300
2000
kHz
kHz
l
Voltage at FB pin
0.985
1
1.015
V
V
V
V
EN/UVLO Rising Threshold
EN/UVLO Falling Threshold
ENUVLO Shutdown Threshold
EN/UVLO Pin Current
Starts Switching (UVLO)
Stops Switching (UVLO)
1.240
1.210
0.6
l
l
1.190
0.3
1.230
0.9
INTV = Disabled
CC
EN/UVLO = 0.3V
EN/UVLO = 1.1V
EN/UVLO = 1.3V
–1
2.0
–0.3
0
2.5
0
1
3.0
0.3
µA
µA
µA
l
OVLO Rising Threshold
OVLO Falling Threshold
ISN Pin Current
1.196
1.055
1.235
1.120
1.250
1.140
V
V
V
V
= V = 12V
23
–10
µA
µA
ISP
ISP
ISN
= V = 0V
ISN
ISP Pin Current
V
V
= V = 12V
23
–10
µA
µA
ISP
ISP
ISN
= V = 0V
ISN
ISP-ISN Current Sense Threshold
V
V
= Float
= 0.75V
96
40
105
52
116
65
mV
mV
CTRL
CTRL
ISMON Voltage
V
V
V
= 100mV, V = 0V
1.20
1.25
32
1.30
V
µA
µA
V
ISP
ISN
SS Pull-Up Current
= 0.8V, V = 0V
SS
FB
FB
SS Pull-Down Current
SYNC input Low Threshold
SYNC input High Threshold
SYNC Pin Current
= 1V, V = 2V
1.25
SS
0.4
0.1
1.5
V
–0.1
0
µA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTM8083E is guaranteed to meet performance specifications
from 0°C to 125°C operating junction temperature. Specifications over
the –40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LTM8083I is guaranteed over the –40°C to 125°C operating junction
temperature range.
Note 3: The LTM8083 includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 150°C when overtemperature protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 4: See output current derating curves for different V , V
and T .
A
IN OUT
Rev. 0
3
For more information www.analog.com
LTM8083
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
3.3VOUT Efficiency
5VOUT Efficiency
8VOUT Efficiency
ꢏꢐ
ꢏ0
ꢑꢐ
ꢑ0
ꢒꢐ
ꢒ0
ꢏꢐ
ꢏ0
ꢑꢐ
ꢑ0
ꢒꢐ
ꢒ0
ꢓꢐ
ꢏꢐ
ꢏ0
ꢑꢐ
ꢑ0
ꢘ
ꢌꢇ
ꢘ
ꢌꢇ
ꢘ
ꢌꢇ
ꢘ
ꢌꢇ
ꢘ
ꢌꢇ
ꢘ
ꢌꢇ
ꢙ ꢔ.ꢔꢘ
ꢙ ꢐꢘ
ꢒꢐ
ꢘ
ꢘ
ꢘ
ꢘ
ꢘ
ꢙ ꢔ.ꢔꢘ
ꢌꢇ
ꢌꢇ
ꢌꢇ
ꢌꢇ
ꢌꢇ
ꢘ
ꢘ
ꢘ
ꢘ
ꢙ ꢓ.ꢓꢘ
ꢙ ꢐꢘ
ꢙ ꢕꢗꢘ
ꢙ ꢗꢚꢘ
ꢙ ꢐꢘ
ꢙ ꢑꢘ
ꢌꢇ
ꢌꢇ
ꢌꢇ
ꢌꢇ
ꢙ ꢗꢖꢘ
ꢙ ꢖꢗꢘ
ꢙ ꢗꢚꢘ
ꢙ ꢔꢓꢘ
ꢒ0
ꢙ ꢖꢚꢘ
ꢙ ꢔꢓꢘ
ꢓꢐ
0
0.ꢓ
0.ꢖ
0.ꢏ
ꢕ.ꢗ
ꢕ.ꢐ
0
0.ꢔ
0.ꢓ
0.ꢏ
ꢗ.ꢖ
ꢗ.ꢐ
0
0.ꢔ
0.ꢓ
0.ꢏ
ꢖ.ꢗ
ꢖ.ꢐ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢑ0ꢑꢓ ꢔ0ꢕ
ꢑ0ꢑꢔ ꢕ0ꢖ
ꢑ0ꢑꢔ ꢕ0ꢔ
12VOUT Efficiency
18VOUT Efficiency
24VOUT Efficiency
ꢏ00
ꢐꢑ
ꢐ0
ꢒꢑ
ꢒ0
ꢓꢑ
ꢓ0
ꢏ00
ꢐꢑ
ꢐ0
ꢒꢑ
ꢒ0
ꢓꢑ
ꢓ0
ꢏ00
ꢐꢑ
ꢐ0
ꢒꢑ
ꢒ0
ꢓꢑ
ꢓ0
ꢙ
ꢚ ꢔ.ꢔꢙ
ꢚ ꢗꢙ
ꢚ ꢏꢘꢙ
ꢚ ꢘꢖꢙ
ꢚ ꢔꢗꢙ
ꢘ
ꢙ ꢑꢘ
ꢘ
ꢙ ꢒꢘ
ꢌꢇ
ꢌꢇ
ꢌꢇ
ꢌꢇ
ꢌꢇ
ꢌꢇ
ꢌꢇ
ꢌꢇ
ꢌꢇ
ꢌꢇ
ꢌꢇ
ꢌꢇ
ꢌꢇ
ꢌꢇ
ꢌꢇ
ꢙ
ꢙ
ꢙ
ꢙ
ꢘ
ꢘ
ꢘ
ꢘ
ꢙ ꢏꢗꢘ
ꢙ ꢏꢒꢘ
ꢙ ꢗꢚꢘ
ꢙ ꢔꢖꢘ
ꢘ
ꢘ
ꢘ
ꢘ
ꢙ ꢏꢗꢘ
ꢙ ꢏꢒꢘ
ꢙ ꢗꢚꢘ
ꢙ ꢔꢖꢘ
0
0.ꢔ
0.ꢗ
0.ꢐ
ꢏ.ꢘ
ꢏ.ꢑ
0
0.ꢔ
0.ꢖ
0.ꢐ
ꢏ.ꢗ
ꢏ.ꢑ
0
0.ꢔ
0.ꢖ
0.ꢐ
ꢏ.ꢗ
ꢏ.ꢑ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢒ0ꢒꢔ ꢕ0ꢖ
ꢒ0ꢒꢔ ꢕ0ꢑ
ꢒ0ꢒꢔ ꢕ0ꢖ
Transient Response from
3.3VIN to 5VOUT
Transient Response from
5VIN to 5VOUT
36VOUT Efficiency
ꢏ00
ꢐꢑ
ꢐ0
ꢒꢑ
ꢒ0
ꢓꢑ
ꢓ0
V
OUT(AC)
V
OUT(AC)
200mV/DIV
200mV/DIV
I
I
LOAD
LOAD
200mA/DIV
200mA/DIV
ꢘ
ꢙ ꢏꢗꢘ
8083 G08
8083 G09
ꢌꢇ
ꢌꢇ
ꢌꢇ
ꢌꢇ
200µs/DIV
200µs/DIV
ꢘ
ꢘ
ꢘ
ꢙ ꢏꢒꢘ
ꢙ ꢗꢚꢘ
ꢙ ꢔꢖꢘ
V
= 3.3V, V
= 5V, f = 1MHz,
V
IN
= 5V, V
= 5V, f = 1MHz,
OUT SW
IN
OUT
SW
0.375A (25%) LOAD STEP, 0.375A/μs
= 10μF CERAMIC
0.375A (25%) LOAD STEP, 0.375A/μs
C = 10μF CERAMIC
OUT
C
OUT
0
0.ꢔ
0.ꢖ
0.ꢐ
ꢏ.ꢗ
ꢏ.ꢑ
INTERNAL COMPENSATION
INTERNAL COMPENSATION
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢒ0ꢒꢔ ꢕ0ꢓ
Rev. 0
4
For more information www.analog.com
LTM8083
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Transient Response from
12VIN to 5VOUT
Transient Response from
24VIN to 5VOUT
Transient Response from
36VIN to 5VOUT
V
V
V
OUT(AC)
200mV/DIV
OUT(AC)
OUT(AC)
100mV/DIV
100mV/DIV
I
I
I
LOAD
200mA/DIV
LOAD
LOAD
200mA/DIV
200mA/DIV
8083 G10
8083 G13
8083 G16
8083 G11
8083 G14
8083 G17
8083 G12
8083 G15
8083 G18
200µs/DIV
200µs/DIV
200µs/DIV
= 5V, f = 1MHz,
V
= 12V, V
= 5V, f = 1MHz,
V
= 24V, V
= 5V, f = 1MHz,
V
= 36V, V
IN
OUT
SW
IN
OUT
SW
IN OUT
SW
0.375A (25%) LOAD STEP, 0.375A/μs
0.375A (25%) LOAD STEP, 0.375A/μs
0.375A (25%) LOAD STEP, 0.375A/μs
C
= 10μF CERAMIC
C
= 10μF CERAMIC
C
= 10μF CERAMIC
INTERNAL COMPENSATION
OUT
OUT
OUT
INTERNAL COMPENSATION
INTERNAL COMPENSATION
Transient Response from
6VIN to 12VOUT
Transient Response from
12VIN to 12VOUT
Transient Response from
24VIN to 12VOUT
V
V
V
OUT(AC)
OUT(AC)
OUT(AC)
200mV/DIV
200mV/DIV
100mV/DIV
I
I
I
LOAD
200mA/DIV
LOAD
LOAD
200mA/DIV
200mA/DIV
200µs/DIV
200µs/DIV
200µs/DIV
V
IN
= 6V, V
= 12V, f = 1MHz,
V
IN
= 12V, V
= 12V, f = 1MHz,
V
IN
= 24V, V
= 12V, f = 1MHz,
OUT SW
OUT
SW
OUT
SW
0.375A (25%) LOAD STEP, 0.375A/μs
0.375A (25%) LOAD STEP, 0.375A/μs
0.375A (25%) LOAD STEP, 0.375A/μs
C
= 10μF CERAMIC
C
= 10μF CERAMIC
C
= 10μF CERAMIC
OUT
OUT
OUT
INTERNAL COMPENSATION
INTERNAL COMPENSATION
INTERNAL COMPENSATION
Transient Response from
36VIN to 12VOUT
Transient Response from
18VIN to 36VOUT
Transient Response from
36VIN to 36VOUT
V
V
V
OUT(AC)
OUT(AC)
1V/DIV
OUT(AC)
1V/DIV
100mV/DIV
I
I
I
LOAD
LOAD
LOAD
200mA/DIV
200mA/DIV
200mA/DIV
200µs/DIV
200µs/DIV
200µs/DIV
V
= 36V, V
= 12V, f = 1MHz,
V
= 18V, V
= 36V, f = 1MHz,
V
= 36V, V
= 36V, f = 1MHz,
OUT SW
IN
OUT
SW
IN
OUT
SW
IN
0.375A (25%) LOAD STEP, 0.375A/μs
= 10μF CERAMIC
0.375A (25%) LOAD STEP, 0.375A/μs
= 10μF CERAMIC
0.375A (25%) LOAD STEP, 0.375A/μs
C = 10μF CERAMIC
OUT
C
C
OUT
OUT
INTERNAL COMPENSATION
INTERNAL COMPENSATION
INTERNAL COMPENSATION
Rev. 0
5
For more information www.analog.com
LTM8083
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Start-Up with 6VIN and 12VOUT
at IOUT = 0.8A
Start-Up with 12VIN and 12VOUT
at IOUT = 1.5A
Start-Up with 24VIN and 12VOUT
at IOUT = 1.5A
V
V
OUT
10V/DIV
V
OUT
OUT
10V/DIV
10V/DIV
I
I
I
OUT
2A/DIV
OUT
OUT
1A/DIV
2A/DIV
8083 G19
8083 G20
8083 G21
2ms/DIV
2ms/DIV
= 12V, f = 1MHz, 1.5A
2ms/DIV
= 12V, f = 1MHz, 1.5A
V
C
= 6V, V
OUT
= 12V, f = 1MHz, 0.8A
V
C
= 12V, V
OUT
V
C
= 24V, V
OUT
OUT
IN
OUT
SW
IN
OUT
SW
IN
SW
= 10μF CERAMIC
= 10μF CERAMIC
= 10μF CERAMIC
SOFT-START CAPACITOR = 0.1μF
SOFT-START CAPACITOR = 0.1μF
SOFT-START CAPACITOR = 0.1μF
USE EN/UVLO PIN TO CONTROL START-UP
USE EN/UVLO PIN TO CONTROL START-UP
USE EN/UVLO PIN TO CONTROL START-UP
Start-Up with 36VIN and 12VOUT
at IOUT = 1.5A
Short-Circuit with 6VIN and
12VOUT at IOUT = 0.8A
Short-Circuit with 12VIN and
12VOUT at IOUT = 1.5A
V
OUT
ꢆ
ꢆ
ꢋꢌꢍ
ꢎꢆꢃꢄꢅꢆ
ꢊꢋꢌ
10V/DIV
ꢍꢆꢃꢄꢅꢆ
I
OUT
ꢅ
ꢅ
2A/DIV
ꢅꢎ
ꢅꢏ
ꢏꢐꢃꢄꢅꢆ
ꢐꢑꢃꢄꢅꢆ
8083 G22
ꢇ0ꢇꢈ ꢉꢀꢈ
ꢇ0ꢇꢈ ꢉꢀꢊ
2ms/DIV
= 12V, f = 1MHz, 1.5A
ꢀ00ꢁꢂꢃꢄꢅꢆ
ꢀ00ꢁꢂꢃꢄꢅꢆ
V
C
= 36V, V
OUT
OUT
SOFT-START CAPACITOR = 0.1μF
IN
SW
= 10μF CERAMIC
USE EN/UVLO PIN TO CONTROL START-UP
Short-Circuit with 24VIN and
12VOUT at IOUT = 1.5A
Short-Circuit with 36VIN and
12VOUT at IOUT = 1.5A
Short-Circuit with 24VIN and
36VOUT at IOUT = 1A
ꢆ
ꢆ
ꢆ
ꢋꢌꢍ
ꢀ0ꢆꢃꢄꢅꢆ
ꢋꢌꢍ
ꢋꢌꢍ
ꢊꢆꢃꢄꢅꢆ
ꢎꢆꢃꢄꢅꢆ
ꢅ
ꢅ
ꢅ
ꢅꢎ
ꢏꢐꢃꢄꢅꢆ
ꢅꢎ
ꢅꢏ
0.ꢊꢏꢃꢄꢅꢆ
0.ꢎꢐꢃꢄꢅꢆ
ꢇ0ꢇꢈ ꢉꢀꢊ
ꢇ0ꢇꢈ ꢉꢀꢊ
ꢇ0ꢇꢈ ꢉꢀꢊ
ꢀ00ꢁꢂꢃꢄꢅꢆ
ꢀ00ꢁꢂꢃꢄꢅꢆ
ꢀ00ꢁꢂꢃꢄꢅꢆ
Rev. 0
6
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LTM8083
PIN FUNCTIONS
PACKAGE ROW AND COLUMN LABELING MAY VARY
INTV (Pin C6): Internal 3.6V Linear Regulator Output.
CC
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
Powered from the SVIN pin, the INTVCC supplies the
internal control circuitry and gate drivers. No decoupling
ceramic capacitor is required.
GND (Bank 0, Pin D7): Tie these GND pins to a local
ground plane below the LTM8083 and the circuit com-
ponents. In most applications, the majority of the heat
of the LTM8083 flows out through these pads, so the
printed circuit design has a large impact on the thermal
performance of the part. See the PCB Layout and Thermal
Considerations sections for more details. Return the feed-
CTRL (Pin C7): ISP-ISN Current Sense Adjustment. The
voltage on this pin determines current limit threshold
voltage of ISP-ISN. The current limit threshold is 100mV
when this pin is floated. Apply a voltage below 1.35V to
reduce the current limit threshold of ISP-ISN across the
output sense resistor. This pin is internally pulled up to 2V
reference voltage with a 100k resistor. See the Applications
Information section for more details.
back divider (R ) to this net.
FB
V
(Bank 1): Input Power. The V pin supplies current
IN
IN
to the internal power switches. This pin must be locally
ISMON (Pin D6): ISP-ISN Current Monitor. This pin pro-
bypassed with an external, low ESR ceramic capacitor.
duces a voltage that is 10 times the voltage of V -V
ISP ISN
plus 0.25V offset voltage. ISMON will equal 1.25V when
– V = 100mV.
V
(Bank 2): Power Output Pins. Apply the output filter
OUT
V
capacitor and the output load between these pins and
ISP
ISN
GND pins.
VC (Pin E6): Error Amplifier Output. The VC pin is nor-
mally left open in LTM8083 applications as it is already
internally compensated.
SVIN (Pin A6): Bias Supply. The SVIN pin supplies the
internal circuitry and the INTV linear regulator. Connect
CC
this pin to V or another power supply. Bypass this pin
IN
RT (Pin E7): Switching Frequency Setting. Connect a
resistor from this pin to ground to set the internal oscil-
lator frequency from 300kHz to 2MHz. See Table 1 for
resistor values to set common switching frequencies.
to ground with a ceramic capacitor.
TST2 (Pin A7): Test Pin 2. This pin is used in production
testing. Do not drive a voltage into this pin; This pin must
be tied to GND.
ISN (Pin F3): Negative Terminal of Current Sense Resistor.
Ensure accurate current sense with Kelvin connection.
EN/UVLO (Pin B6): Enable and Undervoltage Lockout.
Force the pin below 0.3V to shut down the part and reduce
VIN quiescent current to 0.9μA. Force the pin above
1.240V for normal operation. The accurate 1.210V falling
threshold can be used to program an undervoltage lock-
SS (Pin F6): Soft-Start. A 10nF capacitor has been inte-
grated inside LTM8083 for start-up. To increase the
built-in soft-start time, connect a capacitor from SS to
GND. If no additional soft-start time is required, leave
this pin floating.
out (UVLO) threshold with a resistor divider from V to
IN
ground. An accurate 2.5μA pull-down current allows the
FB (Pin F7): Feedback. The LTM8083 regulates its FB
pin to 1V. Connect a resistor divider from this pin to the
output and to ground to set the output voltage. When an
output current sense resistor is connected to ISP and
ISN, connect the resistor network to ISN for improved
load regulation.
programming of V UVLO hysteresis. If neither function
IN
is used, tie this pin directly to V .
IN
OVLO (Pin B7): Overvoltage Lockout. The OVLO pin is
used to program an overvoltage lockout (OVLO) threshold
with a resistor divider from V to ground. Force the pin
IN
above 1.250V to pull SS pin to ground and stop switching.
If not used, tie this pin to ground.
Rev. 0
7
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LTM8083
PIN FUNCTIONS
ISP (Pin G3): Positive Terminal of Current Sense Resistor.
Ensure accurate current sense with Kelvin connection.
25% triangle spread spectrum above internal oscillator
frequency.
SYNC (Pin G6): Switching Frequency Synchronization
or Spread Spectrum Enable. Ground this pin to switch
at the internal oscillator frequency. Apply a clock signal
TST1 (Pin G7): Test Pin 1. This pin is used in production
testing. This pin must be floated. Do not drive a voltage
to this pin.
for external frequency synchronization. Tie to INTV for
CC
BLOCK DIAGRAM
ꢀ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢁꢂꢃ
ꢁꢂ
ꢀꢁ
ꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢀ
ꢀꢁ
Rꢂꢃ
ꢀꢁꢂꢃꢄꢀꢅꢅꢆꢇ ꢂꢅꢈꢇRꢅꢉꢉꢊR
ꢀ00ꢁ
ꢀꢁRꢂ
ꢀꢁꢂꢃꢄ
ꢀ00ꢁ
ꢀꢀ
Rꢀ
ꢀ0ꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢀꢂ
ꢀꢁꢀꢂ
ꢀꢁꢂꢃ
ꢄꢄ
ꢁ
ꢀ0ꢀꢁ ꢂꢃ
Rev. 0
8
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LTM8083
OPERATION
The LTM8083 is a standalone non-isolated buck-boost
switching DC/DC power supply. The buck-boost topol-
ogy allows the LTM8083 to regulate its output voltage
below or above input voltage. Maximum output current
is determined by the input voltage. Higher input voltages
yield higher maximum output current.
A voltage less than 1.35V applied to the CTRL pin reduces
the maximum output current. The current flowing through
the sense resistor is reflected by the voltage of the ISMON
pin. Drive CTRL pin below 0.2V to stop switching.
At light load, the LTM8083 typically runs at its switching
frequency in discontinuous conduction mode. Both buck
and boost reverse current sense thresholds are set to be
zero, thus preventing any reverse current flowing from
the output to the input.
The LTM8083 contains ADI’s proprietary peak-buck peak-
boost current mode controller with four internal low resis-
tance N-channel DMOS switches, power inductor and a
modest amount of input and output capacitors.
As the load becomes lower and lower, the LTM8083 may
run in pulse-skip mode, where the switches are held off
for multiple cycles (i.e., skipping pulses) to maintain the
regulation.
This control scheme directly senses the inductor current
across the internal power switches and provides smooth
transition between buck region, buck-boost region and
boost region. A simplified block diagram is given on the
previous page. A precisely regulated output voltage is
programmable via an external resistor divider from 1V to
36V. The input voltage range is from 3V to 36V.
The LTM8083 enters shutdown mode with less than
0.9μA quiescent current when the EN/UVLO pin is below
its shutdown threshold (0.3V minimum).
The LTM8083 is equipped with a thermal shutdown that
inhibits operation when junction temperature is above
165°C. Prolonged or repetitive operation at junction tem-
perature higher than 125°C may damage or impair the
reliability of the device.
The LTM8083 is a fixed frequency PWM regulator. A resis-
tor from RT pin to GND sets the switching frequency from
300kHz to 2MHz, allowing applications to be optimized
for broad area and efficiency. Driving the SYNC pin will
synchronize the LTM8083 to an external clock source.
A low-ESL 10nF three-terminal capacitor is added on the
input side as well as output side, improving noise decou-
pling for better EMI performance. With a small filter and
Spread Spectrum function enabled, the LTM8083 mod-
ule passes CISPR25 Class 5 conducted and radiated EMI
standards. Refer to Figure 2 and Figure 3 for more details.
In addition to the voltage control loop, the LTM8083 is
equipped with average current control loop for the output.
Add a current sense resistor between ISP and ISN to limit
the output current below the maximum value set by the
CTRL pin. The ISMON pin reflects the current flowing
through the sense resistor.
Rev. 0
9
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LTM8083
APPLICATIONS INFORMATION
The front page shows a typical LTM8083 application
circuit. This Applications Information section serves as
a guideline of selecting external components for typical
applications. The examples and equations in this section
assume continuous conduction mode unless otherwise
specified.
Switching Frequency Setting
The switching frequency of the LTM8083 can be set by the
internal oscillator. With the SYNC pin pulled to ground, the
switching frequency is set by a resistor from the RT pin
to ground. Table 1 shows R resistor values for common
T
switching frequencies.
Programming Output Voltage and Thresholds
Table 1. Switching Frequency vs RT Value (1% Resistor)
f
(kHz)
R (kΩ)
OSC
T
The LTM8083 has a voltage feedback pin FB that can be
used to program a constant-voltage output. The output
voltage can be set by selecting the values of R5 and R6
(Figure 1) according to the following equation:
300
178
124
400
600
78.7
56.2
40.2
33.2
26.1
21.5
17.4
14.3
800
R5+R6
1000
1200
1400
1600
1800
2000
V
= 1.00V •
OUT
R6
ꢌ
ꢍꢎꢁ
Rꢅ
ꢉꢋ
ꢀꢁꢂꢃ0ꢃꢄ
Rꢊ
ꢆꢇꢈ
Spread Spectrum Frequency Modulation
ꢃ0ꢃꢄ ꢉ0ꢅ
Switching regulators can be particularly troublesome for
applications where electromagnetic interference (EMI) is a
concern. To improve the EMI performance, the LTM8083
implements a triangle spread spectrum frequency mod-
Figure 1. Feedback Resistor Connection
In addition, the FB pin also sets output overvoltage thresh-
old. Once the FB pin hits its overvoltage threshold 1.05V,
the LTM8083 stops switching by turning off all four power
switches for protection. The output overvoltage threshold
can be set as:
ulation scheme. With the SYNC pin tied to INTV , the
CC
LTM8083 starts to spread its switching frequency 25%
above the internal oscillator frequency. Besides, a low-ESL
three-terminal capacitor is added on the input side as well
as output side to further improve the EMI performance.
Figure 2 and Figure 3 show the noise spectrum of the
front page application with spread spectrum enabled and
R5+R6
V
= 1.05V •
OUT(OVP)
R6
Switching Frequency Selection
a small EMI filter at 12V , 12V , and 1A load current.
IN
OUT
The detailed schematic is shown in Figure 25.
The LTM8083 uses a constant frequency control scheme
between 300kHz and 2MHz. Selection of the switching
frequency is a trade-off between efficiency and capacitor
size to filter input and output voltage switching noise.
Low frequency operation improves efficiency by reducing
MOSFET switching loss but requires larger capacitor val-
ues. In a noise-sensitive system, the switching frequency
is usually selected to keep the switching noise out of a
sensitive frequency band. For most applications, 1MHz
switching frequency is recommended.
Frequency Synchronization
The LTM8083 switching frequency can be synchronized
to an external clock using the SYNC pin. Driving the SYNC
with a 50% duty cycle waveform is always a good choice,
otherwise maintain the duty cycle between 10% and 90%.
Due to the use of a phase-locked loop (PLL) inside, there
is no restriction between the synchronization frequency
Rev. 0
10
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LTM8083
APPLICATIONS INFORMATION
ꢚ0
To suppress high frequency switching spikes, ceramic
ꢅꢡꢎꢖꢖ ꢌ ꢡꢕꢔꢕꢓꢖ
ꢔꢎꢢ ꢁꢔꢕꢖꢖꢕꢑꢄꢖ
ꢜ0
ꢞ0
capacitors of at least 1µF should be placed from V to
IN
GND and V
to GND as close to the LTM8083 pins as
OUT
ꢌ0
possible. Due to their excellent low ESR characteristics,
ceramic capacitors can significantly reduce input ripple
voltage and help reduce power loss in the higher ESR
bulk capacitors. X5R or X7R capacitors of dielectrics
are preferred, as these materials retain their capacitance
over wide voltage and temperature ranges. Other types,
including Y5V and Z5U have very large temperature and
voltage coefficients of capacitance. Many ceramic capac-
itors, particularly 0805 or 0603 case sizes, have greatly
reduced capacitance at the desired operating voltage. In
an application circuit, they may have only a small fraction
of their nominal capacitance resulting in much higher out-
put voltage ripple than expected.
ꢟ0
ꢝ0
ꢠ0
ꢋ0
0
ꢛꢋ0
ꢛꢠ0
ꢋꢌ0ꢍ
ꢋꢔ
ꢋ0ꢔ
ꢋ0ꢚꢔ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊ
ꢚ0ꢚꢝ ꢀ0ꢋ
Figure 2. CISPR 25 Average Conducted EMI
ꢜ0
ꢞ0
ꢠ0
ꢌ0
ꢡ0
ꢟ0
ꢢ0
ꢋ0
0
ꢅꢣꢎꢕꢕ ꢌ ꢣꢒꢔꢒꢓꢕ
ꢔꢎꢤ ꢁꢔꢒꢕꢕꢒꢖꢄꢕ
Input Capacitance C :
IN
Discontinuous input current is highest in the buck region
due to the top switch M1 toggling on and off. A 10nF
low-ESL three-terminal capacitor is integrated inside the
module to decouple high-frequency input noise. Make
ꢝꢋ0
sure that the C capacitor network has low enough ESR
IN
ꢝꢢ0
and is sized to handle the maximum RMS current. In buck
region, the input RMS current is given by:
ꢋꢌ0ꢍ
ꢋꢔ
ꢋ0ꢔ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊ
ꢋ00ꢔ
ꢋꢐ
ꢜ0ꢜꢟ ꢀ0ꢢ
V
V
IN
Figure 3. CISPR 25 Average Radiated EMI
OUT
I
= I
•
– 1
oMAX
RMS
V
V
OUT
IN
and the internal oscillator frequency. The rising edge of
the synchronization clock represents the beginning of a
switching cycle.
The formula has a maximum at V = 2V , where I =
RMS
IN
OUT
I
/2. This simple worst-case condition is commonly
oMAX
used for design.
C and C
IN
Selection
OUT
Output Capacitance C
:
OUT
Input and output capacitors are necessary to suppress
voltage ripple caused by discontinuous current moving in
or out of the regulator. A parallel combination of capaci-
tors is typically used to achieve high capacitance and low
equivalent series resistance (ESR). Dry tantalum, special
polymer, aluminum electrolytic and ceramic capacitors are
all available in surface mount packages. Capacitors with
low ESR and high ripple current ratings, such as OS-CON
and POSCAP are also available.
Discontinuous current shifts from the input to the output
in the boost region. Make sure that the C
capacitor
network is capable of reducing the outpuOtUvToltage rip-
ple. The effects of ESR and the bulk capacitance must be
considered when choosing the right capacitor for a given
Rev. 0
11
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LTM8083
APPLICATIONS INFORMATION
output ripple voltage. The maximum steady state ripple
due to charging and discharging the bulk capacitance is
given by:
addition, the EN/UVLO pin sinks 2.5µA when the voltage
on the pin is below 1.21V. This current provides user
programmable hysteresis based on the value of R1. The
programmable UVLO thresholds are:
IoMAX • V
– V
IN(MIN)
(
)
OUT
ΔVCAP(BOOST)
=
R1+ R2
COUT • VOUT • fSW
V
= 1.24V •
= 1.21V •
+ 2.5µA • R1
IN(UVLO+)
R2
VOUT • VIN(MAX) – V
(
)
R1+ R2
OUT
ΔVCAP(BUCK)
=
V
IN(UVLO–)
2
R2
8 •L •COUT • VIN(MAX) • fSW
Figure 4 shows the implementation of external shutdown
control while still using the UVLO function. The NMOS
grounds the EN/UVLO pin when turned on, and puts the
LTM8083 in shutdown with 0.9µA quiescent current.
The maximum steady ripple due to the voltage drop
across the ESR is given by:
VOUT •IoMAX
ΔVESR(BOOST)
=
•ESR
V
IN(MAX)
ꢖ
ꢏꢇ
VOUT • VIN(MAX) – V
(
)
•ESR
OUT
ΔVESR(BUCK)
=
Rꢅ
Rꢓ
VIN(MAX) •L • fSW
ꢔꢇꢉꢕꢖꢀꢋ
RUNꢉꢊꢁꢋꢌ
ꢍꢋꢇꢁRꢋꢀ
ꢎꢋꢌꢁꢏꢋꢇꢐꢀꢑ
ꢀꢁꢂꢃ0ꢃꢄ
ꢆꢇꢈ
The bulk output capacitors defined as C
are chosen
OUT
with low enough ESR to meet the output voltage ripple
and transient requirements. COUT can be the low ESR
tantalum capacitor, the low ESR polymer capacitor or
the ceramic capacitor. Multiple capacitors can be placed
in parallel to meet the ESR and RMS current handling
requirements. The typical capacitance is 10μF. Additional
output filtering may be required by the system designer,
if further reduction of output ripple or dynamic transient
spike is required. A 10nF low-ESL three-terminal capaci-
tor is integrated inside the module to decouple high-fre-
quency output noise. Table 6 shows a matrix of different
output voltages and output capacitors to minimize the
voltage droop and overshoot at a current transient.
ꢃ0ꢃꢄ ꢒ0ꢄ
Figure 4. VIN Undervoltage Lockout (UVLO)
A resistor divider from VIN to the OVLO pin implements VIN
overvoltage lockout (OVLO). The OVLO rising threshold
is set at 1.235V with 115mV falling hysteresis. Figure 5
shows the implementation of V OVLO function. The pro-
grammable OVLO thresholds are:
IN
R3 + R4
V
= 1.235V •
= 1.120V •
IN(OVLO+)
R4
R3 + R4
V
IN(OVLO–)
R4
INTV Regulator
CC
An internal P-channel low dropout regulator produces
3.6V at the INTVCC pin from the SVIN supply pin. The
ꢋ
ꢌꢆ
Rꢄ
Rꢉ
INTV powers internal circuitry and gate drivers in the
CC
ꢊꢋꢀꢊ
LTM8083. No bypassing capacitor is required.
ꢀꢁꢂꢃ0ꢃꢄ
ꢅꢆꢇ
Programming V UVLO and OVLO
IN
ꢃ0ꢃꢄ ꢈ0ꢉ
A resistor divider from VIN to the EN/UVLO pin implements
IN
falling threshold is set at 1.21V with 30mV hysteresis. In
V
undervoltage lockout (UVLO). The EN/UVLO enable
Figure 5. VIN Overvoltage Lockout (OVLO)
Rev. 0
12
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LTM8083
APPLICATIONS INFORMATION
Programming Current Limit Threshold
higher load current, lower switching frequency, or smaller
value output filter capacitor. Some level of ripple signal
The ISP-ISN current is programmed by placing a cur-
is acceptable, and the compensation capacitor on the V
C
rent sensing resistor, R , in series with the output. The
CS
pin filters the signal so the average difference between
ISP and ISN is regulated to the user-programmed value.
The ripple voltage amplitude (peak-to-peak) in excess
of 20mV should not cause misoperation, but may lead
to noticeable offset between the average value and the
user-programmed value.
voltage drop across R is (Kelvin) sensed by the ISP and
CS
ISN pins. The voltage on CTRL pin determines current
limit threshold voltage of ISP-ISN. The default setting
of the current limit threshold is full-scale 100mV. The
CTRL pin is pulled up to 2V reference voltage with a 100k
resistor internally. A resistor can be added between CTRL
and GND to form a voltage divider or an external voltage
below 1.3V can be applied to the CTRL pin to reduce the
current limit threshold of ISP-ISN across the output sense
Monitoring Sensed Current
The ISMON pin provides a linear indication of the cur-
rent flowing through the sensing resistor on the output.
It outputs a buffered and amplified monitor of the voltage
difference between ISP and ISN pins. The equation for
resistor. When the CTRL pin voltage, V , is less than
CTRL
1.15V, the current limit threshold is:
V
–250mV
CTRL
V
is:
I
=
ISMON
CL
10 • R
CS
V
=10 • V
+ 250mV
ISMON
(ISP-ISN)
When V
is between 1.15V and 1.35V, the current limit
thresholCdTRvLaries with V
, but departs from the equa-
Soft-Start
CTRL
tion above by an increasing amount as V
increases.
CTRL
The SS pin can be used to program soft-start by connect-
ing an external capacitor C from the SS pin to ground.
Ultimately, when VCTRL > 1.35V the output current thresh-
old is 100mV and no longer varies. The typical V
SS
(ISP-ISN)
A 10nF capacitor has been integrated inside the module.
The internal 32µA pull-up current charges up the capaci-
tor, creating a voltage ramp on the SS pin. As the SS pin
voltage rises linearly from 0.25V to 1V (and beyond), the
output voltage rises smoothly and transitions into output
voltage regulation. The soft-start range is defined to be
the voltage range from 0V to the FB voltage, which is
1V when output is regulated. The soft-start time can be
approximately calculated as:
threshold vs V
is listed in Table 2.
CTRL
Table 2. V(ISP-ISN) Threshold vs VCTRL
(V)
V
V
(mV)
CTRL
(ISP-ISN)
1.15
90
1.20
1.25
1.30
1.35
94.5
98
99.5
100
C
+ 10nF
32µA
SS
t
= 1V •
SS
When VCTRL is higher than 1.35V, the output current limit
threshold is:
Make sure the C is at least five to ten times larger than
SS
100mV
I
=
the optional compensation capacitor on the V pin.
CL
C
R
CS
Loop Compensation
The CTRL pin can also be used in conjunction with a
thermistor to provide overtemperature protection for the
output load, or with a resistor divider to VIN to reduce
output power and switching current when VIN is low.
The presence of a time varying differential voltage ripple
signal across ISP and ISN at the switching frequency is
expected. The amplitude of this signal is increased by
The LTM8083 has already been internally compensated
and should be stable for all output voltages and capac-
itor combinations including all ceramic capacitor appli-
cations. If more switching noise attenuation is required,
an optional capacitor can be added on V pin to ground
outside of the module. Furthermore, to further increase
C
Rev. 0
13
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LTM8083
APPLICATIONS INFORMATION
the bandwidth and phase margin of the circuit, a feedfor-
move. This value is determined with the part mounted
to a 95mm × 76mm PCB with four layers.
ward capacitor (C ) could be added by connecting from
FF
V
to FB pin which is in parallel with R5 in Figure 1.
OUT
2. θ , the thermal resistance from junction to the
JCbottom
The LTpowerCAD design tool is available to down-
load online to perform specific control loop optimiza-
tion and analyze the control stability and load transient
performance.
bottom of the product case, is determined with all of
the component power dissipation flowing through the
bottom of the package. In the typical µModule reg-
ulator, the bulk of the heat flows out the bottom of
the package, but there is always heat flow out into the
ambient environment. As a result, this thermal resis-
tance value may be useful for comparing packages,
but the test conditions don’t generally match the user’s
application.
Thermal Considerations and Output Current Derating
The thermal resistances reported in the Pin Configuration
section of the data sheet are consistent with those param-
eters defined by JESD 51-12 and are intended for use with
finite element analysis (FEA) software modeling tools that
leverage the outcome of thermal modeling, simulation,
and correlation to hardware evaluation performed on a
µModule package mounted to a hardware test board.
The motivation for providing these thermal coefficients
is found in JESD 51-12 (Guidelines for Reporting and
Using Electronic Package Thermal Information).
3. θ
, the thermal resistance from junction to top of
JCtop
the product case, is determined with nearly all of the
component power dissipation flowing through the top
of the package. As the electrical connections of the typ-
ical µModule regulator are on the bottom of the pack-
age, it is rare for an application to operate such that
most of the heat flows from the junction to the top of
the part. As in the case of θ
, this value may be
JCbottom
Many designers may opt to use laboratory equipment and
a test vehicle such as the demo board to anticipate the
µModule regulator’s thermal performance in their appli-
cation at various electrical and environmental operating
conditions to compliment any FEA activities. Without
FEA software, the thermal resistances reported in the
Pin Configuration section are, in and of themselves, not
relevant to providing guidance of thermal performance;
instead, the derating curves provided in this data sheet
can be used in a manner that yields insight and guid-
ance pertaining to one’s application usage, and can be
adapted to correlate thermal performance to one’s own
application.
useful for comparing packages but the test conditions
don’t generally match the user’s application.
A graphical representation of the aforementioned ther-
mal resistances is given in Figure 6; blue resistances
are contained within the μModule regulator, whereas
green resistances are external to the µModule package.
As a practical matter, it should be clear to the reader that
no individual or sub-group of the three thermal resis-
tance parameters defined by JESD 51-12 or provided
in the Pin Configuration section replicates or conveys
normal operating conditions of a μModule regulator.
For example, in normal board-mounted applications,
never does 100% of the device’s total power loss (heat)
thermally conduct exclusively through the top or exclu-
sively through bottom of the µModule package—as the
The Pin Configuration section gives three thermal coeffi-
cients explicitly defined in JESD 51-12; these coefficients
are quoted or paraphrased below:
standard defines for θ
and θ
, respectively.
JCbottom
In practice, power losJsCitsopthermally dissipated in both
directions away from the package—granted, in the
absence of a heat sink and airflow, a majority of the
heat flow is into the board.
1. θJA, the thermal resistance from junction to ambient, is
the natural convection junction-to-ambient air thermal
resistance measured in a one cubic foot sealed enclo-
sure. This environment is sometimes referred to as
“still air” although natural convection causes the air to
Rev. 0
14
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LTM8083
APPLICATIONS INFORMATION
Within the LTM8083, be aware that there are multi-
ple power devices and components dissipating power,
with a consequence that the thermal resistances rel-
ative to different junctions of components or die are
not exactly linear with respect to total package power
loss. To reconcile this complication without sacrificing
modeling simplicity—but also, not ignoring practical
realities—an approach has been taken using FEA soft-
ware modeling along with laboratory testing in a con-
trolled environment chamber to reasonably define and
correlate the thermal resistance values supplied in this
data sheet: (1) Initially, FEA software is used to accu-
rately build the mechanical geometry of the LTM8083
and the specified PCB with all of the correct material
coefficients along with accurate power loss source
definitions; (2) this model simulates a software-de-
fined JEDEC environment consistent with JESD51-
12 to predict power loss heat flow and temperature
readings at different interfaces that enable the calcu-
lation of the JEDEC-defined thermal resistance values;
(3) the model and FEA software is used to evaluate the
LTM8083 with heat sink and airflow; (4) having solved
for and analyzed these thermal resistance values and
simulated various operating conditions in the software
model, a thorough laboratory evaluation replicates the
simulated conditions with thermocouples within a
controlled environment chamber while operating the
device at the same power loss as that which was sim-
ulated. An outcome of this process and due diligence
yields the set of derating curves shown in this data
sheet. After these laboratory tests have been performed
and correlated to the LTM8083 model, then the θ is
JA
provided assuming approximately 100% of power loss
flows from the junction through the board into ambient
with no airflow or top mounted heat sink.
θ
ꢎꢈꢒꢍꢓꢌꢆꢒꢔꢓꢆꢔꢕꢅꢚꢌꢊꢒꢓ Rꢊꢖꢌꢖꢓꢕꢒꢍꢊ
ꢎꢕ
ꢄꢅꢆꢇꢈꢉꢊ ꢇꢊꢋꢌꢍꢊ
θ
ꢎꢈꢒꢍꢓꢌꢆꢒꢔꢓꢆꢔꢍꢕꢖꢊ
ꢍꢕꢖꢊ ꢗꢓꢆꢘꢙꢔꢓꢆꢔꢕꢅꢚꢌꢊꢒꢓ
Rꢊꢖꢌꢖꢓꢕꢒꢍꢊ
ꢎꢍꢏꢐꢑ
ꢗꢓꢆꢘꢙ Rꢊꢖꢌꢖꢓꢕꢒꢍꢊ
ꢎꢈꢒꢍꢓꢌꢆꢒ
ꢕꢅꢚꢌꢊꢒꢓ
θ
ꢎꢍꢛꢐꢏ
ꢎꢈꢒꢍꢓꢌꢆꢒꢔꢓꢆꢔꢍꢕꢖꢊ
ꢍꢕꢖꢊ ꢗꢚꢆꢓꢓꢆꢅꢙꢔꢓꢆꢔꢚꢆꢕRꢇ
Rꢊꢖꢌꢖꢓꢕꢒꢍꢊ
ꢚꢆꢕRꢇꢔꢓꢆꢔꢕꢅꢚꢌꢊꢒꢓ
Rꢊꢖꢌꢖꢓꢕꢒꢍꢊ
ꢗꢚꢆꢓꢓꢆꢅꢙ Rꢊꢖꢌꢖꢓꢕꢒꢍꢊ
ꢀ0ꢀꢁ ꢂ0ꢃ
Figure 6. Graphical Approximation of the Thermal Coefficients, Including JESD 51-12 Terms
Rev. 0
15
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LTM8083
APPLICATIONS INFORMATION
ꢎ.ꢏ
ꢎ.ꢐ
ꢎ.0
0.ꢑ
0.ꢒ
0.ꢏ
0.ꢐ
0
ꢎ.ꢏ
ꢎ.0
ꢐ.ꢏ
ꢐ.0
0.ꢏ
0
ꢎ.0
ꢏ.ꢐ
ꢏ.0
ꢑ.ꢐ
ꢑ.0
0.ꢐ
0
ꢖ
ꢗꢇ
ꢖ
ꢗꢇ
ꢖ
ꢗꢇ
ꢖ
ꢗꢇ
ꢖ
ꢗꢇ
ꢖ
ꢗꢇ
ꢘ ꢎ.ꢎꢖ
ꢘ ꢐꢖ
ꢘ
ꢘ
ꢘ
ꢘ
ꢚ ꢓ.ꢓꢘ
ꢚ ꢖꢘ
ꢚ ꢎꢐꢘ
ꢚ ꢐꢏꢘ
ꢖ
ꢖ
ꢖ
ꢖ
ꢖ
ꢘ ꢒ.ꢒꢖ
ꢘ ꢏꢖ
ꢘ ꢐꢎꢖ
ꢘ ꢎꢙꢖ
ꢘ ꢒꢔꢖ
ꢙꢇ
ꢙꢇ
ꢙꢇ
ꢙꢇ
ꢗꢇ
ꢗꢇ
ꢗꢇ
ꢗꢇ
ꢗꢇ
ꢘ ꢒꢖ
ꢘ ꢑꢏꢖ
ꢘ ꢏꢙꢖ
ꢘ ꢎꢕꢖ
0
0
0
0.ꢓ
0.ꢒ
0.ꢗ
ꢎ.ꢐ
ꢎ.ꢖ
0
0.ꢒ
0.ꢔ
0.ꢕ
ꢐ.ꢎ
ꢐ.ꢏ
0
0.ꢎ
0.ꢕ
0.ꢔ
ꢑ.ꢏ
ꢑ.ꢐ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢑ0ꢑꢓ ꢔ0ꢕ
ꢑ0ꢑꢒ ꢓ0ꢑ
ꢒ0ꢒꢎ ꢓ0ꢔ
Figure 7. Power Loss at 3.3VOUT
Figure 8. Power Loss at 5VOUT
Figure 9. Power Loss at 8VOUT
ꢎ.ꢏ
ꢎ.0
ꢐ.ꢏ
ꢐ.0
0.ꢏ
0
ꢎ.ꢏ
ꢎ.0
ꢐ.ꢏ
ꢐ.0
0.ꢏ
0
ꢎ.0
ꢏ.ꢐ
ꢏ.0
ꢑ.ꢐ
ꢑ.0
0.ꢐ
0
ꢖ
ꢖ
ꢖ
ꢖ
ꢖ
ꢘ ꢒ.ꢒꢖ
ꢘ ꢔꢖ
ꢘ ꢐꢎꢖ
ꢘ ꢎꢙꢖ
ꢘ ꢒꢔꢖ
ꢖ
ꢖ
ꢖ
ꢖ
ꢖ
ꢘ ꢏꢖ
ꢖ
ꢖ
ꢖ
ꢖ
ꢖ
ꢘ ꢒꢖ
ꢗꢇ
ꢗꢇ
ꢗꢇ
ꢗꢇ
ꢗꢇ
ꢗꢇ
ꢗꢇ
ꢗꢇ
ꢗꢇ
ꢗꢇ
ꢗꢇ
ꢗꢇ
ꢗꢇ
ꢗꢇ
ꢗꢇ
ꢘ ꢐꢎꢖ
ꢘ ꢐꢑꢖ
ꢘ ꢎꢙꢖ
ꢘ ꢒꢔꢖ
ꢘ ꢑꢏꢖ
ꢘ ꢑꢒꢖ
ꢘ ꢏꢙꢖ
ꢘ ꢎꢔꢖ
0.ꢒ
0.ꢔ
0.ꢕ
ꢐ.ꢎ
ꢐ.ꢏ
0
0.ꢒ
0.ꢔ
0.ꢕ
ꢐ.ꢎ
ꢐ.ꢏ
0
0.ꢎ
0.ꢔ
0.ꢕ
ꢑ.ꢏ
ꢑ.ꢐ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢑ0ꢑꢒ ꢓꢐ0
ꢑ0ꢑꢒ ꢓꢐꢐ
ꢒ0ꢒꢎ ꢓꢑꢏ
Figure 10. Power Loss at 12VOUT
Figure 11. Power Loss at 18VOUT
Figure 12. Power Loss at 24VOUT
ꢎ.ꢏ
ꢎ.0
ꢐ.ꢏ
ꢐ.0
ꢑ.ꢏ
ꢑ.0
0.ꢏ
0
ꢂ.ꢃ
ꢂ.0
0.ꢈ
0.ꢆ
0.ꢇ
0.ꢃ
0
ꢂ.ꢆ
ꢂ.ꢇ
ꢂ.ꢃ
ꢂ.0
0.ꢈ
0.ꢆ
0.ꢇ
0.ꢃ
0
ꢖ
ꢖ
ꢖ
ꢖ
ꢘ ꢑꢐꢖ
ꢘ ꢑꢒꢖ
ꢘ ꢐꢙꢖ
ꢘ ꢎꢔꢖ
ꢗꢇ
ꢗꢇ
ꢗꢇ
ꢗꢇ
0ꢖꢙꢊ
0ꢖꢙꢊ
ꢃ00ꢖꢙꢊ
ꢇ00ꢖꢙꢊ
ꢃ00ꢖꢙꢊ
ꢇ00ꢖꢙꢊ
0.ꢎ
0.ꢔ
0.ꢕ
ꢑ.ꢐ
ꢑ.ꢏ
ꢀ0 ꢇ0 ꢄ0 ꢆ0 ꢁ0 ꢈ0 ꢅ0 ꢂ00 ꢂꢂ0 ꢂꢃ0
ꢀ0 ꢇ0 ꢄ0 ꢆ0 ꢁ0 ꢈ0 ꢅ0 ꢂ00 ꢂꢂ0 ꢂꢃ0
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢉꢊꢋꢌꢍꢎꢏ ꢏꢍꢊꢐꢍRꢉꢏꢑRꢍ ꢒꢓꢔꢕ
ꢉꢊꢋꢌꢍꢎꢏ ꢏꢍꢊꢐꢍRꢉꢏꢑRꢍ ꢒꢓꢔꢕ
ꢒ0ꢒꢎ ꢓꢑꢎ
ꢈ0ꢈꢀ ꢙꢂꢇ
ꢈ0ꢈꢀ ꢙꢂꢄ
Figure 13. Power Loss at 36VOUT
Figure 14. 5V to 5V Derating
Curve, No Heat Sink
Figure 15. 12V to 5V Derating
Curve, No Heat Sink
Rev. 0
16
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LTM8083
APPLICATIONS INFORMATION
0.ꢁ
0.ꢆ
0.ꢄ
0.ꢇ
0.ꢀ
0.ꢃ
0.ꢂ
0
ꢂ.ꢆ
ꢂ.ꢇ
ꢂ.ꢃ
ꢂ.0
0.ꢈ
0.ꢆ
0.ꢇ
0.ꢃ
0
ꢂ.ꢆ
ꢂ.ꢇ
ꢂ.ꢃ
ꢂ.0
0.ꢈ
0.ꢆ
0.ꢇ
0.ꢃ
0
0ꢖꢙꢊ
ꢃ00ꢖꢙꢊ
ꢇ00ꢖꢙꢊ
0ꢖꢙꢊ
ꢃ00ꢖꢙꢊ
ꢇ00ꢖꢙꢊ
0ꢖꢙꢊ
ꢃ00ꢖꢙꢊ
ꢇ00ꢖꢙꢊ
ꢀ0 ꢇ0 ꢄ0 ꢆ0 ꢁ0 ꢈ0 ꢅ0 ꢂ00 ꢂꢂ0 ꢂꢃ0
ꢀ0 ꢇ0 ꢄ0 ꢆ0 ꢁ0 ꢈ0 ꢅ0 ꢂ00 ꢂꢂ0 ꢂꢃ0
ꢀ0 ꢇ0 ꢄ0 ꢆ0 ꢁ0 ꢈ0 ꢅ0 ꢂ00 ꢂꢂ0 ꢂꢃ0
ꢉꢊꢋꢌꢍꢎꢏ ꢏꢍꢊꢐꢍRꢉꢏꢑRꢍ ꢒꢓꢔꢕ
ꢉꢊꢋꢌꢍꢎꢏ ꢏꢍꢊꢐꢍRꢉꢏꢑRꢍ ꢒꢓꢔꢕ
ꢉꢊꢋꢌꢍꢎꢏ ꢏꢍꢊꢐꢍRꢉꢏꢑRꢍ ꢒꢓꢔꢕ
ꢈ0ꢈꢀ ꢙꢂꢆ
ꢈ0ꢈꢀ ꢙꢂꢁ
ꢈ0ꢈꢀ ꢙꢂꢈ
Figure 16. 5V to 12V Derating
Curve, No Heat Sink
Figure 17. 12V to 12V
Derating Curve, No Heat Sink
Figure 18. 36V to 12V Derating
Curve, No Heat Sink
0.ꢄ0
0.ꢇꢄ
0.ꢇ0
0.ꢀꢄ
0.ꢀ0
0.ꢃꢄ
0.ꢃ0
0.ꢂꢄ
ꢂ.ꢆ
ꢂ.ꢇ
ꢂ.ꢃ
ꢂ.0
0.ꢈ
0.ꢆ
0.ꢇ
0.ꢂ0
0ꢖꢙꢊ
ꢃ00ꢖꢙꢊ
ꢇ00ꢖꢙꢊ
0ꢖꢙꢊ
ꢃ00ꢖꢙꢊ
ꢇ00ꢖꢙꢊ
0.ꢃ
0
0.0ꢄ
0
ꢀ0 ꢇ0 ꢄ0 ꢆ0 ꢁ0 ꢈ0 ꢅ0 ꢂ00 ꢂꢂ0 ꢂꢃ0
ꢀ0 ꢇ0 ꢄ0 ꢆ0 ꢁ0 ꢈ0 ꢅ0 ꢂ00 ꢂꢂ0 ꢂꢃ0
ꢉꢊꢋꢌꢍꢎꢏ ꢏꢍꢊꢐꢍRꢉꢏꢑRꢍ ꢒꢓꢔꢕ
ꢉꢊꢋꢌꢍꢎꢏ ꢏꢍꢊꢐꢍRꢉꢏꢑRꢍ ꢒꢓꢔꢕ
ꢈ0ꢈꢀ ꢙꢂꢅ
ꢈ0ꢈꢀ ꢙꢃ0
Figure 19. 12V to 36V Derating
Curve, No Heat Sink
Figure 20. 36V to 36V Derating
Curve, No Heat Sink
Table 3. 5V Output
DERATING CURVE
Figures 14 and 15
Figures 14 and 15
Figures 14 and 15
V
(V)
POWER LOSS CURVE
Figure 8
AIR FLOW (LFM)
HEAT SINK
None
θ
θ
(°C/W)
23
IN
JA
5, 12
5, 12
5, 12
0
Figure 8
200
400
None
18
Figure 8
None
16
Table 4. 12V Output
DERATING CURVE
V
(V)
POWER LOSS CURVE
Figure 10
AIR FLOW (LFM)
HEAT SINK
None
(°C/W)
23
IN
JA
Figures 16, 17 and 18
Figures 16, 17 and 18
Figures 16, 17 and 18
5, 12, 36
0
5, 12, 36
5, 12, 36
Figure 10
200
400
None
18
Figure 10
None
16
Rev. 0
17
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LTM8083
APPLICATIONS INFORMATION
Table 5. 36V Output
DERATING CURVE
Figures 19 and 20
Figures 19 and 20
Figures 19 and 20
V
(V)
POWER LOSS CURVE
Figure 13
AIR FLOW (LFM)
HEAT SINK
None
θ
(°C/W)
23
IN
JA
12, 36
12, 36
12, 36
0
Figure 13
200
400
None
18
Figure 13
None
16
The 3.3V, 5V, 8V, 12V, 18V, 24V and 36V power loss
curves in Figure 7 to Figure 13 can be used in coordina-
tion with the load current derating curves in Figure 14 to
Figure 20 for calculating an approximate θJA thermal resis-
tance for the LTM8083 with various airflow conditions.
The power loss curves are taken at room temperature, and
are increased with a multiplicative factor according to the
ambient temperature. This approximate factor is: 1.2 for
120°C at junction temperature. Maximum load current is
achievable while increasing ambient temperature as long
as the junction temperature is less than 120°C, which is
a 5°C guard band from maximum junction temperature
of 125°C. When the ambient temperature reaches a point
where the junction temperature is 120°C, then the load
current is lowered to maintain the junction at 120°C while
increasing ambient temperature up to 120°C. The derating
curves are plotted with the output current starting at 1.5A
and the ambient temperature at 30°C. The output voltages
are 5V, 12V, and 36V. These are chosen to include the
lower and higher output voltage ranges for correlating
the thermal resistance. Thermal models are derived from
several temperature measurements in a controlled tem-
perature chamber along with thermal modeling analysis.
The junction temperatures are monitored while ambient
temperature is increased with and without airflow. The
power loss increase with ambient temperature change
is factored into the derating curves. The junctions are
maintained at 120°C maximum while lowering output cur-
rent or power with increasing ambient temperature. The
decreased output current will decrease the internal mod-
ule loss as ambient temperature is increased. The mon-
itored junction temperature of 120°C minus the ambient
operating temperature specifies how much module tem-
perature rise can be allowed. As an example, in Figure 18
the load current is derated to 0.6A at ~100°C with no air
flow or heat sink and the power loss for the 36V to 12V
at 0.6A output is about 0.84W. The 0.84W loss is calcu-
lated with the 0.7W room temperature loss from the 36V
to 12V power loss curve at 0.6A, and the 1.2 multiply-
ing factor at 120°C junction temperature. If the 100°C
ambient temperature is subtracted from the 120°C junc-
tion temperature, then the difference of 20°C divided by
0.84W equals a 23.8°C/W θ thermal resistance. Table 4
JA
specifies a 23°C/W value which is very close. Table 3,
Table 4, Table 5, provide equivalent thermal resistances
for 5V, 12V, and 36V outputs with and without airflow and
heat sinking. The derived thermal resistances in Table 3,
Table 4 and Table 5, for the various conditions can be
multiplied by the calculated power loss as a function of
ambient temperature to derive temperature rise above
ambient, thus maximum junction temperature. Room
temperature power loss can be derived from the efficiency
curves in the Typical Performance Characteristics section
and adjusted with the above ambient temperature mul-
tiplicative factors. The printed circuit board is a 1.6mm
thick 4-layer board with two ounce copper for the two
outer layers and one ounce copper for the two inner lay-
ers. The PCB dimensions are 64mm × 64mm. A Typical
thermal image based on this PCB is shown in Figure 21.
8083 F21
Figure 21. Thermal Image of LTM8083 Running from
24V Input and 36V Output with 1A Load at 25°C Ambient
without Airflow or Heat Sink
Rev. 0
18
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LTM8083
APPLICATIONS INFORMATION
PC Board Layout Checklist/Examples
• The ground plane layer should not have any traces.
The high integration of LTM8083 makes the PCB board
layout very simple and easy. However, to optimize its
electrical and thermal performance, some layout consid-
erations are still necessary.
• Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise
of module. Connect the copper areas to GND
• Keep separation between SYNC and RT pin traces to
minimize noise due to crosstalk between these signals.
• Use large PCB copper areas for high current paths,
including V , GND and V . It helps to minimize the
IN
OUT
• Route ISP and ISN traces together with minimum PCB
trace spacing. Avoid sense lines passing through noisy
areas, such as switch nodes. Ensure accurate current
sensing with Kelvin connections at the current sense
resistor.
PCB conduction loss and thermal stress.
• Place high frequency ceramic input and output capac-
itors next to the V , GND and V
pins to minimize
IN
OUT
high frequency noise.
• Place a dedicated power ground layer underneath
the unit.
• Connect the optional V pin compensation capacitor
C
close to the module, between VC and the signal ground.
The capacitor helps to filter the effects of PCB noise
and output voltage ripple voltage from the compensa-
tion loop.
• Use planes for V and V
to maintain good voltage
IN
OUT
filtering and to keep power losses low.
• To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
Figure 22 gives a good example of the recommended
layout.
• Do not put via directly on the pad, unless they are
capped or plated over.
Table 6. Output Voltage Response vs Component Matrix (Refer to Figure 23)
C
PART NUMBER
VALUE
OUT
MURATA
GCM32EC71H106KA03
10µF, 50V, 1210, X7S
LOAD STEP RISING
PK-PK
DEVIATION
(mV)
RECOVERY
V
V
C
OUT
AND FALLING TIME
(µs)
TIME
(μs)
IN
OUT
(V)
3.3
5
(V)
f
(MHz)
(CER CAP)
COMPENSATION
Internal
LOAD STEP (A)
0 – 0.375
0 – 0.375
0 – 0.375
0 – 0.375
0 – 0.375
0 – 0.375
0 – 0.375
0 – 0.375
0 – 0.375
0 – 0.375
SW
5
1, See Note
10µF
1
1
1
1
1
1
1
1
1
1
640
280
150
320
440
440
350
340
1600
2000
150
75
5
1
1
1
1
1
1
1
1
1
10µF
Internal
12
36
6
5
10µF
Internal
100
150
170
230
200
200
200
220
5
10µF
Internal
12
12
12
12
36
36
10µF
Internal
12
24
36
18
36
10µF
Internal
10µF
Internal
10µF
Internal
10µF
Internal
10µF
Internal
Note: Use 40.2kΩ R resistor to set switching frequency at 1MHz.
T
Rev. 0
19
For more information www.analog.com
LTM8083
APPLICATIONS INFORMATION
ꢍꢆꢎ
ꢍꢆꢎ
ꢅꢆꢄ
R
ꢈꢈ
ꢉ
ꢇꢄ
ꢅꢆ
ꢂꢊ
ꢍ
ꢂ
ꢏ
ꢎ
ꢈ
ꢊ
ꢐ
ꢄ
ꢅꢆ
ꢄ
ꢋꢌꢉ
ꢃ
ꢑ
ꢁ
ꢒ
ꢓ
ꢔ
ꢕ
ꢍꢆꢎ
ꢀ0ꢀꢁ ꢂꢃꢁ
Figure 22. Recommended PCB Layout
TYPICAL APPLICATIONS
ꢀ
ꢀ
ꢁꢂ
ꢁꢂꢃ
ꢀ
ꢀ
ꢁꢂꢃ
ꢁꢂ
ꢃꢀ ꢄꢅ ꢃꢆꢀ
ꢄꢅꢀ
ꢀ0ꢁꢂ
ꢀ0ꢁꢂ
ꢀꢁ
ꢀ00ꢁ
ꢂꢃ
ꢀꢀ0ꢁ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁ
ꢀꢁ0ꢂ
ꢀ0ꢁ
ꢀꢁꢂꢃ0ꢃꢄ
ꢀꢁꢂꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢄꢄ
ꢀꢁRꢂ
ꢀꢁꢀꢂ
Rꢀ
ꢀꢁꢂ
ꢀ
ꢁ
ꢀꢁꢂꢃꢄ
ꢀ0.ꢁꢂ
ꢀꢀ
ꢀꢁꢂ ꢀꢁꢀꢂ ꢀꢁꢂꢃ
ꢀ0ꢀꢁ ꢂꢃ0ꢄ
Figure 23. 18W (12V, 1.5A) 1MHz Buck-Boost Voltage Regulator
Rev. 0
20
For more information www.analog.com
LTM8083
TYPICAL APPLICATIONS
50mΩ
ꢀ
ꢀ
ꢁꢂ
ꢁꢂꢃ
ꢀ
ꢀ
ꢁꢂꢃ
ꢁꢂ
ꢃꢀ ꢄꢅ ꢃꢆꢀ
ꢄꢀ
ꢀ0ꢁꢂ
ꢀ0ꢁꢂ
ꢀꢁ
ꢀ00ꢁ
ꢂꢃ
Rꢀ
ꢁ0ꢂ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁ
ꢀꢁ0ꢂ
ꢀ0ꢁ
ꢀꢁꢂꢃ0ꢃꢄ
10Ω
ꢀꢁꢂꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢄꢄ
ꢀꢁꢂ
10Ω
ꢀꢁRꢂ
ꢀꢁꢀꢂ
Rꢀ
ꢀꢁꢂ
ꢀꢀ0ꢁ
ꢀ
ꢁ
ꢀꢁꢂꢃꢄ
ꢀ0.ꢁꢂ
ꢀꢀ
ꢀꢁꢂ ꢀꢁꢀꢂ ꢀꢁꢂꢃ
ꢀ0ꢀꢁ ꢂꢃ0ꢁ
Figure 24. 7.5W (5V, 1.5A) 1MHz Buck-Boost Voltage Regulator with Output Current Monitor
1000Ω AT 100MHz
0805 FERRITE BEAD
×2
300Ω AT 100MHz
0805 FERRITE BEAD
ꢀ
ꢀ
ꢁꢂ
ꢁꢂꢃ
ꢀ
ꢀ
ꢁꢂꢃ
ꢁꢂ
ꢃꢀ ꢄꢅ ꢃꢆꢀ
ꢄꢅꢀ
0.ꢀꢁꢂ
0.ꢀꢁꢂ
ꢀ0ꢁꢂ
ꢀ0ꢁꢂ
ꢀ0ꢁꢂ
ꢀꢁ
ꢀ00ꢁ
ꢂꢃ
ꢀꢀ0ꢁ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁ
ꢀꢁ0ꢂ
ꢀ0ꢁ
ꢀꢁꢂꢃ0ꢃꢄ
ꢀꢁꢂꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢄꢄ
ꢀꢁRꢂ
ꢀꢁꢀꢂ
Rꢀ
ꢀꢁꢂ
ꢀ
ꢁ
ꢀꢁꢂꢃꢄ
ꢀ0.ꢁꢂ
ꢀꢀ
ꢀꢁꢂ ꢀꢁꢀꢂ ꢀꢁꢂꢃ
ꢀ0ꢀꢁ ꢂꢃ0ꢄ
Figure 25. 18W (12V, 1.5A) 1MHz Buck-Boost Voltage Regulator Compliant with CISPR25 Class 5 Limits
Rev. 0
21
For more information www.analog.com
LTM8083
PACKAGE DESCRIPTION
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
LTM8083 Component BGA Pinout
PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
A1
B1
C1
D1
E1
F1
GND
GND
GND
GND
GND
GND
GND
A2
B2
C2
D2
E2
F2
GND
GND
GND
GND
GND
GND
GND
A3
B3
C3
D3
E3
F3
GND
GND
GND
GND
GND
ISN
A4
B4
C4
D4
E4
F4
V
V
A5
B5
C5
D5
E5
F5
V
V
A6
B6
C6
D6
E6
F6
SV
IN
A7
B7
C7
D7
E7
F7
TST2
OVLO
CTRL
GND
RT
IN
IN
IN
IN
EN/UVLO
INTV
GND
GND
GND
GND
GND
GND
CC
ISMON
V
C
V
V
V
OUT
V
OUT
SS
FB
OUT
OUT
G1
G2
G3
ISP
G4
G5
G6
SYNC
G7
TST1
Rev. 0
22
For more information www.analog.com
LTM8083
PACKAGE DESCRIPTION
ꢤ
ꢷ ꢷ ꢥ ꢥ ꢥ ꢤ
ꢗ . ꢋ
ꢎ . ꢙ
0 . ꢦ
0 . 0 0 0
0 . ꢦ
ꢎ . ꢙ
ꢗ . ꢋ
ꢴ ꢴ ꢴ ꢤ ꢗ ꢵ
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
23
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LTM8083
PACKAGE PHOTO
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
5V ≤ V ≤ 36V, 1.2V ≤ V
LTM8054
LTM8055
LTM8056
LTM8045
LTM8049
36V , 36V , 5.4A Buck-Boost µModule Regulator
≤ 36V, 11.25mm × 15mm × 3.42mm BGA
≤ 36V, 15mm × 15mm × 4.92mm BGA
≤ 48V, 15mm × 15mm × 4.92mm BGA
IN
OUT
IN
OUT
OUT
OUT
36V , 36V , 8.5A Buck-Boost µModule Regulator
5V ≤ V ≤ 36V, 1.2V ≤ V
IN
IN
OUT
58V , 48V , 5.5A Buck-Boost µModule Regulator
5V ≤ V ≤ 58V, 1.2V ≤ V
IN
IN
OUT
Single, Inverting or SEPIC µModule DC/DC Convertor
2.8V ≤ V ≤ 18V. 2.5V ≤ V
≤ 15V, 6.25mm × 11.25mm × 4.92mm BGA
≤ 25V, 9mm × 15mm × 2.42mm BGA
IN
OUT
OUT
Dual Outputs, SEPIC and/or Inverting µModule Regulator 2.6V ≤ V ≤ 20V. 2.5V ≤ V
IN
Rev. 0
10/20
www.analog.com
24
ANALOG DEVICES, INC. 2020
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