MLT04GPZ [ADI]
IC ANALOG MULTIPLIER OR DIVIDER, 8 MHz BAND WIDTH, PDIP18, PLASTIC, DIP-18, Analog Computational Function;
| 型号： | MLT04GPZ |
| 厂家： | 
ADI |
| 描述： | IC ANALOG MULTIPLIER OR DIVIDER, 8 MHz BAND WIDTH, PDIP18, PLASTIC, DIP-18, Analog Computational Function |
| 文件： | 总12页 (文件大小：431K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Four-Channel, Four-Quadrant
Analog Multiplier
a
MLT04
FUNCTIO NAL BLO CK D IAGRAM
18-Lead Epoxy D IP (P Suffix)
FEATURES
Four Independent Channels
Voltage IN, Voltage OUT
18-Lead Wide Body SO IC (S Suffix)
No External Parts Required
8 MHz Bandw idth
W4
1
2
18
17
W1
Four-Quadrant Multiplication
Voltage Output; W = (X × Y)/ 2.5 V
0.2% Typical Linearity Error on X or Y Inputs
Excellent Tem perature Stability: 0.005%
±2.5 V Analog Input Range
Operates from ±5 V Supplies
Low Pow er Dissipation: 150 m W typ
Spice Model Available
GND1
GND4
X4
X1
Y1
3
4
16
15
Y4
MLT04
5
V
14
13
V
CC
EE
Y2
X2
6
7
Y3
X3
12
APPLICATIONS
GND2
W2
8
9
11 GND3
W3
Geom etry Correction in High-Resolution CRT Displays
Waveform Modulation & Generation
Voltage Controlled Am plifiers
Autom atic Gain Control
10
W = (X • Y)/2.5V
Modulation and Dem odulation
GENERAL D ESCRIP TIO N
Fabricated in a complementary bipolar process, the MLT 04
includes four 4-quadrant multiplying cells which have been laser-
trimmed for accuracy. A precision internal bandgap reference
normalizes signal computation to a 0.4 scale factor. Drift over
temperature is under 0.005%/°C. Spot noise voltage of 0.3 µV/√Hz
results in a T HD + Noise performance of 0.02% (LPF = 22 kHz)
for the lower distortion Y channel. T he four 8 MHz channels
consume a total of 150 mW of quiescent power.
T he MLT 04 is a complete, four-channel, voltage output analog
multiplier packaged in an 18-pin DIP or SOIC-18. T hese complete
multipliers are ideal for general purpose applications such as voltage
controlled amplifiers, variable active filters, “zipper” noise free
audio level adjustment, and automatic gain control. Other applica-
tions include cost-effective multiple-channel power calculations
(I × V), polynomial correction generation, and low frequency
modulation. T he MLT 04 multiplier is ideally suited for generating
complex, high-order waveforms especially suitable for geometry
correction in high-resolution CRT display systems.
T he MLT 04 is available in 18-pin plastic DIP, and SOIC-18
surface mount packages. All parts are offered in the extended
industrial temperature range (–40°C to +85°C).
100
40
V
V
T
= +5V
= –5V
V
V
= +5V
= –5V
CC
EE
CC
EE
10
1
= +25°C
T
= +25°C
A
A
90
0
20
0
8.9MHz
–3dB
Av (X OR Y)
LPF = 500kHz
THDX: X = 2.5VP, Y = +2.5V DC
Ø (X OR Y)
–90
–20
–40
0.1
X & Y MEASUREMENTS
SUPERIMPOSED:
X = 100mV RMS, Y = 2.5V DC
Y = 100mV RMS, X = 2.5V DC
THDY: Y = 2.5VP, X = +2.5V DC
0.01
10
100
1k
10k
100k
1M
1k
10k
100k
1M
10M
100M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 1. Gain & Phase vs. Frequency Response
Figure 2. THD + Noise vs. Frequency
REV. B
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood. MA 02062-9106, U.S.A.
Tel: 617/ 329-4700 Fax: 617/ 326-8703
(V = +5 V, V = –5 V, V = ±2.5 V , R = 2 kΩ, T = +25°C unless otherwise noted.)
MLT04–SPECIFICATIONS
CC
EE
IN
P
L
A
P aram eter
Sym bol
Conditions
Min
Typ
Max
Units
MULTIPLIER PERFORMANCE1
Total Error2 X
EX
EY
–2.5 V < X < +2.5 V, Y = +2.5 V
–2.5 V < Y < +2.5 V, X = +2.5 V
–2.5 V < X < +2.5 V, Y = +2.5 V
–2.5 V < Y < +2.5 V, X = +2.5 V
X = –2.5 V, Y = 2.5 V, T A = –40°C to +85°C
Y = –2.5 V, X = 2.5 V, T A = –40°C to +85°C
X = ±2.5 V, Y = ±2.5 V, T A = –40°C to +85°C
X = 0 V, Y = 0 V, T A= –40°C to +85°C
X = 0 V, Y = 0 V, T A= –40°C to +85°C
X = 0 V, Y = ±2.5 V, T A = –40°C to +85°C
Y = 0 V, X = ±2.5 V, T A = –40°C to +85°C
–5
–5
–1
–1
±2
±2
5
5
+1
+1
% FS
% FS
% FS
% FS
%/°C
%/°C
1/V
mV
µV/°C
mV
Total Error2 Y
Linearity Error2 X
Linearity Error2 Y
Total Error Drift
LEX
LEY
TCEX
TCEY
K
ZOS
TCZOS
XOS
±0.2
±0.2
0.005
0.005
0.40
±10
50
Total Error Drift
Scale Factor3
0.38
–50
0.42
50
Output Offset Voltage
Output Offset Drift
Offset Voltage, X
Offset Voltage, Y
–50
–50
±10.5 50
±10.5 50
YOS
mV
DYNAMIC PERFORMANCE
Small Signal Bandwidth
Slew Rate
BW
SR
tS
FT AC
CT AC
VOUT = 0.1 V rms
VOUT = ±2.5 V
VOUT = ∆2.5 V to 1% Error Band
X = 0 V, Y = 1 V rms @ f = 100 kHz
X = Y = 1 V rms Applied to Adjacent Channel
8
53
1
–65
–90
MHz
V/µs
µs
dB
dB
30
Settling Time
AC Feedthrough
Crosstalk @ 100 kHz
OUTPUTS
Audio Band Noise
Wide Band Noise
Spot Noise Voltage
Total Harmonic Distortion
EN
EN
eN
THDX
THDY
ROUT
VPK
f = 10 Hz to 50 kHz
Noise BW = 1.9 MHz
f = 1 kHz
f = 1 kHz, LPF = 22 kHz, Y = 2.5 V
f = 1 kHz, LPF = 22 kHz, X = 2.5 V
76
µV rms
µV rms
µV/√Hz
%
%
Ω
380
0.3
0.1
0.02
40
Open Loop Output Resistance
Voltage Swing
Short Circuit Current
VCC = +5 V, VEE = –5 V
±3.0
±3.3
30
VP
mA
ISC
INPUTS
Analog Input Range
Bias Current
Resistance
IVR
IB
RIN
CIN
GND = 0 V
X = Y = 0 V
–2.5
+2.5
10
V
2.3
1
3
µA
MΩ
pF
Capacitance
SQUARE PERFORMANCE
Total Square Error
ESQ
X = Y = 1
5
% FS
POWER SUPPLIES
Positive Current
ICC
IEE
PDISS
PSSR
VRANGE
VCC = 5.25 V, VEE = –5.25 V
VCC = 5.25 V, VEE = –5.25 V
Calculated = 5 V × ICC + 5 V × IEE
X = Y = 0 V, VCC = ∆5% or VEE = ∆5%
For VCC & VEE
15
15
150
20
20
200
10
±5.25
mA
mA
mW
mV/V
V
Negative Current
Power Dissipation
Supply Sensitivity
Supply Voltage Range
±4.75
NOTES
1Specifications apply to all four multipliers.
2Error is measured as a percent of the ±2.5 V full scale, i.e., 1% FS = 25 mV.
3Scale Factor K is an internally set constant in the multiplier transfer equation W = K × X × Y.
Specifications subject to change without notice.
ABSO LUTE MAXIMUM RATINGS*
O RD ERING INFO RMATIO N*
Supply Voltages VCC, VEE to GND
Inputs XI, YI
Outputs WI
±7 V
VCC, VEE
VCC, VEE
Tem perature
Range
P ackage
D escription
P ackage
O ption
Model
Operating Temperature Range
Maximum Junction Temperature (T J max)
Storage Temperature
Lead Temperature (Soldering, 10 sec)
Package Power Dissipation
Thermal Resistance θJA
PDIP-18 (N-18)
–40°C to +85°C
+150°C
–65°C to +150°C
+300°C
MLT 04GP
MLT 04GS
MLT 04GS-REEL –40°C to +85°C
MLT 04GBC +25°C
–40°C to +85°C
–40°C to +85°C
18-Pin P-DIP N-18
18-Lead SOIC SOL-18
18-Lead SOIC SOL-18
Die
(TJ max–TA)/θJA
*For die specifications contact your local Analog sales office. The MLT04
contains 211 transistors.
74°C/W
89°C/W
SOIC-18 (SOL-18)
*Stresses above those listed under “Absolute Maximum Ratings” may cause perma-
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
section of this specification are not implied.
REV. B
–2–
MLT04
FUNCTIO NAL D ESCRIP TIO N
ANALO G MULTIP LIER ERRO R SO URCES
T he MLT 04 is a low cost quad, 4-quadrant analog multiplier with
single-ended voltage inputs and voltage outputs. T he functional
block diagram for each of the multipliers is illustrated in Figure 3.
Due to packaging constraints, access to internal nodes for externally
adjusting scale factor, output offset voltage, or additional summing
signals is not provided.
Multiplier errors consist primarily of input and output offsets, scale
factor errors, and nonlinearity in the multiplying core. An expres-
sion for the output of a real analog multiplier is given by:
VO = ( K + ∆K ){(VX + X OS )(V Y + Y OS ) + ZOS + f ( X , Y )}
where:
K
∆K
VX
XOS
VY
YOS
ZOS
ƒ(X, Y)
=
=
=
=
=
=
=
=
Multiplier Scale Factor
Scale Factor Error
X-Input Signal
X-Input Offset Voltage
Y-Input Signal
Y-Input Offset Voltage
Multiplier Output Offset Voltage
Nonlinearity
+V
S
MLT04
X1, X2, X3, X4
0.4
W1, W2, W3, W4
G1, G2, G3, G4
Y1, Y2, Y3, Y4
Executing the algebra to simplify the above expression yields
expressions for all the errors in an analog multiplier:
–V
S
Figure 3. Functional Block Diagram of Each MLT04
Multiplier
Ter m
D escr iption
D ependence on Input
KVXVY
T rue Product
Goes to Zero As Either or
Both Inputs Go to Zero
Each of the MLT 04’s analog multipliers is based on a Gilbert cell
multiplier configuration, a 1.23 V bandgap reference, and a unity-
connected output amplifier. Multiplier scale factor is determined
through a differential pair/trimmable resistor network external to
the core. An equivalent circuit for each of the multipliers is shown
in Figure 4.
∆KVYVY Scale-Factor Error
Goes to Zero at VX, VY = 0
Proportional to VX
VXYOS
VYXOS
XOSYOS
Linear “X” Feedthrough
Due to Y-Input Offset
Linear “Y” Feedthrough
Due to X-Input Offset
Proportional to VY
V
CC
Output Offset Due to X-, Independent of VX, VY
Y-Input Offsets
W
INTERNAL
BIAS
OUT
ZOS
Output Offset
Nonlinearity
Independent of VX, VY
ƒ(X, Y)
Depends on Both VX, VY.
Contains T erms Dependent
on VX, VY, T heir Powers
and Cross Products
22k
X
IN
22k
22k
SCALE
FACTOR
GND
Y
IN
200µA
200µA
200µA
200µA
200µA
200µA
V
EE
As shown in the table, the primary static errors in an analog
multiplier are input offset voltages, output offset voltage, scale
factor, and nonlinearity. Of the four sources of error, only two are
externally trimmable in the MLT 04: the X- and Y-input offset
voltages. Output offset voltage in the MLT 04 is factory-trimmed to
±50 mV, and the scale factor is internally adjusted to ±2.5% of full
scale. Input offset voltage errors can be eliminated by using the
optional trim circuit of Figure 6. T his scheme then reduces the net
error to output offset, scale-factor (gain) error, and an irreducible
nonlinearity component in the multiplying core.
Figure 4. Equivalent Circuit for the MLT04
Details of each multiplier’s output-stage amplifier are shown in
Figure 5. T he output stages idles at 200 µA, and the resistors in
series with the emitters of the output stage are 25 Ω. T he output
stage can drive load capacitances up to 500 pF without oscillation.
For loads greater than 500 pF, the outputs of the MLT 04 should
be isolated from the load capacitance with a 100 Ω resistor.
V
CC
+V
S
I
50kΩ
±100mV
50kΩ
FOR X , Y TRIM
OS OS
25Ω
W
CONNECT TO SUM
NODE OF AN EXT OP AMP
OUT
–V
25Ω
S
Figure 6. Optional Offset Voltage Trim Configuration
V
EE
Figure 5. Equivalent Circuit for MLT04 Output Stages
REV. B
–3–
MLT04
Feedthr ough
In the ideal case, the output of the multiplier should be zero if
either input is zero. In reality, some portion of the nonzero input
will “feedthrough” the multiplier and appear at the output. T his is
caused by the product of the nonzero input and the offset voltage of
the “zero” input. Introducing an offset equal to and opposite of the
“zero” input offset voltage will null the linear component of the
feedthrough. Residual feedthrough at the output of the multiplier
is then irreducible core nonlinearity.
100
90
X-INPUT: ±2.5V @ 10Hz
Y-INPUT: +2.5V
10
Y
T
NULLED
= +25°C
0%
OS
A
T ypical X- and Y-input feedthrough curves for the MLT 04 are
shown in Figures 7 and 8, respectively. T hese curves illustrate
MLT 04 feedthrough after “zero” input offset voltage trim.
Residual X-input feedthrough measures 0.08% of full scale,
whereas residual Y-input feedthrough is almost immeasurable.
HORIZONTAL – 0.5V/DIV
Figure 9. X-Input Nonlinearity @ Y = +2.5 V
X-INPUT: ±2.5V @ 10Hz
100
90
Y
NULLED
100
90
OS
T
= +25°C
A
X-INPUT: ±2.5V @ 10Hz
Y-INPUT: –2.5V
10
10
Y
T
NULLED
= +25°C
0%
0%
OS
A
HORIZONTAL – 0.5V/DIV
HORIZONTAL – 0.5V/DIV
Figure 10. X-Input Nonlinearity @ Y = –2.5 V
Figure 7. X-Input Feedthrough with YOS Nulled
Y-INPUT: ±2.5V @ 10Hz
X-INPUT: +2.5V
Y-INPUT: ±2.5V @ 10Hz
100
100
90
X
NULLED
OS
X
NULLED
90
OS
T
= +25°C
A
T
= +25°C
A
10
10
0%
0%
HORIZONTAL – 0.5V/DIV
HORIZONTAL – 0.5V/DIV
Figure 11. Y-Input Nonlinearity @ X = +2.5 V
Figure 8. Y-Input Feedthrough with XOS Nulled
Nonlinear ity
Y-INPUT: ±2.5V @ 10Hz
Multiplier core nonlinearity is the irreducible component of error.
It is the difference between actual performance and “best-straight-
line” theoretical output, for all pairs of input values. It is expressed
as a percentage of full scale with all other dc errors nulled. T ypical
X- and Y-input nonlinearities for the MLT 04 are shown in Figures
9 through 12. Worst-case X-input nonlinearity measured less than
0.2%, and Y-input nonlinearity measured better than 0.06%. For
modulator/demodulator or mixer applications it is, therefore,
recommended that the carrier be connected to the X-input while
the signal is applied to the Y-input.
X-INPUT: –2.5V
100
X
NULLED
= +25°C
90
OS
T
A
10
0%
HORIZONTAL – 0.5V/DIV
Figure 12. Y-Input Nonlinearity @ X = –2.5 V
–4–
REV. B
Typical Performance Characteristics – MLT04
12
9
180
135
90
T
V
= +25°C
= ±5V
A
S
V
V
= 100mV
= +2.5V
X
Y
6
3
45
NBW = 10Hz –50kHz
= +25°C
T
GAIN
100
90
A
0
0
–3
–45
PHASE
–6
–9
–90
PHASE = 68.3
@ 7.142 MHz
°
–135
10
0%
–12
–180
10k
100k
1M
10M
FREQUENCY – Hz
TIME = 10ms/DIV
Figure 13. Broadband Noise
Figure 16. X-Input Gain and Phase vs. Frequency
12
180
135
90
T
V
V
V
= +25°C
= ±5V
A
S
X
Y
9
6
= +2.5V
= 100mV
NBW = 1.9MHz
3
45
T
= +25°C
100
90
A
GAIN
0
0
–3
–45
PHASE
–6
–9
–90
10
–135
PHASE = 68.1
°
0%
@ 8.064 MHz
–12
–180
10k
100k
1M
10M
TIME = 10ms/DIV
FREQUENCY – Hz
Figure 14. Broadband Noise
Figure 17. Y-Input Gain and Phase vs. Frequency
8
6
10000
1000
100
0
C = 320pF
L
V
T
= ±5V
S
C = 560pF
L
= +25
°
C
4
A
C = 220pF
L
2
0
–2
NO C
L
C = 100pF
–4
L
–6
–8
V
= ±5V
= 2k
S
R
T
L
= +25°C
A
–10
–12
1k
10k
100k
1M
10M
100M
10
100
1k
10k
100k
1M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 15. Noise Density vs. Frequency
Figure 18. Am plitude Response vs. Capacitive Load
–5–
REV. B
MLT04 – Typical Performance Characteristics
0
ΩX-INPUT = +2.5V
V
T
= ±5V
S
R
= 10kΩ
L
100
90
= +25°C
A
–20
–40
T
= +25°C
A
V
V
= 0V
= 1V
X
Y
pk
10
–60
–80
0%
V
= 0V
= 1V
Y
X
V
pk
TIME – 100ns/DIV
–100
Figure 22. Y-Input Sm all-Signal Transient Response,
CL = 30 pF
1k
10k
100k
FREQUENCY – Hz
1M
3M
Figure 19. Feedthrough vs. Frequency
ΩX-INPUT = +2.5V
R
T
= 10kΩ
= +25°C
100
90
L
A
0
–20
–40
–60
T
= 25°C
= ±5V
A
V
V
S
= ±2.5V
X
pk
10
V
= +2.5VDC
Y
0%
TIME – 100ns/DIV
Figure 23. Y-Input Sm all-Signal Transient Response,
CL = 100 pF
–80
–100
–120
100
90
1k
10k
100k
FREQUENCY – Hz
1M
10M
Figure 20. Crosstalk vs. Frequency
ΩX-INPUT: +2.5V
10
R
= 10kΩ
0%
L
2.0
1.5
T
= +25°C
A
ΩV = ±5V
S
R
T
= 2kΩ
= +25°C
L
TIME = 100ns/DIV
1.0
A
Y = 100mV RMS
X = 2.5VDC
0.5
Figure 24. Y-Input Large-Signal Transient Re-
sponse, CL = 30 pF
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
X = 100mV RMS
Y = 2.5VDC
100
90
1k
10k
100k
1M
10M
100M
ΩX-INPUT: +2.5V
FREQUENCY – Hz
10
R
= 10kΩ
L
0%
T
= +25°C
A
Figure 21. Gain Flatness vs. Frequency
TIME = 100ns/DIV
Figure 25. Y-Input Large-Signal Transient Response,
CL = 100 pF
–6–
REV. B
MLT04
1
9
8
7
6
5
80
V
V
= ±5V
S
X
= +2.5V
X-INPUT
Y = +2.5VDC
V
= 100mV
Y
75
70
65
60
–3dB BW
0.1
ΩV = ±5V
S
R
T
= 2kΩ
= +25°C
L
0.01
0.001
A
PHASE @ –3dB BW
f
= 1kHz
O
FLPF = 22kHz
Y-INPUT
X = +2.5VDC
0.1
1
10
0
–75
–50
–25
25
50
75
100
125
INPUT SIGNAL LEVEL – Volts
TEMPERATURE –
°
C
P-P
Figure 26. THD + Noise vs. Input Signal Level
Figure 29. Y-Input Gain Bandwidth vs. Tem perature
8
7
0.3
≤V = +2.5V, –2.5V ≤ V ≤ +2.5V
X
Y
Y
V = ±5V
s
V
= +2.5V, –2.5V ≤ V ≤ +2.5V
X
0.2
0.1
6
1%
DISTORTION
5
0
–0.1
–0.2
–0.3
4
3
2
1
0
ΩT = +25°C
A
R
V
= 2kΩ
= ±5V
L
S
–75
–50
–25
25
50
75
100
125
1k
10k
100k
1M
10M
0
TEMPERATURE –
°
C
FREQUENCY – Hz
Figure 27. Linearity Error vs. Tem perature
Figure 30. Maxim um Output Swing vs. Frequency
80
75
70
65
60
9
4.5
4.0
V
V
= ±5V
= 100mV
S
X
V
= +2.5V
Y
POSITIVE SWING
3.5
3.0
8
7
6
5
–3dB BW
2.5
2.0
1.5
1.0
NEGATIVE SWING
PHASE @ –3dB BW
V
T
= ±5V
S
0.5
0
= +25°C
A
10
100
1k
10k
0
–75
–50
–25
25
50
75
100
125
ΩLOAD RESISTANCE – Ω
TEMPERATURE –
°C
Figure 28. X-Input Gain Bandwidth vs. Tem perature
Figure 31. Maxim um Output Swing vs. Resistive Load
–7–
REV. B
MLT04
0.407
0.406
300
250
200
150
V
= ±5V
T
V
= +25°C
= ±5V
S
SS = 1000 MULTIPLIERS
A
NO LOAD
S
X = ±2.5V
Y
@ X = ±2.5V
OS
0.405
X
@ Y = ±2.5V
OS
0.404
0.403
100
50
0
0.402
–75
–50
–25
0
25
50
75
100
125
–12.5 –10 –7.5 –5 –2.5
0
2.5
5
7.5
10 12.5
TEMPERATURE –
°
C
OFFSET VOLTAGE – mV
Figure 35. Scale Factor vs. Tem perature
Figure 32. Offset Voltage Distribution
400
6
4
T
= +25°C
= ±5V
A
V
= ±5V
S
SS = 1000
MULTIPLIERS
350
300
V
S
X
V
= V = 0V
Y
X
, Y = ±2.5V
OS
2
0
250
200
150
100
–2
–4
–6
Y
, X = ±2.5V
OS
50
0
–15 –12
–9
–6
–3
0
3
6
9
12
15
–75
–50
–25
0
25
50
75
100
125
TEMPERATURE –
°C
OUTPUT OFFSET VOLTAGE – mV
Figure 33. Offset Voltage vs. Tem perature
Figure 36. Output Offset Voltage (ZOS) Distribution
400
10
SS = 1000 MULTIPLIERS
T
= +25°C
= ±5V
V
= ±5V
A
350
300
250
200
s
V
S
5
0
150
100
–5
50
0
–10
–75
–50
–25
0
25
50
75
100
125
0.395 0.3975 0.400 0.4025 0.405 0.4075 0.410 0.4125 0.415
SCALE FACTOR – 1/V
TEMPERATURE –
°C
Figure 34. Scale Factor Distribution
Figure 37. Output Offset Voltage (ZOS) vs. Tem perature
–8–
REV.B
MLT04
17
16
15
15
12
V
= ±5V
S
NO LOAD
V
σX +3σ
= V = 0
Y
X
9
6
3
0
X
–3
–6
14
13
–9
σX –3σ
–12
–15
0
200
400
600
800
1000
–75
–50
–25
0
25
50
75
100
125
TEMPERATURE –
°C
HOURS OF OPERATION AT +125°C
Figure 38. Supply Current vs. Tem perature
Figure 41. Output Voltage Offset (ZOS) Distribution
Accelerated by Burn-in
0.424
0.420
0.416
100
80
T
= +25°C
= ±5V
A
V
S
σX +3σ
0.412
+PSRR
0.408
60
X
0.404
–PSRR
0.400
40
20
0.396
σX –3σ
0.392
0.388
0.384
0
0
200
400
600
800
1000
100
1k
10k
FREQUENCY – Hz
100k
1M
HOURS OF OPERATION AT +125
°
C
Figure 39. Power Supply Rejection vs. Frequency
Figure 42. Scale Factor (K) Distribution Acceler-
ated by Burn-in
1.25
1.0
σX +3σ
0.75
0.50
0.25
X
0
–0.25
–0.50
–0.75
σX –3σ
–1.0
–1.25
0
200
400
600
800
1000
HOURS OF OPERATION AT +125
°
C
Figure 40. Linearity Error (LE) Distribution Accelerated
by Burn-in
REV. B
–9–
MLT04
AP P LICATIO NS
T he equation shows a dc term at the output which will vary
strongly with the amplitude of the input, VIN. T he output dc offset
can be eliminated by capacitively coupling the MLT 04’s output
with a high-pass filter. For optimal spectral performance, the
filter’s cutoff frequency should be chosen to eliminate the input
fundamental frequency.
T he MLT 04 is well suited for such applications as modulation/
demodulation, automatic gain control, power measurement, analog
computation, voltage-controlled amplifiers, frequency doublers,
and geometry correction in CRT displays.
Multiplier Connections
A source of error in this configuration is the offset voltages of the X
and Y inputs. T he input offset voltages produce cross products
with the input signal to distort the output waveform. T o circum-
vent this problem, Figure 45 illustrates the use of inverting
amplifiers configured with an OP285 to provide a means by which
the X- and Y-input offsets can be trimmed.
Figure 43 llustrates the basic connections for multiplication. Each
of the four independent multipliers has single-ended voltage inputs
(X, Y) and a low impedance voltage output (W). Also, each
multiplier has its own dedicated ground connection (GND) which
is connected to the circuit’s analog common. For best perfor-
mance, circuit layout should be compact with short component
leads and well-bypassed supply voltage feeds. In applications where
fewer than four multipliers are used, all unused analog inputs must
be returned to the analog common.
ΩP1
50kΩ
+5V
–5V
X
TRIM
OS
R2
ΩR5
500kΩ
10k
1
W4
R1
W1
W1
18
GND4 17
X4
W4
1/4 MLT04
+
3
2
10k
2
GND1
1
2
3
A1
C1
3
+
100pF
W1
X1
Y1
X1
Y1
16
X4
Y4
0.4
1
V
V
O
IN
A1, A2 = 1/2 OP285
ΩR
L
4
5
Y4 15
10kΩ
MLT04
+
A2
5
V
14
EE
V
7
+
–5V
+5V
4
CC
6
R3
10k
Y2
X2
0.1µF
Y2
X2
0.1µF
6
7
Y3 13
X3 12
Y3
X3
R4
10k
ΩR6
500kΩ
Y
TRIM
OS
GND2
W2
GND3
8
9
11
+5V
–5V
ΩP2
50kΩ
W2
W3 10
W3
W
= 0.4 (X1–4 • Y
)
1–4
1–4
Figure 45. Frequency Doubler with Input Offset Voltage
Trim s
Figure 43. Basic Multiplier Connections
Feedback D ivider Connections
T he most commonly used analog divider circuit is the “inverted
multiplier” configuration. As illustrated in Figure 46, an “inverted
multiplier” analog divider can be configured with a multiplier
operating in the feedback loop of an operational amplifier. T he
general form of the transfer function for this circuit configuration is
given by:
Squar ing and Fr equency D oubling
As shown in Figure 44, squaring of an input signal, VIN, is achieved
by connecting the X-and Y-inputs in parallel to produce an output
of VIN2/2.5 V. T he input may have either polarity, but the output
will be positive.
+5V
0.1µF
R2
R1
V
IN
V
= −2. 5 V ×
×
O
V
X
X
1/4 MLT04
+
+
V
IN
Here, the multiplier operates as a voltage-controlled potentiometer
that adjusts the loop gain of the op amp relative to a control signal,
VX. As the control signal to the multiplier decreases, the output of
the multiplier decreases as well. T his has the effect of reducing
negative feedback which, in turn, decreases the amplifier’s loop
gain. T he result is higher closed-loop gain and reduced circuit
bandwidth. As VX is increased, the output of the multiplier
increases which generates more negative feedback — closed-loop
gain drops and circuit bandwidth increases. An example of an
“inverted multiplier” analog divider frequency response is shown in
Figure 47.
W
GND
Y
0.4
2
W = 0.4 V
IN
0.1µF
–5V
Figure 44. Connections for Squaring
When the input is a sine wave given by VIN sin ωt, the squaring
circuit behaves as a frequency doubler because of the trigonometric
identity:
(V sin ωt )2
V
1
2
2
IN
IN
=
(1 − cos 2 ωt )
2.5V
2.5V
–10–
REV. B
MLT04
X1
X1
1/4 MLT04
1/4 MLT04
3
2
3
2
+
+
V
X
D1
1N4148
W1
W1
GND1
Y1
1
1
0.4
0.4
R2
10k
R2
10k
Y1
+
4
4
R1
10k
R1
10k
V
2
V
2
IN
IN
6
6
OP113
OP113
V
V
O
O
3
3
+
+
VIN
VX
VO
=
–2.5V • VIN
VO = –2.5V •
Figure 46. “Inverted-Multiplier” Configuration for
Analog Division
Voltage-Contr olled Low-P ass Filter
T he circuit in Figure 49 illustrates how to construct a voltage-
controlled low-pass filter with an analog multiplier. T he advantage
with this approach over conventional active-filter configurations is
that the overall characteristic cut-off frequency, ωO, will be directly
proportional to a multiplying input voltage. T his permits the
construction of filters in which the capacitors are adjustable
(directly or inversely) by a control voltage. Hence, the frequency
scale of a filter can be manipulated by means of a single voltage
without affecting any other parameters. T he general form of the
circuit’s transfer function is given by:
90
80
70
60
50
40
30
20
10
0
A
VOL
OP113
V
= 0.025V
X
V
= 0.25V
X
V
R2
R1
1
O
= −
V
= 2.5V
1k
X
V
R2 + R1 2. 5RC
IN
s
+ 1
R1
V
X
100
10k
100k
1M
10M
FREQUENCY – Hz
In this circuit, the ratio of R2 to R1 sets the passband gain, and the
break frequency of the filter, ωLP, is given by:
Figure 47. Signal-Dependent Feedback Makes Variables
Out of Am plifier Bandwidth and Stability
R1
V
X
ωLP
=
R1 + R2 2. 5RC
Although this technique works well with almost any operational
amplifier, there is one caveat: for best circuit stability, the unity-
gain crossover frequency of the operational amplifier should be
equal to or less than the MLT 04’s 8 MHz bandwidth.
X1
1/4 MLT04
3
2
+
+
Connection for Squar e Rooting
V
X
C
80pF
R
10k
Another application of the “inverted multiplier” configuration is the
square-root function. As shown in Figure 48, both inputs of the
MLT 04 are wired together and are used as the output of the
circuit. Because the circuit configuration exhibits the following
generalized transfer function:
W1
GND1
1
0.4
2
3
1
V
A1
+
O
+
R1
10k
4
R2
A1 = 1/2 OP285
Y1
10k
R2
VO
=
−2.5 ×
×V
IN
V
IN
R1
VO
1
= –
5RC
VX
VIN
the input signal voltage is limited to the range –2.5 V ≤ VIN < 0. T o
prevent circuit latchup due to positive feedback or input signal
polarity reversal, a 1N4148-type junction diode is used in series
with the output of the multiplier.
1 + S
VX
fLP
=
; fLP = MAX @ VX = 2.5V
π10πRC
Figure 49. A Voltage-Controlled Low-Pass Filter
For example, if R1 = R2 = 10 kΩ , R = 10 kΩ , and C = 80 pF,
Figure 48. Connections for Square Rooting
REV. B
–11–
MLT04
then the output of the circuit has a pole at frequencies from 1 kHz
to 100 kHz for VX ranging from 25 mV to 2.5 V. T he performance
of this low-pass filter is illustrated in Figure 20.
O UTLINE D IMENSIO NS
Dimensions shown in inches and (mm).
18-Lead Epoxy D IP (P Suffix)
30
20
10
18
10
0.280 (7.11)
PIN 1
0.240 (6.10)
9
1
0.325 (8.25)
0.300 (7.62)
0.925 (23.49)
0.845 (21.47)
0.015
(0.38)
MIN
0.210
(5.33)
MAX
0
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
15°
0°
0.25V
V
= 0.025V
2.5V
– 10
0.015 (0.38)
0.008 (0.20)
X
SEATING
PLANE
0.100
(2.54)
BSC
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
– 20
– 30
10
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
18-Lead Wide-Body SO L (S Suffix)
Figure 50. Low-Pass Cutoff Frequency vs. Control
Voltage, VX
18
10
With this approach, it is possible to construct parametric biquad
filters whose parameters (center frequency, passband gain, and Q)
can be adjusted with dc control voltages.
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
0.3937 (10.00)
PIN 1
9
1
0.1043 (2.65)
0.0926 (2.35)
0.4625 (11.75)
0.4469 (11.35)
0.0291 (0.74)
0.0098 (0.25)
x 45°
0.0500 (1.27)
0.0157 (0.40)
8
0
°
°
0.0118 (0.30)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.0500 (1.27)
BSC
0.0125 (0.32)
0.0091 (0.23)
–12–
REV. B
相关型号：
MLT04GSZ
IC ANALOG MULTIPLIER OR DIVIDER, 8 MHz BAND WIDTH, PDSO18, SOIC-18, Analog Computational Function
ADI
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