OP113FS [ADI]
Low Noise, Low Drift Single-Supply Operational Amplifiers; 低噪声，低漂移，单电源运算放大器
| 型号： | OP113FS |
| 厂家： | 
ADI |
| 描述： | Low Noise, Low Drift Single-Supply Operational Amplifiers |
| 文件： | 总16页 (文件大小：331K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Noise, Low Drift
a
Single-Supply Operational Amplifiers
OP113/OP213/OP413
P IN CO NNECTIO NS
FEATURES
Single- or Dual-Supply Operation
Low Noise: 4.7 nV/ √Hz @ 1 kHz
Wide Bandw idth: 3.4 MHz
Low Offset Voltage: 100 V
Very Low Drift: 0.2 V/ ؇C
Unity Gain Stable
8-Lead Nar r ow-Body SO
8-Lead P lastic D IP
NULL
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
NC
1
NULL
–IN A
+IN A
V–
8
NC
V+
OP113
V+
OUT A
NULL
No Phase Reversal
OUT A
NULL
5
4
NC = NO CONNECT
APPLICATIONS
Digital Scales
OP113
NC = NO CONNECT
Multim edia
Strain Gages
Battery Pow ered Instrum entation
Tem perature Transducer Am plifier
8-Lead P lastic D IP
8-Lead Nar r ow-Body SO
OUT A
1
2
3
4
8
7
6
5
V+
OUT A
–IN A
+IN A
V–
1
8
V+
OUT B
–IN B
+IN B
OP213
–IN A
+IN A
V–
OUT B
–IN B
+IN B
GENERAL D ESCRIP TIO N
5
4
T he OP113 family of single supply operational amplifiers fea-
tures both low noise and drift. It has been designed for sys-
tems with internal calibration. Often these processor-based
systems are capable of calibrating corrections for offset and
gain, but they cannot correct for temperature drifts and noise.
Optimized for these parameters, the OP113 family can be used
to take advantage of superior analog performance combined
with digital correction. Many systems using internal calibration
operate from unipolar supplies, usually either +5 volts or +12
volts. T he OP113 family is designed to operate from single
supplies from +4 volts to +36 volts, and to maintain its low
noise and precision performance.
OP213
14-Lead P lastic D IP
16-Lead Wide-Body SO
1
16
OUT A
–IN A
+IN A
V+
OUT D
–IN D
+IN D
OUT A
–IN A
+IN A
V+
1
2
3
4
OUT D
–IN D
14
13
V–
12 +IN D
OP413
+IN C
+IN B
–IN B
OUT B
NC
OP413
V–
11
10
9
–IN C
T he OP113 family is unity gain stable and has a typical gain
bandwidth product of 3.4 MHz. Slew rate is in excess of 1 V/µs.
Noise density is a very low 4.7 nV/√Hz, and noise in the 0.1 Hz
to 10 Hz band is 120 nV p-p. Input offset voltage is guaranteed
and offset drift is guaranteed to be less than 0.8 µV/°C. Input
common-mode range includes the negative supply and to within
1 volt of the positive supply over the full supply range. Phase
reversal protection is designed into the OP113 family for cases
where input voltage range is exceeded. Output voltage swings
also include the negative supply and go to within 1 volt of the
positive rail. T he output is capable of sinking and sourcing
current throughout its range and is specified with 600 Ω loads.
+IN B
–IN B
OUT B
+IN C
–IN C
OUT C
5
6
OUT C
NC
8
9
NC = NO CONNECT
7
8
D/A sigma-delta converters. Often these converters have high
resolutions requiring the lowest noise amplifier to utilize their
full potential. Many of these converters operate in either single
supply or low supply voltage systems, and attaining the greater
signal swing possible increases system performance.
T he OP113 family is specified for single +5 volt and dual ±15
volt operation over the XIND—extended industrial (–40°C to
+85°C) temperature range. T hey are available in plastic and
SOIC surface mount packages.
Digital scales and other strain gage applications benefit from the
very low noise and low drift of the OP113 family. Other appli-
cations include use as a buffer or amplifier for both A/D and
REV. C
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 781/ 329-4700
Fax: 781/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1998
OP113/OP213/OP413–SPECIFICATIONS
(@ V = ؎15.0 V, T = +25؇C unless otherwise noted)
S
A
ELECTRICAL CHARACTERISTICS
“ E” Grade
Typ
“ F” Grade
P aram eter
Sym bol
Conditions
Min
Max
Min
Typ
Max
Units
INPUT CHARACT ERIST ICS
Offset Voltage
VOS
OP113
–40°C ≤ T A
OP213
–40°C ≤ T A
OP413
–40°C ≤ T A
VCM = 0 V,
–40°C ≤ T A
VCM = 0 V
–40°C ≤ T A
75
150
225
250
325
275
350
600
700
µV
µV
µV
µV
µV
µV
nA
nA
≤
≤
≤
≤
≤
+85°C
+85°C
+85°C
+85°C
+85°C
125
100
150
125
175
600
700
Input Bias Current
Input Offset Current
IB
240
IOS
50
+14
50
+14
nA
V
dB
Input Voltage Range
Common-Mode Rejection
VCM
CMR
–15
100
–15
96
–15 V ≤ VCM ≤ +14 V
–15 V ≤ VCM ≤ +14 V,
–40°C ≤ T A
OP113, OP213, RL = 600 Ω,
–40°C ≤ T A +85°C
OP413, RL = 1 kΩ,
–40°C ≤ T A
RL = 2 kΩ,
–40°C ≤ T A
Note 1
116
116
2.4
2.4
8
≤
+85°C
97
1
94
1
dB
Large Signal Voltage Gain
AVO
≤
V/µV
V/µV
≤
+85°C
1
1
≤
+85°C
2
2
V/µV
µV
µV/°C
Long-T erm Offset Voltage1
Offset Voltage Drift
VOS
∆VOS/∆T
150
0.8
300
1.5
Note 2
0.2
O
UT PUT CHARACT ERIST ICS
Output Voltage Swing High
VOH
RL = 2 kΩ
RL = 2 kΩ,
–40°C ≤ T A
RL = 2 kΩ
RL = 2 kΩ,
–40°C ≤ TA
+14
+14
V
≤
+85°C
+13.9
+13.9
V
V
Output Voltage Swing Low
Short Circuit Limit
VOL
–14.5
–14.5
–14.5
–14.5
≤
+85°C
V
mA
ISC
±40
±40
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
VS = ±2 V to ±18 V
VS = ±2 V to ±18 V
103
100
120
120
100
97
dB
dB
–40°C ≤ T A
≤ +85°C
Supply Current/Amplifier
ISY
VOUT = 0 V, RL = ∞,
VS = ±18 V
3
3.8
±18
3
3.8
±18
mA
mA
V
–40°C ≤ T A
≤
+85°C
Supply Voltage Range
VS
+4
+4
AUDIO PERFORMANCE
T HD + Noise
VIN = 3 V rms, RL = 2 kΩ
f = 1 kHz,
0.0009
9
4.7
0.4
120
0.0009
9
4.7
0.4
120
%
Voltage Noise Density
en
f = 10 Hz
f = 1 kHz
f = 1 kHz
0.1 Hz to 10 Hz
nV/√Hz
nV/√Hz
pA/√Hz
nV p-p
Current Noise Density
Voltage Noise
in
en p-p
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Channel Separation
SR
GBP
RL = 2 kΩ
0.8
1.2
3.4
0.8
1.2
3.4
V/µs
MHz
VOUT = 10 V p-p
RL = 2 kΩ, f = 1 kHz
to 0.01%, 0 V to 10 V Step
105
9
105
9
dB
µs
Settling T ime
NOT ES
tS
1Long-term offset voltage is guaranteed by a 1000-hour life test performed on three independent lots at 125 °C, with an LT PD of 1.3.
2Guaranteed specifications, based on characterization data.
Specifications subject to change without notice.
–2–
REV. C
OP113/OP213/OP413
(@ V = +5.0 V, T = +25؇C unless otherwise noted)
ELECTRICAL CHARACTERISTICS
S
A
“ E” Grade
Typ
“ F” Grade
P aram eter
Sym bol
Conditions
Min
Max
Min Typ
Max
Units
INPUT CHARACT ERIST ICS
Offset Voltage
VOS
OP113
–40°C ≤ T A
OP213
–40°C ≤ T A
OP413
–40°C ≤ T A
VCM = 0 V, VOUT = 2
–40°C ≤ T A +85°C
VCM = 0 V, VOUT = 2
–40°C ≤ T A +85°C
125
175
150
225
175
250
650
750
175
250
300
375
325
400
650
750
µV
µV
µV
µV
µV
µV
nA
nA
≤
≤
≤
+85°C
+85°C
+85°C
Input Bias Current
Input Offset Current
IB
300
106
≤
IOS
≤
50
+4
50
+4
nA
V
dB
Input Voltage Range
Common-Mode Rejection
VCM
CMR
0
93
0 V ≤ VCM ≤ 4 V
0 V ≤ VCM ≤ 4 V,
–40°C ≤ T A
OP113, OP213, RL = 600 Ω, 2 kΩ
0.01 V ≤ VOUT 3.9 V
OP413, RL = 600, 2 kΩ,
90
87
2
≤
+85°C
90
2
dB
Large Signal Voltage Gain
AVO
≤
V/µV
0.01 V ≤ VOUT
Note 1
Note 2
≤
3.9 V
1
1
V/µV
µV
µV/°C
Long-T erm Offset Voltage1
Offset Voltage Drift
VOS
∆VOS/∆T
200
1.0
350
1.5
0.2
O
UT PUT CHARACT ERIST ICS
Output Voltage Swing High
VOH
RL = 600 kΩ
RL = 100 kΩ, –40°C ≤ T A ≤ +85°C
RL = 600 Ω, –40°C ≤ TA ≤ +85°C
4.0
4.1
3.9
4.0
4.1
3.9
V
V
V
Output Voltage Swing Low
Short Circuit Limit
VOL
ISC
RL = 600 Ω, –40°C ≤ TA
RL = 100 kΩ, –40°C ≤ TA
≤
+85°C
8
8
8
8
mV
mV
mA
≤ +85°C
±30
±30
POWER SUPPLY
Supply Current
Supply Current
ISY
ISY
VOUT = 2.0 V, No Load
1.6
2.7
3.0
2.7
3.0
mA
mA
–40°C ≤ T A
≤ +85°C
AUDIO PERFORMANCE
T HD + Noise
Voltage Noise Density
VOUT = 0 dBu, f = 1 kHz
f = 10 Hz
f = 1 kHz
f = 1 kHz
0.1 Hz to 10 Hz
0.001
9
4.7
0.45
120
0.001
9
4.7
0.45
120
%
en
nV/√Hz
nV/√Hz
pA/√Hz
nV p-p
Current Noise Density
Voltage Noise
in
en p-p
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Settling T ime
SR
GBP
tS
RL = 2 kΩ
0.6
0.9
3.5
5.8
0.6
V/µs
MHz
µs
3.5
5.8
to 0.01%, 2 V Step
NOT ES
1Long-term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at 125 °C, with an LT PD of 1.3.
2Guaranteed specifications, based on characterization data.
Specifications subject to change without notice.
REV. C
–3–
OP113/OP213/OP413
ABSO LUTE MAXIMUM RATINGS1
O RD ERING GUID E
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . ±10 V
Output Short-Circuit Duration to GND . . . . . . . . . . Indefinite
Storage T emperature Range
Tem perature
Range
P ackage
D escription
P ackage
O ptions
Model
OP113EP
OP113ES
OP113FP
OP113FS
–40°C to +85°C 8-Lead Plastic DIP N-8
–40°C to +85°C 8-Lead SOIC
–40°C to +85°C 8-Lead Plastic DIP N-8
–40°C to +85°C 8-Lead SOIC
SO-8
P, S Package . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating T emperature Range
SO-8
OP113/OP213/OP413E, F . . . . . . . . . . . . . . –40°C to +85°C
Junction T emperature Range
P, S Package . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead T emperature Range (Soldering, 60 sec) . . . . . . . +300°C
OP213EP
OP213ES
OP213FP
OP213FS
–40°C to +85°C 8-Lead Plastic DIP N-8
–40°C to +85°C 8-Lead SOIC
SO-8
–40°C to +85°C 8-Lead Plastic DIP N-8
–40°C to +85°C 8-Lead SOIC
SO-8
2
OP413EP
OP413ES
OP413FP
OP413FS
–40°C to +85°C 14-Lead Plastic DIP N-14
–40°C to +85°C 16-Lead Wide SOIC R-16
–40°C to +85°C 14-Lead Plastic DIP N-14
–40°C to +85°C 16-Lead Wide SOIC R-16
P ackage Type
Units
JA
JC
8-Lead Plastic DIP (P)
8-Lead SOIC (S)
14-Lead Plastic DIP (P)
16-Lead SOIC (S)
103
158
83
43
43
39
27
°C/W
°C/W
°C/W
°C/W
92
NOT ES
1Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2θJA is specified for the worst case conditions, i.e., θJA is specified for device in socket
for cerdip, P-DIP, and LCC packages; θJA is specified for device soldered in circuit
board for SOIC package.
REV. C
–4–
OP113/OP213/OP413
AP P LICATIO NS
2 mV trim range may be somewhat excessive. Reducing the
trimming potentiometer to a 2 kΩ value will give a more reason-
able range of ±400 µV.
T he OP113, OP213 and OP413 form a new family of high
performance amplifiers that feature precision performance in
standard dual supply configurations and, more importantly,
maintain precision performance when a single power supply is
used. In addition to accurate dc specifications, it is the lowest
+15V
–15V
2
16
R5
1k⍀
+10.000V
8
14
15
8
1
3
9
3
2
noise single supply amplifier available with only 4.7 nV/
typical noise density.
√Hz
1
2N2219A
A2
AD588BD
6
11 12 13
1/2
OP213
Single supply applications have special requirements due to the
generally reduced dynamic range of the output signal. Single
supply applications are often operated at voltages of +5 volts or
+12 volts, compared to dual supply applications with supplies of
±12 volts or ±15 volts. T his results in reduced output swings.
Where a dual supply application may often have 20 volts of
signal output swing, single supply applications are limited to, at
most, the supply range and, more commonly, several volts be-
low the supply. In order to attain the greatest swing the single
supply output stage must swing closer to the supply rails than in
dual supply applications.
10
4
7
+10.000V
10F
R3
R4
500⍀
17.2k⍀
0.1%
350⍀
LOAD
CELL
CMRR TRIM
10-TURN
T.C. LESS THAN 50ppm/؇C
6
100mV
F.S.
A1
5
7
OUTPUT
0
10V
4
1/2
OP213
F.S.
–15V
R1
R2
17.2k⍀ 301⍀
0.1% 0.1%
T he OP113 family has a new patented output stage that allows
the output to swing closer to ground, or the negative supply,
than previous bipolar output stages. Previous op amps had
outputs that could swing to within about ten millivolts of the
negative supply in single supply applications. However, the
OP113 family combines both a bipolar and a CMOS device in
the output stage, enabling it to swing to within a few hundred
microvolts of ground.
Figure 1. Precision Load Cell Scale Am plifier
AP P LICATIO N CIRCUITS
A H igh P r ecision Industr ial Load-Cell Scale Am plifier
T he OP113 family makes an excellent amplifier for conditioning
a load-cell bridge. Its low noise greatly improves the signal reso-
lution, allowing the load cell to operate with a smaller output
range, thus reducing its nonlinearity. Figure 1 shows one half of
the OP113 family used to generate a very stable 10.000 V bridge
excitation voltage while the second amplifier provides a differen-
tial gain. R4 should be trimmed for maximum common-mode
rejection.
When operating with reduced supply voltages, the input range is
also reduced. T his reduction in signal range results in reduced
signal-to-noise ratio, for any given amplifier. T here are only two
ways to improve this: increase the signal range or reduce the
noise. T he OP113 family addresses both of these parameters.
Input signal range is from the negative supply to within one
volt of the positive supply over the full supply range. Com-
petitive parts have input ranges that are a half a volt to five
volts less than this. Noise has also been optimized in the OP113
family. At 4.7 nV/√Hz, it is less than one fourth that of competi-
tive devices.
A Low Voltage Single Supply, Str ain-Gage Am plifier
T he true zero swing capability of the OP113 family allows the
amplifier in Figure 2 to amplify the strain-gage bridge accurately
even with no signal input while being powered by a single +5
volt supply. A stable 4.000 V bridge voltage is made possible by
the rail-to-rail OP295 amplifier, whose output can swing to
within a millivolt of either rail. T his high voltage swing greatly
increases the bridge output signal without a corresponding in-
crease in bridge input.
P hase Rever sal
T he OP113 family is protected against phase reversal as long as
both of the inputs are within the supply ranges. However, if there
is a possibility of either input going below the negative supply
(or ground in the single supply case), the inputs should be pro-
tected with a series resistor to limit input current to 2 mA.
+5V
2
IN
2.500V
8
6
REF43
3
2
OUT
1/2
OP295
4
O P 113 O ffset Adjust
2N2222A
1
GND
4
T he OP113 has the facility for external offset adjustment, using
the industry standard arrangement. Pins 1 and 5 are used in
conjunction with a potentiometer of 10 kΩ total resistance,
connected with the wiper to V– (or ground in single supply
applications). T he total adjustment range is about ±2 mV using
this configuration.
4.000V
+5V
8
350⍀
35mV
F.S.
R8
12.0k⍀
R7
20.0k⍀
OUTPUT
0V 3.5V
5
1/2
7
OP295
6
4
Adjusting the offset to zero has minimal effect on offset
drift (assuming the potentiometer has a tempco of less than
1000 ppm/°C). Adjustment away from zero, however, (like all
bipolar amplifiers) will result in a T CVOS of approximately
3.3 µV/°C for every millivolt of induced offset.
R3
20k⍀
3
2
1/2
OP213
1
R4
100k⍀
R2
20k⍀
R1
100k⍀
R5
2.10k⍀
R6
27.4⍀
It is therefore not generally recommended that this trim be used
to compensate for system errors originating outside of the
OP113. T he initial offset of the OP113 is low enough that
external trimming is almost never required but, if necessary, the
R
= 2,127.4⍀
G
Figure 2. Single Supply Strain-Gage Am plifier
REV. C
–5–
OP113/OP213/OP413
A H igh Accur acy Linear ized RTD Ther m om eter Am plifier
Zero suppressing the bridge facilitates simple linearization of the
RT D by feeding back a small amount of the output signal to the
RT D (Resistor T emperature Device). In Figure 3 the left leg of
the bridge is servoed to a virtual ground voltage by amplifier
A1, while the right leg of the bridge is also servoed to zero-volt
by amplifier A2. T his eliminates any error resulting from
common-mode voltage change in the amplifier. A three-wire
RT D is used to balance the wire resistance on both legs of the
bridge, thereby reducing temperature mismatch errors. T he
5.000 V bridge excitation is derived from the extremely stable
AD588 reference device with 1.5 ppm/°C drift performance.
A H igh Accur acy Ther m ocouple Am plifier
Figure 4 shows a popular K-type thermocouple amplifier with
cold-junction compensation. Operating from a single +12 volt
supply, the OP113 family’s low noise allows temperature mea-
surement to better than 0.02°C resolution from 0°C to 1000°C
range. T he cold-junction error is corrected by using an inexpen-
sive silicon diode as a temperature measuring device. It should
be placed as close to the two terminating junctions as physically
possible. An aluminum block might serve well as an isothermal
system.
+5.000V
2
REF02EZ
4
6
+12V
Linearization of the RT D is done by feeding a fraction of the
output voltage back to the RT D in the form of a current. With
just the right amount of positive feedback, the amplifier output
will be linearly proportional to the temperature of the RT D.
R9
0.1F
124k⍀
R1
R5
10.7k⍀ 40.2k⍀
+12V
1N4148
D1
10F
+
0.1F
R8
453⍀
R2
2.74k⍀
–15V +15V
–
–
+
8
2
K-TYPE
THERMOCOUPLE
40.7V/؇C
2
16
1/2
1
+
OP213
11
12
13
R6
0V TO 10.00V
(0؇C TO 1000؇C)
3
14
15
4
200⍀
R4
5.62k⍀
R3
53.6⍀
AD588BD
4
6
1
3
R3
50⍀
R
FULL SCALE ADJUST
G
R2
R5
R7
8
10
7
9
8.25k⍀
4.02k⍀
100⍀
Figure 4. Accurate K-Type Therm ocouple Am plifier
R1
8.25k⍀
10F
R6 should be adjusted for a zero-volt output with the thermo-
couple measuring tip immersed in a zero-degree ice bath. When
calibrating, be sure to adjust R6 initially to cause the output to
swing in the positive direction first. T hen back off in the nega-
tive direction until the output just stops changing.
+15V
R
W1
8
6
5
R4
100⍀
A2
7
V
(10mV/؇C)
100⍀
RTD
OUT
–1.50V = –150؇C
+5.00V = +500؇C
4
1/2
R
R
W2
OP213
–15V
R9
An Ultr alow Noise, Single Supply Instr um entation Am plifier
Extremely low noise instrumentation amplifiers can be built
using the OP113 family. Such an amplifier that operates off a
single supply is shown in Figure 5. Resistors R1–R5 should be
of high precision and low drift type to maximize CMRR perfor-
mance. Although the two inputs are capable of operating to zero
volt, the gain of –100 configuration will limit the amplifier input
common mode to not less than 0.33 V.
W3
5k⍀
R8
49.9k⍀
LINEARITY
ADJUST
@1/2 F.S.
2
3
A1
1
1/2
OP213
Figure 3. Ultraprecision RTD Am plifier
+5V TO +36V
T o calibrate the circuit, first immerse the RT D in a zero-degree
ice bath or substitute an exact 100 Ω resistor in place of the
RT D. Adjust the ZERO ADJUST potentiometer for a 0.000 V
output, then set R9 LINEARIT Y ADJUST potentiometer to
the middle of its adjustment range. Substitute a 280.9 Ω resistor
(equivalent to 500°C) in place of the RT D, and adjust the
FULL-SCALE ADJUST potentiometer for a full-scale voltage
of 5.000 V.
+
1/2
OP213
V
V
IN
OUT
–
1/2
OP213
*R1
10k⍀
*R2
10k⍀
*R3
10k⍀
*R4
10k⍀
*R
G
20k⍀
GAIN =
+ 6
(200⍀ + 12.7⍀)
R
G
T o calibrate out the nonlinearity, substitute a 194.07 Ω resistor
(equivalent to 250°C) in place of the RT D, then adjust the
LINEARIT Y ADJUST potentiometer for a 2.500 V output.
Check and readjust the full-scale and half-scale as needed.
*ALL RESISTORS ؎0.1%, ؎25ppm/؇C
Figure 5. Ultralow Noise, Single Supply Instrum entation
Am plifier
Once calibrated, the amplifier outputs a 10 mV/°C temperature
coefficient with an accuracy better than ±0.5°C over an RT D
measurement range of –150°C to +500°C. Indeed the amplifier
can be calibrated to a higher temperature range, up to 850°C.
REV. C
–6–
OP113/OP213/OP413
Supply Splitter Cir cuit
Low Noise Voltage Refer ence
T he OP113 family has excellent frequency response characteris-
tic that makes it an ideal pseudo-ground reference generator as
shown in Figure 6. T he OP113 family serves as a voltage fol-
lower buffer. In addition, it drives a large capacitor that serves
as a charge reservoir to minimize transient load changes, as well
as a low impedance output device at high frequencies. T he
circuit easily supplies 25 mA load current with good settling
characteristics.
Few reference devices combine low noise and high output drive
capabilities. Figure 7 shows the OP113 family used as a two-
pole active filter that band limits the noise of the 2.500 V refer-
ence. T otal noise measures 3 µV p-p.
+5V
–
+5V
10F
+
8
+
V
= +5V +12V
S
2
2
OUTPUT
+2.500V
1
IN
1/2 OP113
4
R3
2.5k⍀
10k⍀
10k⍀
OUT
6
3
+
C2
3V p-p NOISE
REF43
C1
0.1F
10F
GND
4
R1
5k⍀
Figure 7. Low Noise Voltage Reference
8
1/2 OP113
4
2
3
R4
100⍀
+
+5 V O nly Ster eo D AC for Multim edia
V
S
2
1
OUTPUT
+
T he OP113 family’s low noise and single supply capability are
ideally suited for stereo DAC audio reproduction or sound
synthesis applications such as multimedia systems. Figure 8
shows an 18-bit stereo DAC output setup that is powered from a
single +5 volt supply. The low noise preserves the 18-bit dynamic
range of the AD1868. For DACs that operate on dual supplies,
the OP113 family can also be powered from the same supplies.
C2
1F
R2
5k⍀
Figure 6. False Ground Generator
+5V SUPPLY
AD1868
VBL
VOL
1
2
3
4
5
6
7
8
V
L
16
15
18-BIT
DAC
8
LL
220F
LEFT
1
CHANNEL
OUTPUT
47k⍀
1/2 OP213
+
–
7.68k⍀
330pF
9.76k⍀
18-BIT
DL SERIAL
14
13
12
11
10
9
REG.
100pF
V
V
REF
CK
DR
7.68k⍀
7.68k⍀
AGND
VOR
18-BIT
SERIAL
REG.
LR
REF
DGND
18-BIT
DAC
100pF
7.68k⍀ 9.76k⍀
330pF
6
V
S
220F
RIGHT
VBR
CHANNEL
OUTPUT
47k⍀
7
1/2 OP213
+
–
5
Figure 8. +5 V Only 18-Bit Stereo DAC
SoundPort is a registered trademark of Analog Devices, Inc.
REV. C
–7–
OP113/OP213/OP413
P r ecision Voltage Com par ator
Low Voltage H eadphone Am plifier s
With its PNP inputs and zero volt common-mode capability, the
OP113 family can make useful voltage comparators. T here is
only a slight penalty in speed in comparison to IC comparators.
However, the significant advantage is its voltage accuracy. For
example, VOS can be a few hundred microvolts or less, combined
with CMRR and PSRR exceeding 100 dB, while operating on
5 V supply. Standard comparators like the 111/311 family oper-
ate on 5 volts, but not with common-mode at ground, nor with
offset below 3 mV. Indeed, no commercially available single
supply comparator has a VOS less than 200 µV.
Figure 9 shows a stereo headphone output amplifier for the
AD1849 16-bit SoundPort® Stereo Codec device. T he pseudo-
reference voltage is derived from the common-mode voltage
generated internally by the AD1849, thus providing a conve-
nient bias for the headphone output amplifiers.
OPTIONAL
GAIN
1k⍀
5k⍀
V
REF
+5V
10F
10k⍀
31
LOUT1L
220F
Figure 11 shows the OP113 family response to a 10 mV over-
drive signal when operating in open loop. T he top trace shows
the output rising edge has a 15 µs propagation delay, while the
bottom trace shows a 7 µs delay on the output falling edge. T his
ac response is quite acceptable in many applications.
16⍀
1/2
OP213
+
L VOLUME
CONTROL
HEADPHONE
LEFT
47k⍀
+5V
AD1849
؎10mV OVERDRIVE
1/2
OP213
+5V
V
REF
+2.5V
25k⍀
0V
1/2
OP113
–2.5V
= t = 5ms
100⍀
19
29
CMOUT
LOUT1R
t
r
f
10k⍀
10F
220F
16⍀
1/2
OP213
+
HEADPHONE
RIGHT
47k⍀
R VOLUME
CONTROL
5s
2V
5k⍀
1k⍀
100
90
OPTIONAL
GAIN
V
REF
Figure 9. Headphone Output Am plifier for Multim edia
Sound Codec
Low Noise Micr ophone Am plifier for Multim edia
10
0%
T he OP113 family is ideally suited as a low noise microphone
preamp for low voltage audio applications. Figure 10 shows a
gain of 100 stereo preamp for the AD1849 16-bit SoundPort
Stereo Codec chip. T he common-mode output buffer serves as
a “phantom power” driver for the microphones.
2V
Figure 11. Precision Com parator
T he low noise and 250 µV (maximum) offset voltage enhance
the overall dc accuracy of this type of comparator. Note that
zero crossing detectors and similar ground referred comparisons
can be implemented even if the input swings to –0.3 volts below
ground.
10k⍀
+5V
1/2
OP213
17
MINL
10F
50⍀
LEFT
ELECTRET
CONDENSER
MIC
20⍀
10k⍀
100⍀
AD1849
CMOUT
INPUT
+5V
19
1/2
OP213
100⍀
20⍀
10F
10k⍀
50⍀
1/2
OP213
15
MINR
RIGHT
ELECTRET
CONDENSER
MIC
INPUT
10k⍀
Figure 10. Low Noise Stereo Microphone Am plifier for
Multim edia Sound Codec
SoundPort is a registered trademark of Analog Device, Inc.
REV. C
–8–
OP113/OP213/OP413
100
80
60
40
20
0
150
120
90
60
30
0
V
T
= ؎15V
= +25؇C
V
= ؎15V
S
S
–40؇C
400
؋
OP AMPS PLASTIC PKG
T
+85؇C
A
A
400
؋
OP AMPS PLASTIC PKG
–50 –40 –30 –20 –10
0
10
20
30
40
50
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
INPUT OFFSET VOLTAGE, V – V
TCV – V
OS
OS
Figure 12a. OP113 Input Offset (VOS) Distribution
Figure 13a. OP113 Tem perature Drift (TCVOS
)
@ ±15 V
Distribution @ ±15 V
500
400
300
200
100
0
500
V
= ؎15V
= +25؇C
S
V
= ؎15V
S
T
A
400
300
200
100
0
–40؇C
T
+85؇C
A
896 (PLASTIC)
؋
OP AMPS 896 (PLASTIC)
؋
OP AMPS 0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
–100 –80 –60 –40 –20
0
20
40
60
80
100
TCV – V
INPUT OFFSET VOLTAGE, V – V
OS
OS
Figure 12b. OP213 Input Offset (VOS) Distribution
Figure 13b. OP213 Tem perature Drift (TCVOS
)
@ ±15 V
Distribution @ ±15 V
500
600
500
400
300
200
100
0
V
= ؎15V
= +25؇C
S
T
A
V
= ؎15V
S
400
300
200
100
0
1220
؋
OP AMPS PLASTIC PKG
–40؇C
T
+85؇C
A
1220
؋
OP AMPS PLASTIC PKG
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
–60 –40 –20
0
20
40
60
80
100 120 140
TCV – V
INPUT OFFSET VOLTAGE, V – V
OS
OS
Figure 13c. OP413 Tem perature Drift (TCVOS
)
Figure 12c. OP413 Input Offset (VOS) Distribution
Distribution @ ±15 V
@ ±15 V
REV. C
–9–
OP113/OP213/OP413
500
400
300
200
100
0
1000
800
600
V
= 0V
V
= +5.0V
CM
S
V
= ؎15V
S
V
V
= 5.0V
S
400
200
0
= 2.5V
CM
V
V
= ؎15V
S
= 0V
CM
25
50
75
100
125
–75
–50
–25
0
25
50
75
100
125
–75
–50
–25
0
TEMPERATURE –
C
TEMPERATURE – ؇C
Figure 14. OP113 Input Bias Current vs. Tem perature
Figure 17. OP213 Input Bias Current vs. Tem perature
2.0
1.5
5.0
4.5
4.0
15.0
V
= ؎15V
V
= +5.0V
S
S
+SWING
= 2k⍀
14.5
14.0
13.5
13.0
12.5
R
L
+SWING
= 2k⍀
R
L
+SWING
R
= 600⍀
L
–SWING
= 2k⍀
1.0
R
L
+SWING
R
= 600⍀
L
–SWING
= 2k⍀
–13.5
–14.0
–14.5
–15.0
R
3.5
3.0
L
0.5
0
–SWING
–SWING
R
= 600⍀
L
R
= 600⍀
L
–75
–50
–25
0
25
50
75
100
125
–75
–50
–25
0
25
50
75
100
125
TEMPERATURE – ؇C
TEMPERATURE – ؇C
Figure 15. Output Swing vs. Tem perature and RL @ +5 V
Figure 18. Output Swing vs. Tem perature and RL @ ±15 V
60
20
V
V
= +5.0V
= 3.9V
S
V
= ؎15V
= +25؇C
S
40
20
18
O
T
A
16
14
12
R
= 2k⍀
L
0
–20
–40
10
8
–60
R
= 600⍀
L
–80
6
–100
–120
4
2
0
105
10
100
1k
10k
100k
1M
10M
–75
–50
–25
0
25
50
75
100
125
TEMPERATURE – ؇C
FREQUENCY – Hz
Figure 16. Channel Separation
Figure 19. Open-Loop Gain vs. Tem perature @ +5 V
REV. C
–10–
OP113/OP213/OP413
12.5
10
9
V
V
= ؎15V
= ؎10V
V
V
= ؎15V
= ؎10V
S
D
S
R
= 2k⍀
L
O
10.0
7.5
8
7
6
R
= 2k⍀
L
R
= 1k⍀
L
5
4
3
5.0
R
= 600⍀
L
R
= 600⍀
L
2.5
0
2
1
0
–75
–50
–25
0
25
50
75
100
125
–75
–50
–25
0
25
50
75
100
125
TEMPERATURE – ؇C
TEMPERATURE – ؇C
Figure 20. OP413 Open-Loop Gain vs. Tem perature
Figure 23. OP213 Open-Loop Gain vs. Tem perature
100
100
V+ = 5V
V– = 0V
T
= +25؇C
= ؎15V
A
V
S
T
= +25؇C
A
80
60
40
20
0
80
60
40
20
0
45
45
GAIN
GAIN
90
90
PHASE
PHASE
m = 57؇
135
180
225
m = 72؇
135
180
225
0
0
–20
–20
1k
10k
100k
FREQUENCY – Hz
1M
10M
1k
10k
100k
FREQUENCY – Hz
1M
10M
Figure 24. Open-Loop Gain, Phase vs. Frequency @ ±15 V
Figure 21. Open-Loop Gain, Phase vs. Frequency @ +5 V
50
50
V+ = 5V
V– = 0V
T
= +25؇C
= ؎15V
A
40
30
40
T
= +25؇C
V
A
S
A
= +100
A
A
A
= +100
= +10
= +1
V
V
V
V
30
20
20
10
A
A
= +10
= +1
V
10
0
0
V
–10
–20
–10
–20
1k
1k
10k
100k
1M
10M
10k
100k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 22. Closed-Loop Gain vs. Frequency @ +5 V
Figure 25. Closed-Loop Gain vs. Frequency @ ±15 V
REV. C
–11–
OP113/OP213/OP413
70
5
4
3
70
65
60
55
50
5
4
3
V+ = 5V
V– = 0V
V
= ؎15V
S
65
GBW
GBW
m
60
m
55
50
2
1
2
1
–75
–50
–25
0
25
50
75
100
125
–75
–50
–25
0
25
50
75
100
125
TEMPERATURE – ؇C
TEMPERATURE – ؇C
Figure 26. Gain Bandwidth Product and Phase Margin vs.
Tem perature @ +5 V
Figure 29. Gain Bandwidth Product and Phase Margin vs.
Tem perature @ ±15 V
30
3.0
T
= +25؇C
= ؎15V
T
= +25؇C
= ؎15V
A
A
V
V
S
S
25
20
15
10
5
2.5
2.0
1.5
1.0
0.5
0
0
1
10
100
FREQUENCY – Hz
1k
1
10
100
FREQUENCY – Hz
1k
Figure 27. Voltage Noise Density vs. Frequency
Figure 30. Current Noise Density vs. Frequency
140
140
T
= +25؇C
= ؎15V
V+ = 5V
V– = 0V
A
V
S
120
100
T
= +25؇C
120
100
A
80
60
80
60
40
20
0
40
20
0
100
1k
10k
100k
1M
100
1k
10k
100k
1M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 28. Com m on-Mode Rejection vs. Frequency @ +5 V
Figure 31. Com m on-Mode Rejection vs. Frequency
@ ±15 V
REV. C
–12–
OP113/OP213/OP413
140
40
30
20
T
= +25؇C
= ؎15V
T
= +25؇C
= ؎15V
A
A
V
V
S
S
120
100
+PSRR
80
60
–PSRR
A
= +100
V
40
20
0
10
0
A
= +10
100k
V
A
= +1
V
100
1k
10k
FREQUENCY – Hz
100k
1M
100
1k
10k
FREQUENCY – Hz
1M
Figure 32. Power Supply Rejection vs. Frequency
@ ±15 V
Figure 35. Closed-Loop Output Im pedance vs. Frequency
@ ±15 V
6
30
V
= ؎15V
= 2k⍀
= +25؇C
= +1
V
= +5V
= 2k⍀
= +25؇C
= +1
S
S
R
T
R
T
L
L
5
4
3
2
25
20
15
10
A
A
A
A
VOL
VCL
1
0
5
0
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 33. Maxim um Output Swing vs. Frequency @ +5 V
Figure 36. Maxim um Output Swing vs. Frequency
@ ±15 V
20
50
V
= ؎15V
S
V
= +5V
S
18
45
R
V
= 2k⍀
= 100mV p-p
= +25؇C
L
R
V
= 2k⍀
= 100mV p-p
= +25؇C
L
IN
IN
16
14
12
40
35
30
T
A
T
A
A
= +1
POSITIVE
EDGE
VCL
A
= +1
VCL
NEGATIVE
EDGE
NEGATIVE
EDGE
10
8
25
20
15
POSITIVE
EDGE
6
4
2
0
10
5
0
100
200
300
400
500
100
200
300
400
500
0
0
LOAD CAPACITANCE – pF
LOAD CAPACITANCE – pF
Figure 34. Sm all Signal Overshoot vs. Load Capacitance
@ +5 V
Figure 37. Sm all Signal Overshoot vs. Load Capacitance
@ ±15 V
REV. C
–13–
OP113/OP213/OP413
2.0
2.0
1.5
1.0
0.5
0
V
V
= ؎15V
V
= +5, 0
S
S
+SLEW RATE
+0.5V
V
+4.0V
= ؎10V
OUT
OUT
1.5
1.0
0.5
0
–SLEW RATE
+SLEW RATE
–SLEW RATE
–75
–50
–25
0
25
50
75
100
125
–75
–50
–25
0
25
50
75
100
125
TEMPERATURE – ؇C
TEMPERATURE – ؇C
Figure 41. Slew Rate vs. Tem perature @ ±15 V
(–10 V ≤ VOUT ≤ +10.0 V)
Figure 38. Slew Rate vs. Tem perature @ +5 V
(0.5 V ≤ VOUT ≤ +4.0 V)
1s
1s
100
100
90
90
10
10
0%
0%
20mV
20mV
Figure 42. Input Voltage Noise @ +5 V
(20 nV/ div)
Figure 39. Input Voltage Noise @ ±15 V
(20 nV/div)
5
909⍀
4
100⍀
0.1 – 10Hz
= 1000
V
= ؎18V
S
A
V
V
= ؎15V
S
3
2
V
= +5.0V
S
A
= 100
tOUT
V
Figure 40. Noise Test Diagram
1
0
–75
–50
–25
0
25
50
75
100
125
TEMPERATURE – ؇C
Figure 43. Supply Current vs. Tem perature
REV. C
–14–
OP113/OP213/OP413
* SECOND CURRENT NOISE SOURCE
DN5 27 28 DIN
DN6 28 29 DIN
VN5 27
0
DC 2
+IN
–IN
VN6
*
0
29 DC 2
9V 9V
OUT
* GAIN ST AGE & DOMINANT POLE AT .2000E+01 HZ
G2
R7
V3
D4
34 36 19 20 2.65E–04
34 36 39E+06
35
4
DC 6
36 35 DX
VB2 34
*
4
1.6
* SUPPLY/2 GENERAT OR
ISY
R10
R11
C3
*
7
7
60
60
4
0.2E–3
60 40E+3
4
0
40E+3
1E–9
* CMRR ST AGE & POLE AT 6 kHZ
ECM 50 POLY(2) 3 60
CCM 50 51 26.5E–12
RCM1 50 51 1E6
4
2
60
0
1.6
0
1.6
Figure 44. OP213 Sim plified Schem atic
RCM2 51
4
1
*
*
*OP113 Family SPICE Macro-Model
*
OUT PUT ST AGE
*Copyright 1992 by Analog Devices, Inc.
*
*Node Assignments
*
R12
R13
C4
37 36 1E3
38 36 500
37
6
20E–12
C5
38 39 20E–12
*
*
*
*
Noninverting Input
Inverting Input
Positive Supply
Negative Supply
M1
M2
D5
D6
Q3
VB
R14
Q4
R17
Q5
Q6
R18
Q7
M3
*
39 36 4 4 MN L=9E–6 W=1000E–6 AD=15E–9 AS=15E–9
45 36 4 4 MN L=9E–6 W=1000E–6 AD=15E–9 AS=15E–9
39 47 DX
47 45 DX
39 40 41 QPA 8
7
7
40 DC 0.861
41 375
*
*
Output
6
41
7
7
43 QNA 1
43 15
.SUBCKT OP113 Family
3
2
7
4
43 39
46 45
6
6
QNA 20
QPA 20
*
* INPUT ST AGE
46
36 46
4
15
4
R3
R4
4
4
19 1.5E3
20 1.5E3
QNA 1
6
36 4 4 MN L = 9E–6 W=2000E–6 AD=30E–9 AS=30E–9
C1
19 20 5.31E–12
I1
7
18 106E–6
* NONLINEAR MODELS USED
*
.MODEL DX D (IS=1E–15)
.MODEL DY D (IS=1E–15 BV=7)
IOS
EOS
Q1
2
12
19
3
5
3
25E–09
POLY(1)
51
4
25E–06
1
18
PNP1
Q2
20 12 18
PNP1
.MODEL PNP1 PNP (BF=220)
CIN
D1
D2
EN
GN1
GN2
*
3
3
2
5
0
0
2
1
1
2
2
3
3E–12
DY
DY
22
25
28
.MODEL DEN D(IS=1E–12 RS=1016 KF=3.278E–15 AF=1)
.MODEL DIN D(IS=1E–12 RS=100019 KF=4.173E–15 AF=1)
.MODEL QNA NPN(IS=1.19E–16 BF=253 VAF=193 VAR=15 RB=2.0E3
+ IRB=7.73E–6 RBM=132.8 RE=4 RC=209 CJE=2.1E–13 VJE=0.573
+ MJE=0.364 CJC=1.64E–13 VJC=0.534 MJC=0.5 CJS=1.37E–12
+ VJS=0.59 MJS=0.5 T F=0.43E–9 PT F=30)
0
0
0
1
1E–5
1E–5
.MODEL QPA PNP(IS=5.21E–17 BF=131 VAF=62 VAR= 15 RB=1.52E3
+ IRB=1.67E–5 RBM=368.5 RE=6.31 RC=354.4 CJE=1.1E–13
+ VJE=0.745 MJE=0.33 CJC=2.37E–13 VJC=0.762 MJC=0.4
+ CJS=7.11E–13 VJS=0.45 MJS=0.412 T F=1.0E–9 PT F=30)
.MODEL MN NMOS(LEVEL=3 VT O=1.3 RS=0.3 RD=0.3 T OX=8.5E–8
+ LD=1.48E–6 WD=1E–6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5
+ XJ=1.75E–6 KAPPA=0.8 ET A=0.066 T HET A=0.01 T PG=1 CJ=2.9E–4
+ PB=0.837 MJ=0.407 CJSW=0.5E–9 MJSW=0.33)
*
* VOLT AGE NOISE SOURCE WIT H FLICKER NOISE
DN1
DN2
VN1
VN2
*
21 22 DEN
22 23 DEN
21
0
0
DC 2
23 DC 2
* CURRENT NOISE SOURCE WIT H FLICKER NOISE
DN3
DN4
VN3
VN4
*
24 25 DIN
25 26 DIN
.ENDS OP113 Family
24
0
0
DC 2
26 DC 2
REV. C
–15–
OP113/OP213/OP413
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
8-Lead P lastic D IP
14-Lead P lastic D IP
(N-14)
(N-8)
0.430 (10.92)
0.348 (8.84)
0.795 (20.19)
0.725 (18.41)
14
8
7
8
5
4
0.280 (7.11)
0.240 (6.10)
0.280 (7.11)
0.240 (6.10)
1
0.325 (8.25)
0.300 (7.62)
1
0.195 (4.95)
0.115 (2.93)
0.325 (8.25)
0.300 (7.62)
0.060 (1.52)
0.015 (0.38)
PIN 1
0.060 (1.52)
0.015 (0.38)
PIN 1
0.210 (5.33)
MAX
0.195 (4.95)
0.115 (2.93)
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.92)
0.160 (4.06)
0.115 (2.93)
0.015 (0.38)
SEATING
PLANE
0.022 (0.558) 0.100 0.070 (1.77)
0.015 (0.381)
0.008 (0.204)
0.008 (0.20)
SEATING
PLANE
0.100
(2.54)
BSC
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
(2.54)
BSC
0.014 (0.36)
0.045 (1.15)
8-Lead Nar r ow-Body P lastic D IP
(SO -8)
16-Lead Wide Body SO IC
(R-16)
0.4133 (10.50)
0.3977 (10.00)
16
9
0.1968 (5.00)
0.1890 (4.80)
8
1
5
4
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
1
8
PIN 1
0.0688 (1.75)
0.0532 (1.35)
0.0196 (0.50)
0.0099 (0.25)
0.1043 (2.65)
0.0926 (2.35)
PIN 1
0.0291 (0.74)
0.0098 (0.25)
x 45°
x 45؇
0.0098 (0.25)
0.0040 (0.10)
0.0118 (0.30)
0.0040 (0.10)
8°
0°
0.0500 (1.27)
0.0157 (0.40)
8؇
0؇
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0500
(1.27)
BSC
0.0192 (0.49)
SEATING
PLANE
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
0.0138 (0.35)
REV. C
–16–
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