OP150GBC [ADI]
CMOS Single-Supply Rail-to-Rail Input/Output Operational Amplifier; CMOS单电源轨到轨输入/输出运算放大器
| 型号： | OP150GBC |
| 厂家： | 
ADI |
| 描述： | CMOS Single-Supply Rail-to-Rail Input/Output Operational Amplifier |
| 文件： | 总5页 (文件大小：65K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS Single-Supply Rail-to-Rail
Input/Output Operational Amplifier
a
OP150/OP250/OP450
FEATURES
P IN CO NFIGURATIO NS
Single-Supply Operation: 2.7 V to 6 V
High Output Current: ؎250 m A
Low Supply Current: 600 A/ Am p
Wide Bandw idth: 4 MHz
Slew Rate: 6.5 V/ s
8-Lead Narrow-Body SO
(S Suffix)
5-Lead SO T23-5
(RT Suffix)
No Phase Reversal
Low Input Currents
Unity Gain Stable
OUT
V–
+IN
V+
NC
V+
NC
–IN
+IN
V–
–IN
OP150
OUT
NC
OP150
APPLICATIONS
Battery Pow ered Instrum entation
Multi Media Audio
Medical
8 Lead Epoxy D IP
(P Suffix)
8-Lead Narrow-Body SO
(S Suffix)
Rem ote Sensors
ASIC Input or Output Am plifier
Autom otive
Headphone Driver
V+
1
2
3
4
8
7
6
5
V+
OP250
OUT A
–IN A
+IN A
V–
OUT A
OUT B
–IN A
+IN A
V–
OUT B
–IN B
+IN B
OP250
–IN B
+IN B
GENERAL D ESCRIP TIO N
14-Lead Epoxy D IP
(P Suffix)
T he OP150, OP250 and OP450 are single, dual and quad
CMOS single-supply, 4 MHz bandwidth amplifiers featuring
rail-to-rail inputs and outputs. All are guaranteed to operate from
a 3 volt single supply as well as a +5 volt supply.
14-Lead SO
(S Suffix)
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT A
–IN A
+IN A
V+
OUT D
–IN D
+IN D
V–
T he OP150 family of amplifiers have very low input bias cur-
rents. T he outputs are capable of driving 250 mA loads and are
stable with capacitive loads as high as 500 pF.
OUT D
–IN D
+IN D
V–
OUT A
–IN A
+IN A
V+
OP450
OP450
Applications for these amplifiers include portable medical
equipment, safety and security, and interface for transducers
with high output impedances.
+IN B
+IN C
–IN C
OUT C
+IN C
–IN C
OUT C
+IN B
–IN B
OUT B
–IN B
OUT B
8
Supply current is only 600 µA per amplifier.
T he ability to swing rail-to-rail at both the input and output en-
ables designers to build multistage filters in single-supply sys-
tems and maintain high signal-to-noise ratios.
14-Lead
TSSO P
(RU Suffix)
T he OP150/OP250/OP450 are specified over the extended in-
dustrial (-40°C to +125°C) temperature range. T he OP150
single amplifiers are available in 8-pin SO surface mount and
the 5-pin SOT 23-5 packages. T he OP250 dual is available in 8-
pin plastic DIPs and SO surface mount packages. T he OP450
quad is available in 14-pin DIPs, T SSOP and narrow 14-pin SO
packages. Consult factory for T SSOP availability.
OP450
This inform ation applies to a product under developm ent. Its characteristics and specifications are subject to change without notice.
Analog Devices assum es no obligation regarding future m anufacture unless otherwise agreed to in writing.
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
PRELIMINARY TECHNICAL DATA
REV. 0
OP150/OP250/OP450–SPECIFICATIONS
(@ V = +3.0 V, V = 0.05 V, V = 1.4 V, T = +25؇C, unless otherwise noted)
ELECTRICAL CHARACTERISTICS
S
CM
O
A
P aram eter
Sym bol
Conditions
Min
Typ
Max
Units
INPUT CHARACT ERIST ICS
Offset Voltage OP150
VOS
VOS
IB
5
mV
mV
mV
mV
pA
pA
pA
pA
–40°C ≤ T A ≤ +125°C
–40°C ≤ T A ≤ +125°C
–40°C ≤ T A ≤ +125°C
–40°C ≤ T A ≤ +125°C
Offset Voltage OP250/OP450
Input Bias Current
5
10
25
60
Input Offset Current
IOS
Input Voltage Range
0
3
V
Common-Mode Rejection Ratio
CMRR
AVO
VCM = 0 V to 3 V
–40°C ≤ T A ≤ +125°C
RL = 10 kΩ, VO = 0.3 V to 2.7 V
–40°C ≤ T A ≤ +125°C
RL = 2 kΩ, VO = 0.3 V to 2.7 V
RL = 1 kΩ, VO = 0.3 V to 2.7 V
60
dB
dB
Large Signal Voltage Gain
40
V/mV
V/mV
V/mV
V/mV
µV/°C
pA/°C
pA/°C
Large Signal Voltage Gain
Large Signal Voltage Gain
Offset Voltage Drift
Bias Current Drift
Offset Current Drift
AVO
AVO
∆VOS/∆T
∆IB/∆T
∆IOS/∆T
16
10
OUT PUT CHARACT ERIST ICS
Output Voltage High
VOH
IL = 100 µA
–40°C to +125°C
IL = 10 mA
–40°C to +125°C
IL = 100 µA
–40°C to +125°C
IL = 10 mA
2.95
2.99
2.95
2
V
V
V
V
mV
mV
mV
mV
mA
mA
Ω
Output Voltage Low
VOL
10
55
30
–40°C to +125°C
Output Current
IOUT
±250
–40°C to +125°C
f = 1 MHz, AV = 1
Open Loop Impedance
ZOUT
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
ISY
VS = 2.7 V to 6 V
–40°C ≤ T A ≤ +125°C
VO = 0 V
70
68
dB
dB
µA
µA
Supply Current/Amplifier
500
650
600
–40°C ≤ T A ≤ +125°C
DYNAMIC PERFORMANCE
Slew Rate
Settling T ime
SR
tS
RL =10 kΩ
T o 0.01%
2.7
V/µs
µs
Gain Bandwidth Product
Phase Margin
Channel Separation
GBP
Øo
CS
2
75
MHz
Degrees
dB
f = 1 kHz, RL =10 kΩ
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
µV p-p
nV/√Hz
pA/√Hz
55
Specifications subject to change without notice.
This inform ation applies to a product under developm ent. Its characteristics and specifications are subject to change without notice.
Analog Devices assum es no obligation regarding future m anufacture unless otherwise agreed to in writing.
REV. 0
–2–
PRELIMINARY TECHNICAL DATA
OP150/OP250/OP450
(@ V = +5.0 V, V = 0.05 V, V = 1.4 V, T = +25؇C, unless otherwise noted)
ELECTRICAL CHARACTERISTICS
S
CM
O
A
P aram eter
Sym bol
Conditions
Min
Typ
Max
Units
INPUT CHARACT ERIST ICS
Offset Voltage OP150
VOS
VOS
IB
5
5
mV
mV
mV
mV
pA
pA
pA
pA
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
Offset Voltage OP250/OP450
Input Bias Current
30
50
60
8
16
5
Input Offset Current
IOS
0.1
Input Voltage Range
0
V
Common-Mode Rejection Ratio
CMRR
AVO
VCM = 0 V to 5 V
–40°C ≤ TA ≤ +125°C
60
dB
dB
Large Signal Voltage Gain
RL = 10 kΩ, VO = 0.3 V to 4.7 V
–40°C ≤ TA ≤ +125°C
RL = 2 kΩ, VO = 0.3 V to 2.7 V
RL = 1 kΩ, VO = 0.3 V to 2.7 V
–40°C ≤ TA ≤ +125°C
40
V/mV
V/mV
V/mV
V/mV
µV/°C
pA/°C
pA/°C
Large Signal Voltage Gain
Large Signal Voltage Gain
Offset Voltage Drift
Bias Current Drift
Offset Current Drift
AVO
AVO
∆VOS/∆T
∆IB/∆T
∆IOS/∆T
16
10
1.5
100
20
OUT PUT CHARACT ERIST ICS
Output Voltage High
VOH
IL = 100 µA
–40°C to +125°C
IL = 10 mA
–40°C to +125°C
IL = 100 µA
–40°C to +125°C
IL = 10 mA
4.99
4.95
2
V
V
V
V
mV
mV
mV
mV
mA
mA
Ω
Output Voltage Low
VOL
30
–40°C to +125°C
Output Current
IOUT
±250
–40°C to +125°C
f = 1 MHz, AV = 1
Open Loop Impedance
ZOUT
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
ISY
VS = 2.7 V to 6 V
–40°C ≤ TA ≤ +125°C
VO = 0 V
75
70
dB
dB
µA
µA
Supply Current/Amplifier
–40°C ≤ TA ≤ +125°C
550
6.5
650
DYNAMIC PERFORMANCE
Slew Rate
Full Power Bandwidth
Settling T ime
SR
BWp
tS
RL =10 kΩ
1% Distortion
T o 0.01%
V/µs
kHz
µs
Gain Bandwidth Product
Phase Margin
Channel Separation
GBP
Øo
CS
4
75
MHz
Degrees
dB
f = 1 kHz, RL =10 kΩ
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Voltage Noise Density
Current Noise Density
en p-p
en
en
0.1 Hz to 10 Hz
f = 1 kHz
f = 10 kHz
µV p-p
55
35
nV/√Hz
nV/√Hz
pA/√Hz
in
Specifications subject to change without notice.
This inform ation applies to a product under developm ent. Its characteristics and specifications are subject to change without notice.
Analog Devices assum es no obligation regarding future m anufacture unless otherwise agreed to in writing.
REV. 0
PRELIMINARY TECHNICAL DATA
–3–
OP150/OP250/OP450
(@ V = +5.0 V, V = 0 V, T = +25؇C unless otherwise noted.)
WAFER TEST LIMITS
P aram eter
S
CM
A
Sym bol
Conditions
Lim it
Units
Offset Voltage
Input Bias Current
Input Offset Current
Input Voltage Range
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage High
Output Voltage Low
VOS
IB
IOS
VCM
CMRR
PSRR
AVO
VOH
VOL
ISY
±10
50
10
V– to V+
60
70
mV max
pA max
pA max
V min
dB min
dB min
V/mV min
V min
VCM = 0 V to 10 V
V = +2.7 V to +7 V
RL = 10 kΩ
RL = 2 kΩ to GND
RL = 2 kΩ to V+
VO = 0 V, RL = ∞
2.9
55
650
mV max
µA max
Supply Current/Amplifier
NOT E
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard
product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
ABSO LUTE MAXIMUM RATINGS1
O RD ERING GUID E
Tem perature
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Output Short-Circuit Duration to GND2 . . . . . . . . . Indefinite
Storage T emperature Range
P, S, RT , RU Package . . . . . . . . . . . . . . . . –65°C to +150°C
Operating T emperature Range
OP150/OP250/OP450G . . . . . . . . . . . . . . . –40°C to +125°C
Junction T emperature Range
Model
Range
P ackage O ption
OP150GS
–40°C to +125°C
–40°C to +125°C
+25°C
8-Pin SOIC
5-Pin SOT
DICE
OP150GRT
OP150GBC
OP250GP
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
+25°C
8-Pin Plastic DIP
8-Pin SOIC
8-Pin T SSOP
DICE
OP250GS
OP250GRU
OP250GBC
OP450GP
OP450GS
OP450GRU
OP450GBC
P, S, RT , RU Package . . . . . . . . . . . . . . . . –65°C to +150°C
Lead T emperature Range (Soldering, 60 sec) . . . . . . . +300°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
+25°C
14-Pin Plastic DIP
14-Pin SOIC
14-Pin T SSOP
DICE
3
P ackage Type
θJA
θJC
Units
5-Pin SOT (RT )
8-Pin Plastic DIP (P)
8-Pin SOIC (S)
8-Pin T SSOP (RU)
14-Pin Plastic DIP (P)
14-Pin SOIC (S)
325
103
158
240
76
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
43
43
43
33
36
35
120
180
14-Pin T SSOP( RU)
NOT ES
1Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2θJA is specified for the worst case conditions, i.e., θJA is specified for device in
socket for P-DIP packages; θJA is specified for device soldered in circuit board
for SOIC package.
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the OP150/OP250/OP450 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. T herefore, p roper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
This inform ation applies to a product under developm ent. Its characteristics and specifications are subject to change without notice.
Analog Devices assum es no obligation regarding future m anufacture unless otherwise agreed to in writing.
PRELIMINARY TECHNICAL DATA
REV. 0
–4–
OP150/OP250/OP450
D ICE CH ARACTERISTICS
OP150 Die Size 0.00 × 0.00 Inch, 00 Sq. Mils
Substrate (Die Backside) Is Connected to V–
Transistor Count, 00.
OP250 Die Size 0.044 × 0.045 Inch, 1,980 Sq. Mils
Substrate (Die Backside) Is Connected to V–
Transistor Count, 0.
OP450 Die Size 0.052 × 0.058 Inch, 3,016 Sq. Mils
Substrate (Die Backside) Is Connected to V–
Transistor Count, 127.
2.5
V
OL
V
OH
2.0
1.5
1.0
0.5
0
0
20
40
60
80
100 120 140 160 180 200
R
– Ω
LOAD
Figure 1. ±VOUT vs. RLOAD
This inform ation applies to a product under developm ent. Its characteristics and specifications are subject to change without notice.
Analog Devices assum es no obligation regarding future m anufacture unless otherwise agreed to in writing.
REV. 0
PRELIMINARY TECHNICAL DATA
–5–
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