OP193_02 [ADI]
Precision, Micropower Operational Amplifiers; 高精度，微功耗运算放大器
| 型号： | OP193_02 |
| 厂家： | 
ADI |
| 描述： | Precision, Micropower Operational Amplifiers |
| 文件： | 总16页 (文件大小：216K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Precision, Micropower
Operational Amplifiers
a
OP193/OP293/OP493*
PIN CONFIGURATIONS
FEATURES
Operates from +1.7 V to ؎18 V
Low Supply Current: 15 A/Amplifier
Low Offset Voltage: 75 V
Outputs Sink and Source: ؎8 mA
No Phase Reversal
Single- or Dual-Supply Operation
High Open-Loop Gain: 600 V/mV
Unity-Gain Stable
8-Lead SO
(S Suffix)
8-Lead Epoxy DIP
(P Suffix)
NULL
–IN A
+IN A
V–
NC
NULL
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
NC
OP193
V+
OP193
V+
OUT A
NULL
OUT A
NULL
APPLICATIONS
Digital Scales
NC = NO CONNECT
Strain Gages
Portable Medical Equipment
Battery-Powered Instrumentation
Temperature Transducer Amplifier
8-Lead SO
(S Suffix)
8-Lead Epoxy DIP
(P Suffix)
OUT A
–IN A
+IN A
V–
V+
GENERAL DESCRIPTION
V+
OUT A
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
OP293
OUT B
–IN B
+IN B
The OP193 family of single-supply operational amplifiers fea-
tures a combination of high precision, low supply current and
the ability to operate at low voltages. For high performance in
single-supply systems the input and output ranges include
ground, and the outputs swing from the negative rail to within
600 mV of the positive supply. For low voltage operation the
OP193 family can operate down to 1.7 volts or 0.85 volts.
OP293
OUT B
–IN B
+IN B
16-Lead Wide Body SOL
(S Suffix)
14-Lead Epoxy DIP
(P Suffix)
The combination of high accuracy and low power operation
make the OP193 family useful for battery-powered equipment.
Its low current drain and low voltage operation allow it to
continue performing long after other amplifiers have ceased
functioning either because of battery drain or headroom.
OUT A
OUT D
OUT A
1
2
3
4
5
6
7
OUT D
–IN D
+IN D
V–
14
13
12
11
10
9
–IN A
+IN A
V+
–IN D
+IN D
V–
–IN A
+IN A
V+
The OP193 family is specified for single +2 volt through dual
15 volt operation over the HOT (–40°C to +125°C) temperature
range. They are available in plastic DIPs, plus SOIC surface-
mount packages.
OP493
+IN B
–IN B
OUT B
NC
+IN C
–IN C
OUT C
NC
OP493
+IN B
–IN B
OUT B
+IN C
–IN C
OUT C
8
NC = NO CONNECT
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
OP193/OP293/OP493–SPECIFICATIONS
ELECTRICAL SPECIFICATIONS (@ VS = ؎15.0 V, TA = 25؇C unless otherwise noted)
“E” Grade
“F” Grade
Min Typ Max
Parameter
Symbol
Conditions
Min
Typ Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
OP193
75
150
250
250
350
275
375
µV
µV
µV
µV
µV
µV
OP193, –40°C ≤ TA ≤ +125°C
OP293
OP293, –40°C ≤ TA ≤ +125°C
OP493
OP493, –40°C ≤ TA ≤ +125°C
VCM = 0 V,
–40°C ≤ TA ≤ +125°C
VCM = 0 V,
–40°C ≤ TA ≤ +125°C
175
100
200
125
225
Input Bias Current
Input Offset Current
IB
15
2
20
nA
IOS
4
nA
V
dB
Input Voltage Range
Common-Mode Rejection
VCM
CMRR
–14.9
100
+13.5 –14.9
+13.5
–14.9 ≤ VCM ≤ +14 V
–14.9 ≤ VCM ≤ +14 V,
–40°C ≤ TA ≤ +125°C
RL = 100 kΩ,
–10 V ≤ VOUT ≤ +10 V
–40°C ≤ TA ≤ +85°C
–40°C ≤ TA ≤ +125°C
RL = 10 kΩ,
–10 V ≤ VOUT ≤ +10 V
–40°C ≤ TA ≤ +85°C
–40°C ≤ TA ≤ +125°C
RL = 2 kΩ,
–10 V ≤ VOUT ≤ +10 V
–40°C ≤ TA ≤ +85°C
–40°C ≤ TA ≤ +125°C
Note 1
116
97
116
97
94
dB
Large Signal Voltage Gain
Large Signal Voltage Gain
Large Signal Voltage Gain
AVO
AVO
AVO
VOS
500
300
500
300
V/mV
V/mV
V/mV
300
150
100
300
150
100
350
200
350
200
V/mV
V/mV
V/mV
200
125
200
125
V/mV
V/mV
V/mV
µV
Long Term Offset Voltage
Offset Voltage Drift
150
0.2 1.75
300
∆VOS/∆T Note 2
µV/°C
OUTPUT CHARACTERISTICS
Output Voltage Swing High
VOH IL = 1 mA
14.1
14.2
14.1
14.2
14.1
V
IL = 1 mA,
–40°C ≤ TA ≤ +125°C
IL = 5 mA
14.0
13.9
14.0
13.9
V
V
V
14.1
–14.7 –14.6
Output Voltage Swing Low
VOL
IL = –1 mA
–14.7 –14.6
IL = –1 mA,
–40°C ≤ TA ≤ +125°C
IL = –5 mA
–14.4
+14.2 –14.1
25
–14.4
+14.2 –14.1
25
V
V
mA
Short Circuit Current
ISC
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
VS = 1.5 V to 18 V
VS = 1.5 V to 18 V,
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C, RL = ∞
VOUT = 0 V, VS = 18 V
100
97
120
97
94
120
dB
dB
µA
Supply Current/Amplifier
ISY
30
30
NOISE PERFORMANCE
Voltage Noise Density
Current Noise Density
Voltage Noise
en
in
en p-p
f = 1 kHz
f = 1 kHz
0.1 Hz to 10 Hz
65
0.05
3
65
0.05
3
nV/√Hz
pA/√Hz
µV p-p
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
SR
GBP
RL = 2 kΩ
15
35
15
35
V/ms
kHz
Channel Separation
V
OUT = 10 V p-p,
RL = 2 kΩ, f = 1 kHz
120
120
dB
NOTES
1Long term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at 125°C, with an LTPD of 1.3.
2Offset voltage drift is the average of the –40°C to +25°C delta and the +25°C to +125°C delta.
Specifications subject to change without notice.
–2–
REV. B
OP193/OP293/OP493
ELECTRICAL SPECIFICATIONS (@ VS = 5.0 V, VCM = 0.1 V, TA = 25؇C unless otherwise noted)
“E” Grade
“F” Grade
Parameter
Symbol
Conditions
Min Typ Max
Min Typ Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
OP193
75
150
250
250
350
275
375
20
µV
µV
µV
µV
µV
µV
nA
nA
V
OP193, –40°C ≤ TA ≤ +125°C
OP293
175
100
200
125
225
15
OP293, –40°C ≤ TA ≤ +125°C
OP493
OP493, –40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
Input Bias Current
IB
IOS
VCM
CMRR
Input Offset Current
Input Voltage Range
Common-Mode Rejection
2
4
4
4
0
0
96
0.1 ≤ VCM ≤ 4 V
0.1 ≤ VCM ≤ 4 V,
–40°C ≤ TA ≤ +125°C
RL = 100 kΩ,
0.03 ≤ VOUT ≤ 4.0 V
–40°C ≤ TA ≤ +85°C
–40°C ≤ TA ≤ +125°C
RL = 10 kΩ,
0.03 ≤ VOUT ≤ 4.0 V
–40°C ≤ TA ≤ +85°C
–40°C ≤ TA ≤ +125°C
Note 1
100 116
116
dB
92
92
dB
Large Signal Voltage Gain
Large Signal Voltage Gain
AVO
AVO
VOS
200
125
130
200
125
V/mV
V/mV
V/mV
130
70
75
50
70
75
50
V/mV
V/mV
V/mV
µV
Long Term Offset Voltage
Offset Voltage Drift
150
0.2 1.25
300
∆VOS/∆T Note 2
µV/°C
OUTPUT CHARACTERISTICS
Output Voltage Swing High
VOH
IL = 100 µA
IL = 1 mA
4.4
4.1 4.4
4.4
4.1 4.4
V
V
IL = 1 mA,
–40°C ≤ TA ≤ +125°C
IL = 5 mA
4.0
4.0 4.4
4.0
4.0 4.4
V
V
Output Voltage Swing Low
VOL
IL = –100 µA
IL = –100 µA,
–40°C ≤ TA ≤ +125°C
No Load
140 160
140 160
mV
220
220
5
280 400
mV
mV
mV
5
IL = –1 mA
280 400
IL = –1 mA,
–40°C ≤ TA ≤ +125°C
IL = –5 mA
500
700 900
8
500
700 900
8
mV
mV
mA
Short Circuit Current
ISC
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
VS = 1.7 V to 6.0 V
VS = 1.5 V to 18 V,
–40°C ≤ TA ≤ +125°C
VCM = 2.5 V, RL = ∞
100 120
94
97
90
120
dB
dB
µA
Supply Current/Amplifier
ISY
14.5
14.5
NOISE PERFORMANCE
Voltage Noise Density
Current Noise Density
Voltage Noise
en
in
en p-p
f = 1 kHz
f = 1 kHz
0.1 Hz to 10 Hz
65
0.05
3
65
0.05
3
nV/√Hz
pA/√Hz
µV p-p
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
SR
GBP
RL = 2 kΩ
12
35
12
35
V/ms
kHz
NOTES
1Long term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at 125°C, with an LTPD of 1.3.
2Offset voltage drift is the average of the –40°C to +25°C delta and the +25°C to +125°C delta.
Specifications subject to change without notice.
–3–
REV. B
OP193/OP293/OP493
ELECTRICAL SPECIFICATIONS (@ VS = 3.0 V, VCM = 0.1 V, TA = 25؇C unless otherwise noted)
“E” Grade
“F” Grade
Parameter
Symbol Conditions
Min Typ Max
Min Typ Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
OP193
75
150
250
250
350
275
375
20
µV
µV
µV
µV
µV
µV
nA
nA
V
OP193, –40°C ≤ TA ≤ +125°C
OP293
175
100
200
125
225
15
OP293, –40°C ≤ TA ≤ +125°C
OP493
OP493, –40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
Input Bias Current
IB
IOS
VCM
CMRR
Input Offset Current
Input Voltage Range
Common-Mode Rejection
2
2
4
2
0
97
0
94
0.1 ≤ VCM ≤ 2 V
0.1 ≤ VCM ≤ 2 V,
–40°C ≤ TA ≤ +125°C
RL = 100 kΩ, 0.03 ≤ VOUT ≤ 2 V
–40°C ≤ TA ≤ +85°C
–40°C ≤ TA ≤ +125°C
Note 1
116
100
116
100
dB
90
100
75
87
100
75
dB
Large Signal Voltage Gain
AVO
VOS
V/mV
V/mV
V/mV
µV
Long Term Offset Voltage
Offset Voltage Drift
150
0.2 1.25
300
∆VOS/∆T Note 2
µV/°C
OUTPUT CHARACTERISTICS
Output Voltage Swing High
VOH
VOL
ISC
IL = 1 mA
IL = 1 mA,
–40°C ≤ TA ≤ +125°C
IL = 5 mA
IL = –1 mA
IL = –1 mA
–40°C ≤ TA ≤ +125°C
IL = –5 mA
2.1 2.14
2.1 2.14
V
1.9
1.9 2.1
1.9
1.9 2.1
V
V
mV
Output Voltage Swing Low
280 400
280 400
500
700 900
8
500
700 900
8
mV
mV
mA
Short Circuit Current
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
ISY
VS = +1.7 V to +6 V,
–40°C ≤ TA ≤ +125°C
VCM = 1.5 V, RL = ∞
–40°C ≤ TA ≤ +125°C
100
94
97
90
dB
µA
µA
V
Supply Current/Amplifier
Supply Voltage Range
14.5 22
14.5 22
22
18
22
18
VS
+2
+2
NOISE PERFORMANCE
Voltage Noise Density
Current Noise Density
Voltage Noise
en
in
en p-p
f = 1 kHz
f = 1 kHz
0.1 Hz to 10 Hz
65
0.05
3
65
0.05
3
nV/√Hz
pA/√Hz
µV p-p
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Channel Separation
SR
GBP
RL = 2 kΩ
10
25
10
25
V/ms
kHz
V
OUT = 10 V p-p,
RL = 2 kΩ, f = 1 kHz
120
120
dB
NOTES
1Long term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at 125°C, with an LTPD of 1.3.
2Offset voltage drift is the average of the –40°C to +25°C delta and the +25°C to +125°C delta.
Specifications subject to change without notice.
–4–
REV. B
OP193/OP293/OP493
ELECTRICAL SPECIFICATIONS (@ VS = 2.0 V, VCM = 0.1 V, TA = 25؇C unless otherwise noted)
“E” Grade
“F” Grade
Parameter
Symbol
Conditions
Min Typ Max
Min Typ Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
OP193
75
150
250
250
350
275
375
20
µV
OP193, –40°C ≤ TA ≤ +125°C
OP293
175
100
175
125
225
15
µV
µV
OP293, –40°C ≤ TA ≤ +125°C
OP493
OP493, –40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
µV
µV
µV
Input Bias Current
IB
nA
nA
V
Input Offset Current
Input Voltage Range
Large Signal Voltage Gain
IOS
VCM
AVO
2
1
4
1
0
60
0
60
RL = 100 kΩ, 0.03 ≤ VOUT ≤ 1 V
–40°C ≤ TA ≤ +125°C
Note 1
V/mV
V/mV
µV
70
70
Long Term Offset Voltage
POWER SUPPLY
VOS
150
300
Power Supply Rejection Ratio PSRR
VS = 1.7 V to 6 V,
100
94
97
90
–40°C ≤ TA ≤ +125°C
VCM = 1.0 V, RL = ∞
–40°C ≤ TA ≤ +125°C
dB
µA
µA
V
Supply Current/Amplifier
Supply Voltage Range
ISY
VS
13.2 20
25
13.2 20
25
+2
18
+2
18
NOISE PERFORMANCE
Voltage Noise Density
Current Noise Density
Voltage Noise
en
in
en p-p
f = 1 kHz
f = 1 kHz
0.1 Hz to 10 Hz
65
0.05
3
65
0.05
3
nV/√Hz
pA/√Hz
µV p-p
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
SR
GBP
RL = 2 kΩ
10
25
10
25
V/ms
kHz
Specifications subject to change without notice.
–5–
REV. B
OP193/OP293/OP493
ABSOLUTE MAXIMUM RATINGS1
ORDERING GUIDE
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . 18 V
Output Short-Circuit Duration to Gnd . . . . . . . . . . Indefinite
Storage Temperature Range
P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
OP193/OP293/OP493E, F . . . . . . . . . . . . –40°C to +125°C
Junction Temperature Range
P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300°C
Temperature
Range
Package
Package
Option
Model
Description
OP193ES*
OP193ES-REEL*
–40°C to +125°C
–40°C to +125°C
8-Pin SOIC
8-Pin SOIC
8-Pin SOIC
8-Pin Plastic DIP
8-Pin SOIC
8-Pin SOIC
8-Pin SOIC
8-Pin SOIC
8-Pin SOIC
8-Pin SOIC
8-Pin Plastic DIP
8-Pin SOIC
8-Pin SOIC
8-Pin SOIC
16-Pin SOL
16-Pin SOL
SO-8
SO-8
SO-8
N-8
SO-8
SO-8
SO-8
SO-8
SO-8
SO-8
N-8
SO-8
SO-8
SO-8
SOL-16
SOL-16
OP193ES-REEL7* –40°C to +125°C
OP193FP*
OP193FS
OP193FS-REEL
OP193FS-REEL7
OP293ES
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
OP293ES-REEL
OP293ES-REEL7
OP293FP*
OP293FS
OP293FS-REEL
OP293FS-REEL7
OP493ES*
3
Package Type
θJA
θJC
Unit
8-Pin Plastic DIP (P)
8-Pin SOIC (S)
14-Pin Plastic DIP (P)
16-Pin SOL (S)
103
158
83
43
43
39
27
°C/W
°C/W
°C/W
°C/W
OP493ES-REEL*
OP493FP*
14-Pin Plastic DIP N-14
16-Pin SOL
16-Pin SOL
OP493FS*
SOL-16
SOL-16
OP493FS-REEL*
92
*Not for new design, obsolete April 2002.
NOTES
1Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2For supply voltages less than 18 V, the input voltage is limited to the supply
voltage.
3θJA is specified for the worst case conditions; i.e., θJA is specified for device in socket
for PDIP, and θJA is specified for device soldered in circuit board for SOIC package.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the OP193/OP293/OP493 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–6–
REV. B
Typical Performance Characteristics–OP193/OP293/OP493
200
160
120
80
150
200
160
120
80
V
T
؍
15V
V
V
T
؍
3V S
V
V
؍
3V S
S
؍
25°C ؍
0.1V A
؍
0.1V CM
؍
25°C CM
120
–40°C Յ T Յ +125°C
A
A
450
؋
PDIPS 450
؋
PDIPS 450
؋
PDIPS 90
60
40
40
0
30
0
0
–75 –60–45 –30 –15
0
15 30
60 75
45
–75 –60–45 –30 –15
0
15 30 45 60
75
0
0.2
0.4
TCV
0.6
0.8
1.0
OFFSET – V
OFFSET – V
– Vր°C
OS
TPC 1. OP193 Offset Distribution,
VS = 15 V
TPC 2. OP193 Offset Distribution,
VS = +3 V
TPC 3. OP193 TCVOS Distribution,
VS = +3 V
1
150
120
5V Յ V Յ 30V
T
؍
25°C A
S
V
؍
؎15V S
V
ϭ 5V
S
–PSRR
–40°C Յ T Յ +125°C
A
100
0
–1
–2
–3
–4
120
90
450
؋
PDIPS –40°C
80
60
40
20
0
+PSRR
+125°C
60
+25°C
30
0
0
0.2
0.4
TCV
0.6
0.8
0
1
2
3
4
5
1.0
10
100
1k
10k
COMMON-MODE VOLTAGE – V
– Vր°C
FREQUENCY – Hz
OS
TPC 4. OP193 TCVOS Distribution,
VS = 15 V
TPC 5. Input Bias Current vs.
Common-Mode Voltage
TPC 6. PSRR vs. Frequency
40
25
120
T
؍
25°C A
100
80
60
40
20
0
+ISC
S
20
V
؍
15V
30
20
10
0
+SR
؍
–SR S
V
؍
15V S
V
؍
15V | –ISC |
15V
V
؍
15
10
S
+SR
؍
–SR ؍
+5V V
S
V
؍
+5V S
5
0
+ISC
| –ISC |
؍
+5V V
؍
+5V S
V
S
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
10
100
1k
10k
FREQUENCY – Hz
TEMPERATURE – °C
TEMPERATURE – °C
TPC 7. CMRR vs. Frequency
TPC 8. Slew Rate vs. Temperature
TPC 9. Short Circuit Current vs.
Temperature
–7–
REV. B
OP193/OP293/OP493
25
20
15
10
5
0
–1
–2
–3
–4
–5
0
V
؍
18V
S
–0.5
V
؍
15V S
–0.10
V
V
؍
+2V S
V
V
؍
+2V S
؍
0.1V CM
؍
1V CM
–0.15
–0.20
–0.25
V
V
؍
+2V S
؍
0.1V CM
V
؍
15V S
0
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE – °C
TEMPERATURE – °C
TEMPERATURE – °C
TPC 10. Input Offset Current vs.
Temperature
TPC 11. Input Bias Current vs.
Temperature
TPC 12. Supply Current vs.
Temperature
1000
10000
1000
5V Յ V Յ 30V
S
5V Յ V Յ 30V
5V Յ V Յ 30V
S
S
T
؍
25°C A
T
؍
25°C T
؍
25°C A
A
1000
100
10
100
10
100
10
1
DELTA
FROM V
CC
DELTA
FROM V
EE
1
0.1
1
1
10
100
1k
0.1
1
10
100
1k
0.1
1
10
100
1000 10000
FREQUENCY – Hz
FREQUENCY – Hz
LOAD CURRENT – A
TPC 13. Voltage Noise Density vs.
Frequency
TPC 14. Current Noise Density vs.
Frequency
TPC 15. Delta Output Swing from
Either Rail vs. Current Load
1000
800
2500
2000
60
T
؍
25°C ؍
5V A
V
S
V
؍
15V
V
؍
15V
S
40
20
S
–10V Յ V
Յ +10V
–10V Յ V
Յ +10V
OUT
OUT
600
400
200
0
1500
1000
500
0
V
؍
+5V 0.03V Յ V
V
؍
+5V 0.03V Յ V
S
S
Յ 4V
Յ 4V
OUT
OUT
0
–20
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
10
100
1k
10k
100k
TEMPERATURE – °C
TEMPERATURE – °C
FREQUENCY – Hz
TPC 16. Voltage Gain
(RL = 100 kΩ) vs. Temperature
TPC 17. Voltage Gain
(RL = 10 kΩ) vs. Temperature
TPC 18. Closed-Loop Gain vs.
Frequency, VS = 5 V
–8–
REV. B
OP193/OP293/OP493
60
40
20
0
60
50
40
30
20
10
0
60
T
V
؍
25°C V
A
؍
5V T ؍
25°C ؍
1 V
؍
5V A
S
A
S
+OS
؍
|
–OS
|
؍
15V
S
V
PHASE
R
؍
50k⍀ 50mV Յ V Յ 150mV
LOADS TO GND
L
IN
40
20
90
45
GAIN
+OS
R
؍
ؕ
L
0
0
–45
–90
–20
–40
+OS
؍
|
–OS
|
R
؍
10k⍀ –OS
L
R
؍
ؕ
L
–20
10
10
100
1000
10000
100
1k
10k
100k
100
1k
10k
100k
1M
FREQUENCY – Hz
CAPACITIVE LOAD – pF
FREQUENCY – Hz
TPC 19. Closed-Loop Gain vs.
Frequency, VS = 15 V
TPC 20. Small Signal Overshoot
vs. Capacitive Load
TPC 21. Open-Loop, Gain and
Phase vs. Frequency
V+
60
V
؍
15V S
I
1
I
2
I
3
I4
+INPUT
40
20
90
45
0
2k⍀
2k⍀
PHASE
Q5
Q1
Q2
–INPUT
Q6
GAIN
0
OP293,
Q4
OP493
ONLY
Q3
TO
OUTPUT
STAGE
Q7
–20
–40
–45
Q8
D1
–90
R1
R2
A
A
100
1k
10k
100k
1M
FREQUENCY – Hz
I
5
I6
TPC 22. Open-Loop, Gain and
Phase vs. Frequency
R1
R2
B
B
V–
NULLING
TERMINALS
(OP193 ONLY)
FUNCTIONAL DESCRIPTION
Figure 1. OP193/OP293/OP493 Equivalent Input Circuit
The OP193 family of operational amplifiers are single-supply,
micropower, precision amplifiers whose input and output ranges
both include ground. Input offset voltage (VOS) is only 75 µV
maximum, while the output will deliver 5 mA to a load. Sup-
ply current is only 17 µA.
V+
Q4
FROM
INPUT
STAGE
A simplified schematic of the input stage is shown in Figure 1.
Input transistors Q1 and Q2 are PNP devices, which permit the
inputs to operate down to ground potential. The input transis-
tors have resistors in series with the base terminals to protect the
junctions from over voltage conditions. The second stage is an
NPN cascode which is buffered by an emitter follower before
driving the final PNP gain stage.
Q1
Q5
OUTPUT
Q3
Q2
I
2
I
3
I1
V–
The OP193 includes connections to taps on the input load
resistors, which can be used to null the input offset voltage, VOS
.
Figure 2. OP193/OP293/OP493 Equivalent Output Circuit
The OP293 and OP493 have two additional transistors, Q7 and
Q8. The behavior of these transistors is discussed in the Output
Phase Reversal section of this data sheet.
By operating as an emitter follower, Q1 offers a high impedance
load to the final PNP collector of the input stage. Base drive to
Q2 is derived by monitoring Q1’s collector current. Transistor
Q5 tracks the collector current of Q1. When Q1 is on, Q5 keeps
Q4 off, and current source I1 keeps Q2 turned off. When Q1 is
driven to cutoff (i.e., the output must move toward V–), Q5
allows Q4 to turn on. Q4’s collector current then provides the
base drive for Q3 and Q2, and the output low voltage swing is
set by Q2’s VCE,SAT which is about 5 mV.
The output stage, shown in Figure 2, is a noninverting NPN
“totem-pole” configuration. Current is sourced to the load by
emitter follower Q1, while Q2 provides current sink capability.
When Q2 saturates, the output is pulled to within 5 mV of
ground without an external pull-down resistor. The totem-pole
output stage will supply a minimum of 5 mA to an external
load, even when operating from a single 3.0 V power supply.
REV. B
–9–
OP193/OP293/OP493
Driving Capacitive Loads
weight, and high energy density relative to older primary cells.
Most lithium cells have a nominal output voltage of 3 V and are
noted for a flat discharge characteristic. The low supply voltage
requirement of the OP193, combined with the flat discharge
characteristic of the lithium cell, indicates that the OP193 can
be operated over the entire useful life of the cell. Figure 3 shows
the typical discharge characteristic of a 1 AH lithium cell power-
ing the OP193, OP293, and OP493, with each amplifier, in
turn, driving 2.1 Volts into a 100 kΩ load.
OP193 family amplifiers are unconditionally stable with capacitive
loads less than 200 pF. However, the small signal, unity-gain
overshoot will improve if a resistive load is added. For example,
transient overshoot is 20% when driving a 1000 pF/ 10 kΩ load.
When driving large capacitive loads in unity-gain configurations,
an in-the-loop compensation technique is recommended as
illustrated in Figure 6.
Input Overvoltage Protection
As previously mentioned, the OP193 family of op amps use a
PNP input stage with protection resistors in series with the
inverting and noninverting inputs. The high breakdown of the
PNP transistors, coupled with the protection resistors, provides
a large amount of input protection from over voltage conditions.
The inputs can therefore be taken 20 V beyond either supply
without damaging the amplifier.
4
3
2
Output Phase Reversal—OP193
OP193
OP493
OP293
The OP193’s input PNP collector-base junction can be forward-
biased if the inputs are brought more than one diode drop (0.7 V)
below ground. When this happens to the noninverting input, Q4
of the cascode stage turns on and the output goes high. If the
positive input signal can go below ground, phase reversal can be
prevented by clamping the input to the negative supply (i.e.,
GND) with a diode. The reverse leakage of the diode will, of
course, add to the input bias current of the amplifier. If input bias
current is not critical, a 1N914 will add less than 10 nA of leak-
age. However, its leakage current will double for every 10°C
increase in ambient temperature. For critical applications, the
collector-base junction of a 2N3906 transistor will add only about
10 pA of additional bias current. To limit the current through the
diode under fault conditions, a 1 kΩ resistor is recommended in
series with the input. (The OP193’s internal current limiting
resistors will not protect the external diode.)
1
0
0
1000
2000
3000
4000
5000
6000
7000
HOURS
Figure 3. Lithium Sulfur Dioxide Cell Discharge Character-
istic with OP193 Family and 100 kΩ Loads
Input Offset Voltage Nulling
The OP193 provides two offset nulling terminals that can be
used to adjust the OP193’s internal VOS. In general, operational
amplifier terminals should never be used to adjust system offset
voltages. The offset null circuit of Figure 4 provides about
7 mV of offset adjustment range. A 100 kΩ resistor placed in
series with the wiper arm of the offset null potentiometer, as
shown in Figure 5, reduces the offset adjustment range to 400 µV
and is recommended for applications requiring high null resolu-
tion. Offset nulling does not adversely affect TCVOS performance,
providing that the trimming potentiometer temperature coeffi-
cient does not exceed 100 ppm/°C.
Output Phase Reversal—OP293 and OP493
The OP293 and OP493 include lateral PNP transistors Q7 and
Q8 to protect against phase reversal. If an input is brought more
than one diode drop (≈0.7 V) below ground, Q7 and Q8 com-
bine to level shift the entire cascode stage, including the bias to
Q3 and Q4, simultaneously. In this case Q4 will not saturate
and the output remains low.
V+
The OP293 and OP493 do not exhibit output phase reversal for
inputs up to –5 V below V– at +25°C. The phase reversal limit
at +125°C is about –3 V. If the inputs can be driven below these
levels, an external clamp diode, as discussed in the previous
section, should be added.
7
2
6
OP193
4
3
Battery-Powered Applications
5
1
OP193 series op amps can be operated on a minimum supply
voltage of 1.7 V, and draw only 13 µA of supply current per
amplifier from a 2.0 V supply. In many battery-powered circuits,
OP193 devices can be continuously operated for thousands of
hours before requiring battery replacement, thus reducing
equipment downtime and operating cost.
100k⍀
V–
Figure 4. Offset Nulling Circuit
High performance portable equipment and instruments fre-
quently use lithium cells because of their long shelf life, light
–10–
REV. B
OP193/OP293/OP493
V+
V+
R1
240k⍀
R2
1.5M⍀
(2.5V TO 36V)
7
2
3
7
C1
1000pF
2
6
OP193
6
OP193
4
V
OUT
5
5
3
(1.23V @ 25°C)
1
4
100k⍀
100k⍀
MAT-01AH
Q1
6
1
3
7
5
V–
2
Q2
Figure 5. High Resolution Offset Nulling Circuit
V
V
BE2
BE1
A Micropower False-Ground Generator
Some single-supply circuits work best when inputs are biased
above ground, typically at 1/2 of the supply voltage. In these
cases a false ground can be created by using a voltage divider
buffered by an amplifier. One such circuit is shown in Figure 6.
V1
R3 68k⍀
⌬V
BE
R4
130k⍀
R5 20k⍀
OUTPUT
ADJUST
This circuit will generate a false-ground reference at 1/2 of the
supply voltage, while drawing only about 27 µA from a 5 V supply.
The circuit includes compensation to allow for a 1 µF bypass
capacitor at the false-ground output. The benefit of a large
capacitor is that not only does the false ground present a very low
dc resistance to the load, but its ac impedance is low as well. The
OP193 can both sink and source more than 5 mA, which improves
recovery time from transients in the load current.
Figure 7. A Battery-Powered Voltage Reference
A Single-Supply Current Monitor
Current monitoring essentially consists of amplifying the voltage
drop across a resistor placed in series with the current to be
measured. The difficulty is that only small voltage drops can be
tolerated, and with low precision op amps this greatly limits the
overall resolution. The single-supply current monitor of Figure
8 has a resolution of 10 µA and is capable of monitoring 30 mA
of current. This range can be adjusted by changing the current
sense resistor R1. When measuring total system current, it may
be necessary to include the supply current of the current moni-
tor, which bypasses the current sense resistor, in the final result.
This current can be measured and calibrated (together with the
residual offset) by adjustment of the offset trim potentiometer,
R2. This produces a deliberate temperature dependent offset.
However, the supply current of the OP193 is also proportional
to temperature, and the two effects tend to track. Current in R4
and R5, which also bypasses R1, can be adjusted via a gain trim.
5V OR 12V
10k⍀
0.022F
240k⍀
7
2
100⍀
2.5V OR 6V
6
OP193
3
4
1F
1F
240k⍀
Figure 6. A Micropower False-Ground Generator
V+
A Battery-Powered Voltage Reference
The circuit of Figure 7 is a battery-powered voltage reference
that draws only 17 µA of supply current. At this level, two AA
alkaline cells can power this reference for more than 18 months.
At an output voltage of 1.23 V @ 25°C, drift of the reference is
only 5.5 µV/°C over the industrial temperature range. Load
regulation is 85 µV/mA with line regulation at 120 µV/V.
TO CIRCUIT
UNDER TEST
7
3
6
OP193
I
TEST
V
OUT =
4
2
100mV/mA(I
)
TEST
5
1
Design of the reference is based on the Brokaw bandgap core
technique. Scaling of resistors R1 and R2 produces unequal
currents in Q1 and Q2. The resulting ∆VBE across R3 creates a
temperature-proportional voltage (PTAT) which, in turn, pro-
duces a larger temperature-proportional voltage across R4 and
R5, V1. The temperature coefficient of V1 cancels (first order)
the complementary to absolute temperature (CTAT) coefficient
of VBE1. When adjusted to 1.23 V @ 25°C, output voltage
tempco is at a minimum. Bandgap references can have start-up
problems. With no current in R1 and R2, the OP193 is beyond
its positive input range limit and has an undefined output state.
Shorting Pin 5 (an offset adjust pin) to ground forces the output
high under these circumstances and ensures reliable startup
without significantly degrading the OP193’s offset drift.
R2
9.9k⍀
R2
100k⍀
R1
1⍀
R3
100k⍀
R5
100⍀
Figure 8. Single-Supply Current Monitor
REV. B
–11–
OP193/OP293/OP493
A Single-Supply Instrumentation Amplifier
R1
20k⍀
R2
1.98M⍀
Designing a true single-supply instrumentation amplifier with
zero-input and zero-output operation requires special care.
The traditional configuration, shown in Figure 9, depends upon
amplifier A1’s output being at 0 V when the applied common-
mode input voltage is at 0 V. Any error at the output is multiplied
by the gain of A2. In addition, current flows through resistor R3
as A2’s output voltage increases. A1’s output must remain at 0 V
while sinking the current through R3, or a gain error will result.
With a maximum output voltage of 4 V, the current through R3
is only 2 µA, but this will still produce an appreciable error.
5V
R3
20k⍀
R4
1.98M⍀
V+
A1
1/2 OP293
–IN
V–
5V
10k⍀
5V
Q2
Q1
VN2222
V+
A2
V
OUT
1/2 OP293
R1
20k⍀
R2
1.98M⍀
+IN
V–
5V
R3
20k⍀
R4
1.98M⍀
Figure 10. An Improved Single-Supply, 0 VIN, 0 VOUT
Instrumentation Amplifier
V+
A1
1/2 OP293
5V
–IN
V–
A Low-Power, Temperature to 4–20 mA Transmitter
A simple temperature to 4–20 mA transmitter is shown in Fig-
ure 11. After calibration, this transmitter is accurate to 0.5°C
over the –50°C to +150°C temperature range. The transmitter
operates from 8 V to 40 V with supply rejection better than
3 ppm/V. One half of the OP293 is used to buffer the VTEMP
pin, while the other half regulates the output current to satisfy
the current summation at its noninverting input:
I
SINK
V+
V
OUT
A2
1/2 OP293
+IN
V–
Figure 9. A Conventional Instrumentation Amplifier
One solution to this problem is to use a pull-down resistor. For
example, if R3 = 20 kΩ, then the pull-down resistor must be
less than 400 Ω. However, the pull-down resistor appears as a
fixed load when a common-mode voltage is applied. With a 4 V
common-mode voltage, the additional load current will be 10 mA,
which is unacceptable in a low power application.
VTEMP × R6 + R7
(
)
− V
R2 + R6 + R7
R2 × R10
SET
IOUT
+
R2 × R10
The change in output current with temperature is the derivative
of the transfer function:
Figure 10 shows a better solution. A1’s sink current is provided
by a pair of N-channel FET transistors, configured as a current
mirror. With the values shown, sink current of Q2 is about
340 µA. Thus, with a common-mode voltage of 4 V, the addi-
tional load current is limited to 340 µA versus 10 mA with a
400 Ω resistor.
∆VTEMP
R6 + R7
(
)
∆IOUT
∆T
∆T
R2 × R10
=
1N4002
V+
8V TO 40V
SPAN TRIM
R6
3k⍀
R4
20k⍀
REF-43BZ
R7
2
3
R2
V
2
6
3
4
IN
8
1/2 OP293
4
5k⍀
1k⍀
V
1
TEMP
6
R8
1k⍀
V
OUT
7
2N1711
1/2 OP293
V
TEMP
R3
100k⍀
V
R1 10k⍀
SET
R5
5k⍀
5
R9
100k⍀
GND
ZERO
TRIM
R10
100⍀
1%, 1/2 W
ALL RESISTORS 1/4W, 5% UNLESS OTHERWISE NOTED
I
OUT
R
LOAD
Figure 11. Temperature to 4–20 mA Transmitter
–12–
REV. B
OP193/OP293/OP493
C1
From the formulas, it can be seen that if the span trim is
adjusted before the zero trim, the two trims are not interactive,
which greatly simplifies the calibration procedure.
5V
75nF
R5
5V
R1
200k⍀
200k⍀
2
3
8
Calibration of the transmitter is simple. First, the slope of the
output current versus temperature is calibrated by adjusting the
span trim, R7. A couple of iterations may be required to be sure
the slope is correct.
V
CONTROL
A1
1
6
SQUARE
OUT
1/2 OP293
A2
1/2 OP293
7
4
R2
200k⍀
5
R4
R3
100k⍀
TRIANGLE
OUT
Once the span trim has been completed, the zero trim can be made.
Remember that adjusting the zero trim will not affect the gain.
200k⍀
R7
200k⍀
R6
200k⍀
The zero trim can be set at any known temperature by adjusting
R5 until the output current equals:
R8
200k⍀
5V
∆IFS
OPERATING
IOUT
=
T
(
− TMIN + 4 mA
)
AMBIENT
CD4066
∆T
1
2
3
4
5
6
7
IN/OUT
OUT/IN
OUT/IN
IN/OUT
CONT
14
V
5V
DD
S1
Table I shows the values of R6 required for various temperature
ranges.
CONT 13
CONT 12
IN/OUT 11
OUT/IN 10
S2
Table I. R6 Values vs. Temperature
Temp Range
R6
0°C to 70°C
–40°C to +85°C
–55°C to +150°C
10 kΩ
6.2 kΩ
3 kΩ
S3
S4
CONT
OUT/IN
IN/OUT
9
8
5V
A Micropower Voltage Controlled Oscillator
V
An OP293 in combination with an inexpensive quad CMOS
analog switch forms the precision VCO of Figure 12. This cir-
cuit provides triangle and square wave outputs and draws only
50 µA from a single 5 V supply. A1 acts as an integrator; S1
switches the charging current symmetrically to yield positive and
negative ramps. The integrator is bounded by A2 which acts as
a Schmitt trigger with a precise hysteresis of 1.67 volts, set by
resistors R5, R6, and R7, and associated CMOS switches. The
resulting output of A1 is a triangle wave with upper and lower
levels of 3.33 and 1.67 volts. The output of A2 is a square wave
with almost rail-to-rail swing. With the components shown,
frequency of operation is given by the equation:
SS
Figure 12. Micropower Voltage Controlled Oscillator
A Micropower, Single-Supply Quad Voltage Output 8-Bit DAC
The circuit of Figure 13 uses the DAC8408 CMOS quad 8-bit
DAC and the OP493 to form a single-supply quad voltage out-
put DAC with a supply drain of only 140 µA. The DAC8408 is
used in the voltage switching mode and each DAC has an out-
put resistance (≈10 kΩ) independent of the digital input code.
The output amplifiers act as buffers to avoid loading the DACs.
The 100 kΩ resistors ensure that the OP493 outputs will swing
to within 1/2 LSB of ground, i.e.:
fOUT = VCONTROL V ×10 Hz / V
but this can easily be changed by varying C1. The circuit oper-
ates well up to 500 Hz.
1
2
1.23 V
256
×
= 3 mV
REV. B
–13–
OP193/OP293/OP493
5V
5V
A Single-Supply Micropower Quad Programmable-Gain
Amplifier
3.6k⍀
The combination of the quad OP493 and the DAC8408 quad
8-bit CMOS DAC creates a quad programmable-gain amplifier
with a quiescent supply drain of only 140 µA (Figure 14). The
digital code present at the DAC, which is easily set by a micro-
processor, determines the ratio between the fixed DAC feedback
resistor and the resistance that the DAC feedback ladder pre-
sents to the op amp feedback loop. The gain of each amplifier is:
4
5V
AD589
1.23V
1
2
3
V
DD
V
A
OUT
A
1
I
OUT1A
4
1/4 OP493
DAC A
1/4
DAC8408
V
REF
A
2
11
R1
100k⍀
VOUT
VIN
256
=
n
I
5
6
OUT2A/2B
6
V
B
OUT
where n equals the decimal equivalent of the 8-bit digital code
B
7
14
8
1/4 OP493
present at the DAC.
V
REF
B
DAC B
1/4
8
5
R2
100k⍀
I
OUT1B
DAC8408
If the digital code present at the DAC consists of all zeros, the
feedback loop will be open causing the op amp to saturate. The
10 MΩ resistors placed in parallel with the DAC feedback loop
eliminates this problem with a very small reduction in gain
accuracy. The 2.5 V reference biases the amplifiers to the center
of the linear region providing maximum output swing.
13
12
V
C
OUT
C
I
25 OUT1C
1/4 OP493
DAC C
1/4
DAC8408
V
REF
C
27
R3
100k⍀
I
OUT2C/2D
24
23
9
V
D
OUT
D
1/4 OP493
DAC D
1/4
DAC8408
V
REF
D
21
10
R4
100k⍀
I
OUT1D
OP493
DAC DATA BUS
PINS 9(LSB)–16(MSB)
17
18
19
20
A/B
R/W
DS1
DS2
DIGITAL
CONTROL
SIGNALS
DAC8408ET
DGND
28
Figure 13. Micropower Single-Supply Quad Voltage-
Output 8-Bit DAC
–14–
REV. B
OP193/OP293/OP493
1
V
C1
0.1F
DD
5V
R
A
3
FB
4
V
A
IN
V
A
2
4
REF
R1
10M⍀
I
OUT1A
2
3
DAC A
1/4
DAC8408
A
1
V
A
OUT
1/4 OP493
I
11
OUT2A/2B
5
8
C2
0.1F
R
B
7
FB
V
B
IN
V
B
REF
R2
10M⍀
DAC B
1/4
DAC8408
I
OUT1B
6
5
6
B
7
V
B
OUT
1/4 OP493
C3
0.1F
R
C
26
FB
V
C
IN
V
C
REF
27
25
R3
10M⍀
I
OUT1C
9
DAC C
1/4
DAC8408
C
8
V
C
1/4 OP493
OUT
10
I
OUT2C/2D
24
21
C4
0.1F
R
D
22
FB
V
D
IN
V
D
REF
R4
10M⍀
DAC D
1/4
DAC8408
I
OUT1D
23
13
12
D
14
V
D
1/4 OP493
OUT
DAC DATA BUS
PINS 9(LSB)–16(MSB)
OP493
17
18
19
20
A/B
R/W
DS1
DS2
DIGITAL
CONTROL
SIGNALS
2.5V
REFERENCE
VOLTAGE
DAC8408ET
DGND
28
Figure 14. Single-Supply Micropower Quad Programmable-Gain Amplifier
REV. B
–15–
OP193/OP293/OP493
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Epoxy DIP
(P Suffix)
8-Lead SO
(S Suffix)
8
5
0.280 (7.11)
0.240 (6.10)
8
1
5
PIN 1
0.1574 (4.00)
0.1497 (3.80)
1
4
PIN 1
0.2440 (6.20)
0.2284 (5.80)
4
0.325 (8.25)
0.300 (7.62)
0.430 (10.92)
0.348 (8.84)
0.1968 (5.00)
0.1890 (4.80)
0.0196 (0.50)
0.0099 (0.25)
0.060 (1.52)
0.015 (0.38)
0.195 (4.95)
0.115 (2.93)
x 45°
0.210
(5.33)
MAX
0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0040 (0.10)
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
8
0
°
°
0.0500 (1.27)
0.0160 (0.41)
0.0192 (0.49)
0.0138 (0.35)
0.0500
(1.27)
BSC
0.0098 (0.25)
0.0075 (0.19)
SEATING
PLANE
0.100
(2.54)
BSC
0.070 (1.77)
0.045 (1.15)
0.022 (0.558)
0.014 (0.356)
16-Lead Wide Body SOL
(S Suffix)
14-Lead Epoxy DIP
(P Suffix)
14
8
0.280 (7.11)
0.240 (6.10)
9
16
PIN 1
1
0.2992 (7.60)
0.2914 (7.40)
7
0.325 (8.25)
0.300 (7.62)
0.795 (20.19)
0.725 (18.42)
0.4193 (10.65)
0.3937 (10.00)
8
PIN 1
1
0.060 (1.52)
0.015 (0.38)
0.195 (4.95)
0.115 (2.93)
0.210
(5.33)
MAX
0.130
(3.30)
MIN
0.015 (0.381)
0.008 (0.204)
0.160 (4.06)
0.115 (2.93)
0.1043 (2.65)
0.0926 (2.35)
0.4133 (10.50)
0.3977 (10.00)
0.0291 (0.74)
0.0098 (0.25)
x 45°
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
0.0500 (1.27)
0.0157 (0.40)
8
0
°
°
0.0118 (0.30)
0.0040 (0.10)
0.0500 (1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0125 (0.32)
0.0091 (0.23)
Revision History
Location
Page
Data Sheet changed from REV. A to REV. B.
Deletion of WAFER TEST LIMITS Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Deletion of DICE CHARACTERISTICS Images . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
–16–
REV. B
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