OP215FZ [ADI]
IC DUAL OP-AMP, 2000 uV OFFSET-MAX, 5.7 MHz BAND WIDTH, CDIP8, HERMETIC SEALED, CERDIP-8, Operational Amplifier;
| 型号： | OP215FZ |
| 厂家： | 
ADI |
| 描述： | IC DUAL OP-AMP, 2000 uV OFFSET-MAX, 5.7 MHz BAND WIDTH, CDIP8, HERMETIC SEALED, CERDIP-8, Operational Amplifier 放大器 CD |
| 文件： | 总8页 (文件大小：157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual Precision JFET-Input
Operational Amplifier
a
OP215
FEATURES
High Slew Rate: 10 V/ꢀs Min
Fast Settling Time: 0.9 ꢀs to 0.1% Type
Low Input Offset Voltage Drift: 10 ꢀV/ꢁC Max
Wide Bandwidth: 3.5 MHz Min
Temperature-Compensated Input Bias Currents
Guaranteed Input Bias Current: 18 nA Max (125ꢁC)
Bias Current Specified Warmed Up over Temperature
Low Input Noise Current: 0.01 pA/÷Hz Type
High Common-Mode Rejection Ratio 86 dB Min
Pin Compatible with Standard Dual Pinouts
Models with MIL-STD-883 Class B Processing Available
GENERAL DESCRIPTION
at elevated temperature. Thus, the OP215 features an input bias
current of 1.4 nA at 70∞C ambient (not junction) temperature
which greatly extends the application usefulness of this device.
The OP215 offers the proven JFET-input performance advantages
of high speed and low input bias current with the tracking and
convenience advantages of a dual op amp configuration.
Applications include high-speed amplifiers for current output
DACs, active filters, sample-and-hold buffers, and photocell
amplifiers. For additional precision JFET op amps, see the
OP249 and AD712 data sheets.
Low input offset voltages, low input currents, and low drift are
featured in these high-speed amplifiers.
On-chip zener-zap trimming is used to achieve low VOS, while a
bias-current compensation scheme gives a low input bias current
V+
NOTE
Q10
J5
Q5
R8
R7
Q1
R7, R8 ARE ELECTRONICALLY ADJUSTED
NULL
Q7
NULL
Q6
ON-CHIP FOR MINIMUM OFFSET VOLTAGE
Q9
J8 J7
Q19
R3
J6
Q24
R1
Q8
C2
R2
J1
J3
J2
Q17
NOMINV
INPUT+
J11
R13
Q22
Q25
–INV
7.4pF
Q2
INPUT
Q3
Q4
OUTPUT
R10
Q12
Q18
J10
Q23
R6
R5
3.6
kꢂ
3.6kꢂ
Q14
Q11
R4
C1
Q13
J9
Q21
R9
J4
Q15
Q20
7.4
pF
Q16
R11
R12
V–
Figure 1. Simplified Schematic (1/2 OP215)
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
OP215–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (at V = ±15 V, T = 25ꢁC, unless otherwise noted.)
S
A
OP215E
Type
OP215G
Type
Parameter
Symbol
Conditions
Min
Max
Min
Max
Unit
Input Offset Voltage
VOS
RS = 50 W
‘G’ Grade
0.2
1.0
2.0
2.5
4.0
6.0
mV
mV
Input Offset Current1
Input Bias Current1
Input Resistance
IOS
IB
Tj = 25∞C
3
5
50
100
3
5
100
200
pA
pA
Device Operating
Tj = 25∞C
Device Operating
± 15
± 18
101,2
± 100
± 300
± 15
± 18
101,2
± 300
± 600
pA
pA
RIN
W
Large-Signal Voltage
Gain
AVO
RL Ն 2 kW,
VO = ± 10 V
150
500
50
200
V/mV
Output Voltage Swing
Supply Current
Slew Rate
VO
ISY
RL = 10 kW
RL = 2 kW
± 12
± 11
± 13
± 12
± 11
± 13
V
V
± 12.7
± 12.7
6.0
8.5
7.0
7.0
10.0
12.0
mA
mA
‘G’ Grade
AVCL = 1
SR
10
18
5
15
V/s
Gain Bandwidth
Product3
GBW
3.5
5.7
3.0
5.4
MHz
Closed-Loop Bandwidth CLBW
AVCL = 1
13
12
MHz
Setting Time
tS
To 0.01%
To 0.05%2
To 0.10%
2.3
1.1
0.9
2.4
1.2
1.0
s
s
s
Input Voltage Range
IVR
10.2
–10.2
14.8
–11.5
10.1
–10.1
14.8
–11.5
V
V
Common-Mode
Rejection Ratio
CMRR
VCM = ± IVR
82
100
10
80
96
dB
E, G Grades
Power Supply Rejection PSRR
Ratio
VS = ± 10 V to ± 16 V
VS = ± 10 V to ± 15 V
51
V/V
V/V
16
100
Input Noise Voltage
Density
n
fO = 100 Hz
fO = 1,000 Hz
20
15
20
15
nV/÷Hz
nV/÷Hz
Input Noise Current
Density
In
fO = 100 Hz
fO = 1,000 Hz
0.01
0.01
0.01
0.01
pA/÷Hz
pA/÷Hz
Input Capacitance
CIN
3
3
pF
NOTES
1Input bias current is specified for two different conditions. The Tj = 25∞C specification is with the junction at ambient temperature; the device operating specification is
with the device operating in a warmed up condition at 25∞C ambient. The warmed up bias-current value is correlated to the junction temperature value via the curves
of IS versus Tj and IS versus TA. PMI has a bias-current compensation circuit that gives improved bias current and bias current over temperature versus standard
JFET input op amps. IS and IOS are measured at VCM = 0.
2Setting time is defined here for a unity gain inverter connection using 2 kW resistors. It is the time required for the error voltage (the voltage at the inverting input pin
on the amplifier) to settle to within a specified percent of its final value from the time a 10 V step input is applied to the inverter. See setting time test circuit.
3Sample tested.
Specifications are subject to change without notice.
–2–
REV. A
OP215
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (at V = ±15 V, 0ꢁC Յ T Յ 70ꢁC for E Grade, –40ꢁC Յ T Յ +85ꢁC for G Grade, unless
otherwise noted.)
S
A
A
OP215E
Type
OP215G
Type
Parameter
Symbol
Conditions
Min
Max
Min
Max
Unit
Input Offset Voltage
VOS
RS = 50 W
0.4
1.65
3.5
8.0
mV
Average Input Offset
Voltage Drift
Without External Trim1 TCVOS
3
3
15
6
4
V/∞C
V/∞C
With External Trim
TCVOSn
RP = 100 kW
Input Offset Current2
IOS
Tj = 70∞C
0.06
0.08
0.45
0.80
0.08
0.10
0.65
1.2
nA
nA
TA = 70∞C
Device Operating
Input Bias Current2
Input Voltage Range
IS
Tj = 70∞C
± 0.12 ± 0.70
± 0.16 ± 1.40
± 0.14 ± 0.9
± 0.19 ± 1.8
nA
nA
TA = 70∞C
Device Operating
IVR
10.2
–10.2
14.7
–11.4
10.1
–10.1
14.7
–11.3
V
V
Common-Mode
Rejection Ratio
CMRR
VCM = ± IVR
80
98
76
94
dB
Power Supply Rejection PSRR
Ratio
VS = ± 10 V to ± 16 V
VS = ± 10 V to ± 15 V
13
100
20
159
V/V
Large-Signal
Voltage Gain
AVO
RL Ն 2 kW
50
180
± 13
35
130
V/mV
VO = ± 10 V
Output Voltage Swing
VO
RL Ն 10 kW
± 12
± 12
± 13
V
NOTES
1Sample tested.
2Input bias current is specified for two different conditions. The Tj = 25∞C specification is with the junction at ambient temperature; the Device Operating specification is
with the device operating in a warmed up condition at 25∞C ambient. The warmed up bias-current value is correlated to the junction temperature value via the curves
of IS versus Tj and IS versus TA. PMI has a bias-current compensation circuit that gives improved bias current and bias current over temperature versus standard
JFET input op amps. IS and IOS are measured at VCM = 0.
Specifications are subject to change without notice.
–3–
REV. A
OP215
ABSOLUTE MAXIMUM RATINGS1
Supply Voltage
OP215E, OP215G . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Operating Temperature Range
Package Type
ꢃJA
*
ꢃJC
Unit
8-Lead Hermetic DIP (Z)
8-Lead Plastic DIP (P)
134
96
12
37
∞C/W
∞C/W
OP215E . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0∞C to +70∞C
OP215G . . . . . . . . . . . . . . . . . . . . . . . . . . . –40∞C to +85∞C
Maximum Junction Temperature (Tj) . . . . . . . . . . . . . . 150∞C
Differential Input Voltage
*JA is specified for worst-case mounting conditions, i.e., JA is specified for
device in socket for CerDIP and P-DIP packages.
OP215E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 40 V
OP215G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 30 V
Input Voltage2
OP215E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 V
OP215G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 16 V
Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . 300∞C
Junction Temperature (Tj) . . . . . . . . . . . . . –65∞C to +150∞C
PIN CONFIGURATION
OUT A
–IN A
+IN A
V–
1
2
3
4
V+
8
7
6
5
A
B
OUT B
–IN B
+IN B
–
–
+
+
NOTES
1Absolute maximum ratings apply to packaged parts, unless otherwise noted.
2Unless otherwise specified, the absolute maximum negative input voltage is equal
to one volt more positive than the negative power supply voltage.
ORDERING INFORMATION1
Package
Type
Temperature
Range
TA = 25∞C,
VOS Max (mV)
Model
OP215EZ2
OP215GP2
8-Lead CerDIP
COM
1.0
6.0
8-Lead Plastic DIP
XIND
For military processed devices, please refer to the standard microcircuit drawing
(SMD) available at www.dscc.dla.mil/programs/milspec/default.asp
SMD Part Number
ADI Equivalent
5962-8853801GA2
5962-8853801PA
5962-8838032A2
OP215AJMDA
OP215AZMDA
OP215BRCMDA
NOTES
1Burn-in is available on commercial and industrial temperature range parts in CerDIP and plastic
DIP packages.
2Not for new design, obsolete April 2002.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the OP215 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. A
Typical Performance Characteristics–OP215
10
V
T
= ꢄ15V
= 25ꢁC
= –1
S
A
500ns
100ns
A
V
100
90
100
90
5
0
10mV
5mV
1mV
10
10
10mV
0.5
5mV
1.0
1mV
–5
0%
0%
5V
20mV
–10
0
1.5
2.0
2.5
SETTLINGTIME – ꢀs
TPC 1. Large-Signal Transient
Response
TPC 2. Small-Signal Transient
Response
TPC 3. Settling Time
90
100
110
120
130
140
150
160
170
28
120
100
80
18
16
14
12
10
V
T
= ꢄ15V
= 25ꢁC
S
A
V
= ꢄ15V
S
PHASE MARGIN = 66ꢁ
24
20
16
12
8
BANDWIDTHVARIATION FROM
ꢄ5 <V < ꢄ20V IS < 5%
S
8
CLOSED-LOOP
BANDWIDTH A = ꢅ1
60
6
V
A
> 10
4
2
0
V
40
GAIN BANDWIDTH
PRODUCT
180
190
20
–2
–4
200
0
4
A = 1
V
V
= ꢄ15V
= 25ꢁC
S
A
–6
T
–8
-20
0
–10
1
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY – Hz
–50 –25
0
25
50
75
100 125
1M
10M
FREQUENCY – Hz
100M
TEMPERATURE – ꢁC
TPC 6. Open-Loop Frequency
Response
TPC 5. Bandwidth vs. Temperature
TPC 4. Closed-Loop Bandwidth and
Phase Shift vs. Frequency
100
80
60
40
20
0
28
70
V
T
= ꢄ15V
= 25ꢁC
= ꢅ1
A
V
= ꢅ1
V
T
= ꢄ15V
= 25ꢁC
S
A
V
S
S
A
= ꢄ15V
60
50
40
30
20
10
0
24
20
16
12
8
A
V
NEGATIVE
POSITIVE
4
0
–50 –25
0
25
50
75
100 125
1
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY– Hz
100K
1M
10M
AMBIENTTEMPERATURE – ꢁC
FREQUENCY – Hz
TPC 9. Common-Mode Rejection
Ratio vs. Frequency
TPC 7. Maximum Output Swing vs.
Frequency
TPC 8. Slew Rate vs. Temperature
–5–
REV. A
OP215
120
110
100
90
140
120
100
80
100
10
V
T
= ꢄ15V
= 25ꢁC
V
T
= ꢄ15V
= 25ꢁC
T
= 25ꢁC
S
A
S
S
A
A
= 100
V
POSITIVE
SUPPLY
80
NEGATIVE
SUPPLY
70
60
50
40
30
20
10
0
60
A
= 10
V
1
40
1/f CORNER
FREQUENCY
A
= 1
20
V
0
0.1
1
10
100
1k
10k
10
100
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
FREQUENCY – Hz
TPC 10. Power Supply Rejection vs.
Frequency
TPC 12. Voltage Noise Density vs.
Frequency
TPC 11. Output Impedance vs.
Frequency
BASIC CONNECTIONS
V+
2kꢂ 0.1%
Rp
100kꢂ
+15V
8
2kꢂ 0.1%
2
3
–IN
1
OP215
A
2N4416
5kꢂ
0.1%
OP215
OUT A
10V
0
A
100pF
+IN
4
V
–15V
OUT
SUMMING
MODE
3kꢂ
V–
5kꢂ 0.1%
A
= –1
V
NOTE
SCOPE
V
CAN BE TRIMMED WITH POTENTIOMETERS RANGING FROM
OS
2N4416
+15V
10 kꢂ TO 1 Mꢂ. FOR MOST UNITS TCV WILL BE MINIMUM WHEN
OS
V
IS ADJUSTED WITH A 100kꢂ POTENTIOMETER.
OS
2kꢂ
Figure 4. Input Offset Voltage Nulling
Figure 2. Settling Time Test Circuit
+15V
+5V
0V
2
3
8
1
OP215
V
OUT
A
–5V
V
IN
4
2kꢂ
100pF
–15V
Figure 3. Slew Rate Test Circuit
–6–
REV. A
OP215
BASIC CONNECTIONS
APPLICATIONS INFORMATION
Dynamic Operating Considerations
+15V
8
As with most amplifiers, care should be taken with lead dress,
component placement, and supply de-coupling in order to ensure
stability. For example, resistors from the output to an input should
be placed with the body close to the input to minimize “pick up”
and maximize the frequency of the feedback pole by minimizing
the capacitance from the input to ground.
100kꢂ
200ꢂ
6
5
7
1
OP215
B
A feedback pole is created when the feedback around any amplifier
is resistive. The parallel resistance and capacitance from the
input of the device (usually the inverting input) to ac ground
sets the frequency of the pole. In many instances, the frequency
of this pole is much greater than the expected 3 dB frequency of
the closed-loop gain and, consequently, there is negligible effect
on stability margin. However, if the feedback pole is less than
approximately six times the expected 3 dB frequency, a lead
capacitor should be placed from the output to the negative input
of the op amp. The value of the added capacitor should be such
that the RC time constant of this capacitor and the resistance it
parallels is greater than, or equal to, the original feedback pole
time constant.
100kꢂ
2
3
OP215
A
4
–15V
NOTES
1. T = 125ꢁC TO 150ꢁC
A
2. RESISTORS ARE TYPE
RN55D, ꢄ 1%
Figure 5. Burn-In Circuit
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead CERDIP
(Z-Suffix)
8-Lead Plastic DIP
(P-Suffix)
0.430 (10.92)
0.348 (8.84)
0.055 (1.4)
MAX
0.005 (0.13)
MIN
8
5
8
5
0.280 (7.11)
0.240 (6.10)
0.310 (7.87)
0.220 (5.59)
PIN 1
1
4
1
4
0.325 (8.25)
0.300 (7.62)
PIN 1
0.100 (2.54)
BSC
0.100 (2.54) BSC
0.405 (10.29) MAX
0.320 (8.13)
0.290 (7.37)
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
0.160 (4.06)
0.115 (2.93)
0.195 (4.95)
0.115 (2.93)
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.130
(3.30)
MIN
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.015 (0.381)
0.008 (0.204)
0.022 (0.558) 0.070 (1.77) SEATING
0.014 (0.356) 0.045 (1.15)
0.015 (0.38)
0.008 (0.20)
PLANE
SEATING
15°
0°
0.023 (0.58) 0.070 (1.78)
0.014 (0.36) 0.030 (0.76)
PLANE
REV. A
–7–
OP215
Revision History
Location
Page
Data Sheet changed from REV. 0 to REV. A.
Edits to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2, 3
Edits to ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edits to PIN CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edits to PACKAGE TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Deleted WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Deleted DICE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Deleted TYPICAL ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edits to BURN-IN CIRCUIT figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
–8–
REV. A
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