OP279GP [ADI]
Rail-to-Rail High Output Current Operational Amplifiers; 轨至轨高输出电流运算放大器
| 型号： | OP279GP |
| 厂家： | 
ADI |
| 描述： | Rail-to-Rail High Output Current Operational Amplifiers |
| 文件： | 总16页 (文件大小：231K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rail-to-Rail High Output
a
Current Operational Amplifiers
OP179/OP279
PIN CONFIGURATIONS
FEATURES
Rail-to-Rail Inputs and Outputs
High Output Current: ؎60 mA
Single Supply: +5 V to +12 V
Wide Bandwidth: 5 MHz
High Slew Rate: 3 V/s
Low Distortion: 0.01%
Unity-Gain Stable
5-Lead SOT-23-5
(RT-5)
OP179
OUT A
V+
1
2
5
4
V–
No Phase Reversal
+IN A
3
؊IN A
Short Circuit Protected
Drives Capacitive Loads: 10 nF
8-Lead SOIC and TSSOP
SO-8 (R) and RU-8
APPLICATIONS
Multimedia
Telecom
DAA Transformer Driver
LCD Driver
Low Voltage Servo Control
Modems
OUT A
؊IN A
+IN A
V؊
V+
1
2
3
4
8
7
6
5
OUT B
OP279
؊IN B
+IN B
FET Drivers
8-Lead Plastic DIP
(N-8)
GENERAL DESCRIPTION
The OP179 and OP279 are rail-to-rail, high output current,
single-supply amplifiers. They are designed for low voltage
applications that require either current or capacitive load drive
capability. The OP179/OP279 can sink and source currents of
±60 mA (typical) and are stable with capacitive loads to 10 nF.
+V
OP279
OUT A
–IN A
OUT B
–IN B
+IN B
+IN A
–V
Applications that benefit from the high output current of the
OP179/OP279 include driving headphones, displays, transform-
ers and power transistors. The powerful output is combined with a
unique input stage that maintains very low distortion with
wide common-mode range, even in single supply designs.
Very good audio performance can be attained when using the
OP179/OP279 in +5 volt systems. THD is below 0.01% with a
600 Ω load, and noise is a respectable 21 nV/√Hz. Supply cur-
rent is less than 3.5 mA per amplifier.
The OP179/OP279 can be used as a buffer to provide much
greater drive capability than can usually be provided by CMOS
outputs. CMOS ASICs and DAC often have outputs that can
swing to both the positive supply and ground, but cannot drive
more than a few milliamps.
The single OP179 is available in the 5-lead SOT-23-5 package.
It is specified over the industrial (–40°C to +85°C) temperature
range.
Bandwidth is typically 5 MHz and the slew rate is 3 V/µs, mak-
ing these amplifiers well suited for single supply applications
that require audio bandwidths when used in high gain configu-
rations. Operation is guaranteed from voltages as low as 4.5 V,
up to 12 V.
The OP279 is available in 8-lead plastic DIP, TSSOP and
SO-8 surface mount packages. They are specified over the
industrial (–40°C to +85°C) temperature range.
REV. F
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
OP179/OP279–SPECIFICATIONS
ELECTRICAL SPECIFICATIONS (@ VS = +5.0 V, VCM = 2.5 V, –40؇C ≤ TA ≤ +85؇C unless otherwise noted)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
INPUT CHARACTERISTICS
Offset Voltage
OP179
OP279
Input Bias Current
VOS
VOS
IB
VOUT = 2.5 V
VOUT = 2.5 V
VOUT = 2.5 V, TA = +25°C
VOUT = 2.5 V
VOUT = 2.5 V, TA = +25°C
±5
±4
±300
±700
±50
±100
5
mV
mV
nA
nA
nA
nA
V
Input Offset Current
IOS
VOUT = 2.5 V
Input Voltage Range
VCM
0
Common-Mode Rejection Ratio
Large Signal Voltage Gain
Offset Voltage Drift
CMRR
AVO
∆VOS/∆T
VCM = 0 V to 5 V
RL = 1 kΩ, 0.3 V ≤ VOUT ≤ 4.7 V
56
20
66
4
dB
V/mV
µV/°C
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
VOH
VOL
IL = 10 mA Source
IL = 10 mA Sink, TA = +25°C
+4.8
V
75
100
mV
mV
mA
Ω
I
L = 10 mA Sink
Short Circuit Limit
Output Impedance
ISC
ZOUT
TA = +25°C
f = 1 MHz, AV = 1
±40
22
88
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
Supply Voltage Range
PSRR
ISY
VS
VS = +4.5 V to +12 V
VOUT = 2.5 V
70
dB
mA
V
3.5
+12
+4.5
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Phase Margin
SR
GBP
φm
RL = 1 kΩ, 1 nF
3
5
60
10
V/µs
MHz
Degrees
nF
Capacitive Load Drive
No Oscillation
AUDIO PERFORMANCE
Total Harmonic Distortion
Voltage Noise Density
THD
e
n
0.01
22
%
nV/√Hz
f = 1 kHz
ELECTRICAL SPECIFICATIONS
(@ VS = ؎5.0 V, –40؇C ≤ TA ≤ +85؇C unless otherwise noted)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
INPUT CHARACTERISTICS
Offset Voltage
OP179
OP279
Input Bias Current
VOS
VOS
IB
VOUT = 0
VOUT = 0
TA = +25°C
±5
±4
±300
±700
±50
±100
+5
mV
mV
nA
nA
nA
nA
V
dB
V/mV
µV/°C
Input Offset Current
IOS
TA = +25°C
Input Voltage Range
VCM
CMRR
AVO
–5
56
20
Common-Mode Rejection Ratio
Large Signal Voltage Gain
Offset Voltage Drift
V
CM = –5 V to +5 V
66
3
RL = 1 kΩ, –4.7 V ≤ VOUT ≤ 4.7 V
∆VOS/∆T
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short Circuit Limit
Open-Loop Output Impedance
VOH
VOL
ISC
IL = 10 mA Source
IL = 10 mA Sink
TA = +25°C
+4.8
V
V
mA
Ω
–4.85
3.75
±50
ZOUT
f = 1 MHz, AV = +1
22
3
POWER SUPPLY
Supply Current/Amplifier
ISY
VS = ±6 V, VOUT = 0 V
mA
DYNAMIC PERFORMANCE
Slew Rate
SR
RL = 1 kΩ, 1 nF
V/µs
Full-Power Bandwidth
Gain Bandwidth Product
Phase Margin
BWp
GBP
φm
1% Distortion
kHz
MHz
Degrees
5
69
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
e p-p
0.1 Hz to 10 Hz
f = 1 kHz
2
22
1
µV p-p
nV/√Hz
pA/√Hz
n
e
n
i
n
Specifications subject to change without notice.
–2–
REV. F
OP179/OP279
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+16 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+16 V
Differential Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . . ±1 V
Output Short-Circuit Duration to GND . . . . . . . . . . Indefinite
Storage Temperature Range
P, S, RT, RU Package . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
OP179G/OP279G . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature Range
P, S, RT, RU Package . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300°C
2
Package Types
Unit
JA
JC
5-Lead SOT-23 (RT)
8-Lead Plastic DIP (P)
8-Lead SOIC (S)
256
103
158
240
81
43
43
43
°C/W
°C/W
°C/W
°C/W
8-Lead TSSOP (RU)
NOTES
1The inputs are clamped with back-to-back diodes. If the differential input voltage
exceeds 1 volt, the input current should be limited to 5 mA.
2θJA is specified for the worst case conditions, i.e., θJA is specified for device in socket
for P-DIP, packages; θJA is specified for device soldered in circuit board for SOIC
packages.
ORDERING GUIDE
Package
Temperature Range
Package Description
Package Option
Brand Code
OP179GRT
OP279GP
OP279GS
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
5-Lead SOT-23
8-Lead Plastic DIP
8-Lead SOIC
RT-5
N-8
SO-8
RU-8
A2G
OP279GRU
8-Lead TSSOP
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the OP179/OP279 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–3–
REV. F
OP179/OP279
Typical Performance Graphs
160
90
80
400
V
= +5V
S
V
= +5V
S
T
= +25؇C
140
120
100
80
A
300
200
100
620 x OP AMPS,
PDIP
–40؇C
–I
+I
SC
+25؇C
+85؇C
70
60
0
–100
–200
SC
60
40
V
V
= +5V
50
40
S
= +2.5V
CM
20
0
–300
–400
–2.5
–1.5
–0.5
0.5
1.5
2.5
–50
–25
0
25
50
75
100
0
1
2
3
4
5
INPUT OFFSET – mV
TEMPERATURE – ؇C
COMMON-MODE VOLTAGE – Volts
Figure 1. Input Offset Distribution
Figure 2. Short Circuit Current vs.
Temperature
Figure 3. Input Bias Current
vs. Common-Mode Voltage
7
3.0
100
V
T
= +5V
S
V
T
= +5V
S
–I
6
5
4
3
2
1
SC
= +25؇C
A
2.5
= +25؇C
A
90
80
2.0
1.5
1.0
0.5
0
+I
SC
70
60
V
= ؎5V
S
0
50
–50
0
1
2
3
4
5
–25
0
25
50
75
100
0
1
2
3
4
5
COMMON-MODE VOLTAGE – Volts
COMMON-MODE VOLTAGE – Volts
TEMPERATURE – ؇C
Figure 4. Offset Voltage vs.
Common-Mode Voltage
Figure 5. Short Circuit Current vs.
Temperature
Figure 6. Bandwidth vs.
Common-Mode Voltage
1000
5
120
100
270
225
180
135
V
T
؎2.5V
–40؇C
= 2k⍀
S
R = 2k⍀
L
A
800
600
R
4
L
+EDGE
80
60
40
20
0
GAIN
V
0.3
= 15V
S
3
V
4.7V
OUT
–EDGE
90
45
PHASE
400
200
0
2
V
= +5V
= 1k⍀
= +1nF
R = 1k⍀
S
L
0
1
R
C
L
L
–45
–20
–40
0
–50
–90
10M
–50
–25
0
25
50
75
100
–25
0
25
50
75
100
100
1k
10k
100k
1M
TEMPERATURE – ؇C
TEMPERATURE – ؇C
FREQUENCY – Hz
Figure 7. Open-Loop Gain vs.
Temperature
Figure 8. Slew Rate vs.
Temperature
Figure 9. Open-Loop Gain and
Phase vs. Frequency
–4–
REV. F
OP179/OP279
6.5
6.0
5.5
5
4
120
270
V
T
؎2.5V
–40؇C
S
+EDGE
–EDGE
100
80
60
40
20
0
225
180
135
A
R
= 2k⍀
L
L
V
V
= ؎6V
S
C
= 500pF
GAIN
3
2
1
0
= ؎5V
S
90
45
PHASE
5.0
4.5
4.0
V
= +5V
S
V
= ؎5V
= 1k⍀
= +1nF
0
S
V
= +2.5V
CM
R
C
L
L
–45
–20
–40
–90
10M
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
100
1k
10k
100k
1M
TEMPERATURE – ؇C
FREQUENCY – Hz
TEMPERATURE – ؇C
Figure 11. Slew Rate vs. Temperature
Figure 12. Open-Loop Gain and
Phase vs. Frequency
Figure 10. Supply Current vs.
Temperature
120
100
180
160
140
120
6
T
= +25؇C
A
V
T
؎2.5V
S
T
V
A
R
= +25؇C
= ؎2.5V
A
V
= ؎2.5V OR ؎5V
S
= +25؇C
A
S
5
4
= +1
1k⍀
VCL
L
80
60
40
–PSRR
A
= 10 OR 100
VCL
100
3
2
80
60
40
20
0
+PSRR
20
0
1
0
A
VCL
= 1
10
100
1k
10k 100k
1M
10M
10
100
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
FREQUENCY – Hz
Figure 13. Power Supply Rejection vs.
Frequency
Figure 14. Maximum Output
Swing vs. Frequency
Figure 15. Closed-Loop Output
Impedance vs. Frequency
50
12
V
T
؎2.5V
= +25؇C
80
A
= +100
= +10
S
T
V
A
R
= +25؇C
= ؎5V
= +1
VCL
A
T
= +25؇C
A
40
30
20
A
S
A
R
V
= +1
10
8
70
60
50
40
VCL
R
1k⍀
L
VCL
1k⍀
L
1k⍀
L
؎2.5V
A
S
VCL
VCL
V
= +100mV p-p
IN
6
10
0
A
= +1
4
30
20
10
–10
POSITIVE EDGE AND
NEGATIVE EDGE
2
0
–20
–30
1k
10k
100k
FREQUENCY – Hz
1M
10M
100M
1k
10k
100k
1M
10M
0
0
2k
4k
6k
8k
10k
FREQUENCY – Hz
LOAD CAPACITANCE – pF
Figure 16. Maximum Output Swing
vs. Frequency
Figure 17. Closed-Loop Gain vs.
Frequency
Figure 18. Small Signal Overshoot
vs. Load Capacitance
–5–
REV. F
OP179/OP279
Typical Performance Graphs
100
120
100
60
50
40
30
V
= +5V
S
V
T
= +5V
T
V
= +25؇C
؎2.5V
A
S
T
= +25؇C
A
= +25؇C
S
A
80
60
FREQUENCY = 1kHz
80
60
40
40
20
10
0
20
0
20
0
1
10
100
FREQUENCY – Hz
1k
10k
100
1k
10k
100k
1M
0
1
2
3
4
5
FREQUENCY – Hz
COMMON-MODE VOLTAGE – Volts
Figure 19. Voltage Noise Density vs.
Frequency
Figure 20. Voltage Noise Density vs.
Common-Mode Voltage
Figure 21. Common-Mode
Rejection vs. Frequency
V
THEORY OF OPERATION
POS
The OP179/OP279 is the latest entry in Analog Devices’ ex-
panding family of single-supply devices, designed for the multi-
media and telecom marketplaces. It is a high output current
drive, rail-to-rail input /output operational amplifier, powered
from a single +5 V supply. It is also intended for other low
supply voltage applications where low distortion and high out-
put current drive are needed. To combine the attributes of high
output current and low distortion in rail-to-rail input/output
operation, novel circuit design techniques are used.
R1
6k⍀
R2
3k⍀
Q2
Q3
Q4
R3
2.5k⍀
R4
2.5k⍀
D5
D6
D8
Q6
Q5
Q9
Q1
IN+
IN–
For example, Figure 1 illustrates a simplified equivalent circuit
for the OP179/OP279’s input stage. It is comprised of two PNP
differential pairs, Q5-Q6 and Q7-Q8, operating in parallel, with
diode protection networks. Diode networks D5-D6 and D7-D8
serve to clamp the applied differential input voltage to the
OP179/OP279, thereby protecting the input transistors against
avalanche damage. The fundamental differences between these
two PNP gain stages are that the Q7-Q8 pair are normally OFF
and that their inputs are buffered from the operational amplifier
inputs by Q1-D1-D2 and Q9-D3-D4. Operation is best under-
stood as a function of the applied common-mode voltage:
When the inputs of the OP179/OP279 are biased midway be-
tween the supplies, the differential signal path gain is controlled
by the resistively loaded (via R7, R8) Q5-Q6. As the input
common-mode level is reduced toward the negative supply
(VNEG or GND), the input transistor current sources, I1 and I3,
are forced into saturation, thereby forcing the Q1-D1-D2 and
Q9-D3-D4 networks into cutoff; however, Q5-Q6 remain
active, providing input stage gain. On the other hand, when the
common-mode input voltage is increased toward the positive
supply, Q5-Q6 are driven into cutoff, Q3 is driven into satura-
tion, and Q4 becomes active, providing bias to the Q7-Q8 dif-
ferential pair. The point at which the Q7-Q8 differential pair
becomes active is approximately equal to (VPOS – 1 V).
D7
D3
D1
D2
D4
R5
4k⍀
R6
4k⍀
Q8
Q7
–
+
V
I1
I2
O
R8
2.2k⍀
R7
2.2k⍀
I3
V
NEG
Figure 22. OP179/OP279 Equivalent Input Circuit
The key issue here is the behavior of the input bias currents in
this stage. The input bias currents of the OP179/OP279 over
the range of common-mode voltages from (VNEG + 1 V) to
(VPOS – 1 V) are the arithmetic sum of the base currents in Q1-
Q5 and Q9-Q6. Outside of this range, the input bias currents
are dominated by the base current sum of Q5-Q6 for input
signals close to VNEG, and of Q1-Q5 (Q9-Q6) for input signals
close to VPOS. As a result of this design approach, the input bias
currents in the OP179/OP279 not only exhibit different ampli-
tudes, but also exhibit different polarities. This input bias cur-
rent behavior is best illustrated in Figure 3. It is, therefore, of
paramount importance that the effective source impedances
connected to the OP179/OP279’s inputs are balanced for opti-
mum dc and ac performance.
–6–
REV. F
OP179/OP279
In order to achieve rail-to-rail output behavior, the OP179/OP279
design employs a complementary common-emitter (or gmRL)
output stage (Q15-Q16), as illustrated in Figure 23. These
amplifiers provide output current until they are forced into
saturation which occurs at approximately 50 mV from either
supply rail. Thus, their saturation voltage is the limit on the
maximum output voltage swing in the OP179/OP279. The
output stage also exhibits voltage gain, by virtue of the use of
common-emitter amplifiers; and, as a result, the voltage gain of
the output stage (thus, the open-loop gain of the device) exhib-
its a strong dependence to the total load resistance at the output
of the OP179/OP279 as illustrated in Figure 7.
ensure optimum dc and ac performance, it is important to bal-
ance source impedance levels. For more information on general
overvoltage characteristics of amplifiers refer to the 1993 Seminar
Applications Guide, available from the Analog Devices Literature
Center.
5
4
3
2
1
0
–1
V
POS
–2
–3
–4
–5
105⍀
Q13
I1
I3
Q3
Q7
–2.0
–1.0
0
1.0
2.0
Q15
INPUT VOLTAGE – V
Q4
Q8
Figure 24. OP179/OP279 Input Overvoltage Characteristic
Q11
Q12
Q1
Q2
150⍀
V
OUT
Output Phase Reversal
Q9
Q5
Some operational amplifiers designed for single supply opera-
tion exhibit an output voltage phase reversal when their inputs
are driven beyond their useful common-mode range. Typically
for single-supply bipolar op amps, the negative supply deter-
mines the lower limit of their common-mode range. With these
devices, external clamping diodes, with the anode connected to
ground and the cathode to the inputs, input signal excursions
are prevented from exceeding the device’s negative supply (i.e.,
GND), preventing a condition that could cause the output
voltage to change phase. JFET input amplifiers may also
exhibit phase reversal and, if so, a series input resistor is usually
required to prevent it.
Q16
Q6
Q10
105⍀
I2
I4
Q14
V
NEG
Figure 23. OP179/OP279 Equivalent Output Circuit
Input Overvoltage Protection
As with any semiconductor device, whenever the condition
exists for the input to exceed either supply voltage, the device’s
input overvoltage characteristic must be considered. When an
overvoltage occurs, the amplifier could be damaged, depending
on the magnitude of the applied voltage and the magnitude of
the fault current. Figure 24 illustrates the input overvoltage
characteristic of the OP179/OP279. This graph was generated
with the power supplies at ground and a curve tracer connected
to the input. As can be seen, when the input voltage exceeds
either supply by more than 0.6 V, internal pn-junctions ener-
gize, which allows current to flow from the input to the supplies.
As illustrated in the simplified equivalent input circuit (Figure
22), the OP179/OP279 does not have any internal current limit-
ing resistors, so fault currents can quickly rise to damaging
levels.
The OP179/OP279 is free from reasonable input voltage range
restrictions provided that input voltages no greater than the
supply voltages are applied. Although the device’s output will
not change phase, large currents can flow through the input
protection diodes, shown in Figure 22. Therefore, the tech-
nique recommended in the Input Overvoltage Protection sec-
tion should be applied in those applications where the
likelihood of input voltages exceeding the supply voltages is
possible.
Capacitive Load Drive
The OP179/OP279 has excellent capacitive load driving capa-
bilities. It can drive up to 10 nF directly as the performance
graph titled Small Signal Overshoot vs. Load Capacitance (Fig-
ure 18) shows. However, even though the device is stable, a
capacitive load does not come without a penalty in bandwidth.
As shown in Figure 25, the bandwidth is reduced to under 1 MHz
for loads greater than 3 nF. A “snubber” network on the out-
put won’t increase the bandwidth, but it does significantly re-
duce the amount of overshoot for a given capacitive load. A
snubber consists of a series R-C network (RS, CS), as shown in
Figure 26, connected from the output of the device to ground.
This network operates in parallel with the load capacitor, CL, to
provide phase lag compensation. The actual value of the resis-
tor and capacitor is best determined empirically.
This input current is not inherently damaging to the device as
long as it is limited to 5 mA or less. For the OP179/OP279,
once the input voltage exceeds the supply by more than 0.6 V,
the input current quickly exceeds 5 mA. If this condition con-
tinues to exist, an external series resistor should be added. The
size of the resistor is calculated by dividing the maximum over-
voltage by 5 mA. For example, if the input voltage could reach
100 V, the external resistor should be (100 V/5 mA) = 20 kΩ.
This resistance should be placed in series with either or both
inputs if they are exposed to an overvoltage. Again, in order to
–7–
REV. F
OP179/OP279
7
Table I. Snubber Networks for Large Capacitive Loads
V
R
= ؎5V
= 1k⍀
S
6
Load Capacitance (CL)
Snubber Network (RS, CS)
L
T
= +25؇C
A
10 nF
100 nF
1 µF
20 Ω, 1 µF
5 Ω, 10 µF
0 Ω, 10 µF
5
4
3
Overload Recovery Time
Overload, or overdrive, recovery time of an operational amplifier
is the time required for the output voltage to recover to its linear
region from a saturated condition. This recovery time is impor-
tant in applications where the amplifier must recover after a
large transient event. The circuit in Figure 28 was used to
evaluate the OP179/OP279’s overload recovery time. The
OP179/OP279 takes approximately 1 µs to recover from positive
saturation and approximately 1.2 µs to recover from negative
saturation.
2
1
0
0.01
0.100
1
10
CAPACITIVE LOAD – nF
Figure 25. OP179/OP279 Bandwidth vs. Capacitive Load
+5V
R2
R3
1k⍀
10k⍀
1/2
OP279
+5V
V
OUT
V
R
IN
S
100mV p-p
20V
C
L
10nF
1/2
OP279
R1
909⍀
V
OUT
C
S
1F
R
L
2V p-p
@ 100Hz
499⍀
–5V
Figure 26. Snubber Network Compensates for Capacitive
Load
Figure 28. Overload Recovery Time Test Circuit
The first step is to determine the value of the resistor, RS. A
good starting value is 100 Ω (typically, the optimum value will
be less than 100 Ω). This value is reduced until the small-signal
transient response is optimized. Next, CS is determined—10 µF
is a good starting point. This value is reduced to the smallest
value for acceptable performance (typically, 1 µF). For the case
of a 10 nF load capacitor on the OP179/OP279, the optimal
snubber network is a 20 Ω in series with 1 µF. The benefit is
immediately apparent as seen in the scope photo in Figure 27.
The top trace was taken with a 10 nF load and the bottom trace
with the 20 Ω, 1 µF snubber network in place. The amount of
overshot and ringing is dramatically reduced. Table I illustrates
a few sample snubber networks for large load capacitors.
Output Transient Current Recovery
In many applications, operational amplifiers are used to provide
moderate levels of output current to drive the inputs of ADCs,
small motors, transmission lines and current sources. It is in
these applications that operational amplifiers must recover
quickly to step changes in the load current while maintaining
steady-state load current levels. Because of its high output
current capability and low closed-loop output impedance, the
OP179/OP279 is an excellent choice for these types of applica-
tions. For example, when sourcing or sinking a 25 mA steady-
state load current, the OP179/OP279 exhibits a recovery time of
less than 500 ns to 0.1% for a 10 mA (i.e., 25 mA to 35 mA and
35 mA to 25 mA) step change in load current.
A Precision Negative Voltage Reference
10nF LOAD
100
In many data acquisition applications, the need for a precision
negative reference is required. In general, any positive voltage
reference can be converted into a negative voltage reference
through the use of an operational amplifier and a pair of matched
resistors in an inverting configuration. The disadvantage to that
approach is that the largest single source of error in the circuit is
the relative matching of the resistors used.
ONLY
90
SNUBBER
IN CIRCUIT
10
0%
50mV
2s
The circuit illustrated in Figure 29 avoids the need for tightly
matched resistors with the use of an active integrator circuit. In
this circuit, the output of the voltage reference provides the
input drive for the integrator. The integrator, to maintain cir-
cuit equilibrium, adjusts its output to establish the proper rela-
tionship between the reference’s VOUT and GND. Thus, various
negative output voltages can be chosen simply by substituting
for the appropriate reference IC (see table). To speed up the
Figure 27. Overshoot and Ringing Is Reduced by Adding a
“Snubber” Network in Parallel with the 10 nF Load
–8–
REV. F
OP179/OP279
ON-OFF settling time of the circuit, R2 can be reduced to
50 kΩ or less. Although the integrator’s time constant chosen
here is 1 ms, room exists to trade-off circuit bandwidth and
noise by increasing R3 and decreasing C2. The SHUTDOWN
feature is maintained in the circuit with the simple addition of a
PNP transistor and a 10 kΩ resistor. One caveat with this ap-
proach should be mentioned: although rail-to-rail output ampli-
fiers work best in the application, these operational amplifiers
require a finite amount (mV) of headroom when required to
provide any load current. The choice for the circuit’s negative
supply should take this issue into account.
The low dropout performance of this circuit is provided by stage
U2, one-half of an OP179/OP279 connected as a follower/buffer
for the basic reference voltage produced by U1. The low voltage
saturation characteristic of the OP179/OP279 allows up to 30 mA
of load current in the illustrated use, as a 5 V to 3.3 V converter
with high dc accuracy. In fact, the dc output voltage change for
a 30 mA load current delta measures less than 1 mV. This
corresponds to an equivalent output impedance of < 0.03 Ω. In
this application, the stable 3.3 V from U1 is applied to U2
through a noise filter, R1-C1. U2 replicates the U1 voltage
within a few mV, but at a higher current output at VOUT1, with
the ability to both sink and source output current(s)—unlike
most IC references. R2 and C2 in the feedback path of U2
provide bias compensation for lowest dc error and additional
noise filtering.
V
(V)
U1
OUT
2.5
3.0
3.3
4.5
+5V
REF192
REF193
REF196
REF194
R5
10k⍀
C2
1F
SHUTDOWN
TTL/CMOS
2N3904
Transient performance of the reference/regulator for a 10 mA
step change in load current is also quite good and is determined
largely by the R5-C5 output network. With values as shown, the
transient is about 10 mV peak and settles to within 2 mV in
8 µs, for either polarity. Although room exists for optimizing the
transient response, any changes to the R5-C5 network should be
verified by experiment to preclude the possibility of excessive
ringing with some capacitor types.
2
R3
1k⍀
+5V
U1
3
R4
6
REF195
10⍀
1/2
OP279
–V
REF
C1
1F
GND
4
R2
R1
10k⍀
–10V
100k⍀
To scale VOUT2 to another (higher) output level, the optional
resistor R3 (shown dotted) is added, causing the new VOUT1 to
become:
Figure 29. A Negative Precision Voltage Reference That
Uses No Precision Resistors Exhibits High Output Current
Drive
R2
R3
A High Output Current, Buffered Reference/Regulator
Many applications require stable voltage outputs relatively close
in potential to an unregulated input source. This “low dropout”
type of reference/regulator is readily implemented with a rail-to-
rail output op amp, and is particularly useful when using a
higher current device such as the OP179/OP279. A typical
example is the 3.3 V or 4.5 V reference voltage developed from
a 5 V system source. Generating these voltages requires a three-
terminal reference, such as the REF196 (3.3 V) or the REF194
(4.5 V), both of which feature low power, with sourcing outputs
of 30 mA or less. Figure 30 shows how such a reference can be
outfitted with an OP179/OP279 buffer for higher currents and/
or voltage levels, plus sink and source load capability.
VOUT 1 = VOUT 2 × 1+
As an example, for a VOUT1 = 4.5 V, and VOUT2 = 2.5 V from a
REF192, the gain required of U2 is 1.8 times, so R2 and R3
would be chosen for a ratio of 0.8:1, or 18 kΩ:22.5 kΩ. Note
that for the lowest VOUT1 dc error, the parallel combination of
R2 and R3 should be maintained equal to R1 (as here), and the
R2-R3 resistors should be stable, close tolerance metal film
types.
The circuit can be used as shown as either a 5 V to 3.3 V refer-
ence/regulator, or it can be used with ON/OFF control. By
driving Pin 3 of U1 with a logic control signal as noted, the
output is switched ON/OFF. Note that when ON/OFF control
is used, resistor R4 should be used with U1 to speed ON-OFF
switching.
+V
+5V
S
U2
1/2 OP279
C1
0.1F
V
=
OUT1
3.3V @ 30mA
Direct Access Arrangement for Telephone Line Interface
Figure 31 illustrates a +5 V only transmit/receive telephone line
interface for 110 Ω transmission systems. It allows full duplex
transmission of signals on a transformer coupled 110 Ω line in a
differential manner. Amplifier A1 provides gain that can be
adjusted to meet the modem output drive requirements. Both
A1 and A2 are configured to apply the largest possible signal on a
single supply to the transformer. Because of the OP179/
OP279’s high output current drive and low dropout voltage, the
largest signal available on a single +5 V supply is approximately
4.5 V p-p into a 110 Ω transmission system. Amplifier A3 is
configured as a difference amplifier to extract the receive signal
from the transmission line for amplification by A4. A4’s gain
can be adjusted in the same manner as A1’s to meet the modem’s
input signal requirements. Standard resistor values permit the
use of SIP (Single In-line Package) format resistor arrays. Couple
this with the OP179/OP279’s 8-lead SOIC footprint and this
circuit offers a compact, cost-sensitive solution.
R2
10k⍀
1%
R1
10k⍀
1%
C2
0.1F
R3
C3
0.1F
(SEE TEXT)
C5
2
10F/25V
TANTALUM
6
U1
R4
3
REF196
V
=
OUT2
V
C
3.3k⍀
3.3V
R5
1⍀
ON/OFF
CONTROL
C4
1F
4
INPUT CMOS HI
(OR OPEN) = ON
LO = OFF
V
OUT
V
S
COMMON
COMMON
Figure 30. A High Output Current Reference/Regulator
–9–
REV. F
OP179/OP279
P1
The AMP04 is configured for a gain of 100, producing a circuit
sensitivity of 80 mV/Ω. Capacitor C2 is used across the AMP04’s
Pins 8 and 6 to provide a 16-Hz noise filter. If additional noise
filtering is required, an optional capacitor, CX, can be used
across the AMP04’s input to provide differential-mode noise
rejection.
TX GAIN
ADJUST
R2
9.09k⍀
C1
0.1F
TRANSMIT
TXA
R1
10k⍀
TO TELEPHONE
2k⍀
R3
55⍀
2
LINE
1:1
1
A1
3
R5
10k⍀
6.2V
6.2V
Z
O
R4
55⍀
110⍀
A Single Supply, Balanced Line Driver
+5V DC
The circuit in Figure 33 is a unique line driver circuit topology
used in professional audio applications and has been modified
for automotive audio applications. On a single +12 V supply,
the line driver exhibits less than 0.02% distortion into a 600 Ω
load across the entire audio band (not shown). For loads greater
than 600 Ω, distortion performance improves to where the cir-
cuit exhibits less than 0.002%. The design is a transformerless,
balanced transmission system where output common-mode
rejection of noise is of paramount importance. Like the trans-
former-based system, either output can be shorted to ground for
unbalanced line driver applications without changing the circuit
gain of 1. Other circuit gains can be set according to the equa-
tion in the diagram. This allows the design to be easily config-
ured for noninverting, inverting, or differential operation.
T1
R6
10k⍀
6
5
R7
10k⍀
7
A2
R8
10k⍀
10F
R9
10k⍀
R10
10k⍀
P2
RX GAIN
ADJUST
RECEIVE
RXA
R13
R14
2
3
10k⍀ 9.09k⍀
R11
10k⍀
1
A3
2k⍀
C2
0.1F
6
R12
10k⍀
7
A4
5
A1, A2 = 1/2 OP279
A3, A4 = 1/2 OP279
Figure 31. A Single Supply Direct Access Arrangement for
Modems
A Single Supply, Remote Strain Gage Signal Conditioner
The circuit in Figure 32 illustrates a way by which the OP179/
OP279 can be used in a +12 V single supply, 350 Ω strain gage
signal conditioning circuit. In this circuit, the OP179/OP279
serves two functions: (1) By servoing the output of the REF43’s
+2.5 V output across R1, it provides a 20 mA drive to the 350 Ω
strain gage. In this way, small changes in the strain gage pro-
duce large differential output voltages across the AMP04’s in-
puts. (2) To maximize the circuit’s dynamic range, the other
half of the OP179/OP279 is configured as a supply-splitter
connected to the AMP04’s REF terminal. Thus, tension or
compression in the application can be measured by the circuit.
R3
10k⍀
C3
R5
2
3
47F
50⍀
1
A2
V
O1
R6
10k⍀
R2
10k⍀
R7
10k⍀
+12V
+12V
A1
+12V
2
3
6
5
C1
22F
R8
100k⍀
1
7
R
L
A1
600⍀
V
IN
R9
100k⍀
C2
1F
R1
10k⍀
R11
R12
10k⍀
10k⍀
A1, A2 = 1/2 OP279
C4
47F
+12V
R14
50⍀
R3
R2
6
GAIN =
7
V
A2
O2
5
SET: R7, R10, R11 = R2
SET: R6, R12, R13 = R3
R13
10k⍀
2
0.1F
+2.5V
3
2
6
8
REF43
4
1
A1
F+
4
Figure 33. A Single Supply, Balanced Line Driver for
Automotive Applications
+12V
C2
0.1F
R4
1k⍀
7
3
20mA DRIVE
1
8
S+
S–
6
C
AMP04
X
2
V
O
5
4
80mV/⍀
R1
124⍀
0.1%, LOW TCR
100-ft TWISTED PAIR
BELDEN TYPE 9502
V
O
COMMON
+12V
6
F–
350⍀
STRAIN GAGE
R2
7
+6V
A2
10k⍀
5
C1
10F
R3
10k⍀
A1, A2 = 1/2 OP279
Figure 32. A Single Supply, Remote Strain Gage Signal
Conditioner
–10–
REV. F
OP179/OP279
A Single Supply Headphone Amplifier
UNITY-GAIN, SALLEN-KEY (VCVS) FILTERS
Because of its high speed and large output drive, the OP179/
OP279 makes for an excellent headphone driver, as illustrated
in Figure 34. Its low supply operation and rail-to-rail inputs
and outputs give a maximum signal swing on a single +5 V
supply. To ensure maximum signal swing available to drive the
headphone, the amplifier inputs are biased to V+/2, which is in
this case 2.5 V. The 100 kΩ resistor to the positive supply is
equally split into two 50 kΩ with their common point bypassed
by 10 µF to prevent power supply noise from contaminating the
audio signal.
High Pass Configurations
In Figure 35a is the HP form of a unity-gain 2-pole SK filter
using an OP179/OP279 section. For this filter and its LP coun-
terpart, the gain in the passband is inherently unity, and the
signal phase is noninverting due to the follower hookup. For
simplicity and practicality, capacitors C1-C2are set equal, and
resistors R2-R1 are adjusted to a ratio “N,” which provides the
filter damping “α ” as per the design expressions. A HP design
is begun with selection of standard capacitor values for C1 and
C2 and a calculation of N; then R1 and R2 are calculated as per
the figure expressions.
+V + 5V
In these examples, α (or 1/Q) is set equal to √2, providing a
Butterworth (maximally flat) response characteristic. The filter
corner frequency is normalized to 1 kHz, with resistor values
shown in both rounded and (exact) form. Various other 2-pole
response shapes are also possible with appropriate selection of
α. For a given response type (α), frequency can be easily scaled,
using proportional R or C values.
50k⍀
+V + 5V
220F
10F
16⍀
1/2
OP279
50k⍀
LEFT
HEADPHONE
LEFT
INPUT
50k⍀
10F
100k⍀
R1
11k⍀
(11.254k⍀)
C1
0.01F
OUT
IN
+V
C2
0.01F
+V
U1A
OP279
S
3
2
8
GIVEN: ALPHA, F
SET C1 = C2 = C
50k⍀
50k⍀
1
R2
22k⍀
(22.508k⍀)
4
ALPHA = 2/(N^0.5) = 1/Q
N = 4/(ALPHA)^2 = R2/R1
220F
50k⍀
10F
16⍀
1/2
OP279
–V
RIGHT
HEADPHONE
S
R1 = 1/(2 PI F C (N^0.5))
*
* * *
RIGHT
INPUT
R2 = N R1
*
R = R2
0.1F
10F
100k⍀
1kHz BW SHOWN
Z (HIGH PASS)
f
Figure 34. A Single Supply, Stereo Headphone Driver
a. High Pass
R1
11k⍀
(11.254k⍀)
C1
0.02F
The audio signal is then ac-coupled to each input through a
10 µF capacitor. A large value is needed to ensure that the
20 Hz audio information is not blocked. If the input already has
the proper dc bias, the ac coupling and biasing resistors are not
required. A 220 µF capacitor is used at the output to couple the
amplifier to the headphone. This value is much larger than that
used for the input because of the low impedance of the head-
phones, which can range from 32 Ω to 600 Ω. An additional
16 Ω resistor is used in series with the output capacitor to pro-
tect the op amp’s output stage by limiting capacitor discharge
current. When driving a 48 Ω load, the circuit exhibits less than
0.02% THD+N at low output drive levels (not shown). The
OP179/OP279’s high current output stage can drive this heavy
load to 4 V p-p and maintain less than 1% THD+N.
OUT
IN
R2
11k⍀
(11.254k⍀)
U1B
OP279
GIVEN: ALPHA, F
SET R1 = R2 = R
5
6
7
C2
ALPHA = 2/(M^0.5) = 1/Q
N = 4/(ALPHA)^2 = C2/C1
0.01F
PICK C1
C1 = M*C1
R = 1/(2*P1*F*C1* (M^0.5))
R = R1+R2
1kHz BW SHOWN
0.1F
Z (LOW PASS)
f
b. Low Pass
Active Filters
Figure 35. 2-Pole Unity-Gain Sallen Key HP/LP Filters
Several active filter topologies are useful with the OP179/OP279.
Among these are two popular architectures, the familiar Sallen-
Key (SK) voltage controlled voltage source (VCVS) and the
multiple feedback (MFB) topologies. These filter types can be
arranged for high pass (HP), low pass (LP), and bandpass (BP)
filters. The SK filter type uses the op amp as a fixed gain voltage
follower at unity or a higher gain, while the MFB structure uses
it as an inverting stage. Discussed here are simplified, 2-pole
forms of these filters, highly useful as system building blocks.
Low Pass Configurations
In the LP SK arrangement of Figure 35b, R and C elements are
interchanged, and the resistors are made equal. Here the C2/C1
ratio “M” is used to set the filter α, as noted. This design is begun
with the choice of a standard capacitor value for C1 and a calcu-
lation of M, which forces a value of “M × C1” for C2. Then, the
value “R” for R1 and R2 is calculated as per the expression.
For highest performance, the passive components used for tun-
ing active filters deserve attention. Resistors should be 1%, low
TC, metal film types of the RN55 or RN60 style, or similar.
–11–
REV. F
OP179/OP279
reactive, and limits overall practicality of this filter. The dire
effect of C1 loading can be tempered somewhat by using a small
series input resistance of about 100 Ω, but can still be an issue.
Capacitors should be 1% or 2% film types preferably, such as
polypropylene or polystyrene, or NPO (COG) ceramic for
smaller values. Somewhat lesser performance is available with
the use polyester capacitors.
C1
0.01F
C2
0.01F
Parasitic Effects in Sallen-Key Implementations
IN
OUT
In designing these circuits, moderately low (10 kΩ or less) val-
ues for R1-R2 can be used to minimize the effects of Johnson
noise when critical, with of course practical tradeoffs of capaci-
tor size and expense. DC errors will result for larger values of
resistance, unless bias current compensation is used. To add
bias compensation in the HP filter of Figure 35a, a feedback
compensation resistor with a value equal to R2 is used, shown
optionally as Zf. This will minimize bias induced offset, reduc-
ing it to the product of the OP179/OP279’s IOS and R2. Similar
compensation is applied to the LP filter, using a Zf resistance of
R1 + R2. Using dc compensation and relatively low filter val-
ues, filter output dc errors using the OP179/OP279 will be
dominated by VOS, which is limited to 4 mV or less. A caveat
here is that the additional resistors increase noise substantially—
for example, an unbypassed 10 kΩ resistor generates ≈ 12 nV/
√Hz of noise. However, the resistance can be ac-bypassed to
eliminate noise with a simple shunt capacitor, such as 0.1 µF.
C3
0.01F
R2
33.6k⍀
GIVEN:
ALPHA, F AND H (PASSBAND GAIN)
ALPHA = 1/Q
6
5
7
R1
7.5k⍀
PICK A STD C1 VALUE, THEN:
C3 = C1, C2 = C1/H
R1 = ALPHA / ((2 PI F C1) (2+(1/H)))
U1B
OP279
*
*
*
*
R2 = (H (2+(1/H))) / (ALPHA (2 PI F C1))
*
* * * *
R = R2
1kHz BW EXAMPLE SHOWN
(NOTE: SEE TEXT ON C1 LOADING
CONSIDERATIONS)
0.1F
Z
b
Figure 36. Two-Pole, High Pass Multiple Feedback Filters
In this example, the filter gain is set to unity, the corner fre-
quency is 1 kHz, and the response is a Butterworth type. For
applications where dc output offset is critical, bias current com-
pensation can be used for the amplifier. This is provided by
network Zb, where R is equal to R2, and the capacitor provides
a noise bypass.
Sallen-Key Implementations in Single Supply Applications
The hookups shown illustrate a classical dual supply op amp
application, which for the OP179/OP279 would use supplies up
to ±5 V. However, these filters can also use the op amp in a
single-supply mode, with little if any alteration to the filter itself.
To operate single-supply, the OP179/OP279 is powered from
+5 V at Pin 8 with Pin 4 grounded. The input dc bias for the
op amp must be supplied from a dc source equal to 1/2 supply,
or 2.5 V in this case.
Low Pass Configurations
Figure 37 is a LP MFB 2-pole filter using an OP179/OP279
section. For this filter, the gain in the pass band is user config-
urable over a wide range, and the pass band signal phase is
inverting. Given the design parameters for α , F, and H, a sim-
plified design process is begun by picking a standard value for
C2. Then C1 and resistors R1-R3 are selected as per the rela-
tionships noted. Optional dc bias current compensation is pro-
vided by Zb, where R is equal to the value of R3 plus the parallel
equivalent value of R1 and R2.
For the HP section, dc bias is applied to the common end of R2.
R2 is simply returned to an ac ground that is a well-bypassed
2:1 divider across the 5 V source. This can be as simple as a
pair of 100 kΩ resistors with a 10 µF bypass cap. The output
from the stage is then ac coupled, using an appropriate coupling
cap from U1A to the next stage. For the LP section dc bias is
applied to the input end of R1, in common with the input sig-
nal. This dc can be taken from an unbypassed dual 100 kΩ
divider across the supply, with the input signal ac coupled to the
divider and R1.
R1
11.3k⍀
R2
11.3k⍀
OUT
IN
C2
0.01F
R3
5.62k⍀
GIVEN:
ALPHA, F AND H (PASSBAND GAIN)
ALPHA = 1/Q
5
6
7
PICK A STD C2 VALUE, THEN:
C1 = C2 • (4 • (H +1))/ALPHA^2
R1 = ALPHA/(4 • H • PI • F • C2)
R2 = H • R1
C1
0.04F
Multiple Feedback Filters
U1B
OP279
MFB filters, like their SK relatives, can be used as building
blocks as well. They feature LP and HP operation as well, but
can also be used in a bandpass BP mode. They have the prop-
erty of inverting operation in the pass band, since they are based
on an inverting amplifier structure. Another useful asset is their
ability to be easily configured for gain.
R3 = ALPHA/(4 • (H + 1) • PI • F • C2)
(R1 R2)+R3
1kHz BW EXAMPLE SHOWN
(NOTE: SEE TEXT ON C1 LOADING
CONSIDERATIONS)
0.1F
Z
b
High Pass Configurations
Figure 37. Two-Pole, Low-Pass Multiple Feedback Filters
Figure 36 shows an HP MFB 2-pole filter using an OP179/
OP279 section. For this filter, the gain in the passband is user
configurable, and the signal phase is inverting. The circuit uses
one more tuning component than the SK types. For simplicity,
capacitors C1 and C3 are set to equal standard values, and
resistors R1-R2 are selected as per the relationships noted. Gain
of this filter, H, is set by capacitors C1 and C2, and this factor
limits both gain selectability and precision. Also, input capaci-
tance C1 makes the load seen by the driving stage highly
Gain of this filter, H, is set here by resistors R2 and R1 (as in a
standard op amp inverter), and can be just as precise as these
resistors allow at low frequencies. Because of this flexible and
accurate gain characteristic, plus a low range of component
value spread, this filter is perhaps the most practical of all the
MFB types. Capacitor ratios are best satisfied by paralleling
two or more common types, as in the example, which is a 1 kHz
unity gain Butterworth filter.
–12–
REV. F
OP179/OP279
Bandpass Configurations
C1
0.01F
R3
49.9⍀
HI
R1
31.6k⍀
The MFB bandpass filter using an OP179/OP279 section is
shown in Figure 38. This filter provides reasonably stable me-
dium Q designs for frequencies of up to a few kHz. For best
predictability and stability, operation should be restricted to
applications where the OP179/OP279 has an open-loop gain in
excess of 2Q2 at the filter center frequency.
+V
S
500Hz AND UP
C2
0.01F
U1A
OP279
3
2
1
R2
31.6k⍀
V
4
IN
–V
S
R1
26.4k⍀
(264k⍀)
C1
0.1F
R4
49.9⍀
R6
31.6k⍀
R5
31.6k⍀
LO
IN
OUT
C3
0.01F
C2
0.1F
R7
15.8k⍀
R3
530k⍀
DC – 500Hz
GIVEN:
Q, F, AND A (PASSBAND GAIN)
ALPHA = 1/Q, H = A /Q
O
O
6
5
C4
0.02F
6
5
R2
1.4k⍀
(1.33k⍀)
7
7
PICK A STD C1 VALUE, THEN:
C2 = C1
R1 = 1/(H*(2*PI*F*C1))
R2 = 1/(((2*Q) –H)*(2*PI*F*C1))
R3 = Q/(PI*F*C1)
U1B
OP279
U1B
OP279
R = R3
+V
+5V
S
EXAMPLE: 60Hz, Q = 10,
0.1F
100F/25V
100F/25V
A
= 10 (OR 1)
O
O
TO U1
–V
COM
–5V
A
= 1 FOR '( )' VALUES
0.1F
Z
b
0.1F
S
Figure 38. Two-Pole, Bandpass Multiple Feedback Filters
Figure 39. Two-Way Active Crossover Networks
Given the bandpass design parameters for Q, F, and pass band
gain AO, the design process is begun by picking a standard value
for C1. Then C2 and resistors R1-R3 are selected as per the
relationships noted. This filter is subject to a wide range of
component values by nature. Practical designs should attempt
to restrict resistances to a 1 kΩ to 1 MΩ range, with capacitor
values of 1 µF or less. When needed, dc bias current compensa-
tion is provided by Zb, where R is equal to R3.
In the filter sections, component values have been selected for
good balance between reasonable physical/electrical size, and
lowest noise and distortion. DC offset errors can be minimized
by using dc compensation in the feedback and bias paths, ac
bypassed with capacitors for low noise. Also, since the network
input is reactive, it should driven from a directly coupled low
impedance source at VIN.
Two-Way Loudspeaker Crossover Networks
Figure 40 shows this filter architecture adapted for single supply
operation from a 5 V dc source, along the lines discussed
previously.
Active filters are useful in loudspeaker crossover networks for
reasons of small size, relative freedom from parasitic effects, and
the ease of controlling low/high channel drive, plus the con-
trolled driver damping provided by a dedicated amplifier. Both
Sallen-Key (SK) VCVS and multiple-feedback (MFB) filter
architectures are useful in implementing active crossover net-
works (see Reference 4), and the circuit shown in Figure 39 is
a two-way active crossover which combines the advantages of
both filter topologies. This active crossover exhibits less than
0.01% THD+N at output levels of 1 V rms using general pur-
pose unity gain HP/LP stages. In this two-way example, the LO
signal is a dc-500 Hz LP woofer output, and the HI signal is the
HP (> 500 Hz) tweeter output. U1B forms a MFB LP section
at 500 Hz, while U1A provides a SK HP section, covering fre-
quencies ≥ 500 Hz.
500Hz
AND UP
C1
0.01F
R3
49.9⍀
R1
31.6k⍀
10F
+
HI
+V
S
C2
0.01F
V
IN
100k⍀
U1A
OP279
1
R
IN
3
2
100k⍀
R2
31.6k⍀
4
C
IN
10F
DC –
500Hz
R4
49.9⍀
R6
31.6k⍀
R5
31.6k⍀
10F
+
LO
C3
0.01F
R7
15.8k⍀
100k⍀
+V
S
This crossover network is a Linkwitz-Riley type (see Reference
5), with a damping factor or α of 2 (also referred to as
“Butterworth squared”). A hallmark of the Linkwitz-Riley type
of filter is the fact that the summed magnitude response is flat
across the pass band. A necessary condition for this to happen
is the relative signal polarity of the HI output must be inverted
with respect to the LOW outputs. If only SK filter sections
were used, this requires that the connections to one speaker be
reversed on installation. Alternately, with one inverting stage
used in the LO channel, this accomplishes the same effect. In
the circuit as shown, stage U1B is the MFB LP filter which
provides the necessary polarity inversion. Like the SK sections,
it is configured for unity gain and an α of 2. The cutoff frequency
is 500 Hz, which complements the SK HP section of U4.
6
5
C4
0.02F
100k⍀
7
U1B
OP279
100k⍀
10F
+5V
+V
S
0.1F
100F/25V
TO U1
COM
Figure 40. A Single Supply, Two-Way Active Crossover
–13–
REV. F
OP179/OP279
The crossover example frequency of 500 Hz can be shifted
lower or higher by frequency scaling of either resistors or capaci-
tors. In configuring the circuit for other frequencies, comple-
mentary LP/HP action must be maintained between sections,
and component values within the sections must be in the same
ratio. Table II provides a design aid to adaptation, with sug-
gested standard component values for other frequencies.
References on Active Filters and Active Crossover Networks
1. Sallen, R.P.; Key, E.L., “A Practical Method of Designing
RC Active Filters,” IRE Transactions on Circuit Theory, vol.
CT-2, March 1955.
2. Huelsman, L.P.; Allen, P.E., Introduction to the Theory and
Design of Active Filters, McGraw-Hill, 1980.
3. Zumbahlen, H., “Chapter 6: Passive and Active Analog
Filtering,” within 1992 Analog Devices Amplifier Applications
Guide.
Table II. RC Component Selection for Various Crossover
Frequencies
4. Zumbahlen, H., “Speaker Crossovers,” within Chapter 8 of
R1/C1 (U1A)*
R5/C3 (U1B)**
1993 Analog Devices System Applications Guide.
Crossover Frequency (Hz)
5. Linkwitz, S., “Active Crossover Networks for Noncoincident
100
200
319
500
1 k
2 k
5 k
160 kΩ/0.01 µF
80.6 kΩ/0.01 µF
49.9 kΩ/0.01 µF
31.6 kΩ/0.01 µF
16 kΩ/0.01 µF
8.06 kΩ/0.01 µF
3.16 kΩ/0.01 µF
1.6 kΩ/0.01 µF
Drivers,” JAES, Vol. 24, #1, Jan/Feb 1976.
10 k
Table notes (applicable for α = 2).
* For SK stage U1A: R1 = R2, and C1 = C2, etc.
** For MFB stage U1B: R6 = R5, R7 = R5/2, and C4 = 2C3.
–14–
REV. F
OP179/OP279
OP179/OP279 Spice Macro Model
R10
C3
*
16
15
98
16
10
15.915E-12
* OP179/OP279 SPICE Macro-model
Rev. A, 5/94
*
*
ARG / ADI
* ZERO AT 1.5 MHz
*
E1
R5
R6
C4
*
14
14
18
14
98
18
98
18
(9,39) 1E6
1E6
1
* Copyright 1994 by Analog Devices
*
106.103E-15
* Refer to “README.DOC” file for License Statement. Use of
* this model indicates your acceptance of the terms and pro-
* BIAS CURRENT-VS-COMMON-MODE VOLTAGE
*
* visions in the License Statement.
EP
EN
V3
97
51
20
22
97
23
15
22
98
24
97
26
24
26
0
0
(99,0) 1
(50,0) 1
1.6
2.8
530
1E3
DX
DX
POLY(2) V3 V4 0 –1 1
10E3
POLY(1) (99,39) –1.63 1
POLY(1) (39,50) –2.73 1
DX
DX
*
* Node assignments
21
23
20
51
21
15
24
98
25
51
25
24
*
*
*
*
*
*
noninverting input
V4
R12
R13
D13
D14
FIB
RIB
E3
|
|
|
|
|
inverting input
|
|
|
|
positive supply
|
|
|
2
negative supply
|
|
output
|
E4
.SUBCKT OP179/OP279 3
*
99 50 45
D15
D16
*
* INPUT STAGE AND POLE AT 6 MHz
*
* POLE AT 6 MHz
*
G6
R20
C10
*
* OUTPUT STAGE
*
RS1
RS2
RO1
RO2
G7
I1
1
5
6
4
2
1
1
5
6
5
4
2
2
4
2
50
2
4
2
4
7
8
99
99
6
3
3
98
98
3
60.2E-6
7 QN
8 QN
DX
DX
1.628E3
1.628E3
2.487E3
2.487E3
5.333E-12
POLY(1) (16,39) 0.25E-3 50.118
5E-9
(24,98) 100E-9
(24,98) 100E-9
1E-12
98
40
40
40
98
98
(18,39)
1E6
26.526E-15
1E
6
Q1
Q2
D1
D2
R1
R2
R3
99
39
99
45
45
50
98
60
62
61
98
99
41
45
40
42
39
50
45
50
99
45
60
61
60
98
62
50
45
42
41
40
DX
DZ
6.0345E3
6.0345E3
40
R4
C1
EOS
IOS
GB1
GB2
CIN
*
40
(99,40) 25E-3
(40,50) 25E-3
(45,40) 25E-3
DX
DX
DC
G8
G9
D9
D10
V7
0
* GAIN STAGE AND DOMINANT POLE AT 16 Hz
*
EREF 98
V8
DC 0
FSY
D11
D12
V5
POLY(2) V7 V8 1.711E-3
DZ
DZ
1.54
1.54
D()
D(IS=1E-6)
1
1
0
9
(39,0) 1
(5,6) 402.124E-6
497.359E6
20E-12
0.58
0.47
DX
G1
R7
C2
V1
V2
D5
D6
*
98
9
9
99
11
9
98
98
10
50
10
9
V6
.MODEL
.MODEL
.MODEL
.ENDS
QN NPN(BF=300)
11
DX
* COMMON-MODE STAGE WITH ZERO AT 10 kHz
*
ECM 15
98
16
POLY(2) (3,39) (2,39) 0 0.5 0.5
1E6
R9
15
–15–
REV. F
OP179/OP279
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP
(N-8)
8-Lead Narrow-Body SO
(SO-8)
0.1968 (5.00)
0.1890 (4.80)
0.430 (10.92)
0.348 (8.84)
8
5
8
1
5
4
0.280 (7.11)
0.240 (6.10)
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
1
4
0.325 (8.25)
0.300 (7.62)
0.060 (1.52)
0.015 (0.38)
PIN 1
PIN 1
0.0688 (1.75)
0.0532 (1.35)
0.0196 (0.50)
0.0099 (0.25)
0.195 (4.95)
0.115 (2.93)
x 45°
0.210 (5.33)
MAX
0.0098 (0.25)
0.0040 (0.10)
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
8°
0°
SEATING
PLANE
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.022 (0.558) 0.100 0.070 (1.77)
(2.54)
0.008 (0.204)
SEATING
PLANE
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
0.014 (0.356)
0.045 (1.15)
BSC
8-Lead TSSOP
(RU-8)
5-Lead SOT-23
(RT-5)
0.1220 (3.100)
0.1063 (2.700)
0.122 (3.10)
0.114 (2.90)
PIN 1
3
4
2
1
8
5
0.1181 (3.000)
0.0984 (2.500)
0.0709 (1.800)
0.0590 (1.500)
5
0.0374 (0.950) REF
1
4
0.0748 (1.900)
REF
PIN 1
0.0079 (0.200)
0.0035 (0.090)
0.0256 (0.65)
BSC
0.0512 (1.300)
0.0354 (0.900)
0.0571 (1.450)
0.0354 (0.900)
0.006 (0.15)
0.002 (0.05)
0.0433
(1.10)
MAX
10؇
0؇
SEATING
PLANE
0.0197 (0.500)
0.0118 (0.300)
0.0590 (0.150)
0.0000 (0.000)
0.028 (0.70)
0.020 (0.50)
0.0236 (0.600)
0.0039 (0.100)
8؇
0؇
0.0118 (0.30)
0.0075 (0.19)
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
NOTE:
PACKAGE OUTLINE INCLUSIVE AS SOLDER PLATING.
–16–
REV. F
相关型号：
OP279GSZ-REEL7
DUAL OP-AMP, 4000 uV OFFSET-MAX, 5 MHz BAND WIDTH, PDSO8, ROHS COMPLIANT, SOP-8
ROCHESTER
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