OP470S [ADI]
航空航天用极低噪声四通道运算放大器;
| 型号： | OP470S |
| 厂家： | 
ADI |
| 描述： | 航空航天用极低噪声四通道运算放大器 放大器 航空 运算放大器 放大器电路 |
| 文件： | 总16页 (文件大小：311K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Speed, Low Noise Quad
Operational Amplifier
a
OP471
FEATURES
PIN CONFIGURATIONS
Excellent Speed: 8 V/ꢀs Typ
Low Noise: 11 nV/÷Hz @ 1 kHz Max
Unity-Gain Stable
High Gain Bandwidth: 6.5 MHz Typ
Low Input Offset Voltage: 0.8 mV Max
Low Offset Voltage Drift: 4 ꢀV/ꢁC Max
High Gain: 500 V/mV Min
14-Lead
Hermetic Dip
(Y-Suffix)
14-Lead
Plastic Dip
(P-Suffix)
1
2
3
4
5
6
7
14 OUT D
1
2
3
4
5
6
7
14 OUT D
13 –IN D
12 +IN D
11 V–
OUT A
–IN A
+IN A
V+
OUT A
–IN A
+IN A
V+
13 –IN D
12 +IN D
11 V–
Outstanding CMR: 105 dB Min
Industry Standard Quad Pinouts
OP471
OP471
+IN B
–IN B
OUT B
10 +IN C
+IN B
–IN B
OUT B
10 +IN C
GENERAL DESCRIPTION
9
8
–IN C
9
8
–IN C
The OP471 is a monolithic quad op amp featuring low noise,
11 nV/÷Hz Max @ 1 kHz, excellent speed, 8 V/ms typical, a
gain bandwidth of 6.5 MHz, and unity-gain stability.
OUT C
OUT C
The OP471 has an input offset voltage under 0.8 mV and an
input offset voltage drift below 4 mV/∞C, guaranteed over the full
military temperature range. Open-loop gain of the OP471 is over
500,000 into a 10 kW load ensuring outstanding gain accuracy
and linearity. The input bias current is under 25 nA limiting
errors due to signal source resistance. The OP471’s CMR of
over 105 dB and PSRR of under 5.6 mV/V significantly reduce
errors caused by ground noise and power supply fluctuations.
16-Lead SOIC
(S-Suffix)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
OUT A
–IN A
+IN A
V+
OUT D
–IN D
+IN D
V–
OP471
+IN B
–IN B
OUT B
NC
+IN C
–IN C
The OP471 offers excellent amplifier matching which is important
for applications such as multiple gain blocks, low-noise instru-
mentation amplifiers, quad buffers and low-noise active filters.
10 OUT C
NC
9
The OP471 conforms to the industry standard 14-lead DIP
pinout. It is pin-compatible with the LM148/LM149, HA4741,
RM4156, MC33074, TL084 and TL074 quad op amps and can
be used to upgrade systems using these devices.
NC = NO CONNECT
For applications requiring even lower voltage noise the OP470
with a voltage density of 5 nV/÷Hz Max @ 1 kHz is recommended.
V+
BIAS
OUT
+IN
–IN
V–
Figure 1. Simplified Schematic
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
OP471–SPECIFICATIONS
(@ V = ꢂ15 V, T = 25ꢁC, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS
S
A
OP471E
OP471F
OP471G
Min Typ Max
Parameter
Symbol Conditions
Min Typ Max
Min Typ Max
Unit
mV
Input Offset Voltage
Input Offset Current
Input Bias Current
Input Noise Voltage1
VOS
0.25 0.8
0.5 1.5
1.0 1.8
IOS
IB
VCM = 0 V
VCM = 0 V
4
7
10
25
7
20
50
12
25
30
60
nA
15
nA
en p-p
en
0.1 Hz to 10 Hz
250 500
250 500
250 500
nV p–p
Input Noise
fO = 10 Hz
fO = 100 Hz
fO = 1 kHz
9
7
16
12
9
7
16
12
9
7
16
12
nV/÷Hz
nV/÷Hz
nV/÷Hz
Voltage Density2
6.5 11
6.5 11
6.5 11
Input Noise
Current Density
in
fO = 10 Hz
fO = 100 Hz
fO = 1 kHz
1.7
0.7
0.4
1.7
0.7
0.4
1.7
0 7
0.4
pA÷Hz
pA÷Hz
pA÷Hz
Large-Signal
Voltage Gain
AVO
V = ±10 V
RL = 10 kW
RL = 2 kW
500 700
300 500
300 500
V/mV
V/mV
350 550
±11 ±12
±12 ±13
105 120
175 275
±11 ±12
±12 ±13
175 275
±11 ±12
±12 ±13
Input Voltage Range3
Output Voltage Swing
IVR
VO
V
RL ≥ 2 kW
V
Common-Mode
Rejection
CMR
VCM = ±11 V
95
115
95
115
dB
Power Supply
Rejection Ratio
PSRR
VS = 4.5 V to 18 V
1
5.6
5.6 17.8
5.6 17.8
mV/V
Slew Rate
SR
ISY
6.5
8
6.5
8
6.5
8
V/ms
Supply Current
(All Amplifiers)
No Load
Av = 10
9.2 11
9.2 11
9.2 11
mA
Gain Bandwidth
Product
Channel Separation1
GBW
CS
6.5
6.5
6.5
MHz
dB
VO = 20 V p-p
fO = 10 Hz
125 150
125 150
125 150
Input Capacitance
CIN
RIN
2.6
1.1
2.6
1.1
2.6
1.1
pF
Input Resistance
Differential-Mode
MW
Input Resistance
Common-Mode
RINCM
tS
11
11
11
GW
Settling Time
AV = 1
To 0.1%
To 0.01 %
4.5
7.5
4.5
7.5
4.5
7.5
ms
ms
NOTES
1Guaranteed but not 100% tested.
2Sample tested.
3Guaranteed by CMR test.
–2–
REV. A
OP471
ꢁ
(Vs = ±15 V, –25 C £ TA £ 85ꢁC for OP471E/F, –40ꢁC £ TA £ 85ꢁ for OP471G,
ELECTRICAL CHARACTERISTICS
unless otherwise noted.)
OP471E
OP471F
OP471G
Parameter
Symbol Conditions
Min Typ Max
Min Typ Max
Min Typ Max
Unit
mV
Input Offset Voltage
VOS
0.3 1.1
0.6 2.0
1.2 2.5
4
Average Input
Offset Voltage Drift
TCVOS
1
4
2
7
mV/∞C
Input Offset Current
Input Bias Current
los
IB
VCM = 0 V
VCM = 0 V
5
20
50
8
40
70
20
40
50
75
nA
nA
13
25
Large-Signal
Voltage Gain
VO = ±10 V
RL = 10 kW
RL = 2 kW
Avo
375 600
250 400
200 400
125 200
200 400
125 200
V/mV
Input Voltage Range*
IVR
VO
±11 ±12
±12 ±13
100 115
±11 ±12
±12 ±13
±11 ±12
±12 ±13
V
Output Voltage Swing
RL ≥ 2 kW
V
Common-Mode
Rejection
CMR
V
CM = ±11 V
90
110
90
110
dB
Power Supply
Rejection Ratio
PSRR
ISY
VS = ±4.5 V to ±18 V
3.2 10
9.3 11
18
31.6
18
31.6
mV/V
Supply Current
(All Amplifiers)
No Load
9.3 11
9.3 11
mA
*Guaranteed by CMR test.
ABSOLUTE MAXIMUM RATINGS1
Package Type
ꢃJA*
94
ꢃJC
10
33
23
Unit
∞C/W
∞C/W
∞C/W
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . ±1.0 V
Differential Input Current2 . . . . . . . . . . . . . . . . . . . . ±25 mW
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Voltage
Output Short-Circuit Duration . . . . . . . . . . . . . . .Continuous
Storage Temperature Range
P, Y-Package . . . . . . . . . . . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300∞C
Junction Temperature (Ti) . . . . . . . . . . . . . –65∞C to +150∞C
Operating Temperature Range
14-Lead Hermetic DIP(Y)
14-Lead Plastic DIP(P)
16-Lead SOIC (S)
76
88
*JA is specified for worst-case mounting conditions, i.e., JA is specified for device
in socket for TO, CERDIP, PDIP packages; JA is specified for device soldered to
printed circuit board for SO packages.
ORDERING GUIDE
OP471E, OP471F . . . . . . . . . . . . . . . . . . . –25∞C to +85∞C
OP471G . . . . . . . . . . . . . . . . . . . . . . . . . . . –40∞C to +85∞C
TA = 25∞C
OS MAX
(mV)
Package Options
Operating
Temperature
Range
V
NOTES
1Absolute Maximum Ratings apply to packaged parts, unless otherwise noted.
2The OP471’s inputs are protected by back-to-back diodes. Current limiting
resistors are not used in order to achieve low noise performance. If differential
voltage exceeds ±1.0 V, the input current should be limited to ±25 mA.
14-Lead CERDIP Plastic
800
OP471EY
OP471FY*
IND
IND
XIND
XIND
1,500
1,800
1,800
OP471GP
OP471GS
*Not for new design. Obsolete April 2002.
For military processed devices, please refer to the standard
microcircuit drawing (SMD) available at
www.dscc.dla.mil/programs/milspec/default.asp
5962-88565022A - OP471ARCMDA
5962-88565023A - OP471ATCMDA
5962-8856502CA - OP471AYMDA
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the OP471 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–3–
REV. A
–Typical Performance Characteristics
OP471
100
10
T
= 25ꢁC
T
A
= 25ꢁC
= ꢂ15V
A
AT 10Hz
1s
5mV
V
S
40
30
20
100
90
8
6
4
2
AT 1kHz
10
5
4
3
2
10
0%
T
= 25ꢁC
A
I/F CORNER = 5Hz
10
V
= ꢂ15V
S
0
2
4
6
8
10
1
TIME – Seconds
0
ꢂ5
ꢂ10
ꢂ15
ꢂ20
1
100
1k
FREQUENCY – Hz
SUPPLYVOLTAGE –V
TPC 2. Voltage Noise Density
vs. Supply Voltage
TPC 1. Voltage Noise Density
vs. Frequency
TPC 3. 0.1 Hz to 10 Hz Noise
20
18
16
14
12
10
8
100
400
300
200
T
= 25ꢁC
T
= 25ꢁC
V = ꢂ15V
S
A
S
A
S
V
= ꢂ15V
V
= ꢂ15V
40
30
20
10
5
4
3
2
6
100
I/F CORNER = 5Hz
10
4
2
0
0
1
–75 –50 –25
0
25
50 75 100 125
0
1
2
3
4
5
1
100
1k
TEMPERATURE – ꢁC
TIME – Minutes
FREQUENCY – Hz
TPC 5. Input Offset Voltage vs.
Temperature
TPC 4. Current Noise Density
vs. Frequency
TPC 6. Warm-Up Offset
Voltage Drift
10
9
20
15
10
9
V
V
= ꢂ15V
CM
T = 25ꢁC
A
V = ꢂ15V
S
S
V
CM
= ꢂ15V
S
= 0V
V
= 0V
8
7
6
5
4
3
2
1
0
8
10
7
5
0
6
5
–75 –50 –25
0
25 50
75 100 125
–75 –50 –25
0
25
50 75 100 125
–12.5
–7.5
–2.5
2.5
7.5
12.5
TEMPERATURE – ꢁC
TEMPERATURE – ꢁC
COMMON-MODEVOLTAGE –V
TPC 9. Input Bias Current vs.
Common-Mode Voltage
TPC 8. Input Offset Current vs.
Temperature
TPC 7. Input Bias Current vs.
Temperature
–4–
REV. A
OP471
10
9
130
120
110
100
90
10
8
T
= 25ꢁC
= ꢂ15V
V
= ꢂ15V
A
S
S
T
= +25ꢁC
A
V
T
= +125ꢁC
8
A
7
80
70
60
50
40
30
20
10
T
= –55ꢁC
A
6
6
5
4
4
3
2
2
–75 –50 –25
0
25 50
75 100 125
0
ꢂ5
ꢂ10
ꢂ15
ꢂ20
1
10
100
1k
10k 100k
1M
SUPPLYVOLTAGE –V
FREQUENCY – Hz
TEMPERATURE – ꢁC
TPC 12. Total Supply Current
vs. Temperature
TPC 11. Total Supply Current
vs. Supply Voltage
TPC 10. CMR vs. Frequency
140
130
120
110
100
90
80
70
60
50
40
30
80
60
40
20
0
140
130
120
110
100
90
80
70
60
50
40
30
T
= 25ꢁC
= ꢂ15V
A
S
T
= 25ꢁC
= ꢂ15V
T
= 25ꢁC
= 15V
A
S
A
S
V
V
V
–PSR
+PSR
20
10
0
20
10
0
–20
1
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY – Hz
1
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY – Hz
1k
10k
100k
FREQUENCY – Hz
1M
10M
TPC 13. PSR vs. Frequency
TPC 14. Open-Loop Gain vs. Frequency
TPC 15. Closed-Loop Gain
vs. Frequency
25
20
15
80
2000
80
8
6
4
2
0
T = 25ꢁC
A
V
= ꢂ15V
T
= 25ꢁC
S
A
S
R = 10kꢄ
L
V
= ꢂ15V 100
GBW
PHASE
GAIN
1500
1000
500
0
70
60
50
40
120
140
10
5
PHASE MARGIN
= 57ꢁ
160
180
200
220
ꢅ
0
–5
–10
0
ꢂ5
ꢂ10
ꢂ15
ꢂ20
–75 –50 –25
0
25 50 75 100 125 150
TEMPERATURE – ꢁC
10
6 7 8 9
1
2
3
4
5
SUPPLYVOLTAGE –V
FREQUENCY – MHz
TPC 16. Open-Loop Gain,
Phase Shift vs. Frequency
TPC 17. Open-Loop Gain vs.
Supply Voltage
TPC 18. Gain-Bandwidth Product,
Phase Margin vs. Temperature
–5–
REV. A
OP471
28
24
20
16
12
8
20
18
360
300
240
180
120
T
= 25ꢁC
T
= 25ꢁC
T
= 25ꢁC
= ꢂ15V
A
S
A
S
A
S
V
= ꢂ15V
V
= ꢂ15V
V
THD = 1%
16
14
12
10
8
POSITIVE
SWING
NEGATIVE
SWING
6
A
= 100
V
4
60
0
4
2
A
= 1
V
0
0
100
1k
10k 100k
FREQUENCY – Hz
1M
10M 100M
1k
10k
100k
FREQUENCY – Hz
1M
10M
100
1k
10k
LOAD RESISTANCE – ꢄ
TPC 20. Maximum Output Voltage
vs. Load Resistance
TPC 19. Maximum Output Swing
vs. Frequency
TPC 21. Closed-Loop Output
Impedance vs. Frequency
9.0
8.5
170
1
T
= 25ꢁC
A
S
O
T
= 25ꢁC
A
S
O
L
160
150
140
130
120
110
V
V
= ꢂ15V
V
V
= ꢂ15V
= 10V p-p
= 2kꢄ
= 20V p-pTO 100kHz
R
–SR
8.0
0.1
+SR
7.5
7.0
100
90
0.01
80
70
A = 10
V
6.5
6.0
A
= 1
V
60
50
0.001
–75 –50 –25
0
25
50
75 100 125
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
TEMPERATURE – ꢁC
FREQUENCY – Hz
FREQUENCY – Hz
TPC 23. Channel Separation vs.
Frequency
TPC 22. Slew Rate vs. Temperature
TPC 24. Total Harmonic Distortion
vs. Frequency
T
= 25ꢁC
= ꢂ15V
= 1
T
= 25ꢁC
= ꢂ15V
= 1
A
S
V
A
S
V
V
V
100
90
100
90
A
A
10
10
0%
0%
0.2µs
50mV
5µs
5V
TPC 26. Small-Signal Transient
Response
TPC 25. Large-Signal Transient
Response
–6–
REV. A
OP471
100
10
1
5kꢄ
500ꢄ
1/4
V
V
20V p-p
1
OP471
OP11
OP400
OP471
50kꢄ
50ꢄ
1/4
2
OP471
OP470
RESISTOR
NOISE ONLY
V
1
CHANNEL SEPARATION = 20 LOG
V
/1000
100
1k
10k
100k
2
RS – SOURCE RESISTANCE –ꢄ
Figure 2. Channel Separation Test Circuit
Figure 4. Total Noise vs. Source Resistance (Including
Resistor Noise) at 1 kHz
+18V
2
3
6
5
100
4
1
7
A
B
D
+1V
–1V
+1V
–1V
11
–18V
OP11
OP400
10
9
13
12
OP471
8
14
C
10
OP470
RESISTOR
NOISE ONLY
Figure 3. Burn-In Circuit
1
100
1k
10k
100k
RS – SOURCE RESISTANCE –ꢄ
APPLICATIONS INFORMATION
Voltage and Current Noise
Figure 5. Total Noise vs. Source Resistance (Including
Resistor Noise) at 10 Hz
The OP471 is a very low-noise quad op amp, exhibiting a typical
voltage noise of only 6.5 Hz @ 1 kHz. The low noise character-
istic of the OP471 is, in part, achieved by operating the input
transistors at high collector currents since the voltage noise is
inversely proportional to the square root of the collector current.
Current noise, however, is directly proportional to the square
root of the collector current. As a result, the outstanding voltage
noise performance of the OP471 is gained at the expense of current
noise performance which is typical for low noise amplifiers.
Figure 4 shows the relationship between total noise at 1 kHz
and source resistance. For RS < 1 kW the total noise is domi-
nated by the voltage noise of the OP471. As RS rises above 1 kW,
total noise increases and is dominated by resistor noise rather
than by voltage or current noise of the OP471. When RS exceeds
20 kW, current noise of the OP471 becomes the major contributor
to total noise.
Figure 5 also shows the relationship between total noise and source
resistance, but at 10 Hz. Total noise increases more quickly
than shown in Figure 4 because current noise is inversely pro-
portional to the square root of frequency. In Figure 5, current
noise of the OP471 dominates the total noise when RS > 5 kW.
To obtain the best noise performance in a circuit, it is vital to
understand the relationship between voltage noise (en), current
noise (in), and resistor noise (et).
Total Noise and Source Resistance
The total noise of an op amp can be calculated by:
From Figures 4 and 5, it can be seen that to reduce total noise,
source resistance must be kept to a minimum. In applications
with a high source resistance, the OP400, with lower current
noise than the OP471, will provide lower total noise.
2
En =
e
(
2 + i R 2 + e
)
(
)
( )
n
n
S
t
where:
En = total input referred noise
en = op amp voltage noise
in = op amp current noise
et = source resistance thermal noise
RS = source resistance
The total noise is referred to the input and at the output would
be amplified by the circuit gain.
REV. A
–7–
OP471
1000
For reference, typical source resistances of some signal sources
are listed in Table I.
OP11
OP400
TABLE I.
Source
OP471
OP470
Device
Impedance
Comments
100
Strain gauge
< 500 W
Typically used in
low-frequency applications.
RESISTOR
Magnetic
tapehead
< 1,500 W
< 1,500 W
Low IB very important to reduce
self-magnetization problems
when direct coupling is used.
OP471 IB can be neglected.
NOISE ONLY
10
100
1k
10k
100k
Magnetic
phonograph
cartridges
Similar need for low IB in direct
coupled applications. OP471
will not introduce any
RS – SOURCE RESISTANCE –ꢄ
Figure 6. Peak-to-Peak Noise (0.1 Hz to 10 Hz) vs. Source
Resistance (Includes Resistor Noise)
self -magnetization problem.
Figure 6 shows peak-to-peak noise versus source resistance over
the 0.1 Hz to 10 Hz range. Once again, at low values of RS, the
voltage noise of the OP471 is the major contributor to peak-to-peak
noise. Current noise becomes the major contributor as RS increases.
The crossover point between the OP471 and the OP400 for
peak-to-peak noise is at RS = 17 W.
Linear variable < 1,500 W
differential
transformer
Used in rugged servo-feedback
applications. Bandwidth of
interest is 400 Hz to 5 kHz.
*For further information regarding noise calculations, see “Minimization of
Noise in Op Amp Applications,” Application Note AN-15.
The OP470 is a lower noise version of the OP471, with a typical
noise voltage density of 3.2 nV/÷Hz @ 1 kHz. The OP470 offers
lower offset voltage and higher gain than the OP471, but is a slower
speed device, with a slew rate of 2 V/ms compared to a slew rate
of 8 V/ms for the OP471.
R3
1.24kꢄ
R1
5ꢄ
C1
OP471
DUT
R2
2ꢀF
5ꢄ
OP27E
C4
R6
0.22ꢀF
R5
909ꢄ
600kꢄ
R10
R11
65.4kꢄ
65.4kꢄ
R4
D1
D2
R14
OP15E
R9
200ꢄ
1N4148
1N4148
4.99kꢄ
C3
e
OUT
OP15E
0.22ꢀF
C5
306kꢄ
1ꢀF
R13
5.9kꢄ
R8
10kꢄ
C2
R12
0.032ꢀF
10kꢄ
GAIN = 50,000
= ꢂ15V
V
S
Figure 7. Peak-to-Peak Voltage Noise Test Circuit (0.1 Hz to 10 Hz)
–8–
REV. A
OP471
100
80
60
40
20
0
Noise Measurements - Peak-to-Peak Voltage Noise
The circuit of Figure 7 is a test setup for measuring peak-to-peak
voltage noise. To measure the 500 nV peak-to-peak noise speci-
fication of the OP471 in the 0.1 Hz to 10 Hz range, the following
precautions must be observed:
1. The device must be warmed up for at least five minutes. As
shown in the warm-up drift curve, the offset voltage typically
changes 13 mV due to increasing chip temperature after
power-up. In the 10-second measurement interval, these
temperature-induced effects can exceed tens-of-nanovolts.
2. For similar reasons, the device must be well-shielded from
air currents. Shielding also minimizes thermocouple effects.
3. Sudden motion in the vicinity of the device can also “feedthrough”
to increase the observed noise.
0.01
0.1
1
10
100
FREQUENCY – Hz
4. The test time to measure 0.1 Hz to 10 Hz noise should not exceed
10 seconds. As shown in the noise-tester frequency-response curve
of Figure 8, the 0.1 Hz corner is defined by only one pole. The
test time of 10 seconds acts as an additional pole to eliminate
noise contribution from the frequency band below 0.1 Hz.
Figure 8. 0.1 Hz to 10 Hz Peak-to-Peak Voltage Noise
Test Circuit Frequency Response
Noise Measurement - Noise Voltage Density
The circuit of Figure 9 shows a quick and reliable method of
measuring the noise voltage density of quad op amps. Each
individual amplifier is series connected and is in unity-gain, save
the final amplifier which is in a noninverting gain of 101. Since
the ac noise voltages of each amplifier are uncorrelated, they
add in rms fashion to yield:
5. A noise voltage density test is recommended when measuring
noise on a large number of units. A 10 Hz noise voltage density
measurement will correlate well with a 0.1 Hz to 10 Hz
peak-to-peak noise reading, since both results are determined
by the white noise and the location of the 1/f corner frequency.
Ê
2
2
2
2
ˆ
¯
eOUT =101 enA +enB + enC + enD
6. Power should be supplied to the test circuit by well bypassed,
low noise supplies, e.g, batteries. These will minimize output
noise introduced through the amplifier supply pins.
Ë
The OP471 is a monolithic device with four identical amplifiers.
The noise voltage density of each individual amplifier will
match, giving:
Ê
2
ˆ
¯
eOUT = 101 4en
= 101 2e
(
)
n
Ë
R1
R2
10kꢄ
100ꢄ
1/4
OP471
e
OUT
1/4
OP471
TO SPECTRUM ANALYZER
1/4
OP471
1/4
OP471
e
V
(nV Hz) = 101(2e )
n
OUT
= ꢂ15V
S
Figure 9. Noise Voltage DensityTest Circuit
REV. A
–9–
OP471
Noise Measurement - Current Noise Density
The test circuit shown in Figure 10 can be used to measure current
noise density. The formula relating the voltage output to current
noise density is:
adds phase shift in the feedback network and reduces stability. A
simple circuit to eliminate this effect is shown in Figure 11. The
added components, C1 and R3, decouple the amplifier from the
load capacitance and provide additional stability. The values of
C1 and R3 shown in Figure 11 are for load capacitances of up
to 1,000 pF when used with the OP471.
Ê enOUT ˆ2
2
- 40nV / Hz
Á
˜
(
)
In applications where the OP471’s inverting or noninverting inputs
are driven by a low source impedance (under 100 W) or connected
to ground, if V+ is applied before V–, or when V– is disconnected,
excessive parasitic currents will flow.
Ë
¯
G
in
=
RS
where:
Most applications use dual tracking supplies and with the device
supply pins properly bypassed, power-up will not present a
problem. A source resistance of at least 100 W in series with all
inputs (Figure 11) will limit the parasitic currents to a safe level
if V– is disconnected. It should be noted that any source resistance,
even 100 W, adds noise to the circuit. Where noise is required to
be kept at a minimum, a germanium or Schottky diode can be
used to clamp the V– pin and eliminate the parasitic current
flow instead of using series limiting resistors. For most applica-
tions, only one diode clamp is required per board or system.
G = gain of 10,000
RS = 100 kW source resistance
Capacative Load Driving and Power Supply Considerations
The OP471 is unity-gain stable and is capable of driving large
capacitive loads without oscillating. Nonetheless, good supply
bypassing is highly recommended. Proper supply bypassing
reduces problems caused by supply line noise and improves the
capacitive load driving capability of the OP471.
R3
1.24kꢄ
R
f
R2
R1
100kꢄ
5ꢄ
OP471
DUT
e
OUT TO
OP27E
n
SPECTRUM ANALYZER
OP471
R5
8.06kꢄ
8V/ꢀs
R4
200ꢄ
GAIN = 10,000
= ꢂ15V
Figure 12. Pulsed Operation
Unity-Gain Buffer Applications
When Rf £ 100 W and the input is driven with a fast, large signal
pulse (>1 V), the output waveform will look as shown in Figure 12.
V
S
Figure 10. Current Noise Density Test Circuit
V+
C2
During the fast feedthrough-like portion of the output, the input
protection diodes effectively short the output to the input, and a
current, limited only by the output short-circuit protection, will
be drawn by the signal generator. With Rf ≥ 500 W, the output
is capable of handling the current requirements (IL £ 20 mA at
10 V); the amplifier will stay in its active mode and a smooth
transition will occur.
10ꢀF
+
C3
0.1ꢀF
R2
C1
R1
200pF
V
R3
IN
When Rf > 3 kW, a pole created by Rf and the amplifier’s input
capacitance (2.6 pF) creates additional phase shift and reduces
phase margin. A small capacitor (20 pF to 50 pF) in parallel with
Rf helps eliminate this problem.
50ꢄ
V
OP471
OUT
100ꢄ*
C4
C
L
10ꢀF
1000pF
+
C5
0.1ꢀF
*
APPLICATIONS
Low Noise Amplifier
*SEETEXT
V–
A simple method of reducing amplifier noise by paralleling
amplifiers is shown in Figure 13. Amplifier noise, depicted in
Figure 14, is around 5 nV/÷Hz @ 1 kHz (R.T.I.). Gain for each
paralleled amplifier and the entire circuit is 100. The 200 W
resistors limit circulating currents and provide an effective output
resistance of 50 W. The amplifier is stable with a 10 nF capacitive
load and can supply up to 30 mA of output drive.
PLACE SUPPLY DECOUPLING
CAPACITORS AT OP471
Figure 11. Driving Large Capacitive Loads
In the standard feedback amplifier, the op amp’s output resistance
combines with the load capacitance to form a lowpass filter that
–10–
REV. A
OP471
High-Speed Differential Line Driver
The circuit of Figure 15 is a unique line driver widely used in
professional audio applications. With ±18 V supplies, the line
driver can deliver a differential signal of 30 V p-p into a 1.5 kW
load. The output of the differential line driver looks exactly like
a transformer. Either output can be shorted to ground without
changing the circuit gain of 5, so the amplifier can easily be set
for inverting, noninverting, or differential operation. The line
driver can drive unbalanced loads, like a true transformer.
100
90
10
0%
+15V
V
R3
IN
200ꢄ
1/4
R1
OP471E
50ꢄ
Figure 14. Noise Density of Low-Noise Amplifier, G = 100
R2
5kꢄ
–15V
R4
10kꢄ
R6
200ꢄ
1/4
R11
R4
OP471E
50ꢄ
50ꢄ
1/4
–OUT
OP471
R5
5kꢄ
R8
V
= 100V
IN
R2
OUT
10kꢄ
2kꢄ
R14
R9
1kꢄ
R7
IN
200ꢄ
1/4
2kꢄ
R7
R1
1/4
R13
OP471E
50ꢄ
10kꢄ
OP471
10kꢄ
R6
R9
R8
2kꢄ
10kꢄ
R12
5kꢄ
1kꢄ
R10
R12
R3
50ꢄ
200ꢄ
1/4
OP471
1/4
2kꢄ
+OUT
R10
OP471E
50ꢄ
R5
R11
10kꢄ
5kꢄ
Figure 15. High-Speed Differential Line Driver
Figure 13. Low-Noise Amplifier
High-Output Amplifier
The amplifier shown in Figure 16 is capable of driving 20 V p-p
into a floating 400 W load. Design of the amplifier is based on a
bridge configuration. A1 amplifies the input signal and drives
the load with the help of A2. Amplifier A3 is a unity-gain inverter
which drives the load with help from A4. Gain of the high output
amplifier with the component values shown is 10, but can
easily be changed by varying R1 or R2.
+15V
C1
10ꢀF
R5
+
5kꢄ
C2
0.1ꢀF
R2
R6
9kꢄ
5kꢄ
R1
1kꢄ
R3
R7
1/4
1/4
50ꢄ
50ꢄ
OP471E
A3
OP471E
A1
V
IN
C3
0.1ꢀF
R4
R8
1/4
1/4
R
L
50ꢄ
50ꢄ
C4
OP471E
A4
OP471E
A2
10ꢀF
+
–15V
Figure 16. High-Output Amplifier
–11–
REV. A
OP471
Quad Programmable Gain Amplifier
where n equals the decimal equivalent of the 8-bit digital code
present at the DAC. If the digital code present at the DAC
consists of all zeros, the feedback loop will be open causing the
op amp output to saturate. The 20 MW resistors placed in parallel
with the DAC feedback loop eliminates this problem with a very
small reduction in gain accuracy.
The combination of the quad OP471 and the DAC8408, a quad
8-bit CMOS DAC, creates a space-saving quad programmable gain
amplifier. The digital code present at the DAC, which is easily
set by a microprocessor, determines the ratio between the fixed
DAC feedback resistor and the impedance the DAC ladder presents
to the op amp feedback loop. Gain of each amplifier is:
VOUT
VIN
256
n
= –
V
DD
DAC-8408ET
R
A
FB
V
A
IN
V
A
REF
+15V
R1
20Mꢄ
I
OUT1A
DAC A
DAC B
1/4
V
A
OUT
OP470E
I
OUT2A/2B
–15V
R
B
FB
V
B
C
IN
B
V
REF
R2
20Mꢄ
I
OUT1B
1/4
V
B
OUT
OP470E
R
C
FB
V
IN
C
V
REF
R3
20Mꢄ
I
OUT1C
DAC C
DAC D
1/4
V
C
OUT
OP470E
I
OUT2C/2D
R
D
FB
V
D
IN
V
D
REF
R4
20Mꢄ
I
OUT1D
1/4
V
D
OUT
OP470E
DAC DATA BUS
PINS 9 (LSB) – 16 (MSB)
DGND
Figure 17. Quad Programmable Gain Amplifier
–12–
REV. A
OP471
R2 = R1
Low Phase Error Amplifier
R2
The simple amplifier depicted in Figure 18 utilizes monolithic
matched operational amplifiers and a few resistors to substan-
tially reduce phase error compared to conventional amplifier
designs. At a given gain, the frequency range for a specified phase
accuracy is over a decade greater than for a standard single op
amp amplifier.
R2
K1
1/4
OP471E
A2
V2
The low phase error amplifier performs second-order frequency
compensation through the response of op amp A2 in the feed-
back loop of A1. Both op amps must be extremely well matched
in frequency response. At low frequencies, the A1 feedback loop
forces V2/(K1 + 1) = VIN. The A2 feedback loop forces Vo/(K1 +1)
R1
K1
1/4
R1
OP471E
A1
V
IN
V
O
= V2/(K1 + 1) yielding an overall transfer function of VO/VIN
K1 + 1. The dc gain is determined by the resistor divider at
=
V
= (K + 1)V
1 IN
O
the output, VO, and is not directly affected by the resistor divider
around A2. Note that similar to a conventional single op amp
amplifier, the dc gain is set by resistor ratios only. Minimum
gain for the low phase error amplifier is 10.
ASSUME: A1 AND A2 ARE MATCHED.
ꢆ
T
A
(s) =
s
O
Figure 18. Low Phase Error Amplifier
Figure 19 compares the phase error performance of the low
phase error amplifier with a conventional single op amp amplifier
and a cascaded two-stage amplifier. The low phase error amplifier
shows a much lower phase error, particularly for frequencies where
0
–1
–2
–3
–4
–5
–6
–7
/T < 0.1. For example, phase error of –0.1∞ occurs at 0.002 /
T
SINGLE OP AMP
(CONVENTIONAL
DESIGN)
for the single op amp amplifier, but at 0.11 /T for the low
phase error amplifier.
For more detailed information on the low phase error amplifier,
see Application Note AN-107.
CASCADED
(TWO STAGES)
LOW-PHASE ERROR
AMPLIFIER
0.001
0.005 0.01
0.05 0.1
0.5
1
FREQUENCY RATIO – 1/ꢇ,
ꢆ/ꢆ
T
Figure 19. Phase Error Comparison
REV. A
–13–
OP471
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14-Lead PDIP Package
(N-14)
0.795 (20.19)
0.725 (18.42)
14
8
7
0.280 (7.11)
0.240 (6.10)
1
0.325 (8.25)
0.300 (7.62)
PIN 1
0.100 (2.54)
BSC
0.060 (1.52)
0.015 (0.38)
0.195 (4.95)
0.115 (2.93)
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
SEATING
0.070 (1.77)
0.045 (1.15)
0.022 (0.558)
0.014 (0.356)
PLANE
14-Lead CERDIP Package
(Q-14)
0.005 (0.13) MIN 0.098 (2.49) MAX
14
8
0.310 (7.87)
0.220 (5.59)
PIN 1
1
7
0.320 (8.13)
0.290 (7.37)
0.100 (2.54) BSC
0.785 (19.94) MAX
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.008 (0.20)
SEATING
0.023 (0.58)
0.014 (0.36)
0.070 (1.78)
0.030 (0.76)
15
0
PLANE
16-Lead SOIC Package
(R-16)
0.4133 (10.50)
0.3977 (10.00)
16
1
9
8
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
0.3937 (10.00)
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
0.0098 (0.25)
0.050 (1.27)
BSC
ꢈ 45ꢁ
8ꢁ
0ꢁ
0.0192 (0.49)
0.0138 (0.35)
0.0118 (0.30)
0.0040 (0.10)
SEATING
0.0500 (1.27)
0.0157 (0.40)
0.0125 (0.32)
0.0091 (0.23)
PLANE
–14–
REV. A
OP471
Revision History
Location
Page
Data Sheet changed from REV. 0 to REV. A.
Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Deleted DICE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Deleted WAFER TEST CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
REV. A
–15–
–16–
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