OP497 [ADI]
Precision Picoampere Input Current Quad Operational Amplifier; 精密Picoampere输入电流四路运算放大器
| 型号： | OP497 |
| 厂家： | 
ADI |
| 描述： | Precision Picoampere Input Current Quad Operational Amplifier |
| 文件： | 总12页 (文件大小：300K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Precision Picoampere Input Current
Quad Operational Amplifier
a
OP497
FEATURES
PIN CONNECTIONS
Low Offset Voltage: 50 V max
Low Offset Voltage Drift: 0.5 V/؇C max
Very Low Bias Current
16-Lead Wide Body SOIC
(S-Suffix)
25؇C: 100 pA max
–55؇C to +125؇C: 450 pA max
OUT D
–IN D
+IN D
OUT A
–IN A
1
2
3
4
5
16
15
14
13
12
11
Very High Open-Loop Gain: 2000 V/mV min
Low Supply Current (per Amplifier): 625 A max
Operates from ؎2 V to ؎20 V Supplies
High Common-Mode Rejection: 120 dB min
–
–
+
+
+
–
–
+IN A
V+
V–
OP497
+IN C
+IN B
–IN B
OUT B
NC
APPLICATIONS
+
–IN C
6
7
8
Strain Gage and Bridge Amplifiers
High Stability Thermocouple Amplifiers
Instrumentation Amplifiers
Photo-Current Monitors
10 OUT C
NC
9
NC = NO CONNECT
High Gain Linearity Amplifiers
Long-Term Integrators/Filters
Sample-and-Hold Amplifiers
Peak Detectors
Logarithmic Amplifiers
Battery-Powered Systems
14-Lead Plastic Dip
(P-Suffix)
14-Lead Ceramic Dip
(Y-Suffix)
GENERAL DESCRIPTION
OUT A
1
2
3
4
5
6
7
14 OUT D
The OP497 is a quad op amp with precision performance in the
space-saving, industry standard 16-lead SOlC package. Its com-
bination of exceptional precision with low power and extremely
low input bias current makes the quad OP497 useful in a wide
variety of applications.
–IN A
+IN A
V+
–IN D
13
12
–
–
+
+
–
–
+IN D
11 V–
OP497
+IN C
+IN B
–IN B
OUT B
10
9
+
+
–IN C
Precision performance of the OP497 includes very low offset,
under 50 µV, and low drift, below 0.5 µV/°C. Open-loop gain
exceeds 2000 V/mV ensuring high linearity in every application.
Errors due to common-mode signals are eliminated by the OP497’s
common-mode rejection of over 120 dB. The OP497’s power
supply rejection of over 120 dB minimizes offset voltage changes
experienced in battery-powered systems. Supply current of the
OP497 is under 625 µA per amplifier, and it can operate with
supply voltages as low as 2 V.
OUT C
8
1000
V
V
= ؎15V
= 0V
S
CM
The OP497 utilizes a superbeta input stage with bias current can-
cellation to maintain picoamp bias currents at all temperatures.
This is in contrast to FET input op amps whose bias currents start
in the picoamp range at 25°C, but double for every 10°C rise in
temperature, to reach the nanoamp range above 85°C. Input bias
current of the OP497 is under 100 pA at 25°C and is under 450
pA over the military temperature range.
100
–I
B
+I
B
I
OS
10
Combining precision, low power, and low bias current, the
OP497 is ideal for a number of applications, including instru-
mentation amplifiers, log amplifiers, photo-diode preamplifiers,
and long-term integrators. For a single device, see the OP97; for a
dual device, see the OP297.
–75
–50
–25
0
25
50
75
100
125
TEMPERATURE –
C
Input Bias, Offset Current vs. Temperature
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
OP497–SPECIFICATIONS (@ V = 15 V, T = 25؇C, unless otherwise noted.)
S
A
A
F
C/G
Parameter
Symbol
Condition
Min Typ Max Min Typ Max Min Typ Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
Vos
20
40
50
40
70
80
75
150
150
80
120 250
140 300
150
µV
–40°C ≤ +85°C
–55°C ≤ +125°C
100
Average Input Offset
Voltage Drift
TCVOS
TMIN – TMAX
0.2 0.5
0.1
0.4 1.0
0.1
0.6 1.5
0.1
µV/°C
Long-Term Input Offset
Voltage Stability
µV/Mo
Input Bias Current
IB
VCM = 0 V
–40° ≤ TA ≤ +85°C
–55° ≤ TA ≤ +125°C
30
100
40
60
110 600
150
200
60
80
130 600
200
300
pA
80
450
Average Input Bias
Current Drift
TCIB
Ios
–40° ≤ TA ≤ +85°C
–55° ≤ TA ≤ +125°C
0.3
0.7
30
50
60
0.3
0.7
50
80
90
0.5
15
pA/°C
pA
Input Offset Current
V
CM = OV
100
400
150
200
600
200
300
600
–40° ≤ TA ≤ +85°C
–55° ≤ TA ≤ +125°C
35
Average Input Offset
Current Drift
TCIOS
IVR
0.2
0.3
+13 tl4
+13 +13.5
114 135
108 120
0.4
pA/°C
V
Input Voltage Range1
+ 13 +14
+13 +13.5
120 140
114 130
+13 +14
+13 +13.5
114 135
108 120
T
MIN – TMAX
VCM 13 V
MIN – TMAX
Common-Mode Rejection CMR
Large Signal Voltage Gain AVO
=
dB
T
VO = 10 V,
RL = 2 kΩ
2000 6000
1500 4000
800 2000
1000 3000
1200 4000
800 2000
800 3000
V/mV
–40° ≤ TA ≤ +85°C
–55° ≤ TA ≤ +125°C 1200 4000
Input Resistance
Differential Mode
Input Resistance
Common Mode
RIN
30
30
30
MΩ
RINCM
CIN
500
3
500
3
500
3
GΩ
pF
Input Capacitance
OUTPUT CHARACTERISTICS
Output Voltage Swing
VO
RL = 2 kΩ
13
13 14
13.7
13
13
13.7
14
13
13
13.7V
14
RL = 10 kΩ
TMIN – TMAX
RL = 10 kΩ
13
13.5
25
13
13.5
25
13
13.5
25
Short Circuit
ISC
mA
dB
POWER SUPPLY
Power Supply
PSRR
Vs = 2 V to 20 V 120 140
Vs = 2.5 V to 20 V
114 135
108 120
114 135
108 120
525 625
580 750
2
2.5
Rejection Ratio
T
MIN – TMAX
No Load
MIN – TMAX
Operating Range
MIN – TMAX
114 130
Supply Current
(per Amplifier)
Supply Voltage Range
ISY
VS
525 625
580 750
20
525 625
580 750
20
µA
T
2
2.5
2
2.5
20
20
V
T
20
20
DYNAMIC PERFORMANCE
Slew Rate
SR
0.05 0.15
500
0.05 0.15
500
0.05 0.15
500
V/µS
kHz
Gain Bandwidth Product GBW
Channel Separation
CS
VO = 20 Vp-p,
fo = 10 Hz
150
150
150
dB
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
en p-p
0.1 Hz to 10 Hz
0.3
17
15
20
0.3
17
15
20
0.3
17
15
20
µV/p-p
nV/√Hz
nV/√Hz
fA/√Hz
en = 10 Hz
en = 1 kHz
in = 10 Hz
Current Noise Density
NOTE
1Guaranteed by CMR Test.
Specifications subject to change without notice.
–2–
REV. D
OP497
ABSOLUTE MAXIMUM RATINGS1
ORDERING GUIDE
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V
Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V
Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 V
Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range
Y Package . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +175°C
P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
OP497A, C (Y) . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
OP497F, G (Y) . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
OP497F, G (P, S) . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature
Y Package . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +175°C
P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . 300°C
Temperature
Range
Package
Description
Package
Option
Model
OP497AY* –55°C to +125°C 14-Lead Cerdip
OP497CY* –55°C to +125°C 14-Lead Cerdip
Q-14
Q-14
OP497FP
OP497FS
–40°C to +85°C
–40°C to +85°C
14-Lead Plastic DIP N-14
16-Lead SOIC R-16
14-Lead Plastic DIP N-14
16-Lead SOIC R-16
OP497GP –40°C to +85°C
OP497GS
–40°C to +85°C
*Not for new design; obsolete April 2002.
For a military processed devices, please refer to the Standard
Microcircuit Drawing (SMD) available at www.dscc.dla.mil/
programs.milspec./default.asp.
3
SMD Part Number
ADI Part Number
Package Type
JA
JC
Unit
5962–9452101M2A*
5962–9452101MCA
OP497BRC
OP497BY
14-Pin Cerdip (Y)
14-Pin Plastic DIP (P)
16-Pin SOIC (S)
NOTES
94
76
92
10
33
23
°C/W
°C/W
°C/W
*Not for new designs; obsolete April 2002.
1Absolute Maximum Ratings apply to both DICE and packaged parts, unless
otherwise noted.
2For supply voltages less than 20 V, the absolute maximum input voltage is
equal to the supply voltage.
DICE CHARACTERISTICS
3HIA is specified for worst-case mounting conditions, i.e., JA is specified for
device in socket for cerdip, P-DIP packages; JA is specified for device soldered
to printed circuit board for SOIC package.
–
1/4
V
1
20V p–p @ 10Hz
OP497
+
2k⍀
50k⍀
50⍀
–
1/4
OP497
V
2
+
V
1
CHANNEL SEPARATION = 20 log
(
)
V
/10000
2
Channel Separation Test Circuit
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the OP497 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. D
–3–
(25؇C, Vs = 15 V, unless otherwise noted.)
OP497–Typical Performance Characteristics
50
40
30
20
10
50
40
30
20
10
0
60
T
V
V
= 25؇C
T
A
= 25؇C
A
S
=
15V
= 0V
V
V
=
CM
15V
= 0V
T = 25؇C
A
S
V
=
15V
= 0V
50
40
30
20
10
0
CM
S
V
CM
0
0
10
20
30
40
50
60
–100–80 –60 –40 –20
0
20 40 60 80 100
–100–80 –60 –40 –20
0
20 40 60 80 100
INPUT OFFSET CURRENT – pA
INPUT OFFSET VOLTAGE – V
INPUT BIAS CURRENT – pA
TPC 3. Typical Distribution of
Input Offset Current
TPC 1. Typical Distribution of
Input Offset Voltage
TPC 2. Typical Distribution of
Input Bias Current
70
60
50
40
30
20
10
0
50
40
30
20
10
0
1000
T
V
= 25 C
= ؎15V
A
V
V
= ؎15V
S
V
= ؎15V
= 0V
S
S
= 0V
CM
V
CM
–I
B
+I
B
100
–I
B
+I
B
I
OS
10
–15
–10
–5
0
5
10
15
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
–75 –50 –25
0
25 50 75 100 125
COMMON-MODE VOLTAGE – Volts
TCV – V/؇C
TEMPERATURE – ؇C
OS
TPC 6. Input Bias Current vs.
Common-Mode Voltage
TPC 4. Typical Distribution of
TCVOS
TPC 5. Input Bias, Offset
Current vs. Temperature
100
10
1
10000
1000
100
؎3
؎2
؎1
0
BALANCED OR UNBALANCED
BALANCED OR UNBALANCED
T
V
V
= 25؇C
= ؎15V
A
V
V
=
15V
S
CM
V
=
15V
S
CM
= 0V
S
V
= 0V
= 0V
CM
–55 C
T
125 C
A
T
= +25 C
1M
A
0.1
10
10
100
1k
10k
100k
1M
10M 100M
1k
10k
100k
10M
100
0
1
2
3
4
5
SOURCE RESISTANCE – ⍀
TIME AFTER POWER APPLIED – Minutes
SOURCE RESISTANCE – ⍀
TPC 9. Effective TCVOS vs.
Source Resistance
TPC 8. Effective Offset Voltage
vs. Source Resistance
TPC 7. Input Offset Voltage
Warm-Up Drift
–4–
REV. D
OP497
1000
100
10
10
1
T = 25؇C
A
T
V
= 25؇C
= 2V TO 20V
A
S
V
= ؎2V TO ؎20V
S
5mV
1s
100
90
CURRENT NOISE
10Hz
VOLTAGE NOISE
1kHz
0.1
10
0%
V
T
= 15V
= 25؇C
S
A
1
0.01
0
2
4
6
8
10
2
3
4
5
6
7
10
10
1
10
100
1000
10
10
10
10
TIME – Secs
FREQUENCY – Hz
SOURCE RESISTANCE – ⍀
TPC 10. Voltage Noise Density
vs. Frequency
TPC 12. 0.1 Hz to 10 Hz Noise Voltage
TPC 11. Total Noise Density vs.
Source Resistance
100
80
10000
1000
100
R
V
= 2k⍀
= ؎15V
= ؎10V
V
C
R
= ؎15V
= 30pF
= 1M⍀
= 25؇C
L
S
S
T
= –55؇C
A
L
L
T
A
= +25C
V
CN
GAIN
T
A
T
= +125؇C
A
60
T
A
= +125؇C
PHASE
40
90
T
T
= +25؇C
A
20
135
180
225
= –55؇C
A
0
–20
–40
V
V
= ؎15V
= ؎10V
S
O
1
10
LOAD RESISTANCE – k⍀
20
100
1k
10k
100k
1M
10M
–15
–10
–5
0
5
10
15
FREQUENCY – Hz
OUTPUT VOLTAGE – V
TPC 13. Open-Loop Gain,
Phase vs. Frequency
TPC 14. Open-Loop Gain vs.
Load Resistance
TPC 15. Open-Loop Gain Linearity
160
140
120
100
80
160
140
120
100
80
35
V
T
= ؎15V
= 25؇C
V
T
= ؎15V
= 25؇C
S
V = ؎15V
S
S
A
T
A
= 25؇C
A
A
30
25
20
15
10
5
= +1
VCL
1%THD
R
= 10k⍀
L
–PSR
+PSR
60
60
40
40
20
20
0
0
0
100
1
10
100
1k
10k
100k
1M
1
10
100
1k
10k
100k 1M
1k
10k
100k
FREQUENCY – Hz
FREQUENCY – Hz
FREQUENCY – Hz
TPC 16. Common-Mode
Rejection vs. Frequency
TPC 17. Power Supply
Rejection vs. Frequency
TPC 18. Maximum Output
Swing vs. Frequency
–5–
REV. D
OP497
+V
S
+V
S
35
30
T
A
= 25؇C
T
A
= 25؇C
V
= ؎15V
= 25؇C
S
R
= 10k⍀
L
–0.5
–1.0
–1.5
–0.5
–1.0
–1.5
T
A
A
= +1
VCL
1%THD
25 fO = 1kHz
20
15
10
5
1.5
1.0
0.5
1.5
1.0
0.5
–V
–V
S
S
0
10
0
؎5
؎10
؎15
؎20
0
؎5
؎10
؎15
؎20
100
LOAD RESISTANCE – ⍀
10k
1k
SUPPLY VOLTAGE – V
SUPPLY VOLTAGE – V
TPC 19. Input Common-Mode
Voltage Range vs. Supply Voltage
TPC 21. Output Voltage Swing vs.
Supply Voltage
TPC 20. Maximum Output Swing
vs. Load Resistance
700
35
1000
100
10
T
= –55 C
A
V
T
=
15V
S
A
30
25
20
15
NO LOAD
= 25 C
+125 C
600
T
A
= +25 C
+25 C
T
A
= +125 C
500
V
= ؎15V
–55 C
S
OUTPUT SHORTED
1
TO GROUND
A
= +1
V
400
300
200
–15
–20
–25
–30
–35
T
A
= +25 C
T
A
= +125 C
0.1
0.01
0.001
T
A
= –55 C
0
؎5
؎10
؎15
؎20
0
1
2
3
4
1
10
100
1k
10k
100k
SUPPLY VOLTAGE – V
TIME FROM OUTPUT SHORT – Mins
TPC 22. Supply Current
(per Amplifier) vs. Supply Voltage
TPC 24. Short-Circuit Current vs.
Time Temperature
TPC 23. Closed-Loop Output
Impedance vs. Frequency
V+
70
V
T
= ؎15V
= 25 C
S
A
60
50
40
30
20
10
0
A
= +1
= 100mV p–p
VCL
V
OUT
V
OUT
2.5k⍀
–IN
2.5k⍀
+IN
10
100
1k
10k
LOAD CAPACITANCE – pF
V–
TPC 25. Small-Signal Overshoot
vs. Capacitance Load
TPC 26. Simplified Schematic Showing One Amplifier
–6–
REV. D
OP497
APPLICATIONS INFORMATION
Extremely low bias current over the full military temperature range
makes the OP497 attractive for use in sample-and-hold amplifiers,
peak detectors, and log amplifiers that must operate over a wide
temperature range. Balancing input resistances is not necessary
with the OP497. Offset voltage and TCVOS are degraded only
minimally by high source resistance, even when unbalanced.
100
90
The input pins of the OP497 are protected against large differen-
tial voltage by back-to-back diodes and current-limiting resistors.
Common-mode voltages at the inputs are not restricted, and may
vary over the full range of the supply voltages used.
10
0%
50s
2V
The OP497 requires very little operating headroom about the
supply rails, and is specified for operation with supplies as low
as 2 V. Typically, the common-mode range extends to within
1 V of either rail. The output typically swings to within 1 V of
the rails when using a 10 kΩ load.
Figure 3. Large-Signal Transient Response (AVCL = 1)
GUARDING AND SHIELDING
To maintain the extremely high input impedances of the OP497,
care must be taken in circuit board layout and manufacturing.
Board surfaces must be kept scrupulously clean and free of mois-
ture. Conformal coating is recommended to provide a humidity
barrier. Even a clean PC board can have 100 pA of leakage currents
between adjacent traces, so guard rings should be used around
the inputs. Guard traces are operated at a voltage close to that
on the inputs, as shown in Figure 4, so that leakage currents
become minimal. In noninverting applications, the guard ring
should be connected to the common-mode voltage at the invert-
ing input. In inverting applications, both inputs remain at ground,
so the guard trace should be grounded. Guard traces should be
on both sides of the circuit board.
AC PERFORMANCE
The OP497’s ac characteristics are highly stable over its full
operating temperature range. Unity-gain small-signal response is
shown in Figure 1. Extremely tolerant of capacitive loading on
the output, the OP497 displays excellent response even with
1000 pF loads (Figure 2).
100
90
UNITY GAIN FOLLOWER
NONINVERTING AMPLIFIER
–
–
1/4
OP497
+
1/4
OP497
+
10
0%
20mV
5s
INVERTING AMPLIFIER
MINI-DIP
BOTTOM VIEW
Figure 1. Small-Signal Transient Response
(CLOAD = 100 pF, AVCL = 1)
1
8
–
1/4
A
OP497
+
B
100
90
Figure 4. Guard Ring Layout and Connections
10
0%
20MV
5s
Figure 2. Small-Signal Transient Response
(CLOAD = 1000 pF, AVCL = 1)
REV. D
–7–
OP497
OPEN-LOOP GAIN LINEARITY
PRECISION CURRENT PUMP
The OP497 has both an extremely high gain of 2000 V/mv mini-
mum and constant gain linearity. This enhances the precision of
the OP497 and provides for very high accuracy in high closed-loop
gain applications. Figure 5 illustrates the typical open-loop gain
linearity of the OP 497 over the military temperature range.
Maximum output current of the precision current pump shown
in Figure 7 is 10 mA. Voltage compliance is 10 V with 15 V
supplies. Output impedance of the current transmitter exceeds
3 MΩ with linearity better than 16 bits.
R3
10k⍀
R1
R
= 10k⍀
= ؎15V
= 0V
L
S
10k⍀
2
3
V
V
R5
10k⍀
–
1/4
OP497
I
OUT
؎10mA
CM
1
R2
10k⍀
V
IN
+
T
A
= +125 C
+15V
8
5
R4
10k⍀
7
T
T
= +25C
1/4
A
OP497
6
V
V
IN
IN
4
I
=
=
= 10mA/V
OUT
R5 100⍀
= –55 C
A
–15V
Figure 7. Precision Current Pump
PRECISION POSITIVE PEAK DETECTOR
In Figure 8, the CH must be of polystyrene, Teflon*, or polyeth-
ylene to minimize dielectric absorption and leakage. The droop
rate is determined by the size of CH and the bias current of the
OP497.
–15
–10
–5
0
5
10
15
OUTPUT VOLTAGE – Volts
Figure 5. Open-Loop Linearity of the OP497
APPLICATIONS
1k⍀
Precision Absolute Value Amplifier
+15V
0.1F
The circuit of Figure 6 is a precision absolute value amplifier
with an input impedance of 30 MΩ. The high gain and low
TCVOS of the OP497 ensure accurate operation with microvolt
input signals. In this circuit, the input always appears as a com-
mon-mode signal to the op amps. The CMR of the OP497
exceeds 120 dB, yielding an error of less than 2 ppm.
1N4148
2
6
8
1/4
OP497
1
2N930
1/4
7
1k⍀
V
3
OUT
OP497
1k⍀
V
IN
5
4
C
0.1F
H
1k⍀
–15V
+15V
RESET
C2
0.1F
R1
1k⍀
R3
1k⍀
Figure 8. Precision Positive Peak Detector
C1
30pF
D1
1N4148
SIMPLE BRIDGE CONDITIONING AMPLIFIER
Figure 9 shows a simple bridge conditioning amplifier using
the OP497. The transfer function is:
6
5
8
1/4
OP497
2
3
7
1/4
OP497
1
0V < V
< 10V
OUT
D2
1N4148
R2
2k⍀
V
C3
0.1F
IN
∆R RF
4
VOUT =V
REF
R + ∆R R
–15V
The REF43 provides an accurate and stable reference voltage
for the bridge. To maintain the highest circuit accuracy, RF
should be 0.1% or better with a low temperature coefficient.
Figure 6. Precision Absolute Value Amplifier
*Teflon is a registered trademark of the Dupont Company.
–8–
REV. D
OP497
+5V
2
C2
100pF
V
REF
2.5 V
R
6
R
F
REF43
R2
33k⍀
R
6
4
2
3
1/4
OP497
7
1/4
OP497
V
OUT
1
V
OUT
I
O
5
R + ⌬R
R
1
2
Q1
7
6
3
+5V
Q2
6
5
R
R
5
14
⌬R
R + ⌬R
F
MAT-04E
8
V
OUT
= V
REF
(
)
13
8
1/4
I
7
Q4
REF
9
OP497
4
Q3
10
V+
C1
12
R1
133k⍀
100pF
I
IN
2
3
8
V
IN
–5V
1/4
OP497
1
R3
50k⍀
R4
50k⍀
Figure 9. A Simple Bridge Conditioning Amplifier Using
the OP497
4
–15V
V–
NONLINEAR CIRCUITS
Figure 10. Squaring Amplifier
Due to its low input bias currents, the OP497 is an ideal log
amplifier in nonlinear circuits such as the square and square
root circuits shown in Figures 10 and 11. Using the squaring
circuit of Figure 10 as an example, the analysis begins by writing a
voltage-loop equation across transistors Q1, Q2, Q3, and Q4.
A similar analysis made for the square-root circuit of Figure 11
leads to its transfer function:
V
I
REF
(
IN )(
)
VOUT = R2
R1
In these circuits, IREF is a function of the negative power sup-
ply. To maintain accuracy, the negative supply should be well
regulated. For applications where very high accuracy is required,
a voltage reference may be used to set IREF. An important con-
sideration for the squaring circuit is that a sufficiently large
input voltage can force the output beyond the operating range
S1
IIN
I
IIN
I
IO
IS3
IREF
IS4
VT1In
+VT 2In
=VT 3In I
+VT 4In
S2
All the transistors of the MAT04 are precisely matched and at
the same temperature, so the IS and VT terms cancel, giving:
of the output op amp. Resistor R4 can be changed to scale IREF
,
or Rl and R2 can be varied to keep the output voltage within
the usable range.
2InIIN = InIO + InIREF = In I × I
Exponentiating both sides of thick equation leads to:
(
)
O
REF
R2
33k⍀
2
)
I
(
IN
C2
IO
=
100pF
6
5
IREF
1/4
7
V
OUT
I
O
OP497
Op amp A2 forms a current-to-voltage converter which gives
OUT = R2 × IO. Substituting (VIN/R1) for IIN and the above
equation for IO, yields:
V
1
Q1
2
I
MAT-04E
REF
I
IN
3
7
C1
2
14
Q4
12
100pF
R2 VIN
13
8
VOUT
=
V+
I
R1
REF
6
9
Q2
5
Q3
R1
33k⍀
10
8
2
3
V
IN
1/4
1
OP497
R5
2k⍀
R3
50k⍀
R4
50k⍀
4
V–
–15V
Figure 11. Square-Root Amplifier
Unadjusted accuracy of the square-root circuit is better than
0.1% over an input voltage range of 100 mV to 10 V. For a
similar input voltage range, the accuracy of the squaring circuit
is better than 0.5%.
REV. D
–9–
OP497
OP497 SPICE MACRO-MODEL
The model uses typical parameters for the OP497. The poles and
zeros in the model were determined from the actual open and
closed-loop gain and phase response of the OP497. In this way,
the model presents an accurate ac representation of the actual
device. The model assumes an ambient temperature of 25°C.
Figure 12 and Table I show the node and net list for a SPICE
macro-model of the OP497. The model is a simplified version of
the actual device and simulates important dc parameters such as
VOS, IOS, IB, AVO, CMR, VO, and ISY. AC parameters such as slew
rate, gain and phase response, and CMR change with frequency
are also simulated by the model.
99
V1
13
؎
R3
5
R4
6
D3
12
C2
R
8
7
2
IN2
Q1
Q2
–IN
C3
G1
R7
R1
R2
10
11
D1
D2
98
C
I
OS
IN
R5
R6
D4
؎
E
REF
R
IN1
14
V2
– +
+IN
9
1
؎
I
E
1
OS
50
CCM
CNZ
RNZ1
RCM1
19
20
15
16
17
18
C5
R10
C5
R15
؎
؎
ECM
RCM2
ENZ
RNZ2
G2
G2
98
99
D7
D8
G5
R16
21
G6
G7
R18
I
SY
V3
D5
23
24
+ –
L1
V
20
O
22
27
– +
D6
25 26
G4
V4
R17
R19
D9
D10
50
Figure 12. OP497 Macro Model
–10–
REV. D
OP497
Table I. OP497 SPICE Net-List
* NEGATIVE ZERO AT 1.8 MHz
* Node assignments
*
*
*
*
*
*
noninverting input
inverting input
*
E1
R8
C4
R9
*
17 98
17 18
17 18
18 98
12 21
1E6
–88.419E-15
1
1E6
positive supply
negative supply
output
*SUBCKT OP497
1
2
99
50 27
* POLE AT 6 MHz
*
*
* INPUT STAGE AND POLE AT 6 MHz
*
G2
R15
C8
*
98 19
20 98
20 98
18 21
1E6
26.526E-15
1E-6
RIN1 1
7
2500
RIN2 2
8
2500
R1
R2
R3
R4
CIN
C2
I1
8
7
5
6
7
5
4
7
3
3
99
99
8
6
50
8
7
8
6.782E8
6.782E8
542.57
542.57
3E-12
24.445E-12
0.1E-3
15E-12
POLY(1) 16
10 QX
11 QX
25.374
25.374
DX
* POLE AT 1.8 MHz
*
G6
R20
C10
*
98 20
20 98
20 98
19 21
1E6
88.419E-15
1E-6
* OUTPUT STAGE
*
IOS
EOS 9
21 40E-6
1
R16
R17
ISY
V3
D5
V4
D6
D7
G4
D9
D8
G5
D10
G6
R18
G7
R19
L1
99 21
21 50
99 50
23 22
20 23
22 24
24 20
99 25
25 50
50 25
99 26
26 50
50 26
22 99
99 22
50 22
22 50
22 27
160 k
160 k
331E-6
1.9
DX
1.9
DX
DX
20 22
DY
DX
22 20
DY
99 20
200
20 50
200
0.1E-6
Q1
Q2
R5
R6
D1
D2
*
5
6
10
11
8
9
4
4
9
9
8
DX
EREF98
*
0
21
0
1
5E-3
*GAIN STAGE AND DOMINANT POLE AT 0.11 Hz
*
R7
C3
G1 98
V1
V2
D3 12
D4 14
*
5E-3
5E-3
5E-3
1
2
98
98
12
13
9
2.1703E9
666.67E-12
5
1.275
1.275
DX
99
11
13
12
DX
*
* MODELS USED
*COMMON-MODE GAIN NETWORK WITH ZERO AT 50 MHz
*
*
.MODEL QX NPN (BF = 1.25E6)
.MODEL DX (IS = 1E-15)
.MODEL DZ D(IS = 1E-15 BV = 50)
.ENDS OP497
RCM1 15 16
CCM 15 16
RCM2 16 98
ECM 15 98
1E6
3.18E-9
1
3
21
177.83E-3
REV. D
–11–
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14-Lead Ceramic DIP
(Y-Suffix)
16-Lead Wide-Body SOIC
(S-Suffix)
0.005 (0.13)
0.098 (2.49)
MAX
0.4133 (10.50)
0.3977 (10.00)
MIN
14
1
8
7
16
1
9
8
PIN 1
0.2992 (7.60)
0.2914 (7.40)
0.060 (1.52)
0.015 (0.38)
0.310 (7.87)
0.220 (5.59)
0.4193 (10.65)
0.3937 (10.00)
0.785 (19.94) MAX
0.200 (5.08)
MAX
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
0.0098 (0.25)
0.050 (1.27)
BSC
0.150
(3.81)
MIN
؋
45؇ 0.320 (8.13)
0.290 (7.37)
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.008 (0.20)
8؇
0؇
0.023 (0.58) 0.100 0.070 (1.78)
0.014 (0.36) (2.54) 0.030 (0.76)
BSC
0°–15°
0.0192 (0.49)
0.0138 (0.35)
0.0118 (0.30)
0.0040 (0.10)
SEATING
PLANE
0.0500 (1.27)
0.0157 (0.40)
0.0125 (0.32)
0.0091 (0.23)
SEATING PLANE
14-Lead Epoxy DIP
(P-Suffix)
14
1
8
0.280 (7.11)
0.240 (6.10)
PIN 1
7
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
MIN
0.795 (20.19)
0.725 (18.41)
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.015 (0.38)
0.008 (0.20)
0.160 (4.06)
0.115 (2.92) 0.022 (0.558)
0.014 (0.36)
0.100
(2.54)
BSC
0.070 (1.77)
0.045 (1.15)
0°–15°
Revision History
Location
Page
11/01—Data Sheet changed from REV. C to REV. D.
Edits to PIN CONNECTIONS headings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Deleted WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
–12–
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