OP77BIFJ [ADI]
IC OP-AMP, 100 uV OFFSET-MAX, 0.6 MHz BAND WIDTH, MBCY8, TO-99, 8 PIN, Operational Amplifier;
| 型号： | OP77BIFJ |
| 厂家： | 
ADI |
| 描述： | IC OP-AMP, 100 uV OFFSET-MAX, 0.6 MHz BAND WIDTH, MBCY8, TO-99, 8 PIN, Operational Amplifier 放大器 |
| 文件： | 总16页 (文件大小：218K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Next Generation OP07 Ultralow
Offset Voltage Operational Amplifier
OP77
FEATURES
PIN CONNECTIONS
Outstanding gain linearity
1
2
3
4
8
7
6
5
V
TRIM
–IN
V
TRIM
OS
OP77
OS
Ultrahigh gain, 5000 V/mV min
Low VOS over temperature, 55 μV max
Excellent TCVOS, 0.3 μV/°C max
High PSRR, 3 μV/V max
V+
+IN
V–
OUT
NC
TOP VIEW
(Not to Scale)
NC = NO CONNECT
Low power consumption, 60 mW max
Fits OP07, 725,108A/308A, 741 sockets
Available in die form
Figure 1. 8-Pin Hermetic
DIP_Q-8 (Z Suffix)
V
TRIM
OS
8
V
TRIM
V+
OS
7
5
1
3
OP77
2
6
–IN
OUT
+IN
NC
4
4V– (CASE)
TOP VIEW
(Not to Scale)
NC = NO CONNECT
Figure 2. TO-99
(J Suffix)
GENERAL DESCRIPTION
The OP77 significantly advances the state-of-the-art in
precision op amps. The outstanding gain of 10,000,000 or more
for the OP77 is maintained over the full 10 V output range. This
exceptional gain-linearity eliminates incorrectable system
nonlinearities common in previous monolithic op amps and
provides superior performance in high closed-loop gain
applications. Low initial VOS drift and rapid stabilization time,
combined with only 50 mW of power consumption, are
significant improvements over previous designs. These
characteristics, plus the exceptional TCVOS of 0.3 μV/°C
maximum and the low VOS of 25 μV maximum, eliminates the
need for VOS adjustment and increases system accuracy over
temperature.
A PSRR of 3 μV/V (110 dB) and CMRR of 1.0 μV/V maximum
virtually eliminate errors caused by power supply drifts and
common-mode signals. This combination of outstanding
characteristics makes the OP77 ideally suited for high resolution
instrumentation and other tight error budget systems.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2002–2010 Analog Devices, Inc. All rights reserved.
OP77
TABLE OF CONTENTS
Features .............................................................................................. 1
Thermal Resistance.......................................................................6
ESD Caution...................................................................................6
Typical Performance Characteristics ..............................................7
Test Circuits..................................................................................... 10
Applications..................................................................................... 11
Precision Current Sinks............................................................. 12
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 16
Pin Connections ............................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Electrical Specifications............................................................... 3
Wafer Test Limits.......................................................................... 4
Typical Electrical Characteristics ............................................... 5
Absolute Maximum Ratings............................................................ 6
REVISION HISTORY
4/10—Rev. D to Rev. E
Removed Figure 33 and Two Subsequent Paragraphs............... 12
6/09—Rev. C to Rev. D
Changes to Figure 1 and Figure 2................................................... 1
Changes to Table 1............................................................................ 3
Removed Endnote 1 and Endnote 2 in Table 3 ............................ 4
Changes to Figure 16........................................................................ 9
Changes to Figure 31 and Figure 32............................................. 12
Changes to Figure 38...................................................................... 14
Moved Figure 39 ............................................................................. 14
10/02—Rev. B to Rev. C
Edits to Specifications ...................................................................... 2
Figure 2 Caption Changed ............................................................ 10
Figure 3 Caption Changed ............................................................ 10
Edits to Figure 10............................................................................ 11
Updated Outline Dimensions....................................................... 15
2/02—Rev. A to Rev. B
Remove 8-Lead SO PIN Connection Diagrams........................... 1
Changes to Absolute Maximum Rating......................................... 2
Remove OP77B column from Specifications................................ 2
Remove OP77B column from Electrical Characteristics ........ 3, 5
Remove OP77G column from Wafer Test Limits......................... 6
Remove OP77G column from Typical Electrical Characteristics6
Rev. E | Page 2 of 16
OP77
ELECTRICAL SPECIFICATIONS
@ VS = 15 V, TA = 25°C, unless otherwise noted.
Table 1.
OP77E
Typ
10
OP77F
Typ
20
Parameter
Symbol
VOS
Conditions
Min
Max
Min
Max
Unit
μV
INPUT OFFSET VOLTAGE
LONG-TERM STABILITY1
INPUT OFFSET CURRENT
INPUT BIAS CURRENT
INPUT NOISE VOLTAGE2
INPUT NOISE VOLTAGE DENSITY
25
60
VOS/time
IOS
0.3
0.4
μV/Mo
nA
0.3
1.5
0.3
2.8
IB
−0.2
+1.2
0.35
10.3
10.0
9.6
+2.0
0.6
−0.2
+1.2
0.38
10.5
10.2
9.8
+2.8
0.65
20.0
13.5
11.5
35
nA
enp-p
en
0.1 Hz to 10 Hz
fO = 10 Hz
fO = 100 Hz2
fO = 1000 Hz
0.1 Hz to 10 Hz
fO = 10 Hz
μVp-p
nV/√Hz
18.0
13.0
11.0
30
INPUT NOISE CURRENT2
inp-p
in
14
15
pAp-p
INPUT NOISE CURRENT DENSITY
0.32
0.14
0.12
0.80
0.23
0.17
0.35
0.15
0.13
0.90
0.27
0.18
pA√Hz
fO = 100 Hz2
fO = 1000 Hz
INPUT RESISTANCE
Differential Mode3
Common Mode
RIN
RINCM
IVR
26
13
45
200
14
18.5
13
45
200
14
MΩ
GΩ
INPUT VOLTAGE RANGE
COMMON-MODE REJECTION RATIO
POWER SUPPLY REJECTION RATIO
LARGE-SIGNAL VOLTAGE GAIN
V
CMRR
PSRR
AVO
VCM = 13 V
VS = 3 V to 18 V
RL ≥ 2 kΩ
0.1
0.7
1.0
3.0
0.1
0.7
1.6
3.0
μV/V
μV/V
V/mV
5000 12,000
2000 6000
VO = 10 V
RL ≥ 10 kΩ
RL ≥ 2 kΩ
OUTPUT VOLTAGE SWING
VO
13.5
12.5
12.0
14.0
13.0
12.5
13.5
12.5
12.0
14.0
13.0
12.5
V
RL ≥ 1 kΩ
SLEW RATE2
SR
BW
RO
RL ≥ 2 kΩ
0.1
0.4
0.3
0.1
0.4
0.3
V/μs
MHz
Ω
CLOSED-LOOP BANDWIDTH2
OPEN-LOOP OUTPUT RESISTANCE
POWER CONSUMPTION
AVCL + 1
0.6
60
50
3.5
3
0.6
60
50
3.5
3
Pd
VS = 15 V, no load
VS = 3 V, no load
Rp = 20 kn
60
4.5
60
4.5
mW
OFFSET ADJUSTMENT RANGE
mV
1 Long-term input offset voltage stability refers to the averaged trend line of VOS vs. time over extended periods after the first 30 days of operation. Excluding the initial
hour of operation, changes in VOS during the first 30 operating days are typically 2.5 μV.
2 Sample tested.
3 Guaranteed by design.
Rev. E | Page 3 of 16
OP77
@ VS = 15 V, −25°C ≤ TA ≤ +85°C for OP77FJ and OP77E/OP77F, unless otherwise noted.
Table 2.
OP77E
OP77F
Parameter
Symbol Conditions
Min
Typ
10
Max Min
Typ
Max Unit
INPUT OFFSET VOLTAGE
AVERAGE INPUT OFFSET VOLTAGE DRIFT1
VOS
45
20
100
0.6
4.5
85
μV
TCVOS
IOS
0.1
0.5
1.5
+2.4
8
0.3
0.2
μV/°C
nA
INPUT OFFSET CURRENT
2.2
0.5
AVERAGE INPUT OFFSET CURRENT DRIFT2
INPUT BIAS CURRENT
TCIOS
IB
4.0
1.5
pA/°C
−0.2
+4.0 −0.2
40
+2.4
+6.0 nA
AVERAGE INPUT BIAS CURRENT DRIFT2
TCIB
IVR
15
13.5
60
pA/°C
INPUT VOLTAGE RANGE
13.0
13.5
13.0
V
COMMON-MODE REJECTION RATIO
POWER SUPPLY REJECTION RATIO
LARGE-SIGNAL VOLTAGE GAIN
CMRR
PSRR
AVO
VCM = 13 V
0.1
1.0
1.0
3.0
0.1
3.0
5.0
pV/V
μV/V
V/mV
VS = 3 V to 18 V
RL ≥ 2 kΩ
1.0
2000 6000
1000 4000
VO = 10 V
OUTPUT VOLTAGE SWING
POWER CONSUMPTION
VO
Pd
RL ≥ 2 kΩ
12
13.0
60
12
13.0
60
V
VS = 15 V, no load
75
75
mW
1 OP77E: TCVOS is 100% tested on J and Z packages.
2 Guaranteed by end-point limits.
WAFER TEST LIMITS
@ VS = 15 V, TA = 25°C, for OP77NBC devices, unless otherwise noted.
Table 3.
Parameter
Symbol
Conditions
OP77NBC Limit
Unit
INPUT OFFSET VOLTAGE
INPUT OFFSET CURRENT
INPUT BIAS CURRENT
VOS
IOS
IB
40
2.0
2
μV max
nA max
nA max
INPUT RESISTANCE
Differential Mode
RIN
26
MΩ min
V min
INPUT VOLTAGE RANGE
COMMON-MODE REJECTION RATIO
POWER SUPPLY REJECTION RATIO
OUTPUT VOLTAGE SWING
IVR
13
CMRR
PSRR
VO
VCM = 13 V
VS = 3 V to 18 V
RL = 10 kΩ
RL = 2 kΩ
1
μV/V max
μV/V max
V min
3
13.5
12.5
12.0
2000
RL = 1 kΩ
LARGE-SIGNAL VOLTAGE GAIN
AVO
RL = 2 kΩ
V/mV min
VO = 10 V
DIFFERENTIAL INPUT VOLTAGE
POWER CONSUMPTION
30
60
V max
Pd
VO = 0 V
mW max
Rev. E | Page 4 of 16
OP77
TYPICAL ELECTRICAL CHARACTERISTICS
@ VS = 15 V, TA = 25°C, unless otherwise noted.
Table 4.
Parameter
Symbol
TCVOS
TCVOSn
TCIOS
SR
Conditions
OP77NBC Limit
Unit
AVERAGE INPUT OFFSET VOLTAGE DRIFT
NULLED INPUT OFFSET VOLTAGE DRIFT
AVERAGE INPUT OFFSET CURRENT DRIFT
SLEW RATE
RS = 50 Ω
0.1
0.1
0.5
0.3
0.6
μV/°C
μV/°C
pA/°C
V/μs
RS = 50 Ω, RP = 20 kΩ
RL ≥ 2 kΩ
AVCL + 1
BANDWIDTH
BW
MHz
Rev. E | Page 5 of 16
OP77
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 5.
Parameter1
Rating
Supply Voltage
22 V
Differential Input Voltage
Input Voltage2
30 V
22 V
Output Short-Circuit Duration
Storage Temperature Range
Operating Temperature Range
Junction Temperature (TJ)
Lead Temperature (Soldering, 60 sec)
Indefinite
−65°C to +150°C
−25°C to +85°C
−65°C to +150°C
300°C
THERMAL RESISTANCE
Table 6.
Package Type
1
θJA
θJC
18
16
Unit
°C/W
°C/W
1Absolute Maximum Ratings apply to both dice and packaged parts, unless
otherwise noted.
8-Pin TO-99 H-08 (J Suffix)
8-Lead Hermetic CERDIP Q-8 (Z Suffix)
150
148
2For supply voltages less than 22 V, the absolute maximum input voltage is
equal to the supply voltage.
1θJA is specified for worst-case mounting conditions, i.e., θJA is specified for a
device in socket for the TO-99 and CERDIP packages.
ESD CAUTION
Rev. E | Page 6 of 16
OP77
TYPICAL PERFORMANCE CHARACTERISTICS
2
30
20
V
= ±15V
= 25°C
= 10kΩ
S
J, Z PACKAGES
+0.3µV/°C
T
A
R
L
1
0
MEAN
S.D.
10
0
–10
–1
–2
–20
–30
–0.3µV/°C
–10
–5
0
5
10
–55
–35
–15
5
25
45
65
85
105
125
OUTPUT VOLTAGE (V)
TEMPERATURE (°C)
Figure 3. Gain Linearity (Input Voltage vs. Output Voltage)
Figure 6. Untrimmed Offset Voltage vs. Temperature
25
4
V
T
= ±15V
= 25°C
V
= ±15V
S
A
S
3
2
1
0
20
15
10
5
–1
–2
–3
–4
0
–55
–35
–15
5
25
45
65
85
105
125
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
TEMPERATURE (°C)
TIME AFTER POWER SUPPLY TURN-ON (Minutes)
Figure 4. Open-Loop Gain vs. Temperature
Figure 7. Warm-Up Drift
16
30
25
20
15
T
R
= 25°C
= 2kΩ
A
V
= ±15V
S
L
DEVICE IMMERSED IN
70°C OIL BATH (20 UNITS)
12
8
MAXIMUM
10
5
4
0
AVERAGE
MIMIMUM
0
–10
0
±5
±10
±15
±20
0
10
20
30
40
50
60
70
POWER SUPPLY VOLTAGE (V)
TIME (Seconds)
Figure 5. Open-Loop Gain vs. Power Supply Voltage
Figure 8. Offset Voltage Change Due to Thermal Shock
Rev. E | Page 7 of 16
OP77
100
80
130
120
110
100
V
T
= ±15V
= 25°C
S
A
T
= 25°C
A
60
40
90
80
70
20
0
60
0.1
–20
10
1
10
100
1k
10k
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 9. Closed-Loop Response for Various Gain Configurations
Figure 12. PSRR vs. Frequency
160
0
4
V
T
= ±15V
= 25°C
S
A
V
= ±15V
S
140
120
100
80
45
90
3
2
60
40
20
0
135
180
1
0
–75
0.01
0.1
1
10
100
1k
10k
100k
1M
–50
–25
0
25
50
75
100
125
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 10. Open-Loop Gain/Phase Response
Figure 13. Input Bias Current vs. Temperature
150
140
130
120
2.0
T
A
= 25°C
V
= ±15V
S
1.5
1.0
110
100
90
0.5
0
80
1
10
100
1k
10k
100k
–75
–50
–25
0
25
50
75
100
125
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 11. CMRR vs. Frequency
Figure 14. Input Offset Current vs. Temperature
Rev. E | Page 8 of 16
OP77
10
100
V
T
= ±15V
= 25°C
T
= 25°C
S
A
A
1
10
0.1
100
1
1k
10k
100k
0
10
20
30
40
FREQUENCY (Hz)
TOTAL SUPPLY VOLTAGE V+ TO V– (V)
Figure 15. Input Wideband Noise vs. Bandwidth (0.1 Hz to Frequency
Indicated)
Figure 18. Power Consumption vs. Power Supply
1k
20
RS1 = RS2 = 200kΩ
V
T
= ±15V
= 25°C
= ±10mV
S
A
THERMAL NOISE OF SOURCE
RESISTORS
INCLUDED
V
IN
POSITIVE SWING
NEGATIVE SWING
15
10
EXCLUDED
100
R
= 0
S
10
5
0
V
T
= ±15V
= 25°C
S
A
1
1
10
100
1k
100
1k
LOAD RESISTANCE TO GROUND (Ω)
10k
FREQUENCY (Hz)
Figure 19. Maximum Output Voltage vs. Load Resistance
Figure 16. Total Input Noise Voltage vs. Frequency
40
32
V
T
= ±15V
= 25°C
V
T
= ±15V
= 25°C
S
A
S
A
28
24
20
16
35
30
25
20
15
12
8
4
0
0
1
2
3
4
1k
10k
100k
1M
TIME FROM OUTPUT BEING SHORTENED (Minutes)
FREQUENCY (Hz)
Figure 20. Output Short-Circuit Current vs. Time
Figure 17. Maximum Output Swing vs. Frequency
Rev. E | Page 9 of 16
OP77
TEST CIRCUITS
200kΩ
TYPICAL PRECISION
OP AMP
50Ω
10kΩ
100kΩ
V
Y
V
O
OP77
1MΩ
10Ω
V
= ±10V
IN
V
V
X
O
V
=
V
OS
X
4000
–10V
0V
+10V
R
L
Figure 21. Typical Offset Voltage Test Circuit
A
650V/mV
VO
R
= 2kΩ
L
2.5MΩ
NOTES
1. GAIN NOT CONSISTANT. CAUSES NONLINEAR ERRORS.
2. A SPEC IS ONLY PART OF THE SOLUTION.
V+
VO
100Ω
100Ω
2
3
7
3. CHECK SPECIFICATION TABLE 1 AND TABLE 2 FOR PERFORMANCE.
3.3kΩ
6
OUTPUT
(≈10Hz FILTER)
Figure 25. Open-Loop Gain Linearity
OP77
4.7µF
4
Actual open-loop voltage gain can vary greatly at various output
voltages. All automated testers use endpoint testing and therefore
only show the average gain. This causes errors in high closed-
loop gain circuits. Because this is difficult for manufacturers to
test, users should make their own evaluations. This simple test
circuit makes it easy. An ideal op amp would show a horizontal
scope trace.
V–
V
O
INPUT REFERRED NOISE =
25,000
Figure 22. Typical Low-Frequency Noise Test Circuit
20kΩ
V+
1
2
8
V
Y
–
7
6
OUTPUT
INPUT
+
OP77
3
4
V–
Figure 23. Optional Offset Nulling Circuit
V
–10V
0V
+10V
X
100kΩ
+18V
+
*
10µF
2
10Ω
0.1µF
Figure 26. Output Gain Linearity Trace
7
This is the output gain linearity trace for the new OP77. The
output trace is virtually horizontal at all points, assuring
extremely high gain accuracy. The average open-loop gain is
truly impressive—approximately 10,000,000.
6
OP77
3
4
10kΩ
10kΩ
0.1µF
10Ω
*
10µF
+
–18V
NOTES
*
1 PER BOARD
Figure 24. Burn-In Circuit
Rev. E | Page 10 of 16
OP77
APPLICATIONS
R2
1MΩ
R3
+15V
+15V
0.1µF
R1
1kΩ
R1
R2
2
3
2N2222
2
3
V
7
IN
6
6
OP77
OP77E
2N2907
4
R5
R3
1kΩ
0.1µF
R4
R4
–15V
1MΩ
I
< 100mA
OUT
R3
R1 – R5
GIVEN R3 = R4 + R5, R1 = R2
I
= V
–15V
OUT
IN
(
)
Figure 27. Precision High-Gain Differential Amplifier
Figure 30. 100 mA Current Source
The high gain, gain linearity, CMRR, and low TCVOS of the
OP77 make it possible to obtain performance not previously
available in single-stage, very high-gain amplifier applications.
These current sources can supply both positive and negative
current into a grounded load.
Note that
R1
R2
R3
R4
For best CMR,
must equal
. In this example, with a
R4
R2
⎛
⎜
⎝
⎞
⎟
⎠
R3
R5
+ 1
10 mV differential signal, the maximum errors are as listed in
Table 7.
ZO
=
R5 + R4
R2
R1
Table 7. Maximum Errors
Type
Amount
0.01%/V
0.02%
R5 + R4
R2
R3
R1
And that for ZO to be infinite
must =
Common-Mode Voltage
Gain Linearity, Worst Case
TCVOS
TCIOS
0.003%/°C
0.008%/°C
R
F
10µF
+15V
0.1µF
R
S
2
3
7
INPUT
100Ω
6
OUTPUT
OP77
4
C
LOAD
0.1µF
–15V
Figure 28. Isolating Large Capacitive Loads
This circuit reduces maximum slew rate but allows driving
capacitive loads of any size without instability. Because the boon
resistor is inside the feedback loop, its effect on output
impedance is reduced to insignificance by the high open-loop
gain of the OP77.
R3
1kΩ
R1
100kΩ
2
3
V
IN
6
I
< 15mA
OP77
OUT
R5
10Ω
R2
100kΩ
R4
990Ω
Figure 29. Basic Current Source
Rev. E | Page 11 of 16
OP77
R1
PRECISION CURRENT SINKS
V+
200Ω
IRF520
OP77
V
R
IN
L
I
=
O
V
IN
R1
> 0V
V
IN
I
O
I
=
V
O
IN
R1
> 0V
V
IN
I
200Ω
O
V
IN
IRF520
OP77
FULL SCALE OF 1V.
= 1A/V
R
L
I
O
R1
1Ω
1W
V–
Figure 32. Positive Current Source
The simple high-current sinks, shown Figure 31 and Figure 32,
require the load to float between the power supply and the sink.
Figure 31. Positive Current Sink
In these circuits, the high gain, high CMRR, and low TCVOS of
the OP77 ensure high accuracy.
The high gain and low TCVOS ensure accurate operation with
inputs from microvolts to volts. In Figure 33, the signal always
appears as a common-mode signal to the op amps. The
OP77EZ CMRR of 1 μV/V ensures errors of less than 2 ppm.
1kΩ
1kΩ
+15V
+15V
0.1µF
C1
D1
0.1µF
30pF
1N4148
2
3
7
6
2
3
7
V
D2
OUT
0 < V
OP77E
< 10V
6
OUT
OP77E
4
2N4393
V
IN
0.1µF
4
R3
2kΩ
0.1µF
–15V
–15V
Figure 33. Precision Absolute Value Amplifier
15V
2
2
2
+
10µF
REF-01
REF-01
REF-01
V
OP77
OUT
100Ω
6
6
6
V
V
V
O
O
O
4
4
4
100Ω
100Ω
0.1µF
Figure 34. Low Noise Precision Reference
Rev. E | Page 12 of 16
OP77
Figure 34 relies upon low TCVOS of the OP77 and noise
combined with very high CMRR to provide precision buffering
of the averaged REF-01 voltage outputs.
In Figure 35, CH must be of polystyrene, Teflon*, or
polyethylene to minimize dielectric absorption and leakage.
The droop rate is determined by the size of CH and the bias
current of the AD820.
*Teflon is a registered trademark of the Dupont Company
1kΩ
+15V
+15V
1N4148
0.1µF
0.1µF
2
3
7
2
3
7
6
6
2N930
OP77
V
AD820
4
1kΩ
OUT
1kΩ
V
IN
4
0.1µF
C
H
0.1µF
RESET
–15V
–15V
Figure 35. Precision Positive Peak Detector
Rev. E | Page 13 of 16
OP77
C
+15V
0.1µF
C
+15V
0.1µF
R
F
2
100kΩ
V
IN
R
R
c
a
6
5
R
V
O
S
D1
1N4148
1kΩ
2
3
7
50kΩ
TRIM
V
TH
6
R1
2kΩ
V
OUT
OP77
REF-02
V
OUT
R
R
OP77
b1
V
1.5kΩ
IN
3
4
TEMP
GND
4
0.1µF
0.1µF
bp
–15V
–15V
Figure 36. Precision Threshold Detector/Amplifier
Figure 37. Precision Temperature Sensor
When VIN < VTH, amplifier output swings negative, reversing the
biasing diode D1. VO = VTH if RL= ∞ when VIN > VTH, the loop
closes,
Table 8. Resistor Values
TCVOUT Slope (S)
10 mV/°C
100 mV/°C 10 mV/°F
Temperature Range −55°C to
+125°C
−55°C to
+125°C
−67°F to
+257°C
⎛
⎞
⎟
⎟
⎠
RF
RS
⎜
VIN − VTH 1+
VO = VTH
+
(
)
⎜
Output Voltage
Range
−0.55 V to
+1.25 V
−5.5 V to
+12.5V
−0.67 V to
+2.57V
⎝
CC is selected to smooth the response of the loop.
Zero-Scale
0 V @ 0°C
9.09 kΩ
1.5 kΩ
200 Ω
5.11 kΩ
0 V @ 0°C
15 kΩ
0 V @ 0°F
7.5 kΩ
Ra ( 1% Resistor)
Rb1 ( 1% Resistor)
Rbp (Potentiometer)
Rc ( 1% Resistor)
1.82 kΩ
500 Ω
1.21 kΩ
200 Ω
84.5 kΩ
8.25 kΩ
7
V+
1
(OPTIONAL
NULL)
1
R2A
R2B
R1B
R7
C1
1
8
R1A
Q19
Q9
Q10
Q11 Q12
C2
R9
6
Q7
Q8
OUTPUT
Q3 Q6
Q4
Q5
Q17
C3
R5
R10
Q27
Q16
Q15
3
2
R3
R4
NONINVERTING
INPUT
Q20
Q26
Q25
Q1
Q21
Q22
Q23
Q24
INVERTING
INPUT
Q2
Q18
Q14
R6 R8
Q13
4
V–
1
R2A AND R2B ARE ELECTRONICALLY ADJUSTED ON CHIP AT FACTORY.
Figure 38. Simplified Schematic
Rev. E | Page 14 of 16
OP77
OUTLINE DIMENSIONS
0.005 (0.13)
MIN
0.055 (1.40)
MAX
8
5
0.310 (7.87)
0.220 (5.59)
1
4
0.100 (2.54) BSC
0.405 (10.29) MAX
0.320 (8.13)
0.290 (7.37)
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
15°
0°
0.070 (1.78)
0.030 (0.76)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 39. 8-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-8)
Dimensions shown in inches and (millimeters)
REFERENCE PLANE
0.5000 (12.70)
MIN
0.1850 (4.70)
0.1650 (4.19)
0.1000 (2.54)
BSC
0.2500 (6.35) MIN
0.0500 (1.27) MAX
0.1600 (4.06)
0.1400 (3.56)
5
6
8
4
0.2000
(5.08)
BSC
3
7
0.0450 (1.14)
0.0270 (0.69)
2
1
0.1000
(2.54)
BSC
0.0190 (0.48)
0.0160 (0.41)
0.0340 (0.86)
0.0280 (0.71)
0.0400 (1.02) MAX
0.0210 (0.53)
0.0160 (0.41)
0.0400 (1.02)
0.0100 (0.25)
45° BSC
BASE & SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-002-AK
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 40. 8-Pin Metal Header [TO-99]
(H-08)
Dimensions shown in inches and (millimeters)
Rev. E | Page 15 of 16
OP77
ORDERING GUIDE
Model1
OP77FJ
Temperature Range
Package Description
Package Option
H-08 (J Suffix)
H-08 (J Suffix)
Q-8 (Z Suffix)
Q-8 (Z Suffix)
−25°C to +85°C
−25°C to +85°C
−25°C to +85°C
−25°C to +85°C
8-Pin Metal Header [TO-99]
8-Pin Metal Header [TO-99]
8-Lead Ceramic Dual In-Line Package [CERDIP]
8-Lead Ceramic Dual In-Line Package [CERDIP]
Die
OP77FJZ
OP77EZ
OP77FZ
OP77NBC
1 Z = RoHS Compliant Part.
©2002–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00320-0-4/10(E)
Rev. E | Page 16 of 16
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