OPZ467GPZ [ADI]
IC QUAD OP-AMP, 1000 uV OFFSET-MAX, 22 MHz BAND WIDTH, PDIP14, PLASTIC, MS-001, DIP-14, Operational Amplifier;
| 型号： | OPZ467GPZ |
| 厂家： | 
ADI |
| 描述： | IC QUAD OP-AMP, 1000 uV OFFSET-MAX, 22 MHz BAND WIDTH, PDIP14, PLASTIC, MS-001, DIP-14, Operational Amplifier 放大器 光电二极管 |
| 文件： | 总20页 (文件大小：481K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad Precision, High
Speed Operational Amplifier
OP467
FEATURES
PIN CONFIGURATIONS
High slew rate: 170 V/μs
OUT A
–IN A
+IN A
V+
1
2
3
4
5
6
7
14 OUT D
13 –IN D
Wide bandwidth: 28 MHz
Fast settling time: <200 ns to 0.01%
Low offset voltage: <500 μV
Unity-gain stable
Low voltage operation: 5 V to 15 V
Low supply current: <10 mA
Drives capacitive loads
+
+
+IN D
12
11 V–
OP467
+IN B
–IN B
OUT B
10 +IN C
+
+
9
8
–IN C
OUT C
Figure 1. 14-Lead CERDIP (Y Suffix) and 14-Lead PDIP (P Suffix)
APPLICATIONS
High speed image display drivers
High frequency active filters
Fast instrumentation amplifiers
High speed detectors
Integrators
Photo diode preamps
3
2
1
20 19
+IN A
NC
4
5
6
7
8
18 +IN D
1
2
3
4
5
6
7
8
16
OUT A
–IN A
+IN A
V+
OUT D
17
16
15
14
NC
15 –IN D
OP467
(TOP VIEW)
V+
V–
14
13
12
11
10
9
+IN D
V–
NC
NC
OP467
+IN C
+IN B
+IN B
–IN B
OUT B
NC
+IN C
–IN C
OUT C
NC
9
10 11 12 13
GENERAL DESCRIPTION
The OP467 is a quad, high speed, precision operational
amplifier. It offers the performance of a high speed op amp
combined with the advantages of a precision op amp in a single
package. The OP467 is an ideal choice for applications where,
traditionally, more than one op amp was used to achieve this
level of speed and precision.
NC = NO CONNECT
NC = NO CONNECT
Figure 2. 16-Lead SOIC (S Suffix)
Figure 3. 20-Terminal LCC (RC Suffix)
V+
The internal compensation of the OP467 ensures stable unity-
gain operation, and it can drive large capacitive loads without
oscillation. With a gain bandwidth product of 28 MHz driving a
30 pF load, output slew rate is 170 V/μs, and settling time to
0.01% in less than 200 ns, the OP467 provides excellent
dynamic accuracy in high speed data acquisition systems. The
channel-to-channel separation is typically 60 dB at 10 MHz.
+IN
OUT
–IN
The dc performance of the OP467 includes less than 0.5 mV of
offset, a voltage noise density below 6 nV/√Hz, and a total
supply current under 10 mA. The common-mode rejection
ratio (CMRR) is typically 85 dB. The power supply rejection
ratio (PSRR) is typically 107 dB. PSRR is maintained to better than
40 dB with input frequencies as high as 1 MHz. The low offset and
drift plus high speed and low noise make the OP467 usable in
applications such as high speed detectors and instrumentation.
V–
Figure 4. Simplified Schematic
The OP467 is specified for operation from 5 V to 15 V over
the extended industrial temperature range (−40°C to +85°C)
and is available in a 14-lead PDIP, a 14-lead CERDIP, a 16-lead
SOIC, and a 20-terminal LCC.
Contact your local sales office for the MIL-STD-883 data sheet
and availability.
Rev. *
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
3–20 Analog Devices, Inc. All rights reserved.
©
OP467
TABLE OF CONTENTS
Features .............................................................................................. 1
Output Short-Circuit Performance.......................................... 13
Unused Amplifiers ..................................................................... 13
PCB Layout Considerations...................................................... 13
Grounding................................................................................... 13
Power Supply Considerations................................................... 13
Signal Considerations................................................................ 13
Phase Reversal ............................................................................ 14
Saturation Recovery Time......................................................... 14
High Speed Instrumentation Amplifier .................................. 14
2 MHz Biquad Band-Pass Filter ............................................... 15
Fast I-to-V Converter ................................................................ 16
OP467 SPICE Marco-Model..................................................... 17
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 20
Applications....................................................................................... 1
General Description......................................................................... 1
Pin Configurations ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Wafer Test Limits.......................................................................... 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
Dice Characteristics ..................................................................... 6
ESD Caution.................................................................................. 6
Typical Performance Characteristics ............................................. 7
Applications Information .............................................................. 13
REVISION HISTORY
4/10—Rev. H to Rev. I
3/04—Rev. D to Rev. E
Deleted Endnote 2 From Table 1.................................................... 3
Changes to TPC 1..............................................................................5
Changes to Ordering Guide.............................................................4
Updated Outline Dimensions....................................................... 16
8/09—Rev. G to Rev. H
Changes to Table 4............................................................................ 6
4/01—Rev. C to Rev. D
4/09—Rev. F to Rev. G
Changes to Power Supply Considerations Section..................... 13
Footnote added to Power Supply.....................................................2
Footnote added to Max Ratings ......................................................4
Edits to Power Supply Considerations Section........................... 11
5/07—Rev. E to Rev. F
Updated Format..................................................................Universal
Changes to General Description .................................................... 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Changes to Table 3............................................................................ 5
Updated Outline Dimensions....................................................... 19
Changes to Ordering Guide .......................................................... 20
Rev. I | Page 2 of 20
OP467
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
@ VS = ±±15. V, TA = 21°C, unless otherwise noted5
Table 1.
Parameter
Symbol
Conditions
Min
Typ
Max Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
IB
0.2
0.5
1
600
700
100
150
mV
mV
nA
nA
nA
−40°C ≤ TA ≤ +85°C
VCM = 0 V
VCM = 0 V, −40°C ≤ TA ≤ +85°C
VCM = 0 V
Input Bias Current
150
150
10
Input Offset Current
IOS
VCM = 0 V, −40°C ≤ TA ≤ +85°C
10
nA
Common-Mode Rejection
Large Signal Voltage Gain
CMR
CMR
AVO
VCM
VCM
RL = 2 kΩ
=
=
12 V
80
80
83
90
88
86
dB
dB
dB
12 V, −40°C ≤ TA ≤ +85°C
RL = 2 kΩ, −40°C ≤ TA ≤ +85°C
77.5
dB
Offset Voltage Drift
Bias Current Drift
Long-Term Offset Voltage Drift1
ΔVOS/ΔT
ΔIB/ΔT
ΔVOS/ΔT
3.5
0.2
μV/°C
pA/°C
μV
750
OUTPUT CHARACTERISTICS
Output Voltage Swing
VO
RL = 2 kΩ
RL = 2 kΩ, −40°C ≤ TA ≤ +85°C
13.0
12.9
13.5
13.12
V
V
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
ISY
4.5 V ≤ VS ≤ 18 V
−40°C ≤ TA ≤ +85°C
VO = 0 V
96
86
120
115
8
dB
dB
mA
mA
V
Supply Current
10
13
18
VO = 0 V, −40°C ≤ TA ≤ +85°C
Supply Voltage Range
VS
4.5
DYNAMIC PERFORMANCE
Gain Bandwidth Product
Slew Rate
GBP
SR
AV = +1, CL = 30 pF
VIN = 10 V step, RL = 2 kΩ, CL = 30 pF
AV = +1
AV = −1
VIN = 10 V step
28
MHz
125
170
350
2.7
200
45
V/μs
V/μs
MHz
ns
Full-Power Bandwidth
Settling Time
Phase Margin
BWρ
tS
θ0
To 0.01%, VIN = 10 V step
Degrees
Input Capacitance
Common Mode
Differential
2.0
1.0
pF
pF
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
eN p-p
eN
iN
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
0.15
6
0.8
μV p-p
nV/√Hz
pA/√Hz
1 Long-term offset voltage drift is guaranteed by 1000 hrs. Life test performed on three independent wafer lots at 125°C, with an LTPD of 1.3.
Rev. I | Page 3 of 20
OP467
@ VS = ±±5. V, TA = 2±°C, unless otherwise noted5
Table 2.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
IB
0.3
0.5
1
600
700
100
150
mV
mV
nA
nA
nA
nA
dB
dB
dB
−40°C ≤ TA ≤ +85°C
VCM = 0 V
VCM = 0 V, −40°C ≤ TA ≤ +85°C
VCM = 0 V
VCM = 0 V, −40°C ≤ TA ≤ +85°C
VCM = 2.0 V
VCM = 2.0 V, −40°C ≤ TA ≤ +85°C
RL = 2 kΩ
Input Bias Current
125
150
20
Input Offset Current
IOS
Common-Mode Rejection
Large Signal Voltage Gain
CMR
CMR
AVO
76
76
80
74
85
80
83
RL = 2 kΩ, −40°C ≤ TA ≤ +85°C
dB
Offset Voltage Drift
Bias Current Drift
ΔVOS/ΔT
ΔIB/ΔT
3.5
0.2
μV/°C
pA/°C
OUTPUT CHARACTERISTICS
Output Voltage Swing
VO
RL = 2 kΩ
RL = 2 kΩ, −40°C ≤ TA ≤ +85°C
3.0
3.0
3.5
3.20
V
V
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
ISY
4.5 V ≤ VS ≤ 5.5 V
−40°C ≤ TA ≤ +85°C
VO = 0 V
92
83
107
105
8
dB
dB
mA
mA
Supply Current
10
12
VO = 0 V, −40°C ≤ TA ≤ +85°C
DYNAMIC PERFORMANCE
Gain Bandwidth Product
Slew Rate
GBP
SR
AV = +1
22
MHz
VIN = 5 V step, RL = 2 kΩ, CL = 39 pF
AV = +1
AV = −1
VIN = 5 V step
To 0.01%, VIN = 5 V step
90
90
2.5
280
45
V/μs
V/μs
MHz
ns
Full-Power Bandwidth
Settling Time
Phase Margin
BWρ
tS
θ0
Degrees
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
eN p-p
eN
iN
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
0.15
7
0.8
μV p-p
nV/√Hz
pA/√Hz
Rev. * | Page 4 of 20
OP467
WAFER TEST LIMITS1
@ VS = ±ꢀ±5. V, TA = 2±°C, unless otherwise noted5
Table 3.
Parameter
Symbol
Conditions
Limit
0.5
600
100
12
80
96
83
13.0
10
Unit
Offset Voltage
VOS
IB
IOS
mV max
nA max
nA max
V min/max
dB min
dB min
dB min
V min
Input Bias Current
Input Offset Current
Input Voltage Range2
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage Range
Supply Current
VCM = 0 V
VCM = 0 V
CMRR
PSRR
AVO
VO
ISY
VCM = 12 V
V = 4.5 V to 18 V
RL = 2 kΩ
RL = 2 kΩ
VO = 0 V, RL = ∞
mA max
1 Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard
product dice. Consult sales to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
2 Guaranteed by CMR test.
Rev. * | Page 5 of 20
OP467
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter1
Rating
18 V
18 V
26 V
Limited
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device5 This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied5 Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability5
Supply Voltage
Input Voltage2
Differential Input Voltage2
Output Short-Circuit Duration
Storage Temperature Range
14-Lead CERDIP and 20-Terminal LCC
14-Lead PDIP and 16-Lead SOIC
Operating Temperature Range
OP467A
−65°C to +175°C
−65°C to +150°C
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages5
−55°C to +125°C
−40°C to +85°C
OP467G
Junction Temperature Range
14-Lead CERDIP and 20-Terminal LCC
14-Lead PDIP and 16-Lead SOIC
Lead Temperature (Soldering, 60 sec)
Table 5.
Package Type
−65°C to +175°C
−65°C to +150°C
300°C
1
θJA
94
76
88
78
θJC
10
33
23
33
Unit
°C/W
°C/W
°C/W
°C/W
14-Lead CERDIP (Y)
14-Lead PDIP (P)
16-Lead SOIC (S)
20-Terminal LCC (RC)
1 θJA is specified for the worst-case conditions, that is, θJA is specified for device
in socket for CERDIP, PDIP, and LCC packages, and θJA is specified for device
soldered in circuit board for the SOIC package.
1 Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2 For supply voltages less than 18 V, the absolute maximum input voltage is
equal to the supply voltage.
DICE CHARACTERISTICS
–IN A
2
1
14
–IN D
13
+IN A
V+
3
4
12 +IN D
11
V–
+IN B
–IN B
5
6
10 +IN C
7
8
9
–IN C
Figure 5. 0.111 Inch × 0.100 Inch DIE Size, 11,100 sq. mils,
Substrate Connected to V+, 165 Transistors
ESD CAUTION
Rev. * | Page 6 o f 20
OP467
TYPICAL PERFORMANCE CHARACTERISTICS
100
80
60
40
20
0
80
V
T
= ±15V
= 25°C
S
A
V
R
C
= ±15V
= 1MΩ
= 30pF
S
70
60
50
L
L
A
= +100
VCL
GAIN
40
30
20
10
0
–90
PHASE
A
= +10
VCL
–135
–180
A
= +1
VCL
–10
–20
100
1k
10k
FREQUENCY (Hz)
100k
1M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 6. Open-Loop Gain, Phase vs. Frequency
Figure 9. Closed-Loop Output Impedance vs. Frequency
80
V
T
= ±15V
= 25°C
S
A
0.3
60
40
20
0
V
= ±5V
S
0.2
0.1
0.0
V
= ±15V
S
–0.1
–0.2
–0.3
0
100k
3.4
5.8
–20
10k
1M
FREQUENCY (Hz)
10M
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 7. Closed-Loop Gain vs. Frequency
Figure 10. Gain Error vs. Frequency
25
30
25
20
15
10
5
A
= –1
VCL
20
15
10
5
T
= +125°C
A
A
= +1
VCL
T
= +25°C
A
T
= –55°C
A
V
T
R
= ±15V
= 25°C
= 2kΩ
S
A
L
0
0
1k
10k
100k
FREQUENCY (Hz)
1M
10M
0
±5
±10
±15
±20
SUPPLY VOLTAGE (V)
Figure 11. Maximum VOUT Swing vs. Frequency
Figure 8. Open-Loop Gain vs. Supply Voltage
Rev. * | Page 7 of 20
OP467
12
10
8
60
50
40
30
20
10
0
V
T
R
= ±5V
= 25°C
= 2kΩ
V
= ±15V
= 2kΩ
= 100mV p-p
S
S
A
= +1
VCL
R
V
A
L
L
VIN
A
= +1
VCL
A
= –1
VCL
A
= –1
VCL
6
4
2
0
1k
10k
100k
FREQUENCY (Hz)
1M
10M
10M
1M
0
200
400
600
800
1000
1200
1400
1600
LOAD CAPACITANCE (pF)
Figure 12. Maximum VOUT Swing vs. Frequency
Figure 15. Small Signal Overshoot vs. Load Capacitance
120
100
80
60
40
20
0
60
50
40
30
20
10
0
V
S
T
A
= ±15V
= 25°C
V
R
V
= ±15V
= 2kΩ
S
A
= +1
VCL
L
= 100mV p-p
VIN
A
= –1
VCL
1k
10k
100k
1M
0
200
400
600
800
1000
1200
1400
1600
FREQUENCY (Hz)
LOAD CAPACITANCE (pF)
Figure 13. Common-Mode Rejection vs. Frequency
Figure 16. Small Signal Overshoot vs. Load Capacitance
120
100
80
60
V
= ±15V
V
= ±15V
= 25°C
S
S
A
50
40
T
30
1000pF
500pF
200pF
20
10000pF
60
10
0
40
–10
–20
–30
–40
C
= NETWORK
ANALYZER
IN
20
0
100
1k
10k
100k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 14. Power-Supply Rejection vs. Frequency
Figure 17. Noninverting Gain vs. Capacitive Loads
Rev. * | Page 8 of 20
OP467
0
4
3
V
= ±15V
S
V
V
C
= ±15V
= ±5V
= 50pF
S
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
IN
L
2
1
0
–1
–2
–3
–4
100
1k
10k
100k
1M
10M
100M
0
100
200
300
400
500
FREQUENCY (Hz)
TIME (ns)
Figure 18. Channel Separation vs. Frequency
Figure 21. Settling Time, Negative Edge
12
4
3
V
V
= ±15V
S
±5V ≤ V ≤ 15V
S
= ±5V
IN
10
8
C
= 50pF
L
2
1
0
6
–1
–2
–3
–4
4
2
0
1
10
100
FREQUENCY (Hz)
1k
0
100
200
300
400
500
TIME (ns)
Figure 19. Input Current Noise Density vs. Frequency
Figure 22. Settling Time, Positive Edge
100
20
15
T
= 25°C
A
10
5
10
0
–5
–10
–15
–20
1.0
0.1
1
10
100
1k
10k
0
±5
±10
±15
±20
FREQUENCY (Hz)
SUPPLY VOLTAGE (V)
Figure 20. Voltage Noise Density vs. Frequency
Figure 23. Input Voltage Range vs. Supply Voltage
Rev. * | Page 9 of 20
OP467
500
400
300
200
100
0
50
40
V
= ±15V
= 25°C
S
V
V
R
C
= ±15V
= ±5V
= 10kΩ
= 50pF
S1
S2
T
A
1252 × OP AMPS
L
L
30
20
V
= ±15V
S1
10
0
–10
–20
–30
–40
–50
V
= ±5V
S2
–100 –50
0
50
100 150 200 250 300 350 400
µV)
10k
100k
1M
FREQUENCY (Hz)
10M
100M
INPUT OFFSET VOLTAGE (V
OS
Figure 24. Noninverting Gain vs. Supply Voltage
Figure 27. Input Offset Voltage Distribution
500
400
300
200
100
0
14
12
10
8
V
= ±5V
= 25°C
V
T
= ±15V
= 25°C
S
S
A
T
A
1252 × OP AMPS
POSITIVE
SWING
6
NEGATIVE
SWING
4
2
0
10
–100 –50
0
50
100 150 200 250 300 350 400
µV)
100
1k
10k
INPUT OFFSET VOLTAGE (V
LOAD RESISTANCE (Ω)
OS
Figure 25. Output Swing vs. Load Resistance
Figure 28. Input Offset Voltage Distribution
500
400
300
200
100
0
5
4
3
2
V
T
= ±15V
= 25°C
V
T
= ±15V
= 25°C
S
S
A
A
1252 × OP AMPS
POSITIVE
SWING
NEGATIVE
SWING
1
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
10
100
1k
10k
LOAD RESISTANCE (Ω)
TC V (µV/°C)
OS
Figure 26. Output Swing vs. Load Resistance
Figure 29. TC VOS Distribution
Rev. * | Page 10 of 20
OP467
500
400
300
200
100
0
400
V
= ±5V
= 25°C
S
V
R
A
= ±5V
S
T
A
= 2kΩ
350
300
250
200
150
100
50
L
1252 × OP AMPS
= +1
VCL
+SR
–SR
0
–75
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
–50
–25
0
25
50
75
100
125
TC V (µV/°C)
OS
TEMPERATURE (°C)
Figure 30. TC VOS Distribution
Figure 33. Slew Rate vs. Temperature
60
55
50
45
40
29.0
28.5
28.0
650
V
R
A
= ±15V
S
= 2kΩ
600
550
500
450
400
350
300
250
L
GBW
= –1
VCL
–SR
V
R
= ±5V
= 2kΩ
S
L
+SR
ФM
27.5
27.0
–75
–50
–25
0
25
50
75
100
125
–75
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 31. Phase Margin and Gain Bandwidth vs. Temperature
Figure 34. Slew Rate vs. Temperature
400
400
V
R
A
= ±15V
S
V
R
A
= ±5V
S
= 2kΩ
L
= 2kΩ
350
300
250
200
150
100
50
L
350
300
250
200
150
100
50
= +1
VCL
= –1
VCL
+SR
–SR
+SR
–SR
0
–75
0
–75
–50
–25
0
25
50
75
100
125
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 32. Slew Rate vs. Temperature
Figure 35. Slew Rate vs. Temperature
Rev. * | Page 11 of 20
OP467
10
8
5
200
160
120
R
A
= 5kΩ
= 25°C
F
V = ±15V
S
4
T
0.1%
6
3
0.1%
4
2
2
1
0
0
–5
–4
–3
90
40
0
–2
–4
–6
–8
0.1%
0.1%
–2
–1
–10
0
100
200
SETTLING TIME (ns)
300
400
–75
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 36. Output Step vs. Settling Time
Figure 38. Input Bias Current vs. Temperature
25
20
15
V
= ±15V
S
10
8
T
= +125°C
A
T
= +25°C
A
6
T
= –55°C
A
10
5
4
2
0
0
–75
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
0
±5
±10
±15
±20
SUPPLY VOLTAGE (V)
Figure 37. Supply Current vs. Supply Voltage
Figure 39. Input Offset Current vs. Temperature
Rev. * | Page 12 of 20
OP467
APPLICATIONS INFORMATION
On the other hand, ceramic chip capacitors have excellent ESR
and effective series inductance (ESL) performance at higher
frequencies, and because of their small size, they can be placed
very close to the device pin, further reducing the stray inductance5
Best results are achieved by using a combination of these two
capacitors5 A ± μF to ꢀ. μF tantalum parallel capacitor with a
.5ꢀ μF ceramic chip capacitor is recommended5 If additional
isolation from high frequency resonances of the power supply is
needed, a ferrite bead should be placed in series with the supply
lines between the bypass capacitors and the power supply5 Note
that addition of the ferrite bead introduces a new pole and zero
to the frequency response of the circuit and could cause unstable
operation if it is not selected properly5
OUTPUT SHORT-CIRCUIT PERFORMANCE
To achieve a wide bandwidth and high slew rate, the OP467
output is not short-circuit protected5 Shorting the output to
ground or to the supplies may destroy the device5
For safe operation, the output load current should be limited so
that the junction temperature does not exceed the absolute
maximum junction temperature5
The maximum internal power dissipation can be calculated by
TJ max −TA
PD =
θJA
where:
+V
TJ and TA are junction and ambient temperatures, respectively5
S
+
PD is device internal power dissipation5
10µF TANTALUM
θJA is the packaged device thermal resistance given in the data sheet5
0.1µF CERAMIC CHIP
UNUSED AMPLIFIERS
It is recommended that any unused amplifiers in the quad
package be connected as a unity-gain follower with a ꢀ kΩ
feedback resistor with noninverting input tied to the ground plain5
0.1µF CERAMIC CHIP
10µF TANTALUM
PCB LAYOUT CONSIDERATIONS
–V
S
Satisfactory performance of a high speed op amp largely
depends on a good PCB layout5 To achieve the best dynamic
performance, follow the high frequency layout technique5
Figure 40. Recommended Power Supply Bypass
SIGNAL CONSIDERATIONS
GROUNDING
Input and output traces need special attention to assure a
minimum stray capacitance5 Input nodes are very sensitive to
capacitive reactance, particularly when connected to a high
impedance circuit5 Stray capacitance can inject undesirable
signals from a noisy line into a high impedance input5 Protect
high impedance input traces by providing guard traces around
them, which also improves the channel separation significantly5
A good ground plain is essential to achieve the optimum
performance in high speed applications5 It can significantly
reduce the undesirable effects of ground loops and IR drops by
providing a low impedance reference point5 Best results are
obtained with a multilayer board design with one layer assigned
to the ground plain5 To maintain a continuous and low impedance
ground, avoid running any traces on this layer5
Additionally, any stray capacitance in parallel with the input
capacitance of the op amp generates a pole in the frequency
response of the circuit5 The additional phase shift caused by this
pole reduces the gain margin of the circuit5 If this pole is within
the gain range of the op amp, it causes unstable performance5 To
reduce these undesirable effects, use the lowest impedance
where possible5 Lowering the impedance at this node places the
poles at a higher frequency, far above the gain range of the
amplifier5 Stray capacitance on the PCB can be reduced by making
the traces narrow and as short as possible5 Further reduction
can be realized by choosing a smaller pad size, increasing the
spacing between the traces, and using PCB material with a low
dielectric constant insulator (dielectric constant of some common
insulators: air = ꢀ, Teflon® = 252, and FR4 = 457, with air being
an ideal insulator)5
POWER SUPPLY CONSIDERATIONS
In high frequency circuits, device lead length introduces an
inductance in series with the circuit5 This inductance, combined
with stray capacitance, forms a high frequency resonance circuit5
Poles generated by these circuits cause gain peaking and additional
phase shift, reducing the phase margin of the op amp and leading
to an unstable operation5
A practical solution to this problem is to reduce the resonance
frequency low enough to take advantage of the power supply
rejection of the amplifier5 This is easily done by placing capacitors
across the supply line and the ground plane as close as possible
to the device pin5 Because capacitors also have internal parasitic
components, such as stray inductance, selecting the right capacitor
is important5 To be effective, they should have low impedance
over the frequency range of interest5 Tantalum capacitors are an
excellent choice for their high capacitance/size ratio, but their
effective series resistance (ESR) increases with frequency
making them less effective5
Removing segments of the ground plane directly under the
input and output pads is recommended5
Rev. * | Page 13 of 20
OP467
Outputs of high speed amplifiers are very sensitive to capacitive
loads5 A capacitive load introduces a pair of pole and zero to the
frequency response of the circuit, reducing the phase margin,
leading to unstable operation or oscillation5
DLY 9.824µs
100
90
Generally, it is good design practice to isolate the output of the
amplifier from any capacitive load by placing a resistor between
the output of the amplifier and the rest of the circuits5 A series
resistor of ꢀ. ꢁ to ꢀ.. ꢁ is normally sufficient to isolate the
output from a capacitive load5
10
0%
The OP467 is internally compensated to provide stable
operation and is capable of driving large capacitive loads
without oscillation5
5V
5V
20ns
Figure 42. Saturation Recovery Time, Positive Rail
Sockets are not recommended because they increase the lead
inductance/capacitance and reduce the power dissipation of the
package by increasing the thermal resistance of the leads5 If
sockets must be used, use Teflon or pin sockets with the shortest
possible leads5
DLY 4.806µs
100
90
PHASE REVERSAL
The OP467 is immune to phase reversal; its inputs can exceed
the supply rails by a diode drop without any phase reversal5
10
ΔV1
15.8V
0%
100
90
5V
5V
20ns
OUTPUT
Figure 43. Saturation Recovery Time, Negative Rail
HIGH SPEED INSTRUMENTATION AMPLIFIER
The OP467 performance lends itself to a variety of high speed
applications, including high speed precision instrumentation
amplifiers5 Figure 44 represents a circuit commonly used for
data acquisition, CCD imaging, and other high speed
applications5
10
INTPUT
0%
10V
10V
200µs
The circuit gain is set by RG5 A 2 kΩ resistor sets the circuit gain
to 2; for unity gain, remove RG5 For any other gain settings, use
the following formula
Figure 41. No Phase Reversal (AV = +1)
SATURATION RECOVERY TIME
The OP467 has a fast and symmetrical recovery time from
either rail5 This feature is very useful in applications such as
high speed instrumentation and measurement circuits, where
the amplifier is frequently exposed to large signals that overload
the amplifier5
G = 2/RG (Resistor Value is in kΩ)
RC is used for adjusting the dc common-mode rejection, and CC
is used for ac common-mode rejection adjustments5
–V
IN
C
C
2kΩ
1kΩ
1kΩ
2kΩ
2kΩ
R
10kΩ
G
OUTPUT
1.9kΩ
R
5pF
C
10kΩ
200Ω
10T
+V
IN
Figure 44. A High Speed Instrumentation Amplifier
Rev. * | Page 14 of 20
OP467
2 MHz BIQUAD BAND-PASS FILTER
0.01% 10V STEP
= ±15V
V
S
NEG SLOPE
The circuit in Figure 48 is commonly used in medical imaging
ultrasound receivers5 The 3. MHz bandwidth is sufficient to
accurately produce the 2 MHz center frequency, as the measured
response shows in Figure 495 When the bandwidth of the op
amp is too close to the center frequency of the filter, the internal
phase shift of the amplifier causes excess phase shift at 2 MHz,
which alters the response of the filter5 In fact, if the chosen op
amp has a bandwidth close to 2 MHz, the combined phase shift
of the three op amps causes the loop to oscillate5
2.5mV
–2.5mV
Careful consideration must be given to the layout of this circuit
as with any other high speed circuit5
Figure 45. Instrumentation Amplifier Settling Time to 0.01% for a
10 V Step Input (Negative Slope)
If the phase shift introduced by the layout is large enough, it can
alter the circuit performance, or worse, cause oscillation5
0.01% 10V STEP
V
= ±15V
S
R6
1kΩ
POS SLOPE
C1
50pF
R2
2.5mV
R4
2kΩ
C2
50pF
2kΩ
–2.5mV
R1
3kΩ
R3
2kΩ
1/4
OP467
R5
2kΩ
2kΩ
1/4
OP467
1/4
OP467
1/4
OP467
V
OUT
V
Figure 46. Instrumentation Amplifier Settling Time to 0.01% for a
10 V Step Input (Positive Slope)
IN
Figure 48. 2 MHz Biquad Filter
+V
S
+
0
–10
–20
–30
–40
2kΩ
2kΩ
+
TO
INPUT
AD9617
1kΩ
ERROR
TO SCOPE
TO
IN-AMP
OUTPUT
–V
S
549Ω
61.9Ω
Figure 47. Settling Time Measurement Circuit
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 49. Biquad Filter Response
Rev. * | Page 15 of 20
OP467
+5V
+10V
V
V
R
I
1
2
3
4
5
6
7
8
9
DGND
28
27
26
25
24
23
22
21
DD
+10V
DAC8408
A
V
C
C
REF
REF
A
R
FB
C1
10pF
C3
10pF
FB
2
3
I
OUT 1C
13
12
OUT 1A
1
14
OUT A
OP467
+15V
OUT D
OUT C
OP467
OP467
I
I
I
OUT 2C/
OUT 2A/
OUT 2B
I
OUT 2D
I
I
OUT 1B
OUT 1D
R
V
B
R
D
D
FB
FB
0.1µF
0.1µF
9
4
B
V
REF
6
5
8
REF
C4
10pF
7
OUT B
OP467
10
+10V
C2
10pF
+10V
DB0 (LSB)
DS2 20
11
DS1
R/W
19
18
10 DB1
11 DB2
DIGITAL
CONTROL
SIGNALS
–15V
DB3
DB4
DB5
12
13
14
A/B 17
(MSB) DB7
16
DB6 15
Figure 50. Quad DAC Unipolar Operation
FAST I-TO-V CONVERTER
251.0ns
The fast slew rate and fast settling time of the OP467 are well
suited to the fast buffers and I-to-V converters used in a variety
of applications5 The circuit in Figure ±. is a unipolar quad DAC
consisting of only two ICs5 The current output of the DAC84.8
is converted to a voltage by the OP467 configured as an I-to-V
converter5 This circuit is capable of settling to .5ꢀ% within 2.. ns5
Figure ±ꢀ and Figure ±2 show the full-scale settling time of the
outputs5 To obtain reliable circuit performance, keep the traces
from the IOUT of the DAC to the inverting inputs of the OP467
short to minimize parasitic capacitance5
100
90
10
0%
2V
50mV
100ns
260.0ns
Figure 52. Rising Edge Output Settling Time
DAC8408
100
90
DC OFFSET
R
FB
3pF
2kΩ
I-V
OP467
I
OUT
2kΩ
50kΩ
1kΩ
AD847
604Ω
60.4kΩ
10
0%
Figure 53. DAC VOUT Settling Time Circuit
2V
50mV
100ns
Figure 51. Falling Edge Output Settling Time
Rev. * | Page 16 of 20
OP467
OP467 SPICE MARCO-MODEL
* Node assignments
*
noninverting input
* COMMON-MODE STAGE WITH ZERO AT 1.26 kHz
*
inverting input
positive supply
negative supply
ECM
R8
R9
C3
*
13 98
13 14
14 98
13 14
POLY (2) (1, 20)
1E6
25 . 119
(2,20) 0 0. 5 0 . 5
output
126 . 721E–12
*
. SUBCKT OP467
*
1
2
99
50
27
*POLE AT 400E6
*
* INPUT STAGE
*
R10
C4
G2
*
15
15
98
98
98
15
1E6
0 . 398E–15
(10,20) 1E–6
I1
4
5
0
10E–3
CIN
IOS
Q1
Q2
R3
1
1
5
6
99
99
8
2
2
2
7
5
6
4
4
1
0
1E–12
5E–9
8 QN
9 QN
185 . 681
185 . 681
180 . 508
180 . 508
POLY (1)
(20,0) 1
* OUTPUT STAGE
*
ISY
RMP1
RMP2
RO1
RO2
L1
GO1
GO2
G4
G5
V3
V4
D3
D4
D5
D6
D7
D8
*
99
99
20
99
26
26
26
50
23
24
21
26
15
22
99
99
50
50
50
20
50
26
50
27
99
26
50
50
26
22
21
15
23
24
23
24
–8 . 183E–3
96 . 429E3
96 . 429E3
200
200
1E–7
(99,15) 5E–3
(15,50) 5E–3
(15,26) 5E–3
(26,15) 5E–3
50
50
DX
DX
DX
DX
DY
DY
R4
R5
R6
9
EOS
EREF
*
7
98
(14,20)
50E–6
1
* GAIN STAGE AND DOMINANT POLE AT 1.5 kHz
*
R7
C2
G1
V1
V2
D1
D2
RC
CC
10 98
10 98
98 10
99 11
12 50
10 11
12 10
10 28
28 27
3 . 714E6
28 . 571E–12
(5,6) 5 . 386E–3
1 . 6
1 . 6
DX
DX
1 . 4E3
12E–12
* MODELS USED
*
. MODEL QN NPN (BF=33.333E3)
. MODEL DX D
. MODEL DY D (BV=50)
. ENDS OP467
Rev. * | Page 17 of 20
OP467
99
99
27
99
99
27
+
–
V1
R4
6
R3
5
D5
RMP1
15
D6
11
G01
I
SY
V3
D1
C
C
R
28
C3
C
–
+
R01
L1
21
D3
D4
2
10
20
15
Q1
N–
N+
Q2
7
26
I
OS
8
9
V4
R10
G2
22
13
14
C
1
R7
–
+
IN
C2
G1
R6
C4
98
R5
R8
4
+
–
E
CM
RMP2
G4
R9
23
24
R02
–
+
+
–
E
REF
98
E
D2
OS
+
–
D7
D8
G5
G02
E
REF
12
I1
+
–
V2
50
50
50
50
Figure 55. SPICE Macro-Model Input and Gain Stage
Figure 54. SPICE Macro-Model Output Stage
Rev. * | Page 18 of 20
OP467
OUTLINE DIMENSIONS
0.775 (19.69)
0.750 (19.05)
0.735 (18.67)
14
1
8
7
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.050 (1.27)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 56. 14-Lead Plastic Dual In-Line Package [PDIP]
(N-14)
P-Suffix
Dimensions shown in inches and (millimeters)
0.098 (2.49) MAX
8
0.005 (0.13) MIN
14
0.310 (7.87)
0.220 (5.59)
1
7
PIN 1
0.100 (2.54) BSC
0.785 (19.94) MAX
0.320 (8.13)
0.290 (7.37)
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
15°
0°
0.070 (1.78)
0.030 (0.76)
0.023 (0.58)
0.014 (0.36)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 57. 14-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-14)
Y-Suffix
Dimensions shown in inches and (millimeters)
Rev. I | Page 19 of 20
OP467
10.50 (0.4134)
10.10 (0.3976)
16
1
9
8
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
0.25 (0.
0098)
1.27 (0.0500)
BSC
45°
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 58. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-16)
S-Suffix
Dimensions shown in millimeters and (inches)
0.200 (5.08)
0.075 (1.91)
REF
REF
0.100 (2.54)
0.064 (1.63)
0.100 (2.54) REF
0.095 (2.41)
0.015 (0.38)
MIN
0.075 (1.90)
3
19
18
20
4
8
0.028 (0.71)
0.022 (0.56)
1
0.358 (9.09)
0.358
0.011 (0.28)
0.007 (0.18)
R TYP
(9.09)
MAX
SQ
BOTTOM
VIEW
0.342 (8.69)
SQ
0.050 (1.27)
BSC
14
0.075 (1.91)
13
9
REF
45° TYP
0.088 (2.24)
0.054 (1.37)
0.055 (1.40)
0.045 (1.14)
0.150 (3.81)
BSC
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 59. 20-Terminal Ceramic Leadless Chip Carrier [LCC]
(E-20-1) RC-Suffix
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model1
OP467GP
OP467GPZ
OP467GS
OP467GS-REEL
OP467GSZ
OP467GSZ-REEL
OP467ARC/883C
OP467AY/883C
OP467GBC
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−55°C to +125°C
−55°C to +125°C
Package Description
14-Lead PDIP
14-Lead PDIP
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
20-Terminal LCC
14-Lead CERDIP
Die
Package Option
N-14
N-14
RW-16
RW-16
RW-16
RW-16
E-20-1
Q-14
1 Z = RoHS Compliant Part.
©1993–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00302-0-4/10(I)
Rev. I | Page 20 of 20
相关型号：
OPZ90GPZ
IC OP-AMP, 675 uV OFFSET-MAX, 0.02 MHz BAND WIDTH, PDIP8, PLASTIC, DIP-8, Operational Amplifier
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